arch/arm64/boot/dts/hisilicon/hip05.dtsi

   1 /**
   2  * dts file for Hisilicon D02 Development Board
   3  *
   4  * Copyright (C) 2014,2015 Hisilicon Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * publishhed by the Free Software Foundation.
   9  *
  10  */
  11
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13
  14 / {
  15         compatible = "hisilicon,hip05-d02";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         psci {
  21                 compatible = "arm,psci-0.2";
  22                 method = "smc";
  23         };
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 cpu-map {
  30                         cluster0 {
  31                                 core0 {
  32                                         cpu = <&cpu0>;
  33                                 };
  34                                 core1 {
  35                                         cpu = <&cpu1>;
  36                                 };
  37                                 core2 {
  38                                         cpu = <&cpu2>;
  39                                 };
  40                                 core3 {
  41                                         cpu = <&cpu3>;
  42                                 };
  43                         };
  44                         cluster1 {
  45                                 core0 {
  46                                         cpu = <&cpu4>;
  47                                 };
  48                                 core1 {
  49                                         cpu = <&cpu5>;
  50                                 };
  51                                 core2 {
  52                                         cpu = <&cpu6>;
  53                                 };
  54                                 core3 {
  55                                         cpu = <&cpu7>;
  56                                 };
  57                         };
  58                         cluster2 {
  59                                 core0 {
  60                                         cpu = <&cpu8>;
  61                                 };
  62                                 core1 {
  63                                         cpu = <&cpu9>;
  64                                 };
  65                                 core2 {
  66                                         cpu = <&cpu10>;
  67                                 };
  68                                 core3 {
  69                                         cpu = <&cpu11>;
  70                                 };
  71                         };
  72                         cluster3 {
  73                                 core0 {
  74                                         cpu = <&cpu12>;
  75                                 };
  76                                 core1 {
  77                                         cpu = <&cpu13>;
  78                                 };
  79                                 core2 {
  80                                         cpu = <&cpu14>;
  81                                 };
  82                                 core3 {
  83                                         cpu = <&cpu15>;
  84                                 };
  85                         };
  86                 };
  87
  88                 cpu0: cpu@20000 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a57", "arm,armv8";
  91                         reg = <0x20000>;
  92                         enable-method = "psci";
  93                 };
  94
  95                 cpu1: cpu@20001 {
  96                         device_type = "cpu";
  97                         compatible = "arm,cortex-a57", "arm,armv8";
  98                         reg = <0x20001>;
  99                         enable-method = "psci";
 100                 };
 101
 102                 cpu2: cpu@20002 {
 103                         device_type = "cpu";
 104                         compatible = "arm,cortex-a57", "arm,armv8";
 105                         reg = <0x20002>;
 106                         enable-method = "psci";
 107                 };
 108
 109                 cpu3: cpu@20003 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a57", "arm,armv8";
 112                         reg = <0x20003>;
 113                         enable-method = "psci";
 114                 };
 115
 116                 cpu4: cpu@20100 {
 117                         device_type = "cpu";
 118                         compatible = "arm,cortex-a57", "arm,armv8";
 119                         reg = <0x20100>;
 120                         enable-method = "psci";
 121                 };
 122
 123                 cpu5: cpu@20101 {
 124                         device_type = "cpu";
 125                         compatible = "arm,cortex-a57", "arm,armv8";
 126                         reg = <0x20101>;
 127                         enable-method = "psci";
 128                 };
 129
 130                 cpu6: cpu@20102 {
 131                         device_type = "cpu";
 132                         compatible = "arm,cortex-a57", "arm,armv8";
 133                         reg = <0x20102>;
 134                         enable-method = "psci";
 135                 };
 136
 137                 cpu7: cpu@20103 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a57", "arm,armv8";
 140                         reg = <0x20103>;
 141                         enable-method = "psci";
 142                 };
 143
 144                 cpu8: cpu@20200 {
 145                         device_type = "cpu";
 146                         compatible = "arm,cortex-a57", "arm,armv8";
 147                         reg = <0x20200>;
 148                         enable-method = "psci";
 149                 };
 150
 151                 cpu9: cpu@20201 {
 152                         device_type = "cpu";
 153                         compatible = "arm,cortex-a57", "arm,armv8";
 154                         reg = <0x20201>;
 155                         enable-method = "psci";
 156                 };
 157
 158                 cpu10: cpu@20202 {
 159                         device_type = "cpu";
 160                         compatible = "arm,cortex-a57", "arm,armv8";
 161                         reg = <0x20202>;
 162                         enable-method = "psci";
 163                 };
 164
 165                 cpu11: cpu@20203 {
 166                         device_type = "cpu";
 167                         compatible = "arm,cortex-a57", "arm,armv8";
 168                         reg = <0x20203>;
 169                         enable-method = "psci";
 170                 };
 171
 172                 cpu12: cpu@20300 {
 173                         device_type = "cpu";
 174                         compatible = "arm,cortex-a57", "arm,armv8";
 175                         reg = <0x20300>;
 176                         enable-method = "psci";
 177                 };
 178
 179                 cpu13: cpu@20301 {
 180                         device_type = "cpu";
 181                         compatible = "arm,cortex-a57", "arm,armv8";
 182                         reg = <0x20301>;
 183                         enable-method = "psci";
 184                 };
 185
 186                 cpu14: cpu@20302 {
 187                         device_type = "cpu";
 188                         compatible = "arm,cortex-a57", "arm,armv8";
 189                         reg = <0x20302>;
 190                         enable-method = "psci";
 191                 };
 192
 193                 cpu15: cpu@20303 {
 194                         device_type = "cpu";
 195                         compatible = "arm,cortex-a57", "arm,armv8";
 196                         reg = <0x20303>;
 197                         enable-method = "psci";
 198                 };
 199         };
 200
 201         gic: interrupt-controller@8d000000 {
 202                 compatible = "arm,gic-v3";
 203                 #interrupt-cells = <3>;
 204                 #address-cells = <2>;
 205                 #size-cells = <2>;
 206                 ranges;
 207                 interrupt-controller;
 208                 #redistributor-regions = <1>;
 209                 redistributor-stride = <0x0 0x30000>;
 210                 reg = <0x0 0x8d000000 0 0x10000>,       /* GICD */
 211                       <0x0 0x8d100000 0 0x300000>,      /* GICR */
 212                       <0x0 0xfe000000 0 0x10000>,       /* GICC */
 213                       <0x0 0xfe010000 0 0x10000>,       /* GICH */
 214                       <0x0 0xfe020000 0 0x10000>;       /* GICV */
 215                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 216
 217                 its_totems: interrupt-controller@8c000000 {
 218                         compatible = "arm,gic-v3-its";
 219                         msi-controller;
 220                         reg = <0x0 0x8c000000 0x0 0x40000>;
 221                 };
 222         };
 223
 224         timer {
 225                 compatible = "arm,armv8-timer";
 226                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 227                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 228                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 229                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 230         };
 231
 232         pmu {
 233                 compatible = "arm,armv8-pmuv3";
 234                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 235         };
 236
 237         soc {
 238                 compatible = "simple-bus";
 239                 #address-cells = <2>;
 240                 #size-cells = <2>;
 241                 ranges;
 242
 243                 refclk200mhz: refclk200mhz {
 244                         compatible = "fixed-clock";
 245                         #clock-cells = <0>;
 246                         clock-frequency = <200000000>;
 247                 };
 248
 249                 uart0: uart@80300000 {
 250                         compatible = "snps,dw-apb-uart";
 251                         reg = <0x0 0x80300000 0x0 0x10000>;
 252                         interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
 253                         clocks = <&refclk200mhz>;
 254                         clock-names = "apb_pclk";
 255                         reg-shift = <2>;
 256                         reg-io-width = <4>;
 257                         status = "disabled";
 258                 };
 259
 260                 uart1: uart@80310000 {
 261                         compatible = "snps,dw-apb-uart";
 262                         reg = <0x0 0x80310000 0x0 0x10000>;
 263                         interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 264                         clocks = <&refclk200mhz>;
 265                         clock-names = "apb_pclk";
 266                         reg-shift = <2>;
 267                         reg-io-width = <4>;
 268                         status = "disabled";
 269                 };
 270         };
 271 };