arch/arm64/boot/dts/qcom/msm8916.dtsi

   1 /*
   2  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
  16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
  17
  18 / {
  19         model = "Qualcomm Technologies, Inc. MSM8916";
  20         compatible = "qcom,msm8916";
  21
  22         interrupt-parent = <&intc>;
  23
  24         #address-cells = <2>;
  25         #size-cells = <2>;
  26
  27         aliases {
  28                 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  29                 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
  30         };
  31
  32         chosen { };
  33
  34         memory {
  35                 device_type = "memory";
  36                 /* We expect the bootloader to fill in the reg */
  37                 reg = <0 0 0 0>;
  38         };
  39
  40         cpus {
  41                 #address-cells = <1>;
  42                 #size-cells = <0>;
  43
  44                 CPU0: cpu@0 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a53", "arm,armv8";
  47                         reg = <0x0>;
  48                 };
  49
  50                 CPU1: cpu@1 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a53", "arm,armv8";
  53                         reg = <0x1>;
  54                 };
  55
  56                 CPU2: cpu@2 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a53", "arm,armv8";
  59                         reg = <0x2>;
  60                 };
  61
  62                 CPU3: cpu@3 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a53", "arm,armv8";
  65                         reg = <0x3>;
  66                 };
  67         };
  68
  69         timer {
  70                 compatible = "arm,armv8-timer";
  71                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  72                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  73                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  74                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  75         };
  76
  77         soc: soc {
  78                 #address-cells = <1>;
  79                 #size-cells = <1>;
  80                 ranges = <0 0 0 0xffffffff>;
  81                 compatible = "simple-bus";
  82
  83                 restart@4ab000 {
  84                         compatible = "qcom,pshold";
  85                         reg = <0x4ab000 0x4>;
  86                 };
  87
  88                 msmgpio: pinctrl@1000000 {
  89                         compatible = "qcom,msm8916-pinctrl";
  90                         reg = <0x1000000 0x300000>;
  91                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
  92                         gpio-controller;
  93                         #gpio-cells = <2>;
  94                         interrupt-controller;
  95                         #interrupt-cells = <2>;
  96                 };
  97
  98                 gcc: qcom,gcc@1800000 {
  99                         compatible = "qcom,gcc-msm8916";
 100                         #clock-cells = <1>;
 101                         #reset-cells = <1>;
 102                         reg = <0x1800000 0x80000>;
 103                 };
 104
 105                 blsp1_uart2: serial@78b0000 {
 106                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 107                         reg = <0x78b0000 0x200>;
 108                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 109                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 110                         clock-names = "core", "iface";
 111                         status = "disabled";
 112                 };
 113
 114                 blsp_dma: dma@7884000 {
 115                         compatible = "qcom,bam-v1.7.0";
 116                         reg = <0x07884000 0x23000>;
 117                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 118                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 119                         clock-names = "bam_clk";
 120                         #dma-cells = <1>;
 121                         qcom,ee = <0>;
 122                         status = "disabled";
 123                 };
 124
 125                 blsp_spi1: spi@78b5000 {
 126                         compatible = "qcom,spi-qup-v2.2.1";
 127                         reg = <0x078b5000 0x600>;
 128                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 129                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 130                                  <&gcc GCC_BLSP1_AHB_CLK>;
 131                         clock-names = "core", "iface";
 132                         dmas = <&blsp_dma 5>, <&blsp_dma 4>;
 133                         dma-names = "rx", "tx";
 134                         pinctrl-names = "default", "sleep";
 135                         pinctrl-0 = <&spi1_default>;
 136                         pinctrl-1 = <&spi1_sleep>;
 137                         #address-cells = <1>;
 138                         #size-cells = <0>;
 139                         status = "disabled";
 140                 };
 141
 142                 blsp_spi2: spi@78b6000 {
 143                         compatible = "qcom,spi-qup-v2.2.1";
 144                         reg = <0x078b6000 0x600>;
 145                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 146                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 147                                  <&gcc GCC_BLSP1_AHB_CLK>;
 148                         clock-names = "core", "iface";
 149                         dmas = <&blsp_dma 7>, <&blsp_dma 6>;
 150                         dma-names = "rx", "tx";
 151                         pinctrl-names = "default", "sleep";
 152                         pinctrl-0 = <&spi2_default>;
 153                         pinctrl-1 = <&spi2_sleep>;
 154                         #address-cells = <1>;
 155                         #size-cells = <0>;
 156                         status = "disabled";
 157                 };
 158
 159                 blsp_spi3: spi@78b7000 {
 160                         compatible = "qcom,spi-qup-v2.2.1";
 161                         reg = <0x078b7000 0x600>;
 162                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 163                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
 164                                  <&gcc GCC_BLSP1_AHB_CLK>;
 165                         clock-names = "core", "iface";
 166                         dmas = <&blsp_dma 9>, <&blsp_dma 8>;
 167                         dma-names = "rx", "tx";
 168                         pinctrl-names = "default", "sleep";
 169                         pinctrl-0 = <&spi3_default>;
 170                         pinctrl-1 = <&spi3_sleep>;
 171                         #address-cells = <1>;
 172                         #size-cells = <0>;
 173                         status = "disabled";
 174                 };
 175
 176                 blsp_spi4: spi@78b8000 {
 177                         compatible = "qcom,spi-qup-v2.2.1";
 178                         reg = <0x078b8000 0x600>;
 179                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 180                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
 181                                  <&gcc GCC_BLSP1_AHB_CLK>;
 182                         clock-names = "core", "iface";
 183                         dmas = <&blsp_dma 11>, <&blsp_dma 10>;
 184                         dma-names = "rx", "tx";
 185                         pinctrl-names = "default", "sleep";
 186                         pinctrl-0 = <&spi4_default>;
 187                         pinctrl-1 = <&spi4_sleep>;
 188                         #address-cells = <1>;
 189                         #size-cells = <0>;
 190                         status = "disabled";
 191                 };
 192
 193                 blsp_spi5: spi@78b9000 {
 194                         compatible = "qcom,spi-qup-v2.2.1";
 195                         reg = <0x078b9000 0x600>;
 196                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 197                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
 198                                  <&gcc GCC_BLSP1_AHB_CLK>;
 199                         clock-names = "core", "iface";
 200                         dmas = <&blsp_dma 13>, <&blsp_dma 12>;
 201                         dma-names = "rx", "tx";
 202                         pinctrl-names = "default", "sleep";
 203                         pinctrl-0 = <&spi5_default>;
 204                         pinctrl-1 = <&spi5_sleep>;
 205                         #address-cells = <1>;
 206                         #size-cells = <0>;
 207                         status = "disabled";
 208                 };
 209
 210                 blsp_spi6: spi@78ba000 {
 211                         compatible = "qcom,spi-qup-v2.2.1";
 212                         reg = <0x078ba000 0x600>;
 213                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 214                         clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
 215                                  <&gcc GCC_BLSP1_AHB_CLK>;
 216                         clock-names = "core", "iface";
 217                         dmas = <&blsp_dma 15>, <&blsp_dma 14>;
 218                         dma-names = "rx", "tx";
 219                         pinctrl-names = "default", "sleep";
 220                         pinctrl-0 = <&spi6_default>;
 221                         pinctrl-1 = <&spi6_sleep>;
 222                         #address-cells = <1>;
 223                         #size-cells = <0>;
 224                         status = "disabled";
 225                 };
 226
 227                 blsp_i2c4: i2c@78b8000 {
 228                         compatible = "qcom,i2c-qup-v2.2.1";
 229                         reg = <0x78b8000 0x1000>;
 230                         interrupts = <GIC_SPI 98 0>;
 231                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 232                                 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
 233                         clock-names = "iface", "core";
 234                         pinctrl-names = "default", "sleep";
 235                         pinctrl-0 = <&i2c4_default>;
 236                         pinctrl-1 = <&i2c4_sleep>;
 237                         #address-cells = <1>;
 238                         #size-cells = <0>;
 239                         status = "disabled";
 240                 };
 241
 242                 sdhc_1: sdhci@07824000 {
 243                         compatible = "qcom,sdhci-msm-v4";
 244                         reg = <0x07824900 0x11c>, <0x07824000 0x800>;
 245                         reg-names = "hc_mem", "core_mem";
 246
 247                         interrupts = <0 123 0>, <0 138 0>;
 248                         interrupt-names = "hc_irq", "pwr_irq";
 249                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 250                                  <&gcc GCC_SDCC1_AHB_CLK>;
 251                         clock-names = "core", "iface";
 252                         bus-width = <8>;
 253                         non-removable;
 254                         status = "disabled";
 255                 };
 256
 257                 sdhc_2: sdhci@07864000 {
 258                         compatible = "qcom,sdhci-msm-v4";
 259                         reg = <0x07864900 0x11c>, <0x07864000 0x800>;
 260                         reg-names = "hc_mem", "core_mem";
 261
 262                         interrupts = <0 125 0>, <0 221 0>;
 263                         interrupt-names = "hc_irq", "pwr_irq";
 264                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
 265                                  <&gcc GCC_SDCC2_AHB_CLK>;
 266                         clock-names = "core", "iface";
 267                         bus-width = <4>;
 268                         status = "disabled";
 269                 };
 270
 271                 usb_dev: usb@78d9000 {
 272                         compatible = "qcom,ci-hdrc";
 273                         reg = <0x78d9000 0x400>;
 274                         dr_mode = "peripheral";
 275                         interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
 276                         usb-phy = <&usb_otg>;
 277                         status = "disabled";
 278                 };
 279
 280                 usb_host: ehci@78d9000 {
 281                         compatible = "qcom,ehci-host";
 282                         reg = <0x78d9000 0x400>;
 283                         interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
 284                         usb-phy = <&usb_otg>;
 285                         status = "disabled";
 286                 };
 287
 288                 usb_otg: phy@78d9000 {
 289                         compatible = "qcom,usb-otg-snps";
 290                         reg = <0x78d9000 0x400>;
 291                         interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>,
 292                                      <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
 293
 294                         qcom,vdd-levels = <1 5 7>;
 295                         qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
 296                         dr_mode = "peripheral";
 297                         qcom,otg-control = <2>; // PMIC
 298
 299                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
 300                                  <&gcc GCC_USB_HS_SYSTEM_CLK>,
 301                                  <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 302                         clock-names = "iface", "core", "sleep";
 303
 304                         resets = <&gcc GCC_USB2A_PHY_BCR>,
 305                                  <&gcc GCC_USB_HS_BCR>;
 306                         reset-names = "phy", "link";
 307                         status = "disabled";
 308                 };
 309
 310                 intc: interrupt-controller@b000000 {
 311                         compatible = "qcom,msm-qgic2";
 312                         interrupt-controller;
 313                         #interrupt-cells = <3>;
 314                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 315                 };
 316
 317                 timer@b020000 {
 318                         #address-cells = <1>;
 319                         #size-cells = <1>;
 320                         ranges;
 321                         compatible = "arm,armv7-timer-mem";
 322                         reg = <0xb020000 0x1000>;
 323                         clock-frequency = <19200000>;
 324
 325                         frame@b021000 {
 326                                 frame-number = <0>;
 327                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 328                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 329                                 reg = <0xb021000 0x1000>,
 330                                       <0xb022000 0x1000>;
 331                         };
 332
 333                         frame@b023000 {
 334                                 frame-number = <1>;
 335                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 336                                 reg = <0xb023000 0x1000>;
 337                                 status = "disabled";
 338                         };
 339
 340                         frame@b024000 {
 341                                 frame-number = <2>;
 342                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 343                                 reg = <0xb024000 0x1000>;
 344                                 status = "disabled";
 345                         };
 346
 347                         frame@b025000 {
 348                                 frame-number = <3>;
 349                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 350                                 reg = <0xb025000 0x1000>;
 351                                 status = "disabled";
 352                         };
 353
 354                         frame@b026000 {
 355                                 frame-number = <4>;
 356                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 357                                 reg = <0xb026000 0x1000>;
 358                                 status = "disabled";
 359                         };
 360
 361                         frame@b027000 {
 362                                 frame-number = <5>;
 363                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 364                                 reg = <0xb027000 0x1000>;
 365                                 status = "disabled";
 366                         };
 367
 368                         frame@b028000 {
 369                                 frame-number = <6>;
 370                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 371                                 reg = <0xb028000 0x1000>;
 372                                 status = "disabled";
 373                         };
 374                 };
 375
 376                 spmi_bus: spmi@200f000 {
 377                         compatible = "qcom,spmi-pmic-arb";
 378                         reg = <0x200f000 0x001000>,
 379                               <0x2400000 0x400000>,
 380                               <0x2c00000 0x400000>,
 381                               <0x3800000 0x200000>,
 382                               <0x200a000 0x002100>;
 383                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 384                         interrupt-names = "periph_irq";
 385                         interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
 386                         qcom,ee = <0>;
 387                         qcom,channel = <0>;
 388                         #address-cells = <2>;
 389                         #size-cells = <0>;
 390                         interrupt-controller;
 391                         #interrupt-cells = <4>;
 392                 };
 393         };
 394 };
 395
 396 #include "msm8916-pins.dtsi"