arch/mips/kernel/mips-r2-to-r6-emul.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (c) 2014 Imagination Technologies Ltd.
   7  * Author: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
   8  * Author: Markos Chandras <markos.chandras@imgtec.com>
   9  *
  10  *      MIPS R2 user space instruction emulator for MIPS R6
  11  *
  12  */
  13 #include <linux/bug.h>
  14 #include <linux/compiler.h>
  15 #include <linux/debugfs.h>
  16 #include <linux/init.h>
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/ptrace.h>
  20 #include <linux/seq_file.h>
  21
  22 #include <asm/asm.h>
  23 #include <asm/branch.h>
  24 #include <asm/break.h>
  25 #include <asm/debug.h>
  26 #include <asm/fpu.h>
  27 #include <asm/fpu_emulator.h>
  28 #include <asm/inst.h>
  29 #include <asm/mips-r2-to-r6-emul.h>
  30 #include <asm/local.h>
  31 #include <asm/ptrace.h>
  32 #include <asm/uaccess.h>
  33
  34 #ifdef CONFIG_64BIT
  35 #define ADDIU   "daddiu "
  36 #define INS     "dins "
  37 #define EXT     "dext "
  38 #else
  39 #define ADDIU   "addiu "
  40 #define INS     "ins "
  41 #define EXT     "ext "
  42 #endif /* CONFIG_64BIT */
  43
  44 #define SB      "sb "
  45 #define LB      "lb "
  46 #define LL      "ll "
  47 #define SC      "sc "
  48
  49 DEFINE_PER_CPU(struct mips_r2_emulator_stats, mipsr2emustats);
  50 DEFINE_PER_CPU(struct mips_r2_emulator_stats, mipsr2bdemustats);
  51 DEFINE_PER_CPU(struct mips_r2br_emulator_stats, mipsr2bremustats);
  52
  53 extern const unsigned int fpucondbit[8];
  54
  55 #define MIPS_R2_EMUL_TOTAL_PASS 10
  56
  57 int mipsr2_emulation = 0;
  58
  59 static int __init mipsr2emu_enable(char *s)
  60 {
  61         mipsr2_emulation = 1;
  62
  63         pr_info("MIPS R2-to-R6 Emulator Enabled!");
  64
  65         return 1;
  66 }
  67 __setup("mipsr2emu", mipsr2emu_enable);
  68
  69 /**
  70  * mipsr6_emul - Emulate some frequent R2/R5/R6 instructions in delay slot
  71  * for performance instead of the traditional way of using a stack trampoline
  72  * which is rather slow.
  73  * @regs: Process register set
  74  * @ir: Instruction
  75  */
  76 static inline int mipsr6_emul(struct pt_regs *regs, u32 ir)
  77 {
  78         switch (MIPSInst_OPCODE(ir)) {
  79         case addiu_op:
  80                 if (MIPSInst_RT(ir))
  81                         regs->regs[MIPSInst_RT(ir)] =
  82                                 (s32)regs->regs[MIPSInst_RS(ir)] +
  83                                 (s32)MIPSInst_SIMM(ir);
  84                 return 0;
  85         case daddiu_op:
  86                 if (config_enabled(CONFIG_32BIT))
  87                         break;
  88
  89                 if (MIPSInst_RT(ir))
  90                         regs->regs[MIPSInst_RT(ir)] =
  91                                 (s64)regs->regs[MIPSInst_RS(ir)] +
  92                                 (s64)MIPSInst_SIMM(ir);
  93                 return 0;
  94         case lwc1_op:
  95         case swc1_op:
  96         case cop1_op:
  97         case cop1x_op:
  98                 /* FPU instructions in delay slot */
  99                 return -SIGFPE;
 100         case spec_op:
 101                 switch (MIPSInst_FUNC(ir)) {
 102                 case or_op:
 103                         if (MIPSInst_RD(ir))
 104                                 regs->regs[MIPSInst_RD(ir)] =
 105                                         regs->regs[MIPSInst_RS(ir)] |
 106                                         regs->regs[MIPSInst_RT(ir)];
 107                         return 0;
 108                 case sll_op:
 109                         if (MIPSInst_RS(ir))
 110                                 break;
 111
 112                         if (MIPSInst_RD(ir))
 113                                 regs->regs[MIPSInst_RD(ir)] =
 114                                         (s32)(((u32)regs->regs[MIPSInst_RT(ir)]) <<
 115                                                 MIPSInst_FD(ir));
 116                         return 0;
 117                 case srl_op:
 118                         if (MIPSInst_RS(ir))
 119                                 break;
 120
 121                         if (MIPSInst_RD(ir))
 122                                 regs->regs[MIPSInst_RD(ir)] =
 123                                         (s32)(((u32)regs->regs[MIPSInst_RT(ir)]) >>
 124                                                 MIPSInst_FD(ir));
 125                         return 0;
 126                 case addu_op:
 127                         if (MIPSInst_FD(ir))
 128                                 break;
 129
 130                         if (MIPSInst_RD(ir))
 131                                 regs->regs[MIPSInst_RD(ir)] =
 132                                         (s32)((u32)regs->regs[MIPSInst_RS(ir)] +
 133                                               (u32)regs->regs[MIPSInst_RT(ir)]);
 134                         return 0;
 135                 case subu_op:
 136                         if (MIPSInst_FD(ir))
 137                                 break;
 138
 139                         if (MIPSInst_RD(ir))
 140                                 regs->regs[MIPSInst_RD(ir)] =
 141                                         (s32)((u32)regs->regs[MIPSInst_RS(ir)] -
 142                                               (u32)regs->regs[MIPSInst_RT(ir)]);
 143                         return 0;
 144                 case dsll_op:
 145                         if (config_enabled(CONFIG_32BIT) || MIPSInst_RS(ir))
 146                                 break;
 147
 148                         if (MIPSInst_RD(ir))
 149                                 regs->regs[MIPSInst_RD(ir)] =
 150                                         (s64)(((u64)regs->regs[MIPSInst_RT(ir)]) <<
 151                                                 MIPSInst_FD(ir));
 152                         return 0;
 153                 case dsrl_op:
 154                         if (config_enabled(CONFIG_32BIT) || MIPSInst_RS(ir))
 155                                 break;
 156
 157                         if (MIPSInst_RD(ir))
 158                                 regs->regs[MIPSInst_RD(ir)] =
 159                                         (s64)(((u64)regs->regs[MIPSInst_RT(ir)]) >>
 160                                                 MIPSInst_FD(ir));
 161                         return 0;
 162                 case daddu_op:
 163                         if (config_enabled(CONFIG_32BIT) || MIPSInst_FD(ir))
 164                                 break;
 165
 166                         if (MIPSInst_RD(ir))
 167                                 regs->regs[MIPSInst_RD(ir)] =
 168                                         (u64)regs->regs[MIPSInst_RS(ir)] +
 169                                         (u64)regs->regs[MIPSInst_RT(ir)];
 170                         return 0;
 171                 case dsubu_op:
 172                         if (config_enabled(CONFIG_32BIT) || MIPSInst_FD(ir))
 173                                 break;
 174
 175                         if (MIPSInst_RD(ir))
 176                                 regs->regs[MIPSInst_RD(ir)] =
 177                                         (s64)((u64)regs->regs[MIPSInst_RS(ir)] -
 178                                               (u64)regs->regs[MIPSInst_RT(ir)]);
 179                         return 0;
 180                 }
 181                 break;
 182         default:
 183                 pr_debug("No fastpath BD emulation for instruction 0x%08x (op: %02x)\n",
 184                          ir, MIPSInst_OPCODE(ir));
 185         }
 186
 187         return SIGILL;
 188 }
 189
 190 /**
 191  * movf_func - Emulate a MOVF instruction
 192  * @regs: Process register set
 193  * @ir: Instruction
 194  *
 195  * Returns 0 since it always succeeds.
 196  */
 197 static int movf_func(struct pt_regs *regs, u32 ir)
 198 {
 199         u32 csr;
 200         u32 cond;
 201
 202         csr = current->thread.fpu.fcr31;
 203         cond = fpucondbit[MIPSInst_RT(ir) >> 2];
 204
 205         if (((csr & cond) == 0) && MIPSInst_RD(ir))
 206                 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
 207
 208         MIPS_R2_STATS(movs);
 209
 210         return 0;
 211 }
 212
 213 /**
 214  * movt_func - Emulate a MOVT instruction
 215  * @regs: Process register set
 216  * @ir: Instruction
 217  *
 218  * Returns 0 since it always succeeds.
 219  */
 220 static int movt_func(struct pt_regs *regs, u32 ir)
 221 {
 222         u32 csr;
 223         u32 cond;
 224
 225         csr = current->thread.fpu.fcr31;
 226         cond = fpucondbit[MIPSInst_RT(ir) >> 2];
 227
 228         if (((csr & cond) != 0) && MIPSInst_RD(ir))
 229                 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
 230
 231         MIPS_R2_STATS(movs);
 232
 233         return 0;
 234 }
 235
 236 /**
 237  * jr_func - Emulate a JR instruction.
 238  * @pt_regs: Process register set
 239  * @ir: Instruction
 240  *
 241  * Returns SIGILL if JR was in delay slot, SIGEMT if we
 242  * can't compute the EPC, SIGSEGV if we can't access the
 243  * userland instruction or 0 on success.
 244  */
 245 static int jr_func(struct pt_regs *regs, u32 ir)
 246 {
 247         int err;
 248         unsigned long cepc, epc, nepc;
 249         u32 nir;
 250
 251         if (delay_slot(regs))
 252                 return SIGILL;
 253
 254         /* EPC after the RI/JR instruction */
 255         nepc = regs->cp0_epc;
 256         /* Roll back to the reserved R2 JR instruction */
 257         regs->cp0_epc -= 4;
 258         epc = regs->cp0_epc;
 259         err = __compute_return_epc(regs);
 260
 261         if (err < 0)
 262                 return SIGEMT;
 263
 264
 265         /* Computed EPC */
 266         cepc = regs->cp0_epc;
 267
 268         /* Get DS instruction */
 269         err = __get_user(nir, (u32 __user *)nepc);
 270         if (err)
 271                 return SIGSEGV;
 272
 273         MIPS_R2BR_STATS(jrs);
 274
 275         /* If nir == 0(NOP), then nothing else to do */
 276         if (nir) {
 277                 /*
 278                  * Negative err means FPU instruction in BD-slot,
 279                  * Zero err means 'BD-slot emulation done'
 280                  * For anything else we go back to trampoline emulation.
 281                  */
 282                 err = mipsr6_emul(regs, nir);
 283                 if (err > 0) {
 284                         regs->cp0_epc = nepc;
 285                         err = mips_dsemul(regs, nir, cepc);
 286                         if (err == SIGILL)
 287                                 err = SIGEMT;
 288                         MIPS_R2_STATS(dsemul);
 289                 }
 290         }
 291
 292         return err;
 293 }
 294
 295 /**
 296  * movz_func - Emulate a MOVZ instruction
 297  * @regs: Process register set
 298  * @ir: Instruction
 299  *
 300  * Returns 0 since it always succeeds.
 301  */
 302 static int movz_func(struct pt_regs *regs, u32 ir)
 303 {
 304         if (((regs->regs[MIPSInst_RT(ir)]) == 0) && MIPSInst_RD(ir))
 305                 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
 306         MIPS_R2_STATS(movs);
 307
 308         return 0;
 309 }
 310
 311 /**
 312  * movn_func - Emulate a MOVZ instruction
 313  * @regs: Process register set
 314  * @ir: Instruction
 315  *
 316  * Returns 0 since it always succeeds.
 317  */
 318 static int movn_func(struct pt_regs *regs, u32 ir)
 319 {
 320         if (((regs->regs[MIPSInst_RT(ir)]) != 0) && MIPSInst_RD(ir))
 321                 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
 322         MIPS_R2_STATS(movs);
 323
 324         return 0;
 325 }
 326
 327 /**
 328  * mfhi_func - Emulate a MFHI instruction
 329  * @regs: Process register set
 330  * @ir: Instruction
 331  *
 332  * Returns 0 since it always succeeds.
 333  */
 334 static int mfhi_func(struct pt_regs *regs, u32 ir)
 335 {
 336         if (MIPSInst_RD(ir))
 337                 regs->regs[MIPSInst_RD(ir)] = regs->hi;
 338
 339         MIPS_R2_STATS(hilo);
 340
 341         return 0;
 342 }
 343
 344 /**
 345  * mthi_func - Emulate a MTHI instruction
 346  * @regs: Process register set
 347  * @ir: Instruction
 348  *
 349  * Returns 0 since it always succeeds.
 350  */
 351 static int mthi_func(struct pt_regs *regs, u32 ir)
 352 {
 353         regs->hi = regs->regs[MIPSInst_RS(ir)];
 354
 355         MIPS_R2_STATS(hilo);
 356
 357         return 0;
 358 }
 359
 360 /**
 361  * mflo_func - Emulate a MFLO instruction
 362  * @regs: Process register set
 363  * @ir: Instruction
 364  *
 365  * Returns 0 since it always succeeds.
 366  */
 367 static int mflo_func(struct pt_regs *regs, u32 ir)
 368 {
 369         if (MIPSInst_RD(ir))
 370                 regs->regs[MIPSInst_RD(ir)] = regs->lo;
 371
 372         MIPS_R2_STATS(hilo);
 373
 374         return 0;
 375 }
 376
 377 /**
 378  * mtlo_func - Emulate a MTLO instruction
 379  * @regs: Process register set
 380  * @ir: Instruction
 381  *
 382  * Returns 0 since it always succeeds.
 383  */
 384 static int mtlo_func(struct pt_regs *regs, u32 ir)
 385 {
 386         regs->lo = regs->regs[MIPSInst_RS(ir)];
 387
 388         MIPS_R2_STATS(hilo);
 389
 390         return 0;
 391 }
 392
 393 /**
 394  * mult_func - Emulate a MULT instruction
 395  * @regs: Process register set
 396  * @ir: Instruction
 397  *
 398  * Returns 0 since it always succeeds.
 399  */
 400 static int mult_func(struct pt_regs *regs, u32 ir)
 401 {
 402         s64 res;
 403         s32 rt, rs;
 404
 405         rt = regs->regs[MIPSInst_RT(ir)];
 406         rs = regs->regs[MIPSInst_RS(ir)];
 407         res = (s64)rt * (s64)rs;
 408
 409         rs = res;
 410         regs->lo = (s64)rs;
 411         rt = res >> 32;
 412         res = (s64)rt;
 413         regs->hi = res;
 414
 415         MIPS_R2_STATS(muls);
 416
 417         return 0;
 418 }
 419
 420 /**
 421  * multu_func - Emulate a MULTU instruction
 422  * @regs: Process register set
 423  * @ir: Instruction
 424  *
 425  * Returns 0 since it always succeeds.
 426  */
 427 static int multu_func(struct pt_regs *regs, u32 ir)
 428 {
 429         u64 res;
 430         u32 rt, rs;
 431
 432         rt = regs->regs[MIPSInst_RT(ir)];
 433         rs = regs->regs[MIPSInst_RS(ir)];
 434         res = (u64)rt * (u64)rs;
 435         rt = res;
 436         regs->lo = (s64)rt;
 437         regs->hi = (s64)(res >> 32);
 438
 439         MIPS_R2_STATS(muls);
 440
 441         return 0;
 442 }
 443
 444 /**
 445  * div_func - Emulate a DIV instruction
 446  * @regs: Process register set
 447  * @ir: Instruction
 448  *
 449  * Returns 0 since it always succeeds.
 450  */
 451 static int div_func(struct pt_regs *regs, u32 ir)
 452 {
 453         s32 rt, rs;
 454
 455         rt = regs->regs[MIPSInst_RT(ir)];
 456         rs = regs->regs[MIPSInst_RS(ir)];
 457
 458         regs->lo = (s64)(rs / rt);
 459         regs->hi = (s64)(rs % rt);
 460
 461         MIPS_R2_STATS(divs);
 462
 463         return 0;
 464 }
 465
 466 /**
 467  * divu_func - Emulate a DIVU instruction
 468  * @regs: Process register set
 469  * @ir: Instruction
 470  *
 471  * Returns 0 since it always succeeds.
 472  */
 473 static int divu_func(struct pt_regs *regs, u32 ir)
 474 {
 475         u32 rt, rs;
 476
 477         rt = regs->regs[MIPSInst_RT(ir)];
 478         rs = regs->regs[MIPSInst_RS(ir)];
 479
 480         regs->lo = (s64)(rs / rt);
 481         regs->hi = (s64)(rs % rt);
 482
 483         MIPS_R2_STATS(divs);
 484
 485         return 0;
 486 }
 487
 488 /**
 489  * dmult_func - Emulate a DMULT instruction
 490  * @regs: Process register set
 491  * @ir: Instruction
 492  *
 493  * Returns 0 on success or SIGILL for 32-bit kernels.
 494  */
 495 static int dmult_func(struct pt_regs *regs, u32 ir)
 496 {
 497         s64 res;
 498         s64 rt, rs;
 499
 500         if (config_enabled(CONFIG_32BIT))
 501                 return SIGILL;
 502
 503         rt = regs->regs[MIPSInst_RT(ir)];
 504         rs = regs->regs[MIPSInst_RS(ir)];
 505         res = rt * rs;
 506
 507         regs->lo = res;
 508         __asm__ __volatile__(
 509                 "dmuh %0, %1, %2\t\n"
 510                 : "=r"(res)
 511                 : "r"(rt), "r"(rs));
 512
 513         regs->hi = res;
 514
 515         MIPS_R2_STATS(muls);
 516
 517         return 0;
 518 }
 519
 520 /**
 521  * dmultu_func - Emulate a DMULTU instruction
 522  * @regs: Process register set
 523  * @ir: Instruction
 524  *
 525  * Returns 0 on success or SIGILL for 32-bit kernels.
 526  */
 527 static int dmultu_func(struct pt_regs *regs, u32 ir)
 528 {
 529         u64 res;
 530         u64 rt, rs;
 531
 532         if (config_enabled(CONFIG_32BIT))
 533                 return SIGILL;
 534
 535         rt = regs->regs[MIPSInst_RT(ir)];
 536         rs = regs->regs[MIPSInst_RS(ir)];
 537         res = rt * rs;
 538
 539         regs->lo = res;
 540         __asm__ __volatile__(
 541                 "dmuhu %0, %1, %2\t\n"
 542                 : "=r"(res)
 543                 : "r"(rt), "r"(rs));
 544
 545         regs->hi = res;
 546
 547         MIPS_R2_STATS(muls);
 548
 549         return 0;
 550 }
 551
 552 /**
 553  * ddiv_func - Emulate a DDIV instruction
 554  * @regs: Process register set
 555  * @ir: Instruction
 556  *
 557  * Returns 0 on success or SIGILL for 32-bit kernels.
 558  */
 559 static int ddiv_func(struct pt_regs *regs, u32 ir)
 560 {
 561         s64 rt, rs;
 562
 563         if (config_enabled(CONFIG_32BIT))
 564                 return SIGILL;
 565
 566         rt = regs->regs[MIPSInst_RT(ir)];
 567         rs = regs->regs[MIPSInst_RS(ir)];
 568
 569         regs->lo = rs / rt;
 570         regs->hi = rs % rt;
 571
 572         MIPS_R2_STATS(divs);
 573
 574         return 0;
 575 }
 576
 577 /**
 578  * ddivu_func - Emulate a DDIVU instruction
 579  * @regs: Process register set
 580  * @ir: Instruction
 581  *
 582  * Returns 0 on success or SIGILL for 32-bit kernels.
 583  */
 584 static int ddivu_func(struct pt_regs *regs, u32 ir)
 585 {
 586         u64 rt, rs;
 587
 588         if (config_enabled(CONFIG_32BIT))
 589                 return SIGILL;
 590
 591         rt = regs->regs[MIPSInst_RT(ir)];
 592         rs = regs->regs[MIPSInst_RS(ir)];
 593
 594         regs->lo = rs / rt;
 595         regs->hi = rs % rt;
 596
 597         MIPS_R2_STATS(divs);
 598
 599         return 0;
 600 }
 601
 602 /* R6 removed instructions for the SPECIAL opcode */
 603 static struct r2_decoder_table spec_op_table[] = {
 604         { 0xfc1ff83f, 0x00000008, jr_func },
 605         { 0xfc00ffff, 0x00000018, mult_func },
 606         { 0xfc00ffff, 0x00000019, multu_func },
 607         { 0xfc00ffff, 0x0000001c, dmult_func },
 608         { 0xfc00ffff, 0x0000001d, dmultu_func },
 609         { 0xffff07ff, 0x00000010, mfhi_func },
 610         { 0xfc1fffff, 0x00000011, mthi_func },
 611         { 0xffff07ff, 0x00000012, mflo_func },
 612         { 0xfc1fffff, 0x00000013, mtlo_func },
 613         { 0xfc0307ff, 0x00000001, movf_func },
 614         { 0xfc0307ff, 0x00010001, movt_func },
 615         { 0xfc0007ff, 0x0000000a, movz_func },
 616         { 0xfc0007ff, 0x0000000b, movn_func },
 617         { 0xfc00ffff, 0x0000001a, div_func },
 618         { 0xfc00ffff, 0x0000001b, divu_func },
 619         { 0xfc00ffff, 0x0000001e, ddiv_func },
 620         { 0xfc00ffff, 0x0000001f, ddivu_func },
 621         {}
 622 };
 623
 624 /**
 625  * madd_func - Emulate a MADD instruction
 626  * @regs: Process register set
 627  * @ir: Instruction
 628  *
 629  * Returns 0 since it always succeeds.
 630  */
 631 static int madd_func(struct pt_regs *regs, u32 ir)
 632 {
 633         s64 res;
 634         s32 rt, rs;
 635
 636         rt = regs->regs[MIPSInst_RT(ir)];
 637         rs = regs->regs[MIPSInst_RS(ir)];
 638         res = (s64)rt * (s64)rs;
 639         rt = regs->hi;
 640         rs = regs->lo;
 641         res += ((((s64)rt) << 32) | (u32)rs);
 642
 643         rt = res;
 644         regs->lo = (s64)rt;
 645         rs = res >> 32;
 646         regs->hi = (s64)rs;
 647
 648         MIPS_R2_STATS(dsps);
 649
 650         return 0;
 651 }
 652
 653 /**
 654  * maddu_func - Emulate a MADDU instruction
 655  * @regs: Process register set
 656  * @ir: Instruction
 657  *
 658  * Returns 0 since it always succeeds.
 659  */
 660 static int maddu_func(struct pt_regs *regs, u32 ir)
 661 {
 662         u64 res;
 663         u32 rt, rs;
 664
 665         rt = regs->regs[MIPSInst_RT(ir)];
 666         rs = regs->regs[MIPSInst_RS(ir)];
 667         res = (u64)rt * (u64)rs;
 668         rt = regs->hi;
 669         rs = regs->lo;
 670         res += ((((s64)rt) << 32) | (u32)rs);
 671
 672         rt = res;
 673         regs->lo = (s64)rt;
 674         rs = res >> 32;
 675         regs->hi = (s64)rs;
 676
 677         MIPS_R2_STATS(dsps);
 678
 679         return 0;
 680 }
 681
 682 /**
 683  * msub_func - Emulate a MSUB instruction
 684  * @regs: Process register set
 685  * @ir: Instruction
 686  *
 687  * Returns 0 since it always succeeds.
 688  */
 689 static int msub_func(struct pt_regs *regs, u32 ir)
 690 {
 691         s64 res;
 692         s32 rt, rs;
 693
 694         rt = regs->regs[MIPSInst_RT(ir)];
 695         rs = regs->regs[MIPSInst_RS(ir)];
 696         res = (s64)rt * (s64)rs;
 697         rt = regs->hi;
 698         rs = regs->lo;
 699         res = ((((s64)rt) << 32) | (u32)rs) - res;
 700
 701         rt = res;
 702         regs->lo = (s64)rt;
 703         rs = res >> 32;
 704         regs->hi = (s64)rs;
 705
 706         MIPS_R2_STATS(dsps);
 707
 708         return 0;
 709 }
 710
 711 /**
 712  * msubu_func - Emulate a MSUBU instruction
 713  * @regs: Process register set
 714  * @ir: Instruction
 715  *
 716  * Returns 0 since it always succeeds.
 717  */
 718 static int msubu_func(struct pt_regs *regs, u32 ir)
 719 {
 720         u64 res;
 721         u32 rt, rs;
 722
 723         rt = regs->regs[MIPSInst_RT(ir)];
 724         rs = regs->regs[MIPSInst_RS(ir)];
 725         res = (u64)rt * (u64)rs;
 726         rt = regs->hi;
 727         rs = regs->lo;
 728         res = ((((s64)rt) << 32) | (u32)rs) - res;
 729
 730         rt = res;
 731         regs->lo = (s64)rt;
 732         rs = res >> 32;
 733         regs->hi = (s64)rs;
 734
 735         MIPS_R2_STATS(dsps);
 736
 737         return 0;
 738 }
 739
 740 /**
 741  * mul_func - Emulate a MUL instruction
 742  * @regs: Process register set
 743  * @ir: Instruction
 744  *
 745  * Returns 0 since it always succeeds.
 746  */
 747 static int mul_func(struct pt_regs *regs, u32 ir)
 748 {
 749         s64 res;
 750         s32 rt, rs;
 751
 752         if (!MIPSInst_RD(ir))
 753                 return 0;
 754         rt = regs->regs[MIPSInst_RT(ir)];
 755         rs = regs->regs[MIPSInst_RS(ir)];
 756         res = (s64)rt * (s64)rs;
 757
 758         rs = res;
 759         regs->regs[MIPSInst_RD(ir)] = (s64)rs;
 760
 761         MIPS_R2_STATS(muls);
 762
 763         return 0;
 764 }
 765
 766 /**
 767  * clz_func - Emulate a CLZ instruction
 768  * @regs: Process register set
 769  * @ir: Instruction
 770  *
 771  * Returns 0 since it always succeeds.
 772  */
 773 static int clz_func(struct pt_regs *regs, u32 ir)
 774 {
 775         u32 res;
 776         u32 rs;
 777
 778         if (!MIPSInst_RD(ir))
 779                 return 0;
 780
 781         rs = regs->regs[MIPSInst_RS(ir)];
 782         __asm__ __volatile__("clz %0, %1" : "=r"(res) : "r"(rs));
 783         regs->regs[MIPSInst_RD(ir)] = res;
 784
 785         MIPS_R2_STATS(bops);
 786
 787         return 0;
 788 }
 789
 790 /**
 791  * clo_func - Emulate a CLO instruction
 792  * @regs: Process register set
 793  * @ir: Instruction
 794  *
 795  * Returns 0 since it always succeeds.
 796  */
 797
 798 static int clo_func(struct pt_regs *regs, u32 ir)
 799 {
 800         u32 res;
 801         u32 rs;
 802
 803         if (!MIPSInst_RD(ir))
 804                 return 0;
 805
 806         rs = regs->regs[MIPSInst_RS(ir)];
 807         __asm__ __volatile__("clo %0, %1" : "=r"(res) : "r"(rs));
 808         regs->regs[MIPSInst_RD(ir)] = res;
 809
 810         MIPS_R2_STATS(bops);
 811
 812         return 0;
 813 }
 814
 815 /**
 816  * dclz_func - Emulate a DCLZ instruction
 817  * @regs: Process register set
 818  * @ir: Instruction
 819  *
 820  * Returns 0 since it always succeeds.
 821  */
 822 static int dclz_func(struct pt_regs *regs, u32 ir)
 823 {
 824         u64 res;
 825         u64 rs;
 826
 827         if (config_enabled(CONFIG_32BIT))
 828                 return SIGILL;
 829
 830         if (!MIPSInst_RD(ir))
 831                 return 0;
 832
 833         rs = regs->regs[MIPSInst_RS(ir)];
 834         __asm__ __volatile__("dclz %0, %1" : "=r"(res) : "r"(rs));
 835         regs->regs[MIPSInst_RD(ir)] = res;
 836
 837         MIPS_R2_STATS(bops);
 838
 839         return 0;
 840 }
 841
 842 /**
 843  * dclo_func - Emulate a DCLO instruction
 844  * @regs: Process register set
 845  * @ir: Instruction
 846  *
 847  * Returns 0 since it always succeeds.
 848  */
 849 static int dclo_func(struct pt_regs *regs, u32 ir)
 850 {
 851         u64 res;
 852         u64 rs;
 853
 854         if (config_enabled(CONFIG_32BIT))
 855                 return SIGILL;
 856
 857         if (!MIPSInst_RD(ir))
 858                 return 0;
 859
 860         rs = regs->regs[MIPSInst_RS(ir)];
 861         __asm__ __volatile__("dclo %0, %1" : "=r"(res) : "r"(rs));
 862         regs->regs[MIPSInst_RD(ir)] = res;
 863
 864         MIPS_R2_STATS(bops);
 865
 866         return 0;
 867 }
 868
 869 /* R6 removed instructions for the SPECIAL2 opcode */
 870 static struct r2_decoder_table spec2_op_table[] = {
 871         { 0xfc00ffff, 0x70000000, madd_func },
 872         { 0xfc00ffff, 0x70000001, maddu_func },
 873         { 0xfc0007ff, 0x70000002, mul_func },
 874         { 0xfc00ffff, 0x70000004, msub_func },
 875         { 0xfc00ffff, 0x70000005, msubu_func },
 876         { 0xfc0007ff, 0x70000020, clz_func },
 877         { 0xfc0007ff, 0x70000021, clo_func },
 878         { 0xfc0007ff, 0x70000024, dclz_func },
 879         { 0xfc0007ff, 0x70000025, dclo_func },
 880         { }
 881 };
 882
 883 static inline int mipsr2_find_op_func(struct pt_regs *regs, u32 inst,
 884                                       struct r2_decoder_table *table)
 885 {
 886         struct r2_decoder_table *p;
 887         int err;
 888
 889         for (p = table; p->func; p++) {
 890                 if ((inst & p->mask) == p->code) {
 891                         err = (p->func)(regs, inst);
 892                         return err;
 893                 }
 894         }
 895         return SIGILL;
 896 }
 897
 898 /**
 899  * mipsr2_decoder: Decode and emulate a MIPS R2 instruction
 900  * @regs: Process register set
 901  * @inst: Instruction to decode and emulate
 902  * @fcr31: Floating Point Control and Status Register returned
 903  */
 904 int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31)
 905 {
 906         int err = 0;
 907         unsigned long vaddr;
 908         u32 nir;
 909         unsigned long cpc, epc, nepc, r31, res, rs, rt;
 910
 911         void __user *fault_addr = NULL;
 912         int pass = 0;
 913
 914 repeat:
 915         r31 = regs->regs[31];
 916         epc = regs->cp0_epc;
 917         err = compute_return_epc(regs);
 918         if (err < 0) {
 919                 BUG();
 920                 return SIGEMT;
 921         }
 922         pr_debug("Emulating the 0x%08x R2 instruction @ 0x%08lx (pass=%d))\n",
 923                  inst, epc, pass);
 924
 925         switch (MIPSInst_OPCODE(inst)) {
 926         case spec_op:
 927                 err = mipsr2_find_op_func(regs, inst, spec_op_table);
 928                 if (err < 0) {
 929                         /* FPU instruction under JR */
 930                         regs->cp0_cause |= CAUSEF_BD;
 931                         goto fpu_emul;
 932                 }
 933                 break;
 934         case spec2_op:
 935                 err = mipsr2_find_op_func(regs, inst, spec2_op_table);
 936                 break;
 937         case bcond_op:
 938                 rt = MIPSInst_RT(inst);
 939                 rs = MIPSInst_RS(inst);
 940                 switch (rt) {
 941                 case tgei_op:
 942                         if ((long)regs->regs[rs] >= MIPSInst_SIMM(inst))
 943                                 do_trap_or_bp(regs, 0, "TGEI");
 944
 945                         MIPS_R2_STATS(traps);
 946
 947                         break;
 948                 case tgeiu_op:
 949                         if (regs->regs[rs] >= MIPSInst_UIMM(inst))
 950                                 do_trap_or_bp(regs, 0, "TGEIU");
 951
 952                         MIPS_R2_STATS(traps);
 953
 954                         break;
 955                 case tlti_op:
 956                         if ((long)regs->regs[rs] < MIPSInst_SIMM(inst))
 957                                 do_trap_or_bp(regs, 0, "TLTI");
 958
 959                         MIPS_R2_STATS(traps);
 960
 961                         break;
 962                 case tltiu_op:
 963                         if (regs->regs[rs] < MIPSInst_UIMM(inst))
 964                                 do_trap_or_bp(regs, 0, "TLTIU");
 965
 966                         MIPS_R2_STATS(traps);
 967
 968                         break;
 969                 case teqi_op:
 970                         if (regs->regs[rs] == MIPSInst_SIMM(inst))
 971                                 do_trap_or_bp(regs, 0, "TEQI");
 972
 973                         MIPS_R2_STATS(traps);
 974
 975                         break;
 976                 case tnei_op:
 977                         if (regs->regs[rs] != MIPSInst_SIMM(inst))
 978                                 do_trap_or_bp(regs, 0, "TNEI");
 979
 980                         MIPS_R2_STATS(traps);
 981
 982                         break;
 983                 case bltzl_op:
 984                 case bgezl_op:
 985                 case bltzall_op:
 986                 case bgezall_op:
 987                         if (delay_slot(regs)) {
 988                                 err = SIGILL;
 989                                 break;
 990                         }
 991                         regs->regs[31] = r31;
 992                         regs->cp0_epc = epc;
 993                         err = __compute_return_epc(regs);
 994                         if (err < 0)
 995                                 return SIGEMT;
 996                         if (err != BRANCH_LIKELY_TAKEN)
 997                                 break;
 998                         cpc = regs->cp0_epc;
 999                         nepc = epc + 4;
1000                         err = __get_user(nir, (u32 __user *)nepc);
1001                         if (err) {
1002                                 err = SIGSEGV;
1003                                 break;
1004                         }
1005                         /*
1006                          * This will probably be optimized away when
1007                          * CONFIG_DEBUG_FS is not enabled
1008                          */
1009                         switch (rt) {
1010                         case bltzl_op:
1011                                 MIPS_R2BR_STATS(bltzl);
1012                                 break;
1013                         case bgezl_op:
1014                                 MIPS_R2BR_STATS(bgezl);
1015                                 break;
1016                         case bltzall_op:
1017                                 MIPS_R2BR_STATS(bltzall);
1018                                 break;
1019                         case bgezall_op:
1020                                 MIPS_R2BR_STATS(bgezall);
1021                                 break;
1022                         }
1023
1024                         switch (MIPSInst_OPCODE(nir)) {
1025                         case cop1_op:
1026                         case cop1x_op:
1027                         case lwc1_op:
1028                         case swc1_op:
1029                                 regs->cp0_cause |= CAUSEF_BD;
1030                                 goto fpu_emul;
1031                         }
1032                         if (nir) {
1033                                 err = mipsr6_emul(regs, nir);
1034                                 if (err > 0) {
1035                                         err = mips_dsemul(regs, nir, cpc);
1036                                         if (err == SIGILL)
1037                                                 err = SIGEMT;
1038                                         MIPS_R2_STATS(dsemul);
1039                                 }
1040                         }
1041                         break;
1042                 case bltzal_op:
1043                 case bgezal_op:
1044                         if (delay_slot(regs)) {
1045                                 err = SIGILL;
1046                                 break;
1047                         }
1048                         regs->regs[31] = r31;
1049                         regs->cp0_epc = epc;
1050                         err = __compute_return_epc(regs);
1051                         if (err < 0)
1052                                 return SIGEMT;
1053                         cpc = regs->cp0_epc;
1054                         nepc = epc + 4;
1055                         err = __get_user(nir, (u32 __user *)nepc);
1056                         if (err) {
1057                                 err = SIGSEGV;
1058                                 break;
1059                         }
1060                         /*
1061                          * This will probably be optimized away when
1062                          * CONFIG_DEBUG_FS is not enabled
1063                          */
1064                         switch (rt) {
1065                         case bltzal_op:
1066                                 MIPS_R2BR_STATS(bltzal);
1067                                 break;
1068                         case bgezal_op:
1069                                 MIPS_R2BR_STATS(bgezal);
1070                                 break;
1071                         }
1072
1073                         switch (MIPSInst_OPCODE(nir)) {
1074                         case cop1_op:
1075                         case cop1x_op:
1076                         case lwc1_op:
1077                         case swc1_op:
1078                                 regs->cp0_cause |= CAUSEF_BD;
1079                                 goto fpu_emul;
1080                         }
1081                         if (nir) {
1082                                 err = mipsr6_emul(regs, nir);
1083                                 if (err > 0) {
1084                                         err = mips_dsemul(regs, nir, cpc);
1085                                         if (err == SIGILL)
1086                                                 err = SIGEMT;
1087                                         MIPS_R2_STATS(dsemul);
1088                                 }
1089                         }
1090                         break;
1091                 default:
1092                         regs->regs[31] = r31;
1093                         regs->cp0_epc = epc;
1094                         err = SIGILL;
1095                         break;
1096                 }
1097                 break;
1098
1099         case beql_op:
1100         case bnel_op:
1101         case blezl_op:
1102         case bgtzl_op:
1103                 if (delay_slot(regs)) {
1104                         err = SIGILL;
1105                         break;
1106                 }
1107                 regs->regs[31] = r31;
1108                 regs->cp0_epc = epc;
1109                 err = __compute_return_epc(regs);
1110                 if (err < 0)
1111                         return SIGEMT;
1112                 if (err != BRANCH_LIKELY_TAKEN)
1113                         break;
1114                 cpc = regs->cp0_epc;
1115                 nepc = epc + 4;
1116                 err = __get_user(nir, (u32 __user *)nepc);
1117                 if (err) {
1118                         err = SIGSEGV;
1119                         break;
1120                 }
1121                 /*
1122                  * This will probably be optimized away when
1123                  * CONFIG_DEBUG_FS is not enabled
1124                  */
1125                 switch (MIPSInst_OPCODE(inst)) {
1126                 case beql_op:
1127                         MIPS_R2BR_STATS(beql);
1128                         break;
1129                 case bnel_op:
1130                         MIPS_R2BR_STATS(bnel);
1131                         break;
1132                 case blezl_op:
1133                         MIPS_R2BR_STATS(blezl);
1134                         break;
1135                 case bgtzl_op:
1136                         MIPS_R2BR_STATS(bgtzl);
1137                         break;
1138                 }
1139
1140                 switch (MIPSInst_OPCODE(nir)) {
1141                 case cop1_op:
1142                 case cop1x_op:
1143                 case lwc1_op:
1144                 case swc1_op:
1145                         regs->cp0_cause |= CAUSEF_BD;
1146                         goto fpu_emul;
1147                 }
1148                 if (nir) {
1149                         err = mipsr6_emul(regs, nir);
1150                         if (err > 0) {
1151                                 err = mips_dsemul(regs, nir, cpc);
1152                                 if (err == SIGILL)
1153                                         err = SIGEMT;
1154                                 MIPS_R2_STATS(dsemul);
1155                         }
1156                 }
1157                 break;
1158         case lwc1_op:
1159         case swc1_op:
1160         case cop1_op:
1161         case cop1x_op:
1162 fpu_emul:
1163                 regs->regs[31] = r31;
1164                 regs->cp0_epc = epc;
1165                 if (!used_math()) {     /* First time FPU user.  */
1166                         err = init_fpu();
1167                         set_used_math();
1168                 }
1169                 lose_fpu(1);    /* Save FPU state for the emulator. */
1170
1171                 err = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 0,
1172                                                &fault_addr);
1173                 *fcr31 = current->thread.fpu.fcr31;
1174
1175                 /*
1176                  * We can't allow the emulated instruction to leave any of
1177                  * the cause bits set in $fcr31.
1178                  */
1179                 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
1180
1181                 /*
1182                  * this is a tricky issue - lose_fpu() uses LL/SC atomics
1183                  * if FPU is owned and effectively cancels user level LL/SC.
1184                  * So, it could be logical to don't restore FPU ownership here.
1185                  * But the sequence of multiple FPU instructions is much much
1186                  * more often than LL-FPU-SC and I prefer loop here until
1187                  * next scheduler cycle cancels FPU ownership
1188                  */
1189                 own_fpu(1);     /* Restore FPU state. */
1190
1191                 if (err)
1192                         current->thread.cp0_baduaddr = (unsigned long)fault_addr;
1193
1194                 MIPS_R2_STATS(fpus);
1195
1196                 break;
1197
1198         case lwl_op:
1199                 rt = regs->regs[MIPSInst_RT(inst)];
1200                 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1201                 if (!access_ok(VERIFY_READ, vaddr, 4)) {
1202                         current->thread.cp0_baduaddr = vaddr;
1203                         err = SIGSEGV;
1204                         break;
1205                 }
1206                 __asm__ __volatile__(
1207                         "       .set    push\n"
1208                         "       .set    reorder\n"
1209 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1210                         "1:"    LB      "%1, 0(%2)\n"
1211                                 INS     "%0, %1, 24, 8\n"
1212                         "       andi    %1, %2, 0x3\n"
1213                         "       beq     $0, %1, 9f\n"
1214                                 ADDIU   "%2, %2, -1\n"
1215                         "2:"    LB      "%1, 0(%2)\n"
1216                                 INS     "%0, %1, 16, 8\n"
1217                         "       andi    %1, %2, 0x3\n"
1218                         "       beq     $0, %1, 9f\n"
1219                                 ADDIU   "%2, %2, -1\n"
1220                         "3:"    LB      "%1, 0(%2)\n"
1221                                 INS     "%0, %1, 8, 8\n"
1222                         "       andi    %1, %2, 0x3\n"
1223                         "       beq     $0, %1, 9f\n"
1224                                 ADDIU   "%2, %2, -1\n"
1225                         "4:"    LB      "%1, 0(%2)\n"
1226                                 INS     "%0, %1, 0, 8\n"
1227 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1228                         "1:"    LB      "%1, 0(%2)\n"
1229                                 INS     "%0, %1, 24, 8\n"
1230                                 ADDIU   "%2, %2, 1\n"
1231                         "       andi    %1, %2, 0x3\n"
1232                         "       beq     $0, %1, 9f\n"
1233                         "2:"    LB      "%1, 0(%2)\n"
1234                                 INS     "%0, %1, 16, 8\n"
1235                                 ADDIU   "%2, %2, 1\n"
1236                         "       andi    %1, %2, 0x3\n"
1237                         "       beq     $0, %1, 9f\n"
1238                         "3:"    LB      "%1, 0(%2)\n"
1239                                 INS     "%0, %1, 8, 8\n"
1240                                 ADDIU   "%2, %2, 1\n"
1241                         "       andi    %1, %2, 0x3\n"
1242                         "       beq     $0, %1, 9f\n"
1243                         "4:"    LB      "%1, 0(%2)\n"
1244                                 INS     "%0, %1, 0, 8\n"
1245 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1246                         "9:     sll     %0, %0, 0\n"
1247                         "10:\n"
1248                         "       .insn\n"
1249                         "       .section        .fixup,\"ax\"\n"
1250                         "8:     li      %3,%4\n"
1251                         "       j       10b\n"
1252                         "       .previous\n"
1253                         "       .section        __ex_table,\"a\"\n"
1254                         "       .word   1b,8b\n"
1255                         "       .word   2b,8b\n"
1256                         "       .word   3b,8b\n"
1257                         "       .word   4b,8b\n"
1258                         "       .previous\n"
1259                         "       .set    pop\n"
1260                         : "+&r"(rt), "=&r"(rs),
1261                           "+&r"(vaddr), "+&r"(err)
1262                         : "i"(SIGSEGV));
1263
1264                 if (MIPSInst_RT(inst) && !err)
1265                         regs->regs[MIPSInst_RT(inst)] = rt;
1266
1267                 MIPS_R2_STATS(loads);
1268
1269                 break;
1270
1271         case lwr_op:
1272                 rt = regs->regs[MIPSInst_RT(inst)];
1273                 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1274                 if (!access_ok(VERIFY_READ, vaddr, 4)) {
1275                         current->thread.cp0_baduaddr = vaddr;
1276                         err = SIGSEGV;
1277                         break;
1278                 }
1279                 __asm__ __volatile__(
1280                         "       .set    push\n"
1281                         "       .set    reorder\n"
1282 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1283                         "1:"    LB      "%1, 0(%2)\n"
1284                                 INS     "%0, %1, 0, 8\n"
1285                                 ADDIU   "%2, %2, 1\n"
1286                         "       andi    %1, %2, 0x3\n"
1287                         "       beq     $0, %1, 9f\n"
1288                         "2:"    LB      "%1, 0(%2)\n"
1289                                 INS     "%0, %1, 8, 8\n"
1290                                 ADDIU   "%2, %2, 1\n"
1291                         "       andi    %1, %2, 0x3\n"
1292                         "       beq     $0, %1, 9f\n"
1293                         "3:"    LB      "%1, 0(%2)\n"
1294                                 INS     "%0, %1, 16, 8\n"
1295                                 ADDIU   "%2, %2, 1\n"
1296                         "       andi    %1, %2, 0x3\n"
1297                         "       beq     $0, %1, 9f\n"
1298                         "4:"    LB      "%1, 0(%2)\n"
1299                                 INS     "%0, %1, 24, 8\n"
1300                         "       sll     %0, %0, 0\n"
1301 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1302                         "1:"    LB      "%1, 0(%2)\n"
1303                                 INS     "%0, %1, 0, 8\n"
1304                         "       andi    %1, %2, 0x3\n"
1305                         "       beq     $0, %1, 9f\n"
1306                                 ADDIU   "%2, %2, -1\n"
1307                         "2:"    LB      "%1, 0(%2)\n"
1308                                 INS     "%0, %1, 8, 8\n"
1309                         "       andi    %1, %2, 0x3\n"
1310                         "       beq     $0, %1, 9f\n"
1311                                 ADDIU   "%2, %2, -1\n"
1312                         "3:"    LB      "%1, 0(%2)\n"
1313                                 INS     "%0, %1, 16, 8\n"
1314                         "       andi    %1, %2, 0x3\n"
1315                         "       beq     $0, %1, 9f\n"
1316                                 ADDIU   "%2, %2, -1\n"
1317                         "4:"    LB      "%1, 0(%2)\n"
1318                                 INS     "%0, %1, 24, 8\n"
1319                         "       sll     %0, %0, 0\n"
1320 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1321                         "9:\n"
1322                         "10:\n"
1323                         "       .insn\n"
1324                         "       .section        .fixup,\"ax\"\n"
1325                         "8:     li      %3,%4\n"
1326                         "       j       10b\n"
1327                         "       .previous\n"
1328                         "       .section        __ex_table,\"a\"\n"
1329                         "       .word   1b,8b\n"
1330                         "       .word   2b,8b\n"
1331                         "       .word   3b,8b\n"
1332                         "       .word   4b,8b\n"
1333                         "       .previous\n"
1334                         "       .set    pop\n"
1335                         : "+&r"(rt), "=&r"(rs),
1336                           "+&r"(vaddr), "+&r"(err)
1337                         : "i"(SIGSEGV));
1338                 if (MIPSInst_RT(inst) && !err)
1339                         regs->regs[MIPSInst_RT(inst)] = rt;
1340
1341                 MIPS_R2_STATS(loads);
1342
1343                 break;
1344
1345         case swl_op:
1346                 rt = regs->regs[MIPSInst_RT(inst)];
1347                 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1348                 if (!access_ok(VERIFY_WRITE, vaddr, 4)) {
1349                         current->thread.cp0_baduaddr = vaddr;
1350                         err = SIGSEGV;
1351                         break;
1352                 }
1353                 __asm__ __volatile__(
1354                         "       .set    push\n"
1355                         "       .set    reorder\n"
1356 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1357                                 EXT     "%1, %0, 24, 8\n"
1358                         "1:"    SB      "%1, 0(%2)\n"
1359                         "       andi    %1, %2, 0x3\n"
1360                         "       beq     $0, %1, 9f\n"
1361                                 ADDIU   "%2, %2, -1\n"
1362                                 EXT     "%1, %0, 16, 8\n"
1363                         "2:"    SB      "%1, 0(%2)\n"
1364                         "       andi    %1, %2, 0x3\n"
1365                         "       beq     $0, %1, 9f\n"
1366                                 ADDIU   "%2, %2, -1\n"
1367                                 EXT     "%1, %0, 8, 8\n"
1368                         "3:"    SB      "%1, 0(%2)\n"
1369                         "       andi    %1, %2, 0x3\n"
1370                         "       beq     $0, %1, 9f\n"
1371                                 ADDIU   "%2, %2, -1\n"
1372                                 EXT     "%1, %0, 0, 8\n"
1373                         "4:"    SB      "%1, 0(%2)\n"
1374 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1375                                 EXT     "%1, %0, 24, 8\n"
1376                         "1:"    SB      "%1, 0(%2)\n"
1377                                 ADDIU   "%2, %2, 1\n"
1378                         "       andi    %1, %2, 0x3\n"
1379                         "       beq     $0, %1, 9f\n"
1380                                 EXT     "%1, %0, 16, 8\n"
1381                         "2:"    SB      "%1, 0(%2)\n"
1382                                 ADDIU   "%2, %2, 1\n"
1383                         "       andi    %1, %2, 0x3\n"
1384                         "       beq     $0, %1, 9f\n"
1385                                 EXT     "%1, %0, 8, 8\n"
1386                         "3:"    SB      "%1, 0(%2)\n"
1387                                 ADDIU   "%2, %2, 1\n"
1388                         "       andi    %1, %2, 0x3\n"
1389                         "       beq     $0, %1, 9f\n"
1390                                 EXT     "%1, %0, 0, 8\n"
1391                         "4:"    SB      "%1, 0(%2)\n"
1392 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1393                         "9:\n"
1394                         "       .insn\n"
1395                         "       .section        .fixup,\"ax\"\n"
1396                         "8:     li      %3,%4\n"
1397                         "       j       9b\n"
1398                         "       .previous\n"
1399                         "       .section        __ex_table,\"a\"\n"
1400                         "       .word   1b,8b\n"
1401                         "       .word   2b,8b\n"
1402                         "       .word   3b,8b\n"
1403                         "       .word   4b,8b\n"
1404                         "       .previous\n"
1405                         "       .set    pop\n"
1406                         : "+&r"(rt), "=&r"(rs),
1407                           "+&r"(vaddr), "+&r"(err)
1408                         : "i"(SIGSEGV)
1409                         : "memory");
1410
1411                 MIPS_R2_STATS(stores);
1412
1413                 break;
1414
1415         case swr_op:
1416                 rt = regs->regs[MIPSInst_RT(inst)];
1417                 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1418                 if (!access_ok(VERIFY_WRITE, vaddr, 4)) {
1419                         current->thread.cp0_baduaddr = vaddr;
1420                         err = SIGSEGV;
1421                         break;
1422                 }
1423                 __asm__ __volatile__(
1424                         "       .set    push\n"
1425                         "       .set    reorder\n"
1426 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1427                                 EXT     "%1, %0, 0, 8\n"
1428                         "1:"    SB      "%1, 0(%2)\n"
1429                                 ADDIU   "%2, %2, 1\n"
1430                         "       andi    %1, %2, 0x3\n"
1431                         "       beq     $0, %1, 9f\n"
1432                                 EXT     "%1, %0, 8, 8\n"
1433                         "2:"    SB      "%1, 0(%2)\n"
1434                                 ADDIU   "%2, %2, 1\n"
1435                         "       andi    %1, %2, 0x3\n"
1436                         "       beq     $0, %1, 9f\n"
1437                                 EXT     "%1, %0, 16, 8\n"
1438                         "3:"    SB      "%1, 0(%2)\n"
1439                                 ADDIU   "%2, %2, 1\n"
1440                         "       andi    %1, %2, 0x3\n"
1441                         "       beq     $0, %1, 9f\n"
1442                                 EXT     "%1, %0, 24, 8\n"
1443                         "4:"    SB      "%1, 0(%2)\n"
1444 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1445                                 EXT     "%1, %0, 0, 8\n"
1446                         "1:"    SB      "%1, 0(%2)\n"
1447                         "       andi    %1, %2, 0x3\n"
1448                         "       beq     $0, %1, 9f\n"
1449                                 ADDIU   "%2, %2, -1\n"
1450                                 EXT     "%1, %0, 8, 8\n"
1451                         "2:"    SB      "%1, 0(%2)\n"
1452                         "       andi    %1, %2, 0x3\n"
1453                         "       beq     $0, %1, 9f\n"
1454                                 ADDIU   "%2, %2, -1\n"
1455                                 EXT     "%1, %0, 16, 8\n"
1456                         "3:"    SB      "%1, 0(%2)\n"
1457                         "       andi    %1, %2, 0x3\n"
1458                         "       beq     $0, %1, 9f\n"
1459                                 ADDIU   "%2, %2, -1\n"
1460                                 EXT     "%1, %0, 24, 8\n"
1461                         "4:"    SB      "%1, 0(%2)\n"
1462 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1463                         "9:\n"
1464                         "       .insn\n"
1465                         "       .section        .fixup,\"ax\"\n"
1466                         "8:     li      %3,%4\n"
1467                         "       j       9b\n"
1468                         "       .previous\n"
1469                         "       .section        __ex_table,\"a\"\n"
1470                         "       .word   1b,8b\n"
1471                         "       .word   2b,8b\n"
1472                         "       .word   3b,8b\n"
1473                         "       .word   4b,8b\n"
1474                         "       .previous\n"
1475                         "       .set    pop\n"
1476                         : "+&r"(rt), "=&r"(rs),
1477                           "+&r"(vaddr), "+&r"(err)
1478                         : "i"(SIGSEGV)
1479                         : "memory");
1480
1481                 MIPS_R2_STATS(stores);
1482
1483                 break;
1484
1485         case ldl_op:
1486                 if (config_enabled(CONFIG_32BIT)) {
1487                     err = SIGILL;
1488                     break;
1489                 }
1490
1491                 rt = regs->regs[MIPSInst_RT(inst)];
1492                 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1493                 if (!access_ok(VERIFY_READ, vaddr, 8)) {
1494                         current->thread.cp0_baduaddr = vaddr;
1495                         err = SIGSEGV;
1496                         break;
1497                 }
1498                 __asm__ __volatile__(
1499                         "       .set    push\n"
1500                         "       .set    reorder\n"
1501 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1502                         "1:     lb      %1, 0(%2)\n"
1503                         "       dinsu   %0, %1, 56, 8\n"
1504                         "       andi    %1, %2, 0x7\n"
1505                         "       beq     $0, %1, 9f\n"
1506                         "       daddiu  %2, %2, -1\n"
1507                         "2:     lb      %1, 0(%2)\n"
1508                         "       dinsu   %0, %1, 48, 8\n"
1509                         "       andi    %1, %2, 0x7\n"
1510                         "       beq     $0, %1, 9f\n"
1511                         "       daddiu  %2, %2, -1\n"
1512                         "3:     lb      %1, 0(%2)\n"
1513                         "       dinsu   %0, %1, 40, 8\n"
1514                         "       andi    %1, %2, 0x7\n"
1515                         "       beq     $0, %1, 9f\n"
1516                         "       daddiu  %2, %2, -1\n"
1517                         "4:     lb      %1, 0(%2)\n"
1518                         "       dinsu   %0, %1, 32, 8\n"
1519                         "       andi    %1, %2, 0x7\n"
1520                         "       beq     $0, %1, 9f\n"
1521                         "       daddiu  %2, %2, -1\n"
1522                         "5:     lb      %1, 0(%2)\n"
1523                         "       dins    %0, %1, 24, 8\n"
1524                         "       andi    %1, %2, 0x7\n"
1525                         "       beq     $0, %1, 9f\n"
1526                         "       daddiu  %2, %2, -1\n"
1527                         "6:     lb      %1, 0(%2)\n"
1528                         "       dins    %0, %1, 16, 8\n"
1529                         "       andi    %1, %2, 0x7\n"
1530                         "       beq     $0, %1, 9f\n"
1531                         "       daddiu  %2, %2, -1\n"
1532                         "7:     lb      %1, 0(%2)\n"
1533                         "       dins    %0, %1, 8, 8\n"
1534                         "       andi    %1, %2, 0x7\n"
1535                         "       beq     $0, %1, 9f\n"
1536                         "       daddiu  %2, %2, -1\n"
1537                         "0:     lb      %1, 0(%2)\n"
1538                         "       dins    %0, %1, 0, 8\n"
1539 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1540                         "1:     lb      %1, 0(%2)\n"
1541                         "       dinsu   %0, %1, 56, 8\n"
1542                         "       daddiu  %2, %2, 1\n"
1543                         "       andi    %1, %2, 0x7\n"
1544                         "       beq     $0, %1, 9f\n"
1545                         "2:     lb      %1, 0(%2)\n"
1546                         "       dinsu   %0, %1, 48, 8\n"
1547                         "       daddiu  %2, %2, 1\n"
1548                         "       andi    %1, %2, 0x7\n"
1549                         "       beq     $0, %1, 9f\n"
1550                         "3:     lb      %1, 0(%2)\n"
1551                         "       dinsu   %0, %1, 40, 8\n"
1552                         "       daddiu  %2, %2, 1\n"
1553                         "       andi    %1, %2, 0x7\n"
1554                         "       beq     $0, %1, 9f\n"
1555                         "4:     lb      %1, 0(%2)\n"
1556                         "       dinsu   %0, %1, 32, 8\n"
1557                         "       daddiu  %2, %2, 1\n"
1558                         "       andi    %1, %2, 0x7\n"
1559                         "       beq     $0, %1, 9f\n"
1560                         "5:     lb      %1, 0(%2)\n"
1561                         "       dins    %0, %1, 24, 8\n"
1562                         "       daddiu  %2, %2, 1\n"
1563                         "       andi    %1, %2, 0x7\n"
1564                         "       beq     $0, %1, 9f\n"
1565                         "6:     lb      %1, 0(%2)\n"
1566                         "       dins    %0, %1, 16, 8\n"
1567                         "       daddiu  %2, %2, 1\n"
1568                         "       andi    %1, %2, 0x7\n"
1569                         "       beq     $0, %1, 9f\n"
1570                         "7:     lb      %1, 0(%2)\n"
1571                         "       dins    %0, %1, 8, 8\n"
1572                         "       daddiu  %2, %2, 1\n"
1573                         "       andi    %1, %2, 0x7\n"
1574                         "       beq     $0, %1, 9f\n"
1575                         "0:     lb      %1, 0(%2)\n"
1576                         "       dins    %0, %1, 0, 8\n"
1577 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1578                         "9:\n"
1579                         "       .insn\n"
1580                         "       .section        .fixup,\"ax\"\n"
1581                         "8:     li      %3,%4\n"
1582                         "       j       9b\n"
1583                         "       .previous\n"
1584                         "       .section        __ex_table,\"a\"\n"
1585                         "       .word   1b,8b\n"
1586                         "       .word   2b,8b\n"
1587                         "       .word   3b,8b\n"
1588                         "       .word   4b,8b\n"
1589                         "       .word   5b,8b\n"
1590                         "       .word   6b,8b\n"
1591                         "       .word   7b,8b\n"
1592                         "       .word   0b,8b\n"
1593                         "       .previous\n"
1594                         "       .set    pop\n"
1595                         : "+&r"(rt), "=&r"(rs),
1596                           "+&r"(vaddr), "+&r"(err)
1597                         : "i"(SIGSEGV));
1598                 if (MIPSInst_RT(inst) && !err)
1599                         regs->regs[MIPSInst_RT(inst)] = rt;
1600
1601                 MIPS_R2_STATS(loads);
1602                 break;
1603
1604         case ldr_op:
1605                 if (config_enabled(CONFIG_32BIT)) {
1606                     err = SIGILL;
1607                     break;
1608                 }
1609
1610                 rt = regs->regs[MIPSInst_RT(inst)];
1611                 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1612                 if (!access_ok(VERIFY_READ, vaddr, 8)) {
1613                         current->thread.cp0_baduaddr = vaddr;
1614                         err = SIGSEGV;
1615                         break;
1616                 }
1617                 __asm__ __volatile__(
1618                         "       .set    push\n"
1619                         "       .set    reorder\n"
1620 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1621                         "1:     lb      %1, 0(%2)\n"
1622                         "       dins   %0, %1, 0, 8\n"
1623                         "       daddiu  %2, %2, 1\n"
1624                         "       andi    %1, %2, 0x7\n"
1625                         "       beq     $0, %1, 9f\n"
1626                         "2:     lb      %1, 0(%2)\n"
1627                         "       dins   %0, %1, 8, 8\n"
1628                         "       daddiu  %2, %2, 1\n"
1629                         "       andi    %1, %2, 0x7\n"
1630                         "       beq     $0, %1, 9f\n"
1631                         "3:     lb      %1, 0(%2)\n"
1632                         "       dins   %0, %1, 16, 8\n"
1633                         "       daddiu  %2, %2, 1\n"
1634                         "       andi    %1, %2, 0x7\n"
1635                         "       beq     $0, %1, 9f\n"
1636                         "4:     lb      %1, 0(%2)\n"
1637                         "       dins   %0, %1, 24, 8\n"
1638                         "       daddiu  %2, %2, 1\n"
1639                         "       andi    %1, %2, 0x7\n"
1640                         "       beq     $0, %1, 9f\n"
1641                         "5:     lb      %1, 0(%2)\n"
1642                         "       dinsu    %0, %1, 32, 8\n"
1643                         "       daddiu  %2, %2, 1\n"
1644                         "       andi    %1, %2, 0x7\n"
1645                         "       beq     $0, %1, 9f\n"
1646                         "6:     lb      %1, 0(%2)\n"
1647                         "       dinsu    %0, %1, 40, 8\n"
1648                         "       daddiu  %2, %2, 1\n"
1649                         "       andi    %1, %2, 0x7\n"
1650                         "       beq     $0, %1, 9f\n"
1651                         "7:     lb      %1, 0(%2)\n"
1652                         "       dinsu    %0, %1, 48, 8\n"
1653                         "       daddiu  %2, %2, 1\n"
1654                         "       andi    %1, %2, 0x7\n"
1655                         "       beq     $0, %1, 9f\n"
1656                         "0:     lb      %1, 0(%2)\n"
1657                         "       dinsu    %0, %1, 56, 8\n"
1658 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1659                         "1:     lb      %1, 0(%2)\n"
1660                         "       dins   %0, %1, 0, 8\n"
1661                         "       andi    %1, %2, 0x7\n"
1662                         "       beq     $0, %1, 9f\n"
1663                         "       daddiu  %2, %2, -1\n"
1664                         "2:     lb      %1, 0(%2)\n"
1665                         "       dins   %0, %1, 8, 8\n"
1666                         "       andi    %1, %2, 0x7\n"
1667                         "       beq     $0, %1, 9f\n"
1668                         "       daddiu  %2, %2, -1\n"
1669                         "3:     lb      %1, 0(%2)\n"
1670                         "       dins   %0, %1, 16, 8\n"
1671                         "       andi    %1, %2, 0x7\n"
1672                         "       beq     $0, %1, 9f\n"
1673                         "       daddiu  %2, %2, -1\n"
1674                         "4:     lb      %1, 0(%2)\n"
1675                         "       dins   %0, %1, 24, 8\n"
1676                         "       andi    %1, %2, 0x7\n"
1677                         "       beq     $0, %1, 9f\n"
1678                         "       daddiu  %2, %2, -1\n"
1679                         "5:     lb      %1, 0(%2)\n"
1680                         "       dinsu    %0, %1, 32, 8\n"
1681                         "       andi    %1, %2, 0x7\n"
1682                         "       beq     $0, %1, 9f\n"
1683                         "       daddiu  %2, %2, -1\n"
1684                         "6:     lb      %1, 0(%2)\n"
1685                         "       dinsu    %0, %1, 40, 8\n"
1686                         "       andi    %1, %2, 0x7\n"
1687                         "       beq     $0, %1, 9f\n"
1688                         "       daddiu  %2, %2, -1\n"
1689                         "7:     lb      %1, 0(%2)\n"
1690                         "       dinsu    %0, %1, 48, 8\n"
1691                         "       andi    %1, %2, 0x7\n"
1692                         "       beq     $0, %1, 9f\n"
1693                         "       daddiu  %2, %2, -1\n"
1694                         "0:     lb      %1, 0(%2)\n"
1695                         "       dinsu    %0, %1, 56, 8\n"
1696 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1697                         "9:\n"
1698                         "       .insn\n"
1699                         "       .section        .fixup,\"ax\"\n"
1700                         "8:     li     %3,%4\n"
1701                         "       j      9b\n"
1702                         "       .previous\n"
1703                         "       .section        __ex_table,\"a\"\n"
1704                         "       .word  1b,8b\n"
1705                         "       .word  2b,8b\n"
1706                         "       .word  3b,8b\n"
1707                         "       .word  4b,8b\n"
1708                         "       .word  5b,8b\n"
1709                         "       .word  6b,8b\n"
1710                         "       .word  7b,8b\n"
1711                         "       .word  0b,8b\n"
1712                         "       .previous\n"
1713                         "       .set    pop\n"
1714                         : "+&r"(rt), "=&r"(rs),
1715                           "+&r"(vaddr), "+&r"(err)
1716                         : "i"(SIGSEGV));
1717                 if (MIPSInst_RT(inst) && !err)
1718                         regs->regs[MIPSInst_RT(inst)] = rt;
1719
1720                 MIPS_R2_STATS(loads);
1721                 break;
1722
1723         case sdl_op:
1724                 if (config_enabled(CONFIG_32BIT)) {
1725                     err = SIGILL;
1726                     break;
1727                 }
1728
1729                 rt = regs->regs[MIPSInst_RT(inst)];
1730                 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1731                 if (!access_ok(VERIFY_WRITE, vaddr, 8)) {
1732                         current->thread.cp0_baduaddr = vaddr;
1733                         err = SIGSEGV;
1734                         break;
1735                 }
1736                 __asm__ __volatile__(
1737                         "       .set    push\n"
1738                         "       .set    reorder\n"
1739 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1740                         "       dextu   %1, %0, 56, 8\n"
1741                         "1:     sb      %1, 0(%2)\n"
1742                         "       andi    %1, %2, 0x7\n"
1743                         "       beq     $0, %1, 9f\n"
1744                         "       daddiu  %2, %2, -1\n"
1745                         "       dextu   %1, %0, 48, 8\n"
1746                         "2:     sb      %1, 0(%2)\n"
1747                         "       andi    %1, %2, 0x7\n"
1748                         "       beq     $0, %1, 9f\n"
1749                         "       daddiu  %2, %2, -1\n"
1750                         "       dextu   %1, %0, 40, 8\n"
1751                         "3:     sb      %1, 0(%2)\n"
1752                         "       andi    %1, %2, 0x7\n"
1753                         "       beq     $0, %1, 9f\n"
1754                         "       daddiu  %2, %2, -1\n"
1755                         "       dextu   %1, %0, 32, 8\n"
1756                         "4:     sb      %1, 0(%2)\n"
1757                         "       andi    %1, %2, 0x7\n"
1758                         "       beq     $0, %1, 9f\n"
1759                         "       daddiu  %2, %2, -1\n"
1760                         "       dext    %1, %0, 24, 8\n"
1761                         "5:     sb      %1, 0(%2)\n"
1762                         "       andi    %1, %2, 0x7\n"
1763                         "       beq     $0, %1, 9f\n"
1764                         "       daddiu  %2, %2, -1\n"
1765                         "       dext    %1, %0, 16, 8\n"
1766                         "6:     sb      %1, 0(%2)\n"
1767                         "       andi    %1, %2, 0x7\n"
1768                         "       beq     $0, %1, 9f\n"
1769                         "       daddiu  %2, %2, -1\n"
1770                         "       dext    %1, %0, 8, 8\n"
1771                         "7:     sb      %1, 0(%2)\n"
1772                         "       andi    %1, %2, 0x7\n"
1773                         "       beq     $0, %1, 9f\n"
1774                         "       daddiu  %2, %2, -1\n"
1775                         "       dext    %1, %0, 0, 8\n"
1776                         "0:     sb      %1, 0(%2)\n"
1777 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1778                         "       dextu   %1, %0, 56, 8\n"
1779                         "1:     sb      %1, 0(%2)\n"
1780                         "       daddiu  %2, %2, 1\n"
1781                         "       andi    %1, %2, 0x7\n"
1782                         "       beq     $0, %1, 9f\n"
1783                         "       dextu   %1, %0, 48, 8\n"
1784                         "2:     sb      %1, 0(%2)\n"
1785                         "       daddiu  %2, %2, 1\n"
1786                         "       andi    %1, %2, 0x7\n"
1787                         "       beq     $0, %1, 9f\n"
1788                         "       dextu   %1, %0, 40, 8\n"
1789                         "3:     sb      %1, 0(%2)\n"
1790                         "       daddiu  %2, %2, 1\n"
1791                         "       andi    %1, %2, 0x7\n"
1792                         "       beq     $0, %1, 9f\n"
1793                         "       dextu   %1, %0, 32, 8\n"
1794                         "4:     sb      %1, 0(%2)\n"
1795                         "       daddiu  %2, %2, 1\n"
1796                         "       andi    %1, %2, 0x7\n"
1797                         "       beq     $0, %1, 9f\n"
1798                         "       dext    %1, %0, 24, 8\n"
1799                         "5:     sb      %1, 0(%2)\n"
1800                         "       daddiu  %2, %2, 1\n"
1801                         "       andi    %1, %2, 0x7\n"
1802                         "       beq     $0, %1, 9f\n"
1803                         "       dext    %1, %0, 16, 8\n"
1804                         "6:     sb      %1, 0(%2)\n"
1805                         "       daddiu  %2, %2, 1\n"
1806                         "       andi    %1, %2, 0x7\n"
1807                         "       beq     $0, %1, 9f\n"
1808                         "       dext    %1, %0, 8, 8\n"
1809                         "7:     sb      %1, 0(%2)\n"
1810                         "       daddiu  %2, %2, 1\n"
1811                         "       andi    %1, %2, 0x7\n"
1812                         "       beq     $0, %1, 9f\n"
1813                         "       dext    %1, %0, 0, 8\n"
1814                         "0:     sb      %1, 0(%2)\n"
1815 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1816                         "9:\n"
1817                         "       .insn\n"
1818                         "       .section        .fixup,\"ax\"\n"
1819                         "8:     li      %3,%4\n"
1820                         "       j       9b\n"
1821                         "       .previous\n"
1822                         "       .section        __ex_table,\"a\"\n"
1823                         "       .word   1b,8b\n"
1824                         "       .word   2b,8b\n"
1825                         "       .word   3b,8b\n"
1826                         "       .word   4b,8b\n"
1827                         "       .word   5b,8b\n"
1828                         "       .word   6b,8b\n"
1829                         "       .word   7b,8b\n"
1830                         "       .word   0b,8b\n"
1831                         "       .previous\n"
1832                         "       .set    pop\n"
1833                         : "+&r"(rt), "=&r"(rs),
1834                           "+&r"(vaddr), "+&r"(err)
1835                         : "i"(SIGSEGV)
1836                         : "memory");
1837
1838                 MIPS_R2_STATS(stores);
1839                 break;
1840
1841         case sdr_op:
1842                 if (config_enabled(CONFIG_32BIT)) {
1843                     err = SIGILL;
1844                     break;
1845                 }
1846
1847                 rt = regs->regs[MIPSInst_RT(inst)];
1848                 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1849                 if (!access_ok(VERIFY_WRITE, vaddr, 8)) {
1850                         current->thread.cp0_baduaddr = vaddr;
1851                         err = SIGSEGV;
1852                         break;
1853                 }
1854                 __asm__ __volatile__(
1855                         "       .set    push\n"
1856                         "       .set    reorder\n"
1857 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1858                         "       dext    %1, %0, 0, 8\n"
1859                         "1:     sb      %1, 0(%2)\n"
1860                         "       daddiu  %2, %2, 1\n"
1861                         "       andi    %1, %2, 0x7\n"
1862                         "       beq     $0, %1, 9f\n"
1863                         "       dext    %1, %0, 8, 8\n"
1864                         "2:     sb      %1, 0(%2)\n"
1865                         "       daddiu  %2, %2, 1\n"
1866                         "       andi    %1, %2, 0x7\n"
1867                         "       beq     $0, %1, 9f\n"
1868                         "       dext    %1, %0, 16, 8\n"
1869                         "3:     sb      %1, 0(%2)\n"
1870                         "       daddiu  %2, %2, 1\n"
1871                         "       andi    %1, %2, 0x7\n"
1872                         "       beq     $0, %1, 9f\n"
1873                         "       dext    %1, %0, 24, 8\n"
1874                         "4:     sb      %1, 0(%2)\n"
1875                         "       daddiu  %2, %2, 1\n"
1876                         "       andi    %1, %2, 0x7\n"
1877                         "       beq     $0, %1, 9f\n"
1878                         "       dextu   %1, %0, 32, 8\n"
1879                         "5:     sb      %1, 0(%2)\n"
1880                         "       daddiu  %2, %2, 1\n"
1881                         "       andi    %1, %2, 0x7\n"
1882                         "       beq     $0, %1, 9f\n"
1883                         "       dextu   %1, %0, 40, 8\n"
1884                         "6:     sb      %1, 0(%2)\n"
1885                         "       daddiu  %2, %2, 1\n"
1886                         "       andi    %1, %2, 0x7\n"
1887                         "       beq     $0, %1, 9f\n"
1888                         "       dextu   %1, %0, 48, 8\n"
1889                         "7:     sb      %1, 0(%2)\n"
1890                         "       daddiu  %2, %2, 1\n"
1891                         "       andi    %1, %2, 0x7\n"
1892                         "       beq     $0, %1, 9f\n"
1893                         "       dextu   %1, %0, 56, 8\n"
1894                         "0:     sb      %1, 0(%2)\n"
1895 #else /* !CONFIG_CPU_LITTLE_ENDIAN */
1896                         "       dext    %1, %0, 0, 8\n"
1897                         "1:     sb      %1, 0(%2)\n"
1898                         "       andi    %1, %2, 0x7\n"
1899                         "       beq     $0, %1, 9f\n"
1900                         "       daddiu  %2, %2, -1\n"
1901                         "       dext    %1, %0, 8, 8\n"
1902                         "2:     sb      %1, 0(%2)\n"
1903                         "       andi    %1, %2, 0x7\n"
1904                         "       beq     $0, %1, 9f\n"
1905                         "       daddiu  %2, %2, -1\n"
1906                         "       dext    %1, %0, 16, 8\n"
1907                         "3:     sb      %1, 0(%2)\n"
1908                         "       andi    %1, %2, 0x7\n"
1909                         "       beq     $0, %1, 9f\n"
1910                         "       daddiu  %2, %2, -1\n"
1911                         "       dext    %1, %0, 24, 8\n"
1912                         "4:     sb      %1, 0(%2)\n"
1913                         "       andi    %1, %2, 0x7\n"
1914                         "       beq     $0, %1, 9f\n"
1915                         "       daddiu  %2, %2, -1\n"
1916                         "       dextu   %1, %0, 32, 8\n"
1917                         "5:     sb      %1, 0(%2)\n"
1918                         "       andi    %1, %2, 0x7\n"
1919                         "       beq     $0, %1, 9f\n"
1920                         "       daddiu  %2, %2, -1\n"
1921                         "       dextu   %1, %0, 40, 8\n"
1922                         "6:     sb      %1, 0(%2)\n"
1923                         "       andi    %1, %2, 0x7\n"
1924                         "       beq     $0, %1, 9f\n"
1925                         "       daddiu  %2, %2, -1\n"
1926                         "       dextu   %1, %0, 48, 8\n"
1927                         "7:     sb      %1, 0(%2)\n"
1928                         "       andi    %1, %2, 0x7\n"
1929                         "       beq     $0, %1, 9f\n"
1930                         "       daddiu  %2, %2, -1\n"
1931                         "       dextu   %1, %0, 56, 8\n"
1932                         "0:     sb      %1, 0(%2)\n"
1933 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1934                         "9:\n"
1935                         "       .insn\n"
1936                         "       .section        .fixup,\"ax\"\n"
1937                         "8:     li      %3,%4\n"
1938                         "       j       9b\n"
1939                         "       .previous\n"
1940                         "       .section        __ex_table,\"a\"\n"
1941                         "       .word   1b,8b\n"
1942                         "       .word   2b,8b\n"
1943                         "       .word   3b,8b\n"
1944                         "       .word   4b,8b\n"
1945                         "       .word   5b,8b\n"
1946                         "       .word   6b,8b\n"
1947                         "       .word   7b,8b\n"
1948                         "       .word   0b,8b\n"
1949                         "       .previous\n"
1950                         "       .set    pop\n"
1951                         : "+&r"(rt), "=&r"(rs),
1952                           "+&r"(vaddr), "+&r"(err)
1953                         : "i"(SIGSEGV)
1954                         : "memory");
1955
1956                 MIPS_R2_STATS(stores);
1957
1958                 break;
1959         case ll_op:
1960                 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1961                 if (vaddr & 0x3) {
1962                         current->thread.cp0_baduaddr = vaddr;
1963                         err = SIGBUS;
1964                         break;
1965                 }
1966                 if (!access_ok(VERIFY_READ, vaddr, 4)) {
1967                         current->thread.cp0_baduaddr = vaddr;
1968                         err = SIGBUS;
1969                         break;
1970                 }
1971
1972                 if (!cpu_has_rw_llb) {
1973                         /*
1974                          * An LL/SC block can't be safely emulated without
1975                          * a Config5/LLB availability. So it's probably time to
1976                          * kill our process before things get any worse. This is
1977                          * because Config5/LLB allows us to use ERETNC so that
1978                          * the LLAddr/LLB bit is not cleared when we return from
1979                          * an exception. MIPS R2 LL/SC instructions trap with an
1980                          * RI exception so once we emulate them here, we return
1981                          * back to userland with ERETNC. That preserves the
1982                          * LLAddr/LLB so the subsequent SC instruction will
1983                          * succeed preserving the atomic semantics of the LL/SC
1984                          * block. Without that, there is no safe way to emulate
1985                          * an LL/SC block in MIPSR2 userland.
1986                          */
1987                         pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n");
1988                         err = SIGKILL;
1989                         break;
1990                 }
1991
1992                 __asm__ __volatile__(
1993                         "1:\n"
1994                         "ll     %0, 0(%2)\n"
1995                         "2:\n"
1996                         ".insn\n"
1997                         ".section        .fixup,\"ax\"\n"
1998                         "3:\n"
1999                         "li     %1, %3\n"
2000                         "j      2b\n"
2001                         ".previous\n"
2002                         ".section        __ex_table,\"a\"\n"
2003                         ".word  1b, 3b\n"
2004                         ".previous\n"
2005                         : "=&r"(res), "+&r"(err)
2006                         : "r"(vaddr), "i"(SIGSEGV)
2007                         : "memory");
2008
2009                 if (MIPSInst_RT(inst) && !err)
2010                         regs->regs[MIPSInst_RT(inst)] = res;
2011                 MIPS_R2_STATS(llsc);
2012
2013                 break;
2014
2015         case sc_op:
2016                 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
2017                 if (vaddr & 0x3) {
2018                         current->thread.cp0_baduaddr = vaddr;
2019                         err = SIGBUS;
2020                         break;
2021                 }
2022                 if (!access_ok(VERIFY_WRITE, vaddr, 4)) {
2023                         current->thread.cp0_baduaddr = vaddr;
2024                         err = SIGBUS;
2025                         break;
2026                 }
2027
2028                 if (!cpu_has_rw_llb) {
2029                         /*
2030                          * An LL/SC block can't be safely emulated without
2031                          * a Config5/LLB availability. So it's probably time to
2032                          * kill our process before things get any worse. This is
2033                          * because Config5/LLB allows us to use ERETNC so that
2034                          * the LLAddr/LLB bit is not cleared when we return from
2035                          * an exception. MIPS R2 LL/SC instructions trap with an
2036                          * RI exception so once we emulate them here, we return
2037                          * back to userland with ERETNC. That preserves the
2038                          * LLAddr/LLB so the subsequent SC instruction will
2039                          * succeed preserving the atomic semantics of the LL/SC
2040                          * block. Without that, there is no safe way to emulate
2041                          * an LL/SC block in MIPSR2 userland.
2042                          */
2043                         pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n");
2044                         err = SIGKILL;
2045                         break;
2046                 }
2047
2048                 res = regs->regs[MIPSInst_RT(inst)];
2049
2050                 __asm__ __volatile__(
2051                         "1:\n"
2052                         "sc     %0, 0(%2)\n"
2053                         "2:\n"
2054                         ".insn\n"
2055                         ".section        .fixup,\"ax\"\n"
2056                         "3:\n"
2057                         "li     %1, %3\n"
2058                         "j      2b\n"
2059                         ".previous\n"
2060                         ".section        __ex_table,\"a\"\n"
2061                         ".word  1b, 3b\n"
2062                         ".previous\n"
2063                         : "+&r"(res), "+&r"(err)
2064                         : "r"(vaddr), "i"(SIGSEGV));
2065
2066                 if (MIPSInst_RT(inst) && !err)
2067                         regs->regs[MIPSInst_RT(inst)] = res;
2068
2069                 MIPS_R2_STATS(llsc);
2070
2071                 break;
2072
2073         case lld_op:
2074                 if (config_enabled(CONFIG_32BIT)) {
2075                     err = SIGILL;
2076                     break;
2077                 }
2078
2079                 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
2080                 if (vaddr & 0x7) {
2081                         current->thread.cp0_baduaddr = vaddr;
2082                         err = SIGBUS;
2083                         break;
2084                 }
2085                 if (!access_ok(VERIFY_READ, vaddr, 8)) {
2086                         current->thread.cp0_baduaddr = vaddr;
2087                         err = SIGBUS;
2088                         break;
2089                 }
2090
2091                 if (!cpu_has_rw_llb) {
2092                         /*
2093                          * An LL/SC block can't be safely emulated without
2094                          * a Config5/LLB availability. So it's probably time to
2095                          * kill our process before things get any worse. This is
2096                          * because Config5/LLB allows us to use ERETNC so that
2097                          * the LLAddr/LLB bit is not cleared when we return from
2098                          * an exception. MIPS R2 LL/SC instructions trap with an
2099                          * RI exception so once we emulate them here, we return
2100                          * back to userland with ERETNC. That preserves the
2101                          * LLAddr/LLB so the subsequent SC instruction will
2102                          * succeed preserving the atomic semantics of the LL/SC
2103                          * block. Without that, there is no safe way to emulate
2104                          * an LL/SC block in MIPSR2 userland.
2105                          */
2106                         pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n");
2107                         err = SIGKILL;
2108                         break;
2109                 }
2110
2111                 __asm__ __volatile__(
2112                         "1:\n"
2113                         "lld    %0, 0(%2)\n"
2114                         "2:\n"
2115                         ".insn\n"
2116                         ".section        .fixup,\"ax\"\n"
2117                         "3:\n"
2118                         "li     %1, %3\n"
2119                         "j      2b\n"
2120                         ".previous\n"
2121                         ".section        __ex_table,\"a\"\n"
2122                         ".word  1b, 3b\n"
2123                         ".previous\n"
2124                         : "=&r"(res), "+&r"(err)
2125                         : "r"(vaddr), "i"(SIGSEGV)
2126                         : "memory");
2127                 if (MIPSInst_RT(inst) && !err)
2128                         regs->regs[MIPSInst_RT(inst)] = res;
2129
2130                 MIPS_R2_STATS(llsc);
2131
2132                 break;
2133
2134         case scd_op:
2135                 if (config_enabled(CONFIG_32BIT)) {
2136                     err = SIGILL;
2137                     break;
2138                 }
2139
2140                 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
2141                 if (vaddr & 0x7) {
2142                         current->thread.cp0_baduaddr = vaddr;
2143                         err = SIGBUS;
2144                         break;
2145                 }
2146                 if (!access_ok(VERIFY_WRITE, vaddr, 8)) {
2147                         current->thread.cp0_baduaddr = vaddr;
2148                         err = SIGBUS;
2149                         break;
2150                 }
2151
2152                 if (!cpu_has_rw_llb) {
2153                         /*
2154                          * An LL/SC block can't be safely emulated without
2155                          * a Config5/LLB availability. So it's probably time to
2156                          * kill our process before things get any worse. This is
2157                          * because Config5/LLB allows us to use ERETNC so that
2158                          * the LLAddr/LLB bit is not cleared when we return from
2159                          * an exception. MIPS R2 LL/SC instructions trap with an
2160                          * RI exception so once we emulate them here, we return
2161                          * back to userland with ERETNC. That preserves the
2162                          * LLAddr/LLB so the subsequent SC instruction will
2163                          * succeed preserving the atomic semantics of the LL/SC
2164                          * block. Without that, there is no safe way to emulate
2165                          * an LL/SC block in MIPSR2 userland.
2166                          */
2167                         pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n");
2168                         err = SIGKILL;
2169                         break;
2170                 }
2171
2172                 res = regs->regs[MIPSInst_RT(inst)];
2173
2174                 __asm__ __volatile__(
2175                         "1:\n"
2176                         "scd    %0, 0(%2)\n"
2177                         "2:\n"
2178                         ".insn\n"
2179                         ".section        .fixup,\"ax\"\n"
2180                         "3:\n"
2181                         "li     %1, %3\n"
2182                         "j      2b\n"
2183                         ".previous\n"
2184                         ".section        __ex_table,\"a\"\n"
2185                         ".word  1b, 3b\n"
2186                         ".previous\n"
2187                         : "+&r"(res), "+&r"(err)
2188                         : "r"(vaddr), "i"(SIGSEGV));
2189
2190                 if (MIPSInst_RT(inst) && !err)
2191                         regs->regs[MIPSInst_RT(inst)] = res;
2192
2193                 MIPS_R2_STATS(llsc);
2194
2195                 break;
2196         case pref_op:
2197                 /* skip it */
2198                 break;
2199         default:
2200                 err = SIGILL;
2201         }
2202
2203         /*
2204          * Lets not return to userland just yet. It's constly and
2205          * it's likely we have more R2 instructions to emulate
2206          */
2207         if (!err && (pass++ < MIPS_R2_EMUL_TOTAL_PASS)) {
2208                 regs->cp0_cause &= ~CAUSEF_BD;
2209                 err = get_user(inst, (u32 __user *)regs->cp0_epc);
2210                 if (!err)
2211                         goto repeat;
2212
2213                 if (err < 0)
2214                         err = SIGSEGV;
2215         }
2216
2217         if (err && (err != SIGEMT)) {
2218                 regs->regs[31] = r31;
2219                 regs->cp0_epc = epc;
2220         }
2221
2222         /* Likely a MIPS R6 compatible instruction */
2223         if (pass && (err == SIGILL))
2224                 err = 0;
2225
2226         return err;
2227 }
2228
2229 #ifdef CONFIG_DEBUG_FS
2230
2231 static int mipsr2_stats_show(struct seq_file *s, void *unused)
2232 {
2233
2234         seq_printf(s, "Instruction\tTotal\tBDslot\n------------------------------\n");
2235         seq_printf(s, "movs\t\t%ld\t%ld\n",
2236                    (unsigned long)__this_cpu_read(mipsr2emustats.movs),
2237                    (unsigned long)__this_cpu_read(mipsr2bdemustats.movs));
2238         seq_printf(s, "hilo\t\t%ld\t%ld\n",
2239                    (unsigned long)__this_cpu_read(mipsr2emustats.hilo),
2240                    (unsigned long)__this_cpu_read(mipsr2bdemustats.hilo));
2241         seq_printf(s, "muls\t\t%ld\t%ld\n",
2242                    (unsigned long)__this_cpu_read(mipsr2emustats.muls),
2243                    (unsigned long)__this_cpu_read(mipsr2bdemustats.muls));
2244         seq_printf(s, "divs\t\t%ld\t%ld\n",
2245                    (unsigned long)__this_cpu_read(mipsr2emustats.divs),
2246                    (unsigned long)__this_cpu_read(mipsr2bdemustats.divs));
2247         seq_printf(s, "dsps\t\t%ld\t%ld\n",
2248                    (unsigned long)__this_cpu_read(mipsr2emustats.dsps),
2249                    (unsigned long)__this_cpu_read(mipsr2bdemustats.dsps));
2250         seq_printf(s, "bops\t\t%ld\t%ld\n",
2251                    (unsigned long)__this_cpu_read(mipsr2emustats.bops),
2252                    (unsigned long)__this_cpu_read(mipsr2bdemustats.bops));
2253         seq_printf(s, "traps\t\t%ld\t%ld\n",
2254                    (unsigned long)__this_cpu_read(mipsr2emustats.traps),
2255                    (unsigned long)__this_cpu_read(mipsr2bdemustats.traps));
2256         seq_printf(s, "fpus\t\t%ld\t%ld\n",
2257                    (unsigned long)__this_cpu_read(mipsr2emustats.fpus),
2258                    (unsigned long)__this_cpu_read(mipsr2bdemustats.fpus));
2259         seq_printf(s, "loads\t\t%ld\t%ld\n",
2260                    (unsigned long)__this_cpu_read(mipsr2emustats.loads),
2261                    (unsigned long)__this_cpu_read(mipsr2bdemustats.loads));
2262         seq_printf(s, "stores\t\t%ld\t%ld\n",
2263                    (unsigned long)__this_cpu_read(mipsr2emustats.stores),
2264                    (unsigned long)__this_cpu_read(mipsr2bdemustats.stores));
2265         seq_printf(s, "llsc\t\t%ld\t%ld\n",
2266                    (unsigned long)__this_cpu_read(mipsr2emustats.llsc),
2267                    (unsigned long)__this_cpu_read(mipsr2bdemustats.llsc));
2268         seq_printf(s, "dsemul\t\t%ld\t%ld\n",
2269                    (unsigned long)__this_cpu_read(mipsr2emustats.dsemul),
2270                    (unsigned long)__this_cpu_read(mipsr2bdemustats.dsemul));
2271         seq_printf(s, "jr\t\t%ld\n",
2272                    (unsigned long)__this_cpu_read(mipsr2bremustats.jrs));
2273         seq_printf(s, "bltzl\t\t%ld\n",
2274                    (unsigned long)__this_cpu_read(mipsr2bremustats.bltzl));
2275         seq_printf(s, "bgezl\t\t%ld\n",
2276                    (unsigned long)__this_cpu_read(mipsr2bremustats.bgezl));
2277         seq_printf(s, "bltzll\t\t%ld\n",
2278                    (unsigned long)__this_cpu_read(mipsr2bremustats.bltzll));
2279         seq_printf(s, "bgezll\t\t%ld\n",
2280                    (unsigned long)__this_cpu_read(mipsr2bremustats.bgezll));
2281         seq_printf(s, "bltzal\t\t%ld\n",
2282                    (unsigned long)__this_cpu_read(mipsr2bremustats.bltzal));
2283         seq_printf(s, "bgezal\t\t%ld\n",
2284                    (unsigned long)__this_cpu_read(mipsr2bremustats.bgezal));
2285         seq_printf(s, "beql\t\t%ld\n",
2286                    (unsigned long)__this_cpu_read(mipsr2bremustats.beql));
2287         seq_printf(s, "bnel\t\t%ld\n",
2288                    (unsigned long)__this_cpu_read(mipsr2bremustats.bnel));
2289         seq_printf(s, "blezl\t\t%ld\n",
2290                    (unsigned long)__this_cpu_read(mipsr2bremustats.blezl));
2291         seq_printf(s, "bgtzl\t\t%ld\n",
2292                    (unsigned long)__this_cpu_read(mipsr2bremustats.bgtzl));
2293
2294         return 0;
2295 }
2296
2297 static int mipsr2_stats_clear_show(struct seq_file *s, void *unused)
2298 {
2299         mipsr2_stats_show(s, unused);
2300
2301         __this_cpu_write((mipsr2emustats).movs, 0);
2302         __this_cpu_write((mipsr2bdemustats).movs, 0);
2303         __this_cpu_write((mipsr2emustats).hilo, 0);
2304         __this_cpu_write((mipsr2bdemustats).hilo, 0);
2305         __this_cpu_write((mipsr2emustats).muls, 0);
2306         __this_cpu_write((mipsr2bdemustats).muls, 0);
2307         __this_cpu_write((mipsr2emustats).divs, 0);
2308         __this_cpu_write((mipsr2bdemustats).divs, 0);
2309         __this_cpu_write((mipsr2emustats).dsps, 0);
2310         __this_cpu_write((mipsr2bdemustats).dsps, 0);
2311         __this_cpu_write((mipsr2emustats).bops, 0);
2312         __this_cpu_write((mipsr2bdemustats).bops, 0);
2313         __this_cpu_write((mipsr2emustats).traps, 0);
2314         __this_cpu_write((mipsr2bdemustats).traps, 0);
2315         __this_cpu_write((mipsr2emustats).fpus, 0);
2316         __this_cpu_write((mipsr2bdemustats).fpus, 0);
2317         __this_cpu_write((mipsr2emustats).loads, 0);
2318         __this_cpu_write((mipsr2bdemustats).loads, 0);
2319         __this_cpu_write((mipsr2emustats).stores, 0);
2320         __this_cpu_write((mipsr2bdemustats).stores, 0);
2321         __this_cpu_write((mipsr2emustats).llsc, 0);
2322         __this_cpu_write((mipsr2bdemustats).llsc, 0);
2323         __this_cpu_write((mipsr2emustats).dsemul, 0);
2324         __this_cpu_write((mipsr2bdemustats).dsemul, 0);
2325         __this_cpu_write((mipsr2bremustats).jrs, 0);
2326         __this_cpu_write((mipsr2bremustats).bltzl, 0);
2327         __this_cpu_write((mipsr2bremustats).bgezl, 0);
2328         __this_cpu_write((mipsr2bremustats).bltzll, 0);
2329         __this_cpu_write((mipsr2bremustats).bgezll, 0);
2330         __this_cpu_write((mipsr2bremustats).bltzal, 0);
2331         __this_cpu_write((mipsr2bremustats).bgezal, 0);
2332         __this_cpu_write((mipsr2bremustats).beql, 0);
2333         __this_cpu_write((mipsr2bremustats).bnel, 0);
2334         __this_cpu_write((mipsr2bremustats).blezl, 0);
2335         __this_cpu_write((mipsr2bremustats).bgtzl, 0);
2336
2337         return 0;
2338 }
2339
2340 static int mipsr2_stats_open(struct inode *inode, struct file *file)
2341 {
2342         return single_open(file, mipsr2_stats_show, inode->i_private);
2343 }
2344
2345 static int mipsr2_stats_clear_open(struct inode *inode, struct file *file)
2346 {
2347         return single_open(file, mipsr2_stats_clear_show, inode->i_private);
2348 }
2349
2350 static const struct file_operations mipsr2_emul_fops = {
2351         .open                   = mipsr2_stats_open,
2352         .read                   = seq_read,
2353         .llseek                 = seq_lseek,
2354         .release                = single_release,
2355 };
2356
2357 static const struct file_operations mipsr2_clear_fops = {
2358         .open                   = mipsr2_stats_clear_open,
2359         .read                   = seq_read,
2360         .llseek                 = seq_lseek,
2361         .release                = single_release,
2362 };
2363
2364
2365 static int __init mipsr2_init_debugfs(void)
2366 {
2367         struct dentry           *mipsr2_emul;
2368
2369         if (!mips_debugfs_dir)
2370                 return -ENODEV;
2371
2372         mipsr2_emul = debugfs_create_file("r2_emul_stats", S_IRUGO,
2373                                           mips_debugfs_dir, NULL,
2374                                           &mipsr2_emul_fops);
2375         if (!mipsr2_emul)
2376                 return -ENOMEM;
2377
2378         mipsr2_emul = debugfs_create_file("r2_emul_stats_clear", S_IRUGO,
2379                                           mips_debugfs_dir, NULL,
2380                                           &mipsr2_clear_fops);
2381         if (!mipsr2_emul)
2382                 return -ENOMEM;
2383
2384         return 0;
2385 }
2386
2387 device_initcall(mipsr2_init_debugfs);
2388
2389 #endif /* CONFIG_DEBUG_FS */