arch/mips/kernel/smp-cps.c

   1 /*
   2  * Copyright (C) 2013 Imagination Technologies
   3  * Author: Paul Burton <paul.burton@imgtec.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation;  either version 2 of the  License, or (at your
   8  * option) any later version.
   9  */
  10
  11 #include <linux/io.h>
  12 #include <linux/irqchip/mips-gic.h>
  13 #include <linux/sched.h>
  14 #include <linux/slab.h>
  15 #include <linux/smp.h>
  16 #include <linux/types.h>
  17
  18 #include <asm/bcache.h>
  19 #include <asm/mips-cm.h>
  20 #include <asm/mips-cpc.h>
  21 #include <asm/mips_mt.h>
  22 #include <asm/mipsregs.h>
  23 #include <asm/pm-cps.h>
  24 #include <asm/r4kcache.h>
  25 #include <asm/smp-cps.h>
  26 #include <asm/time.h>
  27 #include <asm/uasm.h>
  28
  29 static DECLARE_BITMAP(core_power, NR_CPUS);
  30
  31 struct core_boot_config *mips_cps_core_bootcfg;
  32
  33 static unsigned core_vpe_count(unsigned core)
  34 {
  35         unsigned cfg;
  36
  37         if (!config_enabled(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt)
  38                 return 1;
  39
  40         write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF);
  41         cfg = read_gcr_co_config() & CM_GCR_Cx_CONFIG_PVPE_MSK;
  42         return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
  43 }
  44
  45 static void __init cps_smp_setup(void)
  46 {
  47         unsigned int ncores, nvpes, core_vpes;
  48         int c, v;
  49
  50         /* Detect & record VPE topology */
  51         ncores = mips_cm_numcores();
  52         pr_info("VPE topology ");
  53         for (c = nvpes = 0; c < ncores; c++) {
  54                 core_vpes = core_vpe_count(c);
  55                 pr_cont("%c%u", c ? ',' : '{', core_vpes);
  56
  57                 /* Use the number of VPEs in core 0 for smp_num_siblings */
  58                 if (!c)
  59                         smp_num_siblings = core_vpes;
  60
  61                 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
  62                         cpu_data[nvpes + v].core = c;
  63 #ifdef CONFIG_MIPS_MT_SMP
  64                         cpu_data[nvpes + v].vpe_id = v;
  65 #endif
  66                 }
  67
  68                 nvpes += core_vpes;
  69         }
  70         pr_cont("} total %u\n", nvpes);
  71
  72         /* Indicate present CPUs (CPU being synonymous with VPE) */
  73         for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
  74                 set_cpu_possible(v, true);
  75                 set_cpu_present(v, true);
  76                 __cpu_number_map[v] = v;
  77                 __cpu_logical_map[v] = v;
  78         }
  79
  80         /* Set a coherent default CCA (CWB) */
  81         change_c0_config(CONF_CM_CMASK, 0x5);
  82
  83         /* Core 0 is powered up (we're running on it) */
  84         bitmap_set(core_power, 0, 1);
  85
  86         /* Initialise core 0 */
  87         mips_cps_core_init();
  88
  89         /* Make core 0 coherent with everything */
  90         write_gcr_cl_coherence(0xff);
  91
  92 #ifdef CONFIG_MIPS_MT_FPAFF
  93         /* If we have an FPU, enroll ourselves in the FPU-full mask */
  94         if (cpu_has_fpu)
  95                 cpumask_set_cpu(0, &mt_fpu_cpumask);
  96 #endif /* CONFIG_MIPS_MT_FPAFF */
  97 }
  98
  99 static void __init cps_prepare_cpus(unsigned int max_cpus)
 100 {
 101         unsigned ncores, core_vpes, c, cca;
 102         bool cca_unsuitable;
 103         u32 *entry_code;
 104
 105         mips_mt_set_cpuoptions();
 106
 107         /* Detect whether the CCA is unsuited to multi-core SMP */
 108         cca = read_c0_config() & CONF_CM_CMASK;
 109         switch (cca) {
 110         case 0x4: /* CWBE */
 111         case 0x5: /* CWB */
 112                 /* The CCA is coherent, multi-core is fine */
 113                 cca_unsuitable = false;
 114                 break;
 115
 116         default:
 117                 /* CCA is not coherent, multi-core is not usable */
 118                 cca_unsuitable = true;
 119         }
 120
 121         /* Warn the user if the CCA prevents multi-core */
 122         ncores = mips_cm_numcores();
 123         if (cca_unsuitable && ncores > 1) {
 124                 pr_warn("Using only one core due to unsuitable CCA 0x%x\n",
 125                         cca);
 126
 127                 for_each_present_cpu(c) {
 128                         if (cpu_data[c].core)
 129                                 set_cpu_present(c, false);
 130                 }
 131         }
 132
 133         /*
 134          * Patch the start of mips_cps_core_entry to provide:
 135          *
 136          * v1 = CM base address
 137          * s0 = kseg0 CCA
 138          */
 139         entry_code = (u32 *)&mips_cps_core_entry;
 140         UASM_i_LA(&entry_code, 3, (long)mips_cm_base);
 141         uasm_i_addiu(&entry_code, 16, 0, cca);
 142         blast_dcache_range((unsigned long)&mips_cps_core_entry,
 143                            (unsigned long)entry_code);
 144         bc_wback_inv((unsigned long)&mips_cps_core_entry,
 145                      (void *)entry_code - (void *)&mips_cps_core_entry);
 146         __sync();
 147
 148         /* Allocate core boot configuration structs */
 149         mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg),
 150                                         GFP_KERNEL);
 151         if (!mips_cps_core_bootcfg) {
 152                 pr_err("Failed to allocate boot config for %u cores\n", ncores);
 153                 goto err_out;
 154         }
 155
 156         /* Allocate VPE boot configuration structs */
 157         for (c = 0; c < ncores; c++) {
 158                 core_vpes = core_vpe_count(c);
 159                 mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes,
 160                                 sizeof(*mips_cps_core_bootcfg[c].vpe_config),
 161                                 GFP_KERNEL);
 162                 if (!mips_cps_core_bootcfg[c].vpe_config) {
 163                         pr_err("Failed to allocate %u VPE boot configs\n",
 164                                core_vpes);
 165                         goto err_out;
 166                 }
 167         }
 168
 169         /* Mark this CPU as booted */
 170         atomic_set(&mips_cps_core_bootcfg[current_cpu_data.core].vpe_mask,
 171                    1 << cpu_vpe_id(&current_cpu_data));
 172
 173         return;
 174 err_out:
 175         /* Clean up allocations */
 176         if (mips_cps_core_bootcfg) {
 177                 for (c = 0; c < ncores; c++)
 178                         kfree(mips_cps_core_bootcfg[c].vpe_config);
 179                 kfree(mips_cps_core_bootcfg);
 180                 mips_cps_core_bootcfg = NULL;
 181         }
 182
 183         /* Effectively disable SMP by declaring CPUs not present */
 184         for_each_possible_cpu(c) {
 185                 if (c == 0)
 186                         continue;
 187                 set_cpu_present(c, false);
 188         }
 189 }
 190
 191 static void boot_core(unsigned core)
 192 {
 193         u32 access;
 194
 195         /* Select the appropriate core */
 196         write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF);
 197
 198         /* Set its reset vector */
 199         write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
 200
 201         /* Ensure its coherency is disabled */
 202         write_gcr_co_coherence(0);
 203
 204         /* Ensure the core can access the GCRs */
 205         access = read_gcr_access();
 206         access |= 1 << (CM_GCR_ACCESS_ACCESSEN_SHF + core);
 207         write_gcr_access(access);
 208
 209         if (mips_cpc_present()) {
 210                 /* Reset the core */
 211                 mips_cpc_lock_other(core);
 212                 write_cpc_co_cmd(CPC_Cx_CMD_RESET);
 213                 mips_cpc_unlock_other();
 214         } else {
 215                 /* Take the core out of reset */
 216                 write_gcr_co_reset_release(0);
 217         }
 218
 219         /* The core is now powered up */
 220         bitmap_set(core_power, core, 1);
 221 }
 222
 223 static void remote_vpe_boot(void *dummy)
 224 {
 225         mips_cps_boot_vpes();
 226 }
 227
 228 static void cps_boot_secondary(int cpu, struct task_struct *idle)
 229 {
 230         unsigned core = cpu_data[cpu].core;
 231         unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
 232         struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
 233         struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
 234         unsigned int remote;
 235         int err;
 236
 237         vpe_cfg->pc = (unsigned long)&smp_bootstrap;
 238         vpe_cfg->sp = __KSTK_TOS(idle);
 239         vpe_cfg->gp = (unsigned long)task_thread_info(idle);
 240
 241         atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);
 242
 243         preempt_disable();
 244
 245         if (!test_bit(core, core_power)) {
 246                 /* Boot a VPE on a powered down core */
 247                 boot_core(core);
 248                 goto out;
 249         }
 250
 251         if (core != current_cpu_data.core) {
 252                 /* Boot a VPE on another powered up core */
 253                 for (remote = 0; remote < NR_CPUS; remote++) {
 254                         if (cpu_data[remote].core != core)
 255                                 continue;
 256                         if (cpu_online(remote))
 257                                 break;
 258                 }
 259                 BUG_ON(remote >= NR_CPUS);
 260
 261                 err = smp_call_function_single(remote, remote_vpe_boot,
 262                                                NULL, 1);
 263                 if (err)
 264                         panic("Failed to call remote CPU\n");
 265                 goto out;
 266         }
 267
 268         BUG_ON(!cpu_has_mipsmt);
 269
 270         /* Boot a VPE on this core */
 271         mips_cps_boot_vpes();
 272 out:
 273         preempt_enable();
 274 }
 275
 276 static void cps_init_secondary(void)
 277 {
 278         /* Disable MT - we only want to run 1 TC per VPE */
 279         if (cpu_has_mipsmt)
 280                 dmt();
 281
 282         change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 |
 283                                  STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7);
 284 }
 285
 286 static void cps_smp_finish(void)
 287 {
 288         write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
 289
 290 #ifdef CONFIG_MIPS_MT_FPAFF
 291         /* If we have an FPU, enroll ourselves in the FPU-full mask */
 292         if (cpu_has_fpu)
 293                 cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
 294 #endif /* CONFIG_MIPS_MT_FPAFF */
 295
 296         local_irq_enable();
 297 }
 298
 299 #ifdef CONFIG_HOTPLUG_CPU
 300
 301 static int cps_cpu_disable(void)
 302 {
 303         unsigned cpu = smp_processor_id();
 304         struct core_boot_config *core_cfg;
 305
 306         if (!cpu)
 307                 return -EBUSY;
 308
 309         if (!cps_pm_support_state(CPS_PM_POWER_GATED))
 310                 return -EINVAL;
 311
 312         core_cfg = &mips_cps_core_bootcfg[current_cpu_data.core];
 313         atomic_sub(1 << cpu_vpe_id(&current_cpu_data), &core_cfg->vpe_mask);
 314         smp_mb__after_atomic();
 315         set_cpu_online(cpu, false);
 316         cpumask_clear_cpu(cpu, &cpu_callin_map);
 317
 318         return 0;
 319 }
 320
 321 static DECLARE_COMPLETION(cpu_death_chosen);
 322 static unsigned cpu_death_sibling;
 323 static enum {
 324         CPU_DEATH_HALT,
 325         CPU_DEATH_POWER,
 326 } cpu_death;
 327
 328 void play_dead(void)
 329 {
 330         unsigned cpu, core;
 331
 332         local_irq_disable();
 333         idle_task_exit();
 334         cpu = smp_processor_id();
 335         cpu_death = CPU_DEATH_POWER;
 336
 337         if (cpu_has_mipsmt) {
 338                 core = cpu_data[cpu].core;
 339
 340                 /* Look for another online VPE within the core */
 341                 for_each_online_cpu(cpu_death_sibling) {
 342                         if (cpu_data[cpu_death_sibling].core != core)
 343                                 continue;
 344
 345                         /*
 346                          * There is an online VPE within the core. Just halt
 347                          * this TC and leave the core alone.
 348                          */
 349                         cpu_death = CPU_DEATH_HALT;
 350                         break;
 351                 }
 352         }
 353
 354         /* This CPU has chosen its way out */
 355         complete(&cpu_death_chosen);
 356
 357         if (cpu_death == CPU_DEATH_HALT) {
 358                 /* Halt this TC */
 359                 write_c0_tchalt(TCHALT_H);
 360                 instruction_hazard();
 361         } else {
 362                 /* Power down the core */
 363                 cps_pm_enter_state(CPS_PM_POWER_GATED);
 364         }
 365
 366         /* This should never be reached */
 367         panic("Failed to offline CPU %u", cpu);
 368 }
 369
 370 static void wait_for_sibling_halt(void *ptr_cpu)
 371 {
 372         unsigned cpu = (unsigned long)ptr_cpu;
 373         unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
 374         unsigned halted;
 375         unsigned long flags;
 376
 377         do {
 378                 local_irq_save(flags);
 379                 settc(vpe_id);
 380                 halted = read_tc_c0_tchalt();
 381                 local_irq_restore(flags);
 382         } while (!(halted & TCHALT_H));
 383 }
 384
 385 static void cps_cpu_die(unsigned int cpu)
 386 {
 387         unsigned core = cpu_data[cpu].core;
 388         unsigned stat;
 389         int err;
 390
 391         /* Wait for the cpu to choose its way out */
 392         if (!wait_for_completion_timeout(&cpu_death_chosen,
 393                                          msecs_to_jiffies(5000))) {
 394                 pr_err("CPU%u: didn't offline\n", cpu);
 395                 return;
 396         }
 397
 398         /*
 399          * Now wait for the CPU to actually offline. Without doing this that
 400          * offlining may race with one or more of:
 401          *
 402          *   - Onlining the CPU again.
 403          *   - Powering down the core if another VPE within it is offlined.
 404          *   - A sibling VPE entering a non-coherent state.
 405          *
 406          * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing
 407          * with which we could race, so do nothing.
 408          */
 409         if (cpu_death == CPU_DEATH_POWER) {
 410                 /*
 411                  * Wait for the core to enter a powered down or clock gated
 412                  * state, the latter happening when a JTAG probe is connected
 413                  * in which case the CPC will refuse to power down the core.
 414                  */
 415                 do {
 416                         mips_cpc_lock_other(core);
 417                         stat = read_cpc_co_stat_conf();
 418                         stat &= CPC_Cx_STAT_CONF_SEQSTATE_MSK;
 419                         mips_cpc_unlock_other();
 420                 } while (stat != CPC_Cx_STAT_CONF_SEQSTATE_D0 &&
 421                          stat != CPC_Cx_STAT_CONF_SEQSTATE_D2 &&
 422                          stat != CPC_Cx_STAT_CONF_SEQSTATE_U2);
 423
 424                 /* Indicate the core is powered off */
 425                 bitmap_clear(core_power, core, 1);
 426         } else if (cpu_has_mipsmt) {
 427                 /*
 428                  * Have a CPU with access to the offlined CPUs registers wait
 429                  * for its TC to halt.
 430                  */
 431                 err = smp_call_function_single(cpu_death_sibling,
 432                                                wait_for_sibling_halt,
 433                                                (void *)(unsigned long)cpu, 1);
 434                 if (err)
 435                         panic("Failed to call remote sibling CPU\n");
 436         }
 437 }
 438
 439 #endif /* CONFIG_HOTPLUG_CPU */
 440
 441 static struct plat_smp_ops cps_smp_ops = {
 442         .smp_setup              = cps_smp_setup,
 443         .prepare_cpus           = cps_prepare_cpus,
 444         .boot_secondary         = cps_boot_secondary,
 445         .init_secondary         = cps_init_secondary,
 446         .smp_finish             = cps_smp_finish,
 447         .send_ipi_single        = gic_send_ipi_single,
 448         .send_ipi_mask          = gic_send_ipi_mask,
 449 #ifdef CONFIG_HOTPLUG_CPU
 450         .cpu_disable            = cps_cpu_disable,
 451         .cpu_die                = cps_cpu_die,
 452 #endif
 453 };
 454
 455 bool mips_cps_smp_in_use(void)
 456 {
 457         extern struct plat_smp_ops *mp_ops;
 458         return mp_ops == &cps_smp_ops;
 459 }
 460
 461 int register_cps_smp_ops(void)
 462 {
 463         if (!mips_cm_present()) {
 464                 pr_warn("MIPS CPS SMP unable to proceed without a CM\n");
 465                 return -ENODEV;
 466         }
 467
 468         /* check we have a GIC - we need one for IPIs */
 469         if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX_MSK)) {
 470                 pr_warn("MIPS CPS SMP unable to proceed without a GIC\n");
 471                 return -ENODEV;
 472         }
 473
 474         register_smp_ops(&cps_smp_ops);
 475         return 0;
 476 }