arch/mips/lantiq/xway/sysctrl.c

   1 /*
   2  *  This program is free software; you can redistribute it and/or modify it
   3  *  under the terms of the GNU General Public License version 2 as published
   4  *  by the Free Software Foundation.
   5  *
   6  *  Copyright (C) 2011-2012 John Crispin <blogic@openwrt.org>
   7  *  Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
   8  */
   9
  10 #include <linux/ioport.h>
  11 #include <linux/export.h>
  12 #include <linux/clkdev.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/of.h>
  15 #include <linux/of_platform.h>
  16 #include <linux/of_address.h>
  17
  18 #include <lantiq_soc.h>
  19
  20 #include "../clk.h"
  21 #include "../prom.h"
  22
  23 /* clock control register for legacy */
  24 #define CGU_IFCCR       0x0018
  25 #define CGU_IFCCR_VR9   0x0024
  26 /* system clock register for legacy */
  27 #define CGU_SYS         0x0010
  28 /* pci control register */
  29 #define CGU_PCICR       0x0034
  30 #define CGU_PCICR_VR9   0x0038
  31 /* ephy configuration register */
  32 #define CGU_EPHY        0x10
  33
  34 /* Legacy PMU register for ar9, ase, danube */
  35 /* power control register */
  36 #define PMU_PWDCR       0x1C
  37 /* power status register */
  38 #define PMU_PWDSR       0x20
  39 /* power control register */
  40 #define PMU_PWDCR1      0x24
  41 /* power status register */
  42 #define PMU_PWDSR1      0x28
  43 /* power control register */
  44 #define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR))
  45 /* power status register */
  46 #define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR))
  47
  48
  49 /* PMU register for ar10 and grx390 */
  50
  51 /* First register set */
  52 #define PMU_CLK_SR      0x20 /* status */
  53 #define PMU_CLK_CR_A    0x24 /* Enable */
  54 #define PMU_CLK_CR_B    0x28 /* Disable */
  55 /* Second register set */
  56 #define PMU_CLK_SR1     0x30 /* status */
  57 #define PMU_CLK_CR1_A   0x34 /* Enable */
  58 #define PMU_CLK_CR1_B   0x38 /* Disable */
  59 /* Third register set */
  60 #define PMU_ANA_SR      0x40 /* status */
  61 #define PMU_ANA_CR_A    0x44 /* Enable */
  62 #define PMU_ANA_CR_B    0x48 /* Disable */
  63
  64 /* Status */
  65 static u32 pmu_clk_sr[] = {
  66         PMU_CLK_SR,
  67         PMU_CLK_SR1,
  68         PMU_ANA_SR,
  69 };
  70
  71 /* Enable */
  72 static u32 pmu_clk_cr_a[] = {
  73         PMU_CLK_CR_A,
  74         PMU_CLK_CR1_A,
  75         PMU_ANA_CR_A,
  76 };
  77
  78 /* Disable */
  79 static u32 pmu_clk_cr_b[] = {
  80         PMU_CLK_CR_B,
  81         PMU_CLK_CR1_B,
  82         PMU_ANA_CR_B,
  83 };
  84
  85 #define PWDCR_EN_XRX(x)         (pmu_clk_cr_a[(x)])
  86 #define PWDCR_DIS_XRX(x)        (pmu_clk_cr_b[(x)])
  87 #define PWDSR_XRX(x)            (pmu_clk_sr[(x)])
  88
  89 /* clock gates that we can en/disable */
  90 #define PMU_USB0_P      BIT(0)
  91 #define PMU_ASE_SDIO    BIT(2) /* ASE special */
  92 #define PMU_PCI         BIT(4)
  93 #define PMU_DMA         BIT(5)
  94 #define PMU_USB0        BIT(6)
  95 #define PMU_ASC0        BIT(7)
  96 #define PMU_EPHY        BIT(7)  /* ase */
  97 #define PMU_USIF        BIT(7) /* from vr9 until grx390 */
  98 #define PMU_SPI         BIT(8)
  99 #define PMU_DFE         BIT(9)
 100 #define PMU_EBU         BIT(10)
 101 #define PMU_STP         BIT(11)
 102 #define PMU_GPT         BIT(12)
 103 #define PMU_AHBS        BIT(13) /* vr9 */
 104 #define PMU_FPI         BIT(14)
 105 #define PMU_AHBM        BIT(15)
 106 #define PMU_SDIO        BIT(16) /* danube, ar9, vr9 */
 107 #define PMU_ASC1        BIT(17)
 108 #define PMU_PPE_QSB     BIT(18)
 109 #define PMU_PPE_SLL01   BIT(19)
 110 #define PMU_DEU         BIT(20)
 111 #define PMU_PPE_TC      BIT(21)
 112 #define PMU_PPE_EMA     BIT(22)
 113 #define PMU_PPE_DPLUM   BIT(23)
 114 #define PMU_PPE_DP      BIT(23)
 115 #define PMU_PPE_DPLUS   BIT(24)
 116 #define PMU_USB1_P      BIT(26)
 117 #define PMU_USB1        BIT(27)
 118 #define PMU_SWITCH      BIT(28)
 119 #define PMU_PPE_TOP     BIT(29)
 120 #define PMU_GPHY        BIT(30)
 121 #define PMU_PCIE_CLK    BIT(31)
 122
 123 #define PMU1_PCIE_PHY   BIT(0)  /* vr9-specific,moved in ar10/grx390 */
 124 #define PMU1_PCIE_CTL   BIT(1)
 125 #define PMU1_PCIE_PDI   BIT(4)
 126 #define PMU1_PCIE_MSI   BIT(5)
 127 #define PMU1_CKE        BIT(6)
 128 #define PMU1_PCIE1_CTL  BIT(17)
 129 #define PMU1_PCIE1_PDI  BIT(20)
 130 #define PMU1_PCIE1_MSI  BIT(21)
 131 #define PMU1_PCIE2_CTL  BIT(25)
 132 #define PMU1_PCIE2_PDI  BIT(26)
 133 #define PMU1_PCIE2_MSI  BIT(27)
 134
 135 #define PMU_ANALOG_USB0_P       BIT(0)
 136 #define PMU_ANALOG_USB1_P       BIT(1)
 137 #define PMU_ANALOG_PCIE0_P      BIT(8)
 138 #define PMU_ANALOG_PCIE1_P      BIT(9)
 139 #define PMU_ANALOG_PCIE2_P      BIT(10)
 140 #define PMU_ANALOG_DSL_AFE      BIT(16)
 141 #define PMU_ANALOG_DCDC_2V5     BIT(17)
 142 #define PMU_ANALOG_DCDC_1VX     BIT(18)
 143 #define PMU_ANALOG_DCDC_1V0     BIT(19)
 144
 145 #define pmu_w32(x, y)   ltq_w32((x), pmu_membase + (y))
 146 #define pmu_r32(x)      ltq_r32(pmu_membase + (x))
 147
 148 static void __iomem *pmu_membase;
 149 void __iomem *ltq_cgu_membase;
 150 void __iomem *ltq_ebu_membase;
 151
 152 static u32 ifccr = CGU_IFCCR;
 153 static u32 pcicr = CGU_PCICR;
 154
 155 static DEFINE_SPINLOCK(g_pmu_lock);
 156
 157 /* legacy function kept alive to ease clkdev transition */
 158 void ltq_pmu_enable(unsigned int module)
 159 {
 160         int retry = 1000000;
 161
 162         spin_lock(&g_pmu_lock);
 163         pmu_w32(pmu_r32(PMU_PWDCR) & ~module, PMU_PWDCR);
 164         do {} while (--retry && (pmu_r32(PMU_PWDSR) & module));
 165         spin_unlock(&g_pmu_lock);
 166
 167         if (!retry)
 168                 panic("activating PMU module failed!");
 169 }
 170 EXPORT_SYMBOL(ltq_pmu_enable);
 171
 172 /* legacy function kept alive to ease clkdev transition */
 173 void ltq_pmu_disable(unsigned int module)
 174 {
 175         int retry = 1000000;
 176
 177         spin_lock(&g_pmu_lock);
 178         pmu_w32(pmu_r32(PMU_PWDCR) | module, PMU_PWDCR);
 179         do {} while (--retry && (!(pmu_r32(PMU_PWDSR) & module)));
 180         spin_unlock(&g_pmu_lock);
 181
 182         if (!retry)
 183                 pr_warn("deactivating PMU module failed!");
 184 }
 185 EXPORT_SYMBOL(ltq_pmu_disable);
 186
 187 /* enable a hw clock */
 188 static int cgu_enable(struct clk *clk)
 189 {
 190         ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr);
 191         return 0;
 192 }
 193
 194 /* disable a hw clock */
 195 static void cgu_disable(struct clk *clk)
 196 {
 197         ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr);
 198 }
 199
 200 /* enable a clock gate */
 201 static int pmu_enable(struct clk *clk)
 202 {
 203         int retry = 1000000;
 204
 205         if (of_machine_is_compatible("lantiq,ar10")
 206             || of_machine_is_compatible("lantiq,grx390")) {
 207                 pmu_w32(clk->bits, PWDCR_EN_XRX(clk->module));
 208                 do {} while (--retry &&
 209                              (!(pmu_r32(PWDSR_XRX(clk->module)) & clk->bits)));
 210
 211         } else {
 212                 spin_lock(&g_pmu_lock);
 213                 pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits,
 214                                 PWDCR(clk->module));
 215                 do {} while (--retry &&
 216                              (pmu_r32(PWDSR(clk->module)) & clk->bits));
 217                 spin_unlock(&g_pmu_lock);
 218         }
 219
 220         if (!retry)
 221                 panic("activating PMU module failed!");
 222
 223         return 0;
 224 }
 225
 226 /* disable a clock gate */
 227 static void pmu_disable(struct clk *clk)
 228 {
 229         int retry = 1000000;
 230
 231         if (of_machine_is_compatible("lantiq,ar10")
 232             || of_machine_is_compatible("lantiq,grx390")) {
 233                 pmu_w32(clk->bits, PWDCR_DIS_XRX(clk->module));
 234                 do {} while (--retry &&
 235                              (pmu_r32(PWDSR_XRX(clk->module)) & clk->bits));
 236         } else {
 237                 spin_lock(&g_pmu_lock);
 238                 pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits,
 239                                 PWDCR(clk->module));
 240                 do {} while (--retry &&
 241                              (!(pmu_r32(PWDSR(clk->module)) & clk->bits)));
 242                 spin_unlock(&g_pmu_lock);
 243         }
 244
 245         if (!retry)
 246                 pr_warn("deactivating PMU module failed!");
 247 }
 248
 249 /* the pci enable helper */
 250 static int pci_enable(struct clk *clk)
 251 {
 252         unsigned int val = ltq_cgu_r32(ifccr);
 253         /* set bus clock speed */
 254         if (of_machine_is_compatible("lantiq,ar9") ||
 255                         of_machine_is_compatible("lantiq,vr9")) {
 256                 val &= ~0x1f00000;
 257                 if (clk->rate == CLOCK_33M)
 258                         val |= 0xe00000;
 259                 else
 260                         val |= 0x700000; /* 62.5M */
 261         } else {
 262                 val &= ~0xf00000;
 263                 if (clk->rate == CLOCK_33M)
 264                         val |= 0x800000;
 265                 else
 266                         val |= 0x400000; /* 62.5M */
 267         }
 268         ltq_cgu_w32(val, ifccr);
 269         pmu_enable(clk);
 270         return 0;
 271 }
 272
 273 /* enable the external clock as a source */
 274 static int pci_ext_enable(struct clk *clk)
 275 {
 276         ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~(1 << 16), ifccr);
 277         ltq_cgu_w32((1 << 30), pcicr);
 278         return 0;
 279 }
 280
 281 /* disable the external clock as a source */
 282 static void pci_ext_disable(struct clk *clk)
 283 {
 284         ltq_cgu_w32(ltq_cgu_r32(ifccr) | (1 << 16), ifccr);
 285         ltq_cgu_w32((1 << 31) | (1 << 30), pcicr);
 286 }
 287
 288 /* enable a clockout source */
 289 static int clkout_enable(struct clk *clk)
 290 {
 291         int i;
 292
 293         /* get the correct rate */
 294         for (i = 0; i < 4; i++) {
 295                 if (clk->rates[i] == clk->rate) {
 296                         int shift = 14 - (2 * clk->module);
 297                         int enable = 7 - clk->module;
 298                         unsigned int val = ltq_cgu_r32(ifccr);
 299
 300                         val &= ~(3 << shift);
 301                         val |= i << shift;
 302                         val |= enable;
 303                         ltq_cgu_w32(val, ifccr);
 304                         return 0;
 305                 }
 306         }
 307         return -1;
 308 }
 309
 310 /* manage the clock gates via PMU */
 311 static void clkdev_add_pmu(const char *dev, const char *con, bool deactivate,
 312                            unsigned int module, unsigned int bits)
 313 {
 314         struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 315
 316         clk->cl.dev_id = dev;
 317         clk->cl.con_id = con;
 318         clk->cl.clk = clk;
 319         clk->enable = pmu_enable;
 320         clk->disable = pmu_disable;
 321         clk->module = module;
 322         clk->bits = bits;
 323         if (deactivate) {
 324                 /*
 325                  * Disable it during the initialization. Module should enable
 326                  * when used
 327                  */
 328                 pmu_disable(clk);
 329         }
 330         clkdev_add(&clk->cl);
 331 }
 332
 333 /* manage the clock generator */
 334 static void clkdev_add_cgu(const char *dev, const char *con,
 335                                         unsigned int bits)
 336 {
 337         struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 338
 339         clk->cl.dev_id = dev;
 340         clk->cl.con_id = con;
 341         clk->cl.clk = clk;
 342         clk->enable = cgu_enable;
 343         clk->disable = cgu_disable;
 344         clk->bits = bits;
 345         clkdev_add(&clk->cl);
 346 }
 347
 348 /* pci needs its own enable function as the setup is a bit more complex */
 349 static unsigned long valid_pci_rates[] = {CLOCK_33M, CLOCK_62_5M, 0};
 350
 351 static void clkdev_add_pci(void)
 352 {
 353         struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 354         struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL);
 355
 356         /* main pci clock */
 357         clk->cl.dev_id = "17000000.pci";
 358         clk->cl.con_id = NULL;
 359         clk->cl.clk = clk;
 360         clk->rate = CLOCK_33M;
 361         clk->rates = valid_pci_rates;
 362         clk->enable = pci_enable;
 363         clk->disable = pmu_disable;
 364         clk->module = 0;
 365         clk->bits = PMU_PCI;
 366         clkdev_add(&clk->cl);
 367
 368         /* use internal/external bus clock */
 369         clk_ext->cl.dev_id = "17000000.pci";
 370         clk_ext->cl.con_id = "external";
 371         clk_ext->cl.clk = clk_ext;
 372         clk_ext->enable = pci_ext_enable;
 373         clk_ext->disable = pci_ext_disable;
 374         clkdev_add(&clk_ext->cl);
 375 }
 376
 377 /* xway socs can generate clocks on gpio pins */
 378 static unsigned long valid_clkout_rates[4][5] = {
 379         {CLOCK_32_768K, CLOCK_1_536M, CLOCK_2_5M, CLOCK_12M, 0},
 380         {CLOCK_40M, CLOCK_12M, CLOCK_24M, CLOCK_48M, 0},
 381         {CLOCK_25M, CLOCK_40M, CLOCK_30M, CLOCK_60M, 0},
 382         {CLOCK_12M, CLOCK_50M, CLOCK_32_768K, CLOCK_25M, 0},
 383 };
 384
 385 static void clkdev_add_clkout(void)
 386 {
 387         int i;
 388
 389         for (i = 0; i < 4; i++) {
 390                 struct clk *clk;
 391                 char *name;
 392
 393                 name = kzalloc(sizeof("clkout0"), GFP_KERNEL);
 394                 sprintf(name, "clkout%d", i);
 395
 396                 clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 397                 clk->cl.dev_id = "1f103000.cgu";
 398                 clk->cl.con_id = name;
 399                 clk->cl.clk = clk;
 400                 clk->rate = 0;
 401                 clk->rates = valid_clkout_rates[i];
 402                 clk->enable = clkout_enable;
 403                 clk->module = i;
 404                 clkdev_add(&clk->cl);
 405         }
 406 }
 407
 408 /* bring up all register ranges that we need for basic system control */
 409 void __init ltq_soc_init(void)
 410 {
 411         struct resource res_pmu, res_cgu, res_ebu;
 412         struct device_node *np_pmu =
 413                         of_find_compatible_node(NULL, NULL, "lantiq,pmu-xway");
 414         struct device_node *np_cgu =
 415                         of_find_compatible_node(NULL, NULL, "lantiq,cgu-xway");
 416         struct device_node *np_ebu =
 417                         of_find_compatible_node(NULL, NULL, "lantiq,ebu-xway");
 418
 419         /* check if all the core register ranges are available */
 420         if (!np_pmu || !np_cgu || !np_ebu)
 421                 panic("Failed to load core nodes from devicetree");
 422
 423         if (of_address_to_resource(np_pmu, 0, &res_pmu) ||
 424                         of_address_to_resource(np_cgu, 0, &res_cgu) ||
 425                         of_address_to_resource(np_ebu, 0, &res_ebu))
 426                 panic("Failed to get core resources");
 427
 428         if (!request_mem_region(res_pmu.start, resource_size(&res_pmu),
 429                                 res_pmu.name) ||
 430                 !request_mem_region(res_cgu.start, resource_size(&res_cgu),
 431                                 res_cgu.name) ||
 432                 !request_mem_region(res_ebu.start, resource_size(&res_ebu),
 433                                 res_ebu.name))
 434                 pr_err("Failed to request core resources");
 435
 436         pmu_membase = ioremap_nocache(res_pmu.start, resource_size(&res_pmu));
 437         ltq_cgu_membase = ioremap_nocache(res_cgu.start,
 438                                                 resource_size(&res_cgu));
 439         ltq_ebu_membase = ioremap_nocache(res_ebu.start,
 440                                                 resource_size(&res_ebu));
 441         if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase)
 442                 panic("Failed to remap core resources");
 443
 444         /* make sure to unprotect the memory region where flash is located */
 445         ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
 446
 447         /* add our generic xway clocks */
 448         clkdev_add_pmu("10000000.fpi", NULL, 0, 0, PMU_FPI);
 449         clkdev_add_pmu("1e100400.serial", NULL, 0, 0, PMU_ASC0);
 450         clkdev_add_pmu("1e100a00.gptu", NULL, 1, 0, PMU_GPT);
 451         clkdev_add_pmu("1e100bb0.stp", NULL, 1, 0, PMU_STP);
 452         clkdev_add_pmu("1e104100.dma", NULL, 1, 0, PMU_DMA);
 453         clkdev_add_pmu("1e100800.spi", NULL, 1, 0, PMU_SPI);
 454         clkdev_add_pmu("1e105300.ebu", NULL, 0, 0, PMU_EBU);
 455         clkdev_add_clkout();
 456
 457         /* add the soc dependent clocks */
 458         if (of_machine_is_compatible("lantiq,vr9")) {
 459                 ifccr = CGU_IFCCR_VR9;
 460                 pcicr = CGU_PCICR_VR9;
 461         } else {
 462                 clkdev_add_pmu("1e180000.etop", NULL, 1, 0, PMU_PPE);
 463         }
 464
 465         if (!of_machine_is_compatible("lantiq,ase")) {
 466                 clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
 467                 clkdev_add_pci();
 468         }
 469
 470         if (of_machine_is_compatible("lantiq,grx390") ||
 471             of_machine_is_compatible("lantiq,ar10")) {
 472                 clkdev_add_pmu("1e101000.usb", "phy", 1, 2, PMU_ANALOG_USB0_P);
 473                 clkdev_add_pmu("1e106000.usb", "phy", 1, 2, PMU_ANALOG_USB1_P);
 474                 /* rc 0 */
 475                 clkdev_add_pmu("1d900000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE0_P);
 476                 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
 477                 clkdev_add_pmu("1d900000.pcie", "pdi", 1, 1, PMU1_PCIE_PDI);
 478                 clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL);
 479                 /* rc 1 */
 480                 clkdev_add_pmu("19000000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE1_P);
 481                 clkdev_add_pmu("19000000.pcie", "msi", 1, 1, PMU1_PCIE1_MSI);
 482                 clkdev_add_pmu("19000000.pcie", "pdi", 1, 1, PMU1_PCIE1_PDI);
 483                 clkdev_add_pmu("19000000.pcie", "ctl", 1, 1, PMU1_PCIE1_CTL);
 484         }
 485
 486         if (of_machine_is_compatible("lantiq,ase")) {
 487                 if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
 488                         clkdev_add_static(CLOCK_266M, CLOCK_133M,
 489                                                 CLOCK_133M, CLOCK_266M);
 490                 else
 491                         clkdev_add_static(CLOCK_133M, CLOCK_133M,
 492                                                 CLOCK_133M, CLOCK_133M);
 493                 clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
 494                 clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
 495                 clkdev_add_pmu("1e180000.etop", "ppe", 1, 0, PMU_PPE);
 496                 clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY);
 497                 clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY);
 498                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_ASE_SDIO);
 499                 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
 500         } else if (of_machine_is_compatible("lantiq,grx390")) {
 501                 clkdev_add_static(ltq_grx390_cpu_hz(), ltq_grx390_fpi_hz(),
 502                                   ltq_grx390_fpi_hz(), ltq_grx390_pp32_hz());
 503                 clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
 504                 clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
 505                 /* rc 2 */
 506                 clkdev_add_pmu("1a800000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE2_P);
 507                 clkdev_add_pmu("1a800000.pcie", "msi", 1, 1, PMU1_PCIE2_MSI);
 508                 clkdev_add_pmu("1a800000.pcie", "pdi", 1, 1, PMU1_PCIE2_PDI);
 509                 clkdev_add_pmu("1a800000.pcie", "ctl", 1, 1, PMU1_PCIE2_CTL);
 510                 clkdev_add_pmu("1e108000.eth", NULL, 1, 0, PMU_SWITCH | PMU_PPE_DP);
 511                 clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
 512                 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
 513         } else if (of_machine_is_compatible("lantiq,ar10")) {
 514                 clkdev_add_static(ltq_ar10_cpu_hz(), ltq_ar10_fpi_hz(),
 515                                   ltq_ar10_fpi_hz(), ltq_ar10_pp32_hz());
 516                 clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
 517                 clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
 518                 clkdev_add_pmu("1e108000.eth", NULL, 1, 0, PMU_SWITCH |
 519                                PMU_PPE_DP | PMU_PPE_TC);
 520                 clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
 521                 clkdev_add_pmu("1f203000.rcu", "gphy", 1, 0, PMU_GPHY);
 522                 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
 523                 clkdev_add_pmu("1e116000.mei", "afe", 1, 2, PMU_ANALOG_DSL_AFE);
 524                 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
 525         } else if (of_machine_is_compatible("lantiq,vr9")) {
 526                 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
 527                                 ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
 528                 clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
 529                 clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0 | PMU_AHBM);
 530                 clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
 531                 clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1 | PMU_AHBM);
 532                 clkdev_add_pmu("1d900000.pcie", "phy", 1, 1, PMU1_PCIE_PHY);
 533                 clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK);
 534                 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
 535                 clkdev_add_pmu("1d900000.pcie", "pdi", 1, 1, PMU1_PCIE_PDI);
 536                 clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL);
 537                 clkdev_add_pmu(NULL, "ahb", 1, 0, PMU_AHBM | PMU_AHBS);
 538
 539                 clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
 540                 clkdev_add_pmu("1e108000.eth", NULL, 1, 0,
 541                                 PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
 542                                 PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
 543                                 PMU_PPE_QSB | PMU_PPE_TOP);
 544                 clkdev_add_pmu("1f203000.rcu", "gphy", 1, 0, PMU_GPHY);
 545                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
 546                 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
 547                 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
 548         } else if (of_machine_is_compatible("lantiq,ar9")) {
 549                 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
 550                                 ltq_ar9_fpi_hz(), CLOCK_250M);
 551                 clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
 552                 clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
 553                 clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
 554                 clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
 555                 clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);
 556                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
 557                 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
 558                 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
 559                 clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
 560         } else {
 561                 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
 562                                 ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
 563                 clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
 564                 clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
 565                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
 566                 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
 567                 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
 568                 clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
 569         }
 570 }