arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi

   1 /*
   2  * P5040 Silicon/SoC Device Tree Source (pre include)
   3  *
   4  * Copyright 2012 - 2015 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * This software is provided by Freescale Semiconductor "as is" and any
  24  * express or implied warranties, including, but not limited to, the implied
  25  * warranties of merchantability and fitness for a particular purpose are
  26  * disclaimed. In no event shall Freescale Semiconductor be liable for any
  27  * direct, indirect, incidental, special, exemplary, or consequential damages
  28  * (including, but not limited to, procurement of substitute goods or services;
  29  * loss of use, data, or profits; or business interruption) however caused and
  30  * on any theory of liability, whether in contract, strict liability, or tort
  31  * (including negligence or otherwise) arising in any way out of the use of this
  32  * software, even if advised of the possibility of such damage.
  33  */
  34
  35 /dts-v1/;
  36
  37 /include/ "e5500_power_isa.dtsi"
  38
  39 / {
  40         compatible = "fsl,P5040";
  41         #address-cells = <2>;
  42         #size-cells = <2>;
  43         interrupt-parent = <&mpic>;
  44
  45         aliases {
  46                 ccsr = &soc;
  47                 dcsr = &dcsr;
  48
  49                 serial0 = &serial0;
  50                 serial1 = &serial1;
  51                 serial2 = &serial2;
  52                 serial3 = &serial3;
  53                 pci0 = &pci0;
  54                 pci1 = &pci1;
  55                 pci2 = &pci2;
  56                 usb0 = &usb0;
  57                 usb1 = &usb1;
  58                 dma0 = &dma0;
  59                 dma1 = &dma1;
  60                 sdhc = &sdhc;
  61                 msi0 = &msi0;
  62                 msi1 = &msi1;
  63                 msi2 = &msi2;
  64
  65                 crypto = &crypto;
  66                 sec_jr0 = &sec_jr0;
  67                 sec_jr1 = &sec_jr1;
  68                 sec_jr2 = &sec_jr2;
  69                 sec_jr3 = &sec_jr3;
  70                 rtic_a = &rtic_a;
  71                 rtic_b = &rtic_b;
  72                 rtic_c = &rtic_c;
  73                 rtic_d = &rtic_d;
  74                 sec_mon = &sec_mon;
  75
  76                 fman0 = &fman0;
  77                 fman1 = &fman1;
  78                 ethernet0 = &enet0;
  79                 ethernet1 = &enet1;
  80                 ethernet2 = &enet2;
  81                 ethernet3 = &enet3;
  82                 ethernet4 = &enet4;
  83                 ethernet5 = &enet5;
  84                 ethernet6 = &enet6;
  85                 ethernet7 = &enet7;
  86                 ethernet8 = &enet8;
  87                 ethernet9 = &enet9;
  88                 ethernet10 = &enet10;
  89                 ethernet11 = &enet11;
  90         };
  91
  92         cpus {
  93                 #address-cells = <1>;
  94                 #size-cells = <0>;
  95
  96                 cpu0: PowerPC,e5500@0 {
  97                         device_type = "cpu";
  98                         reg = <0>;
  99                         clocks = <&mux0>;
 100                         next-level-cache = <&L2_0>;
 101                         fsl,portid-mapping = <0x80000000>;
 102                         L2_0: l2-cache {
 103                                 next-level-cache = <&cpc>;
 104                         };
 105                 };
 106                 cpu1: PowerPC,e5500@1 {
 107                         device_type = "cpu";
 108                         reg = <1>;
 109                         clocks = <&mux1>;
 110                         next-level-cache = <&L2_1>;
 111                         fsl,portid-mapping = <0x40000000>;
 112                         L2_1: l2-cache {
 113                                 next-level-cache = <&cpc>;
 114                         };
 115                 };
 116                 cpu2: PowerPC,e5500@2 {
 117                         device_type = "cpu";
 118                         reg = <2>;
 119                         clocks = <&mux2>;
 120                         next-level-cache = <&L2_2>;
 121                         fsl,portid-mapping = <0x20000000>;
 122                         L2_2: l2-cache {
 123                                 next-level-cache = <&cpc>;
 124                         };
 125                 };
 126                 cpu3: PowerPC,e5500@3 {
 127                         device_type = "cpu";
 128                         reg = <3>;
 129                         clocks = <&mux3>;
 130                         next-level-cache = <&L2_3>;
 131                         fsl,portid-mapping = <0x10000000>;
 132                         L2_3: l2-cache {
 133                                 next-level-cache = <&cpc>;
 134                         };
 135                 };
 136         };
 137 };