arch/powerpc/boot/dts/kmcoge4.dts

   1 /*
   2  * Keymile kmcoge4 Device Tree Source, based on the P2041RDB DTS
   3  *
   4  * (C) Copyright 2014
   5  * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
   6  *
   7  * Copyright 2011 Freescale Semiconductor Inc.
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  */
  14
  15 /include/ "fsl/p2041si-pre.dtsi"
  16
  17 / {
  18         model = "keymile,kmcoge4";
  19         compatible = "keymile,kmcoge4", "keymile,kmp204x";
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22         interrupt-parent = <&mpic>;
  23
  24         memory {
  25                 device_type = "memory";
  26         };
  27
  28         reserved-memory {
  29                 #address-cells = <2>;
  30                 #size-cells = <2>;
  31                 ranges;
  32
  33                 bman_fbpr: bman-fbpr {
  34                         size = <0 0x1000000>;
  35                         alignment = <0 0x1000000>;
  36                 };
  37                 qman_fqd: qman-fqd {
  38                         size = <0 0x400000>;
  39                         alignment = <0 0x400000>;
  40                 };
  41                 qman_pfdr: qman-pfdr {
  42                         size = <0 0x2000000>;
  43                         alignment = <0 0x2000000>;
  44                 };
  45         };
  46
  47         dcsr: dcsr@f00000000 {
  48                 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
  49         };
  50
  51         bportals: bman-portals@ff4000000 {
  52                 ranges = <0x0 0xf 0xf4000000 0x200000>;
  53         };
  54
  55         qportals: qman-portals@ff4200000 {
  56                 ranges = <0x0 0xf 0xf4200000 0x200000>;
  57         };
  58
  59         soc: soc@ffe000000 {
  60                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  61                 reg = <0xf 0xfe000000 0 0x00001000>;
  62                 spi@110000 {
  63                         flash@0 {
  64                                 #address-cells = <1>;
  65                                 #size-cells = <1>;
  66                                 compatible = "spansion,s25fl256s1";
  67                                 reg = <0>;
  68                                 spi-max-frequency = <20000000>; /* input clock */
  69                         };
  70
  71                         network_clock@1 {
  72                                 compatible = "zarlink,zl30343";
  73                                 reg = <1>;
  74                                 spi-max-frequency = <8000000>;
  75                         };
  76
  77                         flash@2 {
  78                                 #address-cells = <1>;
  79                                 #size-cells = <1>;
  80                                 compatible = "micron,m25p32";
  81                                 reg = <2>;
  82                                 spi-max-frequency = <15000000>;
  83                         };
  84                 };
  85
  86                 i2c@119000 {
  87                         status = "disabled";
  88                 };
  89
  90                 i2c@119100 {
  91                         status = "disabled";
  92                 };
  93
  94                 usb0: usb@210000 {
  95                         status = "disabled";
  96                 };
  97
  98                 usb1: usb@211000 {
  99                         status = "disabled";
 100                 };
 101
 102                 sata@220000 {
 103                         status = "disabled";
 104                 };
 105
 106                 sata@221000 {
 107                         status = "disabled";
 108                 };
 109         };
 110
 111         rio: rapidio@ffe0c0000 {
 112                 status = "disabled";
 113         };
 114
 115         lbc: localbus@ffe124000 {
 116                 reg = <0xf 0xfe124000 0 0x1000>;
 117                 ranges = <0 0 0xf 0xffa00000 0x00040000         /* LB 0 */
 118                           1 0 0xf 0xfb000000 0x00010000         /* LB 1 */
 119                           2 0 0xf 0xd0000000 0x10000000         /* LB 2 */
 120                           3 0 0xf 0xe0000000 0x10000000>;       /* LB 3 */
 121
 122                 nand@0,0 {
 123                         #address-cells = <1>;
 124                         #size-cells = <1>;
 125                         compatible = "fsl,elbc-fcm-nand";
 126                         reg = <0 0 0x40000>;
 127                 };
 128
 129                 board-control@1,0 {
 130                         compatible = "keymile,qriox";
 131                         reg = <1 0 0x80>;
 132                 };
 133
 134                 chassis-mgmt@3,0 {
 135                         compatible = "keymile,bfticu";
 136                         interrupt-controller;
 137                         #interrupt-cells = <2>;
 138                         reg = <3 0 0x100>;
 139                         interrupt-parent = <&mpic>;
 140                         interrupts = <6 1 0 0>;
 141                 };
 142         };
 143
 144         pci0: pcie@ffe200000 {
 145                 reg = <0xf 0xfe200000 0 0x1000>;
 146                 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
 147                           0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
 148                 pcie@0 {
 149                         ranges = <0x02000000 0 0xe0000000
 150                                   0x02000000 0 0xe0000000
 151                                   0 0x20000000
 152
 153                                   0x01000000 0 0x00000000
 154                                   0x01000000 0 0x00000000
 155                                   0 0x00010000>;
 156                 };
 157         };
 158
 159         pci1: pcie@ffe201000 {
 160                 status = "disabled";
 161         };
 162
 163         pci2: pcie@ffe202000 {
 164                 reg = <0xf 0xfe202000 0 0x1000>;
 165                 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000
 166                           0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>;
 167                 pcie@0 {
 168                         ranges = <0x02000000 0 0xe0000000
 169                                   0x02000000 0 0xe0000000
 170                                   0 0x20000000
 171
 172                                   0x01000000 0 0x00000000
 173                                   0x01000000 0 0x00000000
 174                                   0 0x00010000>;
 175                 };
 176         };
 177 };
 178
 179 /include/ "fsl/p2041si-post.dtsi"