2 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
3 * Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
6 * Architecture- / platform-specific boot-time initialization code for
7 * the IBM iSeries LPAR. Adapted from original code by Grant Erickson and
8 * code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
19 #include <linux/config.h>
20 #include <linux/init.h>
21 #include <linux/threads.h>
22 #include <linux/smp.h>
23 #include <linux/param.h>
24 #include <linux/string.h>
25 #include <linux/initrd.h>
26 #include <linux/seq_file.h>
27 #include <linux/kdev_t.h>
28 #include <linux/major.h>
29 #include <linux/root_dev.h>
30 #include <linux/kernel.h>
32 #include <asm/processor.h>
33 #include <asm/machdep.h>
36 #include <asm/pgtable.h>
37 #include <asm/mmu_context.h>
38 #include <asm/cputable.h>
39 #include <asm/sections.h>
40 #include <asm/iommu.h>
41 #include <asm/firmware.h>
42 #include <asm/systemcfg.h>
43 #include <asm/system.h>
46 #include <asm/cache.h>
47 #include <asm/sections.h>
48 #include <asm/abs_addr.h>
49 #include <asm/iseries/hv_lp_config.h>
50 #include <asm/iseries/hv_call_event.h>
51 #include <asm/iseries/hv_call_xm.h>
52 #include <asm/iseries/it_lp_queue.h>
53 #include <asm/iseries/mf.h>
54 #include <asm/iseries/hv_lp_event.h>
55 #include <asm/iseries/lpar_map.h>
60 #include "vpd_areas.h"
61 #include "processor_vpd.h"
62 #include "main_store.h"
66 extern void hvlog(char *fmt, ...);
69 #define DBG(fmt...) hvlog(fmt)
74 /* Function Prototypes */
75 static unsigned long build_iSeries_Memory_Map(void);
76 static void iseries_shared_idle(void);
77 static void iseries_dedicated_idle(void);
79 extern void iSeries_pci_final_fixup(void);
81 static void iSeries_pci_final_fixup(void) { }
84 /* Global Variables */
85 int piranha_simulator;
87 extern int rd_size; /* Defined in drivers/block/rd.c */
88 extern unsigned long embedded_sysmap_start;
89 extern unsigned long embedded_sysmap_end;
91 extern unsigned long iSeries_recal_tb;
92 extern unsigned long iSeries_recal_titan;
94 static int mf_initialized;
96 static unsigned long cmd_mem_limit;
99 unsigned long absStart;
100 unsigned long absEnd;
101 unsigned long logicalStart;
102 unsigned long logicalEnd;
106 * Process the main store vpd to determine where the holes in memory are
107 * and return the number of physical blocks and fill in the array of
110 static unsigned long iSeries_process_Condor_mainstore_vpd(
111 struct MemoryBlock *mb_array, unsigned long max_entries)
113 unsigned long holeFirstChunk, holeSizeChunks;
114 unsigned long numMemoryBlocks = 1;
115 struct IoHriMainStoreSegment4 *msVpd =
116 (struct IoHriMainStoreSegment4 *)xMsVpd;
117 unsigned long holeStart = msVpd->nonInterleavedBlocksStartAdr;
118 unsigned long holeEnd = msVpd->nonInterleavedBlocksEndAdr;
119 unsigned long holeSize = holeEnd - holeStart;
121 printk("Mainstore_VPD: Condor\n");
123 * Determine if absolute memory has any
124 * holes so that we can interpret the
125 * access map we get back from the hypervisor
128 mb_array[0].logicalStart = 0;
129 mb_array[0].logicalEnd = 0x100000000;
130 mb_array[0].absStart = 0;
131 mb_array[0].absEnd = 0x100000000;
135 holeStart = holeStart & 0x000fffffffffffff;
136 holeStart = addr_to_chunk(holeStart);
137 holeFirstChunk = holeStart;
138 holeSize = addr_to_chunk(holeSize);
139 holeSizeChunks = holeSize;
140 printk( "Main store hole: start chunk = %0lx, size = %0lx chunks\n",
141 holeFirstChunk, holeSizeChunks );
142 mb_array[0].logicalEnd = holeFirstChunk;
143 mb_array[0].absEnd = holeFirstChunk;
144 mb_array[1].logicalStart = holeFirstChunk;
145 mb_array[1].logicalEnd = 0x100000000 - holeSizeChunks;
146 mb_array[1].absStart = holeFirstChunk + holeSizeChunks;
147 mb_array[1].absEnd = 0x100000000;
149 return numMemoryBlocks;
152 #define MaxSegmentAreas 32
153 #define MaxSegmentAdrRangeBlocks 128
154 #define MaxAreaRangeBlocks 4
156 static unsigned long iSeries_process_Regatta_mainstore_vpd(
157 struct MemoryBlock *mb_array, unsigned long max_entries)
159 struct IoHriMainStoreSegment5 *msVpdP =
160 (struct IoHriMainStoreSegment5 *)xMsVpd;
161 unsigned long numSegmentBlocks = 0;
162 u32 existsBits = msVpdP->msAreaExists;
163 unsigned long area_num;
165 printk("Mainstore_VPD: Regatta\n");
167 for (area_num = 0; area_num < MaxSegmentAreas; ++area_num ) {
168 unsigned long numAreaBlocks;
169 struct IoHriMainStoreArea4 *currentArea;
171 if (existsBits & 0x80000000) {
172 unsigned long block_num;
174 currentArea = &msVpdP->msAreaArray[area_num];
175 numAreaBlocks = currentArea->numAdrRangeBlocks;
176 printk("ms_vpd: processing area %2ld blocks=%ld",
177 area_num, numAreaBlocks);
178 for (block_num = 0; block_num < numAreaBlocks;
180 /* Process an address range block */
181 struct MemoryBlock tempBlock;
185 (unsigned long)currentArea->xAdrRangeBlock[block_num].blockStart;
187 (unsigned long)currentArea->xAdrRangeBlock[block_num].blockEnd;
188 tempBlock.logicalStart = 0;
189 tempBlock.logicalEnd = 0;
190 printk("\n block %ld absStart=%016lx absEnd=%016lx",
191 block_num, tempBlock.absStart,
194 for (i = 0; i < numSegmentBlocks; ++i) {
195 if (mb_array[i].absStart ==
199 if (i == numSegmentBlocks) {
200 if (numSegmentBlocks == max_entries)
201 panic("iSeries_process_mainstore_vpd: too many memory blocks");
202 mb_array[numSegmentBlocks] = tempBlock;
205 printk(" (duplicate)");
211 /* Now sort the blocks found into ascending sequence */
212 if (numSegmentBlocks > 1) {
215 for (m = 0; m < numSegmentBlocks - 1; ++m) {
216 for (n = numSegmentBlocks - 1; m < n; --n) {
217 if (mb_array[n].absStart <
218 mb_array[n-1].absStart) {
219 struct MemoryBlock tempBlock;
221 tempBlock = mb_array[n];
222 mb_array[n] = mb_array[n-1];
223 mb_array[n-1] = tempBlock;
229 * Assign "logical" addresses to each block. These
230 * addresses correspond to the hypervisor "bitmap" space.
231 * Convert all addresses into units of 256K chunks.
234 unsigned long i, nextBitmapAddress;
236 printk("ms_vpd: %ld sorted memory blocks\n", numSegmentBlocks);
237 nextBitmapAddress = 0;
238 for (i = 0; i < numSegmentBlocks; ++i) {
239 unsigned long length = mb_array[i].absEnd -
240 mb_array[i].absStart;
242 mb_array[i].logicalStart = nextBitmapAddress;
243 mb_array[i].logicalEnd = nextBitmapAddress + length;
244 nextBitmapAddress += length;
245 printk(" Bitmap range: %016lx - %016lx\n"
246 " Absolute range: %016lx - %016lx\n",
247 mb_array[i].logicalStart,
248 mb_array[i].logicalEnd,
249 mb_array[i].absStart, mb_array[i].absEnd);
250 mb_array[i].absStart = addr_to_chunk(mb_array[i].absStart &
252 mb_array[i].absEnd = addr_to_chunk(mb_array[i].absEnd &
254 mb_array[i].logicalStart =
255 addr_to_chunk(mb_array[i].logicalStart);
256 mb_array[i].logicalEnd = addr_to_chunk(mb_array[i].logicalEnd);
260 return numSegmentBlocks;
263 static unsigned long iSeries_process_mainstore_vpd(struct MemoryBlock *mb_array,
264 unsigned long max_entries)
267 unsigned long mem_blocks = 0;
269 if (cpu_has_feature(CPU_FTR_SLB))
270 mem_blocks = iSeries_process_Regatta_mainstore_vpd(mb_array,
273 mem_blocks = iSeries_process_Condor_mainstore_vpd(mb_array,
276 printk("Mainstore_VPD: numMemoryBlocks = %ld \n", mem_blocks);
277 for (i = 0; i < mem_blocks; ++i) {
278 printk("Mainstore_VPD: block %3ld logical chunks %016lx - %016lx\n"
279 " abs chunks %016lx - %016lx\n",
280 i, mb_array[i].logicalStart, mb_array[i].logicalEnd,
281 mb_array[i].absStart, mb_array[i].absEnd);
286 static void __init iSeries_get_cmdline(void)
290 /* copy the command line parameter from the primary VSP */
291 HvCallEvent_dmaToSp(cmd_line, 2 * 64* 1024, 256,
292 HvLpDma_Direction_RemoteToLocal);
297 if (!*p || *p == '\n')
304 static void __init iSeries_init_early(void)
306 DBG(" -> iSeries_init_early()\n");
308 ppc64_firmware_features = FW_FEATURE_ISERIES;
310 ppc64_interrupt_controller = IC_ISERIES;
312 #if defined(CONFIG_BLK_DEV_INITRD)
314 * If the init RAM disk has been configured and there is
315 * a non-zero starting address for it, set it up
318 initrd_start = (unsigned long)__va(naca.xRamDisk);
319 initrd_end = initrd_start + naca.xRamDiskSize * HW_PAGE_SIZE;
320 initrd_below_start_ok = 1; // ramdisk in kernel space
321 ROOT_DEV = Root_RAM0;
322 if (((rd_size * 1024) / HW_PAGE_SIZE) < naca.xRamDiskSize)
323 rd_size = (naca.xRamDiskSize * HW_PAGE_SIZE) / 1024;
325 #endif /* CONFIG_BLK_DEV_INITRD */
327 /* ROOT_DEV = MKDEV(VIODASD_MAJOR, 1); */
330 iSeries_recal_tb = get_tb();
331 iSeries_recal_titan = HvCallXm_loadTod();
334 * Initialize the hash table management pointers
339 * Initialize the DMA/TCE management
341 iommu_init_early_iSeries();
343 /* Initialize machine-dependency vectors */
347 if (itLpNaca.xPirEnvironMode == 0)
348 piranha_simulator = 1;
350 /* Associate Lp Event Queue 0 with processor 0 */
351 HvCallEvent_setLpEventQueueInterruptProc(0, 0);
357 /* If we were passed an initrd, set the ROOT_DEV properly if the values
358 * look sensible. If not, clear initrd reference.
360 #ifdef CONFIG_BLK_DEV_INITRD
361 if (initrd_start >= KERNELBASE && initrd_end >= KERNELBASE &&
362 initrd_end > initrd_start)
363 ROOT_DEV = Root_RAM0;
365 initrd_start = initrd_end = 0;
366 #endif /* CONFIG_BLK_DEV_INITRD */
368 DBG(" <- iSeries_init_early()\n");
371 struct mschunks_map mschunks_map = {
372 /* XXX We don't use these, but Piranha might need them. */
373 .chunk_size = MSCHUNKS_CHUNK_SIZE,
374 .chunk_shift = MSCHUNKS_CHUNK_SHIFT,
375 .chunk_mask = MSCHUNKS_OFFSET_MASK,
377 EXPORT_SYMBOL(mschunks_map);
379 void mschunks_alloc(unsigned long num_chunks)
381 klimit = _ALIGN(klimit, sizeof(u32));
382 mschunks_map.mapping = (u32 *)klimit;
383 klimit += num_chunks * sizeof(u32);
384 mschunks_map.num_chunks = num_chunks;
388 * The iSeries may have very large memories ( > 128 GB ) and a partition
389 * may get memory in "chunks" that may be anywhere in the 2**52 real
390 * address space. The chunks are 256K in size. To map this to the
391 * memory model Linux expects, the AS/400 specific code builds a
392 * translation table to translate what Linux thinks are "physical"
393 * addresses to the actual real addresses. This allows us to make
394 * it appear to Linux that we have contiguous memory starting at
395 * physical address zero while in fact this could be far from the truth.
396 * To avoid confusion, I'll let the words physical and/or real address
397 * apply to the Linux addresses while I'll use "absolute address" to
398 * refer to the actual hardware real address.
400 * build_iSeries_Memory_Map gets information from the Hypervisor and
401 * looks at the Main Store VPD to determine the absolute addresses
402 * of the memory that has been assigned to our partition and builds
403 * a table used to translate Linux's physical addresses to these
404 * absolute addresses. Absolute addresses are needed when
405 * communicating with the hypervisor (e.g. to build HPT entries)
407 * Returns the physical memory size
410 static unsigned long __init build_iSeries_Memory_Map(void)
412 u32 loadAreaFirstChunk, loadAreaLastChunk, loadAreaSize;
414 u32 hptFirstChunk, hptLastChunk, hptSizeChunks, hptSizePages;
415 u32 totalChunks,moreChunks;
416 u32 currChunk, thisChunk, absChunk;
420 struct MemoryBlock mb[32];
421 unsigned long numMemoryBlocks, curBlock;
423 /* Chunk size on iSeries is 256K bytes */
424 totalChunks = (u32)HvLpConfig_getMsChunks();
425 mschunks_alloc(totalChunks);
428 * Get absolute address of our load area
429 * and map it to physical address 0
430 * This guarantees that the loadarea ends up at physical 0
431 * otherwise, it might not be returned by PLIC as the first
435 loadAreaFirstChunk = (u32)addr_to_chunk(itLpNaca.xLoadAreaAddr);
436 loadAreaSize = itLpNaca.xLoadAreaChunks;
439 * Only add the pages already mapped here.
440 * Otherwise we might add the hpt pages
441 * The rest of the pages of the load area
442 * aren't in the HPT yet and can still
443 * be assigned an arbitrary physical address
445 if ((loadAreaSize * 64) > HvPagesToMap)
446 loadAreaSize = HvPagesToMap / 64;
448 loadAreaLastChunk = loadAreaFirstChunk + loadAreaSize - 1;
451 * TODO Do we need to do something if the HPT is in the 64MB load area?
452 * This would be required if the itLpNaca.xLoadAreaChunks includes
456 printk("Mapping load area - physical addr = 0000000000000000\n"
457 " absolute addr = %016lx\n",
458 chunk_to_addr(loadAreaFirstChunk));
459 printk("Load area size %dK\n", loadAreaSize * 256);
461 for (nextPhysChunk = 0; nextPhysChunk < loadAreaSize; ++nextPhysChunk)
462 mschunks_map.mapping[nextPhysChunk] =
463 loadAreaFirstChunk + nextPhysChunk;
466 * Get absolute address of our HPT and remember it so
467 * we won't map it to any physical address
469 hptFirstChunk = (u32)addr_to_chunk(HvCallHpt_getHptAddress());
470 hptSizePages = (u32)HvCallHpt_getHptPages();
471 hptSizeChunks = hptSizePages >>
472 (MSCHUNKS_CHUNK_SHIFT - HW_PAGE_SHIFT);
473 hptLastChunk = hptFirstChunk + hptSizeChunks - 1;
475 printk("HPT absolute addr = %016lx, size = %dK\n",
476 chunk_to_addr(hptFirstChunk), hptSizeChunks * 256);
478 ppc64_pft_size = __ilog2(hptSizePages * HW_PAGE_SIZE);
481 * The actual hashed page table is in the hypervisor,
482 * we have no direct access
487 * Determine if absolute memory has any
488 * holes so that we can interpret the
489 * access map we get back from the hypervisor
492 numMemoryBlocks = iSeries_process_mainstore_vpd(mb, 32);
495 * Process the main store access map from the hypervisor
496 * to build up our physical -> absolute translation table
501 moreChunks = totalChunks;
504 map = HvCallSm_get64BitsOfAccessMap(itLpNaca.xLpIndex,
506 thisChunk = currChunk;
508 chunkBit = map >> 63;
512 while (thisChunk >= mb[curBlock].logicalEnd) {
514 if (curBlock >= numMemoryBlocks)
515 panic("out of memory blocks");
517 if (thisChunk < mb[curBlock].logicalStart)
518 panic("memory block error");
520 absChunk = mb[curBlock].absStart +
521 (thisChunk - mb[curBlock].logicalStart);
522 if (((absChunk < hptFirstChunk) ||
523 (absChunk > hptLastChunk)) &&
524 ((absChunk < loadAreaFirstChunk) ||
525 (absChunk > loadAreaLastChunk))) {
526 mschunks_map.mapping[nextPhysChunk] =
538 * main store size (in chunks) is
539 * totalChunks - hptSizeChunks
540 * which should be equal to
543 return chunk_to_addr(nextPhysChunk);
549 static void __init iSeries_setup_arch(void)
551 unsigned procIx = get_paca()->lppaca.dyn_hv_phys_proc_index;
553 if (get_paca()->lppaca.shared_proc) {
554 ppc_md.idle_loop = iseries_shared_idle;
555 printk(KERN_INFO "Using shared processor idle loop\n");
557 ppc_md.idle_loop = iseries_dedicated_idle;
558 printk(KERN_INFO "Using dedicated idle loop\n");
561 /* Setup the Lp Event Queue */
562 setup_hvlpevent_queue();
564 printk("Max logical processors = %d\n",
565 itVpdAreas.xSlicMaxLogicalProcs);
566 printk("Max physical processors = %d\n",
567 itVpdAreas.xSlicMaxPhysicalProcs);
569 _systemcfg->processor = xIoHriProcessorVpd[procIx].xPVR;
570 printk("Processor version = %x\n", _systemcfg->processor);
573 static void iSeries_show_cpuinfo(struct seq_file *m)
575 seq_printf(m, "machine\t\t: 64-bit iSeries Logical Partition\n");
582 static int iSeries_get_irq(struct pt_regs *regs)
584 /* -2 means ignore this interrupt */
591 static void iSeries_restart(char *cmd)
599 static void iSeries_power_off(void)
607 static void iSeries_halt(void)
612 static void __init iSeries_progress(char * st, unsigned short code)
614 printk("Progress: [%04x] - %s\n", (unsigned)code, st);
615 if (!piranha_simulator && mf_initialized) {
617 mf_display_progress(code);
623 static void __init iSeries_fixup_klimit(void)
626 * Change klimit to take into account any ram disk
627 * that may be included
630 klimit = KERNELBASE + (u64)naca.xRamDisk +
631 (naca.xRamDiskSize * HW_PAGE_SIZE);
634 * No ram disk was included - check and see if there
635 * was an embedded system map. Change klimit to take
636 * into account any embedded system map
638 if (embedded_sysmap_end)
639 klimit = KERNELBASE + ((embedded_sysmap_end + 4095) &
644 static int __init iSeries_src_init(void)
646 /* clear the progress line */
647 ppc_md.progress(" ", 0xffff);
651 late_initcall(iSeries_src_init);
653 static inline void process_iSeries_events(void)
655 asm volatile ("li 0,0x5555; sc" : : : "r0", "r3");
658 static void yield_shared_processor(void)
662 HvCall_setEnabledInterrupts(HvCall_MaskIPI |
668 /* Compute future tb value when yield should expire */
669 HvCall_yieldProcessor(HvCall_YieldTimed, tb+tb_ticks_per_jiffy);
672 * The decrementer stops during the yield. Force a fake decrementer
673 * here and let the timer_interrupt code sort out the actual time.
675 get_paca()->lppaca.int_dword.fields.decr_int = 1;
676 process_iSeries_events();
679 static void iseries_shared_idle(void)
682 while (!need_resched() && !hvlpevent_is_pending()) {
684 ppc64_runlatch_off();
686 /* Recheck with irqs off */
687 if (!need_resched() && !hvlpevent_is_pending())
688 yield_shared_processor();
696 if (hvlpevent_is_pending())
697 process_iSeries_events();
699 preempt_enable_no_resched();
705 static void iseries_dedicated_idle(void)
708 set_thread_flag(TIF_POLLING_NRFLAG);
711 if (!need_resched()) {
712 while (!need_resched()) {
713 ppc64_runlatch_off();
716 if (hvlpevent_is_pending()) {
719 process_iSeries_events();
727 preempt_enable_no_resched();
734 void __init iSeries_init_IRQ(void) { }
737 static int __init iseries_probe(int platform)
739 return PLATFORM_ISERIES_LPAR == platform;
742 struct machdep_calls __initdata iseries_md = {
743 .setup_arch = iSeries_setup_arch,
744 .show_cpuinfo = iSeries_show_cpuinfo,
745 .init_IRQ = iSeries_init_IRQ,
746 .get_irq = iSeries_get_irq,
747 .init_early = iSeries_init_early,
748 .pcibios_fixup = iSeries_pci_final_fixup,
749 .restart = iSeries_restart,
750 .power_off = iSeries_power_off,
751 .halt = iSeries_halt,
752 .get_boot_time = iSeries_get_boot_time,
753 .set_rtc_time = iSeries_set_rtc_time,
754 .get_rtc_time = iSeries_get_rtc_time,
755 .calibrate_decr = generic_calibrate_decr,
756 .progress = iSeries_progress,
757 .probe = iseries_probe,
758 /* XXX Implement enable_pmcs for iSeries */
762 unsigned char data[PAGE_SIZE];
766 struct iseries_flat_dt {
767 struct boot_param_header header;
773 struct iseries_flat_dt iseries_dt;
775 void dt_init(struct iseries_flat_dt *dt)
777 dt->header.off_mem_rsvmap =
778 offsetof(struct iseries_flat_dt, reserve_map);
779 dt->header.off_dt_struct = offsetof(struct iseries_flat_dt, dt);
780 dt->header.off_dt_strings = offsetof(struct iseries_flat_dt, strings);
781 dt->header.totalsize = sizeof(struct iseries_flat_dt);
782 dt->header.dt_strings_size = sizeof(struct blob);
784 /* There is no notion of hardware cpu id on iSeries */
785 dt->header.boot_cpuid_phys = smp_processor_id();
787 dt->dt.next = (unsigned long)&dt->dt.data;
788 dt->strings.next = (unsigned long)&dt->strings.data;
790 dt->header.magic = OF_DT_HEADER;
791 dt->header.version = 0x10;
792 dt->header.last_comp_version = 0x10;
794 dt->reserve_map[0] = 0;
795 dt->reserve_map[1] = 0;
798 void dt_check_blob(struct blob *b)
800 if (b->next >= (unsigned long)&b->next) {
801 DBG("Ran out of space in flat device tree blob!\n");
806 void dt_push_u32(struct iseries_flat_dt *dt, u32 value)
808 *((u32*)dt->dt.next) = value;
809 dt->dt.next += sizeof(u32);
811 dt_check_blob(&dt->dt);
814 void dt_push_u64(struct iseries_flat_dt *dt, u64 value)
816 *((u64*)dt->dt.next) = value;
817 dt->dt.next += sizeof(u64);
819 dt_check_blob(&dt->dt);
822 unsigned long dt_push_bytes(struct blob *blob, char *data, int len)
824 unsigned long start = blob->next - (unsigned long)blob->data;
826 memcpy((char *)blob->next, data, len);
827 blob->next = _ALIGN(blob->next + len, 4);
834 void dt_start_node(struct iseries_flat_dt *dt, char *name)
836 dt_push_u32(dt, OF_DT_BEGIN_NODE);
837 dt_push_bytes(&dt->dt, name, strlen(name) + 1);
840 #define dt_end_node(dt) dt_push_u32(dt, OF_DT_END_NODE)
842 void dt_prop(struct iseries_flat_dt *dt, char *name, char *data, int len)
844 unsigned long offset;
846 dt_push_u32(dt, OF_DT_PROP);
848 /* Length of the data */
849 dt_push_u32(dt, len);
851 /* Put the property name in the string blob. */
852 offset = dt_push_bytes(&dt->strings, name, strlen(name) + 1);
854 /* The offset of the properties name in the string blob. */
855 dt_push_u32(dt, (u32)offset);
857 /* The actual data. */
858 dt_push_bytes(&dt->dt, data, len);
861 void dt_prop_str(struct iseries_flat_dt *dt, char *name, char *data)
863 dt_prop(dt, name, data, strlen(data) + 1); /* + 1 for NULL */
866 void dt_prop_u32(struct iseries_flat_dt *dt, char *name, u32 data)
868 dt_prop(dt, name, (char *)&data, sizeof(u32));
871 void dt_prop_u64(struct iseries_flat_dt *dt, char *name, u64 data)
873 dt_prop(dt, name, (char *)&data, sizeof(u64));
876 void dt_prop_u64_list(struct iseries_flat_dt *dt, char *name, u64 *data, int n)
878 dt_prop(dt, name, (char *)data, sizeof(u64) * n);
881 void dt_prop_empty(struct iseries_flat_dt *dt, char *name)
883 dt_prop(dt, name, NULL, 0);
886 void dt_cpus(struct iseries_flat_dt *dt)
888 unsigned char buf[32];
890 unsigned int i, index;
891 struct IoHriProcessorVpd *d;
894 snprintf(buf, 32, "PowerPC,%s", cur_cpu_spec->cpu_name);
895 p = strchr(buf, ' ');
896 if (!p) p = buf + strlen(buf);
898 dt_start_node(dt, "cpus");
899 dt_prop_u32(dt, "#address-cells", 1);
900 dt_prop_u32(dt, "#size-cells", 0);
902 for (i = 0; i < NR_CPUS; i++) {
903 if (paca[i].lppaca.dyn_proc_status >= 2)
906 snprintf(p, 32 - (p - buf), "@%d", i);
907 dt_start_node(dt, buf);
909 dt_prop_str(dt, "device_type", "cpu");
911 index = paca[i].lppaca.dyn_hv_phys_proc_index;
912 d = &xIoHriProcessorVpd[index];
914 dt_prop_u32(dt, "i-cache-size", d->xInstCacheSize * 1024);
915 dt_prop_u32(dt, "i-cache-line-size", d->xInstCacheOperandSize);
917 dt_prop_u32(dt, "d-cache-size", d->xDataL1CacheSizeKB * 1024);
918 dt_prop_u32(dt, "d-cache-line-size", d->xDataCacheOperandSize);
920 /* magic conversions to Hz copied from old code */
921 dt_prop_u32(dt, "clock-frequency",
922 ((1UL << 34) * 1000000) / d->xProcFreq);
923 dt_prop_u32(dt, "timebase-frequency",
924 ((1UL << 32) * 1000000) / d->xTimeBaseFreq);
926 dt_prop_u32(dt, "reg", i);
934 void build_flat_dt(struct iseries_flat_dt *dt, unsigned long phys_mem_size)
940 dt_start_node(dt, "");
942 dt_prop_u32(dt, "#address-cells", 2);
943 dt_prop_u32(dt, "#size-cells", 2);
946 dt_start_node(dt, "memory@0");
947 dt_prop_str(dt, "name", "memory");
948 dt_prop_str(dt, "device_type", "memory");
950 tmp[1] = phys_mem_size;
951 dt_prop_u64_list(dt, "reg", tmp, 2);
955 dt_start_node(dt, "chosen");
956 dt_prop_u32(dt, "linux,platform", PLATFORM_ISERIES_LPAR);
958 dt_prop_u64(dt, "linux,memory-limit", cmd_mem_limit);
965 dt_push_u32(dt, OF_DT_END);
968 void * __init iSeries_early_setup(void)
970 unsigned long phys_mem_size;
972 iSeries_fixup_klimit();
975 * Initialize the table which translate Linux physical addresses to
976 * AS/400 absolute addresses
978 phys_mem_size = build_iSeries_Memory_Map();
980 iSeries_get_cmdline();
982 /* Save unparsed command line copy for /proc/cmdline */
983 strlcpy(saved_command_line, cmd_line, COMMAND_LINE_SIZE);
985 /* Parse early parameters, in particular mem=x */
988 build_flat_dt(&iseries_dt, phys_mem_size);
990 return (void *) __pa(&iseries_dt);
994 * On iSeries we just parse the mem=X option from the command line.
995 * On pSeries it's a bit more complicated, see prom_init_mem()
997 static int __init early_parsemem(char *p)
1000 cmd_mem_limit = ALIGN(memparse(p, &p), PAGE_SIZE);
1003 early_param("mem", early_parsemem);