arch/powerpc/platforms/powermac/pic.c

   1 /*
   2  *  Support for the interrupt controllers found on Power Macintosh,
   3  *  currently Apple's "Grand Central" interrupt controller in all
   4  *  it's incarnations. OpenPIC support used on newer machines is
   5  *  in a separate file
   6  *
   7  *  Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
   8  *
   9  *  Maintained by Benjamin Herrenschmidt (benh@kernel.crashing.org)
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version
  14  *  2 of the License, or (at your option) any later version.
  15  *
  16  */
  17
  18 #include <linux/config.h>
  19 #include <linux/stddef.h>
  20 #include <linux/init.h>
  21 #include <linux/sched.h>
  22 #include <linux/signal.h>
  23 #include <linux/pci.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/sysdev.h>
  26 #include <linux/adb.h>
  27 #include <linux/pmu.h>
  28 #include <linux/module.h>
  29
  30 #include <asm/sections.h>
  31 #include <asm/io.h>
  32 #include <asm/smp.h>
  33 #include <asm/prom.h>
  34 #include <asm/pci-bridge.h>
  35 #include <asm/time.h>
  36 #include <asm/pmac_feature.h>
  37 #include <asm/mpic.h>
  38
  39 #include "pmac.h"
  40
  41 /*
  42  * XXX this should be in xmon.h, but putting it there means xmon.h
  43  * has to include <linux/interrupt.h> (to get irqreturn_t), which
  44  * causes all sorts of problems.  -- paulus
  45  */
  46 extern irqreturn_t xmon_irq(int, void *, struct pt_regs *);
  47
  48 #ifdef CONFIG_PPC32
  49 struct pmac_irq_hw {
  50         unsigned int    event;
  51         unsigned int    enable;
  52         unsigned int    ack;
  53         unsigned int    level;
  54 };
  55
  56 /* Default addresses */
  57 static volatile struct pmac_irq_hw *pmac_irq_hw[4] = {
  58         (struct pmac_irq_hw *) 0xf3000020,
  59         (struct pmac_irq_hw *) 0xf3000010,
  60         (struct pmac_irq_hw *) 0xf4000020,
  61         (struct pmac_irq_hw *) 0xf4000010,
  62 };
  63
  64 #define GC_LEVEL_MASK           0x3ff00000
  65 #define OHARE_LEVEL_MASK        0x1ff00000
  66 #define HEATHROW_LEVEL_MASK     0x1ff00000
  67
  68 static int max_irqs;
  69 static int max_real_irqs;
  70 static u32 level_mask[4];
  71
  72 static DEFINE_SPINLOCK(pmac_pic_lock);
  73
  74 #define GATWICK_IRQ_POOL_SIZE        10
  75 static struct interrupt_info gatwick_int_pool[GATWICK_IRQ_POOL_SIZE];
  76
  77 /*
  78  * Mark an irq as "lost".  This is only used on the pmac
  79  * since it can lose interrupts (see pmac_set_irq_mask).
  80  * -- Cort
  81  */
  82 void
  83 __set_lost(unsigned long irq_nr, int nokick)
  84 {
  85         if (!test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
  86                 atomic_inc(&ppc_n_lost_interrupts);
  87                 if (!nokick)
  88                         set_dec(1);
  89         }
  90 }
  91
  92 static void
  93 pmac_mask_and_ack_irq(unsigned int irq_nr)
  94 {
  95         unsigned long bit = 1UL << (irq_nr & 0x1f);
  96         int i = irq_nr >> 5;
  97         unsigned long flags;
  98
  99         if ((unsigned)irq_nr >= max_irqs)
 100                 return;
 101
 102         clear_bit(irq_nr, ppc_cached_irq_mask);
 103         if (test_and_clear_bit(irq_nr, ppc_lost_interrupts))
 104                 atomic_dec(&ppc_n_lost_interrupts);
 105         spin_lock_irqsave(&pmac_pic_lock, flags);
 106         out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
 107         out_le32(&pmac_irq_hw[i]->ack, bit);
 108         do {
 109                 /* make sure ack gets to controller before we enable
 110                    interrupts */
 111                 mb();
 112         } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
 113                 != (ppc_cached_irq_mask[i] & bit));
 114         spin_unlock_irqrestore(&pmac_pic_lock, flags);
 115 }
 116
 117 static void pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
 118 {
 119         unsigned long bit = 1UL << (irq_nr & 0x1f);
 120         int i = irq_nr >> 5;
 121         unsigned long flags;
 122
 123         if ((unsigned)irq_nr >= max_irqs)
 124                 return;
 125
 126         spin_lock_irqsave(&pmac_pic_lock, flags);
 127         /* enable unmasked interrupts */
 128         out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
 129
 130         do {
 131                 /* make sure mask gets to controller before we
 132                    return to user */
 133                 mb();
 134         } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
 135                 != (ppc_cached_irq_mask[i] & bit));
 136
 137         /*
 138          * Unfortunately, setting the bit in the enable register
 139          * when the device interrupt is already on *doesn't* set
 140          * the bit in the flag register or request another interrupt.
 141          */
 142         if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
 143                 __set_lost((ulong)irq_nr, nokicklost);
 144         spin_unlock_irqrestore(&pmac_pic_lock, flags);
 145 }
 146
 147 /* When an irq gets requested for the first client, if it's an
 148  * edge interrupt, we clear any previous one on the controller
 149  */
 150 static unsigned int pmac_startup_irq(unsigned int irq_nr)
 151 {
 152         unsigned long bit = 1UL << (irq_nr & 0x1f);
 153         int i = irq_nr >> 5;
 154
 155         if ((irq_desc[irq_nr].status & IRQ_LEVEL) == 0)
 156                 out_le32(&pmac_irq_hw[i]->ack, bit);
 157         set_bit(irq_nr, ppc_cached_irq_mask);
 158         pmac_set_irq_mask(irq_nr, 0);
 159
 160         return 0;
 161 }
 162
 163 static void pmac_mask_irq(unsigned int irq_nr)
 164 {
 165         clear_bit(irq_nr, ppc_cached_irq_mask);
 166         pmac_set_irq_mask(irq_nr, 0);
 167         mb();
 168 }
 169
 170 static void pmac_unmask_irq(unsigned int irq_nr)
 171 {
 172         set_bit(irq_nr, ppc_cached_irq_mask);
 173         pmac_set_irq_mask(irq_nr, 0);
 174 }
 175
 176 static void pmac_end_irq(unsigned int irq_nr)
 177 {
 178         if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
 179             && irq_desc[irq_nr].action) {
 180                 set_bit(irq_nr, ppc_cached_irq_mask);
 181                 pmac_set_irq_mask(irq_nr, 1);
 182         }
 183 }
 184
 185
 186 struct hw_interrupt_type pmac_pic = {
 187         .typename       = " PMAC-PIC ",
 188         .startup        = pmac_startup_irq,
 189         .enable         = pmac_unmask_irq,
 190         .disable        = pmac_mask_irq,
 191         .ack            = pmac_mask_and_ack_irq,
 192         .end            = pmac_end_irq,
 193 };
 194
 195 struct hw_interrupt_type gatwick_pic = {
 196         .typename       = " GATWICK  ",
 197         .startup        = pmac_startup_irq,
 198         .enable         = pmac_unmask_irq,
 199         .disable        = pmac_mask_irq,
 200         .ack            = pmac_mask_and_ack_irq,
 201         .end            = pmac_end_irq,
 202 };
 203
 204 static irqreturn_t gatwick_action(int cpl, void *dev_id, struct pt_regs *regs)
 205 {
 206         int irq, bits;
 207
 208         for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
 209                 int i = irq >> 5;
 210                 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
 211                 /* We must read level interrupts from the level register */
 212                 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
 213                 bits &= ppc_cached_irq_mask[i];
 214                 if (bits == 0)
 215                         continue;
 216                 irq += __ilog2(bits);
 217                 __do_IRQ(irq, regs);
 218                 return IRQ_HANDLED;
 219         }
 220         printk("gatwick irq not from gatwick pic\n");
 221         return IRQ_NONE;
 222 }
 223
 224 int
 225 pmac_get_irq(struct pt_regs *regs)
 226 {
 227         int irq;
 228         unsigned long bits = 0;
 229
 230 #ifdef CONFIG_SMP
 231         void psurge_smp_message_recv(struct pt_regs *);
 232
 233         /* IPI's are a hack on the powersurge -- Cort */
 234         if ( smp_processor_id() != 0 ) {
 235                 psurge_smp_message_recv(regs);
 236                 return -2;      /* ignore, already handled */
 237         }
 238 #endif /* CONFIG_SMP */
 239         for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
 240                 int i = irq >> 5;
 241                 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
 242                 /* We must read level interrupts from the level register */
 243                 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
 244                 bits &= ppc_cached_irq_mask[i];
 245                 if (bits == 0)
 246                         continue;
 247                 irq += __ilog2(bits);
 248                 break;
 249         }
 250
 251         return irq;
 252 }
 253
 254 /* This routine will fix some missing interrupt values in the device tree
 255  * on the gatwick mac-io controller used by some PowerBooks
 256  */
 257 static void __init
 258 pmac_fix_gatwick_interrupts(struct device_node *gw, int irq_base)
 259 {
 260         struct device_node *node;
 261         int count;
 262
 263         memset(gatwick_int_pool, 0, sizeof(gatwick_int_pool));
 264         node = gw->child;
 265         count = 0;
 266         while(node)
 267         {
 268                 /* Fix SCC */
 269                 if (strcasecmp(node->name, "escc") == 0)
 270                         if (node->child) {
 271                                 if (node->child->n_intrs < 3) {
 272                                         node->child->intrs = &gatwick_int_pool[count];
 273                                         count += 3;
 274                                 }
 275                                 node->child->n_intrs = 3;
 276                                 node->child->intrs[0].line = 15+irq_base;
 277                                 node->child->intrs[1].line =  4+irq_base;
 278                                 node->child->intrs[2].line =  5+irq_base;
 279                                 printk(KERN_INFO "irq: fixed SCC on second controller (%d,%d,%d)\n",
 280                                         node->child->intrs[0].line,
 281                                         node->child->intrs[1].line,
 282                                         node->child->intrs[2].line);
 283                         }
 284                 /* Fix media-bay & left SWIM */
 285                 if (strcasecmp(node->name, "media-bay") == 0) {
 286                         struct device_node* ya_node;
 287
 288                         if (node->n_intrs == 0)
 289                                 node->intrs = &gatwick_int_pool[count++];
 290                         node->n_intrs = 1;
 291                         node->intrs[0].line = 29+irq_base;
 292                         printk(KERN_INFO "irq: fixed media-bay on second controller (%d)\n",
 293                                         node->intrs[0].line);
 294
 295                         ya_node = node->child;
 296                         while(ya_node)
 297                         {
 298                                 if (strcasecmp(ya_node->name, "floppy") == 0) {
 299                                         if (ya_node->n_intrs < 2) {
 300                                                 ya_node->intrs = &gatwick_int_pool[count];
 301                                                 count += 2;
 302                                         }
 303                                         ya_node->n_intrs = 2;
 304                                         ya_node->intrs[0].line = 19+irq_base;
 305                                         ya_node->intrs[1].line =  1+irq_base;
 306                                         printk(KERN_INFO "irq: fixed floppy on second controller (%d,%d)\n",
 307                                                 ya_node->intrs[0].line, ya_node->intrs[1].line);
 308                                 }
 309                                 if (strcasecmp(ya_node->name, "ata4") == 0) {
 310                                         if (ya_node->n_intrs < 2) {
 311                                                 ya_node->intrs = &gatwick_int_pool[count];
 312                                                 count += 2;
 313                                         }
 314                                         ya_node->n_intrs = 2;
 315                                         ya_node->intrs[0].line = 14+irq_base;
 316                                         ya_node->intrs[1].line =  3+irq_base;
 317                                         printk(KERN_INFO "irq: fixed ide on second controller (%d,%d)\n",
 318                                                 ya_node->intrs[0].line, ya_node->intrs[1].line);
 319                                 }
 320                                 ya_node = ya_node->sibling;
 321                         }
 322                 }
 323                 node = node->sibling;
 324         }
 325         if (count > 10) {
 326                 printk("WARNING !! Gatwick interrupt pool overflow\n");
 327                 printk("  GATWICK_IRQ_POOL_SIZE = %d\n", GATWICK_IRQ_POOL_SIZE);
 328                 printk("              requested = %d\n", count);
 329         }
 330 }
 331
 332 /*
 333  * The PowerBook 3400/2400/3500 can have a combo ethernet/modem
 334  * card which includes an ohare chip that acts as a second interrupt
 335  * controller.  If we find this second ohare, set it up and fix the
 336  * interrupt value in the device tree for the ethernet chip.
 337  */
 338 static int __init enable_second_ohare(void)
 339 {
 340         unsigned char bus, devfn;
 341         unsigned short cmd;
 342         unsigned long addr;
 343         struct device_node *irqctrler = find_devices("pci106b,7");
 344         struct device_node *ether;
 345
 346         if (irqctrler == NULL || irqctrler->n_addrs <= 0)
 347                 return -1;
 348         addr = (unsigned long) ioremap(irqctrler->addrs[0].address, 0x40);
 349         pmac_irq_hw[1] = (volatile struct pmac_irq_hw *)(addr + 0x20);
 350         max_irqs = 64;
 351         if (pci_device_from_OF_node(irqctrler, &bus, &devfn) == 0) {
 352                 struct pci_controller* hose = pci_find_hose_for_OF_device(irqctrler);
 353                 if (!hose)
 354                     printk(KERN_ERR "Can't find PCI hose for OHare2 !\n");
 355                 else {
 356                     early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd);
 357                     cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 358                     cmd &= ~PCI_COMMAND_IO;
 359                     early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd);
 360                 }
 361         }
 362
 363         /* Fix interrupt for the modem/ethernet combo controller. The number
 364            in the device tree (27) is bogus (correct for the ethernet-only
 365            board but not the combo ethernet/modem board).
 366            The real interrupt is 28 on the second controller -> 28+32 = 60.
 367         */
 368         ether = find_devices("pci1011,14");
 369         if (ether && ether->n_intrs > 0) {
 370                 ether->intrs[0].line = 60;
 371                 printk(KERN_INFO "irq: Fixed ethernet IRQ to %d\n",
 372                        ether->intrs[0].line);
 373         }
 374
 375         /* Return the interrupt number of the cascade */
 376         return irqctrler->intrs[0].line;
 377 }
 378
 379 #ifdef CONFIG_XMON
 380 static struct irqaction xmon_action = {
 381         .handler        = xmon_irq,
 382         .flags          = 0,
 383         .mask           = CPU_MASK_NONE,
 384         .name           = "NMI - XMON"
 385 };
 386 #endif
 387
 388 static struct irqaction gatwick_cascade_action = {
 389         .handler        = gatwick_action,
 390         .flags          = SA_INTERRUPT,
 391         .mask           = CPU_MASK_NONE,
 392         .name           = "cascade",
 393 };
 394 #endif /* CONFIG_PPC32 */
 395
 396 static int pmac_u3_cascade(struct pt_regs *regs, void *data)
 397 {
 398         return mpic_get_one_irq((struct mpic *)data, regs);
 399 }
 400
 401 void __init pmac_pic_init(void)
 402 {
 403         struct device_node *irqctrler  = NULL;
 404         struct device_node *irqctrler2 = NULL;
 405         struct device_node *np;
 406 #ifdef CONFIG_PPC32
 407         int i;
 408         unsigned long addr;
 409         int irq_cascade = -1;
 410 #endif
 411         struct mpic *mpic1, *mpic2;
 412
 413         /* We first try to detect Apple's new Core99 chipset, since mac-io
 414          * is quite different on those machines and contains an IBM MPIC2.
 415          */
 416         np = find_type_devices("open-pic");
 417         while (np) {
 418                 if (np->parent && !strcmp(np->parent->name, "u3"))
 419                         irqctrler2 = np;
 420                 else
 421                         irqctrler = np;
 422                 np = np->next;
 423         }
 424         if (irqctrler != NULL && irqctrler->n_addrs > 0) {
 425                 unsigned char senses[128];
 426
 427                 printk(KERN_INFO "PowerMac using OpenPIC irq controller at 0x%08x\n",
 428                        (unsigned int)irqctrler->addrs[0].address);
 429                 pmac_call_feature(PMAC_FTR_ENABLE_MPIC, irqctrler, 0, 0);
 430
 431                 prom_get_irq_senses(senses, 0, 128);
 432                 mpic1 = mpic_alloc(irqctrler->addrs[0].address,
 433                                    MPIC_PRIMARY | MPIC_WANTS_RESET,
 434                                    0, 0, 128, 252, senses, 128, " OpenPIC  ");
 435                 BUG_ON(mpic1 == NULL);
 436                 mpic_init(mpic1);
 437
 438                 if (irqctrler2 != NULL && irqctrler2->n_intrs > 0 &&
 439                     irqctrler2->n_addrs > 0) {
 440                         printk(KERN_INFO "Slave OpenPIC at 0x%08x hooked on IRQ %d\n",
 441                                (u32)irqctrler2->addrs[0].address,
 442                                irqctrler2->intrs[0].line);
 443
 444                         pmac_call_feature(PMAC_FTR_ENABLE_MPIC, irqctrler2, 0, 0);
 445                         prom_get_irq_senses(senses, 128, 128 + 124);
 446
 447                         /* We don't need to set MPIC_BROKEN_U3 here since we don't have
 448                          * hypertransport interrupts routed to it
 449                          */
 450                         mpic2 = mpic_alloc(irqctrler2->addrs[0].address,
 451                                            MPIC_BIG_ENDIAN | MPIC_WANTS_RESET,
 452                                            0, 128, 124, 0, senses, 124,
 453                                            " U3-MPIC  ");
 454                         BUG_ON(mpic2 == NULL);
 455                         mpic_init(mpic2);
 456                         mpic_setup_cascade(irqctrler2->intrs[0].line,
 457                                            pmac_u3_cascade, mpic2);
 458                 }
 459 #if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
 460                 {
 461                         struct device_node* pswitch;
 462                         int nmi_irq;
 463
 464                         pswitch = find_devices("programmer-switch");
 465                         if (pswitch && pswitch->n_intrs) {
 466                                 nmi_irq = pswitch->intrs[0].line;
 467                                 mpic_irq_set_priority(nmi_irq, 9);
 468                                 setup_irq(nmi_irq, &xmon_action);
 469                         }
 470                 }
 471 #endif  /* CONFIG_XMON */
 472                 return;
 473         }
 474         irqctrler = NULL;
 475
 476 #ifdef CONFIG_PPC32
 477         /* Get the level/edge settings, assume if it's not
 478          * a Grand Central nor an OHare, then it's an Heathrow
 479          * (or Paddington).
 480          */
 481         ppc_md.get_irq = pmac_get_irq;
 482         if (find_devices("gc"))
 483                 level_mask[0] = GC_LEVEL_MASK;
 484         else if (find_devices("ohare")) {
 485                 level_mask[0] = OHARE_LEVEL_MASK;
 486                 /* We might have a second cascaded ohare */
 487                 level_mask[1] = OHARE_LEVEL_MASK;
 488         } else {
 489                 level_mask[0] = HEATHROW_LEVEL_MASK;
 490                 level_mask[1] = 0;
 491                 /* We might have a second cascaded heathrow */
 492                 level_mask[2] = HEATHROW_LEVEL_MASK;
 493                 level_mask[3] = 0;
 494         }
 495
 496         /*
 497          * G3 powermacs and 1999 G3 PowerBooks have 64 interrupts,
 498          * 1998 G3 Series PowerBooks have 128,
 499          * other powermacs have 32.
 500          * The combo ethernet/modem card for the Powerstar powerbooks
 501          * (2400/3400/3500, ohare based) has a second ohare chip
 502          * effectively making a total of 64.
 503          */
 504         max_irqs = max_real_irqs = 32;
 505         irqctrler = find_devices("mac-io");
 506         if (irqctrler)
 507         {
 508                 max_real_irqs = 64;
 509                 if (irqctrler->next)
 510                         max_irqs = 128;
 511                 else
 512                         max_irqs = 64;
 513         }
 514         for ( i = 0; i < max_real_irqs ; i++ )
 515                 irq_desc[i].handler = &pmac_pic;
 516
 517         /* get addresses of first controller */
 518         if (irqctrler) {
 519                 if  (irqctrler->n_addrs > 0) {
 520                         addr = (unsigned long)
 521                                 ioremap(irqctrler->addrs[0].address, 0x40);
 522                         for (i = 0; i < 2; ++i)
 523                                 pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
 524                                         (addr + (2 - i) * 0x10);
 525                 }
 526
 527                 /* get addresses of second controller */
 528                 irqctrler = irqctrler->next;
 529                 if (irqctrler && irqctrler->n_addrs > 0) {
 530                         addr = (unsigned long)
 531                                 ioremap(irqctrler->addrs[0].address, 0x40);
 532                         for (i = 2; i < 4; ++i)
 533                                 pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
 534                                         (addr + (4 - i) * 0x10);
 535                         irq_cascade = irqctrler->intrs[0].line;
 536                         if (device_is_compatible(irqctrler, "gatwick"))
 537                                 pmac_fix_gatwick_interrupts(irqctrler, max_real_irqs);
 538                 }
 539         } else {
 540                 /* older powermacs have a GC (grand central) or ohare at
 541                    f3000000, with interrupt control registers at f3000020. */
 542                 addr = (unsigned long) ioremap(0xf3000000, 0x40);
 543                 pmac_irq_hw[0] = (volatile struct pmac_irq_hw *) (addr + 0x20);
 544         }
 545
 546         /* PowerBooks 3400 and 3500 can have a second controller in a second
 547            ohare chip, on the combo ethernet/modem card */
 548         if (machine_is_compatible("AAPL,3400/2400")
 549              || machine_is_compatible("AAPL,3500"))
 550                 irq_cascade = enable_second_ohare();
 551
 552         /* disable all interrupts in all controllers */
 553         for (i = 0; i * 32 < max_irqs; ++i)
 554                 out_le32(&pmac_irq_hw[i]->enable, 0);
 555         /* mark level interrupts */
 556         for (i = 0; i < max_irqs; i++)
 557                 if (level_mask[i >> 5] & (1UL << (i & 0x1f)))
 558                         irq_desc[i].status = IRQ_LEVEL;
 559
 560         /* get interrupt line of secondary interrupt controller */
 561         if (irq_cascade >= 0) {
 562                 printk(KERN_INFO "irq: secondary controller on irq %d\n",
 563                         (int)irq_cascade);
 564                 for ( i = max_real_irqs ; i < max_irqs ; i++ )
 565                         irq_desc[i].handler = &gatwick_pic;
 566                 setup_irq(irq_cascade, &gatwick_cascade_action);
 567         }
 568         printk("System has %d possible interrupts\n", max_irqs);
 569         if (max_irqs != max_real_irqs)
 570                 printk(KERN_DEBUG "%d interrupts on main controller\n",
 571                         max_real_irqs);
 572
 573 #ifdef CONFIG_XMON
 574         setup_irq(20, &xmon_action);
 575 #endif  /* CONFIG_XMON */
 576 #endif  /* CONFIG_PPC32 */
 577 }
 578
 579 #if defined(CONFIG_PM) && defined(CONFIG_PPC32)
 580 /*
 581  * These procedures are used in implementing sleep on the powerbooks.
 582  * sleep_save_intrs() saves the states of all interrupt enables
 583  * and disables all interrupts except for the nominated one.
 584  * sleep_restore_intrs() restores the states of all interrupt enables.
 585  */
 586 unsigned long sleep_save_mask[2];
 587
 588 /* This used to be passed by the PMU driver but that link got
 589  * broken with the new driver model. We use this tweak for now...
 590  */
 591 static int pmacpic_find_viaint(void)
 592 {
 593         int viaint = -1;
 594
 595 #ifdef CONFIG_ADB_PMU
 596         struct device_node *np;
 597
 598         if (pmu_get_model() != PMU_OHARE_BASED)
 599                 goto not_found;
 600         np = of_find_node_by_name(NULL, "via-pmu");
 601         if (np == NULL)
 602                 goto not_found;
 603         viaint = np->intrs[0].line;
 604 #endif /* CONFIG_ADB_PMU */
 605
 606 not_found:
 607         return viaint;
 608 }
 609
 610 static int pmacpic_suspend(struct sys_device *sysdev, pm_message_t state)
 611 {
 612         int viaint = pmacpic_find_viaint();
 613
 614         sleep_save_mask[0] = ppc_cached_irq_mask[0];
 615         sleep_save_mask[1] = ppc_cached_irq_mask[1];
 616         ppc_cached_irq_mask[0] = 0;
 617         ppc_cached_irq_mask[1] = 0;
 618         if (viaint > 0)
 619                 set_bit(viaint, ppc_cached_irq_mask);
 620         out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
 621         if (max_real_irqs > 32)
 622                 out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
 623         (void)in_le32(&pmac_irq_hw[0]->event);
 624         /* make sure mask gets to controller before we return to caller */
 625         mb();
 626         (void)in_le32(&pmac_irq_hw[0]->enable);
 627
 628         return 0;
 629 }
 630
 631 static int pmacpic_resume(struct sys_device *sysdev)
 632 {
 633         int i;
 634
 635         out_le32(&pmac_irq_hw[0]->enable, 0);
 636         if (max_real_irqs > 32)
 637                 out_le32(&pmac_irq_hw[1]->enable, 0);
 638         mb();
 639         for (i = 0; i < max_real_irqs; ++i)
 640                 if (test_bit(i, sleep_save_mask))
 641                         pmac_unmask_irq(i);
 642
 643         return 0;
 644 }
 645
 646 #endif /* CONFIG_PM && CONFIG_PPC32 */
 647
 648 static struct sysdev_class pmacpic_sysclass = {
 649         set_kset_name("pmac_pic"),
 650 };
 651
 652 static struct sys_device device_pmacpic = {
 653         .id             = 0,
 654         .cls            = &pmacpic_sysclass,
 655 };
 656
 657 static struct sysdev_driver driver_pmacpic = {
 658 #if defined(CONFIG_PM) && defined(CONFIG_PPC32)
 659         .suspend        = &pmacpic_suspend,
 660         .resume         = &pmacpic_resume,
 661 #endif /* CONFIG_PM && CONFIG_PPC32 */
 662 };
 663
 664 static int __init init_pmacpic_sysfs(void)
 665 {
 666 #ifdef CONFIG_PPC32
 667         if (max_irqs == 0)
 668                 return -ENODEV;
 669 #endif
 670         printk(KERN_DEBUG "Registering pmac pic with sysfs...\n");
 671         sysdev_class_register(&pmacpic_sysclass);
 672         sysdev_register(&device_pmacpic);
 673         sysdev_driver_register(&pmacpic_sysclass, &driver_pmacpic);
 674         return 0;
 675 }
 676
 677 subsys_initcall(init_pmacpic_sysfs);
 678