arch/sparc/mm/init_64.c

   1 /*
   2  *  arch/sparc64/mm/init.c
   3  *
   4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
   5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/string.h>
  12 #include <linux/init.h>
  13 #include <linux/bootmem.h>
  14 #include <linux/mm.h>
  15 #include <linux/hugetlb.h>
  16 #include <linux/initrd.h>
  17 #include <linux/swap.h>
  18 #include <linux/pagemap.h>
  19 #include <linux/poison.h>
  20 #include <linux/fs.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/kprobes.h>
  23 #include <linux/cache.h>
  24 #include <linux/sort.h>
  25 #include <linux/percpu.h>
  26 #include <linux/memblock.h>
  27 #include <linux/mmzone.h>
  28 #include <linux/gfp.h>
  29
  30 #include <asm/head.h>
  31 #include <asm/page.h>
  32 #include <asm/pgalloc.h>
  33 #include <asm/pgtable.h>
  34 #include <asm/oplib.h>
  35 #include <asm/iommu.h>
  36 #include <asm/io.h>
  37 #include <asm/uaccess.h>
  38 #include <asm/mmu_context.h>
  39 #include <asm/tlbflush.h>
  40 #include <asm/dma.h>
  41 #include <asm/starfire.h>
  42 #include <asm/tlb.h>
  43 #include <asm/spitfire.h>
  44 #include <asm/sections.h>
  45 #include <asm/tsb.h>
  46 #include <asm/hypervisor.h>
  47 #include <asm/prom.h>
  48 #include <asm/mdesc.h>
  49 #include <asm/cpudata.h>
  50 #include <asm/irq.h>
  51
  52 #include "init_64.h"
  53
  54 unsigned long kern_linear_pte_xor[4] __read_mostly;
  55
  56 /* A bitmap, two bits for every 256MB of physical memory.  These two
  57  * bits determine what page size we use for kernel linear
  58  * translations.  They form an index into kern_linear_pte_xor[].  The
  59  * value in the indexed slot is XOR'd with the TLB miss virtual
  60  * address to form the resulting TTE.  The mapping is:
  61  *
  62  *      0       ==>     4MB
  63  *      1       ==>     256MB
  64  *      2       ==>     2GB
  65  *      3       ==>     16GB
  66  *
  67  * All sun4v chips support 256MB pages.  Only SPARC-T4 and later
  68  * support 2GB pages, and hopefully future cpus will support the 16GB
  69  * pages as well.  For slots 2 and 3, we encode a 256MB TTE xor there
  70  * if these larger page sizes are not supported by the cpu.
  71  *
  72  * It would be nice to determine this from the machine description
  73  * 'cpu' properties, but we need to have this table setup before the
  74  * MDESC is initialized.
  75  */
  76 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
  77
  78 #ifndef CONFIG_DEBUG_PAGEALLOC
  79 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
  80  * Space is allocated for this right after the trap table in
  81  * arch/sparc64/kernel/head.S
  82  */
  83 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
  84 #endif
  85
  86 static unsigned long cpu_pgsz_mask;
  87
  88 #define MAX_BANKS       32
  89
  90 static struct linux_prom64_registers pavail[MAX_BANKS];
  91 static int pavail_ents;
  92
  93 static int cmp_p64(const void *a, const void *b)
  94 {
  95         const struct linux_prom64_registers *x = a, *y = b;
  96
  97         if (x->phys_addr > y->phys_addr)
  98                 return 1;
  99         if (x->phys_addr < y->phys_addr)
 100                 return -1;
 101         return 0;
 102 }
 103
 104 static void __init read_obp_memory(const char *property,
 105                                    struct linux_prom64_registers *regs,
 106                                    int *num_ents)
 107 {
 108         phandle node = prom_finddevice("/memory");
 109         int prop_size = prom_getproplen(node, property);
 110         int ents, ret, i;
 111
 112         ents = prop_size / sizeof(struct linux_prom64_registers);
 113         if (ents > MAX_BANKS) {
 114                 prom_printf("The machine has more %s property entries than "
 115                             "this kernel can support (%d).\n",
 116                             property, MAX_BANKS);
 117                 prom_halt();
 118         }
 119
 120         ret = prom_getproperty(node, property, (char *) regs, prop_size);
 121         if (ret == -1) {
 122                 prom_printf("Couldn't get %s property from /memory.\n",
 123                                 property);
 124                 prom_halt();
 125         }
 126
 127         /* Sanitize what we got from the firmware, by page aligning
 128          * everything.
 129          */
 130         for (i = 0; i < ents; i++) {
 131                 unsigned long base, size;
 132
 133                 base = regs[i].phys_addr;
 134                 size = regs[i].reg_size;
 135
 136                 size &= PAGE_MASK;
 137                 if (base & ~PAGE_MASK) {
 138                         unsigned long new_base = PAGE_ALIGN(base);
 139
 140                         size -= new_base - base;
 141                         if ((long) size < 0L)
 142                                 size = 0UL;
 143                         base = new_base;
 144                 }
 145                 if (size == 0UL) {
 146                         /* If it is empty, simply get rid of it.
 147                          * This simplifies the logic of the other
 148                          * functions that process these arrays.
 149                          */
 150                         memmove(&regs[i], &regs[i + 1],
 151                                 (ents - i - 1) * sizeof(regs[0]));
 152                         i--;
 153                         ents--;
 154                         continue;
 155                 }
 156                 regs[i].phys_addr = base;
 157                 regs[i].reg_size = size;
 158         }
 159
 160         *num_ents = ents;
 161
 162         sort(regs, ents, sizeof(struct linux_prom64_registers),
 163              cmp_p64, NULL);
 164 }
 165
 166 unsigned long sparc64_valid_addr_bitmap[VALID_ADDR_BITMAP_BYTES /
 167                                         sizeof(unsigned long)];
 168 EXPORT_SYMBOL(sparc64_valid_addr_bitmap);
 169
 170 /* Kernel physical address base and size in bytes.  */
 171 unsigned long kern_base __read_mostly;
 172 unsigned long kern_size __read_mostly;
 173
 174 /* Initial ramdisk setup */
 175 extern unsigned long sparc_ramdisk_image64;
 176 extern unsigned int sparc_ramdisk_image;
 177 extern unsigned int sparc_ramdisk_size;
 178
 179 struct page *mem_map_zero __read_mostly;
 180 EXPORT_SYMBOL(mem_map_zero);
 181
 182 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
 183
 184 unsigned long sparc64_kern_pri_context __read_mostly;
 185 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
 186 unsigned long sparc64_kern_sec_context __read_mostly;
 187
 188 int num_kernel_image_mappings;
 189
 190 #ifdef CONFIG_DEBUG_DCFLUSH
 191 atomic_t dcpage_flushes = ATOMIC_INIT(0);
 192 #ifdef CONFIG_SMP
 193 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
 194 #endif
 195 #endif
 196
 197 inline void flush_dcache_page_impl(struct page *page)
 198 {
 199         BUG_ON(tlb_type == hypervisor);
 200 #ifdef CONFIG_DEBUG_DCFLUSH
 201         atomic_inc(&dcpage_flushes);
 202 #endif
 203
 204 #ifdef DCACHE_ALIASING_POSSIBLE
 205         __flush_dcache_page(page_address(page),
 206                             ((tlb_type == spitfire) &&
 207                              page_mapping(page) != NULL));
 208 #else
 209         if (page_mapping(page) != NULL &&
 210             tlb_type == spitfire)
 211                 __flush_icache_page(__pa(page_address(page)));
 212 #endif
 213 }
 214
 215 #define PG_dcache_dirty         PG_arch_1
 216 #define PG_dcache_cpu_shift     32UL
 217 #define PG_dcache_cpu_mask      \
 218         ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
 219
 220 #define dcache_dirty_cpu(page) \
 221         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
 222
 223 static inline void set_dcache_dirty(struct page *page, int this_cpu)
 224 {
 225         unsigned long mask = this_cpu;
 226         unsigned long non_cpu_bits;
 227
 228         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
 229         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
 230
 231         __asm__ __volatile__("1:\n\t"
 232                              "ldx       [%2], %%g7\n\t"
 233                              "and       %%g7, %1, %%g1\n\t"
 234                              "or        %%g1, %0, %%g1\n\t"
 235                              "casx      [%2], %%g7, %%g1\n\t"
 236                              "cmp       %%g7, %%g1\n\t"
 237                              "bne,pn    %%xcc, 1b\n\t"
 238                              " nop"
 239                              : /* no outputs */
 240                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
 241                              : "g1", "g7");
 242 }
 243
 244 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
 245 {
 246         unsigned long mask = (1UL << PG_dcache_dirty);
 247
 248         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
 249                              "1:\n\t"
 250                              "ldx       [%2], %%g7\n\t"
 251                              "srlx      %%g7, %4, %%g1\n\t"
 252                              "and       %%g1, %3, %%g1\n\t"
 253                              "cmp       %%g1, %0\n\t"
 254                              "bne,pn    %%icc, 2f\n\t"
 255                              " andn     %%g7, %1, %%g1\n\t"
 256                              "casx      [%2], %%g7, %%g1\n\t"
 257                              "cmp       %%g7, %%g1\n\t"
 258                              "bne,pn    %%xcc, 1b\n\t"
 259                              " nop\n"
 260                              "2:"
 261                              : /* no outputs */
 262                              : "r" (cpu), "r" (mask), "r" (&page->flags),
 263                                "i" (PG_dcache_cpu_mask),
 264                                "i" (PG_dcache_cpu_shift)
 265                              : "g1", "g7");
 266 }
 267
 268 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
 269 {
 270         unsigned long tsb_addr = (unsigned long) ent;
 271
 272         if (tlb_type == cheetah_plus || tlb_type == hypervisor)
 273                 tsb_addr = __pa(tsb_addr);
 274
 275         __tsb_insert(tsb_addr, tag, pte);
 276 }
 277
 278 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
 279
 280 static void flush_dcache(unsigned long pfn)
 281 {
 282         struct page *page;
 283
 284         page = pfn_to_page(pfn);
 285         if (page) {
 286                 unsigned long pg_flags;
 287
 288                 pg_flags = page->flags;
 289                 if (pg_flags & (1UL << PG_dcache_dirty)) {
 290                         int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
 291                                    PG_dcache_cpu_mask);
 292                         int this_cpu = get_cpu();
 293
 294                         /* This is just to optimize away some function calls
 295                          * in the SMP case.
 296                          */
 297                         if (cpu == this_cpu)
 298                                 flush_dcache_page_impl(page);
 299                         else
 300                                 smp_flush_dcache_page_impl(page, cpu);
 301
 302                         clear_dcache_dirty_cpu(page, cpu);
 303
 304                         put_cpu();
 305                 }
 306         }
 307 }
 308
 309 /* mm->context.lock must be held */
 310 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
 311                                     unsigned long tsb_hash_shift, unsigned long address,
 312                                     unsigned long tte)
 313 {
 314         struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
 315         unsigned long tag;
 316
 317         if (unlikely(!tsb))
 318                 return;
 319
 320         tsb += ((address >> tsb_hash_shift) &
 321                 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
 322         tag = (address >> 22UL);
 323         tsb_insert(tsb, tag, tte);
 324 }
 325
 326 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
 327 static inline bool is_hugetlb_pte(pte_t pte)
 328 {
 329         if ((tlb_type == hypervisor &&
 330              (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
 331             (tlb_type != hypervisor &&
 332              (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U))
 333                 return true;
 334         return false;
 335 }
 336 #endif
 337
 338 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
 339 {
 340         struct mm_struct *mm;
 341         unsigned long flags;
 342         pte_t pte = *ptep;
 343
 344         if (tlb_type != hypervisor) {
 345                 unsigned long pfn = pte_pfn(pte);
 346
 347                 if (pfn_valid(pfn))
 348                         flush_dcache(pfn);
 349         }
 350
 351         mm = vma->vm_mm;
 352
 353         spin_lock_irqsave(&mm->context.lock, flags);
 354
 355 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
 356         if (mm->context.huge_pte_count && is_hugetlb_pte(pte))
 357                 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
 358                                         address, pte_val(pte));
 359         else
 360 #endif
 361                 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
 362                                         address, pte_val(pte));
 363
 364         spin_unlock_irqrestore(&mm->context.lock, flags);
 365 }
 366
 367 void flush_dcache_page(struct page *page)
 368 {
 369         struct address_space *mapping;
 370         int this_cpu;
 371
 372         if (tlb_type == hypervisor)
 373                 return;
 374
 375         /* Do not bother with the expensive D-cache flush if it
 376          * is merely the zero page.  The 'bigcore' testcase in GDB
 377          * causes this case to run millions of times.
 378          */
 379         if (page == ZERO_PAGE(0))
 380                 return;
 381
 382         this_cpu = get_cpu();
 383
 384         mapping = page_mapping(page);
 385         if (mapping && !mapping_mapped(mapping)) {
 386                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
 387                 if (dirty) {
 388                         int dirty_cpu = dcache_dirty_cpu(page);
 389
 390                         if (dirty_cpu == this_cpu)
 391                                 goto out;
 392                         smp_flush_dcache_page_impl(page, dirty_cpu);
 393                 }
 394                 set_dcache_dirty(page, this_cpu);
 395         } else {
 396                 /* We could delay the flush for the !page_mapping
 397                  * case too.  But that case is for exec env/arg
 398                  * pages and those are %99 certainly going to get
 399                  * faulted into the tlb (and thus flushed) anyways.
 400                  */
 401                 flush_dcache_page_impl(page);
 402         }
 403
 404 out:
 405         put_cpu();
 406 }
 407 EXPORT_SYMBOL(flush_dcache_page);
 408
 409 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
 410 {
 411         /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
 412         if (tlb_type == spitfire) {
 413                 unsigned long kaddr;
 414
 415                 /* This code only runs on Spitfire cpus so this is
 416                  * why we can assume _PAGE_PADDR_4U.
 417                  */
 418                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
 419                         unsigned long paddr, mask = _PAGE_PADDR_4U;
 420
 421                         if (kaddr >= PAGE_OFFSET)
 422                                 paddr = kaddr & mask;
 423                         else {
 424                                 pgd_t *pgdp = pgd_offset_k(kaddr);
 425                                 pud_t *pudp = pud_offset(pgdp, kaddr);
 426                                 pmd_t *pmdp = pmd_offset(pudp, kaddr);
 427                                 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
 428
 429                                 paddr = pte_val(*ptep) & mask;
 430                         }
 431                         __flush_icache_page(paddr);
 432                 }
 433         }
 434 }
 435 EXPORT_SYMBOL(flush_icache_range);
 436
 437 void mmu_info(struct seq_file *m)
 438 {
 439         static const char *pgsz_strings[] = {
 440                 "8K", "64K", "512K", "4MB", "32MB",
 441                 "256MB", "2GB", "16GB",
 442         };
 443         int i, printed;
 444
 445         if (tlb_type == cheetah)
 446                 seq_printf(m, "MMU Type\t: Cheetah\n");
 447         else if (tlb_type == cheetah_plus)
 448                 seq_printf(m, "MMU Type\t: Cheetah+\n");
 449         else if (tlb_type == spitfire)
 450                 seq_printf(m, "MMU Type\t: Spitfire\n");
 451         else if (tlb_type == hypervisor)
 452                 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
 453         else
 454                 seq_printf(m, "MMU Type\t: ???\n");
 455
 456         seq_printf(m, "MMU PGSZs\t: ");
 457         printed = 0;
 458         for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
 459                 if (cpu_pgsz_mask & (1UL << i)) {
 460                         seq_printf(m, "%s%s",
 461                                    printed ? "," : "", pgsz_strings[i]);
 462                         printed++;
 463                 }
 464         }
 465         seq_putc(m, '\n');
 466
 467 #ifdef CONFIG_DEBUG_DCFLUSH
 468         seq_printf(m, "DCPageFlushes\t: %d\n",
 469                    atomic_read(&dcpage_flushes));
 470 #ifdef CONFIG_SMP
 471         seq_printf(m, "DCPageFlushesXC\t: %d\n",
 472                    atomic_read(&dcpage_flushes_xcall));
 473 #endif /* CONFIG_SMP */
 474 #endif /* CONFIG_DEBUG_DCFLUSH */
 475 }
 476
 477 struct linux_prom_translation prom_trans[512] __read_mostly;
 478 unsigned int prom_trans_ents __read_mostly;
 479
 480 unsigned long kern_locked_tte_data;
 481
 482 /* The obp translations are saved based on 8k pagesize, since obp can
 483  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
 484  * HI_OBP_ADDRESS range are handled in ktlb.S.
 485  */
 486 static inline int in_obp_range(unsigned long vaddr)
 487 {
 488         return (vaddr >= LOW_OBP_ADDRESS &&
 489                 vaddr < HI_OBP_ADDRESS);
 490 }
 491
 492 static int cmp_ptrans(const void *a, const void *b)
 493 {
 494         const struct linux_prom_translation *x = a, *y = b;
 495
 496         if (x->virt > y->virt)
 497                 return 1;
 498         if (x->virt < y->virt)
 499                 return -1;
 500         return 0;
 501 }
 502
 503 /* Read OBP translations property into 'prom_trans[]'.  */
 504 static void __init read_obp_translations(void)
 505 {
 506         int n, node, ents, first, last, i;
 507
 508         node = prom_finddevice("/virtual-memory");
 509         n = prom_getproplen(node, "translations");
 510         if (unlikely(n == 0 || n == -1)) {
 511                 prom_printf("prom_mappings: Couldn't get size.\n");
 512                 prom_halt();
 513         }
 514         if (unlikely(n > sizeof(prom_trans))) {
 515                 prom_printf("prom_mappings: Size %d is too big.\n", n);
 516                 prom_halt();
 517         }
 518
 519         if ((n = prom_getproperty(node, "translations",
 520                                   (char *)&prom_trans[0],
 521                                   sizeof(prom_trans))) == -1) {
 522                 prom_printf("prom_mappings: Couldn't get property.\n");
 523                 prom_halt();
 524         }
 525
 526         n = n / sizeof(struct linux_prom_translation);
 527
 528         ents = n;
 529
 530         sort(prom_trans, ents, sizeof(struct linux_prom_translation),
 531              cmp_ptrans, NULL);
 532
 533         /* Now kick out all the non-OBP entries.  */
 534         for (i = 0; i < ents; i++) {
 535                 if (in_obp_range(prom_trans[i].virt))
 536                         break;
 537         }
 538         first = i;
 539         for (; i < ents; i++) {
 540                 if (!in_obp_range(prom_trans[i].virt))
 541                         break;
 542         }
 543         last = i;
 544
 545         for (i = 0; i < (last - first); i++) {
 546                 struct linux_prom_translation *src = &prom_trans[i + first];
 547                 struct linux_prom_translation *dest = &prom_trans[i];
 548
 549                 *dest = *src;
 550         }
 551         for (; i < ents; i++) {
 552                 struct linux_prom_translation *dest = &prom_trans[i];
 553                 dest->virt = dest->size = dest->data = 0x0UL;
 554         }
 555
 556         prom_trans_ents = last - first;
 557
 558         if (tlb_type == spitfire) {
 559                 /* Clear diag TTE bits. */
 560                 for (i = 0; i < prom_trans_ents; i++)
 561                         prom_trans[i].data &= ~0x0003fe0000000000UL;
 562         }
 563
 564         /* Force execute bit on.  */
 565         for (i = 0; i < prom_trans_ents; i++)
 566                 prom_trans[i].data |= (tlb_type == hypervisor ?
 567                                        _PAGE_EXEC_4V : _PAGE_EXEC_4U);
 568 }
 569
 570 static void __init hypervisor_tlb_lock(unsigned long vaddr,
 571                                        unsigned long pte,
 572                                        unsigned long mmu)
 573 {
 574         unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
 575
 576         if (ret != 0) {
 577                 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
 578                             "errors with %lx\n", vaddr, 0, pte, mmu, ret);
 579                 prom_halt();
 580         }
 581 }
 582
 583 static unsigned long kern_large_tte(unsigned long paddr);
 584
 585 static void __init remap_kernel(void)
 586 {
 587         unsigned long phys_page, tte_vaddr, tte_data;
 588         int i, tlb_ent = sparc64_highest_locked_tlbent();
 589
 590         tte_vaddr = (unsigned long) KERNBASE;
 591         phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
 592         tte_data = kern_large_tte(phys_page);
 593
 594         kern_locked_tte_data = tte_data;
 595
 596         /* Now lock us into the TLBs via Hypervisor or OBP. */
 597         if (tlb_type == hypervisor) {
 598                 for (i = 0; i < num_kernel_image_mappings; i++) {
 599                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
 600                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
 601                         tte_vaddr += 0x400000;
 602                         tte_data += 0x400000;
 603                 }
 604         } else {
 605                 for (i = 0; i < num_kernel_image_mappings; i++) {
 606                         prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
 607                         prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
 608                         tte_vaddr += 0x400000;
 609                         tte_data += 0x400000;
 610                 }
 611                 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
 612         }
 613         if (tlb_type == cheetah_plus) {
 614                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
 615                                             CTX_CHEETAH_PLUS_NUC);
 616                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
 617                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
 618         }
 619 }
 620
 621
 622 static void __init inherit_prom_mappings(void)
 623 {
 624         /* Now fixup OBP's idea about where we really are mapped. */
 625         printk("Remapping the kernel... ");
 626         remap_kernel();
 627         printk("done.\n");
 628 }
 629
 630 void prom_world(int enter)
 631 {
 632         if (!enter)
 633                 set_fs(get_fs());
 634
 635         __asm__ __volatile__("flushw");
 636 }
 637
 638 void __flush_dcache_range(unsigned long start, unsigned long end)
 639 {
 640         unsigned long va;
 641
 642         if (tlb_type == spitfire) {
 643                 int n = 0;
 644
 645                 for (va = start; va < end; va += 32) {
 646                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
 647                         if (++n >= 512)
 648                                 break;
 649                 }
 650         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 651                 start = __pa(start);
 652                 end = __pa(end);
 653                 for (va = start; va < end; va += 32)
 654                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 655                                              "membar #Sync"
 656                                              : /* no outputs */
 657                                              : "r" (va),
 658                                                "i" (ASI_DCACHE_INVALIDATE));
 659         }
 660 }
 661 EXPORT_SYMBOL(__flush_dcache_range);
 662
 663 /* get_new_mmu_context() uses "cache + 1".  */
 664 DEFINE_SPINLOCK(ctx_alloc_lock);
 665 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
 666 #define MAX_CTX_NR      (1UL << CTX_NR_BITS)
 667 #define CTX_BMAP_SLOTS  BITS_TO_LONGS(MAX_CTX_NR)
 668 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
 669
 670 /* Caller does TLB context flushing on local CPU if necessary.
 671  * The caller also ensures that CTX_VALID(mm->context) is false.
 672  *
 673  * We must be careful about boundary cases so that we never
 674  * let the user have CTX 0 (nucleus) or we ever use a CTX
 675  * version of zero (and thus NO_CONTEXT would not be caught
 676  * by version mis-match tests in mmu_context.h).
 677  *
 678  * Always invoked with interrupts disabled.
 679  */
 680 void get_new_mmu_context(struct mm_struct *mm)
 681 {
 682         unsigned long ctx, new_ctx;
 683         unsigned long orig_pgsz_bits;
 684         int new_version;
 685
 686         spin_lock(&ctx_alloc_lock);
 687         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
 688         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
 689         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
 690         new_version = 0;
 691         if (new_ctx >= (1 << CTX_NR_BITS)) {
 692                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
 693                 if (new_ctx >= ctx) {
 694                         int i;
 695                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
 696                                 CTX_FIRST_VERSION;
 697                         if (new_ctx == 1)
 698                                 new_ctx = CTX_FIRST_VERSION;
 699
 700                         /* Don't call memset, for 16 entries that's just
 701                          * plain silly...
 702                          */
 703                         mmu_context_bmap[0] = 3;
 704                         mmu_context_bmap[1] = 0;
 705                         mmu_context_bmap[2] = 0;
 706                         mmu_context_bmap[3] = 0;
 707                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
 708                                 mmu_context_bmap[i + 0] = 0;
 709                                 mmu_context_bmap[i + 1] = 0;
 710                                 mmu_context_bmap[i + 2] = 0;
 711                                 mmu_context_bmap[i + 3] = 0;
 712                         }
 713                         new_version = 1;
 714                         goto out;
 715                 }
 716         }
 717         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
 718         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
 719 out:
 720         tlb_context_cache = new_ctx;
 721         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
 722         spin_unlock(&ctx_alloc_lock);
 723
 724         if (unlikely(new_version))
 725                 smp_new_mmu_context_version();
 726 }
 727
 728 static int numa_enabled = 1;
 729 static int numa_debug;
 730
 731 static int __init early_numa(char *p)
 732 {
 733         if (!p)
 734                 return 0;
 735
 736         if (strstr(p, "off"))
 737                 numa_enabled = 0;
 738
 739         if (strstr(p, "debug"))
 740                 numa_debug = 1;
 741
 742         return 0;
 743 }
 744 early_param("numa", early_numa);
 745
 746 #define numadbg(f, a...) \
 747 do {    if (numa_debug) \
 748                 printk(KERN_INFO f, ## a); \
 749 } while (0)
 750
 751 static void __init find_ramdisk(unsigned long phys_base)
 752 {
 753 #ifdef CONFIG_BLK_DEV_INITRD
 754         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
 755                 unsigned long ramdisk_image;
 756
 757                 /* Older versions of the bootloader only supported a
 758                  * 32-bit physical address for the ramdisk image
 759                  * location, stored at sparc_ramdisk_image.  Newer
 760                  * SILO versions set sparc_ramdisk_image to zero and
 761                  * provide a full 64-bit physical address at
 762                  * sparc_ramdisk_image64.
 763                  */
 764                 ramdisk_image = sparc_ramdisk_image;
 765                 if (!ramdisk_image)
 766                         ramdisk_image = sparc_ramdisk_image64;
 767
 768                 /* Another bootloader quirk.  The bootloader normalizes
 769                  * the physical address to KERNBASE, so we have to
 770                  * factor that back out and add in the lowest valid
 771                  * physical page address to get the true physical address.
 772                  */
 773                 ramdisk_image -= KERNBASE;
 774                 ramdisk_image += phys_base;
 775
 776                 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
 777                         ramdisk_image, sparc_ramdisk_size);
 778
 779                 initrd_start = ramdisk_image;
 780                 initrd_end = ramdisk_image + sparc_ramdisk_size;
 781
 782                 memblock_reserve(initrd_start, sparc_ramdisk_size);
 783
 784                 initrd_start += PAGE_OFFSET;
 785                 initrd_end += PAGE_OFFSET;
 786         }
 787 #endif
 788 }
 789
 790 struct node_mem_mask {
 791         unsigned long mask;
 792         unsigned long val;
 793 };
 794 static struct node_mem_mask node_masks[MAX_NUMNODES];
 795 static int num_node_masks;
 796
 797 int numa_cpu_lookup_table[NR_CPUS];
 798 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
 799
 800 #ifdef CONFIG_NEED_MULTIPLE_NODES
 801
 802 struct mdesc_mblock {
 803         u64     base;
 804         u64     size;
 805         u64     offset; /* RA-to-PA */
 806 };
 807 static struct mdesc_mblock *mblocks;
 808 static int num_mblocks;
 809
 810 static unsigned long ra_to_pa(unsigned long addr)
 811 {
 812         int i;
 813
 814         for (i = 0; i < num_mblocks; i++) {
 815                 struct mdesc_mblock *m = &mblocks[i];
 816
 817                 if (addr >= m->base &&
 818                     addr < (m->base + m->size)) {
 819                         addr += m->offset;
 820                         break;
 821                 }
 822         }
 823         return addr;
 824 }
 825
 826 static int find_node(unsigned long addr)
 827 {
 828         int i;
 829
 830         addr = ra_to_pa(addr);
 831         for (i = 0; i < num_node_masks; i++) {
 832                 struct node_mem_mask *p = &node_masks[i];
 833
 834                 if ((addr & p->mask) == p->val)
 835                         return i;
 836         }
 837         return -1;
 838 }
 839
 840 static u64 memblock_nid_range(u64 start, u64 end, int *nid)
 841 {
 842         *nid = find_node(start);
 843         start += PAGE_SIZE;
 844         while (start < end) {
 845                 int n = find_node(start);
 846
 847                 if (n != *nid)
 848                         break;
 849                 start += PAGE_SIZE;
 850         }
 851
 852         if (start > end)
 853                 start = end;
 854
 855         return start;
 856 }
 857 #endif
 858
 859 /* This must be invoked after performing all of the necessary
 860  * memblock_set_node() calls for 'nid'.  We need to be able to get
 861  * correct data from get_pfn_range_for_nid().
 862  */
 863 static void __init allocate_node_data(int nid)
 864 {
 865         struct pglist_data *p;
 866         unsigned long start_pfn, end_pfn;
 867 #ifdef CONFIG_NEED_MULTIPLE_NODES
 868         unsigned long paddr;
 869
 870         paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
 871         if (!paddr) {
 872                 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
 873                 prom_halt();
 874         }
 875         NODE_DATA(nid) = __va(paddr);
 876         memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
 877
 878         NODE_DATA(nid)->node_id = nid;
 879 #endif
 880
 881         p = NODE_DATA(nid);
 882
 883         get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
 884         p->node_start_pfn = start_pfn;
 885         p->node_spanned_pages = end_pfn - start_pfn;
 886 }
 887
 888 static void init_node_masks_nonnuma(void)
 889 {
 890         int i;
 891
 892         numadbg("Initializing tables for non-numa.\n");
 893
 894         node_masks[0].mask = node_masks[0].val = 0;
 895         num_node_masks = 1;
 896
 897         for (i = 0; i < NR_CPUS; i++)
 898                 numa_cpu_lookup_table[i] = 0;
 899
 900         cpumask_setall(&numa_cpumask_lookup_table[0]);
 901 }
 902
 903 #ifdef CONFIG_NEED_MULTIPLE_NODES
 904 struct pglist_data *node_data[MAX_NUMNODES];
 905
 906 EXPORT_SYMBOL(numa_cpu_lookup_table);
 907 EXPORT_SYMBOL(numa_cpumask_lookup_table);
 908 EXPORT_SYMBOL(node_data);
 909
 910 struct mdesc_mlgroup {
 911         u64     node;
 912         u64     latency;
 913         u64     match;
 914         u64     mask;
 915 };
 916 static struct mdesc_mlgroup *mlgroups;
 917 static int num_mlgroups;
 918
 919 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
 920                                    u32 cfg_handle)
 921 {
 922         u64 arc;
 923
 924         mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
 925                 u64 target = mdesc_arc_target(md, arc);
 926                 const u64 *val;
 927
 928                 val = mdesc_get_property(md, target,
 929                                          "cfg-handle", NULL);
 930                 if (val && *val == cfg_handle)
 931                         return 0;
 932         }
 933         return -ENODEV;
 934 }
 935
 936 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
 937                                     u32 cfg_handle)
 938 {
 939         u64 arc, candidate, best_latency = ~(u64)0;
 940
 941         candidate = MDESC_NODE_NULL;
 942         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
 943                 u64 target = mdesc_arc_target(md, arc);
 944                 const char *name = mdesc_node_name(md, target);
 945                 const u64 *val;
 946
 947                 if (strcmp(name, "pio-latency-group"))
 948                         continue;
 949
 950                 val = mdesc_get_property(md, target, "latency", NULL);
 951                 if (!val)
 952                         continue;
 953
 954                 if (*val < best_latency) {
 955                         candidate = target;
 956                         best_latency = *val;
 957                 }
 958         }
 959
 960         if (candidate == MDESC_NODE_NULL)
 961                 return -ENODEV;
 962
 963         return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
 964 }
 965
 966 int of_node_to_nid(struct device_node *dp)
 967 {
 968         const struct linux_prom64_registers *regs;
 969         struct mdesc_handle *md;
 970         u32 cfg_handle;
 971         int count, nid;
 972         u64 grp;
 973
 974         /* This is the right thing to do on currently supported
 975          * SUN4U NUMA platforms as well, as the PCI controller does
 976          * not sit behind any particular memory controller.
 977          */
 978         if (!mlgroups)
 979                 return -1;
 980
 981         regs = of_get_property(dp, "reg", NULL);
 982         if (!regs)
 983                 return -1;
 984
 985         cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
 986
 987         md = mdesc_grab();
 988
 989         count = 0;
 990         nid = -1;
 991         mdesc_for_each_node_by_name(md, grp, "group") {
 992                 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
 993                         nid = count;
 994                         break;
 995                 }
 996                 count++;
 997         }
 998
 999         mdesc_release(md);
1000
1001         return nid;
1002 }
1003
1004 static void __init add_node_ranges(void)
1005 {
1006         struct memblock_region *reg;
1007
1008         for_each_memblock(memory, reg) {
1009                 unsigned long size = reg->size;
1010                 unsigned long start, end;
1011
1012                 start = reg->base;
1013                 end = start + size;
1014                 while (start < end) {
1015                         unsigned long this_end;
1016                         int nid;
1017
1018                         this_end = memblock_nid_range(start, end, &nid);
1019
1020                         numadbg("Setting memblock NUMA node nid[%d] "
1021                                 "start[%lx] end[%lx]\n",
1022                                 nid, start, this_end);
1023
1024                         memblock_set_node(start, this_end - start, nid);
1025                         start = this_end;
1026                 }
1027         }
1028 }
1029
1030 static int __init grab_mlgroups(struct mdesc_handle *md)
1031 {
1032         unsigned long paddr;
1033         int count = 0;
1034         u64 node;
1035
1036         mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1037                 count++;
1038         if (!count)
1039                 return -ENOENT;
1040
1041         paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
1042                           SMP_CACHE_BYTES);
1043         if (!paddr)
1044                 return -ENOMEM;
1045
1046         mlgroups = __va(paddr);
1047         num_mlgroups = count;
1048
1049         count = 0;
1050         mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1051                 struct mdesc_mlgroup *m = &mlgroups[count++];
1052                 const u64 *val;
1053
1054                 m->node = node;
1055
1056                 val = mdesc_get_property(md, node, "latency", NULL);
1057                 m->latency = *val;
1058                 val = mdesc_get_property(md, node, "address-match", NULL);
1059                 m->match = *val;
1060                 val = mdesc_get_property(md, node, "address-mask", NULL);
1061                 m->mask = *val;
1062
1063                 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1064                         "match[%llx] mask[%llx]\n",
1065                         count - 1, m->node, m->latency, m->match, m->mask);
1066         }
1067
1068         return 0;
1069 }
1070
1071 static int __init grab_mblocks(struct mdesc_handle *md)
1072 {
1073         unsigned long paddr;
1074         int count = 0;
1075         u64 node;
1076
1077         mdesc_for_each_node_by_name(md, node, "mblock")
1078                 count++;
1079         if (!count)
1080                 return -ENOENT;
1081
1082         paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
1083                           SMP_CACHE_BYTES);
1084         if (!paddr)
1085                 return -ENOMEM;
1086
1087         mblocks = __va(paddr);
1088         num_mblocks = count;
1089
1090         count = 0;
1091         mdesc_for_each_node_by_name(md, node, "mblock") {
1092                 struct mdesc_mblock *m = &mblocks[count++];
1093                 const u64 *val;
1094
1095                 val = mdesc_get_property(md, node, "base", NULL);
1096                 m->base = *val;
1097                 val = mdesc_get_property(md, node, "size", NULL);
1098                 m->size = *val;
1099                 val = mdesc_get_property(md, node,
1100                                          "address-congruence-offset", NULL);
1101
1102                 /* The address-congruence-offset property is optional.
1103                  * Explicity zero it be identifty this.
1104                  */
1105                 if (val)
1106                         m->offset = *val;
1107                 else
1108                         m->offset = 0UL;
1109
1110                 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1111                         count - 1, m->base, m->size, m->offset);
1112         }
1113
1114         return 0;
1115 }
1116
1117 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1118                                                u64 grp, cpumask_t *mask)
1119 {
1120         u64 arc;
1121
1122         cpumask_clear(mask);
1123
1124         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1125                 u64 target = mdesc_arc_target(md, arc);
1126                 const char *name = mdesc_node_name(md, target);
1127                 const u64 *id;
1128
1129                 if (strcmp(name, "cpu"))
1130                         continue;
1131                 id = mdesc_get_property(md, target, "id", NULL);
1132                 if (*id < nr_cpu_ids)
1133                         cpumask_set_cpu(*id, mask);
1134         }
1135 }
1136
1137 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1138 {
1139         int i;
1140
1141         for (i = 0; i < num_mlgroups; i++) {
1142                 struct mdesc_mlgroup *m = &mlgroups[i];
1143                 if (m->node == node)
1144                         return m;
1145         }
1146         return NULL;
1147 }
1148
1149 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1150                                       int index)
1151 {
1152         struct mdesc_mlgroup *candidate = NULL;
1153         u64 arc, best_latency = ~(u64)0;
1154         struct node_mem_mask *n;
1155
1156         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1157                 u64 target = mdesc_arc_target(md, arc);
1158                 struct mdesc_mlgroup *m = find_mlgroup(target);
1159                 if (!m)
1160                         continue;
1161                 if (m->latency < best_latency) {
1162                         candidate = m;
1163                         best_latency = m->latency;
1164                 }
1165         }
1166         if (!candidate)
1167                 return -ENOENT;
1168
1169         if (num_node_masks != index) {
1170                 printk(KERN_ERR "Inconsistent NUMA state, "
1171                        "index[%d] != num_node_masks[%d]\n",
1172                        index, num_node_masks);
1173                 return -EINVAL;
1174         }
1175
1176         n = &node_masks[num_node_masks++];
1177
1178         n->mask = candidate->mask;
1179         n->val = candidate->match;
1180
1181         numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
1182                 index, n->mask, n->val, candidate->latency);
1183
1184         return 0;
1185 }
1186
1187 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1188                                          int index)
1189 {
1190         cpumask_t mask;
1191         int cpu;
1192
1193         numa_parse_mdesc_group_cpus(md, grp, &mask);
1194
1195         for_each_cpu(cpu, &mask)
1196                 numa_cpu_lookup_table[cpu] = index;
1197         cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1198
1199         if (numa_debug) {
1200                 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1201                 for_each_cpu(cpu, &mask)
1202                         printk("%d ", cpu);
1203                 printk("]\n");
1204         }
1205
1206         return numa_attach_mlgroup(md, grp, index);
1207 }
1208
1209 static int __init numa_parse_mdesc(void)
1210 {
1211         struct mdesc_handle *md = mdesc_grab();
1212         int i, err, count;
1213         u64 node;
1214
1215         node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1216         if (node == MDESC_NODE_NULL) {
1217                 mdesc_release(md);
1218                 return -ENOENT;
1219         }
1220
1221         err = grab_mblocks(md);
1222         if (err < 0)
1223                 goto out;
1224
1225         err = grab_mlgroups(md);
1226         if (err < 0)
1227                 goto out;
1228
1229         count = 0;
1230         mdesc_for_each_node_by_name(md, node, "group") {
1231                 err = numa_parse_mdesc_group(md, node, count);
1232                 if (err < 0)
1233                         break;
1234                 count++;
1235         }
1236
1237         add_node_ranges();
1238
1239         for (i = 0; i < num_node_masks; i++) {
1240                 allocate_node_data(i);
1241                 node_set_online(i);
1242         }
1243
1244         err = 0;
1245 out:
1246         mdesc_release(md);
1247         return err;
1248 }
1249
1250 static int __init numa_parse_jbus(void)
1251 {
1252         unsigned long cpu, index;
1253
1254         /* NUMA node id is encoded in bits 36 and higher, and there is
1255          * a 1-to-1 mapping from CPU ID to NUMA node ID.
1256          */
1257         index = 0;
1258         for_each_present_cpu(cpu) {
1259                 numa_cpu_lookup_table[cpu] = index;
1260                 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1261                 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1262                 node_masks[index].val = cpu << 36UL;
1263
1264                 index++;
1265         }
1266         num_node_masks = index;
1267
1268         add_node_ranges();
1269
1270         for (index = 0; index < num_node_masks; index++) {
1271                 allocate_node_data(index);
1272                 node_set_online(index);
1273         }
1274
1275         return 0;
1276 }
1277
1278 static int __init numa_parse_sun4u(void)
1279 {
1280         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1281                 unsigned long ver;
1282
1283                 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1284                 if ((ver >> 32UL) == __JALAPENO_ID ||
1285                     (ver >> 32UL) == __SERRANO_ID)
1286                         return numa_parse_jbus();
1287         }
1288         return -1;
1289 }
1290
1291 static int __init bootmem_init_numa(void)
1292 {
1293         int err = -1;
1294
1295         numadbg("bootmem_init_numa()\n");
1296
1297         if (numa_enabled) {
1298                 if (tlb_type == hypervisor)
1299                         err = numa_parse_mdesc();
1300                 else
1301                         err = numa_parse_sun4u();
1302         }
1303         return err;
1304 }
1305
1306 #else
1307
1308 static int bootmem_init_numa(void)
1309 {
1310         return -1;
1311 }
1312
1313 #endif
1314
1315 static void __init bootmem_init_nonnuma(void)
1316 {
1317         unsigned long top_of_ram = memblock_end_of_DRAM();
1318         unsigned long total_ram = memblock_phys_mem_size();
1319
1320         numadbg("bootmem_init_nonnuma()\n");
1321
1322         printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1323                top_of_ram, total_ram);
1324         printk(KERN_INFO "Memory hole size: %ldMB\n",
1325                (top_of_ram - total_ram) >> 20);
1326
1327         init_node_masks_nonnuma();
1328         memblock_set_node(0, (phys_addr_t)ULLONG_MAX, 0);
1329         allocate_node_data(0);
1330         node_set_online(0);
1331 }
1332
1333 static unsigned long __init bootmem_init(unsigned long phys_base)
1334 {
1335         unsigned long end_pfn;
1336
1337         end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1338         max_pfn = max_low_pfn = end_pfn;
1339         min_low_pfn = (phys_base >> PAGE_SHIFT);
1340
1341         if (bootmem_init_numa() < 0)
1342                 bootmem_init_nonnuma();
1343
1344         /* Dump memblock with node info. */
1345         memblock_dump_all();
1346
1347         /* XXX cpu notifier XXX */
1348
1349         sparse_memory_present_with_active_regions(MAX_NUMNODES);
1350         sparse_init();
1351
1352         return end_pfn;
1353 }
1354
1355 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1356 static int pall_ents __initdata;
1357
1358 #ifdef CONFIG_DEBUG_PAGEALLOC
1359 static unsigned long __ref kernel_map_range(unsigned long pstart,
1360                                             unsigned long pend, pgprot_t prot)
1361 {
1362         unsigned long vstart = PAGE_OFFSET + pstart;
1363         unsigned long vend = PAGE_OFFSET + pend;
1364         unsigned long alloc_bytes = 0UL;
1365
1366         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1367                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1368                             vstart, vend);
1369                 prom_halt();
1370         }
1371
1372         while (vstart < vend) {
1373                 unsigned long this_end, paddr = __pa(vstart);
1374                 pgd_t *pgd = pgd_offset_k(vstart);
1375                 pud_t *pud;
1376                 pmd_t *pmd;
1377                 pte_t *pte;
1378
1379                 pud = pud_offset(pgd, vstart);
1380                 if (pud_none(*pud)) {
1381                         pmd_t *new;
1382
1383                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1384                         alloc_bytes += PAGE_SIZE;
1385                         pud_populate(&init_mm, pud, new);
1386                 }
1387
1388                 pmd = pmd_offset(pud, vstart);
1389                 if (!pmd_present(*pmd)) {
1390                         pte_t *new;
1391
1392                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1393                         alloc_bytes += PAGE_SIZE;
1394                         pmd_populate_kernel(&init_mm, pmd, new);
1395                 }
1396
1397                 pte = pte_offset_kernel(pmd, vstart);
1398                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1399                 if (this_end > vend)
1400                         this_end = vend;
1401
1402                 while (vstart < this_end) {
1403                         pte_val(*pte) = (paddr | pgprot_val(prot));
1404
1405                         vstart += PAGE_SIZE;
1406                         paddr += PAGE_SIZE;
1407                         pte++;
1408                 }
1409         }
1410
1411         return alloc_bytes;
1412 }
1413
1414 extern unsigned int kvmap_linear_patch[1];
1415 #endif /* CONFIG_DEBUG_PAGEALLOC */
1416
1417 static void __init kpte_set_val(unsigned long index, unsigned long val)
1418 {
1419         unsigned long *ptr = kpte_linear_bitmap;
1420
1421         val <<= ((index % (BITS_PER_LONG / 2)) * 2);
1422         ptr += (index / (BITS_PER_LONG / 2));
1423
1424         *ptr |= val;
1425 }
1426
1427 static const unsigned long kpte_shift_min = 28; /* 256MB */
1428 static const unsigned long kpte_shift_max = 34; /* 16GB */
1429 static const unsigned long kpte_shift_incr = 3;
1430
1431 static unsigned long kpte_mark_using_shift(unsigned long start, unsigned long end,
1432                                            unsigned long shift)
1433 {
1434         unsigned long size = (1UL << shift);
1435         unsigned long mask = (size - 1UL);
1436         unsigned long remains = end - start;
1437         unsigned long val;
1438
1439         if (remains < size || (start & mask))
1440                 return start;
1441
1442         /* VAL maps:
1443          *
1444          *      shift 28 --> kern_linear_pte_xor index 1
1445          *      shift 31 --> kern_linear_pte_xor index 2
1446          *      shift 34 --> kern_linear_pte_xor index 3
1447          */
1448         val = ((shift - kpte_shift_min) / kpte_shift_incr) + 1;
1449
1450         remains &= ~mask;
1451         if (shift != kpte_shift_max)
1452                 remains = size;
1453
1454         while (remains) {
1455                 unsigned long index = start >> kpte_shift_min;
1456
1457                 kpte_set_val(index, val);
1458
1459                 start += 1UL << kpte_shift_min;
1460                 remains -= 1UL << kpte_shift_min;
1461         }
1462
1463         return start;
1464 }
1465
1466 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1467 {
1468         unsigned long smallest_size, smallest_mask;
1469         unsigned long s;
1470
1471         smallest_size = (1UL << kpte_shift_min);
1472         smallest_mask = (smallest_size - 1UL);
1473
1474         while (start < end) {
1475                 unsigned long orig_start = start;
1476
1477                 for (s = kpte_shift_max; s >= kpte_shift_min; s -= kpte_shift_incr) {
1478                         start = kpte_mark_using_shift(start, end, s);
1479
1480                         if (start != orig_start)
1481                                 break;
1482                 }
1483
1484                 if (start == orig_start)
1485                         start = (start + smallest_size) & ~smallest_mask;
1486         }
1487 }
1488
1489 static void __init init_kpte_bitmap(void)
1490 {
1491         unsigned long i;
1492
1493         for (i = 0; i < pall_ents; i++) {
1494                 unsigned long phys_start, phys_end;
1495
1496                 phys_start = pall[i].phys_addr;
1497                 phys_end = phys_start + pall[i].reg_size;
1498
1499                 mark_kpte_bitmap(phys_start, phys_end);
1500         }
1501 }
1502
1503 static void __init kernel_physical_mapping_init(void)
1504 {
1505 #ifdef CONFIG_DEBUG_PAGEALLOC
1506         unsigned long i, mem_alloced = 0UL;
1507
1508         for (i = 0; i < pall_ents; i++) {
1509                 unsigned long phys_start, phys_end;
1510
1511                 phys_start = pall[i].phys_addr;
1512                 phys_end = phys_start + pall[i].reg_size;
1513
1514                 mem_alloced += kernel_map_range(phys_start, phys_end,
1515                                                 PAGE_KERNEL);
1516         }
1517
1518         printk("Allocated %ld bytes for kernel page tables.\n",
1519                mem_alloced);
1520
1521         kvmap_linear_patch[0] = 0x01000000; /* nop */
1522         flushi(&kvmap_linear_patch[0]);
1523
1524         __flush_tlb_all();
1525 #endif
1526 }
1527
1528 #ifdef CONFIG_DEBUG_PAGEALLOC
1529 void kernel_map_pages(struct page *page, int numpages, int enable)
1530 {
1531         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1532         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1533
1534         kernel_map_range(phys_start, phys_end,
1535                          (enable ? PAGE_KERNEL : __pgprot(0)));
1536
1537         flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1538                                PAGE_OFFSET + phys_end);
1539
1540         /* we should perform an IPI and flush all tlbs,
1541          * but that can deadlock->flush only current cpu.
1542          */
1543         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1544                                  PAGE_OFFSET + phys_end);
1545 }
1546 #endif
1547
1548 unsigned long __init find_ecache_flush_span(unsigned long size)
1549 {
1550         int i;
1551
1552         for (i = 0; i < pavail_ents; i++) {
1553                 if (pavail[i].reg_size >= size)
1554                         return pavail[i].phys_addr;
1555         }
1556
1557         return ~0UL;
1558 }
1559
1560 unsigned long PAGE_OFFSET;
1561 EXPORT_SYMBOL(PAGE_OFFSET);
1562
1563 static void __init page_offset_shift_patch_one(unsigned int *insn, unsigned long phys_bits)
1564 {
1565         unsigned long final_shift;
1566         unsigned int val = *insn;
1567         unsigned int cnt;
1568
1569         /* We are patching in ilog2(max_supported_phys_address), and
1570          * we are doing so in a manner similar to a relocation addend.
1571          * That is, we are adding the shift value to whatever value
1572          * is in the shift instruction count field already.
1573          */
1574         cnt = (val & 0x3f);
1575         val &= ~0x3f;
1576
1577         /* If we are trying to shift >= 64 bits, clear the destination
1578          * register.  This can happen when phys_bits ends up being equal
1579          * to MAX_PHYS_ADDRESS_BITS.
1580          */
1581         final_shift = (cnt + (64 - phys_bits));
1582         if (final_shift >= 64) {
1583                 unsigned int rd = (val >> 25) & 0x1f;
1584
1585                 val = 0x80100000 | (rd << 25);
1586         } else {
1587                 val |= final_shift;
1588         }
1589         *insn = val;
1590
1591         __asm__ __volatile__("flush     %0"
1592                              : /* no outputs */
1593                              : "r" (insn));
1594 }
1595
1596 static void __init page_offset_shift_patch(unsigned long phys_bits)
1597 {
1598         extern unsigned int __page_offset_shift_patch;
1599         extern unsigned int __page_offset_shift_patch_end;
1600         unsigned int *p;
1601
1602         p = &__page_offset_shift_patch;
1603         while (p < &__page_offset_shift_patch_end) {
1604                 unsigned int *insn = (unsigned int *)(unsigned long)*p;
1605
1606                 page_offset_shift_patch_one(insn, phys_bits);
1607
1608                 p++;
1609         }
1610 }
1611
1612 static void __init setup_page_offset(void)
1613 {
1614         unsigned long max_phys_bits = 40;
1615
1616         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1617                 max_phys_bits = 42;
1618         } else if (tlb_type == hypervisor) {
1619                 switch (sun4v_chip_type) {
1620                 case SUN4V_CHIP_NIAGARA1:
1621                 case SUN4V_CHIP_NIAGARA2:
1622                         max_phys_bits = 39;
1623                         break;
1624                 case SUN4V_CHIP_NIAGARA3:
1625                         max_phys_bits = 43;
1626                         break;
1627                 case SUN4V_CHIP_NIAGARA4:
1628                 case SUN4V_CHIP_NIAGARA5:
1629                 case SUN4V_CHIP_SPARC64X:
1630                 default:
1631                         max_phys_bits = 47;
1632                         break;
1633                 }
1634         }
1635
1636         if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
1637                 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
1638                             max_phys_bits);
1639                 prom_halt();
1640         }
1641
1642         PAGE_OFFSET = PAGE_OFFSET_BY_BITS(max_phys_bits);
1643
1644         pr_info("PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
1645                 PAGE_OFFSET, max_phys_bits);
1646
1647         page_offset_shift_patch(max_phys_bits);
1648 }
1649
1650 static void __init tsb_phys_patch(void)
1651 {
1652         struct tsb_ldquad_phys_patch_entry *pquad;
1653         struct tsb_phys_patch_entry *p;
1654
1655         pquad = &__tsb_ldquad_phys_patch;
1656         while (pquad < &__tsb_ldquad_phys_patch_end) {
1657                 unsigned long addr = pquad->addr;
1658
1659                 if (tlb_type == hypervisor)
1660                         *(unsigned int *) addr = pquad->sun4v_insn;
1661                 else
1662                         *(unsigned int *) addr = pquad->sun4u_insn;
1663                 wmb();
1664                 __asm__ __volatile__("flush     %0"
1665                                      : /* no outputs */
1666                                      : "r" (addr));
1667
1668                 pquad++;
1669         }
1670
1671         p = &__tsb_phys_patch;
1672         while (p < &__tsb_phys_patch_end) {
1673                 unsigned long addr = p->addr;
1674
1675                 *(unsigned int *) addr = p->insn;
1676                 wmb();
1677                 __asm__ __volatile__("flush     %0"
1678                                      : /* no outputs */
1679                                      : "r" (addr));
1680
1681                 p++;
1682         }
1683 }
1684
1685 /* Don't mark as init, we give this to the Hypervisor.  */
1686 #ifndef CONFIG_DEBUG_PAGEALLOC
1687 #define NUM_KTSB_DESCR  2
1688 #else
1689 #define NUM_KTSB_DESCR  1
1690 #endif
1691 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1692 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1693
1694 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
1695 {
1696         pa >>= KTSB_PHYS_SHIFT;
1697
1698         while (start < end) {
1699                 unsigned int *ia = (unsigned int *)(unsigned long)*start;
1700
1701                 ia[0] = (ia[0] & ~0x3fffff) | (pa >> 10);
1702                 __asm__ __volatile__("flush     %0" : : "r" (ia));
1703
1704                 ia[1] = (ia[1] & ~0x3ff) | (pa & 0x3ff);
1705                 __asm__ __volatile__("flush     %0" : : "r" (ia + 1));
1706
1707                 start++;
1708         }
1709 }
1710
1711 static void ktsb_phys_patch(void)
1712 {
1713         extern unsigned int __swapper_tsb_phys_patch;
1714         extern unsigned int __swapper_tsb_phys_patch_end;
1715         unsigned long ktsb_pa;
1716
1717         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1718         patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
1719                             &__swapper_tsb_phys_patch_end, ktsb_pa);
1720 #ifndef CONFIG_DEBUG_PAGEALLOC
1721         {
1722         extern unsigned int __swapper_4m_tsb_phys_patch;
1723         extern unsigned int __swapper_4m_tsb_phys_patch_end;
1724         ktsb_pa = (kern_base +
1725                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1726         patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
1727                             &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
1728         }
1729 #endif
1730 }
1731
1732 static void __init sun4v_ktsb_init(void)
1733 {
1734         unsigned long ktsb_pa;
1735
1736         /* First KTSB for PAGE_SIZE mappings.  */
1737         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1738
1739         switch (PAGE_SIZE) {
1740         case 8 * 1024:
1741         default:
1742                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1743                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1744                 break;
1745
1746         case 64 * 1024:
1747                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1748                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1749                 break;
1750
1751         case 512 * 1024:
1752                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1753                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1754                 break;
1755
1756         case 4 * 1024 * 1024:
1757                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1758                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1759                 break;
1760         }
1761
1762         ktsb_descr[0].assoc = 1;
1763         ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1764         ktsb_descr[0].ctx_idx = 0;
1765         ktsb_descr[0].tsb_base = ktsb_pa;
1766         ktsb_descr[0].resv = 0;
1767
1768 #ifndef CONFIG_DEBUG_PAGEALLOC
1769         /* Second KTSB for 4MB/256MB/2GB/16GB mappings.  */
1770         ktsb_pa = (kern_base +
1771                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1772
1773         ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1774         ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
1775                                     HV_PGSZ_MASK_256MB |
1776                                     HV_PGSZ_MASK_2GB |
1777                                     HV_PGSZ_MASK_16GB) &
1778                                    cpu_pgsz_mask);
1779         ktsb_descr[1].assoc = 1;
1780         ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1781         ktsb_descr[1].ctx_idx = 0;
1782         ktsb_descr[1].tsb_base = ktsb_pa;
1783         ktsb_descr[1].resv = 0;
1784 #endif
1785 }
1786
1787 void sun4v_ktsb_register(void)
1788 {
1789         unsigned long pa, ret;
1790
1791         pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1792
1793         ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1794         if (ret != 0) {
1795                 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1796                             "errors with %lx\n", pa, ret);
1797                 prom_halt();
1798         }
1799 }
1800
1801 static void __init sun4u_linear_pte_xor_finalize(void)
1802 {
1803 #ifndef CONFIG_DEBUG_PAGEALLOC
1804         /* This is where we would add Panther support for
1805          * 32MB and 256MB pages.
1806          */
1807 #endif
1808 }
1809
1810 static void __init sun4v_linear_pte_xor_finalize(void)
1811 {
1812 #ifndef CONFIG_DEBUG_PAGEALLOC
1813         if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
1814                 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1815                         PAGE_OFFSET;
1816                 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1817                                            _PAGE_P_4V | _PAGE_W_4V);
1818         } else {
1819                 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1820         }
1821
1822         if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
1823                 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
1824                         PAGE_OFFSET;
1825                 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1826                                            _PAGE_P_4V | _PAGE_W_4V);
1827         } else {
1828                 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
1829         }
1830
1831         if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
1832                 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
1833                         PAGE_OFFSET;
1834                 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1835                                            _PAGE_P_4V | _PAGE_W_4V);
1836         } else {
1837                 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
1838         }
1839 #endif
1840 }
1841
1842 /* paging_init() sets up the page tables */
1843
1844 static unsigned long last_valid_pfn;
1845 pgd_t swapper_pg_dir[PTRS_PER_PGD];
1846
1847 static void sun4u_pgprot_init(void);
1848 static void sun4v_pgprot_init(void);
1849
1850 void __init paging_init(void)
1851 {
1852         unsigned long end_pfn, shift, phys_base;
1853         unsigned long real_end, i;
1854         int node;
1855
1856         setup_page_offset();
1857
1858         /* These build time checkes make sure that the dcache_dirty_cpu()
1859          * page->flags usage will work.
1860          *
1861          * When a page gets marked as dcache-dirty, we store the
1862          * cpu number starting at bit 32 in the page->flags.  Also,
1863          * functions like clear_dcache_dirty_cpu use the cpu mask
1864          * in 13-bit signed-immediate instruction fields.
1865          */
1866
1867         /*
1868          * Page flags must not reach into upper 32 bits that are used
1869          * for the cpu number
1870          */
1871         BUILD_BUG_ON(NR_PAGEFLAGS > 32);
1872
1873         /*
1874          * The bit fields placed in the high range must not reach below
1875          * the 32 bit boundary. Otherwise we cannot place the cpu field
1876          * at the 32 bit boundary.
1877          */
1878         BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1879                 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
1880
1881         BUILD_BUG_ON(NR_CPUS > 4096);
1882
1883         kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1884         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1885
1886         /* Invalidate both kernel TSBs.  */
1887         memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1888 #ifndef CONFIG_DEBUG_PAGEALLOC
1889         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1890 #endif
1891
1892         if (tlb_type == hypervisor)
1893                 sun4v_pgprot_init();
1894         else
1895                 sun4u_pgprot_init();
1896
1897         if (tlb_type == cheetah_plus ||
1898             tlb_type == hypervisor) {
1899                 tsb_phys_patch();
1900                 ktsb_phys_patch();
1901         }
1902
1903         if (tlb_type == hypervisor)
1904                 sun4v_patch_tlb_handlers();
1905
1906         /* Find available physical memory...
1907          *
1908          * Read it twice in order to work around a bug in openfirmware.
1909          * The call to grab this table itself can cause openfirmware to
1910          * allocate memory, which in turn can take away some space from
1911          * the list of available memory.  Reading it twice makes sure
1912          * we really do get the final value.
1913          */
1914         read_obp_translations();
1915         read_obp_memory("reg", &pall[0], &pall_ents);
1916         read_obp_memory("available", &pavail[0], &pavail_ents);
1917         read_obp_memory("available", &pavail[0], &pavail_ents);
1918
1919         phys_base = 0xffffffffffffffffUL;
1920         for (i = 0; i < pavail_ents; i++) {
1921                 phys_base = min(phys_base, pavail[i].phys_addr);
1922                 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
1923         }
1924
1925         memblock_reserve(kern_base, kern_size);
1926
1927         find_ramdisk(phys_base);
1928
1929         memblock_enforce_memory_limit(cmdline_memory_size);
1930
1931         memblock_allow_resize();
1932         memblock_dump_all();
1933
1934         set_bit(0, mmu_context_bmap);
1935
1936         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1937
1938         real_end = (unsigned long)_end;
1939         num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22);
1940         printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1941                num_kernel_image_mappings);
1942
1943         /* Set kernel pgd to upper alias so physical page computations
1944          * work.
1945          */
1946         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1947
1948         memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1949
1950         /* Now can init the kernel/bad page tables. */
1951         pud_set(pud_offset(&swapper_pg_dir[0], 0),
1952                 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1953
1954         inherit_prom_mappings();
1955
1956         init_kpte_bitmap();
1957
1958         /* Ok, we can use our TLB miss and window trap handlers safely.  */
1959         setup_tba();
1960
1961         __flush_tlb_all();
1962
1963         prom_build_devicetree();
1964         of_populate_present_mask();
1965 #ifndef CONFIG_SMP
1966         of_fill_in_cpu_data();
1967 #endif
1968
1969         if (tlb_type == hypervisor) {
1970                 sun4v_mdesc_init();
1971                 mdesc_populate_present_mask(cpu_all_mask);
1972 #ifndef CONFIG_SMP
1973                 mdesc_fill_in_cpu_data(cpu_all_mask);
1974 #endif
1975                 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
1976
1977                 sun4v_linear_pte_xor_finalize();
1978
1979                 sun4v_ktsb_init();
1980                 sun4v_ktsb_register();
1981         } else {
1982                 unsigned long impl, ver;
1983
1984                 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
1985                                  HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
1986
1987                 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
1988                 impl = ((ver >> 32) & 0xffff);
1989                 if (impl == PANTHER_IMPL)
1990                         cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
1991                                           HV_PGSZ_MASK_256MB);
1992
1993                 sun4u_linear_pte_xor_finalize();
1994         }
1995
1996         /* Flush the TLBs and the 4M TSB so that the updated linear
1997          * pte XOR settings are realized for all mappings.
1998          */
1999         __flush_tlb_all();
2000 #ifndef CONFIG_DEBUG_PAGEALLOC
2001         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2002 #endif
2003         __flush_tlb_all();
2004
2005         /* Setup bootmem... */
2006         last_valid_pfn = end_pfn = bootmem_init(phys_base);
2007
2008         /* Once the OF device tree and MDESC have been setup, we know
2009          * the list of possible cpus.  Therefore we can allocate the
2010          * IRQ stacks.
2011          */
2012         for_each_possible_cpu(i) {
2013                 node = cpu_to_node(i);
2014
2015                 softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
2016                                                         THREAD_SIZE,
2017                                                         THREAD_SIZE, 0);
2018                 hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
2019                                                         THREAD_SIZE,
2020                                                         THREAD_SIZE, 0);
2021         }
2022
2023         kernel_physical_mapping_init();
2024
2025         {
2026                 unsigned long max_zone_pfns[MAX_NR_ZONES];
2027
2028                 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
2029
2030                 max_zone_pfns[ZONE_NORMAL] = end_pfn;
2031
2032                 free_area_init_nodes(max_zone_pfns);
2033         }
2034
2035         printk("Booting Linux...\n");
2036 }
2037
2038 int page_in_phys_avail(unsigned long paddr)
2039 {
2040         int i;
2041
2042         paddr &= PAGE_MASK;
2043
2044         for (i = 0; i < pavail_ents; i++) {
2045                 unsigned long start, end;
2046
2047                 start = pavail[i].phys_addr;
2048                 end = start + pavail[i].reg_size;
2049
2050                 if (paddr >= start && paddr < end)
2051                         return 1;
2052         }
2053         if (paddr >= kern_base && paddr < (kern_base + kern_size))
2054                 return 1;
2055 #ifdef CONFIG_BLK_DEV_INITRD
2056         if (paddr >= __pa(initrd_start) &&
2057             paddr < __pa(PAGE_ALIGN(initrd_end)))
2058                 return 1;
2059 #endif
2060
2061         return 0;
2062 }
2063
2064 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
2065 static int pavail_rescan_ents __initdata;
2066
2067 /* Certain OBP calls, such as fetching "available" properties, can
2068  * claim physical memory.  So, along with initializing the valid
2069  * address bitmap, what we do here is refetch the physical available
2070  * memory list again, and make sure it provides at least as much
2071  * memory as 'pavail' does.
2072  */
2073 static void __init setup_valid_addr_bitmap_from_pavail(unsigned long *bitmap)
2074 {
2075         int i;
2076
2077         read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
2078
2079         for (i = 0; i < pavail_ents; i++) {
2080                 unsigned long old_start, old_end;
2081
2082                 old_start = pavail[i].phys_addr;
2083                 old_end = old_start + pavail[i].reg_size;
2084                 while (old_start < old_end) {
2085                         int n;
2086
2087                         for (n = 0; n < pavail_rescan_ents; n++) {
2088                                 unsigned long new_start, new_end;
2089
2090                                 new_start = pavail_rescan[n].phys_addr;
2091                                 new_end = new_start +
2092                                         pavail_rescan[n].reg_size;
2093
2094                                 if (new_start <= old_start &&
2095                                     new_end >= (old_start + PAGE_SIZE)) {
2096                                         set_bit(old_start >> 22, bitmap);
2097                                         goto do_next_page;
2098                                 }
2099                         }
2100
2101                         prom_printf("mem_init: Lost memory in pavail\n");
2102                         prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
2103                                     pavail[i].phys_addr,
2104                                     pavail[i].reg_size);
2105                         prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
2106                                     pavail_rescan[i].phys_addr,
2107                                     pavail_rescan[i].reg_size);
2108                         prom_printf("mem_init: Cannot continue, aborting.\n");
2109                         prom_halt();
2110
2111                 do_next_page:
2112                         old_start += PAGE_SIZE;
2113                 }
2114         }
2115 }
2116
2117 static void __init patch_tlb_miss_handler_bitmap(void)
2118 {
2119         extern unsigned int valid_addr_bitmap_insn[];
2120         extern unsigned int valid_addr_bitmap_patch[];
2121
2122         valid_addr_bitmap_insn[1] = valid_addr_bitmap_patch[1];
2123         mb();
2124         valid_addr_bitmap_insn[0] = valid_addr_bitmap_patch[0];
2125         flushi(&valid_addr_bitmap_insn[0]);
2126 }
2127
2128 static void __init register_page_bootmem_info(void)
2129 {
2130 #ifdef CONFIG_NEED_MULTIPLE_NODES
2131         int i;
2132
2133         for_each_online_node(i)
2134                 if (NODE_DATA(i)->node_spanned_pages)
2135                         register_page_bootmem_info_node(NODE_DATA(i));
2136 #endif
2137 }
2138 void __init mem_init(void)
2139 {
2140         unsigned long addr, last;
2141
2142         addr = PAGE_OFFSET + kern_base;
2143         last = PAGE_ALIGN(kern_size) + addr;
2144         while (addr < last) {
2145                 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
2146                 addr += PAGE_SIZE;
2147         }
2148
2149         setup_valid_addr_bitmap_from_pavail(sparc64_valid_addr_bitmap);
2150         patch_tlb_miss_handler_bitmap();
2151
2152         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2153
2154         register_page_bootmem_info();
2155         free_all_bootmem();
2156
2157         /*
2158          * Set up the zero page, mark it reserved, so that page count
2159          * is not manipulated when freeing the page from user ptes.
2160          */
2161         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2162         if (mem_map_zero == NULL) {
2163                 prom_printf("paging_init: Cannot alloc zero page.\n");
2164                 prom_halt();
2165         }
2166         mark_page_reserved(mem_map_zero);
2167
2168         mem_init_print_info(NULL);
2169
2170         if (tlb_type == cheetah || tlb_type == cheetah_plus)
2171                 cheetah_ecache_flush_init();
2172 }
2173
2174 void free_initmem(void)
2175 {
2176         unsigned long addr, initend;
2177         int do_free = 1;
2178
2179         /* If the physical memory maps were trimmed by kernel command
2180          * line options, don't even try freeing this initmem stuff up.
2181          * The kernel image could have been in the trimmed out region
2182          * and if so the freeing below will free invalid page structs.
2183          */
2184         if (cmdline_memory_size)
2185                 do_free = 0;
2186
2187         /*
2188          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2189          */
2190         addr = PAGE_ALIGN((unsigned long)(__init_begin));
2191         initend = (unsigned long)(__init_end) & PAGE_MASK;
2192         for (; addr < initend; addr += PAGE_SIZE) {
2193                 unsigned long page;
2194
2195                 page = (addr +
2196                         ((unsigned long) __va(kern_base)) -
2197                         ((unsigned long) KERNBASE));
2198                 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2199
2200                 if (do_free)
2201                         free_reserved_page(virt_to_page(page));
2202         }
2203 }
2204
2205 #ifdef CONFIG_BLK_DEV_INITRD
2206 void free_initrd_mem(unsigned long start, unsigned long end)
2207 {
2208         free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
2209                            "initrd");
2210 }
2211 #endif
2212
2213 #define _PAGE_CACHE_4U  (_PAGE_CP_4U | _PAGE_CV_4U)
2214 #define _PAGE_CACHE_4V  (_PAGE_CP_4V | _PAGE_CV_4V)
2215 #define __DIRTY_BITS_4U  (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2216 #define __DIRTY_BITS_4V  (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2217 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2218 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2219
2220 pgprot_t PAGE_KERNEL __read_mostly;
2221 EXPORT_SYMBOL(PAGE_KERNEL);
2222
2223 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2224 pgprot_t PAGE_COPY __read_mostly;
2225
2226 pgprot_t PAGE_SHARED __read_mostly;
2227 EXPORT_SYMBOL(PAGE_SHARED);
2228
2229 unsigned long pg_iobits __read_mostly;
2230
2231 unsigned long _PAGE_IE __read_mostly;
2232 EXPORT_SYMBOL(_PAGE_IE);
2233
2234 unsigned long _PAGE_E __read_mostly;
2235 EXPORT_SYMBOL(_PAGE_E);
2236
2237 unsigned long _PAGE_CACHE __read_mostly;
2238 EXPORT_SYMBOL(_PAGE_CACHE);
2239
2240 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2241 unsigned long vmemmap_table[VMEMMAP_SIZE];
2242
2243 static long __meminitdata addr_start, addr_end;
2244 static int __meminitdata node_start;
2245
2246 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2247                                int node)
2248 {
2249         unsigned long phys_start = (vstart - VMEMMAP_BASE);
2250         unsigned long phys_end = (vend - VMEMMAP_BASE);
2251         unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
2252         unsigned long end = VMEMMAP_ALIGN(phys_end);
2253         unsigned long pte_base;
2254
2255         pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2256                     _PAGE_CP_4U | _PAGE_CV_4U |
2257                     _PAGE_P_4U | _PAGE_W_4U);
2258         if (tlb_type == hypervisor)
2259                 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2260                             _PAGE_CP_4V | _PAGE_CV_4V |
2261                             _PAGE_P_4V | _PAGE_W_4V);
2262
2263         for (; addr < end; addr += VMEMMAP_CHUNK) {
2264                 unsigned long *vmem_pp =
2265                         vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
2266                 void *block;
2267
2268                 if (!(*vmem_pp & _PAGE_VALID)) {
2269                         block = vmemmap_alloc_block(1UL << 22, node);
2270                         if (!block)
2271                                 return -ENOMEM;
2272
2273                         *vmem_pp = pte_base | __pa(block);
2274
2275                         /* check to see if we have contiguous blocks */
2276                         if (addr_end != addr || node_start != node) {
2277                                 if (addr_start)
2278                                         printk(KERN_DEBUG " [%lx-%lx] on node %d\n",
2279                                                addr_start, addr_end-1, node_start);
2280                                 addr_start = addr;
2281                                 node_start = node;
2282                         }
2283                         addr_end = addr + VMEMMAP_CHUNK;
2284                 }
2285         }
2286         return 0;
2287 }
2288
2289 void __meminit vmemmap_populate_print_last(void)
2290 {
2291         if (addr_start) {
2292                 printk(KERN_DEBUG " [%lx-%lx] on node %d\n",
2293                        addr_start, addr_end-1, node_start);
2294                 addr_start = 0;
2295                 addr_end = 0;
2296                 node_start = 0;
2297         }
2298 }
2299
2300 void vmemmap_free(unsigned long start, unsigned long end)
2301 {
2302 }
2303
2304 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2305
2306 static void prot_init_common(unsigned long page_none,
2307                              unsigned long page_shared,
2308                              unsigned long page_copy,
2309                              unsigned long page_readonly,
2310                              unsigned long page_exec_bit)
2311 {
2312         PAGE_COPY = __pgprot(page_copy);
2313         PAGE_SHARED = __pgprot(page_shared);
2314
2315         protection_map[0x0] = __pgprot(page_none);
2316         protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2317         protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2318         protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2319         protection_map[0x4] = __pgprot(page_readonly);
2320         protection_map[0x5] = __pgprot(page_readonly);
2321         protection_map[0x6] = __pgprot(page_copy);
2322         protection_map[0x7] = __pgprot(page_copy);
2323         protection_map[0x8] = __pgprot(page_none);
2324         protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2325         protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2326         protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2327         protection_map[0xc] = __pgprot(page_readonly);
2328         protection_map[0xd] = __pgprot(page_readonly);
2329         protection_map[0xe] = __pgprot(page_shared);
2330         protection_map[0xf] = __pgprot(page_shared);
2331 }
2332
2333 static void __init sun4u_pgprot_init(void)
2334 {
2335         unsigned long page_none, page_shared, page_copy, page_readonly;
2336         unsigned long page_exec_bit;
2337         int i;
2338
2339         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2340                                 _PAGE_CACHE_4U | _PAGE_P_4U |
2341                                 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2342                                 _PAGE_EXEC_4U);
2343         PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2344                                        _PAGE_CACHE_4U | _PAGE_P_4U |
2345                                        __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2346                                        _PAGE_EXEC_4U | _PAGE_L_4U);
2347
2348         _PAGE_IE = _PAGE_IE_4U;
2349         _PAGE_E = _PAGE_E_4U;
2350         _PAGE_CACHE = _PAGE_CACHE_4U;
2351
2352         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2353                      __ACCESS_BITS_4U | _PAGE_E_4U);
2354
2355 #ifdef CONFIG_DEBUG_PAGEALLOC
2356         kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2357 #else
2358         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2359                 PAGE_OFFSET;
2360 #endif
2361         kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2362                                    _PAGE_P_4U | _PAGE_W_4U);
2363
2364         for (i = 1; i < 4; i++)
2365                 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2366
2367         _PAGE_ALL_SZ_BITS =  (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2368                               _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2369                               _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2370
2371
2372         page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2373         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2374                        __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2375         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2376                        __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2377         page_readonly   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2378                            __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2379
2380         page_exec_bit = _PAGE_EXEC_4U;
2381
2382         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2383                          page_exec_bit);
2384 }
2385
2386 static void __init sun4v_pgprot_init(void)
2387 {
2388         unsigned long page_none, page_shared, page_copy, page_readonly;
2389         unsigned long page_exec_bit;
2390         int i;
2391
2392         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2393                                 _PAGE_CACHE_4V | _PAGE_P_4V |
2394                                 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2395                                 _PAGE_EXEC_4V);
2396         PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2397
2398         _PAGE_IE = _PAGE_IE_4V;
2399         _PAGE_E = _PAGE_E_4V;
2400         _PAGE_CACHE = _PAGE_CACHE_4V;
2401
2402 #ifdef CONFIG_DEBUG_PAGEALLOC
2403         kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2404 #else
2405         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2406                 PAGE_OFFSET;
2407 #endif
2408         kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2409                                    _PAGE_P_4V | _PAGE_W_4V);
2410
2411         for (i = 1; i < 4; i++)
2412                 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2413
2414         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2415                      __ACCESS_BITS_4V | _PAGE_E_4V);
2416
2417         _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2418                              _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2419                              _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2420                              _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2421
2422         page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
2423         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2424                        __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2425         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2426                        __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2427         page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2428                          __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2429
2430         page_exec_bit = _PAGE_EXEC_4V;
2431
2432         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2433                          page_exec_bit);
2434 }
2435
2436 unsigned long pte_sz_bits(unsigned long sz)
2437 {
2438         if (tlb_type == hypervisor) {
2439                 switch (sz) {
2440                 case 8 * 1024:
2441                 default:
2442                         return _PAGE_SZ8K_4V;
2443                 case 64 * 1024:
2444                         return _PAGE_SZ64K_4V;
2445                 case 512 * 1024:
2446                         return _PAGE_SZ512K_4V;
2447                 case 4 * 1024 * 1024:
2448                         return _PAGE_SZ4MB_4V;
2449                 }
2450         } else {
2451                 switch (sz) {
2452                 case 8 * 1024:
2453                 default:
2454                         return _PAGE_SZ8K_4U;
2455                 case 64 * 1024:
2456                         return _PAGE_SZ64K_4U;
2457                 case 512 * 1024:
2458                         return _PAGE_SZ512K_4U;
2459                 case 4 * 1024 * 1024:
2460                         return _PAGE_SZ4MB_4U;
2461                 }
2462         }
2463 }
2464
2465 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2466 {
2467         pte_t pte;
2468
2469         pte_val(pte)  = page | pgprot_val(pgprot_noncached(prot));
2470         pte_val(pte) |= (((unsigned long)space) << 32);
2471         pte_val(pte) |= pte_sz_bits(page_size);
2472
2473         return pte;
2474 }
2475
2476 static unsigned long kern_large_tte(unsigned long paddr)
2477 {
2478         unsigned long val;
2479
2480         val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2481                _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2482                _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2483         if (tlb_type == hypervisor)
2484                 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2485                        _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
2486                        _PAGE_EXEC_4V | _PAGE_W_4V);
2487
2488         return val | paddr;
2489 }
2490
2491 /* If not locked, zap it. */
2492 void __flush_tlb_all(void)
2493 {
2494         unsigned long pstate;
2495         int i;
2496
2497         __asm__ __volatile__("flushw\n\t"
2498                              "rdpr      %%pstate, %0\n\t"
2499                              "wrpr      %0, %1, %%pstate"
2500                              : "=r" (pstate)
2501                              : "i" (PSTATE_IE));
2502         if (tlb_type == hypervisor) {
2503                 sun4v_mmu_demap_all();
2504         } else if (tlb_type == spitfire) {
2505                 for (i = 0; i < 64; i++) {
2506                         /* Spitfire Errata #32 workaround */
2507                         /* NOTE: Always runs on spitfire, so no
2508                          *       cheetah+ page size encodings.
2509                          */
2510                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2511                                              "flush     %%g6"
2512                                              : /* No outputs */
2513                                              : "r" (0),
2514                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2515
2516                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2517                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2518                                                      "membar #Sync"
2519                                                      : /* no outputs */
2520                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2521                                 spitfire_put_dtlb_data(i, 0x0UL);
2522                         }
2523
2524                         /* Spitfire Errata #32 workaround */
2525                         /* NOTE: Always runs on spitfire, so no
2526                          *       cheetah+ page size encodings.
2527                          */
2528                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2529                                              "flush     %%g6"
2530                                              : /* No outputs */
2531                                              : "r" (0),
2532                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2533
2534                         if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2535                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2536                                                      "membar #Sync"
2537                                                      : /* no outputs */
2538                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2539                                 spitfire_put_itlb_data(i, 0x0UL);
2540                         }
2541                 }
2542         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2543                 cheetah_flush_dtlb_all();
2544                 cheetah_flush_itlb_all();
2545         }
2546         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
2547                              : : "r" (pstate));
2548 }
2549
2550 pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
2551                             unsigned long address)
2552 {
2553         struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2554                                        __GFP_REPEAT | __GFP_ZERO);
2555         pte_t *pte = NULL;
2556
2557         if (page)
2558                 pte = (pte_t *) page_address(page);
2559
2560         return pte;
2561 }
2562
2563 pgtable_t pte_alloc_one(struct mm_struct *mm,
2564                         unsigned long address)
2565 {
2566         struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2567                                        __GFP_REPEAT | __GFP_ZERO);
2568         if (!page)
2569                 return NULL;
2570         if (!pgtable_page_ctor(page)) {
2571                 free_hot_cold_page(page, 0);
2572                 return NULL;
2573         }
2574         return (pte_t *) page_address(page);
2575 }
2576
2577 void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2578 {
2579         free_page((unsigned long)pte);
2580 }
2581
2582 static void __pte_free(pgtable_t pte)
2583 {
2584         struct page *page = virt_to_page(pte);
2585
2586         pgtable_page_dtor(page);
2587         __free_page(page);
2588 }
2589
2590 void pte_free(struct mm_struct *mm, pgtable_t pte)
2591 {
2592         __pte_free(pte);
2593 }
2594
2595 void pgtable_free(void *table, bool is_page)
2596 {
2597         if (is_page)
2598                 __pte_free(table);
2599         else
2600                 kmem_cache_free(pgtable_cache, table);
2601 }
2602
2603 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2604 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2605                           pmd_t *pmd)
2606 {
2607         unsigned long pte, flags;
2608         struct mm_struct *mm;
2609         pmd_t entry = *pmd;
2610
2611         if (!pmd_large(entry) || !pmd_young(entry))
2612                 return;
2613
2614         pte = pmd_val(entry);
2615
2616         /* We are fabricating 8MB pages using 4MB real hw pages.  */
2617         pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
2618
2619         mm = vma->vm_mm;
2620
2621         spin_lock_irqsave(&mm->context.lock, flags);
2622
2623         if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2624                 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
2625                                         addr, pte);
2626
2627         spin_unlock_irqrestore(&mm->context.lock, flags);
2628 }
2629 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2630
2631 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2632 static void context_reload(void *__data)
2633 {
2634         struct mm_struct *mm = __data;
2635
2636         if (mm == current->mm)
2637                 load_secondary_context(mm);
2638 }
2639
2640 void hugetlb_setup(struct pt_regs *regs)
2641 {
2642         struct mm_struct *mm = current->mm;
2643         struct tsb_config *tp;
2644
2645         if (in_atomic() || !mm) {
2646                 const struct exception_table_entry *entry;
2647
2648                 entry = search_exception_tables(regs->tpc);
2649                 if (entry) {
2650                         regs->tpc = entry->fixup;
2651                         regs->tnpc = regs->tpc + 4;
2652                         return;
2653                 }
2654                 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2655                 die_if_kernel("HugeTSB in atomic", regs);
2656         }
2657
2658         tp = &mm->context.tsb_block[MM_TSB_HUGE];
2659         if (likely(tp->tsb == NULL))
2660                 tsb_grow(mm, MM_TSB_HUGE, 0);
2661
2662         tsb_context_switch(mm);
2663         smp_tsb_sync(mm);
2664
2665         /* On UltraSPARC-III+ and later, configure the second half of
2666          * the Data-TLB for huge pages.
2667          */
2668         if (tlb_type == cheetah_plus) {
2669                 unsigned long ctx;
2670
2671                 spin_lock(&ctx_alloc_lock);
2672                 ctx = mm->context.sparc64_ctx_val;
2673                 ctx &= ~CTX_PGSZ_MASK;
2674                 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
2675                 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
2676
2677                 if (ctx != mm->context.sparc64_ctx_val) {
2678                         /* When changing the page size fields, we
2679                          * must perform a context flush so that no
2680                          * stale entries match.  This flush must
2681                          * occur with the original context register
2682                          * settings.
2683                          */
2684                         do_flush_tlb_mm(mm);
2685
2686                         /* Reload the context register of all processors
2687                          * also executing in this address space.
2688                          */
2689                         mm->context.sparc64_ctx_val = ctx;
2690                         on_each_cpu(context_reload, mm, 0);
2691                 }
2692                 spin_unlock(&ctx_alloc_lock);
2693         }
2694 }
2695 #endif