2 * Procedures for creating, accessing and interpreting the device tree.
4 * Paul Mackerras August 1996.
5 * Copyright (C) 1996-2005 Paul Mackerras.
7 * Adapted for 64bit PowerPC by Dave Engebretsen and Peter Bergner.
8 * {engebret|bergner}@us.ibm.com
10 * Adapted for sparc64 by David S. Miller davem@davemloft.net
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
18 #include <linux/kernel.h>
19 #include <linux/types.h>
20 #include <linux/string.h>
22 #include <linux/bootmem.h>
23 #include <linux/module.h>
26 #include <asm/of_device.h>
27 #include <asm/oplib.h>
33 static struct device_node *allnodes;
35 /* use when traversing tree through the allnext, child, sibling,
36 * or parent members of struct device_node.
38 static DEFINE_RWLOCK(devtree_lock);
40 int of_device_is_compatible(const struct device_node *device,
46 cp = of_get_property(device, "compatible", &cplen);
50 if (strncmp(cp, compat, strlen(compat)) == 0)
59 EXPORT_SYMBOL(of_device_is_compatible);
61 struct device_node *of_get_parent(const struct device_node *node)
63 struct device_node *np;
72 EXPORT_SYMBOL(of_get_parent);
74 struct device_node *of_get_next_child(const struct device_node *node,
75 struct device_node *prev)
77 struct device_node *next;
79 next = prev ? prev->sibling : node->child;
80 for (; next != 0; next = next->sibling) {
86 EXPORT_SYMBOL(of_get_next_child);
88 struct device_node *of_find_node_by_path(const char *path)
90 struct device_node *np = allnodes;
92 for (; np != 0; np = np->allnext) {
93 if (np->full_name != 0 && strcmp(np->full_name, path) == 0)
99 EXPORT_SYMBOL(of_find_node_by_path);
101 struct device_node *of_find_node_by_phandle(phandle handle)
103 struct device_node *np;
105 for (np = allnodes; np != 0; np = np->allnext)
106 if (np->node == handle)
111 EXPORT_SYMBOL(of_find_node_by_phandle);
113 struct device_node *of_find_node_by_name(struct device_node *from,
116 struct device_node *np;
118 np = from ? from->allnext : allnodes;
119 for (; np != NULL; np = np->allnext)
120 if (np->name != NULL && strcmp(np->name, name) == 0)
125 EXPORT_SYMBOL(of_find_node_by_name);
127 struct device_node *of_find_node_by_type(struct device_node *from,
130 struct device_node *np;
132 np = from ? from->allnext : allnodes;
133 for (; np != 0; np = np->allnext)
134 if (np->type != 0 && strcmp(np->type, type) == 0)
139 EXPORT_SYMBOL(of_find_node_by_type);
141 struct device_node *of_find_compatible_node(struct device_node *from,
142 const char *type, const char *compatible)
144 struct device_node *np;
146 np = from ? from->allnext : allnodes;
147 for (; np != 0; np = np->allnext) {
149 && !(np->type != 0 && strcmp(np->type, type) == 0))
151 if (of_device_is_compatible(np, compatible))
157 EXPORT_SYMBOL(of_find_compatible_node);
159 struct property *of_find_property(const struct device_node *np,
165 for (pp = np->properties; pp != 0; pp = pp->next) {
166 if (strcasecmp(pp->name, name) == 0) {
174 EXPORT_SYMBOL(of_find_property);
176 int of_getintprop_default(struct device_node *np, const char *name, int def)
178 struct property *prop;
181 prop = of_find_property(np, name, &len);
182 if (!prop || len != 4)
185 return *(int *) prop->value;
187 EXPORT_SYMBOL(of_getintprop_default);
189 int of_set_property(struct device_node *dp, const char *name, void *val, int len)
191 struct property **prevp;
195 new_val = kmalloc(len, GFP_KERNEL);
199 memcpy(new_val, val, len);
203 write_lock(&devtree_lock);
204 prevp = &dp->properties;
206 struct property *prop = *prevp;
208 if (!strcasecmp(prop->name, name)) {
209 void *old_val = prop->value;
212 ret = prom_setprop(dp->node, name, val, len);
215 prop->value = new_val;
218 if (OF_IS_DYNAMIC(prop))
221 OF_MARK_DYNAMIC(prop);
227 prevp = &(*prevp)->next;
229 write_unlock(&devtree_lock);
231 /* XXX Upate procfs if necessary... */
235 EXPORT_SYMBOL(of_set_property);
237 static unsigned int prom_early_allocated;
239 static void * __init prom_early_alloc(unsigned long size)
243 ret = __alloc_bootmem(size, SMP_CACHE_BYTES, 0UL);
245 memset(ret, 0, size);
247 prom_early_allocated += size;
253 /* PSYCHO interrupt mapping support. */
254 #define PSYCHO_IMAP_A_SLOT0 0x0c00UL
255 #define PSYCHO_IMAP_B_SLOT0 0x0c20UL
256 static unsigned long psycho_pcislot_imap_offset(unsigned long ino)
258 unsigned int bus = (ino & 0x10) >> 4;
259 unsigned int slot = (ino & 0x0c) >> 2;
262 return PSYCHO_IMAP_A_SLOT0 + (slot * 8);
264 return PSYCHO_IMAP_B_SLOT0 + (slot * 8);
267 #define PSYCHO_IMAP_SCSI 0x1000UL
268 #define PSYCHO_IMAP_ETH 0x1008UL
269 #define PSYCHO_IMAP_BPP 0x1010UL
270 #define PSYCHO_IMAP_AU_REC 0x1018UL
271 #define PSYCHO_IMAP_AU_PLAY 0x1020UL
272 #define PSYCHO_IMAP_PFAIL 0x1028UL
273 #define PSYCHO_IMAP_KMS 0x1030UL
274 #define PSYCHO_IMAP_FLPY 0x1038UL
275 #define PSYCHO_IMAP_SHW 0x1040UL
276 #define PSYCHO_IMAP_KBD 0x1048UL
277 #define PSYCHO_IMAP_MS 0x1050UL
278 #define PSYCHO_IMAP_SER 0x1058UL
279 #define PSYCHO_IMAP_TIM0 0x1060UL
280 #define PSYCHO_IMAP_TIM1 0x1068UL
281 #define PSYCHO_IMAP_UE 0x1070UL
282 #define PSYCHO_IMAP_CE 0x1078UL
283 #define PSYCHO_IMAP_A_ERR 0x1080UL
284 #define PSYCHO_IMAP_B_ERR 0x1088UL
285 #define PSYCHO_IMAP_PMGMT 0x1090UL
286 #define PSYCHO_IMAP_GFX 0x1098UL
287 #define PSYCHO_IMAP_EUPA 0x10a0UL
289 static unsigned long __psycho_onboard_imap_off[] = {
290 /*0x20*/ PSYCHO_IMAP_SCSI,
291 /*0x21*/ PSYCHO_IMAP_ETH,
292 /*0x22*/ PSYCHO_IMAP_BPP,
293 /*0x23*/ PSYCHO_IMAP_AU_REC,
294 /*0x24*/ PSYCHO_IMAP_AU_PLAY,
295 /*0x25*/ PSYCHO_IMAP_PFAIL,
296 /*0x26*/ PSYCHO_IMAP_KMS,
297 /*0x27*/ PSYCHO_IMAP_FLPY,
298 /*0x28*/ PSYCHO_IMAP_SHW,
299 /*0x29*/ PSYCHO_IMAP_KBD,
300 /*0x2a*/ PSYCHO_IMAP_MS,
301 /*0x2b*/ PSYCHO_IMAP_SER,
302 /*0x2c*/ PSYCHO_IMAP_TIM0,
303 /*0x2d*/ PSYCHO_IMAP_TIM1,
304 /*0x2e*/ PSYCHO_IMAP_UE,
305 /*0x2f*/ PSYCHO_IMAP_CE,
306 /*0x30*/ PSYCHO_IMAP_A_ERR,
307 /*0x31*/ PSYCHO_IMAP_B_ERR,
308 /*0x32*/ PSYCHO_IMAP_PMGMT,
309 /*0x33*/ PSYCHO_IMAP_GFX,
310 /*0x34*/ PSYCHO_IMAP_EUPA,
312 #define PSYCHO_ONBOARD_IRQ_BASE 0x20
313 #define PSYCHO_ONBOARD_IRQ_LAST 0x34
314 #define psycho_onboard_imap_offset(__ino) \
315 __psycho_onboard_imap_off[(__ino) - PSYCHO_ONBOARD_IRQ_BASE]
317 #define PSYCHO_ICLR_A_SLOT0 0x1400UL
318 #define PSYCHO_ICLR_SCSI 0x1800UL
320 #define psycho_iclr_offset(ino) \
321 ((ino & 0x20) ? (PSYCHO_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
322 (PSYCHO_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
324 static unsigned int psycho_irq_build(struct device_node *dp,
328 unsigned long controller_regs = (unsigned long) _data;
329 unsigned long imap, iclr;
330 unsigned long imap_off, iclr_off;
334 if (ino < PSYCHO_ONBOARD_IRQ_BASE) {
336 imap_off = psycho_pcislot_imap_offset(ino);
339 if (ino > PSYCHO_ONBOARD_IRQ_LAST) {
340 prom_printf("psycho_irq_build: Wacky INO [%x]\n", ino);
343 imap_off = psycho_onboard_imap_offset(ino);
346 /* Now build the IRQ bucket. */
347 imap = controller_regs + imap_off;
349 iclr_off = psycho_iclr_offset(ino);
350 iclr = controller_regs + iclr_off;
352 if ((ino & 0x20) == 0)
353 inofixup = ino & 0x03;
355 return build_irq(inofixup, iclr, imap);
358 static void __init psycho_irq_trans_init(struct device_node *dp)
360 const struct linux_prom64_registers *regs;
362 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
363 dp->irq_trans->irq_build = psycho_irq_build;
365 regs = of_get_property(dp, "reg", NULL);
366 dp->irq_trans->data = (void *) regs[2].phys_addr;
369 #define sabre_read(__reg) \
371 __asm__ __volatile__("ldxa [%1] %2, %0" \
373 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
378 struct sabre_irq_data {
379 unsigned long controller_regs;
380 unsigned int pci_first_busno;
382 #define SABRE_CONFIGSPACE 0x001000000UL
383 #define SABRE_WRSYNC 0x1c20UL
385 #define SABRE_CONFIG_BASE(CONFIG_SPACE) \
386 (CONFIG_SPACE | (1UL << 24))
387 #define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG) \
388 (((unsigned long)(BUS) << 16) | \
389 ((unsigned long)(DEVFN) << 8) | \
390 ((unsigned long)(REG)))
392 /* When a device lives behind a bridge deeper in the PCI bus topology
393 * than APB, a special sequence must run to make sure all pending DMA
394 * transfers at the time of IRQ delivery are visible in the coherency
395 * domain by the cpu. This sequence is to perform a read on the far
396 * side of the non-APB bridge, then perform a read of Sabre's DMA
397 * write-sync register.
399 static void sabre_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
401 unsigned int phys_hi = (unsigned int) (unsigned long) _arg1;
402 struct sabre_irq_data *irq_data = _arg2;
403 unsigned long controller_regs = irq_data->controller_regs;
404 unsigned long sync_reg = controller_regs + SABRE_WRSYNC;
405 unsigned long config_space = controller_regs + SABRE_CONFIGSPACE;
406 unsigned int bus, devfn;
409 config_space = SABRE_CONFIG_BASE(config_space);
411 bus = (phys_hi >> 16) & 0xff;
412 devfn = (phys_hi >> 8) & 0xff;
414 config_space |= SABRE_CONFIG_ENCODE(bus, devfn, 0x00);
416 __asm__ __volatile__("membar #Sync\n\t"
417 "lduha [%1] %2, %0\n\t"
420 : "r" ((u16 *) config_space),
421 "i" (ASI_PHYS_BYPASS_EC_E_L)
424 sabre_read(sync_reg);
427 #define SABRE_IMAP_A_SLOT0 0x0c00UL
428 #define SABRE_IMAP_B_SLOT0 0x0c20UL
429 #define SABRE_IMAP_SCSI 0x1000UL
430 #define SABRE_IMAP_ETH 0x1008UL
431 #define SABRE_IMAP_BPP 0x1010UL
432 #define SABRE_IMAP_AU_REC 0x1018UL
433 #define SABRE_IMAP_AU_PLAY 0x1020UL
434 #define SABRE_IMAP_PFAIL 0x1028UL
435 #define SABRE_IMAP_KMS 0x1030UL
436 #define SABRE_IMAP_FLPY 0x1038UL
437 #define SABRE_IMAP_SHW 0x1040UL
438 #define SABRE_IMAP_KBD 0x1048UL
439 #define SABRE_IMAP_MS 0x1050UL
440 #define SABRE_IMAP_SER 0x1058UL
441 #define SABRE_IMAP_UE 0x1070UL
442 #define SABRE_IMAP_CE 0x1078UL
443 #define SABRE_IMAP_PCIERR 0x1080UL
444 #define SABRE_IMAP_GFX 0x1098UL
445 #define SABRE_IMAP_EUPA 0x10a0UL
446 #define SABRE_ICLR_A_SLOT0 0x1400UL
447 #define SABRE_ICLR_B_SLOT0 0x1480UL
448 #define SABRE_ICLR_SCSI 0x1800UL
449 #define SABRE_ICLR_ETH 0x1808UL
450 #define SABRE_ICLR_BPP 0x1810UL
451 #define SABRE_ICLR_AU_REC 0x1818UL
452 #define SABRE_ICLR_AU_PLAY 0x1820UL
453 #define SABRE_ICLR_PFAIL 0x1828UL
454 #define SABRE_ICLR_KMS 0x1830UL
455 #define SABRE_ICLR_FLPY 0x1838UL
456 #define SABRE_ICLR_SHW 0x1840UL
457 #define SABRE_ICLR_KBD 0x1848UL
458 #define SABRE_ICLR_MS 0x1850UL
459 #define SABRE_ICLR_SER 0x1858UL
460 #define SABRE_ICLR_UE 0x1870UL
461 #define SABRE_ICLR_CE 0x1878UL
462 #define SABRE_ICLR_PCIERR 0x1880UL
464 static unsigned long sabre_pcislot_imap_offset(unsigned long ino)
466 unsigned int bus = (ino & 0x10) >> 4;
467 unsigned int slot = (ino & 0x0c) >> 2;
470 return SABRE_IMAP_A_SLOT0 + (slot * 8);
472 return SABRE_IMAP_B_SLOT0 + (slot * 8);
475 static unsigned long __sabre_onboard_imap_off[] = {
476 /*0x20*/ SABRE_IMAP_SCSI,
477 /*0x21*/ SABRE_IMAP_ETH,
478 /*0x22*/ SABRE_IMAP_BPP,
479 /*0x23*/ SABRE_IMAP_AU_REC,
480 /*0x24*/ SABRE_IMAP_AU_PLAY,
481 /*0x25*/ SABRE_IMAP_PFAIL,
482 /*0x26*/ SABRE_IMAP_KMS,
483 /*0x27*/ SABRE_IMAP_FLPY,
484 /*0x28*/ SABRE_IMAP_SHW,
485 /*0x29*/ SABRE_IMAP_KBD,
486 /*0x2a*/ SABRE_IMAP_MS,
487 /*0x2b*/ SABRE_IMAP_SER,
488 /*0x2c*/ 0 /* reserved */,
489 /*0x2d*/ 0 /* reserved */,
490 /*0x2e*/ SABRE_IMAP_UE,
491 /*0x2f*/ SABRE_IMAP_CE,
492 /*0x30*/ SABRE_IMAP_PCIERR,
493 /*0x31*/ 0 /* reserved */,
494 /*0x32*/ 0 /* reserved */,
495 /*0x33*/ SABRE_IMAP_GFX,
496 /*0x34*/ SABRE_IMAP_EUPA,
498 #define SABRE_ONBOARD_IRQ_BASE 0x20
499 #define SABRE_ONBOARD_IRQ_LAST 0x30
500 #define sabre_onboard_imap_offset(__ino) \
501 __sabre_onboard_imap_off[(__ino) - SABRE_ONBOARD_IRQ_BASE]
503 #define sabre_iclr_offset(ino) \
504 ((ino & 0x20) ? (SABRE_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
505 (SABRE_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
507 static int sabre_device_needs_wsync(struct device_node *dp)
509 struct device_node *parent = dp->parent;
510 const char *parent_model, *parent_compat;
512 /* This traversal up towards the root is meant to
515 * 1) non-PCI bus sitting under PCI, such as 'ebus'
516 * 2) the PCI controller interrupts themselves, which
517 * will use the sabre_irq_build but do not need
518 * the DMA synchronization handling
521 if (!strcmp(parent->type, "pci"))
523 parent = parent->parent;
529 parent_model = of_get_property(parent,
532 (!strcmp(parent_model, "SUNW,sabre") ||
533 !strcmp(parent_model, "SUNW,simba")))
536 parent_compat = of_get_property(parent,
539 (!strcmp(parent_compat, "pci108e,a000") ||
540 !strcmp(parent_compat, "pci108e,a001")))
546 static unsigned int sabre_irq_build(struct device_node *dp,
550 struct sabre_irq_data *irq_data = _data;
551 unsigned long controller_regs = irq_data->controller_regs;
552 const struct linux_prom_pci_registers *regs;
553 unsigned long imap, iclr;
554 unsigned long imap_off, iclr_off;
559 if (ino < SABRE_ONBOARD_IRQ_BASE) {
561 imap_off = sabre_pcislot_imap_offset(ino);
564 if (ino > SABRE_ONBOARD_IRQ_LAST) {
565 prom_printf("sabre_irq_build: Wacky INO [%x]\n", ino);
568 imap_off = sabre_onboard_imap_offset(ino);
571 /* Now build the IRQ bucket. */
572 imap = controller_regs + imap_off;
574 iclr_off = sabre_iclr_offset(ino);
575 iclr = controller_regs + iclr_off;
577 if ((ino & 0x20) == 0)
578 inofixup = ino & 0x03;
580 virt_irq = build_irq(inofixup, iclr, imap);
582 /* If the parent device is a PCI<->PCI bridge other than
583 * APB, we have to install a pre-handler to ensure that
584 * all pending DMA is drained before the interrupt handler
587 regs = of_get_property(dp, "reg", NULL);
588 if (regs && sabre_device_needs_wsync(dp)) {
589 irq_install_pre_handler(virt_irq,
591 (void *) (long) regs->phys_hi,
598 static void __init sabre_irq_trans_init(struct device_node *dp)
600 const struct linux_prom64_registers *regs;
601 struct sabre_irq_data *irq_data;
604 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
605 dp->irq_trans->irq_build = sabre_irq_build;
607 irq_data = prom_early_alloc(sizeof(struct sabre_irq_data));
609 regs = of_get_property(dp, "reg", NULL);
610 irq_data->controller_regs = regs[0].phys_addr;
612 busrange = of_get_property(dp, "bus-range", NULL);
613 irq_data->pci_first_busno = busrange[0];
615 dp->irq_trans->data = irq_data;
618 /* SCHIZO interrupt mapping support. Unlike Psycho, for this controller the
619 * imap/iclr registers are per-PBM.
621 #define SCHIZO_IMAP_BASE 0x1000UL
622 #define SCHIZO_ICLR_BASE 0x1400UL
624 static unsigned long schizo_imap_offset(unsigned long ino)
626 return SCHIZO_IMAP_BASE + (ino * 8UL);
629 static unsigned long schizo_iclr_offset(unsigned long ino)
631 return SCHIZO_ICLR_BASE + (ino * 8UL);
634 static unsigned long schizo_ino_to_iclr(unsigned long pbm_regs,
638 return pbm_regs + schizo_iclr_offset(ino);
641 static unsigned long schizo_ino_to_imap(unsigned long pbm_regs,
644 return pbm_regs + schizo_imap_offset(ino);
647 #define schizo_read(__reg) \
649 __asm__ __volatile__("ldxa [%1] %2, %0" \
651 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
655 #define schizo_write(__reg, __val) \
656 __asm__ __volatile__("stxa %0, [%1] %2" \
658 : "r" (__val), "r" (__reg), \
659 "i" (ASI_PHYS_BYPASS_EC_E) \
662 static void tomatillo_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
664 unsigned long sync_reg = (unsigned long) _arg2;
665 u64 mask = 1UL << (ino & IMAP_INO);
669 schizo_write(sync_reg, mask);
674 val = schizo_read(sync_reg);
679 printk("tomatillo_wsync_handler: DMA won't sync [%lx:%lx]\n",
684 static unsigned char cacheline[64]
685 __attribute__ ((aligned (64)));
687 __asm__ __volatile__("rd %%fprs, %0\n\t"
689 "wr %1, 0x0, %%fprs\n\t"
690 "stda %%f0, [%5] %6\n\t"
691 "wr %0, 0x0, %%fprs\n\t"
693 : "=&r" (mask), "=&r" (val)
694 : "0" (mask), "1" (val),
695 "i" (FPRS_FEF), "r" (&cacheline[0]),
696 "i" (ASI_BLK_COMMIT_P));
700 struct schizo_irq_data {
701 unsigned long pbm_regs;
702 unsigned long sync_reg;
707 static unsigned int schizo_irq_build(struct device_node *dp,
711 struct schizo_irq_data *irq_data = _data;
712 unsigned long pbm_regs = irq_data->pbm_regs;
713 unsigned long imap, iclr;
720 /* Now build the IRQ bucket. */
721 imap = schizo_ino_to_imap(pbm_regs, ino);
722 iclr = schizo_ino_to_iclr(pbm_regs, ino);
724 /* On Schizo, no inofixup occurs. This is because each
725 * INO has it's own IMAP register. On Psycho and Sabre
726 * there is only one IMAP register for each PCI slot even
727 * though four different INOs can be generated by each
730 * But, for JBUS variants (essentially, Tomatillo), we have
731 * to fixup the lowest bit of the interrupt group number.
735 is_tomatillo = (irq_data->sync_reg != 0UL);
738 if (irq_data->portid & 1)
739 ign_fixup = (1 << 6);
742 virt_irq = build_irq(ign_fixup, iclr, imap);
745 irq_install_pre_handler(virt_irq,
746 tomatillo_wsync_handler,
747 ((irq_data->chip_version <= 4) ?
748 (void *) 1 : (void *) 0),
749 (void *) irq_data->sync_reg);
755 static void __init __schizo_irq_trans_init(struct device_node *dp,
758 const struct linux_prom64_registers *regs;
759 struct schizo_irq_data *irq_data;
761 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
762 dp->irq_trans->irq_build = schizo_irq_build;
764 irq_data = prom_early_alloc(sizeof(struct schizo_irq_data));
766 regs = of_get_property(dp, "reg", NULL);
767 dp->irq_trans->data = irq_data;
769 irq_data->pbm_regs = regs[0].phys_addr;
771 irq_data->sync_reg = regs[3].phys_addr + 0x1a18UL;
773 irq_data->sync_reg = 0UL;
774 irq_data->portid = of_getintprop_default(dp, "portid", 0);
775 irq_data->chip_version = of_getintprop_default(dp, "version#", 0);
778 static void __init schizo_irq_trans_init(struct device_node *dp)
780 __schizo_irq_trans_init(dp, 0);
783 static void __init tomatillo_irq_trans_init(struct device_node *dp)
785 __schizo_irq_trans_init(dp, 1);
788 static unsigned int pci_sun4v_irq_build(struct device_node *dp,
792 u32 devhandle = (u32) (unsigned long) _data;
794 return sun4v_build_irq(devhandle, devino);
797 static void __init pci_sun4v_irq_trans_init(struct device_node *dp)
799 const struct linux_prom64_registers *regs;
801 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
802 dp->irq_trans->irq_build = pci_sun4v_irq_build;
804 regs = of_get_property(dp, "reg", NULL);
805 dp->irq_trans->data = (void *) (unsigned long)
806 ((regs->phys_addr >> 32UL) & 0x0fffffff);
809 struct fire_irq_data {
810 unsigned long pbm_regs;
814 #define FIRE_IMAP_BASE 0x001000
815 #define FIRE_ICLR_BASE 0x001400
817 static unsigned long fire_imap_offset(unsigned long ino)
819 return FIRE_IMAP_BASE + (ino * 8UL);
822 static unsigned long fire_iclr_offset(unsigned long ino)
824 return FIRE_ICLR_BASE + (ino * 8UL);
827 static unsigned long fire_ino_to_iclr(unsigned long pbm_regs,
830 return pbm_regs + fire_iclr_offset(ino);
833 static unsigned long fire_ino_to_imap(unsigned long pbm_regs,
836 return pbm_regs + fire_imap_offset(ino);
839 static unsigned int fire_irq_build(struct device_node *dp,
843 struct fire_irq_data *irq_data = _data;
844 unsigned long pbm_regs = irq_data->pbm_regs;
845 unsigned long imap, iclr;
846 unsigned long int_ctrlr;
850 /* Now build the IRQ bucket. */
851 imap = fire_ino_to_imap(pbm_regs, ino);
852 iclr = fire_ino_to_iclr(pbm_regs, ino);
854 /* Set the interrupt controller number. */
856 upa_writeq(int_ctrlr, imap);
858 /* The interrupt map registers do not have an INO field
859 * like other chips do. They return zero in the INO
860 * field, and the interrupt controller number is controlled
861 * in bits 6 to 9. So in order for build_irq() to get
862 * the INO right we pass it in as part of the fixup
863 * which will get added to the map register zero value
864 * read by build_irq().
866 ino |= (irq_data->portid << 6);
868 return build_irq(ino, iclr, imap);
871 static void __init fire_irq_trans_init(struct device_node *dp)
873 const struct linux_prom64_registers *regs;
874 struct fire_irq_data *irq_data;
876 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
877 dp->irq_trans->irq_build = fire_irq_build;
879 irq_data = prom_early_alloc(sizeof(struct fire_irq_data));
881 regs = of_get_property(dp, "reg", NULL);
882 dp->irq_trans->data = irq_data;
884 irq_data->pbm_regs = regs[0].phys_addr;
885 irq_data->portid = of_getintprop_default(dp, "portid", 0);
887 #endif /* CONFIG_PCI */
890 /* INO number to IMAP register offset for SYSIO external IRQ's.
891 * This should conform to both Sunfire/Wildfire server and Fusion
894 #define SYSIO_IMAP_SLOT0 0x2c00UL
895 #define SYSIO_IMAP_SLOT1 0x2c08UL
896 #define SYSIO_IMAP_SLOT2 0x2c10UL
897 #define SYSIO_IMAP_SLOT3 0x2c18UL
898 #define SYSIO_IMAP_SCSI 0x3000UL
899 #define SYSIO_IMAP_ETH 0x3008UL
900 #define SYSIO_IMAP_BPP 0x3010UL
901 #define SYSIO_IMAP_AUDIO 0x3018UL
902 #define SYSIO_IMAP_PFAIL 0x3020UL
903 #define SYSIO_IMAP_KMS 0x3028UL
904 #define SYSIO_IMAP_FLPY 0x3030UL
905 #define SYSIO_IMAP_SHW 0x3038UL
906 #define SYSIO_IMAP_KBD 0x3040UL
907 #define SYSIO_IMAP_MS 0x3048UL
908 #define SYSIO_IMAP_SER 0x3050UL
909 #define SYSIO_IMAP_TIM0 0x3060UL
910 #define SYSIO_IMAP_TIM1 0x3068UL
911 #define SYSIO_IMAP_UE 0x3070UL
912 #define SYSIO_IMAP_CE 0x3078UL
913 #define SYSIO_IMAP_SBERR 0x3080UL
914 #define SYSIO_IMAP_PMGMT 0x3088UL
915 #define SYSIO_IMAP_GFX 0x3090UL
916 #define SYSIO_IMAP_EUPA 0x3098UL
918 #define bogon ((unsigned long) -1)
919 static unsigned long sysio_irq_offsets[] = {
920 /* SBUS Slot 0 --> 3, level 1 --> 7 */
921 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
922 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
923 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
924 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
925 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
926 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
927 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
928 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
930 /* Onboard devices (not relevant/used on SunFire). */
961 #define NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets)
963 /* Convert Interrupt Mapping register pointer to associated
964 * Interrupt Clear register pointer, SYSIO specific version.
966 #define SYSIO_ICLR_UNUSED0 0x3400UL
967 #define SYSIO_ICLR_SLOT0 0x3408UL
968 #define SYSIO_ICLR_SLOT1 0x3448UL
969 #define SYSIO_ICLR_SLOT2 0x3488UL
970 #define SYSIO_ICLR_SLOT3 0x34c8UL
971 static unsigned long sysio_imap_to_iclr(unsigned long imap)
973 unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0;
977 static unsigned int sbus_of_build_irq(struct device_node *dp,
981 unsigned long reg_base = (unsigned long) _data;
982 const struct linux_prom_registers *regs;
983 unsigned long imap, iclr;
989 regs = of_get_property(dp, "reg", NULL);
991 sbus_slot = regs->which_io;
994 ino += (sbus_slot * 8);
996 imap = sysio_irq_offsets[ino];
997 if (imap == ((unsigned long)-1)) {
998 prom_printf("get_irq_translations: Bad SYSIO INO[%x]\n",
1004 /* SYSIO inconsistency. For external SLOTS, we have to select
1005 * the right ICLR register based upon the lower SBUS irq level
1009 iclr = sysio_imap_to_iclr(imap);
1011 sbus_level = ino & 0x7;
1015 iclr = reg_base + SYSIO_ICLR_SLOT0;
1018 iclr = reg_base + SYSIO_ICLR_SLOT1;
1021 iclr = reg_base + SYSIO_ICLR_SLOT2;
1025 iclr = reg_base + SYSIO_ICLR_SLOT3;
1029 iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
1031 return build_irq(sbus_level, iclr, imap);
1034 static void __init sbus_irq_trans_init(struct device_node *dp)
1036 const struct linux_prom64_registers *regs;
1038 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
1039 dp->irq_trans->irq_build = sbus_of_build_irq;
1041 regs = of_get_property(dp, "reg", NULL);
1042 dp->irq_trans->data = (void *) (unsigned long) regs->phys_addr;
1044 #endif /* CONFIG_SBUS */
1047 static unsigned int central_build_irq(struct device_node *dp,
1051 struct device_node *central_dp = _data;
1052 struct of_device *central_op = of_find_device_by_node(central_dp);
1053 struct resource *res;
1054 unsigned long imap, iclr;
1057 if (!strcmp(dp->name, "eeprom")) {
1058 res = ¢ral_op->resource[5];
1059 } else if (!strcmp(dp->name, "zs")) {
1060 res = ¢ral_op->resource[4];
1061 } else if (!strcmp(dp->name, "clock-board")) {
1062 res = ¢ral_op->resource[3];
1067 imap = res->start + 0x00UL;
1068 iclr = res->start + 0x10UL;
1070 /* Set the INO state to idle, and disable. */
1071 upa_writel(0, iclr);
1074 tmp = upa_readl(imap);
1076 upa_writel(tmp, imap);
1078 return build_irq(0, iclr, imap);
1081 static void __init central_irq_trans_init(struct device_node *dp)
1083 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
1084 dp->irq_trans->irq_build = central_build_irq;
1086 dp->irq_trans->data = dp;
1091 void (*init)(struct device_node *);
1095 static struct irq_trans __initdata pci_irq_trans_table[] = {
1096 { "SUNW,sabre", sabre_irq_trans_init },
1097 { "pci108e,a000", sabre_irq_trans_init },
1098 { "pci108e,a001", sabre_irq_trans_init },
1099 { "SUNW,psycho", psycho_irq_trans_init },
1100 { "pci108e,8000", psycho_irq_trans_init },
1101 { "SUNW,schizo", schizo_irq_trans_init },
1102 { "pci108e,8001", schizo_irq_trans_init },
1103 { "SUNW,schizo+", schizo_irq_trans_init },
1104 { "pci108e,8002", schizo_irq_trans_init },
1105 { "SUNW,tomatillo", tomatillo_irq_trans_init },
1106 { "pci108e,a801", tomatillo_irq_trans_init },
1107 { "SUNW,sun4v-pci", pci_sun4v_irq_trans_init },
1108 { "pciex108e,80f0", fire_irq_trans_init },
1112 static unsigned int sun4v_vdev_irq_build(struct device_node *dp,
1113 unsigned int devino,
1116 u32 devhandle = (u32) (unsigned long) _data;
1118 return sun4v_build_irq(devhandle, devino);
1121 static void __init sun4v_vdev_irq_trans_init(struct device_node *dp)
1123 const struct linux_prom64_registers *regs;
1125 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
1126 dp->irq_trans->irq_build = sun4v_vdev_irq_build;
1128 regs = of_get_property(dp, "reg", NULL);
1129 dp->irq_trans->data = (void *) (unsigned long)
1130 ((regs->phys_addr >> 32UL) & 0x0fffffff);
1133 static void __init irq_trans_init(struct device_node *dp)
1141 model = of_get_property(dp, "model", NULL);
1143 model = of_get_property(dp, "compatible", NULL);
1145 for (i = 0; i < ARRAY_SIZE(pci_irq_trans_table); i++) {
1146 struct irq_trans *t = &pci_irq_trans_table[i];
1148 if (!strcmp(model, t->name))
1154 if (!strcmp(dp->name, "sbus") ||
1155 !strcmp(dp->name, "sbi"))
1156 return sbus_irq_trans_init(dp);
1158 if (!strcmp(dp->name, "fhc") &&
1159 !strcmp(dp->parent->name, "central"))
1160 return central_irq_trans_init(dp);
1161 if (!strcmp(dp->name, "virtual-devices"))
1162 return sun4v_vdev_irq_trans_init(dp);
1165 static int is_root_node(const struct device_node *dp)
1170 return (dp->parent == NULL);
1173 /* The following routines deal with the black magic of fully naming a
1176 * Certain well known named nodes are just the simple name string.
1178 * Actual devices have an address specifier appended to the base name
1179 * string, like this "foo@addr". The "addr" can be in any number of
1180 * formats, and the platform plus the type of the node determine the
1181 * format and how it is constructed.
1183 * For children of the ROOT node, the naming convention is fixed and
1184 * determined by whether this is a sun4u or sun4v system.
1186 * For children of other nodes, it is bus type specific. So
1187 * we walk up the tree until we discover a "device_type" property
1188 * we recognize and we go from there.
1190 * As an example, the boot device on my workstation has a full path:
1192 * /pci@1e,600000/ide@d/disk@0,0:c
1194 static void __init sun4v_path_component(struct device_node *dp, char *tmp_buf)
1196 struct linux_prom64_registers *regs;
1197 struct property *rprop;
1198 u32 high_bits, low_bits, type;
1200 rprop = of_find_property(dp, "reg", NULL);
1204 regs = rprop->value;
1205 if (!is_root_node(dp->parent)) {
1206 sprintf(tmp_buf, "%s@%x,%x",
1208 (unsigned int) (regs->phys_addr >> 32UL),
1209 (unsigned int) (regs->phys_addr & 0xffffffffUL));
1213 type = regs->phys_addr >> 60UL;
1214 high_bits = (regs->phys_addr >> 32UL) & 0x0fffffffUL;
1215 low_bits = (regs->phys_addr & 0xffffffffUL);
1217 if (type == 0 || type == 8) {
1218 const char *prefix = (type == 0) ? "m" : "i";
1221 sprintf(tmp_buf, "%s@%s%x,%x",
1223 high_bits, low_bits);
1225 sprintf(tmp_buf, "%s@%s%x",
1229 } else if (type == 12) {
1230 sprintf(tmp_buf, "%s@%x",
1231 dp->name, high_bits);
1235 static void __init sun4u_path_component(struct device_node *dp, char *tmp_buf)
1237 struct linux_prom64_registers *regs;
1238 struct property *prop;
1240 prop = of_find_property(dp, "reg", NULL);
1245 if (!is_root_node(dp->parent)) {
1246 sprintf(tmp_buf, "%s@%x,%x",
1248 (unsigned int) (regs->phys_addr >> 32UL),
1249 (unsigned int) (regs->phys_addr & 0xffffffffUL));
1253 prop = of_find_property(dp, "upa-portid", NULL);
1255 prop = of_find_property(dp, "portid", NULL);
1257 unsigned long mask = 0xffffffffUL;
1259 if (tlb_type >= cheetah)
1262 sprintf(tmp_buf, "%s@%x,%x",
1264 *(u32 *)prop->value,
1265 (unsigned int) (regs->phys_addr & mask));
1269 /* "name@slot,offset" */
1270 static void __init sbus_path_component(struct device_node *dp, char *tmp_buf)
1272 struct linux_prom_registers *regs;
1273 struct property *prop;
1275 prop = of_find_property(dp, "reg", NULL);
1280 sprintf(tmp_buf, "%s@%x,%x",
1286 /* "name@devnum[,func]" */
1287 static void __init pci_path_component(struct device_node *dp, char *tmp_buf)
1289 struct linux_prom_pci_registers *regs;
1290 struct property *prop;
1293 prop = of_find_property(dp, "reg", NULL);
1298 devfn = (regs->phys_hi >> 8) & 0xff;
1300 sprintf(tmp_buf, "%s@%x,%x",
1305 sprintf(tmp_buf, "%s@%x",
1311 /* "name@UPA_PORTID,offset" */
1312 static void __init upa_path_component(struct device_node *dp, char *tmp_buf)
1314 struct linux_prom64_registers *regs;
1315 struct property *prop;
1317 prop = of_find_property(dp, "reg", NULL);
1323 prop = of_find_property(dp, "upa-portid", NULL);
1327 sprintf(tmp_buf, "%s@%x,%x",
1329 *(u32 *) prop->value,
1330 (unsigned int) (regs->phys_addr & 0xffffffffUL));
1334 static void __init vdev_path_component(struct device_node *dp, char *tmp_buf)
1336 struct property *prop;
1339 prop = of_find_property(dp, "reg", NULL);
1345 sprintf(tmp_buf, "%s@%x", dp->name, *regs);
1348 /* "name@addrhi,addrlo" */
1349 static void __init ebus_path_component(struct device_node *dp, char *tmp_buf)
1351 struct linux_prom64_registers *regs;
1352 struct property *prop;
1354 prop = of_find_property(dp, "reg", NULL);
1360 sprintf(tmp_buf, "%s@%x,%x",
1362 (unsigned int) (regs->phys_addr >> 32UL),
1363 (unsigned int) (regs->phys_addr & 0xffffffffUL));
1366 /* "name@bus,addr" */
1367 static void __init i2c_path_component(struct device_node *dp, char *tmp_buf)
1369 struct property *prop;
1372 prop = of_find_property(dp, "reg", NULL);
1378 /* This actually isn't right... should look at the #address-cells
1379 * property of the i2c bus node etc. etc.
1381 sprintf(tmp_buf, "%s@%x,%x",
1382 dp->name, regs[0], regs[1]);
1385 /* "name@reg0[,reg1]" */
1386 static void __init usb_path_component(struct device_node *dp, char *tmp_buf)
1388 struct property *prop;
1391 prop = of_find_property(dp, "reg", NULL);
1397 if (prop->length == sizeof(u32) || regs[1] == 1) {
1398 sprintf(tmp_buf, "%s@%x",
1401 sprintf(tmp_buf, "%s@%x,%x",
1402 dp->name, regs[0], regs[1]);
1406 /* "name@reg0reg1[,reg2reg3]" */
1407 static void __init ieee1394_path_component(struct device_node *dp, char *tmp_buf)
1409 struct property *prop;
1412 prop = of_find_property(dp, "reg", NULL);
1418 if (regs[2] || regs[3]) {
1419 sprintf(tmp_buf, "%s@%08x%08x,%04x%08x",
1420 dp->name, regs[0], regs[1], regs[2], regs[3]);
1422 sprintf(tmp_buf, "%s@%08x%08x",
1423 dp->name, regs[0], regs[1]);
1427 static void __init __build_path_component(struct device_node *dp, char *tmp_buf)
1429 struct device_node *parent = dp->parent;
1431 if (parent != NULL) {
1432 if (!strcmp(parent->type, "pci") ||
1433 !strcmp(parent->type, "pciex"))
1434 return pci_path_component(dp, tmp_buf);
1435 if (!strcmp(parent->type, "sbus"))
1436 return sbus_path_component(dp, tmp_buf);
1437 if (!strcmp(parent->type, "upa"))
1438 return upa_path_component(dp, tmp_buf);
1439 if (!strcmp(parent->type, "ebus"))
1440 return ebus_path_component(dp, tmp_buf);
1441 if (!strcmp(parent->name, "usb") ||
1442 !strcmp(parent->name, "hub"))
1443 return usb_path_component(dp, tmp_buf);
1444 if (!strcmp(parent->type, "i2c"))
1445 return i2c_path_component(dp, tmp_buf);
1446 if (!strcmp(parent->type, "firewire"))
1447 return ieee1394_path_component(dp, tmp_buf);
1448 if (!strcmp(parent->type, "virtual-devices"))
1449 return vdev_path_component(dp, tmp_buf);
1451 /* "isa" is handled with platform naming */
1454 /* Use platform naming convention. */
1455 if (tlb_type == hypervisor)
1456 return sun4v_path_component(dp, tmp_buf);
1458 return sun4u_path_component(dp, tmp_buf);
1461 static char * __init build_path_component(struct device_node *dp)
1463 char tmp_buf[64], *n;
1466 __build_path_component(dp, tmp_buf);
1467 if (tmp_buf[0] == '\0')
1468 strcpy(tmp_buf, dp->name);
1470 n = prom_early_alloc(strlen(tmp_buf) + 1);
1476 static char * __init build_full_name(struct device_node *dp)
1478 int len, ourlen, plen;
1481 plen = strlen(dp->parent->full_name);
1482 ourlen = strlen(dp->path_component_name);
1483 len = ourlen + plen + 2;
1485 n = prom_early_alloc(len);
1486 strcpy(n, dp->parent->full_name);
1487 if (!is_root_node(dp->parent)) {
1488 strcpy(n + plen, "/");
1491 strcpy(n + plen, dp->path_component_name);
1496 static unsigned int unique_id;
1498 static struct property * __init build_one_prop(phandle node, char *prev, char *special_name, void *special_val, int special_len)
1500 static struct property *tmp = NULL;
1505 memset(p, 0, sizeof(*p) + 32);
1508 p = prom_early_alloc(sizeof(struct property) + 32);
1509 p->unique_id = unique_id++;
1512 p->name = (char *) (p + 1);
1514 strcpy(p->name, special_name);
1515 p->length = special_len;
1516 p->value = prom_early_alloc(special_len);
1517 memcpy(p->value, special_val, special_len);
1520 prom_firstprop(node, p->name);
1522 prom_nextprop(node, prev, p->name);
1524 if (strlen(p->name) == 0) {
1528 p->length = prom_getproplen(node, p->name);
1529 if (p->length <= 0) {
1532 p->value = prom_early_alloc(p->length + 1);
1533 prom_getproperty(node, p->name, p->value, p->length);
1534 ((unsigned char *)p->value)[p->length] = '\0';
1540 static struct property * __init build_prop_list(phandle node)
1542 struct property *head, *tail;
1544 head = tail = build_one_prop(node, NULL,
1545 ".node", &node, sizeof(node));
1547 tail->next = build_one_prop(node, NULL, NULL, NULL, 0);
1550 tail->next = build_one_prop(node, tail->name,
1558 static char * __init get_one_property(phandle node, const char *name)
1560 char *buf = "<NULL>";
1563 len = prom_getproplen(node, name);
1565 buf = prom_early_alloc(len);
1566 prom_getproperty(node, name, buf, len);
1572 static struct device_node * __init create_node(phandle node, struct device_node *parent)
1574 struct device_node *dp;
1579 dp = prom_early_alloc(sizeof(*dp));
1580 dp->unique_id = unique_id++;
1581 dp->parent = parent;
1583 kref_init(&dp->kref);
1585 dp->name = get_one_property(node, "name");
1586 dp->type = get_one_property(node, "device_type");
1589 dp->properties = build_prop_list(node);
1596 static struct device_node * __init build_tree(struct device_node *parent, phandle node, struct device_node ***nextp)
1598 struct device_node *ret = NULL, *prev_sibling = NULL;
1599 struct device_node *dp;
1602 dp = create_node(node, parent);
1607 prev_sibling->sibling = dp;
1614 *nextp = &dp->allnext;
1616 dp->path_component_name = build_path_component(dp);
1617 dp->full_name = build_full_name(dp);
1619 dp->child = build_tree(dp, prom_getchild(node), nextp);
1621 node = prom_getsibling(node);
1627 static const char *get_mid_prop(void)
1629 return (tlb_type == spitfire ? "upa-portid" : "portid");
1632 struct device_node *of_find_node_by_cpuid(int cpuid)
1634 struct device_node *dp;
1635 const char *mid_prop = get_mid_prop();
1637 for_each_node_by_type(dp, "cpu") {
1638 int id = of_getintprop_default(dp, mid_prop, -1);
1639 const char *this_mid_prop = mid_prop;
1642 this_mid_prop = "cpuid";
1643 id = of_getintprop_default(dp, this_mid_prop, -1);
1647 prom_printf("OF: Serious problem, cpu lacks "
1648 "%s property", this_mid_prop);
1657 static void __init of_fill_in_cpu_data(void)
1659 struct device_node *dp;
1660 const char *mid_prop = get_mid_prop();
1663 for_each_node_by_type(dp, "cpu") {
1664 int cpuid = of_getintprop_default(dp, mid_prop, -1);
1665 const char *this_mid_prop = mid_prop;
1666 struct device_node *portid_parent;
1669 portid_parent = NULL;
1671 this_mid_prop = "cpuid";
1672 cpuid = of_getintprop_default(dp, this_mid_prop, -1);
1678 portid_parent = portid_parent->parent;
1681 portid = of_getintprop_default(portid_parent,
1690 prom_printf("OF: Serious problem, cpu lacks "
1691 "%s property", this_mid_prop);
1698 if (cpuid >= NR_CPUS)
1701 /* On uniprocessor we only want the values for the
1702 * real physical cpu the kernel booted onto, however
1703 * cpu_data() only has one entry at index 0.
1705 if (cpuid != real_hard_smp_processor_id())
1710 cpu_data(cpuid).clock_tick =
1711 of_getintprop_default(dp, "clock-frequency", 0);
1713 if (portid_parent) {
1714 cpu_data(cpuid).dcache_size =
1715 of_getintprop_default(dp, "l1-dcache-size",
1717 cpu_data(cpuid).dcache_line_size =
1718 of_getintprop_default(dp, "l1-dcache-line-size",
1720 cpu_data(cpuid).icache_size =
1721 of_getintprop_default(dp, "l1-icache-size",
1723 cpu_data(cpuid).icache_line_size =
1724 of_getintprop_default(dp, "l1-icache-line-size",
1726 cpu_data(cpuid).ecache_size =
1727 of_getintprop_default(dp, "l2-cache-size", 0);
1728 cpu_data(cpuid).ecache_line_size =
1729 of_getintprop_default(dp, "l2-cache-line-size", 0);
1730 if (!cpu_data(cpuid).ecache_size ||
1731 !cpu_data(cpuid).ecache_line_size) {
1732 cpu_data(cpuid).ecache_size =
1733 of_getintprop_default(portid_parent,
1736 cpu_data(cpuid).ecache_line_size =
1737 of_getintprop_default(portid_parent,
1738 "l2-cache-line-size", 64);
1741 cpu_data(cpuid).core_id = portid + 1;
1742 cpu_data(cpuid).proc_id = portid;
1744 sparc64_multi_core = 1;
1747 cpu_data(cpuid).dcache_size =
1748 of_getintprop_default(dp, "dcache-size", 16 * 1024);
1749 cpu_data(cpuid).dcache_line_size =
1750 of_getintprop_default(dp, "dcache-line-size", 32);
1752 cpu_data(cpuid).icache_size =
1753 of_getintprop_default(dp, "icache-size", 16 * 1024);
1754 cpu_data(cpuid).icache_line_size =
1755 of_getintprop_default(dp, "icache-line-size", 32);
1757 cpu_data(cpuid).ecache_size =
1758 of_getintprop_default(dp, "ecache-size",
1760 cpu_data(cpuid).ecache_line_size =
1761 of_getintprop_default(dp, "ecache-line-size", 64);
1763 cpu_data(cpuid).core_id = 0;
1764 cpu_data(cpuid).proc_id = -1;
1768 cpu_set(cpuid, cpu_present_map);
1769 cpu_set(cpuid, cpu_possible_map);
1773 smp_fill_in_sib_core_maps();
1776 void __init prom_build_devicetree(void)
1778 struct device_node **nextp;
1780 allnodes = create_node(prom_root_node, NULL);
1781 allnodes->path_component_name = "";
1782 allnodes->full_name = "/";
1784 nextp = &allnodes->allnext;
1785 allnodes->child = build_tree(allnodes,
1786 prom_getchild(allnodes->node),
1788 printk("PROM: Built device tree with %u bytes of memory.\n",
1789 prom_early_allocated);
1791 if (tlb_type != hypervisor)
1792 of_fill_in_cpu_data();