arch/x86/kernel/apic/apic_numachip.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Numascale NumaConnect-Specific APIC Code
   7  *
   8  * Copyright (C) 2011 Numascale AS. All rights reserved.
   9  *
  10  * Send feedback to <support@numascale.com>
  11  *
  12  */
  13
  14 #include <linux/init.h>
  15
  16 #include <asm/numachip/numachip.h>
  17 #include <asm/numachip/numachip_csr.h>
  18 #include <asm/ipi.h>
  19 #include <asm/apic_flat_64.h>
  20 #include <asm/pgtable.h>
  21 #include <asm/pci_x86.h>
  22
  23 u8 numachip_system __read_mostly;
  24 static const struct apic apic_numachip1;
  25 static const struct apic apic_numachip2;
  26 static void (*numachip_apic_icr_write)(int apicid, unsigned int val) __read_mostly;
  27
  28 static unsigned int numachip1_get_apic_id(unsigned long x)
  29 {
  30         unsigned long value;
  31         unsigned int id = (x >> 24) & 0xff;
  32
  33         if (static_cpu_has_safe(X86_FEATURE_NODEID_MSR)) {
  34                 rdmsrl(MSR_FAM10H_NODE_ID, value);
  35                 id |= (value << 2) & 0xff00;
  36         }
  37
  38         return id;
  39 }
  40
  41 static unsigned long numachip1_set_apic_id(unsigned int id)
  42 {
  43         unsigned long x;
  44
  45         x = ((id & 0xffU) << 24);
  46         return x;
  47 }
  48
  49 static unsigned int numachip2_get_apic_id(unsigned long x)
  50 {
  51         u64 mcfg;
  52
  53         rdmsrl(MSR_FAM10H_MMIO_CONF_BASE, mcfg);
  54         return ((mcfg >> (28 - 8)) & 0xfff00) | (x >> 24);
  55 }
  56
  57 static unsigned long numachip2_set_apic_id(unsigned int id)
  58 {
  59         return id << 24;
  60 }
  61
  62 static int numachip_apic_id_valid(int apicid)
  63 {
  64         /* Trust what bootloader passes in MADT */
  65         return 1;
  66 }
  67
  68 static int numachip_apic_id_registered(void)
  69 {
  70         return 1;
  71 }
  72
  73 static int numachip_phys_pkg_id(int initial_apic_id, int index_msb)
  74 {
  75         return initial_apic_id >> index_msb;
  76 }
  77
  78 static void numachip1_apic_icr_write(int apicid, unsigned int val)
  79 {
  80         write_lcsr(CSR_G3_EXT_IRQ_GEN, (apicid << 16) | val);
  81 }
  82
  83 static void numachip2_apic_icr_write(int apicid, unsigned int val)
  84 {
  85         numachip2_write32_lcsr(NUMACHIP2_APIC_ICR, (apicid << 12) | val);
  86 }
  87
  88 static int numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip)
  89 {
  90         numachip_apic_icr_write(phys_apicid, APIC_DM_INIT);
  91         numachip_apic_icr_write(phys_apicid, APIC_DM_STARTUP |
  92                 (start_rip >> 12));
  93
  94         return 0;
  95 }
  96
  97 static void numachip_send_IPI_one(int cpu, int vector)
  98 {
  99         int local_apicid, apicid = per_cpu(x86_cpu_to_apicid, cpu);
 100         unsigned int dmode;
 101
 102         preempt_disable();
 103         local_apicid = __this_cpu_read(x86_cpu_to_apicid);
 104
 105         /* Send via local APIC where non-local part matches */
 106         if (!((apicid ^ local_apicid) >> NUMACHIP_LAPIC_BITS)) {
 107                 unsigned long flags;
 108
 109                 local_irq_save(flags);
 110                 __default_send_IPI_dest_field(apicid, vector,
 111                         APIC_DEST_PHYSICAL);
 112                 local_irq_restore(flags);
 113                 preempt_enable();
 114                 return;
 115         }
 116         preempt_enable();
 117
 118         dmode = (vector == NMI_VECTOR) ? APIC_DM_NMI : APIC_DM_FIXED;
 119         numachip_apic_icr_write(apicid, dmode | vector);
 120 }
 121
 122 static void numachip_send_IPI_mask(const struct cpumask *mask, int vector)
 123 {
 124         unsigned int cpu;
 125
 126         for_each_cpu(cpu, mask)
 127                 numachip_send_IPI_one(cpu, vector);
 128 }
 129
 130 static void numachip_send_IPI_mask_allbutself(const struct cpumask *mask,
 131                                                 int vector)
 132 {
 133         unsigned int this_cpu = smp_processor_id();
 134         unsigned int cpu;
 135
 136         for_each_cpu(cpu, mask) {
 137                 if (cpu != this_cpu)
 138                         numachip_send_IPI_one(cpu, vector);
 139         }
 140 }
 141
 142 static void numachip_send_IPI_allbutself(int vector)
 143 {
 144         unsigned int this_cpu = smp_processor_id();
 145         unsigned int cpu;
 146
 147         for_each_online_cpu(cpu) {
 148                 if (cpu != this_cpu)
 149                         numachip_send_IPI_one(cpu, vector);
 150         }
 151 }
 152
 153 static void numachip_send_IPI_all(int vector)
 154 {
 155         numachip_send_IPI_mask(cpu_online_mask, vector);
 156 }
 157
 158 static void numachip_send_IPI_self(int vector)
 159 {
 160         apic_write(APIC_SELF_IPI, vector);
 161 }
 162
 163 static int __init numachip1_probe(void)
 164 {
 165         return apic == &apic_numachip1;
 166 }
 167
 168 static int __init numachip2_probe(void)
 169 {
 170         return apic == &apic_numachip2;
 171 }
 172
 173 static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
 174 {
 175         u64 val;
 176         u32 nodes = 1;
 177
 178         this_cpu_write(cpu_llc_id, node);
 179
 180         /* Account for nodes per socket in multi-core-module processors */
 181         if (static_cpu_has_safe(X86_FEATURE_NODEID_MSR)) {
 182                 rdmsrl(MSR_FAM10H_NODE_ID, val);
 183                 nodes = ((val >> 3) & 7) + 1;
 184         }
 185
 186         c->phys_proc_id = node / nodes;
 187 }
 188
 189 static int __init numachip_system_init(void)
 190 {
 191         /* Map the LCSR area and set up the apic_icr_write function */
 192         switch (numachip_system) {
 193         case 1:
 194                 init_extra_mapping_uc(NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_SIZE);
 195                 numachip_apic_icr_write = numachip1_apic_icr_write;
 196                 x86_init.pci.arch_init = pci_numachip_init;
 197                 break;
 198         case 2:
 199                 init_extra_mapping_uc(NUMACHIP2_LCSR_BASE, NUMACHIP2_LCSR_SIZE);
 200                 numachip_apic_icr_write = numachip2_apic_icr_write;
 201
 202                 /* Use MCFG config cycles rather than locked CF8 cycles */
 203                 raw_pci_ops = &pci_mmcfg;
 204                 break;
 205         default:
 206                 return 0;
 207         }
 208
 209         x86_cpuinit.fixup_cpu_id = fixup_cpu_id;
 210
 211         return 0;
 212 }
 213 early_initcall(numachip_system_init);
 214
 215 static int numachip1_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 216 {
 217         if ((strncmp(oem_id, "NUMASC", 6) != 0) ||
 218             (strncmp(oem_table_id, "NCONNECT", 8) != 0))
 219                 return 0;
 220
 221         numachip_system = 1;
 222
 223         return 1;
 224 }
 225
 226 static int numachip2_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 227 {
 228         if ((strncmp(oem_id, "NUMASC", 6) != 0) ||
 229             (strncmp(oem_table_id, "NCONECT2", 8) != 0))
 230                 return 0;
 231
 232         numachip_system = 2;
 233
 234         return 1;
 235 }
 236
 237 /* APIC IPIs are queued */
 238 static void numachip_apic_wait_icr_idle(void)
 239 {
 240 }
 241
 242 /* APIC NMI IPIs are queued */
 243 static u32 numachip_safe_apic_wait_icr_idle(void)
 244 {
 245         return 0;
 246 }
 247
 248 static const struct apic apic_numachip1 __refconst = {
 249         .name                           = "NumaConnect system",
 250         .probe                          = numachip1_probe,
 251         .acpi_madt_oem_check            = numachip1_acpi_madt_oem_check,
 252         .apic_id_valid                  = numachip_apic_id_valid,
 253         .apic_id_registered             = numachip_apic_id_registered,
 254
 255         .irq_delivery_mode              = dest_Fixed,
 256         .irq_dest_mode                  = 0, /* physical */
 257
 258         .target_cpus                    = online_target_cpus,
 259         .disable_esr                    = 0,
 260         .dest_logical                   = 0,
 261         .check_apicid_used              = NULL,
 262
 263         .vector_allocation_domain       = default_vector_allocation_domain,
 264         .init_apic_ldr                  = flat_init_apic_ldr,
 265
 266         .ioapic_phys_id_map             = NULL,
 267         .setup_apic_routing             = NULL,
 268         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 269         .apicid_to_cpu_present          = NULL,
 270         .check_phys_apicid_present      = default_check_phys_apicid_present,
 271         .phys_pkg_id                    = numachip_phys_pkg_id,
 272
 273         .get_apic_id                    = numachip1_get_apic_id,
 274         .set_apic_id                    = numachip1_set_apic_id,
 275         .apic_id_mask                   = 0xffU << 24,
 276
 277         .cpu_mask_to_apicid_and         = default_cpu_mask_to_apicid_and,
 278
 279         .send_IPI_mask                  = numachip_send_IPI_mask,
 280         .send_IPI_mask_allbutself       = numachip_send_IPI_mask_allbutself,
 281         .send_IPI_allbutself            = numachip_send_IPI_allbutself,
 282         .send_IPI_all                   = numachip_send_IPI_all,
 283         .send_IPI_self                  = numachip_send_IPI_self,
 284
 285         .wakeup_secondary_cpu           = numachip_wakeup_secondary,
 286         .inquire_remote_apic            = NULL, /* REMRD not supported */
 287
 288         .read                           = native_apic_mem_read,
 289         .write                          = native_apic_mem_write,
 290         .eoi_write                      = native_apic_mem_write,
 291         .icr_read                       = native_apic_icr_read,
 292         .icr_write                      = native_apic_icr_write,
 293         .wait_icr_idle                  = numachip_apic_wait_icr_idle,
 294         .safe_wait_icr_idle             = numachip_safe_apic_wait_icr_idle,
 295 };
 296
 297 apic_driver(apic_numachip1);
 298
 299 static const struct apic apic_numachip2 __refconst = {
 300         .name                           = "NumaConnect2 system",
 301         .probe                          = numachip2_probe,
 302         .acpi_madt_oem_check            = numachip2_acpi_madt_oem_check,
 303         .apic_id_valid                  = numachip_apic_id_valid,
 304         .apic_id_registered             = numachip_apic_id_registered,
 305
 306         .irq_delivery_mode              = dest_Fixed,
 307         .irq_dest_mode                  = 0, /* physical */
 308
 309         .target_cpus                    = online_target_cpus,
 310         .disable_esr                    = 0,
 311         .dest_logical                   = 0,
 312         .check_apicid_used              = NULL,
 313
 314         .vector_allocation_domain       = default_vector_allocation_domain,
 315         .init_apic_ldr                  = flat_init_apic_ldr,
 316
 317         .ioapic_phys_id_map             = NULL,
 318         .setup_apic_routing             = NULL,
 319         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 320         .apicid_to_cpu_present          = NULL,
 321         .check_phys_apicid_present      = default_check_phys_apicid_present,
 322         .phys_pkg_id                    = numachip_phys_pkg_id,
 323
 324         .get_apic_id                    = numachip2_get_apic_id,
 325         .set_apic_id                    = numachip2_set_apic_id,
 326         .apic_id_mask                   = 0xffU << 24,
 327
 328         .cpu_mask_to_apicid_and         = default_cpu_mask_to_apicid_and,
 329
 330         .send_IPI_mask                  = numachip_send_IPI_mask,
 331         .send_IPI_mask_allbutself       = numachip_send_IPI_mask_allbutself,
 332         .send_IPI_allbutself            = numachip_send_IPI_allbutself,
 333         .send_IPI_all                   = numachip_send_IPI_all,
 334         .send_IPI_self                  = numachip_send_IPI_self,
 335
 336         .wakeup_secondary_cpu           = numachip_wakeup_secondary,
 337         .inquire_remote_apic            = NULL, /* REMRD not supported */
 338
 339         .read                           = native_apic_mem_read,
 340         .write                          = native_apic_mem_write,
 341         .eoi_write                      = native_apic_mem_write,
 342         .icr_read                       = native_apic_icr_read,
 343         .icr_write                      = native_apic_icr_write,
 344         .wait_icr_idle                  = numachip_apic_wait_icr_idle,
 345         .safe_wait_icr_idle             = numachip_safe_apic_wait_icr_idle,
 346 };
 347
 348 apic_driver(apic_numachip2);