arch/x86/kernel/apic/x2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2009 Silicon Graphics, Inc. All rights reserved.
   9  */
  10 #include <linux/cpumask.h>
  11 #include <linux/hardirq.h>
  12 #include <linux/proc_fs.h>
  13 #include <linux/threads.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/string.h>
  17 #include <linux/ctype.h>
  18 #include <linux/sched.h>
  19 #include <linux/timer.h>
  20 #include <linux/slab.h>
  21 #include <linux/cpu.h>
  22 #include <linux/init.h>
  23 #include <linux/io.h>
  24 #include <linux/pci.h>
  25 #include <linux/kdebug.h>
  26
  27 #include <asm/uv/uv_mmrs.h>
  28 #include <asm/uv/uv_hub.h>
  29 #include <asm/current.h>
  30 #include <asm/pgtable.h>
  31 #include <asm/uv/bios.h>
  32 #include <asm/uv/uv.h>
  33 #include <asm/apic.h>
  34 #include <asm/ipi.h>
  35 #include <asm/smp.h>
  36 #include <asm/x86_init.h>
  37
  38 DEFINE_PER_CPU(int, x2apic_extra_bits);
  39
  40 #define PR_DEVEL(fmt, args...)  pr_devel("%s: " fmt, __func__, args)
  41
  42 static enum uv_system_type uv_system_type;
  43 static u64 gru_start_paddr, gru_end_paddr;
  44 int uv_min_hub_revision_id;
  45 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
  46 static DEFINE_SPINLOCK(uv_nmi_lock);
  47
  48 static inline bool is_GRU_range(u64 start, u64 end)
  49 {
  50         return start >= gru_start_paddr && end <= gru_end_paddr;
  51 }
  52
  53 static bool uv_is_untracked_pat_range(u64 start, u64 end)
  54 {
  55         return is_ISA_range(start, end) || is_GRU_range(start, end);
  56 }
  57
  58 static int early_get_nodeid(void)
  59 {
  60         union uvh_node_id_u node_id;
  61         unsigned long *mmr;
  62
  63         mmr = early_ioremap(UV_LOCAL_MMR_BASE | UVH_NODE_ID, sizeof(*mmr));
  64         node_id.v = *mmr;
  65         early_iounmap(mmr, sizeof(*mmr));
  66
  67         /* Currently, all blades have same revision number */
  68         uv_min_hub_revision_id = node_id.s.revision;
  69
  70         return node_id.s.node_id;
  71 }
  72
  73 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
  74 {
  75         int nodeid;
  76
  77         if (!strcmp(oem_id, "SGI")) {
  78                 nodeid = early_get_nodeid();
  79                 x86_platform.is_untracked_pat_range =  uv_is_untracked_pat_range;
  80                 x86_platform.nmi_init = uv_nmi_init;
  81                 if (!strcmp(oem_table_id, "UVL"))
  82                         uv_system_type = UV_LEGACY_APIC;
  83                 else if (!strcmp(oem_table_id, "UVX"))
  84                         uv_system_type = UV_X2APIC;
  85                 else if (!strcmp(oem_table_id, "UVH")) {
  86                         __get_cpu_var(x2apic_extra_bits) =
  87                                 nodeid << (UV_APIC_PNODE_SHIFT - 1);
  88                         uv_system_type = UV_NON_UNIQUE_APIC;
  89                         return 1;
  90                 }
  91         }
  92         return 0;
  93 }
  94
  95 enum uv_system_type get_uv_system_type(void)
  96 {
  97         return uv_system_type;
  98 }
  99
 100 int is_uv_system(void)
 101 {
 102         return uv_system_type != UV_NONE;
 103 }
 104 EXPORT_SYMBOL_GPL(is_uv_system);
 105
 106 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
 107 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
 108
 109 struct uv_blade_info *uv_blade_info;
 110 EXPORT_SYMBOL_GPL(uv_blade_info);
 111
 112 short *uv_node_to_blade;
 113 EXPORT_SYMBOL_GPL(uv_node_to_blade);
 114
 115 short *uv_cpu_to_blade;
 116 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
 117
 118 short uv_possible_blades;
 119 EXPORT_SYMBOL_GPL(uv_possible_blades);
 120
 121 unsigned long sn_rtc_cycles_per_second;
 122 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
 123
 124 static const struct cpumask *uv_target_cpus(void)
 125 {
 126         return cpu_online_mask;
 127 }
 128
 129 static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
 130 {
 131         cpumask_clear(retmask);
 132         cpumask_set_cpu(cpu, retmask);
 133 }
 134
 135 static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 136 {
 137 #ifdef CONFIG_SMP
 138         unsigned long val;
 139         int pnode;
 140
 141         pnode = uv_apicid_to_pnode(phys_apicid);
 142         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 143             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 144             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 145             APIC_DM_INIT;
 146         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 147         mdelay(10);
 148
 149         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 150             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 151             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 152             APIC_DM_STARTUP;
 153         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 154
 155         atomic_set(&init_deasserted, 1);
 156 #endif
 157         return 0;
 158 }
 159
 160 static void uv_send_IPI_one(int cpu, int vector)
 161 {
 162         unsigned long apicid;
 163         int pnode;
 164
 165         apicid = per_cpu(x86_cpu_to_apicid, cpu);
 166         pnode = uv_apicid_to_pnode(apicid);
 167         uv_hub_send_ipi(pnode, apicid, vector);
 168 }
 169
 170 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
 171 {
 172         unsigned int cpu;
 173
 174         for_each_cpu(cpu, mask)
 175                 uv_send_IPI_one(cpu, vector);
 176 }
 177
 178 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 179 {
 180         unsigned int this_cpu = smp_processor_id();
 181         unsigned int cpu;
 182
 183         for_each_cpu(cpu, mask) {
 184                 if (cpu != this_cpu)
 185                         uv_send_IPI_one(cpu, vector);
 186         }
 187 }
 188
 189 static void uv_send_IPI_allbutself(int vector)
 190 {
 191         unsigned int this_cpu = smp_processor_id();
 192         unsigned int cpu;
 193
 194         for_each_online_cpu(cpu) {
 195                 if (cpu != this_cpu)
 196                         uv_send_IPI_one(cpu, vector);
 197         }
 198 }
 199
 200 static void uv_send_IPI_all(int vector)
 201 {
 202         uv_send_IPI_mask(cpu_online_mask, vector);
 203 }
 204
 205 static int uv_apic_id_registered(void)
 206 {
 207         return 1;
 208 }
 209
 210 static void uv_init_apic_ldr(void)
 211 {
 212 }
 213
 214 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
 215 {
 216         /*
 217          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 218          * May as well be the first.
 219          */
 220         int cpu = cpumask_first(cpumask);
 221
 222         if ((unsigned)cpu < nr_cpu_ids)
 223                 return per_cpu(x86_cpu_to_apicid, cpu);
 224         else
 225                 return BAD_APICID;
 226 }
 227
 228 static unsigned int
 229 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 230                           const struct cpumask *andmask)
 231 {
 232         int cpu;
 233
 234         /*
 235          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 236          * May as well be the first.
 237          */
 238         for_each_cpu_and(cpu, cpumask, andmask) {
 239                 if (cpumask_test_cpu(cpu, cpu_online_mask))
 240                         break;
 241         }
 242         return per_cpu(x86_cpu_to_apicid, cpu);
 243 }
 244
 245 static unsigned int x2apic_get_apic_id(unsigned long x)
 246 {
 247         unsigned int id;
 248
 249         WARN_ON(preemptible() && num_online_cpus() > 1);
 250         id = x | __get_cpu_var(x2apic_extra_bits);
 251
 252         return id;
 253 }
 254
 255 static unsigned long set_apic_id(unsigned int id)
 256 {
 257         unsigned long x;
 258
 259         /* maskout x2apic_extra_bits ? */
 260         x = id;
 261         return x;
 262 }
 263
 264 static unsigned int uv_read_apic_id(void)
 265 {
 266
 267         return x2apic_get_apic_id(apic_read(APIC_ID));
 268 }
 269
 270 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
 271 {
 272         return uv_read_apic_id() >> index_msb;
 273 }
 274
 275 static void uv_send_IPI_self(int vector)
 276 {
 277         apic_write(APIC_SELF_IPI, vector);
 278 }
 279
 280 struct apic __refdata apic_x2apic_uv_x = {
 281
 282         .name                           = "UV large system",
 283         .probe                          = NULL,
 284         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
 285         .apic_id_registered             = uv_apic_id_registered,
 286
 287         .irq_delivery_mode              = dest_Fixed,
 288         .irq_dest_mode                  = 0, /* physical */
 289
 290         .target_cpus                    = uv_target_cpus,
 291         .disable_esr                    = 0,
 292         .dest_logical                   = APIC_DEST_LOGICAL,
 293         .check_apicid_used              = NULL,
 294         .check_apicid_present           = NULL,
 295
 296         .vector_allocation_domain       = uv_vector_allocation_domain,
 297         .init_apic_ldr                  = uv_init_apic_ldr,
 298
 299         .ioapic_phys_id_map             = NULL,
 300         .setup_apic_routing             = NULL,
 301         .multi_timer_check              = NULL,
 302         .apicid_to_node                 = NULL,
 303         .cpu_to_logical_apicid          = NULL,
 304         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 305         .apicid_to_cpu_present          = NULL,
 306         .setup_portio_remap             = NULL,
 307         .check_phys_apicid_present      = default_check_phys_apicid_present,
 308         .enable_apic_mode               = NULL,
 309         .phys_pkg_id                    = uv_phys_pkg_id,
 310         .mps_oem_check                  = NULL,
 311
 312         .get_apic_id                    = x2apic_get_apic_id,
 313         .set_apic_id                    = set_apic_id,
 314         .apic_id_mask                   = 0xFFFFFFFFu,
 315
 316         .cpu_mask_to_apicid             = uv_cpu_mask_to_apicid,
 317         .cpu_mask_to_apicid_and         = uv_cpu_mask_to_apicid_and,
 318
 319         .send_IPI_mask                  = uv_send_IPI_mask,
 320         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
 321         .send_IPI_allbutself            = uv_send_IPI_allbutself,
 322         .send_IPI_all                   = uv_send_IPI_all,
 323         .send_IPI_self                  = uv_send_IPI_self,
 324
 325         .wakeup_secondary_cpu           = uv_wakeup_secondary,
 326         .trampoline_phys_low            = DEFAULT_TRAMPOLINE_PHYS_LOW,
 327         .trampoline_phys_high           = DEFAULT_TRAMPOLINE_PHYS_HIGH,
 328         .wait_for_init_deassert         = NULL,
 329         .smp_callin_clear_local_apic    = NULL,
 330         .inquire_remote_apic            = NULL,
 331
 332         .read                           = native_apic_msr_read,
 333         .write                          = native_apic_msr_write,
 334         .icr_read                       = native_x2apic_icr_read,
 335         .icr_write                      = native_x2apic_icr_write,
 336         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
 337         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
 338 };
 339
 340 static __cpuinit void set_x2apic_extra_bits(int pnode)
 341 {
 342         __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
 343 }
 344
 345 /*
 346  * Called on boot cpu.
 347  */
 348 static __init int boot_pnode_to_blade(int pnode)
 349 {
 350         int blade;
 351
 352         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 353                 if (pnode == uv_blade_info[blade].pnode)
 354                         return blade;
 355         BUG();
 356 }
 357
 358 struct redir_addr {
 359         unsigned long redirect;
 360         unsigned long alias;
 361 };
 362
 363 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 364
 365 static __initdata struct redir_addr redir_addrs[] = {
 366         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
 367         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
 368         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
 369 };
 370
 371 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 372 {
 373         union uvh_si_alias0_overlay_config_u alias;
 374         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 375         int i;
 376
 377         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 378                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
 379                 if (alias.s.enable && alias.s.base == 0) {
 380                         *size = (1UL << alias.s.m_alias);
 381                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 382                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 383                         return;
 384                 }
 385         }
 386         *base = *size = 0;
 387 }
 388
 389 enum map_type {map_wb, map_uc};
 390
 391 static __init void map_high(char *id, unsigned long base, int pshift,
 392                         int bshift, int max_pnode, enum map_type map_type)
 393 {
 394         unsigned long bytes, paddr;
 395
 396         paddr = base << pshift;
 397         bytes = (1UL << bshift) * (max_pnode + 1);
 398         printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
 399                                                 paddr + bytes);
 400         if (map_type == map_uc)
 401                 init_extra_mapping_uc(paddr, bytes);
 402         else
 403                 init_extra_mapping_wb(paddr, bytes);
 404
 405 }
 406 static __init void map_gru_high(int max_pnode)
 407 {
 408         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 409         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 410
 411         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 412         if (gru.s.enable) {
 413                 map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
 414                 gru_start_paddr = ((u64)gru.s.base << shift);
 415                 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
 416
 417         }
 418 }
 419
 420 static __init void map_mmr_high(int max_pnode)
 421 {
 422         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 423         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 424
 425         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 426         if (mmr.s.enable)
 427                 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
 428 }
 429
 430 static __init void map_mmioh_high(int max_pnode)
 431 {
 432         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 433         int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 434
 435         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
 436         if (mmioh.s.enable)
 437                 map_high("MMIOH", mmioh.s.base, shift, mmioh.s.m_io,
 438                         max_pnode, map_uc);
 439 }
 440
 441 static __init void map_low_mmrs(void)
 442 {
 443         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 444         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 445 }
 446
 447 static __init void uv_rtc_init(void)
 448 {
 449         long status;
 450         u64 ticks_per_sec;
 451
 452         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
 453                                         &ticks_per_sec);
 454         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
 455                 printk(KERN_WARNING
 456                         "unable to determine platform RTC clock frequency, "
 457                         "guessing.\n");
 458                 /* BIOS gives wrong value for clock freq. so guess */
 459                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 460         } else
 461                 sn_rtc_cycles_per_second = ticks_per_sec;
 462 }
 463
 464 /*
 465  * percpu heartbeat timer
 466  */
 467 static void uv_heartbeat(unsigned long ignored)
 468 {
 469         struct timer_list *timer = &uv_hub_info->scir.timer;
 470         unsigned char bits = uv_hub_info->scir.state;
 471
 472         /* flip heartbeat bit */
 473         bits ^= SCIR_CPU_HEARTBEAT;
 474
 475         /* is this cpu idle? */
 476         if (idle_cpu(raw_smp_processor_id()))
 477                 bits &= ~SCIR_CPU_ACTIVITY;
 478         else
 479                 bits |= SCIR_CPU_ACTIVITY;
 480
 481         /* update system controller interface reg */
 482         uv_set_scir_bits(bits);
 483
 484         /* enable next timer period */
 485         mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
 486 }
 487
 488 static void __cpuinit uv_heartbeat_enable(int cpu)
 489 {
 490         while (!uv_cpu_hub_info(cpu)->scir.enabled) {
 491                 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
 492
 493                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
 494                 setup_timer(timer, uv_heartbeat, cpu);
 495                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
 496                 add_timer_on(timer, cpu);
 497                 uv_cpu_hub_info(cpu)->scir.enabled = 1;
 498
 499                 /* also ensure that boot cpu is enabled */
 500                 cpu = 0;
 501         }
 502 }
 503
 504 #ifdef CONFIG_HOTPLUG_CPU
 505 static void __cpuinit uv_heartbeat_disable(int cpu)
 506 {
 507         if (uv_cpu_hub_info(cpu)->scir.enabled) {
 508                 uv_cpu_hub_info(cpu)->scir.enabled = 0;
 509                 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
 510         }
 511         uv_set_cpu_scir_bits(cpu, 0xff);
 512 }
 513
 514 /*
 515  * cpu hotplug notifier
 516  */
 517 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
 518                                        unsigned long action, void *hcpu)
 519 {
 520         long cpu = (long)hcpu;
 521
 522         switch (action) {
 523         case CPU_ONLINE:
 524                 uv_heartbeat_enable(cpu);
 525                 break;
 526         case CPU_DOWN_PREPARE:
 527                 uv_heartbeat_disable(cpu);
 528                 break;
 529         default:
 530                 break;
 531         }
 532         return NOTIFY_OK;
 533 }
 534
 535 static __init void uv_scir_register_cpu_notifier(void)
 536 {
 537         hotcpu_notifier(uv_scir_cpu_notify, 0);
 538 }
 539
 540 #else /* !CONFIG_HOTPLUG_CPU */
 541
 542 static __init void uv_scir_register_cpu_notifier(void)
 543 {
 544 }
 545
 546 static __init int uv_init_heartbeat(void)
 547 {
 548         int cpu;
 549
 550         if (is_uv_system())
 551                 for_each_online_cpu(cpu)
 552                         uv_heartbeat_enable(cpu);
 553         return 0;
 554 }
 555
 556 late_initcall(uv_init_heartbeat);
 557
 558 #endif /* !CONFIG_HOTPLUG_CPU */
 559
 560 /* Direct Legacy VGA I/O traffic to designated IOH */
 561 int uv_set_vga_state(struct pci_dev *pdev, bool decode,
 562                       unsigned int command_bits, bool change_bridge)
 563 {
 564         int domain, bus, rc;
 565
 566         PR_DEVEL("devfn %x decode %d cmd %x chg_brdg %d\n",
 567                         pdev->devfn, decode, command_bits, change_bridge);
 568
 569         if (!change_bridge)
 570                 return 0;
 571
 572         if ((command_bits & PCI_COMMAND_IO) == 0)
 573                 return 0;
 574
 575         domain = pci_domain_nr(pdev->bus);
 576         bus = pdev->bus->number;
 577
 578         rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
 579         PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
 580
 581         return rc;
 582 }
 583
 584 /*
 585  * Called on each cpu to initialize the per_cpu UV data area.
 586  * FIXME: hotplug not supported yet
 587  */
 588 void __cpuinit uv_cpu_init(void)
 589 {
 590         /* CPU 0 initilization will be done via uv_system_init. */
 591         if (!uv_blade_info)
 592                 return;
 593
 594         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 595
 596         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 597                 set_x2apic_extra_bits(uv_hub_info->pnode);
 598 }
 599
 600 /*
 601  * When NMI is received, print a stack trace.
 602  */
 603 int uv_handle_nmi(struct notifier_block *self, unsigned long reason, void *data)
 604 {
 605         if (reason != DIE_NMI_IPI)
 606                 return NOTIFY_OK;
 607         /*
 608          * Use a lock so only one cpu prints at a time
 609          * to prevent intermixed output.
 610          */
 611         spin_lock(&uv_nmi_lock);
 612         pr_info("NMI stack dump cpu %u:\n", smp_processor_id());
 613         dump_stack();
 614         spin_unlock(&uv_nmi_lock);
 615
 616         return NOTIFY_STOP;
 617 }
 618
 619 static struct notifier_block uv_dump_stack_nmi_nb = {
 620         .notifier_call  = uv_handle_nmi
 621 };
 622
 623 void uv_register_nmi_notifier(void)
 624 {
 625         if (register_die_notifier(&uv_dump_stack_nmi_nb))
 626                 printk(KERN_WARNING "UV NMI handler failed to register\n");
 627 }
 628
 629 void uv_nmi_init(void)
 630 {
 631         unsigned int value;
 632
 633         /*
 634          * Unmask NMI on all cpus
 635          */
 636         value = apic_read(APIC_LVT1) | APIC_DM_NMI;
 637         value &= ~APIC_LVT_MASKED;
 638         apic_write(APIC_LVT1, value);
 639 }
 640
 641 void __init uv_system_init(void)
 642 {
 643         union uvh_si_addr_map_config_u m_n_config;
 644         union uvh_node_id_u node_id;
 645         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
 646         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
 647         int gnode_extra, max_pnode = 0;
 648         unsigned long mmr_base, present, paddr;
 649         unsigned short pnode_mask;
 650
 651         map_low_mmrs();
 652
 653         m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
 654         m_val = m_n_config.s.m_skt;
 655         n_val = m_n_config.s.n_skt;
 656         mmr_base =
 657             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 658             ~UV_MMR_ENABLE;
 659         pnode_mask = (1 << n_val) - 1;
 660         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 661         gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
 662         gnode_upper = ((unsigned long)gnode_extra  << m_val);
 663         printk(KERN_DEBUG "UV: N %d, M %d, gnode_upper 0x%lx, gnode_extra 0x%x\n",
 664                         n_val, m_val, gnode_upper, gnode_extra);
 665
 666         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 667
 668         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
 669                 uv_possible_blades +=
 670                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
 671         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
 672
 673         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
 674         uv_blade_info = kmalloc(bytes, GFP_KERNEL);
 675         BUG_ON(!uv_blade_info);
 676         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 677                 uv_blade_info[blade].memory_nid = -1;
 678
 679         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 680
 681         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
 682         uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
 683         BUG_ON(!uv_node_to_blade);
 684         memset(uv_node_to_blade, 255, bytes);
 685
 686         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
 687         uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
 688         BUG_ON(!uv_cpu_to_blade);
 689         memset(uv_cpu_to_blade, 255, bytes);
 690
 691         blade = 0;
 692         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
 693                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
 694                 for (j = 0; j < 64; j++) {
 695                         if (!test_bit(j, &present))
 696                                 continue;
 697                         uv_blade_info[blade].pnode = (i * 64 + j);
 698                         uv_blade_info[blade].nr_possible_cpus = 0;
 699                         uv_blade_info[blade].nr_online_cpus = 0;
 700                         blade++;
 701                 }
 702         }
 703
 704         uv_bios_init();
 705         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
 706                             &sn_region_size, &system_serial_number);
 707         uv_rtc_init();
 708
 709         for_each_present_cpu(cpu) {
 710                 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
 711
 712                 nid = cpu_to_node(cpu);
 713                 pnode = uv_apicid_to_pnode(apicid);
 714                 blade = boot_pnode_to_blade(pnode);
 715                 lcpu = uv_blade_info[blade].nr_possible_cpus;
 716                 uv_blade_info[blade].nr_possible_cpus++;
 717
 718                 /* Any node on the blade, else will contain -1. */
 719                 uv_blade_info[blade].memory_nid = nid;
 720
 721                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 722                 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
 723                 uv_cpu_hub_info(cpu)->m_val = m_val;
 724                 uv_cpu_hub_info(cpu)->n_val = n_val;
 725                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 726                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 727                 uv_cpu_hub_info(cpu)->pnode = pnode;
 728                 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
 729                 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
 730                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 731                 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
 732                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
 733                 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
 734                 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
 735                 uv_node_to_blade[nid] = blade;
 736                 uv_cpu_to_blade[cpu] = blade;
 737                 max_pnode = max(pnode, max_pnode);
 738         }
 739
 740         /* Add blade/pnode info for nodes without cpus */
 741         for_each_online_node(nid) {
 742                 if (uv_node_to_blade[nid] >= 0)
 743                         continue;
 744                 paddr = node_start_pfn(nid) << PAGE_SHIFT;
 745                 paddr = uv_soc_phys_ram_to_gpa(paddr);
 746                 pnode = (paddr >> m_val) & pnode_mask;
 747                 blade = boot_pnode_to_blade(pnode);
 748                 uv_node_to_blade[nid] = blade;
 749                 max_pnode = max(pnode, max_pnode);
 750         }
 751
 752         map_gru_high(max_pnode);
 753         map_mmr_high(max_pnode);
 754         map_mmioh_high(max_pnode);
 755
 756         uv_cpu_init();
 757         uv_scir_register_cpu_notifier();
 758         uv_register_nmi_notifier();
 759         proc_mkdir("sgi_uv", NULL);
 760
 761         /* register Legacy VGA I/O redirection handler */
 762         pci_register_set_vga_state(uv_set_vga_state);
 763 }