arch/x86/kernel/hpet.c

   1 #include <linux/clocksource.h>
   2 #include <linux/clockchips.h>
   3 #include <linux/interrupt.h>
   4 #include <linux/export.h>
   5 #include <linux/delay.h>
   6 #include <linux/errno.h>
   7 #include <linux/i8253.h>
   8 #include <linux/slab.h>
   9 #include <linux/hpet.h>
  10 #include <linux/init.h>
  11 #include <linux/cpu.h>
  12 #include <linux/pm.h>
  13 #include <linux/io.h>
  14
  15 #include <asm/irqdomain.h>
  16 #include <asm/fixmap.h>
  17 #include <asm/hpet.h>
  18 #include <asm/time.h>
  19
  20 #define HPET_MASK                       CLOCKSOURCE_MASK(32)
  21
  22 /* FSEC = 10^-15
  23    NSEC = 10^-9 */
  24 #define FSEC_PER_NSEC                   1000000L
  25
  26 #define HPET_DEV_USED_BIT               2
  27 #define HPET_DEV_USED                   (1 << HPET_DEV_USED_BIT)
  28 #define HPET_DEV_VALID                  0x8
  29 #define HPET_DEV_FSB_CAP                0x1000
  30 #define HPET_DEV_PERI_CAP               0x2000
  31
  32 #define HPET_MIN_CYCLES                 128
  33 #define HPET_MIN_PROG_DELTA             (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
  34
  35 /*
  36  * HPET address is set in acpi/boot.c, when an ACPI entry exists
  37  */
  38 unsigned long                           hpet_address;
  39 u8                                      hpet_blockid; /* OS timer block num */
  40 bool                                    hpet_msi_disable;
  41
  42 #ifdef CONFIG_PCI_MSI
  43 static unsigned int                     hpet_num_timers;
  44 #endif
  45 static void __iomem                     *hpet_virt_address;
  46
  47 struct hpet_dev {
  48         struct clock_event_device       evt;
  49         unsigned int                    num;
  50         int                             cpu;
  51         unsigned int                    irq;
  52         unsigned int                    flags;
  53         char                            name[10];
  54 };
  55
  56 inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
  57 {
  58         return container_of(evtdev, struct hpet_dev, evt);
  59 }
  60
  61 inline unsigned int hpet_readl(unsigned int a)
  62 {
  63         return readl(hpet_virt_address + a);
  64 }
  65
  66 static inline void hpet_writel(unsigned int d, unsigned int a)
  67 {
  68         writel(d, hpet_virt_address + a);
  69 }
  70
  71 #ifdef CONFIG_X86_64
  72 #include <asm/pgtable.h>
  73 #endif
  74
  75 static inline void hpet_set_mapping(void)
  76 {
  77         hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
  78 }
  79
  80 static inline void hpet_clear_mapping(void)
  81 {
  82         iounmap(hpet_virt_address);
  83         hpet_virt_address = NULL;
  84 }
  85
  86 /*
  87  * HPET command line enable / disable
  88  */
  89 bool boot_hpet_disable;
  90 bool hpet_force_user;
  91 static bool hpet_verbose;
  92
  93 static int __init hpet_setup(char *str)
  94 {
  95         while (str) {
  96                 char *next = strchr(str, ',');
  97
  98                 if (next)
  99                         *next++ = 0;
 100                 if (!strncmp("disable", str, 7))
 101                         boot_hpet_disable = true;
 102                 if (!strncmp("force", str, 5))
 103                         hpet_force_user = true;
 104                 if (!strncmp("verbose", str, 7))
 105                         hpet_verbose = true;
 106                 str = next;
 107         }
 108         return 1;
 109 }
 110 __setup("hpet=", hpet_setup);
 111
 112 static int __init disable_hpet(char *str)
 113 {
 114         boot_hpet_disable = true;
 115         return 1;
 116 }
 117 __setup("nohpet", disable_hpet);
 118
 119 static inline int is_hpet_capable(void)
 120 {
 121         return !boot_hpet_disable && hpet_address;
 122 }
 123
 124 /*
 125  * HPET timer interrupt enable / disable
 126  */
 127 static bool hpet_legacy_int_enabled;
 128
 129 /**
 130  * is_hpet_enabled - check whether the hpet timer interrupt is enabled
 131  */
 132 int is_hpet_enabled(void)
 133 {
 134         return is_hpet_capable() && hpet_legacy_int_enabled;
 135 }
 136 EXPORT_SYMBOL_GPL(is_hpet_enabled);
 137
 138 static void _hpet_print_config(const char *function, int line)
 139 {
 140         u32 i, timers, l, h;
 141         printk(KERN_INFO "hpet: %s(%d):\n", function, line);
 142         l = hpet_readl(HPET_ID);
 143         h = hpet_readl(HPET_PERIOD);
 144         timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
 145         printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
 146         l = hpet_readl(HPET_CFG);
 147         h = hpet_readl(HPET_STATUS);
 148         printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
 149         l = hpet_readl(HPET_COUNTER);
 150         h = hpet_readl(HPET_COUNTER+4);
 151         printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
 152
 153         for (i = 0; i < timers; i++) {
 154                 l = hpet_readl(HPET_Tn_CFG(i));
 155                 h = hpet_readl(HPET_Tn_CFG(i)+4);
 156                 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
 157                        i, l, h);
 158                 l = hpet_readl(HPET_Tn_CMP(i));
 159                 h = hpet_readl(HPET_Tn_CMP(i)+4);
 160                 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
 161                        i, l, h);
 162                 l = hpet_readl(HPET_Tn_ROUTE(i));
 163                 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
 164                 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
 165                        i, l, h);
 166         }
 167 }
 168
 169 #define hpet_print_config()                                     \
 170 do {                                                            \
 171         if (hpet_verbose)                                       \
 172                 _hpet_print_config(__func__, __LINE__); \
 173 } while (0)
 174
 175 /*
 176  * When the hpet driver (/dev/hpet) is enabled, we need to reserve
 177  * timer 0 and timer 1 in case of RTC emulation.
 178  */
 179 #ifdef CONFIG_HPET
 180
 181 static void hpet_reserve_msi_timers(struct hpet_data *hd);
 182
 183 static void hpet_reserve_platform_timers(unsigned int id)
 184 {
 185         struct hpet __iomem *hpet = hpet_virt_address;
 186         struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
 187         unsigned int nrtimers, i;
 188         struct hpet_data hd;
 189
 190         nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
 191
 192         memset(&hd, 0, sizeof(hd));
 193         hd.hd_phys_address      = hpet_address;
 194         hd.hd_address           = hpet;
 195         hd.hd_nirqs             = nrtimers;
 196         hpet_reserve_timer(&hd, 0);
 197
 198 #ifdef CONFIG_HPET_EMULATE_RTC
 199         hpet_reserve_timer(&hd, 1);
 200 #endif
 201
 202         /*
 203          * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
 204          * is wrong for i8259!) not the output IRQ.  Many BIOS writers
 205          * don't bother configuring *any* comparator interrupts.
 206          */
 207         hd.hd_irq[0] = HPET_LEGACY_8254;
 208         hd.hd_irq[1] = HPET_LEGACY_RTC;
 209
 210         for (i = 2; i < nrtimers; timer++, i++) {
 211                 hd.hd_irq[i] = (readl(&timer->hpet_config) &
 212                         Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
 213         }
 214
 215         hpet_reserve_msi_timers(&hd);
 216
 217         hpet_alloc(&hd);
 218
 219 }
 220 #else
 221 static void hpet_reserve_platform_timers(unsigned int id) { }
 222 #endif
 223
 224 /*
 225  * Common hpet info
 226  */
 227 static unsigned long hpet_freq;
 228
 229 static struct clock_event_device hpet_clockevent;
 230
 231 static void hpet_stop_counter(void)
 232 {
 233         u32 cfg = hpet_readl(HPET_CFG);
 234         cfg &= ~HPET_CFG_ENABLE;
 235         hpet_writel(cfg, HPET_CFG);
 236 }
 237
 238 static void hpet_reset_counter(void)
 239 {
 240         hpet_writel(0, HPET_COUNTER);
 241         hpet_writel(0, HPET_COUNTER + 4);
 242 }
 243
 244 static void hpet_start_counter(void)
 245 {
 246         unsigned int cfg = hpet_readl(HPET_CFG);
 247         cfg |= HPET_CFG_ENABLE;
 248         hpet_writel(cfg, HPET_CFG);
 249 }
 250
 251 static void hpet_restart_counter(void)
 252 {
 253         hpet_stop_counter();
 254         hpet_reset_counter();
 255         hpet_start_counter();
 256 }
 257
 258 static void hpet_resume_device(void)
 259 {
 260         force_hpet_resume();
 261 }
 262
 263 static void hpet_resume_counter(struct clocksource *cs)
 264 {
 265         hpet_resume_device();
 266         hpet_restart_counter();
 267 }
 268
 269 static void hpet_enable_legacy_int(void)
 270 {
 271         unsigned int cfg = hpet_readl(HPET_CFG);
 272
 273         cfg |= HPET_CFG_LEGACY;
 274         hpet_writel(cfg, HPET_CFG);
 275         hpet_legacy_int_enabled = true;
 276 }
 277
 278 static void hpet_legacy_clockevent_register(void)
 279 {
 280         /* Start HPET legacy interrupts */
 281         hpet_enable_legacy_int();
 282
 283         /*
 284          * Start hpet with the boot cpu mask and make it
 285          * global after the IO_APIC has been initialized.
 286          */
 287         hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
 288         clockevents_config_and_register(&hpet_clockevent, hpet_freq,
 289                                         HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
 290         global_clock_event = &hpet_clockevent;
 291         printk(KERN_DEBUG "hpet clockevent registered\n");
 292 }
 293
 294 static int hpet_set_periodic(struct clock_event_device *evt, int timer)
 295 {
 296         unsigned int cfg, cmp, now;
 297         uint64_t delta;
 298
 299         hpet_stop_counter();
 300         delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult;
 301         delta >>= evt->shift;
 302         now = hpet_readl(HPET_COUNTER);
 303         cmp = now + (unsigned int)delta;
 304         cfg = hpet_readl(HPET_Tn_CFG(timer));
 305         cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL |
 306                HPET_TN_32BIT;
 307         hpet_writel(cfg, HPET_Tn_CFG(timer));
 308         hpet_writel(cmp, HPET_Tn_CMP(timer));
 309         udelay(1);
 310         /*
 311          * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
 312          * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
 313          * bit is automatically cleared after the first write.
 314          * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
 315          * Publication # 24674)
 316          */
 317         hpet_writel((unsigned int)delta, HPET_Tn_CMP(timer));
 318         hpet_start_counter();
 319         hpet_print_config();
 320
 321         return 0;
 322 }
 323
 324 static int hpet_set_oneshot(struct clock_event_device *evt, int timer)
 325 {
 326         unsigned int cfg;
 327
 328         cfg = hpet_readl(HPET_Tn_CFG(timer));
 329         cfg &= ~HPET_TN_PERIODIC;
 330         cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
 331         hpet_writel(cfg, HPET_Tn_CFG(timer));
 332
 333         return 0;
 334 }
 335
 336 static int hpet_shutdown(struct clock_event_device *evt, int timer)
 337 {
 338         unsigned int cfg;
 339
 340         cfg = hpet_readl(HPET_Tn_CFG(timer));
 341         cfg &= ~HPET_TN_ENABLE;
 342         hpet_writel(cfg, HPET_Tn_CFG(timer));
 343
 344         return 0;
 345 }
 346
 347 static int hpet_resume(struct clock_event_device *evt, int timer)
 348 {
 349         if (!timer) {
 350                 hpet_enable_legacy_int();
 351         } else {
 352                 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 353
 354                 irq_domain_activate_irq(irq_get_irq_data(hdev->irq));
 355                 disable_irq(hdev->irq);
 356                 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
 357                 enable_irq(hdev->irq);
 358         }
 359         hpet_print_config();
 360
 361         return 0;
 362 }
 363
 364 static int hpet_next_event(unsigned long delta,
 365                            struct clock_event_device *evt, int timer)
 366 {
 367         u32 cnt;
 368         s32 res;
 369
 370         cnt = hpet_readl(HPET_COUNTER);
 371         cnt += (u32) delta;
 372         hpet_writel(cnt, HPET_Tn_CMP(timer));
 373
 374         /*
 375          * HPETs are a complete disaster. The compare register is
 376          * based on a equal comparison and neither provides a less
 377          * than or equal functionality (which would require to take
 378          * the wraparound into account) nor a simple count down event
 379          * mode. Further the write to the comparator register is
 380          * delayed internally up to two HPET clock cycles in certain
 381          * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
 382          * longer delays. We worked around that by reading back the
 383          * compare register, but that required another workaround for
 384          * ICH9,10 chips where the first readout after write can
 385          * return the old stale value. We already had a minimum
 386          * programming delta of 5us enforced, but a NMI or SMI hitting
 387          * between the counter readout and the comparator write can
 388          * move us behind that point easily. Now instead of reading
 389          * the compare register back several times, we make the ETIME
 390          * decision based on the following: Return ETIME if the
 391          * counter value after the write is less than HPET_MIN_CYCLES
 392          * away from the event or if the counter is already ahead of
 393          * the event. The minimum programming delta for the generic
 394          * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
 395          */
 396         res = (s32)(cnt - hpet_readl(HPET_COUNTER));
 397
 398         return res < HPET_MIN_CYCLES ? -ETIME : 0;
 399 }
 400
 401 static int hpet_legacy_shutdown(struct clock_event_device *evt)
 402 {
 403         return hpet_shutdown(evt, 0);
 404 }
 405
 406 static int hpet_legacy_set_oneshot(struct clock_event_device *evt)
 407 {
 408         return hpet_set_oneshot(evt, 0);
 409 }
 410
 411 static int hpet_legacy_set_periodic(struct clock_event_device *evt)
 412 {
 413         return hpet_set_periodic(evt, 0);
 414 }
 415
 416 static int hpet_legacy_resume(struct clock_event_device *evt)
 417 {
 418         return hpet_resume(evt, 0);
 419 }
 420
 421 static int hpet_legacy_next_event(unsigned long delta,
 422                         struct clock_event_device *evt)
 423 {
 424         return hpet_next_event(delta, evt, 0);
 425 }
 426
 427 /*
 428  * The hpet clock event device
 429  */
 430 static struct clock_event_device hpet_clockevent = {
 431         .name                   = "hpet",
 432         .features               = CLOCK_EVT_FEAT_PERIODIC |
 433                                   CLOCK_EVT_FEAT_ONESHOT,
 434         .set_state_periodic     = hpet_legacy_set_periodic,
 435         .set_state_oneshot      = hpet_legacy_set_oneshot,
 436         .set_state_shutdown     = hpet_legacy_shutdown,
 437         .tick_resume            = hpet_legacy_resume,
 438         .set_next_event         = hpet_legacy_next_event,
 439         .irq                    = 0,
 440         .rating                 = 50,
 441 };
 442
 443 /*
 444  * HPET MSI Support
 445  */
 446 #ifdef CONFIG_PCI_MSI
 447
 448 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
 449 static struct hpet_dev  *hpet_devs;
 450 static struct irq_domain *hpet_domain;
 451
 452 void hpet_msi_unmask(struct irq_data *data)
 453 {
 454         struct hpet_dev *hdev = irq_data_get_irq_handler_data(data);
 455         unsigned int cfg;
 456
 457         /* unmask it */
 458         cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
 459         cfg |= HPET_TN_ENABLE | HPET_TN_FSB;
 460         hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
 461 }
 462
 463 void hpet_msi_mask(struct irq_data *data)
 464 {
 465         struct hpet_dev *hdev = irq_data_get_irq_handler_data(data);
 466         unsigned int cfg;
 467
 468         /* mask it */
 469         cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
 470         cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
 471         hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
 472 }
 473
 474 void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
 475 {
 476         hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
 477         hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
 478 }
 479
 480 void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
 481 {
 482         msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
 483         msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
 484         msg->address_hi = 0;
 485 }
 486
 487 static int hpet_msi_shutdown(struct clock_event_device *evt)
 488 {
 489         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 490
 491         return hpet_shutdown(evt, hdev->num);
 492 }
 493
 494 static int hpet_msi_set_oneshot(struct clock_event_device *evt)
 495 {
 496         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 497
 498         return hpet_set_oneshot(evt, hdev->num);
 499 }
 500
 501 static int hpet_msi_set_periodic(struct clock_event_device *evt)
 502 {
 503         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 504
 505         return hpet_set_periodic(evt, hdev->num);
 506 }
 507
 508 static int hpet_msi_resume(struct clock_event_device *evt)
 509 {
 510         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 511
 512         return hpet_resume(evt, hdev->num);
 513 }
 514
 515 static int hpet_msi_next_event(unsigned long delta,
 516                                 struct clock_event_device *evt)
 517 {
 518         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 519         return hpet_next_event(delta, evt, hdev->num);
 520 }
 521
 522 static irqreturn_t hpet_interrupt_handler(int irq, void *data)
 523 {
 524         struct hpet_dev *dev = (struct hpet_dev *)data;
 525         struct clock_event_device *hevt = &dev->evt;
 526
 527         if (!hevt->event_handler) {
 528                 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
 529                                 dev->num);
 530                 return IRQ_HANDLED;
 531         }
 532
 533         hevt->event_handler(hevt);
 534         return IRQ_HANDLED;
 535 }
 536
 537 static int hpet_setup_irq(struct hpet_dev *dev)
 538 {
 539
 540         if (request_irq(dev->irq, hpet_interrupt_handler,
 541                         IRQF_TIMER | IRQF_NOBALANCING,
 542                         dev->name, dev))
 543                 return -1;
 544
 545         disable_irq(dev->irq);
 546         irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
 547         enable_irq(dev->irq);
 548
 549         printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
 550                          dev->name, dev->irq);
 551
 552         return 0;
 553 }
 554
 555 /* This should be called in specific @cpu */
 556 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
 557 {
 558         struct clock_event_device *evt = &hdev->evt;
 559
 560         WARN_ON(cpu != smp_processor_id());
 561         if (!(hdev->flags & HPET_DEV_VALID))
 562                 return;
 563
 564         hdev->cpu = cpu;
 565         per_cpu(cpu_hpet_dev, cpu) = hdev;
 566         evt->name = hdev->name;
 567         hpet_setup_irq(hdev);
 568         evt->irq = hdev->irq;
 569
 570         evt->rating = 110;
 571         evt->features = CLOCK_EVT_FEAT_ONESHOT;
 572         if (hdev->flags & HPET_DEV_PERI_CAP) {
 573                 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
 574                 evt->set_state_periodic = hpet_msi_set_periodic;
 575         }
 576
 577         evt->set_state_shutdown = hpet_msi_shutdown;
 578         evt->set_state_oneshot = hpet_msi_set_oneshot;
 579         evt->tick_resume = hpet_msi_resume;
 580         evt->set_next_event = hpet_msi_next_event;
 581         evt->cpumask = cpumask_of(hdev->cpu);
 582
 583         clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
 584                                         0x7FFFFFFF);
 585 }
 586
 587 #ifdef CONFIG_HPET
 588 /* Reserve at least one timer for userspace (/dev/hpet) */
 589 #define RESERVE_TIMERS 1
 590 #else
 591 #define RESERVE_TIMERS 0
 592 #endif
 593
 594 static void hpet_msi_capability_lookup(unsigned int start_timer)
 595 {
 596         unsigned int id;
 597         unsigned int num_timers;
 598         unsigned int num_timers_used = 0;
 599         int i, irq;
 600
 601         if (hpet_msi_disable)
 602                 return;
 603
 604         if (boot_cpu_has(X86_FEATURE_ARAT))
 605                 return;
 606         id = hpet_readl(HPET_ID);
 607
 608         num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
 609         num_timers++; /* Value read out starts from 0 */
 610         hpet_print_config();
 611
 612         hpet_domain = hpet_create_irq_domain(hpet_blockid);
 613         if (!hpet_domain)
 614                 return;
 615
 616         hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
 617         if (!hpet_devs)
 618                 return;
 619
 620         hpet_num_timers = num_timers;
 621
 622         for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
 623                 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
 624                 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
 625
 626                 /* Only consider HPET timer with MSI support */
 627                 if (!(cfg & HPET_TN_FSB_CAP))
 628                         continue;
 629
 630                 hdev->flags = 0;
 631                 if (cfg & HPET_TN_PERIODIC_CAP)
 632                         hdev->flags |= HPET_DEV_PERI_CAP;
 633                 sprintf(hdev->name, "hpet%d", i);
 634                 hdev->num = i;
 635
 636                 irq = hpet_assign_irq(hpet_domain, hdev, hdev->num);
 637                 if (irq <= 0)
 638                         continue;
 639
 640                 hdev->irq = irq;
 641                 hdev->flags |= HPET_DEV_FSB_CAP;
 642                 hdev->flags |= HPET_DEV_VALID;
 643                 num_timers_used++;
 644                 if (num_timers_used == num_possible_cpus())
 645                         break;
 646         }
 647
 648         printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
 649                 num_timers, num_timers_used);
 650 }
 651
 652 #ifdef CONFIG_HPET
 653 static void hpet_reserve_msi_timers(struct hpet_data *hd)
 654 {
 655         int i;
 656
 657         if (!hpet_devs)
 658                 return;
 659
 660         for (i = 0; i < hpet_num_timers; i++) {
 661                 struct hpet_dev *hdev = &hpet_devs[i];
 662
 663                 if (!(hdev->flags & HPET_DEV_VALID))
 664                         continue;
 665
 666                 hd->hd_irq[hdev->num] = hdev->irq;
 667                 hpet_reserve_timer(hd, hdev->num);
 668         }
 669 }
 670 #endif
 671
 672 static struct hpet_dev *hpet_get_unused_timer(void)
 673 {
 674         int i;
 675
 676         if (!hpet_devs)
 677                 return NULL;
 678
 679         for (i = 0; i < hpet_num_timers; i++) {
 680                 struct hpet_dev *hdev = &hpet_devs[i];
 681
 682                 if (!(hdev->flags & HPET_DEV_VALID))
 683                         continue;
 684                 if (test_and_set_bit(HPET_DEV_USED_BIT,
 685                         (unsigned long *)&hdev->flags))
 686                         continue;
 687                 return hdev;
 688         }
 689         return NULL;
 690 }
 691
 692 struct hpet_work_struct {
 693         struct delayed_work work;
 694         struct completion complete;
 695 };
 696
 697 static void hpet_work(struct work_struct *w)
 698 {
 699         struct hpet_dev *hdev;
 700         int cpu = smp_processor_id();
 701         struct hpet_work_struct *hpet_work;
 702
 703         hpet_work = container_of(w, struct hpet_work_struct, work.work);
 704
 705         hdev = hpet_get_unused_timer();
 706         if (hdev)
 707                 init_one_hpet_msi_clockevent(hdev, cpu);
 708
 709         complete(&hpet_work->complete);
 710 }
 711
 712 static int hpet_cpuhp_notify(struct notifier_block *n,
 713                 unsigned long action, void *hcpu)
 714 {
 715         unsigned long cpu = (unsigned long)hcpu;
 716         struct hpet_work_struct work;
 717         struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
 718
 719         switch (action & 0xf) {
 720         case CPU_ONLINE:
 721                 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
 722                 init_completion(&work.complete);
 723                 /* FIXME: add schedule_work_on() */
 724                 schedule_delayed_work_on(cpu, &work.work, 0);
 725                 wait_for_completion(&work.complete);
 726                 destroy_delayed_work_on_stack(&work.work);
 727                 break;
 728         case CPU_DEAD:
 729                 if (hdev) {
 730                         free_irq(hdev->irq, hdev);
 731                         hdev->flags &= ~HPET_DEV_USED;
 732                         per_cpu(cpu_hpet_dev, cpu) = NULL;
 733                 }
 734                 break;
 735         }
 736         return NOTIFY_OK;
 737 }
 738 #else
 739
 740 static void hpet_msi_capability_lookup(unsigned int start_timer)
 741 {
 742         return;
 743 }
 744
 745 #ifdef CONFIG_HPET
 746 static void hpet_reserve_msi_timers(struct hpet_data *hd)
 747 {
 748         return;
 749 }
 750 #endif
 751
 752 static int hpet_cpuhp_notify(struct notifier_block *n,
 753                 unsigned long action, void *hcpu)
 754 {
 755         return NOTIFY_OK;
 756 }
 757
 758 #endif
 759
 760 /*
 761  * Clock source related code
 762  */
 763 static cycle_t read_hpet(struct clocksource *cs)
 764 {
 765         return (cycle_t)hpet_readl(HPET_COUNTER);
 766 }
 767
 768 static struct clocksource clocksource_hpet = {
 769         .name           = "hpet",
 770         .rating         = 250,
 771         .read           = read_hpet,
 772         .mask           = HPET_MASK,
 773         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 774         .resume         = hpet_resume_counter,
 775         .archdata       = { .vclock_mode = VCLOCK_HPET },
 776 };
 777
 778 static int hpet_clocksource_register(void)
 779 {
 780         u64 start, now;
 781         cycle_t t1;
 782
 783         /* Start the counter */
 784         hpet_restart_counter();
 785
 786         /* Verify whether hpet counter works */
 787         t1 = hpet_readl(HPET_COUNTER);
 788         start = rdtsc();
 789
 790         /*
 791          * We don't know the TSC frequency yet, but waiting for
 792          * 200000 TSC cycles is safe:
 793          * 4 GHz == 50us
 794          * 1 GHz == 200us
 795          */
 796         do {
 797                 rep_nop();
 798                 now = rdtsc();
 799         } while ((now - start) < 200000UL);
 800
 801         if (t1 == hpet_readl(HPET_COUNTER)) {
 802                 printk(KERN_WARNING
 803                        "HPET counter not counting. HPET disabled\n");
 804                 return -ENODEV;
 805         }
 806
 807         clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
 808         return 0;
 809 }
 810
 811 static u32 *hpet_boot_cfg;
 812
 813 /**
 814  * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
 815  */
 816 int __init hpet_enable(void)
 817 {
 818         u32 hpet_period, cfg, id;
 819         u64 freq;
 820         unsigned int i, last;
 821
 822         if (!is_hpet_capable())
 823                 return 0;
 824
 825         hpet_set_mapping();
 826
 827         /*
 828          * Read the period and check for a sane value:
 829          */
 830         hpet_period = hpet_readl(HPET_PERIOD);
 831
 832         /*
 833          * AMD SB700 based systems with spread spectrum enabled use a
 834          * SMM based HPET emulation to provide proper frequency
 835          * setting. The SMM code is initialized with the first HPET
 836          * register access and takes some time to complete. During
 837          * this time the config register reads 0xffffffff. We check
 838          * for max. 1000 loops whether the config register reads a non
 839          * 0xffffffff value to make sure that HPET is up and running
 840          * before we go further. A counting loop is safe, as the HPET
 841          * access takes thousands of CPU cycles. On non SB700 based
 842          * machines this check is only done once and has no side
 843          * effects.
 844          */
 845         for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
 846                 if (i == 1000) {
 847                         printk(KERN_WARNING
 848                                "HPET config register value = 0xFFFFFFFF. "
 849                                "Disabling HPET\n");
 850                         goto out_nohpet;
 851                 }
 852         }
 853
 854         if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
 855                 goto out_nohpet;
 856
 857         /*
 858          * The period is a femto seconds value. Convert it to a
 859          * frequency.
 860          */
 861         freq = FSEC_PER_SEC;
 862         do_div(freq, hpet_period);
 863         hpet_freq = freq;
 864
 865         /*
 866          * Read the HPET ID register to retrieve the IRQ routing
 867          * information and the number of channels
 868          */
 869         id = hpet_readl(HPET_ID);
 870         hpet_print_config();
 871
 872         last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
 873
 874 #ifdef CONFIG_HPET_EMULATE_RTC
 875         /*
 876          * The legacy routing mode needs at least two channels, tick timer
 877          * and the rtc emulation channel.
 878          */
 879         if (!last)
 880                 goto out_nohpet;
 881 #endif
 882
 883         cfg = hpet_readl(HPET_CFG);
 884         hpet_boot_cfg = kmalloc((last + 2) * sizeof(*hpet_boot_cfg),
 885                                 GFP_KERNEL);
 886         if (hpet_boot_cfg)
 887                 *hpet_boot_cfg = cfg;
 888         else
 889                 pr_warn("HPET initial state will not be saved\n");
 890         cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
 891         hpet_writel(cfg, HPET_CFG);
 892         if (cfg)
 893                 pr_warn("HPET: Unrecognized bits %#x set in global cfg\n",
 894                         cfg);
 895
 896         for (i = 0; i <= last; ++i) {
 897                 cfg = hpet_readl(HPET_Tn_CFG(i));
 898                 if (hpet_boot_cfg)
 899                         hpet_boot_cfg[i + 1] = cfg;
 900                 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
 901                 hpet_writel(cfg, HPET_Tn_CFG(i));
 902                 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
 903                          | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
 904                          | HPET_TN_FSB | HPET_TN_FSB_CAP);
 905                 if (cfg)
 906                         pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n",
 907                                 cfg, i);
 908         }
 909         hpet_print_config();
 910
 911         if (hpet_clocksource_register())
 912                 goto out_nohpet;
 913
 914         if (id & HPET_ID_LEGSUP) {
 915                 hpet_legacy_clockevent_register();
 916                 return 1;
 917         }
 918         return 0;
 919
 920 out_nohpet:
 921         hpet_clear_mapping();
 922         hpet_address = 0;
 923         return 0;
 924 }
 925
 926 /*
 927  * Needs to be late, as the reserve_timer code calls kalloc !
 928  *
 929  * Not a problem on i386 as hpet_enable is called from late_time_init,
 930  * but on x86_64 it is necessary !
 931  */
 932 static __init int hpet_late_init(void)
 933 {
 934         int cpu;
 935
 936         if (boot_hpet_disable)
 937                 return -ENODEV;
 938
 939         if (!hpet_address) {
 940                 if (!force_hpet_address)
 941                         return -ENODEV;
 942
 943                 hpet_address = force_hpet_address;
 944                 hpet_enable();
 945         }
 946
 947         if (!hpet_virt_address)
 948                 return -ENODEV;
 949
 950         if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
 951                 hpet_msi_capability_lookup(2);
 952         else
 953                 hpet_msi_capability_lookup(0);
 954
 955         hpet_reserve_platform_timers(hpet_readl(HPET_ID));
 956         hpet_print_config();
 957
 958         if (hpet_msi_disable)
 959                 return 0;
 960
 961         if (boot_cpu_has(X86_FEATURE_ARAT))
 962                 return 0;
 963
 964         cpu_notifier_register_begin();
 965         for_each_online_cpu(cpu) {
 966                 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
 967         }
 968
 969         /* This notifier should be called after workqueue is ready */
 970         __hotcpu_notifier(hpet_cpuhp_notify, -20);
 971         cpu_notifier_register_done();
 972
 973         return 0;
 974 }
 975 fs_initcall(hpet_late_init);
 976
 977 void hpet_disable(void)
 978 {
 979         if (is_hpet_capable() && hpet_virt_address) {
 980                 unsigned int cfg = hpet_readl(HPET_CFG), id, last;
 981
 982                 if (hpet_boot_cfg)
 983                         cfg = *hpet_boot_cfg;
 984                 else if (hpet_legacy_int_enabled) {
 985                         cfg &= ~HPET_CFG_LEGACY;
 986                         hpet_legacy_int_enabled = false;
 987                 }
 988                 cfg &= ~HPET_CFG_ENABLE;
 989                 hpet_writel(cfg, HPET_CFG);
 990
 991                 if (!hpet_boot_cfg)
 992                         return;
 993
 994                 id = hpet_readl(HPET_ID);
 995                 last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
 996
 997                 for (id = 0; id <= last; ++id)
 998                         hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id));
 999
1000                 if (*hpet_boot_cfg & HPET_CFG_ENABLE)
1001                         hpet_writel(*hpet_boot_cfg, HPET_CFG);
1002         }
1003 }
1004
1005 #ifdef CONFIG_HPET_EMULATE_RTC
1006
1007 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
1008  * is enabled, we support RTC interrupt functionality in software.
1009  * RTC has 3 kinds of interrupts:
1010  * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
1011  *    is updated
1012  * 2) Alarm Interrupt - generate an interrupt at a specific time of day
1013  * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
1014  *    2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
1015  * (1) and (2) above are implemented using polling at a frequency of
1016  * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
1017  * overhead. (DEFAULT_RTC_INT_FREQ)
1018  * For (3), we use interrupts at 64Hz or user specified periodic
1019  * frequency, whichever is higher.
1020  */
1021 #include <linux/mc146818rtc.h>
1022 #include <linux/rtc.h>
1023 #include <asm/rtc.h>
1024
1025 #define DEFAULT_RTC_INT_FREQ    64
1026 #define DEFAULT_RTC_SHIFT       6
1027 #define RTC_NUM_INTS            1
1028
1029 static unsigned long hpet_rtc_flags;
1030 static int hpet_prev_update_sec;
1031 static struct rtc_time hpet_alarm_time;
1032 static unsigned long hpet_pie_count;
1033 static u32 hpet_t1_cmp;
1034 static u32 hpet_default_delta;
1035 static u32 hpet_pie_delta;
1036 static unsigned long hpet_pie_limit;
1037
1038 static rtc_irq_handler irq_handler;
1039
1040 /*
1041  * Check that the hpet counter c1 is ahead of the c2
1042  */
1043 static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1044 {
1045         return (s32)(c2 - c1) < 0;
1046 }
1047
1048 /*
1049  * Registers a IRQ handler.
1050  */
1051 int hpet_register_irq_handler(rtc_irq_handler handler)
1052 {
1053         if (!is_hpet_enabled())
1054                 return -ENODEV;
1055         if (irq_handler)
1056                 return -EBUSY;
1057
1058         irq_handler = handler;
1059
1060         return 0;
1061 }
1062 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1063
1064 /*
1065  * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1066  * and does cleanup.
1067  */
1068 void hpet_unregister_irq_handler(rtc_irq_handler handler)
1069 {
1070         if (!is_hpet_enabled())
1071                 return;
1072
1073         irq_handler = NULL;
1074         hpet_rtc_flags = 0;
1075 }
1076 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1077
1078 /*
1079  * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1080  * is not supported by all HPET implementations for timer 1.
1081  *
1082  * hpet_rtc_timer_init() is called when the rtc is initialized.
1083  */
1084 int hpet_rtc_timer_init(void)
1085 {
1086         unsigned int cfg, cnt, delta;
1087         unsigned long flags;
1088
1089         if (!is_hpet_enabled())
1090                 return 0;
1091
1092         if (!hpet_default_delta) {
1093                 uint64_t clc;
1094
1095                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1096                 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1097                 hpet_default_delta = clc;
1098         }
1099
1100         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1101                 delta = hpet_default_delta;
1102         else
1103                 delta = hpet_pie_delta;
1104
1105         local_irq_save(flags);
1106
1107         cnt = delta + hpet_readl(HPET_COUNTER);
1108         hpet_writel(cnt, HPET_T1_CMP);
1109         hpet_t1_cmp = cnt;
1110
1111         cfg = hpet_readl(HPET_T1_CFG);
1112         cfg &= ~HPET_TN_PERIODIC;
1113         cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1114         hpet_writel(cfg, HPET_T1_CFG);
1115
1116         local_irq_restore(flags);
1117
1118         return 1;
1119 }
1120 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1121
1122 static void hpet_disable_rtc_channel(void)
1123 {
1124         u32 cfg = hpet_readl(HPET_T1_CFG);
1125         cfg &= ~HPET_TN_ENABLE;
1126         hpet_writel(cfg, HPET_T1_CFG);
1127 }
1128
1129 /*
1130  * The functions below are called from rtc driver.
1131  * Return 0 if HPET is not being used.
1132  * Otherwise do the necessary changes and return 1.
1133  */
1134 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1135 {
1136         if (!is_hpet_enabled())
1137                 return 0;
1138
1139         hpet_rtc_flags &= ~bit_mask;
1140         if (unlikely(!hpet_rtc_flags))
1141                 hpet_disable_rtc_channel();
1142
1143         return 1;
1144 }
1145 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1146
1147 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1148 {
1149         unsigned long oldbits = hpet_rtc_flags;
1150
1151         if (!is_hpet_enabled())
1152                 return 0;
1153
1154         hpet_rtc_flags |= bit_mask;
1155
1156         if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1157                 hpet_prev_update_sec = -1;
1158
1159         if (!oldbits)
1160                 hpet_rtc_timer_init();
1161
1162         return 1;
1163 }
1164 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1165
1166 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1167                         unsigned char sec)
1168 {
1169         if (!is_hpet_enabled())
1170                 return 0;
1171
1172         hpet_alarm_time.tm_hour = hrs;
1173         hpet_alarm_time.tm_min = min;
1174         hpet_alarm_time.tm_sec = sec;
1175
1176         return 1;
1177 }
1178 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1179
1180 int hpet_set_periodic_freq(unsigned long freq)
1181 {
1182         uint64_t clc;
1183
1184         if (!is_hpet_enabled())
1185                 return 0;
1186
1187         if (freq <= DEFAULT_RTC_INT_FREQ)
1188                 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1189         else {
1190                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1191                 do_div(clc, freq);
1192                 clc >>= hpet_clockevent.shift;
1193                 hpet_pie_delta = clc;
1194                 hpet_pie_limit = 0;
1195         }
1196         return 1;
1197 }
1198 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1199
1200 int hpet_rtc_dropped_irq(void)
1201 {
1202         return is_hpet_enabled();
1203 }
1204 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1205
1206 static void hpet_rtc_timer_reinit(void)
1207 {
1208         unsigned int delta;
1209         int lost_ints = -1;
1210
1211         if (unlikely(!hpet_rtc_flags))
1212                 hpet_disable_rtc_channel();
1213
1214         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1215                 delta = hpet_default_delta;
1216         else
1217                 delta = hpet_pie_delta;
1218
1219         /*
1220          * Increment the comparator value until we are ahead of the
1221          * current count.
1222          */
1223         do {
1224                 hpet_t1_cmp += delta;
1225                 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1226                 lost_ints++;
1227         } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1228
1229         if (lost_ints) {
1230                 if (hpet_rtc_flags & RTC_PIE)
1231                         hpet_pie_count += lost_ints;
1232                 if (printk_ratelimit())
1233                         printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1234                                 lost_ints);
1235         }
1236 }
1237
1238 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1239 {
1240         struct rtc_time curr_time;
1241         unsigned long rtc_int_flag = 0;
1242
1243         hpet_rtc_timer_reinit();
1244         memset(&curr_time, 0, sizeof(struct rtc_time));
1245
1246         if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1247                 get_rtc_time(&curr_time);
1248
1249         if (hpet_rtc_flags & RTC_UIE &&
1250             curr_time.tm_sec != hpet_prev_update_sec) {
1251                 if (hpet_prev_update_sec >= 0)
1252                         rtc_int_flag = RTC_UF;
1253                 hpet_prev_update_sec = curr_time.tm_sec;
1254         }
1255
1256         if (hpet_rtc_flags & RTC_PIE &&
1257             ++hpet_pie_count >= hpet_pie_limit) {
1258                 rtc_int_flag |= RTC_PF;
1259                 hpet_pie_count = 0;
1260         }
1261
1262         if (hpet_rtc_flags & RTC_AIE &&
1263             (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1264             (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1265             (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1266                         rtc_int_flag |= RTC_AF;
1267
1268         if (rtc_int_flag) {
1269                 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1270                 if (irq_handler)
1271                         irq_handler(rtc_int_flag, dev_id);
1272         }
1273         return IRQ_HANDLED;
1274 }
1275 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
1276 #endif