drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "gmc_v8_0.h"
  27 #include "amdgpu_ucode.h"
  28
  29 #include "gmc/gmc_8_1_d.h"
  30 #include "gmc/gmc_8_1_sh_mask.h"
  31
  32 #include "bif/bif_5_0_d.h"
  33 #include "bif/bif_5_0_sh_mask.h"
  34
  35 #include "oss/oss_3_0_d.h"
  36 #include "oss/oss_3_0_sh_mask.h"
  37
  38 #include "vid.h"
  39 #include "vi.h"
  40
  41
  42 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
  43 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  44
  45 MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
  46 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
  47 MODULE_FIRMWARE("amdgpu/fiji_mc.bin");
  48
  49 static const u32 golden_settings_tonga_a11[] =
  50 {
  51         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  52         mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
  53         mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
  54         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  55         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  56         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  57         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  58 };
  59
  60 static const u32 tonga_mgcg_cgcg_init[] =
  61 {
  62         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  63 };
  64
  65 static const u32 golden_settings_fiji_a10[] =
  66 {
  67         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  68         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  69         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  70         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  71 };
  72
  73 static const u32 fiji_mgcg_cgcg_init[] =
  74 {
  75         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  76 };
  77
  78 static const u32 golden_settings_iceland_a11[] =
  79 {
  80         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  81         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  82         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  83         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  84 };
  85
  86 static const u32 iceland_mgcg_cgcg_init[] =
  87 {
  88         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  89 };
  90
  91 static const u32 cz_mgcg_cgcg_init[] =
  92 {
  93         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  94 };
  95
  96 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
  97 {
  98         switch (adev->asic_type) {
  99         case CHIP_TOPAZ:
 100                 amdgpu_program_register_sequence(adev,
 101                                                  iceland_mgcg_cgcg_init,
 102                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
 103                 amdgpu_program_register_sequence(adev,
 104                                                  golden_settings_iceland_a11,
 105                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
 106                 break;
 107         case CHIP_FIJI:
 108                 amdgpu_program_register_sequence(adev,
 109                                                  fiji_mgcg_cgcg_init,
 110                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 111                 amdgpu_program_register_sequence(adev,
 112                                                  golden_settings_fiji_a10,
 113                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 114                 break;
 115         case CHIP_TONGA:
 116                 amdgpu_program_register_sequence(adev,
 117                                                  tonga_mgcg_cgcg_init,
 118                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 119                 amdgpu_program_register_sequence(adev,
 120                                                  golden_settings_tonga_a11,
 121                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 122                 break;
 123         case CHIP_CARRIZO:
 124                 amdgpu_program_register_sequence(adev,
 125                                                  cz_mgcg_cgcg_init,
 126                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 127                 break;
 128         default:
 129                 break;
 130         }
 131 }
 132
 133 /**
 134  * gmc8_mc_wait_for_idle - wait for MC idle callback.
 135  *
 136  * @adev: amdgpu_device pointer
 137  *
 138  * Wait for the MC (memory controller) to be idle.
 139  * (evergreen+).
 140  * Returns 0 if the MC is idle, -1 if not.
 141  */
 142 int gmc_v8_0_mc_wait_for_idle(struct amdgpu_device *adev)
 143 {
 144         unsigned i;
 145         u32 tmp;
 146
 147         for (i = 0; i < adev->usec_timeout; i++) {
 148                 /* read MC_STATUS */
 149                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__VMC_BUSY_MASK |
 150                                                SRBM_STATUS__MCB_BUSY_MASK |
 151                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
 152                                                SRBM_STATUS__MCC_BUSY_MASK |
 153                                                SRBM_STATUS__MCD_BUSY_MASK |
 154                                                SRBM_STATUS__VMC1_BUSY_MASK);
 155                 if (!tmp)
 156                         return 0;
 157                 udelay(1);
 158         }
 159         return -1;
 160 }
 161
 162 void gmc_v8_0_mc_stop(struct amdgpu_device *adev,
 163                       struct amdgpu_mode_mc_save *save)
 164 {
 165         u32 blackout;
 166
 167         if (adev->mode_info.num_crtc)
 168                 amdgpu_display_stop_mc_access(adev, save);
 169
 170         amdgpu_asic_wait_for_mc_idle(adev);
 171
 172         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 173         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
 174                 /* Block CPU access */
 175                 WREG32(mmBIF_FB_EN, 0);
 176                 /* blackout the MC */
 177                 blackout = REG_SET_FIELD(blackout,
 178                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
 179                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
 180         }
 181         /* wait for the MC to settle */
 182         udelay(100);
 183 }
 184
 185 void gmc_v8_0_mc_resume(struct amdgpu_device *adev,
 186                         struct amdgpu_mode_mc_save *save)
 187 {
 188         u32 tmp;
 189
 190         /* unblackout the MC */
 191         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 192         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 193         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 194         /* allow CPU access */
 195         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 196         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 197         WREG32(mmBIF_FB_EN, tmp);
 198
 199         if (adev->mode_info.num_crtc)
 200                 amdgpu_display_resume_mc_access(adev, save);
 201 }
 202
 203 /**
 204  * gmc_v8_0_init_microcode - load ucode images from disk
 205  *
 206  * @adev: amdgpu_device pointer
 207  *
 208  * Use the firmware interface to load the ucode images into
 209  * the driver (not loaded into hw).
 210  * Returns 0 on success, error on failure.
 211  */
 212 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
 213 {
 214         const char *chip_name;
 215         char fw_name[30];
 216         int err;
 217
 218         DRM_DEBUG("\n");
 219
 220         switch (adev->asic_type) {
 221         case CHIP_TOPAZ:
 222                 chip_name = "topaz";
 223                 break;
 224         case CHIP_TONGA:
 225                 chip_name = "tonga";
 226                 break;
 227         case CHIP_FIJI:
 228                 chip_name = "fiji";
 229                 break;
 230         case CHIP_CARRIZO:
 231                 return 0;
 232         default: BUG();
 233         }
 234
 235         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 236         err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
 237         if (err)
 238                 goto out;
 239         err = amdgpu_ucode_validate(adev->mc.fw);
 240
 241 out:
 242         if (err) {
 243                 printk(KERN_ERR
 244                        "mc: Failed to load firmware \"%s\"\n",
 245                        fw_name);
 246                 release_firmware(adev->mc.fw);
 247                 adev->mc.fw = NULL;
 248         }
 249         return err;
 250 }
 251
 252 /**
 253  * gmc_v8_0_mc_load_microcode - load MC ucode into the hw
 254  *
 255  * @adev: amdgpu_device pointer
 256  *
 257  * Load the GDDR MC ucode into the hw (CIK).
 258  * Returns 0 on success, error on failure.
 259  */
 260 static int gmc_v8_0_mc_load_microcode(struct amdgpu_device *adev)
 261 {
 262         const struct mc_firmware_header_v1_0 *hdr;
 263         const __le32 *fw_data = NULL;
 264         const __le32 *io_mc_regs = NULL;
 265         u32 running, blackout = 0;
 266         int i, ucode_size, regs_size;
 267
 268         if (!adev->mc.fw)
 269                 return -EINVAL;
 270
 271         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 272         amdgpu_ucode_print_mc_hdr(&hdr->header);
 273
 274         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 275         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 276         io_mc_regs = (const __le32 *)
 277                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 278         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 279         fw_data = (const __le32 *)
 280                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 281
 282         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 283
 284         if (running == 0) {
 285                 if (running) {
 286                         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 287                         WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
 288                 }
 289
 290                 /* reset the engine and set to writable */
 291                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 292                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 293
 294                 /* load mc io regs */
 295                 for (i = 0; i < regs_size; i++) {
 296                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 297                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 298                 }
 299                 /* load the MC ucode */
 300                 for (i = 0; i < ucode_size; i++)
 301                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 302
 303                 /* put the engine back into the active state */
 304                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 305                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 306                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 307
 308                 /* wait for training to complete */
 309                 for (i = 0; i < adev->usec_timeout; i++) {
 310                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 311                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 312                                 break;
 313                         udelay(1);
 314                 }
 315                 for (i = 0; i < adev->usec_timeout; i++) {
 316                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 317                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 318                                 break;
 319                         udelay(1);
 320                 }
 321
 322                 if (running)
 323                         WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
 324         }
 325
 326         return 0;
 327 }
 328
 329 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
 330                                        struct amdgpu_mc *mc)
 331 {
 332         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 333                 /* leave room for at least 1024M GTT */
 334                 dev_warn(adev->dev, "limiting VRAM\n");
 335                 mc->real_vram_size = 0xFFC0000000ULL;
 336                 mc->mc_vram_size = 0xFFC0000000ULL;
 337         }
 338         amdgpu_vram_location(adev, &adev->mc, 0);
 339         adev->mc.gtt_base_align = 0;
 340         amdgpu_gtt_location(adev, mc);
 341 }
 342
 343 /**
 344  * gmc_v8_0_mc_program - program the GPU memory controller
 345  *
 346  * @adev: amdgpu_device pointer
 347  *
 348  * Set the location of vram, gart, and AGP in the GPU's
 349  * physical address space (CIK).
 350  */
 351 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
 352 {
 353         struct amdgpu_mode_mc_save save;
 354         u32 tmp;
 355         int i, j;
 356
 357         /* Initialize HDP */
 358         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 359                 WREG32((0xb05 + j), 0x00000000);
 360                 WREG32((0xb06 + j), 0x00000000);
 361                 WREG32((0xb07 + j), 0x00000000);
 362                 WREG32((0xb08 + j), 0x00000000);
 363                 WREG32((0xb09 + j), 0x00000000);
 364         }
 365         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 366
 367         if (adev->mode_info.num_crtc)
 368                 amdgpu_display_set_vga_render_state(adev, false);
 369
 370         gmc_v8_0_mc_stop(adev, &save);
 371         if (amdgpu_asic_wait_for_mc_idle(adev)) {
 372                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 373         }
 374         /* Update configuration */
 375         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 376                adev->mc.vram_start >> 12);
 377         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 378                adev->mc.vram_end >> 12);
 379         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 380                adev->vram_scratch.gpu_addr >> 12);
 381         tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
 382         tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
 383         WREG32(mmMC_VM_FB_LOCATION, tmp);
 384         /* XXX double check these! */
 385         WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
 386         WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 387         WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 388         WREG32(mmMC_VM_AGP_BASE, 0);
 389         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 390         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 391         if (amdgpu_asic_wait_for_mc_idle(adev)) {
 392                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 393         }
 394         gmc_v8_0_mc_resume(adev, &save);
 395
 396         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 397
 398         tmp = RREG32(mmHDP_MISC_CNTL);
 399         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
 400         WREG32(mmHDP_MISC_CNTL, tmp);
 401
 402         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 403         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 404 }
 405
 406 /**
 407  * gmc_v8_0_mc_init - initialize the memory controller driver params
 408  *
 409  * @adev: amdgpu_device pointer
 410  *
 411  * Look up the amount of vram, vram width, and decide how to place
 412  * vram and gart within the GPU's physical address space (CIK).
 413  * Returns 0 for success.
 414  */
 415 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
 416 {
 417         u32 tmp;
 418         int chansize, numchan;
 419
 420         /* Get VRAM informations */
 421         tmp = RREG32(mmMC_ARB_RAMCFG);
 422         if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 423                 chansize = 64;
 424         } else {
 425                 chansize = 32;
 426         }
 427         tmp = RREG32(mmMC_SHARED_CHMAP);
 428         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 429         case 0:
 430         default:
 431                 numchan = 1;
 432                 break;
 433         case 1:
 434                 numchan = 2;
 435                 break;
 436         case 2:
 437                 numchan = 4;
 438                 break;
 439         case 3:
 440                 numchan = 8;
 441                 break;
 442         case 4:
 443                 numchan = 3;
 444                 break;
 445         case 5:
 446                 numchan = 6;
 447                 break;
 448         case 6:
 449                 numchan = 10;
 450                 break;
 451         case 7:
 452                 numchan = 12;
 453                 break;
 454         case 8:
 455                 numchan = 16;
 456                 break;
 457         }
 458         adev->mc.vram_width = numchan * chansize;
 459         /* Could aper size report 0 ? */
 460         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 461         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 462         /* size in MB on si */
 463         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 464         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 465         adev->mc.visible_vram_size = adev->mc.aper_size;
 466
 467         /* unless the user had overridden it, set the gart
 468          * size equal to the 1024 or vram, whichever is larger.
 469          */
 470         if (amdgpu_gart_size == -1)
 471                 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
 472         else
 473                 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
 474
 475         gmc_v8_0_vram_gtt_location(adev, &adev->mc);
 476
 477         return 0;
 478 }
 479
 480 /*
 481  * GART
 482  * VMID 0 is the physical GPU addresses as used by the kernel.
 483  * VMIDs 1-15 are used for userspace clients and are handled
 484  * by the amdgpu vm/hsa code.
 485  */
 486
 487 /**
 488  * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback
 489  *
 490  * @adev: amdgpu_device pointer
 491  * @vmid: vm instance to flush
 492  *
 493  * Flush the TLB for the requested page table (CIK).
 494  */
 495 static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 496                                         uint32_t vmid)
 497 {
 498         /* flush hdp cache */
 499         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 500
 501         /* bits 0-15 are the VM contexts0-15 */
 502         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 503 }
 504
 505 /**
 506  * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO
 507  *
 508  * @adev: amdgpu_device pointer
 509  * @cpu_pt_addr: cpu address of the page table
 510  * @gpu_page_idx: entry in the page table to update
 511  * @addr: dst addr to write into pte/pde
 512  * @flags: access flags
 513  *
 514  * Update the page tables using the CPU.
 515  */
 516 static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev,
 517                                      void *cpu_pt_addr,
 518                                      uint32_t gpu_page_idx,
 519                                      uint64_t addr,
 520                                      uint32_t flags)
 521 {
 522         void __iomem *ptr = (void *)cpu_pt_addr;
 523         uint64_t value;
 524
 525         /*
 526          * PTE format on VI:
 527          * 63:40 reserved
 528          * 39:12 4k physical page base address
 529          * 11:7 fragment
 530          * 6 write
 531          * 5 read
 532          * 4 exe
 533          * 3 reserved
 534          * 2 snooped
 535          * 1 system
 536          * 0 valid
 537          *
 538          * PDE format on VI:
 539          * 63:59 block fragment size
 540          * 58:40 reserved
 541          * 39:1 physical base address of PTE
 542          * bits 5:1 must be 0.
 543          * 0 valid
 544          */
 545         value = addr & 0x000000FFFFFFF000ULL;
 546         value |= flags;
 547         writeq(value, ptr + (gpu_page_idx * 8));
 548
 549         return 0;
 550 }
 551
 552 /**
 553  * gmc_v8_0_gart_enable - gart enable
 554  *
 555  * @adev: amdgpu_device pointer
 556  *
 557  * This sets up the TLBs, programs the page tables for VMID0,
 558  * sets up the hw for VMIDs 1-15 which are allocated on
 559  * demand, and sets up the global locations for the LDS, GDS,
 560  * and GPUVM for FSA64 clients (CIK).
 561  * Returns 0 for success, errors for failure.
 562  */
 563 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 564 {
 565         int r, i;
 566         u32 tmp;
 567
 568         if (adev->gart.robj == NULL) {
 569                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 570                 return -EINVAL;
 571         }
 572         r = amdgpu_gart_table_vram_pin(adev);
 573         if (r)
 574                 return r;
 575         /* Setup TLB control */
 576         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 577         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 578         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 579         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 580         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 581         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 582         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 583         /* Setup L2 cache */
 584         tmp = RREG32(mmVM_L2_CNTL);
 585         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 586         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 587         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 588         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 589         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 590         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 591         WREG32(mmVM_L2_CNTL, tmp);
 592         tmp = RREG32(mmVM_L2_CNTL2);
 593         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 594         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 595         WREG32(mmVM_L2_CNTL2, tmp);
 596         tmp = RREG32(mmVM_L2_CNTL3);
 597         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 598         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
 599         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
 600         WREG32(mmVM_L2_CNTL3, tmp);
 601         /* XXX: set to enable PTE/PDE in system memory */
 602         tmp = RREG32(mmVM_L2_CNTL4);
 603         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
 604         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
 605         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
 606         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
 607         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
 608         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
 609         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
 610         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
 611         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
 612         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
 613         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
 614         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
 615         WREG32(mmVM_L2_CNTL4, tmp);
 616         /* setup context0 */
 617         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
 618         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, (adev->mc.gtt_end >> 12) - 1);
 619         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 620         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 621                         (u32)(adev->dummy_page.addr >> 12));
 622         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 623         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 624         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 625         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 626         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 627         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 628
 629         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
 630         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
 631         WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
 632
 633         /* empty context1-15 */
 634         /* FIXME start with 4G, once using 2 level pt switch to full
 635          * vm size space
 636          */
 637         /* set vm size, must be a multiple of 4 */
 638         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 639         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 640         for (i = 1; i < 16; i++) {
 641                 if (i < 8)
 642                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 643                                adev->gart.table_addr >> 12);
 644                 else
 645                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 646                                adev->gart.table_addr >> 12);
 647         }
 648
 649         /* enable context1-15 */
 650         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 651                (u32)(adev->dummy_page.addr >> 12));
 652         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 653         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 654         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 655         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 656         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 657         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 658         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 659         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 660         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 661         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 662         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 663         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 664                             amdgpu_vm_block_size - 9);
 665         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 666
 667         gmc_v8_0_gart_flush_gpu_tlb(adev, 0);
 668         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 669                  (unsigned)(adev->mc.gtt_size >> 20),
 670                  (unsigned long long)adev->gart.table_addr);
 671         adev->gart.ready = true;
 672         return 0;
 673 }
 674
 675 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
 676 {
 677         int r;
 678
 679         if (adev->gart.robj) {
 680                 WARN(1, "R600 PCIE GART already initialized\n");
 681                 return 0;
 682         }
 683         /* Initialize common gart structure */
 684         r = amdgpu_gart_init(adev);
 685         if (r)
 686                 return r;
 687         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 688         return amdgpu_gart_table_vram_alloc(adev);
 689 }
 690
 691 /**
 692  * gmc_v8_0_gart_disable - gart disable
 693  *
 694  * @adev: amdgpu_device pointer
 695  *
 696  * This disables all VM page table (CIK).
 697  */
 698 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
 699 {
 700         u32 tmp;
 701
 702         /* Disable all tables */
 703         WREG32(mmVM_CONTEXT0_CNTL, 0);
 704         WREG32(mmVM_CONTEXT1_CNTL, 0);
 705         /* Setup TLB control */
 706         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 707         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 708         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 709         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 710         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 711         /* Setup L2 cache */
 712         tmp = RREG32(mmVM_L2_CNTL);
 713         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 714         WREG32(mmVM_L2_CNTL, tmp);
 715         WREG32(mmVM_L2_CNTL2, 0);
 716         amdgpu_gart_table_vram_unpin(adev);
 717 }
 718
 719 /**
 720  * gmc_v8_0_gart_fini - vm fini callback
 721  *
 722  * @adev: amdgpu_device pointer
 723  *
 724  * Tears down the driver GART/VM setup (CIK).
 725  */
 726 static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
 727 {
 728         amdgpu_gart_table_vram_free(adev);
 729         amdgpu_gart_fini(adev);
 730 }
 731
 732 /*
 733  * vm
 734  * VMID 0 is the physical GPU addresses as used by the kernel.
 735  * VMIDs 1-15 are used for userspace clients and are handled
 736  * by the amdgpu vm/hsa code.
 737  */
 738 /**
 739  * gmc_v8_0_vm_init - cik vm init callback
 740  *
 741  * @adev: amdgpu_device pointer
 742  *
 743  * Inits cik specific vm parameters (number of VMs, base of vram for
 744  * VMIDs 1-15) (CIK).
 745  * Returns 0 for success.
 746  */
 747 static int gmc_v8_0_vm_init(struct amdgpu_device *adev)
 748 {
 749         /*
 750          * number of VMs
 751          * VMID 0 is reserved for System
 752          * amdgpu graphics/compute will use VMIDs 1-7
 753          * amdkfd will use VMIDs 8-15
 754          */
 755         adev->vm_manager.nvm = AMDGPU_NUM_OF_VMIDS;
 756
 757         /* base offset of vram pages */
 758         if (adev->flags & AMD_IS_APU) {
 759                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
 760                 tmp <<= 22;
 761                 adev->vm_manager.vram_base_offset = tmp;
 762         } else
 763                 adev->vm_manager.vram_base_offset = 0;
 764
 765         return 0;
 766 }
 767
 768 /**
 769  * gmc_v8_0_vm_fini - cik vm fini callback
 770  *
 771  * @adev: amdgpu_device pointer
 772  *
 773  * Tear down any asic specific VM setup (CIK).
 774  */
 775 static void gmc_v8_0_vm_fini(struct amdgpu_device *adev)
 776 {
 777 }
 778
 779 /**
 780  * gmc_v8_0_vm_decode_fault - print human readable fault info
 781  *
 782  * @adev: amdgpu_device pointer
 783  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 784  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 785  *
 786  * Print human readable fault information (CIK).
 787  */
 788 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
 789                                      u32 status, u32 addr, u32 mc_client)
 790 {
 791         u32 mc_id;
 792         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 793         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 794                                         PROTECTIONS);
 795         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 796                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 797
 798         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 799                               MEMORY_CLIENT_ID);
 800
 801         printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 802                protections, vmid, addr,
 803                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 804                              MEMORY_CLIENT_RW) ?
 805                "write" : "read", block, mc_client, mc_id);
 806 }
 807
 808 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
 809 {
 810         switch (mc_seq_vram_type) {
 811         case MC_SEQ_MISC0__MT__GDDR1:
 812                 return AMDGPU_VRAM_TYPE_GDDR1;
 813         case MC_SEQ_MISC0__MT__DDR2:
 814                 return AMDGPU_VRAM_TYPE_DDR2;
 815         case MC_SEQ_MISC0__MT__GDDR3:
 816                 return AMDGPU_VRAM_TYPE_GDDR3;
 817         case MC_SEQ_MISC0__MT__GDDR4:
 818                 return AMDGPU_VRAM_TYPE_GDDR4;
 819         case MC_SEQ_MISC0__MT__GDDR5:
 820                 return AMDGPU_VRAM_TYPE_GDDR5;
 821         case MC_SEQ_MISC0__MT__HBM:
 822                 return AMDGPU_VRAM_TYPE_HBM;
 823         case MC_SEQ_MISC0__MT__DDR3:
 824                 return AMDGPU_VRAM_TYPE_DDR3;
 825         default:
 826                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 827         }
 828 }
 829
 830 static int gmc_v8_0_early_init(void *handle)
 831 {
 832         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 833
 834         gmc_v8_0_set_gart_funcs(adev);
 835         gmc_v8_0_set_irq_funcs(adev);
 836
 837         if (adev->flags & AMD_IS_APU) {
 838                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 839         } else {
 840                 u32 tmp = RREG32(mmMC_SEQ_MISC0);
 841                 tmp &= MC_SEQ_MISC0__MT__MASK;
 842                 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
 843         }
 844
 845         return 0;
 846 }
 847
 848 static int gmc_v8_0_late_init(void *handle)
 849 {
 850         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 851
 852         return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 853 }
 854
 855 static int gmc_v8_0_sw_init(void *handle)
 856 {
 857         int r;
 858         int dma_bits;
 859         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 860
 861         r = amdgpu_gem_init(adev);
 862         if (r)
 863                 return r;
 864
 865         r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
 866         if (r)
 867                 return r;
 868
 869         r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
 870         if (r)
 871                 return r;
 872
 873         /* Adjust VM size here.
 874          * Currently set to 4GB ((1 << 20) 4k pages).
 875          * Max GPUVM size for cayman and SI is 40 bits.
 876          */
 877         adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
 878
 879         /* Set the internal MC address mask
 880          * This is the max address of the GPU's
 881          * internal address space.
 882          */
 883         adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
 884
 885         /* set DMA mask + need_dma32 flags.
 886          * PCIE - can handle 40-bits.
 887          * IGP - can handle 40-bits
 888          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
 889          */
 890         adev->need_dma32 = false;
 891         dma_bits = adev->need_dma32 ? 32 : 40;
 892         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 893         if (r) {
 894                 adev->need_dma32 = true;
 895                 dma_bits = 32;
 896                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
 897         }
 898         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 899         if (r) {
 900                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
 901                 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
 902         }
 903
 904         r = gmc_v8_0_init_microcode(adev);
 905         if (r) {
 906                 DRM_ERROR("Failed to load mc firmware!\n");
 907                 return r;
 908         }
 909
 910         r = gmc_v8_0_mc_init(adev);
 911         if (r)
 912                 return r;
 913
 914         /* Memory manager */
 915         r = amdgpu_bo_init(adev);
 916         if (r)
 917                 return r;
 918
 919         r = gmc_v8_0_gart_init(adev);
 920         if (r)
 921                 return r;
 922
 923         if (!adev->vm_manager.enabled) {
 924                 r = gmc_v8_0_vm_init(adev);
 925                 if (r) {
 926                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
 927                         return r;
 928                 }
 929                 adev->vm_manager.enabled = true;
 930         }
 931
 932         return r;
 933 }
 934
 935 static int gmc_v8_0_sw_fini(void *handle)
 936 {
 937         int i;
 938         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 939
 940         if (adev->vm_manager.enabled) {
 941                 for (i = 0; i < AMDGPU_NUM_VM; ++i)
 942                         amdgpu_fence_unref(&adev->vm_manager.active[i]);
 943                 gmc_v8_0_vm_fini(adev);
 944                 adev->vm_manager.enabled = false;
 945         }
 946         gmc_v8_0_gart_fini(adev);
 947         amdgpu_gem_fini(adev);
 948         amdgpu_bo_fini(adev);
 949
 950         return 0;
 951 }
 952
 953 static int gmc_v8_0_hw_init(void *handle)
 954 {
 955         int r;
 956         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 957
 958         gmc_v8_0_init_golden_registers(adev);
 959
 960         gmc_v8_0_mc_program(adev);
 961
 962         if (!(adev->flags & AMD_IS_APU)) {
 963                 r = gmc_v8_0_mc_load_microcode(adev);
 964                 if (r) {
 965                         DRM_ERROR("Failed to load MC firmware!\n");
 966                         return r;
 967                 }
 968         }
 969
 970         r = gmc_v8_0_gart_enable(adev);
 971         if (r)
 972                 return r;
 973
 974         return r;
 975 }
 976
 977 static int gmc_v8_0_hw_fini(void *handle)
 978 {
 979         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 980
 981         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
 982         gmc_v8_0_gart_disable(adev);
 983
 984         return 0;
 985 }
 986
 987 static int gmc_v8_0_suspend(void *handle)
 988 {
 989         int i;
 990         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 991
 992         if (adev->vm_manager.enabled) {
 993                 for (i = 0; i < AMDGPU_NUM_VM; ++i)
 994                         amdgpu_fence_unref(&adev->vm_manager.active[i]);
 995                 gmc_v8_0_vm_fini(adev);
 996                 adev->vm_manager.enabled = false;
 997         }
 998         gmc_v8_0_hw_fini(adev);
 999
1000         return 0;
1001 }
1002
1003 static int gmc_v8_0_resume(void *handle)
1004 {
1005         int r;
1006         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1007
1008         r = gmc_v8_0_hw_init(adev);
1009         if (r)
1010                 return r;
1011
1012         if (!adev->vm_manager.enabled) {
1013                 r = gmc_v8_0_vm_init(adev);
1014                 if (r) {
1015                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1016                         return r;
1017                 }
1018                 adev->vm_manager.enabled = true;
1019         }
1020
1021         return r;
1022 }
1023
1024 static bool gmc_v8_0_is_idle(void *handle)
1025 {
1026         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1027         u32 tmp = RREG32(mmSRBM_STATUS);
1028
1029         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1030                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1031                 return false;
1032
1033         return true;
1034 }
1035
1036 static int gmc_v8_0_wait_for_idle(void *handle)
1037 {
1038         unsigned i;
1039         u32 tmp;
1040         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1041
1042         for (i = 0; i < adev->usec_timeout; i++) {
1043                 /* read MC_STATUS */
1044                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1045                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1046                                                SRBM_STATUS__MCC_BUSY_MASK |
1047                                                SRBM_STATUS__MCD_BUSY_MASK |
1048                                                SRBM_STATUS__VMC_BUSY_MASK |
1049                                                SRBM_STATUS__VMC1_BUSY_MASK);
1050                 if (!tmp)
1051                         return 0;
1052                 udelay(1);
1053         }
1054         return -ETIMEDOUT;
1055
1056 }
1057
1058 static void gmc_v8_0_print_status(void *handle)
1059 {
1060         int i, j;
1061         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1062
1063         dev_info(adev->dev, "GMC 8.x registers\n");
1064         dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",
1065                 RREG32(mmSRBM_STATUS));
1066         dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
1067                 RREG32(mmSRBM_STATUS2));
1068
1069         dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1070                  RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
1071         dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1072                  RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
1073         dev_info(adev->dev, "  MC_VM_MX_L1_TLB_CNTL=0x%08X\n",
1074                  RREG32(mmMC_VM_MX_L1_TLB_CNTL));
1075         dev_info(adev->dev, "  VM_L2_CNTL=0x%08X\n",
1076                  RREG32(mmVM_L2_CNTL));
1077         dev_info(adev->dev, "  VM_L2_CNTL2=0x%08X\n",
1078                  RREG32(mmVM_L2_CNTL2));
1079         dev_info(adev->dev, "  VM_L2_CNTL3=0x%08X\n",
1080                  RREG32(mmVM_L2_CNTL3));
1081         dev_info(adev->dev, "  VM_L2_CNTL4=0x%08X\n",
1082                  RREG32(mmVM_L2_CNTL4));
1083         dev_info(adev->dev, "  VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n",
1084                  RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR));
1085         dev_info(adev->dev, "  VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n",
1086                  RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR));
1087         dev_info(adev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1088                  RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR));
1089         dev_info(adev->dev, "  VM_CONTEXT0_CNTL2=0x%08X\n",
1090                  RREG32(mmVM_CONTEXT0_CNTL2));
1091         dev_info(adev->dev, "  VM_CONTEXT0_CNTL=0x%08X\n",
1092                  RREG32(mmVM_CONTEXT0_CNTL));
1093         dev_info(adev->dev, "  VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR=0x%08X\n",
1094                  RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR));
1095         dev_info(adev->dev, "  VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR=0x%08X\n",
1096                  RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR));
1097         dev_info(adev->dev, "  mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET=0x%08X\n",
1098                  RREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET));
1099         dev_info(adev->dev, "  VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n",
1100                  RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR));
1101         dev_info(adev->dev, "  VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n",
1102                  RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR));
1103         dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1104                  RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR));
1105         dev_info(adev->dev, "  VM_CONTEXT1_CNTL2=0x%08X\n",
1106                  RREG32(mmVM_CONTEXT1_CNTL2));
1107         dev_info(adev->dev, "  VM_CONTEXT1_CNTL=0x%08X\n",
1108                  RREG32(mmVM_CONTEXT1_CNTL));
1109         for (i = 0; i < 16; i++) {
1110                 if (i < 8)
1111                         dev_info(adev->dev, "  VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1112                                  i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i));
1113                 else
1114                         dev_info(adev->dev, "  VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1115                                  i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8));
1116         }
1117         dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n",
1118                  RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR));
1119         dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n",
1120                  RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR));
1121         dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n",
1122                  RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR));
1123         dev_info(adev->dev, "  MC_VM_FB_LOCATION=0x%08X\n",
1124                  RREG32(mmMC_VM_FB_LOCATION));
1125         dev_info(adev->dev, "  MC_VM_AGP_BASE=0x%08X\n",
1126                  RREG32(mmMC_VM_AGP_BASE));
1127         dev_info(adev->dev, "  MC_VM_AGP_TOP=0x%08X\n",
1128                  RREG32(mmMC_VM_AGP_TOP));
1129         dev_info(adev->dev, "  MC_VM_AGP_BOT=0x%08X\n",
1130                  RREG32(mmMC_VM_AGP_BOT));
1131
1132         dev_info(adev->dev, "  HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n",
1133                  RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL));
1134         dev_info(adev->dev, "  HDP_NONSURFACE_BASE=0x%08X\n",
1135                  RREG32(mmHDP_NONSURFACE_BASE));
1136         dev_info(adev->dev, "  HDP_NONSURFACE_INFO=0x%08X\n",
1137                  RREG32(mmHDP_NONSURFACE_INFO));
1138         dev_info(adev->dev, "  HDP_NONSURFACE_SIZE=0x%08X\n",
1139                  RREG32(mmHDP_NONSURFACE_SIZE));
1140         dev_info(adev->dev, "  HDP_MISC_CNTL=0x%08X\n",
1141                  RREG32(mmHDP_MISC_CNTL));
1142         dev_info(adev->dev, "  HDP_HOST_PATH_CNTL=0x%08X\n",
1143                  RREG32(mmHDP_HOST_PATH_CNTL));
1144
1145         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
1146                 dev_info(adev->dev, "  %d:\n", i);
1147                 dev_info(adev->dev, "  0x%04X=0x%08X\n",
1148                          0xb05 + j, RREG32(0xb05 + j));
1149                 dev_info(adev->dev, "  0x%04X=0x%08X\n",
1150                          0xb06 + j, RREG32(0xb06 + j));
1151                 dev_info(adev->dev, "  0x%04X=0x%08X\n",
1152                          0xb07 + j, RREG32(0xb07 + j));
1153                 dev_info(adev->dev, "  0x%04X=0x%08X\n",
1154                          0xb08 + j, RREG32(0xb08 + j));
1155                 dev_info(adev->dev, "  0x%04X=0x%08X\n",
1156                          0xb09 + j, RREG32(0xb09 + j));
1157         }
1158
1159         dev_info(adev->dev, "  BIF_FB_EN=0x%08X\n",
1160                  RREG32(mmBIF_FB_EN));
1161 }
1162
1163 static int gmc_v8_0_soft_reset(void *handle)
1164 {
1165         struct amdgpu_mode_mc_save save;
1166         u32 srbm_soft_reset = 0;
1167         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1168         u32 tmp = RREG32(mmSRBM_STATUS);
1169
1170         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1171                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1172                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1173
1174         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1175                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1176                 if (!(adev->flags & AMD_IS_APU))
1177                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1178                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1179         }
1180
1181         if (srbm_soft_reset) {
1182                 gmc_v8_0_print_status((void *)adev);
1183
1184                 gmc_v8_0_mc_stop(adev, &save);
1185                 if (gmc_v8_0_wait_for_idle(adev)) {
1186                         dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1187                 }
1188
1189
1190                 tmp = RREG32(mmSRBM_SOFT_RESET);
1191                 tmp |= srbm_soft_reset;
1192                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1193                 WREG32(mmSRBM_SOFT_RESET, tmp);
1194                 tmp = RREG32(mmSRBM_SOFT_RESET);
1195
1196                 udelay(50);
1197
1198                 tmp &= ~srbm_soft_reset;
1199                 WREG32(mmSRBM_SOFT_RESET, tmp);
1200                 tmp = RREG32(mmSRBM_SOFT_RESET);
1201
1202                 /* Wait a little for things to settle down */
1203                 udelay(50);
1204
1205                 gmc_v8_0_mc_resume(adev, &save);
1206                 udelay(50);
1207
1208                 gmc_v8_0_print_status((void *)adev);
1209         }
1210
1211         return 0;
1212 }
1213
1214 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1215                                              struct amdgpu_irq_src *src,
1216                                              unsigned type,
1217                                              enum amdgpu_interrupt_state state)
1218 {
1219         u32 tmp;
1220         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1221                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1222                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1223                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1224                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1225                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1226                     VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1227
1228         switch (state) {
1229         case AMDGPU_IRQ_STATE_DISABLE:
1230                 /* system context */
1231                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1232                 tmp &= ~bits;
1233                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1234                 /* VMs */
1235                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1236                 tmp &= ~bits;
1237                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1238                 break;
1239         case AMDGPU_IRQ_STATE_ENABLE:
1240                 /* system context */
1241                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1242                 tmp |= bits;
1243                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1244                 /* VMs */
1245                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1246                 tmp |= bits;
1247                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1248                 break;
1249         default:
1250                 break;
1251         }
1252
1253         return 0;
1254 }
1255
1256 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1257                                       struct amdgpu_irq_src *source,
1258                                       struct amdgpu_iv_entry *entry)
1259 {
1260         u32 addr, status, mc_client;
1261
1262         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1263         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1264         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1265         /* reset addr and status */
1266         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1267
1268         if (!addr && !status)
1269                 return 0;
1270
1271         dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1272                 entry->src_id, entry->src_data);
1273         dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1274                 addr);
1275         dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1276                 status);
1277         gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
1278
1279         return 0;
1280 }
1281
1282 static int gmc_v8_0_set_clockgating_state(void *handle,
1283                                           enum amd_clockgating_state state)
1284 {
1285         return 0;
1286 }
1287
1288 static int gmc_v8_0_set_powergating_state(void *handle,
1289                                           enum amd_powergating_state state)
1290 {
1291         return 0;
1292 }
1293
1294 const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1295         .early_init = gmc_v8_0_early_init,
1296         .late_init = gmc_v8_0_late_init,
1297         .sw_init = gmc_v8_0_sw_init,
1298         .sw_fini = gmc_v8_0_sw_fini,
1299         .hw_init = gmc_v8_0_hw_init,
1300         .hw_fini = gmc_v8_0_hw_fini,
1301         .suspend = gmc_v8_0_suspend,
1302         .resume = gmc_v8_0_resume,
1303         .is_idle = gmc_v8_0_is_idle,
1304         .wait_for_idle = gmc_v8_0_wait_for_idle,
1305         .soft_reset = gmc_v8_0_soft_reset,
1306         .print_status = gmc_v8_0_print_status,
1307         .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1308         .set_powergating_state = gmc_v8_0_set_powergating_state,
1309 };
1310
1311 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
1312         .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb,
1313         .set_pte_pde = gmc_v8_0_gart_set_pte_pde,
1314 };
1315
1316 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1317         .set = gmc_v8_0_vm_fault_interrupt_state,
1318         .process = gmc_v8_0_process_interrupt,
1319 };
1320
1321 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev)
1322 {
1323         if (adev->gart.gart_funcs == NULL)
1324                 adev->gart.gart_funcs = &gmc_v8_0_gart_funcs;
1325 }
1326
1327 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1328 {
1329         adev->mc.vm_fault.num_types = 1;
1330         adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1331 }