drivers/gpu/drm/exynos/exynos_drm_fimc.c

   1 /*
   2  * Copyright (C) 2012 Samsung Electronics Co.Ltd
   3  * Authors:
   4  *      Eunchul Kim <chulspro.kim@samsung.com>
   5  *      Jinyoung Jeon <jy0.jeon@samsung.com>
   6  *      Sangmin Lee <lsmin.lee@samsung.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14 #include <linux/kernel.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/regmap.h>
  18 #include <linux/clk.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/of.h>
  21 #include <linux/spinlock.h>
  22
  23 #include <drm/drmP.h>
  24 #include <drm/exynos_drm.h>
  25 #include "regs-fimc.h"
  26 #include "exynos_drm_drv.h"
  27 #include "exynos_drm_ipp.h"
  28 #include "exynos_drm_fimc.h"
  29
  30 /*
  31  * FIMC stands for Fully Interactive Mobile Camera and
  32  * supports image scaler/rotator and input/output DMA operations.
  33  * input DMA reads image data from the memory.
  34  * output DMA writes image data to memory.
  35  * FIMC supports image rotation and image effect functions.
  36  *
  37  * M2M operation : supports crop/scale/rotation/csc so on.
  38  * Memory ----> FIMC H/W ----> Memory.
  39  * Writeback operation : supports cloned screen with FIMD.
  40  * FIMD ----> FIMC H/W ----> Memory.
  41  * Output operation : supports direct display using local path.
  42  * Memory ----> FIMC H/W ----> FIMD.
  43  */
  44
  45 /*
  46  * TODO
  47  * 1. check suspend/resume api if needed.
  48  * 2. need to check use case platform_device_id.
  49  * 3. check src/dst size with, height.
  50  * 4. added check_prepare api for right register.
  51  * 5. need to add supported list in prop_list.
  52  * 6. check prescaler/scaler optimization.
  53  */
  54
  55 #define FIMC_MAX_DEVS   4
  56 #define FIMC_MAX_SRC    2
  57 #define FIMC_MAX_DST    32
  58 #define FIMC_SHFACTOR   10
  59 #define FIMC_BUF_STOP   1
  60 #define FIMC_BUF_START  2
  61 #define FIMC_WIDTH_ITU_709      1280
  62 #define FIMC_REFRESH_MAX        60
  63 #define FIMC_REFRESH_MIN        12
  64 #define FIMC_CROP_MAX   8192
  65 #define FIMC_CROP_MIN   32
  66 #define FIMC_SCALE_MAX  4224
  67 #define FIMC_SCALE_MIN  32
  68
  69 #define get_fimc_context(dev)   platform_get_drvdata(to_platform_device(dev))
  70 #define get_ctx_from_ippdrv(ippdrv)     container_of(ippdrv,\
  71                                         struct fimc_context, ippdrv);
  72 enum fimc_wb {
  73         FIMC_WB_NONE,
  74         FIMC_WB_A,
  75         FIMC_WB_B,
  76 };
  77
  78 enum {
  79         FIMC_CLK_LCLK,
  80         FIMC_CLK_GATE,
  81         FIMC_CLK_WB_A,
  82         FIMC_CLK_WB_B,
  83         FIMC_CLK_MUX,
  84         FIMC_CLK_PARENT,
  85         FIMC_CLKS_MAX
  86 };
  87
  88 static const char * const fimc_clock_names[] = {
  89         [FIMC_CLK_LCLK]   = "sclk_fimc",
  90         [FIMC_CLK_GATE]   = "fimc",
  91         [FIMC_CLK_WB_A]   = "pxl_async0",
  92         [FIMC_CLK_WB_B]   = "pxl_async1",
  93         [FIMC_CLK_MUX]    = "mux",
  94         [FIMC_CLK_PARENT] = "parent",
  95 };
  96
  97 #define FIMC_DEFAULT_LCLK_FREQUENCY 133000000UL
  98
  99 /*
 100  * A structure of scaler.
 101  *
 102  * @range: narrow, wide.
 103  * @bypass: unused scaler path.
 104  * @up_h: horizontal scale up.
 105  * @up_v: vertical scale up.
 106  * @hratio: horizontal ratio.
 107  * @vratio: vertical ratio.
 108  */
 109 struct fimc_scaler {
 110         bool    range;
 111         bool bypass;
 112         bool up_h;
 113         bool up_v;
 114         u32 hratio;
 115         u32 vratio;
 116 };
 117
 118 /*
 119  * A structure of scaler capability.
 120  *
 121  * find user manual table 43-1.
 122  * @in_hori: scaler input horizontal size.
 123  * @bypass: scaler bypass mode.
 124  * @dst_h_wo_rot: target horizontal size without output rotation.
 125  * @dst_h_rot: target horizontal size with output rotation.
 126  * @rl_w_wo_rot: real width without input rotation.
 127  * @rl_h_rot: real height without output rotation.
 128  */
 129 struct fimc_capability {
 130         /* scaler */
 131         u32     in_hori;
 132         u32     bypass;
 133         /* output rotator */
 134         u32     dst_h_wo_rot;
 135         u32     dst_h_rot;
 136         /* input rotator */
 137         u32     rl_w_wo_rot;
 138         u32     rl_h_rot;
 139 };
 140
 141 /*
 142  * A structure of fimc context.
 143  *
 144  * @ippdrv: prepare initialization using ippdrv.
 145  * @regs_res: register resources.
 146  * @regs: memory mapped io registers.
 147  * @lock: locking of operations.
 148  * @clocks: fimc clocks.
 149  * @clk_frequency: LCLK clock frequency.
 150  * @sysreg: handle to SYSREG block regmap.
 151  * @sc: scaler infomations.
 152  * @pol: porarity of writeback.
 153  * @id: fimc id.
 154  * @irq: irq number.
 155  * @suspended: qos operations.
 156  */
 157 struct fimc_context {
 158         struct exynos_drm_ippdrv        ippdrv;
 159         struct resource *regs_res;
 160         void __iomem    *regs;
 161         spinlock_t      lock;
 162         struct clk      *clocks[FIMC_CLKS_MAX];
 163         u32             clk_frequency;
 164         struct regmap   *sysreg;
 165         struct fimc_scaler      sc;
 166         struct exynos_drm_ipp_pol       pol;
 167         int     id;
 168         int     irq;
 169         bool    suspended;
 170 };
 171
 172 static u32 fimc_read(struct fimc_context *ctx, u32 reg)
 173 {
 174         return readl(ctx->regs + reg);
 175 }
 176
 177 static void fimc_write(struct fimc_context *ctx, u32 val, u32 reg)
 178 {
 179         writel(val, ctx->regs + reg);
 180 }
 181
 182 static void fimc_set_bits(struct fimc_context *ctx, u32 reg, u32 bits)
 183 {
 184         void __iomem *r = ctx->regs + reg;
 185
 186         writel(readl(r) | bits, r);
 187 }
 188
 189 static void fimc_clear_bits(struct fimc_context *ctx, u32 reg, u32 bits)
 190 {
 191         void __iomem *r = ctx->regs + reg;
 192
 193         writel(readl(r) & ~bits, r);
 194 }
 195
 196 static void fimc_sw_reset(struct fimc_context *ctx)
 197 {
 198         u32 cfg;
 199
 200         /* stop dma operation */
 201         cfg = fimc_read(ctx, EXYNOS_CISTATUS);
 202         if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg))
 203                 fimc_clear_bits(ctx, EXYNOS_MSCTRL, EXYNOS_MSCTRL_ENVID);
 204
 205         fimc_set_bits(ctx, EXYNOS_CISRCFMT, EXYNOS_CISRCFMT_ITU601_8BIT);
 206
 207         /* disable image capture */
 208         fimc_clear_bits(ctx, EXYNOS_CIIMGCPT,
 209                 EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN);
 210
 211         /* s/w reset */
 212         fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_SWRST);
 213
 214         /* s/w reset complete */
 215         fimc_clear_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_SWRST);
 216
 217         /* reset sequence */
 218         fimc_write(ctx, 0x0, EXYNOS_CIFCNTSEQ);
 219 }
 220
 221 static int fimc_set_camblk_fimd0_wb(struct fimc_context *ctx)
 222 {
 223         return regmap_update_bits(ctx->sysreg, SYSREG_CAMERA_BLK,
 224                                   SYSREG_FIMD0WB_DEST_MASK,
 225                                   ctx->id << SYSREG_FIMD0WB_DEST_SHIFT);
 226 }
 227
 228 static void fimc_set_type_ctrl(struct fimc_context *ctx, enum fimc_wb wb)
 229 {
 230         u32 cfg;
 231
 232         DRM_DEBUG_KMS("wb[%d]\n", wb);
 233
 234         cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
 235         cfg &= ~(EXYNOS_CIGCTRL_TESTPATTERN_MASK |
 236                 EXYNOS_CIGCTRL_SELCAM_ITU_MASK |
 237                 EXYNOS_CIGCTRL_SELCAM_MIPI_MASK |
 238                 EXYNOS_CIGCTRL_SELCAM_FIMC_MASK |
 239                 EXYNOS_CIGCTRL_SELWB_CAMIF_MASK |
 240                 EXYNOS_CIGCTRL_SELWRITEBACK_MASK);
 241
 242         switch (wb) {
 243         case FIMC_WB_A:
 244                 cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_A |
 245                         EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK);
 246                 break;
 247         case FIMC_WB_B:
 248                 cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_B |
 249                         EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK);
 250                 break;
 251         case FIMC_WB_NONE:
 252         default:
 253                 cfg |= (EXYNOS_CIGCTRL_SELCAM_ITU_A |
 254                         EXYNOS_CIGCTRL_SELWRITEBACK_A |
 255                         EXYNOS_CIGCTRL_SELCAM_MIPI_A |
 256                         EXYNOS_CIGCTRL_SELCAM_FIMC_ITU);
 257                 break;
 258         }
 259
 260         fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
 261 }
 262
 263 static void fimc_set_polarity(struct fimc_context *ctx,
 264                 struct exynos_drm_ipp_pol *pol)
 265 {
 266         u32 cfg;
 267
 268         DRM_DEBUG_KMS("inv_pclk[%d]inv_vsync[%d]\n",
 269                 pol->inv_pclk, pol->inv_vsync);
 270         DRM_DEBUG_KMS("inv_href[%d]inv_hsync[%d]\n",
 271                 pol->inv_href, pol->inv_hsync);
 272
 273         cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
 274         cfg &= ~(EXYNOS_CIGCTRL_INVPOLPCLK | EXYNOS_CIGCTRL_INVPOLVSYNC |
 275                  EXYNOS_CIGCTRL_INVPOLHREF | EXYNOS_CIGCTRL_INVPOLHSYNC);
 276
 277         if (pol->inv_pclk)
 278                 cfg |= EXYNOS_CIGCTRL_INVPOLPCLK;
 279         if (pol->inv_vsync)
 280                 cfg |= EXYNOS_CIGCTRL_INVPOLVSYNC;
 281         if (pol->inv_href)
 282                 cfg |= EXYNOS_CIGCTRL_INVPOLHREF;
 283         if (pol->inv_hsync)
 284                 cfg |= EXYNOS_CIGCTRL_INVPOLHSYNC;
 285
 286         fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
 287 }
 288
 289 static void fimc_handle_jpeg(struct fimc_context *ctx, bool enable)
 290 {
 291         u32 cfg;
 292
 293         DRM_DEBUG_KMS("enable[%d]\n", enable);
 294
 295         cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
 296         if (enable)
 297                 cfg |= EXYNOS_CIGCTRL_CAM_JPEG;
 298         else
 299                 cfg &= ~EXYNOS_CIGCTRL_CAM_JPEG;
 300
 301         fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
 302 }
 303
 304 static void fimc_mask_irq(struct fimc_context *ctx, bool enable)
 305 {
 306         u32 cfg;
 307
 308         DRM_DEBUG_KMS("enable[%d]\n", enable);
 309
 310         cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
 311         if (enable) {
 312                 cfg &= ~EXYNOS_CIGCTRL_IRQ_OVFEN;
 313                 cfg |= EXYNOS_CIGCTRL_IRQ_ENABLE | EXYNOS_CIGCTRL_IRQ_LEVEL;
 314         } else
 315                 cfg &= ~EXYNOS_CIGCTRL_IRQ_ENABLE;
 316         fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
 317 }
 318
 319 static void fimc_clear_irq(struct fimc_context *ctx)
 320 {
 321         fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_CLR);
 322 }
 323
 324 static bool fimc_check_ovf(struct fimc_context *ctx)
 325 {
 326         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 327         u32 status, flag;
 328
 329         status = fimc_read(ctx, EXYNOS_CISTATUS);
 330         flag = EXYNOS_CISTATUS_OVFIY | EXYNOS_CISTATUS_OVFICB |
 331                 EXYNOS_CISTATUS_OVFICR;
 332
 333         DRM_DEBUG_KMS("flag[0x%x]\n", flag);
 334
 335         if (status & flag) {
 336                 fimc_set_bits(ctx, EXYNOS_CIWDOFST,
 337                         EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB |
 338                         EXYNOS_CIWDOFST_CLROVFICR);
 339
 340                 dev_err(ippdrv->dev, "occurred overflow at %d, status 0x%x.\n",
 341                         ctx->id, status);
 342                 return true;
 343         }
 344
 345         return false;
 346 }
 347
 348 static bool fimc_check_frame_end(struct fimc_context *ctx)
 349 {
 350         u32 cfg;
 351
 352         cfg = fimc_read(ctx, EXYNOS_CISTATUS);
 353
 354         DRM_DEBUG_KMS("cfg[0x%x]\n", cfg);
 355
 356         if (!(cfg & EXYNOS_CISTATUS_FRAMEEND))
 357                 return false;
 358
 359         cfg &= ~(EXYNOS_CISTATUS_FRAMEEND);
 360         fimc_write(ctx, cfg, EXYNOS_CISTATUS);
 361
 362         return true;
 363 }
 364
 365 static int fimc_get_buf_id(struct fimc_context *ctx)
 366 {
 367         u32 cfg;
 368         int frame_cnt, buf_id;
 369
 370         cfg = fimc_read(ctx, EXYNOS_CISTATUS2);
 371         frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg);
 372
 373         if (frame_cnt == 0)
 374                 frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg);
 375
 376         DRM_DEBUG_KMS("present[%d]before[%d]\n",
 377                 EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg),
 378                 EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg));
 379
 380         if (frame_cnt == 0) {
 381                 DRM_ERROR("failed to get frame count.\n");
 382                 return -EIO;
 383         }
 384
 385         buf_id = frame_cnt - 1;
 386         DRM_DEBUG_KMS("buf_id[%d]\n", buf_id);
 387
 388         return buf_id;
 389 }
 390
 391 static void fimc_handle_lastend(struct fimc_context *ctx, bool enable)
 392 {
 393         u32 cfg;
 394
 395         DRM_DEBUG_KMS("enable[%d]\n", enable);
 396
 397         cfg = fimc_read(ctx, EXYNOS_CIOCTRL);
 398         if (enable)
 399                 cfg |= EXYNOS_CIOCTRL_LASTENDEN;
 400         else
 401                 cfg &= ~EXYNOS_CIOCTRL_LASTENDEN;
 402
 403         fimc_write(ctx, cfg, EXYNOS_CIOCTRL);
 404 }
 405
 406
 407 static int fimc_src_set_fmt_order(struct fimc_context *ctx, u32 fmt)
 408 {
 409         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 410         u32 cfg;
 411
 412         DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
 413
 414         /* RGB */
 415         cfg = fimc_read(ctx, EXYNOS_CISCCTRL);
 416         cfg &= ~EXYNOS_CISCCTRL_INRGB_FMT_RGB_MASK;
 417
 418         switch (fmt) {
 419         case DRM_FORMAT_RGB565:
 420                 cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB565;
 421                 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
 422                 return 0;
 423         case DRM_FORMAT_RGB888:
 424         case DRM_FORMAT_XRGB8888:
 425                 cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB888;
 426                 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
 427                 return 0;
 428         default:
 429                 /* bypass */
 430                 break;
 431         }
 432
 433         /* YUV */
 434         cfg = fimc_read(ctx, EXYNOS_MSCTRL);
 435         cfg &= ~(EXYNOS_MSCTRL_ORDER2P_SHIFT_MASK |
 436                 EXYNOS_MSCTRL_C_INT_IN_2PLANE |
 437                 EXYNOS_MSCTRL_ORDER422_YCBYCR);
 438
 439         switch (fmt) {
 440         case DRM_FORMAT_YUYV:
 441                 cfg |= EXYNOS_MSCTRL_ORDER422_YCBYCR;
 442                 break;
 443         case DRM_FORMAT_YVYU:
 444                 cfg |= EXYNOS_MSCTRL_ORDER422_YCRYCB;
 445                 break;
 446         case DRM_FORMAT_UYVY:
 447                 cfg |= EXYNOS_MSCTRL_ORDER422_CBYCRY;
 448                 break;
 449         case DRM_FORMAT_VYUY:
 450         case DRM_FORMAT_YUV444:
 451                 cfg |= EXYNOS_MSCTRL_ORDER422_CRYCBY;
 452                 break;
 453         case DRM_FORMAT_NV21:
 454         case DRM_FORMAT_NV61:
 455                 cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CRCB |
 456                         EXYNOS_MSCTRL_C_INT_IN_2PLANE);
 457                 break;
 458         case DRM_FORMAT_YUV422:
 459         case DRM_FORMAT_YUV420:
 460         case DRM_FORMAT_YVU420:
 461                 cfg |= EXYNOS_MSCTRL_C_INT_IN_3PLANE;
 462                 break;
 463         case DRM_FORMAT_NV12:
 464         case DRM_FORMAT_NV16:
 465                 cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CBCR |
 466                         EXYNOS_MSCTRL_C_INT_IN_2PLANE);
 467                 break;
 468         default:
 469                 dev_err(ippdrv->dev, "inavlid source yuv order 0x%x.\n", fmt);
 470                 return -EINVAL;
 471         }
 472
 473         fimc_write(ctx, cfg, EXYNOS_MSCTRL);
 474
 475         return 0;
 476 }
 477
 478 static int fimc_src_set_fmt(struct device *dev, u32 fmt)
 479 {
 480         struct fimc_context *ctx = get_fimc_context(dev);
 481         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 482         u32 cfg;
 483
 484         DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
 485
 486         cfg = fimc_read(ctx, EXYNOS_MSCTRL);
 487         cfg &= ~EXYNOS_MSCTRL_INFORMAT_RGB;
 488
 489         switch (fmt) {
 490         case DRM_FORMAT_RGB565:
 491         case DRM_FORMAT_RGB888:
 492         case DRM_FORMAT_XRGB8888:
 493                 cfg |= EXYNOS_MSCTRL_INFORMAT_RGB;
 494                 break;
 495         case DRM_FORMAT_YUV444:
 496                 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420;
 497                 break;
 498         case DRM_FORMAT_YUYV:
 499         case DRM_FORMAT_YVYU:
 500         case DRM_FORMAT_UYVY:
 501         case DRM_FORMAT_VYUY:
 502                 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422_1PLANE;
 503                 break;
 504         case DRM_FORMAT_NV16:
 505         case DRM_FORMAT_NV61:
 506         case DRM_FORMAT_YUV422:
 507                 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422;
 508                 break;
 509         case DRM_FORMAT_YUV420:
 510         case DRM_FORMAT_YVU420:
 511         case DRM_FORMAT_NV12:
 512         case DRM_FORMAT_NV21:
 513                 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420;
 514                 break;
 515         default:
 516                 dev_err(ippdrv->dev, "inavlid source format 0x%x.\n", fmt);
 517                 return -EINVAL;
 518         }
 519
 520         fimc_write(ctx, cfg, EXYNOS_MSCTRL);
 521
 522         cfg = fimc_read(ctx, EXYNOS_CIDMAPARAM);
 523         cfg &= ~EXYNOS_CIDMAPARAM_R_MODE_MASK;
 524
 525         cfg |= EXYNOS_CIDMAPARAM_R_MODE_LINEAR;
 526
 527         fimc_write(ctx, cfg, EXYNOS_CIDMAPARAM);
 528
 529         return fimc_src_set_fmt_order(ctx, fmt);
 530 }
 531
 532 static int fimc_src_set_transf(struct device *dev,
 533                 enum drm_exynos_degree degree,
 534                 enum drm_exynos_flip flip, bool *swap)
 535 {
 536         struct fimc_context *ctx = get_fimc_context(dev);
 537         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 538         u32 cfg1, cfg2;
 539
 540         DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
 541
 542         cfg1 = fimc_read(ctx, EXYNOS_MSCTRL);
 543         cfg1 &= ~(EXYNOS_MSCTRL_FLIP_X_MIRROR |
 544                 EXYNOS_MSCTRL_FLIP_Y_MIRROR);
 545
 546         cfg2 = fimc_read(ctx, EXYNOS_CITRGFMT);
 547         cfg2 &= ~EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
 548
 549         switch (degree) {
 550         case EXYNOS_DRM_DEGREE_0:
 551                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
 552                         cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR;
 553                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
 554                         cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR;
 555                 break;
 556         case EXYNOS_DRM_DEGREE_90:
 557                 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
 558                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
 559                         cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR;
 560                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
 561                         cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR;
 562                 break;
 563         case EXYNOS_DRM_DEGREE_180:
 564                 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR |
 565                         EXYNOS_MSCTRL_FLIP_Y_MIRROR);
 566                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
 567                         cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR;
 568                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
 569                         cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR;
 570                 break;
 571         case EXYNOS_DRM_DEGREE_270:
 572                 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR |
 573                         EXYNOS_MSCTRL_FLIP_Y_MIRROR);
 574                 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
 575                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
 576                         cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR;
 577                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
 578                         cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR;
 579                 break;
 580         default:
 581                 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);
 582                 return -EINVAL;
 583         }
 584
 585         fimc_write(ctx, cfg1, EXYNOS_MSCTRL);
 586         fimc_write(ctx, cfg2, EXYNOS_CITRGFMT);
 587         *swap = (cfg2 & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) ? 1 : 0;
 588
 589         return 0;
 590 }
 591
 592 static int fimc_set_window(struct fimc_context *ctx,
 593                 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
 594 {
 595         u32 cfg, h1, h2, v1, v2;
 596
 597         /* cropped image */
 598         h1 = pos->x;
 599         h2 = sz->hsize - pos->w - pos->x;
 600         v1 = pos->y;
 601         v2 = sz->vsize - pos->h - pos->y;
 602
 603         DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]hsize[%d]vsize[%d]\n",
 604                 pos->x, pos->y, pos->w, pos->h, sz->hsize, sz->vsize);
 605         DRM_DEBUG_KMS("h1[%d]h2[%d]v1[%d]v2[%d]\n", h1, h2, v1, v2);
 606
 607         /*
 608          * set window offset 1, 2 size
 609          * check figure 43-21 in user manual
 610          */
 611         cfg = fimc_read(ctx, EXYNOS_CIWDOFST);
 612         cfg &= ~(EXYNOS_CIWDOFST_WINHOROFST_MASK |
 613                 EXYNOS_CIWDOFST_WINVEROFST_MASK);
 614         cfg |= (EXYNOS_CIWDOFST_WINHOROFST(h1) |
 615                 EXYNOS_CIWDOFST_WINVEROFST(v1));
 616         cfg |= EXYNOS_CIWDOFST_WINOFSEN;
 617         fimc_write(ctx, cfg, EXYNOS_CIWDOFST);
 618
 619         cfg = (EXYNOS_CIWDOFST2_WINHOROFST2(h2) |
 620                 EXYNOS_CIWDOFST2_WINVEROFST2(v2));
 621         fimc_write(ctx, cfg, EXYNOS_CIWDOFST2);
 622
 623         return 0;
 624 }
 625
 626 static int fimc_src_set_size(struct device *dev, int swap,
 627                 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
 628 {
 629         struct fimc_context *ctx = get_fimc_context(dev);
 630         struct drm_exynos_pos img_pos = *pos;
 631         struct drm_exynos_sz img_sz = *sz;
 632         u32 cfg;
 633
 634         DRM_DEBUG_KMS("swap[%d]hsize[%d]vsize[%d]\n",
 635                 swap, sz->hsize, sz->vsize);
 636
 637         /* original size */
 638         cfg = (EXYNOS_ORGISIZE_HORIZONTAL(img_sz.hsize) |
 639                 EXYNOS_ORGISIZE_VERTICAL(img_sz.vsize));
 640
 641         fimc_write(ctx, cfg, EXYNOS_ORGISIZE);
 642
 643         DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", pos->x, pos->y, pos->w, pos->h);
 644
 645         if (swap) {
 646                 img_pos.w = pos->h;
 647                 img_pos.h = pos->w;
 648                 img_sz.hsize = sz->vsize;
 649                 img_sz.vsize = sz->hsize;
 650         }
 651
 652         /* set input DMA image size */
 653         cfg = fimc_read(ctx, EXYNOS_CIREAL_ISIZE);
 654         cfg &= ~(EXYNOS_CIREAL_ISIZE_HEIGHT_MASK |
 655                 EXYNOS_CIREAL_ISIZE_WIDTH_MASK);
 656         cfg |= (EXYNOS_CIREAL_ISIZE_WIDTH(img_pos.w) |
 657                 EXYNOS_CIREAL_ISIZE_HEIGHT(img_pos.h));
 658         fimc_write(ctx, cfg, EXYNOS_CIREAL_ISIZE);
 659
 660         /*
 661          * set input FIFO image size
 662          * for now, we support only ITU601 8 bit mode
 663          */
 664         cfg = (EXYNOS_CISRCFMT_ITU601_8BIT |
 665                 EXYNOS_CISRCFMT_SOURCEHSIZE(img_sz.hsize) |
 666                 EXYNOS_CISRCFMT_SOURCEVSIZE(img_sz.vsize));
 667         fimc_write(ctx, cfg, EXYNOS_CISRCFMT);
 668
 669         /* offset Y(RGB), Cb, Cr */
 670         cfg = (EXYNOS_CIIYOFF_HORIZONTAL(img_pos.x) |
 671                 EXYNOS_CIIYOFF_VERTICAL(img_pos.y));
 672         fimc_write(ctx, cfg, EXYNOS_CIIYOFF);
 673         cfg = (EXYNOS_CIICBOFF_HORIZONTAL(img_pos.x) |
 674                 EXYNOS_CIICBOFF_VERTICAL(img_pos.y));
 675         fimc_write(ctx, cfg, EXYNOS_CIICBOFF);
 676         cfg = (EXYNOS_CIICROFF_HORIZONTAL(img_pos.x) |
 677                 EXYNOS_CIICROFF_VERTICAL(img_pos.y));
 678         fimc_write(ctx, cfg, EXYNOS_CIICROFF);
 679
 680         return fimc_set_window(ctx, &img_pos, &img_sz);
 681 }
 682
 683 static int fimc_src_set_addr(struct device *dev,
 684                 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
 685                 enum drm_exynos_ipp_buf_type buf_type)
 686 {
 687         struct fimc_context *ctx = get_fimc_context(dev);
 688         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 689         struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
 690         struct drm_exynos_ipp_property *property;
 691         struct drm_exynos_ipp_config *config;
 692
 693         if (!c_node) {
 694                 DRM_ERROR("failed to get c_node.\n");
 695                 return -EINVAL;
 696         }
 697
 698         property = &c_node->property;
 699
 700         DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
 701                 property->prop_id, buf_id, buf_type);
 702
 703         if (buf_id > FIMC_MAX_SRC) {
 704                 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);
 705                 return -ENOMEM;
 706         }
 707
 708         /* address register set */
 709         switch (buf_type) {
 710         case IPP_BUF_ENQUEUE:
 711                 config = &property->config[EXYNOS_DRM_OPS_SRC];
 712                 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_Y],
 713                         EXYNOS_CIIYSA0);
 714
 715                 if (config->fmt == DRM_FORMAT_YVU420) {
 716                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
 717                                 EXYNOS_CIICBSA0);
 718                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
 719                                 EXYNOS_CIICRSA0);
 720                 } else {
 721                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
 722                                 EXYNOS_CIICBSA0);
 723                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
 724                                 EXYNOS_CIICRSA0);
 725                 }
 726                 break;
 727         case IPP_BUF_DEQUEUE:
 728                 fimc_write(ctx, 0x0, EXYNOS_CIIYSA0);
 729                 fimc_write(ctx, 0x0, EXYNOS_CIICBSA0);
 730                 fimc_write(ctx, 0x0, EXYNOS_CIICRSA0);
 731                 break;
 732         default:
 733                 /* bypass */
 734                 break;
 735         }
 736
 737         return 0;
 738 }
 739
 740 static struct exynos_drm_ipp_ops fimc_src_ops = {
 741         .set_fmt = fimc_src_set_fmt,
 742         .set_transf = fimc_src_set_transf,
 743         .set_size = fimc_src_set_size,
 744         .set_addr = fimc_src_set_addr,
 745 };
 746
 747 static int fimc_dst_set_fmt_order(struct fimc_context *ctx, u32 fmt)
 748 {
 749         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 750         u32 cfg;
 751
 752         DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
 753
 754         /* RGB */
 755         cfg = fimc_read(ctx, EXYNOS_CISCCTRL);
 756         cfg &= ~EXYNOS_CISCCTRL_OUTRGB_FMT_RGB_MASK;
 757
 758         switch (fmt) {
 759         case DRM_FORMAT_RGB565:
 760                 cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB565;
 761                 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
 762                 return 0;
 763         case DRM_FORMAT_RGB888:
 764                 cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888;
 765                 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
 766                 return 0;
 767         case DRM_FORMAT_XRGB8888:
 768                 cfg |= (EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888 |
 769                         EXYNOS_CISCCTRL_EXTRGB_EXTENSION);
 770                 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
 771                 break;
 772         default:
 773                 /* bypass */
 774                 break;
 775         }
 776
 777         /* YUV */
 778         cfg = fimc_read(ctx, EXYNOS_CIOCTRL);
 779         cfg &= ~(EXYNOS_CIOCTRL_ORDER2P_MASK |
 780                 EXYNOS_CIOCTRL_ORDER422_MASK |
 781                 EXYNOS_CIOCTRL_YCBCR_PLANE_MASK);
 782
 783         switch (fmt) {
 784         case DRM_FORMAT_XRGB8888:
 785                 cfg |= EXYNOS_CIOCTRL_ALPHA_OUT;
 786                 break;
 787         case DRM_FORMAT_YUYV:
 788                 cfg |= EXYNOS_CIOCTRL_ORDER422_YCBYCR;
 789                 break;
 790         case DRM_FORMAT_YVYU:
 791                 cfg |= EXYNOS_CIOCTRL_ORDER422_YCRYCB;
 792                 break;
 793         case DRM_FORMAT_UYVY:
 794                 cfg |= EXYNOS_CIOCTRL_ORDER422_CBYCRY;
 795                 break;
 796         case DRM_FORMAT_VYUY:
 797                 cfg |= EXYNOS_CIOCTRL_ORDER422_CRYCBY;
 798                 break;
 799         case DRM_FORMAT_NV21:
 800         case DRM_FORMAT_NV61:
 801                 cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CRCB;
 802                 cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE;
 803                 break;
 804         case DRM_FORMAT_YUV422:
 805         case DRM_FORMAT_YUV420:
 806         case DRM_FORMAT_YVU420:
 807                 cfg |= EXYNOS_CIOCTRL_YCBCR_3PLANE;
 808                 break;
 809         case DRM_FORMAT_NV12:
 810         case DRM_FORMAT_NV16:
 811                 cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CBCR;
 812                 cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE;
 813                 break;
 814         default:
 815                 dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt);
 816                 return -EINVAL;
 817         }
 818
 819         fimc_write(ctx, cfg, EXYNOS_CIOCTRL);
 820
 821         return 0;
 822 }
 823
 824 static int fimc_dst_set_fmt(struct device *dev, u32 fmt)
 825 {
 826         struct fimc_context *ctx = get_fimc_context(dev);
 827         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 828         u32 cfg;
 829
 830         DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
 831
 832         cfg = fimc_read(ctx, EXYNOS_CIEXTEN);
 833
 834         if (fmt == DRM_FORMAT_AYUV) {
 835                 cfg |= EXYNOS_CIEXTEN_YUV444_OUT;
 836                 fimc_write(ctx, cfg, EXYNOS_CIEXTEN);
 837         } else {
 838                 cfg &= ~EXYNOS_CIEXTEN_YUV444_OUT;
 839                 fimc_write(ctx, cfg, EXYNOS_CIEXTEN);
 840
 841                 cfg = fimc_read(ctx, EXYNOS_CITRGFMT);
 842                 cfg &= ~EXYNOS_CITRGFMT_OUTFORMAT_MASK;
 843
 844                 switch (fmt) {
 845                 case DRM_FORMAT_RGB565:
 846                 case DRM_FORMAT_RGB888:
 847                 case DRM_FORMAT_XRGB8888:
 848                         cfg |= EXYNOS_CITRGFMT_OUTFORMAT_RGB;
 849                         break;
 850                 case DRM_FORMAT_YUYV:
 851                 case DRM_FORMAT_YVYU:
 852                 case DRM_FORMAT_UYVY:
 853                 case DRM_FORMAT_VYUY:
 854                         cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE;
 855                         break;
 856                 case DRM_FORMAT_NV16:
 857                 case DRM_FORMAT_NV61:
 858                 case DRM_FORMAT_YUV422:
 859                         cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422;
 860                         break;
 861                 case DRM_FORMAT_YUV420:
 862                 case DRM_FORMAT_YVU420:
 863                 case DRM_FORMAT_NV12:
 864                 case DRM_FORMAT_NV21:
 865                         cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR420;
 866                         break;
 867                 default:
 868                         dev_err(ippdrv->dev, "inavlid target format 0x%x.\n",
 869                                 fmt);
 870                         return -EINVAL;
 871                 }
 872
 873                 fimc_write(ctx, cfg, EXYNOS_CITRGFMT);
 874         }
 875
 876         cfg = fimc_read(ctx, EXYNOS_CIDMAPARAM);
 877         cfg &= ~EXYNOS_CIDMAPARAM_W_MODE_MASK;
 878
 879         cfg |= EXYNOS_CIDMAPARAM_W_MODE_LINEAR;
 880
 881         fimc_write(ctx, cfg, EXYNOS_CIDMAPARAM);
 882
 883         return fimc_dst_set_fmt_order(ctx, fmt);
 884 }
 885
 886 static int fimc_dst_set_transf(struct device *dev,
 887                 enum drm_exynos_degree degree,
 888                 enum drm_exynos_flip flip, bool *swap)
 889 {
 890         struct fimc_context *ctx = get_fimc_context(dev);
 891         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 892         u32 cfg;
 893
 894         DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
 895
 896         cfg = fimc_read(ctx, EXYNOS_CITRGFMT);
 897         cfg &= ~EXYNOS_CITRGFMT_FLIP_MASK;
 898         cfg &= ~EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE;
 899
 900         switch (degree) {
 901         case EXYNOS_DRM_DEGREE_0:
 902                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
 903                         cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR;
 904                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
 905                         cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
 906                 break;
 907         case EXYNOS_DRM_DEGREE_90:
 908                 cfg |= EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE;
 909                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
 910                         cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR;
 911                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
 912                         cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
 913                 break;
 914         case EXYNOS_DRM_DEGREE_180:
 915                 cfg |= (EXYNOS_CITRGFMT_FLIP_X_MIRROR |
 916                         EXYNOS_CITRGFMT_FLIP_Y_MIRROR);
 917                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
 918                         cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR;
 919                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
 920                         cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
 921                 break;
 922         case EXYNOS_DRM_DEGREE_270:
 923                 cfg |= (EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE |
 924                         EXYNOS_CITRGFMT_FLIP_X_MIRROR |
 925                         EXYNOS_CITRGFMT_FLIP_Y_MIRROR);
 926                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
 927                         cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR;
 928                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
 929                         cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
 930                 break;
 931         default:
 932                 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);
 933                 return -EINVAL;
 934         }
 935
 936         fimc_write(ctx, cfg, EXYNOS_CITRGFMT);
 937         *swap = (cfg & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) ? 1 : 0;
 938
 939         return 0;
 940 }
 941
 942 static int fimc_set_prescaler(struct fimc_context *ctx, struct fimc_scaler *sc,
 943                 struct drm_exynos_pos *src, struct drm_exynos_pos *dst)
 944 {
 945         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 946         u32 cfg, cfg_ext, shfactor;
 947         u32 pre_dst_width, pre_dst_height;
 948         u32 hfactor, vfactor;
 949         int ret = 0;
 950         u32 src_w, src_h, dst_w, dst_h;
 951
 952         cfg_ext = fimc_read(ctx, EXYNOS_CITRGFMT);
 953         if (cfg_ext & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) {
 954                 src_w = src->h;
 955                 src_h = src->w;
 956         } else {
 957                 src_w = src->w;
 958                 src_h = src->h;
 959         }
 960
 961         if (cfg_ext & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) {
 962                 dst_w = dst->h;
 963                 dst_h = dst->w;
 964         } else {
 965                 dst_w = dst->w;
 966                 dst_h = dst->h;
 967         }
 968
 969         /* fimc_ippdrv_check_property assures that dividers are not null */
 970         hfactor = fls(src_w / dst_w / 2);
 971         if (hfactor > FIMC_SHFACTOR / 2) {
 972                 dev_err(ippdrv->dev, "failed to get ratio horizontal.\n");
 973                 return -EINVAL;
 974         }
 975
 976         vfactor = fls(src_h / dst_h / 2);
 977         if (vfactor > FIMC_SHFACTOR / 2) {
 978                 dev_err(ippdrv->dev, "failed to get ratio vertical.\n");
 979                 return -EINVAL;
 980         }
 981
 982         pre_dst_width = src_w >> hfactor;
 983         pre_dst_height = src_h >> vfactor;
 984         DRM_DEBUG_KMS("pre_dst_width[%d]pre_dst_height[%d]\n",
 985                 pre_dst_width, pre_dst_height);
 986         DRM_DEBUG_KMS("hfactor[%d]vfactor[%d]\n", hfactor, vfactor);
 987
 988         sc->hratio = (src_w << 14) / (dst_w << hfactor);
 989         sc->vratio = (src_h << 14) / (dst_h << vfactor);
 990         sc->up_h = (dst_w >= src_w) ? true : false;
 991         sc->up_v = (dst_h >= src_h) ? true : false;
 992         DRM_DEBUG_KMS("hratio[%d]vratio[%d]up_h[%d]up_v[%d]\n",
 993                 sc->hratio, sc->vratio, sc->up_h, sc->up_v);
 994
 995         shfactor = FIMC_SHFACTOR - (hfactor + vfactor);
 996         DRM_DEBUG_KMS("shfactor[%d]\n", shfactor);
 997
 998         cfg = (EXYNOS_CISCPRERATIO_SHFACTOR(shfactor) |
 999                 EXYNOS_CISCPRERATIO_PREHORRATIO(1 << hfactor) |
1000                 EXYNOS_CISCPRERATIO_PREVERRATIO(1 << vfactor));
1001         fimc_write(ctx, cfg, EXYNOS_CISCPRERATIO);
1002
1003         cfg = (EXYNOS_CISCPREDST_PREDSTWIDTH(pre_dst_width) |
1004                 EXYNOS_CISCPREDST_PREDSTHEIGHT(pre_dst_height));
1005         fimc_write(ctx, cfg, EXYNOS_CISCPREDST);
1006
1007         return ret;
1008 }
1009
1010 static void fimc_set_scaler(struct fimc_context *ctx, struct fimc_scaler *sc)
1011 {
1012         u32 cfg, cfg_ext;
1013
1014         DRM_DEBUG_KMS("range[%d]bypass[%d]up_h[%d]up_v[%d]\n",
1015                 sc->range, sc->bypass, sc->up_h, sc->up_v);
1016         DRM_DEBUG_KMS("hratio[%d]vratio[%d]\n",
1017                 sc->hratio, sc->vratio);
1018
1019         cfg = fimc_read(ctx, EXYNOS_CISCCTRL);
1020         cfg &= ~(EXYNOS_CISCCTRL_SCALERBYPASS |
1021                 EXYNOS_CISCCTRL_SCALEUP_H | EXYNOS_CISCCTRL_SCALEUP_V |
1022                 EXYNOS_CISCCTRL_MAIN_V_RATIO_MASK |
1023                 EXYNOS_CISCCTRL_MAIN_H_RATIO_MASK |
1024                 EXYNOS_CISCCTRL_CSCR2Y_WIDE |
1025                 EXYNOS_CISCCTRL_CSCY2R_WIDE);
1026
1027         if (sc->range)
1028                 cfg |= (EXYNOS_CISCCTRL_CSCR2Y_WIDE |
1029                         EXYNOS_CISCCTRL_CSCY2R_WIDE);
1030         if (sc->bypass)
1031                 cfg |= EXYNOS_CISCCTRL_SCALERBYPASS;
1032         if (sc->up_h)
1033                 cfg |= EXYNOS_CISCCTRL_SCALEUP_H;
1034         if (sc->up_v)
1035                 cfg |= EXYNOS_CISCCTRL_SCALEUP_V;
1036
1037         cfg |= (EXYNOS_CISCCTRL_MAINHORRATIO((sc->hratio >> 6)) |
1038                 EXYNOS_CISCCTRL_MAINVERRATIO((sc->vratio >> 6)));
1039         fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
1040
1041         cfg_ext = fimc_read(ctx, EXYNOS_CIEXTEN);
1042         cfg_ext &= ~EXYNOS_CIEXTEN_MAINHORRATIO_EXT_MASK;
1043         cfg_ext &= ~EXYNOS_CIEXTEN_MAINVERRATIO_EXT_MASK;
1044         cfg_ext |= (EXYNOS_CIEXTEN_MAINHORRATIO_EXT(sc->hratio) |
1045                 EXYNOS_CIEXTEN_MAINVERRATIO_EXT(sc->vratio));
1046         fimc_write(ctx, cfg_ext, EXYNOS_CIEXTEN);
1047 }
1048
1049 static int fimc_dst_set_size(struct device *dev, int swap,
1050                 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
1051 {
1052         struct fimc_context *ctx = get_fimc_context(dev);
1053         struct drm_exynos_pos img_pos = *pos;
1054         struct drm_exynos_sz img_sz = *sz;
1055         u32 cfg;
1056
1057         DRM_DEBUG_KMS("swap[%d]hsize[%d]vsize[%d]\n",
1058                 swap, sz->hsize, sz->vsize);
1059
1060         /* original size */
1061         cfg = (EXYNOS_ORGOSIZE_HORIZONTAL(img_sz.hsize) |
1062                 EXYNOS_ORGOSIZE_VERTICAL(img_sz.vsize));
1063
1064         fimc_write(ctx, cfg, EXYNOS_ORGOSIZE);
1065
1066         DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", pos->x, pos->y, pos->w, pos->h);
1067
1068         /* CSC ITU */
1069         cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
1070         cfg &= ~EXYNOS_CIGCTRL_CSC_MASK;
1071
1072         if (sz->hsize >= FIMC_WIDTH_ITU_709)
1073                 cfg |= EXYNOS_CIGCTRL_CSC_ITU709;
1074         else
1075                 cfg |= EXYNOS_CIGCTRL_CSC_ITU601;
1076
1077         fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
1078
1079         if (swap) {
1080                 img_pos.w = pos->h;
1081                 img_pos.h = pos->w;
1082                 img_sz.hsize = sz->vsize;
1083                 img_sz.vsize = sz->hsize;
1084         }
1085
1086         /* target image size */
1087         cfg = fimc_read(ctx, EXYNOS_CITRGFMT);
1088         cfg &= ~(EXYNOS_CITRGFMT_TARGETH_MASK |
1089                 EXYNOS_CITRGFMT_TARGETV_MASK);
1090         cfg |= (EXYNOS_CITRGFMT_TARGETHSIZE(img_pos.w) |
1091                 EXYNOS_CITRGFMT_TARGETVSIZE(img_pos.h));
1092         fimc_write(ctx, cfg, EXYNOS_CITRGFMT);
1093
1094         /* target area */
1095         cfg = EXYNOS_CITAREA_TARGET_AREA(img_pos.w * img_pos.h);
1096         fimc_write(ctx, cfg, EXYNOS_CITAREA);
1097
1098         /* offset Y(RGB), Cb, Cr */
1099         cfg = (EXYNOS_CIOYOFF_HORIZONTAL(img_pos.x) |
1100                 EXYNOS_CIOYOFF_VERTICAL(img_pos.y));
1101         fimc_write(ctx, cfg, EXYNOS_CIOYOFF);
1102         cfg = (EXYNOS_CIOCBOFF_HORIZONTAL(img_pos.x) |
1103                 EXYNOS_CIOCBOFF_VERTICAL(img_pos.y));
1104         fimc_write(ctx, cfg, EXYNOS_CIOCBOFF);
1105         cfg = (EXYNOS_CIOCROFF_HORIZONTAL(img_pos.x) |
1106                 EXYNOS_CIOCROFF_VERTICAL(img_pos.y));
1107         fimc_write(ctx, cfg, EXYNOS_CIOCROFF);
1108
1109         return 0;
1110 }
1111
1112 static void fimc_dst_set_buf_seq(struct fimc_context *ctx, u32 buf_id,
1113                 enum drm_exynos_ipp_buf_type buf_type)
1114 {
1115         unsigned long flags;
1116         u32 buf_num;
1117         u32 cfg;
1118
1119         DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type);
1120
1121         spin_lock_irqsave(&ctx->lock, flags);
1122
1123         cfg = fimc_read(ctx, EXYNOS_CIFCNTSEQ);
1124
1125         if (buf_type == IPP_BUF_ENQUEUE)
1126                 cfg |= (1 << buf_id);
1127         else
1128                 cfg &= ~(1 << buf_id);
1129
1130         fimc_write(ctx, cfg, EXYNOS_CIFCNTSEQ);
1131
1132         buf_num = hweight32(cfg);
1133
1134         if (buf_type == IPP_BUF_ENQUEUE && buf_num >= FIMC_BUF_START)
1135                 fimc_mask_irq(ctx, true);
1136         else if (buf_type == IPP_BUF_DEQUEUE && buf_num <= FIMC_BUF_STOP)
1137                 fimc_mask_irq(ctx, false);
1138
1139         spin_unlock_irqrestore(&ctx->lock, flags);
1140 }
1141
1142 static int fimc_dst_set_addr(struct device *dev,
1143                 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
1144                 enum drm_exynos_ipp_buf_type buf_type)
1145 {
1146         struct fimc_context *ctx = get_fimc_context(dev);
1147         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1148         struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1149         struct drm_exynos_ipp_property *property;
1150         struct drm_exynos_ipp_config *config;
1151
1152         if (!c_node) {
1153                 DRM_ERROR("failed to get c_node.\n");
1154                 return -EINVAL;
1155         }
1156
1157         property = &c_node->property;
1158
1159         DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
1160                 property->prop_id, buf_id, buf_type);
1161
1162         if (buf_id > FIMC_MAX_DST) {
1163                 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);
1164                 return -ENOMEM;
1165         }
1166
1167         /* address register set */
1168         switch (buf_type) {
1169         case IPP_BUF_ENQUEUE:
1170                 config = &property->config[EXYNOS_DRM_OPS_DST];
1171
1172                 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_Y],
1173                         EXYNOS_CIOYSA(buf_id));
1174
1175                 if (config->fmt == DRM_FORMAT_YVU420) {
1176                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
1177                                 EXYNOS_CIOCBSA(buf_id));
1178                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
1179                                 EXYNOS_CIOCRSA(buf_id));
1180                 } else {
1181                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
1182                                 EXYNOS_CIOCBSA(buf_id));
1183                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
1184                                 EXYNOS_CIOCRSA(buf_id));
1185                 }
1186                 break;
1187         case IPP_BUF_DEQUEUE:
1188                 fimc_write(ctx, 0x0, EXYNOS_CIOYSA(buf_id));
1189                 fimc_write(ctx, 0x0, EXYNOS_CIOCBSA(buf_id));
1190                 fimc_write(ctx, 0x0, EXYNOS_CIOCRSA(buf_id));
1191                 break;
1192         default:
1193                 /* bypass */
1194                 break;
1195         }
1196
1197         fimc_dst_set_buf_seq(ctx, buf_id, buf_type);
1198
1199         return 0;
1200 }
1201
1202 static struct exynos_drm_ipp_ops fimc_dst_ops = {
1203         .set_fmt = fimc_dst_set_fmt,
1204         .set_transf = fimc_dst_set_transf,
1205         .set_size = fimc_dst_set_size,
1206         .set_addr = fimc_dst_set_addr,
1207 };
1208
1209 static irqreturn_t fimc_irq_handler(int irq, void *dev_id)
1210 {
1211         struct fimc_context *ctx = dev_id;
1212         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1213         struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1214         struct drm_exynos_ipp_event_work *event_work =
1215                 c_node->event_work;
1216         int buf_id;
1217
1218         DRM_DEBUG_KMS("fimc id[%d]\n", ctx->id);
1219
1220         fimc_clear_irq(ctx);
1221         if (fimc_check_ovf(ctx))
1222                 return IRQ_NONE;
1223
1224         if (!fimc_check_frame_end(ctx))
1225                 return IRQ_NONE;
1226
1227         buf_id = fimc_get_buf_id(ctx);
1228         if (buf_id < 0)
1229                 return IRQ_HANDLED;
1230
1231         DRM_DEBUG_KMS("buf_id[%d]\n", buf_id);
1232
1233         fimc_dst_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE);
1234
1235         event_work->ippdrv = ippdrv;
1236         event_work->buf_id[EXYNOS_DRM_OPS_DST] = buf_id;
1237         queue_work(ippdrv->event_workq, &event_work->work);
1238
1239         return IRQ_HANDLED;
1240 }
1241
1242 static int fimc_init_prop_list(struct exynos_drm_ippdrv *ippdrv)
1243 {
1244         struct drm_exynos_ipp_prop_list *prop_list = &ippdrv->prop_list;
1245
1246         prop_list->version = 1;
1247         prop_list->writeback = 1;
1248         prop_list->refresh_min = FIMC_REFRESH_MIN;
1249         prop_list->refresh_max = FIMC_REFRESH_MAX;
1250         prop_list->flip = (1 << EXYNOS_DRM_FLIP_NONE) |
1251                                 (1 << EXYNOS_DRM_FLIP_VERTICAL) |
1252                                 (1 << EXYNOS_DRM_FLIP_HORIZONTAL);
1253         prop_list->degree = (1 << EXYNOS_DRM_DEGREE_0) |
1254                                 (1 << EXYNOS_DRM_DEGREE_90) |
1255                                 (1 << EXYNOS_DRM_DEGREE_180) |
1256                                 (1 << EXYNOS_DRM_DEGREE_270);
1257         prop_list->csc = 1;
1258         prop_list->crop = 1;
1259         prop_list->crop_max.hsize = FIMC_CROP_MAX;
1260         prop_list->crop_max.vsize = FIMC_CROP_MAX;
1261         prop_list->crop_min.hsize = FIMC_CROP_MIN;
1262         prop_list->crop_min.vsize = FIMC_CROP_MIN;
1263         prop_list->scale = 1;
1264         prop_list->scale_max.hsize = FIMC_SCALE_MAX;
1265         prop_list->scale_max.vsize = FIMC_SCALE_MAX;
1266         prop_list->scale_min.hsize = FIMC_SCALE_MIN;
1267         prop_list->scale_min.vsize = FIMC_SCALE_MIN;
1268
1269         return 0;
1270 }
1271
1272 static inline bool fimc_check_drm_flip(enum drm_exynos_flip flip)
1273 {
1274         switch (flip) {
1275         case EXYNOS_DRM_FLIP_NONE:
1276         case EXYNOS_DRM_FLIP_VERTICAL:
1277         case EXYNOS_DRM_FLIP_HORIZONTAL:
1278         case EXYNOS_DRM_FLIP_BOTH:
1279                 return true;
1280         default:
1281                 DRM_DEBUG_KMS("invalid flip\n");
1282                 return false;
1283         }
1284 }
1285
1286 static int fimc_ippdrv_check_property(struct device *dev,
1287                 struct drm_exynos_ipp_property *property)
1288 {
1289         struct fimc_context *ctx = get_fimc_context(dev);
1290         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1291         struct drm_exynos_ipp_prop_list *pp = &ippdrv->prop_list;
1292         struct drm_exynos_ipp_config *config;
1293         struct drm_exynos_pos *pos;
1294         struct drm_exynos_sz *sz;
1295         bool swap;
1296         int i;
1297
1298         for_each_ipp_ops(i) {
1299                 if ((i == EXYNOS_DRM_OPS_SRC) &&
1300                         (property->cmd == IPP_CMD_WB))
1301                         continue;
1302
1303                 config = &property->config[i];
1304                 pos = &config->pos;
1305                 sz = &config->sz;
1306
1307                 /* check for flip */
1308                 if (!fimc_check_drm_flip(config->flip)) {
1309                         DRM_ERROR("invalid flip.\n");
1310                         goto err_property;
1311                 }
1312
1313                 /* check for degree */
1314                 switch (config->degree) {
1315                 case EXYNOS_DRM_DEGREE_90:
1316                 case EXYNOS_DRM_DEGREE_270:
1317                         swap = true;
1318                         break;
1319                 case EXYNOS_DRM_DEGREE_0:
1320                 case EXYNOS_DRM_DEGREE_180:
1321                         swap = false;
1322                         break;
1323                 default:
1324                         DRM_ERROR("invalid degree.\n");
1325                         goto err_property;
1326                 }
1327
1328                 /* check for buffer bound */
1329                 if ((pos->x + pos->w > sz->hsize) ||
1330                         (pos->y + pos->h > sz->vsize)) {
1331                         DRM_ERROR("out of buf bound.\n");
1332                         goto err_property;
1333                 }
1334
1335                 /* check for crop */
1336                 if ((i == EXYNOS_DRM_OPS_SRC) && (pp->crop)) {
1337                         if (swap) {
1338                                 if ((pos->h < pp->crop_min.hsize) ||
1339                                         (sz->vsize > pp->crop_max.hsize) ||
1340                                         (pos->w < pp->crop_min.vsize) ||
1341                                         (sz->hsize > pp->crop_max.vsize)) {
1342                                         DRM_ERROR("out of crop size.\n");
1343                                         goto err_property;
1344                                 }
1345                         } else {
1346                                 if ((pos->w < pp->crop_min.hsize) ||
1347                                         (sz->hsize > pp->crop_max.hsize) ||
1348                                         (pos->h < pp->crop_min.vsize) ||
1349                                         (sz->vsize > pp->crop_max.vsize)) {
1350                                         DRM_ERROR("out of crop size.\n");
1351                                         goto err_property;
1352                                 }
1353                         }
1354                 }
1355
1356                 /* check for scale */
1357                 if ((i == EXYNOS_DRM_OPS_DST) && (pp->scale)) {
1358                         if (swap) {
1359                                 if ((pos->h < pp->scale_min.hsize) ||
1360                                         (sz->vsize > pp->scale_max.hsize) ||
1361                                         (pos->w < pp->scale_min.vsize) ||
1362                                         (sz->hsize > pp->scale_max.vsize)) {
1363                                         DRM_ERROR("out of scale size.\n");
1364                                         goto err_property;
1365                                 }
1366                         } else {
1367                                 if ((pos->w < pp->scale_min.hsize) ||
1368                                         (sz->hsize > pp->scale_max.hsize) ||
1369                                         (pos->h < pp->scale_min.vsize) ||
1370                                         (sz->vsize > pp->scale_max.vsize)) {
1371                                         DRM_ERROR("out of scale size.\n");
1372                                         goto err_property;
1373                                 }
1374                         }
1375                 }
1376         }
1377
1378         return 0;
1379
1380 err_property:
1381         for_each_ipp_ops(i) {
1382                 if ((i == EXYNOS_DRM_OPS_SRC) &&
1383                         (property->cmd == IPP_CMD_WB))
1384                         continue;
1385
1386                 config = &property->config[i];
1387                 pos = &config->pos;
1388                 sz = &config->sz;
1389
1390                 DRM_ERROR("[%s]f[%d]r[%d]pos[%d %d %d %d]sz[%d %d]\n",
1391                         i ? "dst" : "src", config->flip, config->degree,
1392                         pos->x, pos->y, pos->w, pos->h,
1393                         sz->hsize, sz->vsize);
1394         }
1395
1396         return -EINVAL;
1397 }
1398
1399 static void fimc_clear_addr(struct fimc_context *ctx)
1400 {
1401         int i;
1402
1403         for (i = 0; i < FIMC_MAX_SRC; i++) {
1404                 fimc_write(ctx, 0, EXYNOS_CIIYSA(i));
1405                 fimc_write(ctx, 0, EXYNOS_CIICBSA(i));
1406                 fimc_write(ctx, 0, EXYNOS_CIICRSA(i));
1407         }
1408
1409         for (i = 0; i < FIMC_MAX_DST; i++) {
1410                 fimc_write(ctx, 0, EXYNOS_CIOYSA(i));
1411                 fimc_write(ctx, 0, EXYNOS_CIOCBSA(i));
1412                 fimc_write(ctx, 0, EXYNOS_CIOCRSA(i));
1413         }
1414 }
1415
1416 static int fimc_ippdrv_reset(struct device *dev)
1417 {
1418         struct fimc_context *ctx = get_fimc_context(dev);
1419
1420         /* reset h/w block */
1421         fimc_sw_reset(ctx);
1422
1423         /* reset scaler capability */
1424         memset(&ctx->sc, 0x0, sizeof(ctx->sc));
1425
1426         fimc_clear_addr(ctx);
1427
1428         return 0;
1429 }
1430
1431 static int fimc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1432 {
1433         struct fimc_context *ctx = get_fimc_context(dev);
1434         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1435         struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1436         struct drm_exynos_ipp_property *property;
1437         struct drm_exynos_ipp_config *config;
1438         struct drm_exynos_pos   img_pos[EXYNOS_DRM_OPS_MAX];
1439         struct drm_exynos_ipp_set_wb set_wb;
1440         int ret, i;
1441         u32 cfg0, cfg1;
1442
1443         DRM_DEBUG_KMS("cmd[%d]\n", cmd);
1444
1445         if (!c_node) {
1446                 DRM_ERROR("failed to get c_node.\n");
1447                 return -EINVAL;
1448         }
1449
1450         property = &c_node->property;
1451
1452         fimc_mask_irq(ctx, true);
1453
1454         for_each_ipp_ops(i) {
1455                 config = &property->config[i];
1456                 img_pos[i] = config->pos;
1457         }
1458
1459         ret = fimc_set_prescaler(ctx, &ctx->sc,
1460                 &img_pos[EXYNOS_DRM_OPS_SRC],
1461                 &img_pos[EXYNOS_DRM_OPS_DST]);
1462         if (ret) {
1463                 dev_err(dev, "failed to set precalser.\n");
1464                 return ret;
1465         }
1466
1467         /* If set ture, we can save jpeg about screen */
1468         fimc_handle_jpeg(ctx, false);
1469         fimc_set_scaler(ctx, &ctx->sc);
1470         fimc_set_polarity(ctx, &ctx->pol);
1471
1472         switch (cmd) {
1473         case IPP_CMD_M2M:
1474                 fimc_set_type_ctrl(ctx, FIMC_WB_NONE);
1475                 fimc_handle_lastend(ctx, false);
1476
1477                 /* setup dma */
1478                 cfg0 = fimc_read(ctx, EXYNOS_MSCTRL);
1479                 cfg0 &= ~EXYNOS_MSCTRL_INPUT_MASK;
1480                 cfg0 |= EXYNOS_MSCTRL_INPUT_MEMORY;
1481                 fimc_write(ctx, cfg0, EXYNOS_MSCTRL);
1482                 break;
1483         case IPP_CMD_WB:
1484                 fimc_set_type_ctrl(ctx, FIMC_WB_A);
1485                 fimc_handle_lastend(ctx, true);
1486
1487                 /* setup FIMD */
1488                 ret = fimc_set_camblk_fimd0_wb(ctx);
1489                 if (ret < 0) {
1490                         dev_err(dev, "camblk setup failed.\n");
1491                         return ret;
1492                 }
1493
1494                 set_wb.enable = 1;
1495                 set_wb.refresh = property->refresh_rate;
1496                 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1497                 break;
1498         case IPP_CMD_OUTPUT:
1499         default:
1500                 ret = -EINVAL;
1501                 dev_err(dev, "invalid operations.\n");
1502                 return ret;
1503         }
1504
1505         /* Reset status */
1506         fimc_write(ctx, 0x0, EXYNOS_CISTATUS);
1507
1508         cfg0 = fimc_read(ctx, EXYNOS_CIIMGCPT);
1509         cfg0 &= ~EXYNOS_CIIMGCPT_IMGCPTEN_SC;
1510         cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN_SC;
1511
1512         /* Scaler */
1513         cfg1 = fimc_read(ctx, EXYNOS_CISCCTRL);
1514         cfg1 &= ~EXYNOS_CISCCTRL_SCAN_MASK;
1515         cfg1 |= (EXYNOS_CISCCTRL_PROGRESSIVE |
1516                 EXYNOS_CISCCTRL_SCALERSTART);
1517
1518         fimc_write(ctx, cfg1, EXYNOS_CISCCTRL);
1519
1520         /* Enable image capture*/
1521         cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN;
1522         fimc_write(ctx, cfg0, EXYNOS_CIIMGCPT);
1523
1524         /* Disable frame end irq */
1525         fimc_clear_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_END_DISABLE);
1526
1527         fimc_clear_bits(ctx, EXYNOS_CIOCTRL, EXYNOS_CIOCTRL_WEAVE_MASK);
1528
1529         if (cmd == IPP_CMD_M2M)
1530                 fimc_set_bits(ctx, EXYNOS_MSCTRL, EXYNOS_MSCTRL_ENVID);
1531
1532         return 0;
1533 }
1534
1535 static void fimc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1536 {
1537         struct fimc_context *ctx = get_fimc_context(dev);
1538         struct drm_exynos_ipp_set_wb set_wb = {0, 0};
1539         u32 cfg;
1540
1541         DRM_DEBUG_KMS("cmd[%d]\n", cmd);
1542
1543         switch (cmd) {
1544         case IPP_CMD_M2M:
1545                 /* Source clear */
1546                 cfg = fimc_read(ctx, EXYNOS_MSCTRL);
1547                 cfg &= ~EXYNOS_MSCTRL_INPUT_MASK;
1548                 cfg &= ~EXYNOS_MSCTRL_ENVID;
1549                 fimc_write(ctx, cfg, EXYNOS_MSCTRL);
1550                 break;
1551         case IPP_CMD_WB:
1552                 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1553                 break;
1554         case IPP_CMD_OUTPUT:
1555         default:
1556                 dev_err(dev, "invalid operations.\n");
1557                 break;
1558         }
1559
1560         fimc_mask_irq(ctx, false);
1561
1562         /* reset sequence */
1563         fimc_write(ctx, 0x0, EXYNOS_CIFCNTSEQ);
1564
1565         /* Scaler disable */
1566         fimc_clear_bits(ctx, EXYNOS_CISCCTRL, EXYNOS_CISCCTRL_SCALERSTART);
1567
1568         /* Disable image capture */
1569         fimc_clear_bits(ctx, EXYNOS_CIIMGCPT,
1570                 EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN);
1571
1572         /* Enable frame end irq */
1573         fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_END_DISABLE);
1574 }
1575
1576 static void fimc_put_clocks(struct fimc_context *ctx)
1577 {
1578         int i;
1579
1580         for (i = 0; i < FIMC_CLKS_MAX; i++) {
1581                 if (IS_ERR(ctx->clocks[i]))
1582                         continue;
1583                 clk_put(ctx->clocks[i]);
1584                 ctx->clocks[i] = ERR_PTR(-EINVAL);
1585         }
1586 }
1587
1588 static int fimc_setup_clocks(struct fimc_context *ctx)
1589 {
1590         struct device *fimc_dev = ctx->ippdrv.dev;
1591         struct device *dev;
1592         int ret, i;
1593
1594         for (i = 0; i < FIMC_CLKS_MAX; i++)
1595                 ctx->clocks[i] = ERR_PTR(-EINVAL);
1596
1597         for (i = 0; i < FIMC_CLKS_MAX; i++) {
1598                 if (i == FIMC_CLK_WB_A || i == FIMC_CLK_WB_B)
1599                         dev = fimc_dev->parent;
1600                 else
1601                         dev = fimc_dev;
1602
1603                 ctx->clocks[i] = clk_get(dev, fimc_clock_names[i]);
1604                 if (IS_ERR(ctx->clocks[i])) {
1605                         if (i >= FIMC_CLK_MUX)
1606                                 break;
1607                         ret = PTR_ERR(ctx->clocks[i]);
1608                         dev_err(fimc_dev, "failed to get clock: %s\n",
1609                                                 fimc_clock_names[i]);
1610                         goto e_clk_free;
1611                 }
1612         }
1613
1614         /* Optional FIMC LCLK parent clock setting */
1615         if (!IS_ERR(ctx->clocks[FIMC_CLK_PARENT])) {
1616                 ret = clk_set_parent(ctx->clocks[FIMC_CLK_MUX],
1617                                      ctx->clocks[FIMC_CLK_PARENT]);
1618                 if (ret < 0) {
1619                         dev_err(fimc_dev, "failed to set parent.\n");
1620                         goto e_clk_free;
1621                 }
1622         }
1623
1624         ret = clk_set_rate(ctx->clocks[FIMC_CLK_LCLK], ctx->clk_frequency);
1625         if (ret < 0)
1626                 goto e_clk_free;
1627
1628         ret = clk_prepare_enable(ctx->clocks[FIMC_CLK_LCLK]);
1629         if (!ret)
1630                 return ret;
1631 e_clk_free:
1632         fimc_put_clocks(ctx);
1633         return ret;
1634 }
1635
1636 static int fimc_parse_dt(struct fimc_context *ctx)
1637 {
1638         struct device_node *node = ctx->ippdrv.dev->of_node;
1639
1640         /* Handle only devices that support the LCD Writeback data path */
1641         if (!of_property_read_bool(node, "samsung,lcd-wb"))
1642                 return -ENODEV;
1643
1644         if (of_property_read_u32(node, "clock-frequency",
1645                                         &ctx->clk_frequency))
1646                 ctx->clk_frequency = FIMC_DEFAULT_LCLK_FREQUENCY;
1647
1648         ctx->id = of_alias_get_id(node, "fimc");
1649
1650         if (ctx->id < 0) {
1651                 dev_err(ctx->ippdrv.dev, "failed to get node alias id.\n");
1652                 return -EINVAL;
1653         }
1654
1655         return 0;
1656 }
1657
1658 static int fimc_probe(struct platform_device *pdev)
1659 {
1660         struct device *dev = &pdev->dev;
1661         struct fimc_context *ctx;
1662         struct resource *res;
1663         struct exynos_drm_ippdrv *ippdrv;
1664         int ret;
1665
1666         if (!dev->of_node) {
1667                 dev_err(dev, "device tree node not found.\n");
1668                 return -ENODEV;
1669         }
1670
1671         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1672         if (!ctx)
1673                 return -ENOMEM;
1674
1675         ctx->ippdrv.dev = dev;
1676
1677         ret = fimc_parse_dt(ctx);
1678         if (ret < 0)
1679                 return ret;
1680
1681         ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1682                                                 "samsung,sysreg");
1683         if (IS_ERR(ctx->sysreg)) {
1684                 dev_err(dev, "syscon regmap lookup failed.\n");
1685                 return PTR_ERR(ctx->sysreg);
1686         }
1687
1688         /* resource memory */
1689         ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1690         ctx->regs = devm_ioremap_resource(dev, ctx->regs_res);
1691         if (IS_ERR(ctx->regs))
1692                 return PTR_ERR(ctx->regs);
1693
1694         /* resource irq */
1695         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1696         if (!res) {
1697                 dev_err(dev, "failed to request irq resource.\n");
1698                 return -ENOENT;
1699         }
1700
1701         ctx->irq = res->start;
1702         ret = devm_request_threaded_irq(dev, ctx->irq, NULL, fimc_irq_handler,
1703                 IRQF_ONESHOT, "drm_fimc", ctx);
1704         if (ret < 0) {
1705                 dev_err(dev, "failed to request irq.\n");
1706                 return ret;
1707         }
1708
1709         ret = fimc_setup_clocks(ctx);
1710         if (ret < 0)
1711                 return ret;
1712
1713         ippdrv = &ctx->ippdrv;
1714         ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &fimc_src_ops;
1715         ippdrv->ops[EXYNOS_DRM_OPS_DST] = &fimc_dst_ops;
1716         ippdrv->check_property = fimc_ippdrv_check_property;
1717         ippdrv->reset = fimc_ippdrv_reset;
1718         ippdrv->start = fimc_ippdrv_start;
1719         ippdrv->stop = fimc_ippdrv_stop;
1720         ret = fimc_init_prop_list(ippdrv);
1721         if (ret < 0) {
1722                 dev_err(dev, "failed to init property list.\n");
1723                 goto err_put_clk;
1724         }
1725
1726         DRM_DEBUG_KMS("id[%d]ippdrv[0x%x]\n", ctx->id, (int)ippdrv);
1727
1728         spin_lock_init(&ctx->lock);
1729         platform_set_drvdata(pdev, ctx);
1730
1731         pm_runtime_enable(dev);
1732
1733         ret = exynos_drm_ippdrv_register(ippdrv);
1734         if (ret < 0) {
1735                 dev_err(dev, "failed to register drm fimc device.\n");
1736                 goto err_pm_dis;
1737         }
1738
1739         dev_info(dev, "drm fimc registered successfully.\n");
1740
1741         return 0;
1742
1743 err_pm_dis:
1744         pm_runtime_disable(dev);
1745 err_put_clk:
1746         fimc_put_clocks(ctx);
1747
1748         return ret;
1749 }
1750
1751 static int fimc_remove(struct platform_device *pdev)
1752 {
1753         struct device *dev = &pdev->dev;
1754         struct fimc_context *ctx = get_fimc_context(dev);
1755         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1756
1757         exynos_drm_ippdrv_unregister(ippdrv);
1758
1759         fimc_put_clocks(ctx);
1760         pm_runtime_set_suspended(dev);
1761         pm_runtime_disable(dev);
1762
1763         return 0;
1764 }
1765
1766 #ifdef CONFIG_PM
1767 static int fimc_clk_ctrl(struct fimc_context *ctx, bool enable)
1768 {
1769         DRM_DEBUG_KMS("enable[%d]\n", enable);
1770
1771         if (enable) {
1772                 clk_prepare_enable(ctx->clocks[FIMC_CLK_GATE]);
1773                 clk_prepare_enable(ctx->clocks[FIMC_CLK_WB_A]);
1774                 ctx->suspended = false;
1775         } else {
1776                 clk_disable_unprepare(ctx->clocks[FIMC_CLK_GATE]);
1777                 clk_disable_unprepare(ctx->clocks[FIMC_CLK_WB_A]);
1778                 ctx->suspended = true;
1779         }
1780
1781         return 0;
1782 }
1783
1784 #ifdef CONFIG_PM_SLEEP
1785 static int fimc_suspend(struct device *dev)
1786 {
1787         struct fimc_context *ctx = get_fimc_context(dev);
1788
1789         DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1790
1791         if (pm_runtime_suspended(dev))
1792                 return 0;
1793
1794         return fimc_clk_ctrl(ctx, false);
1795 }
1796
1797 static int fimc_resume(struct device *dev)
1798 {
1799         struct fimc_context *ctx = get_fimc_context(dev);
1800
1801         DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1802
1803         if (!pm_runtime_suspended(dev))
1804                 return fimc_clk_ctrl(ctx, true);
1805
1806         return 0;
1807 }
1808 #endif
1809
1810 static int fimc_runtime_suspend(struct device *dev)
1811 {
1812         struct fimc_context *ctx = get_fimc_context(dev);
1813
1814         DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1815
1816         return  fimc_clk_ctrl(ctx, false);
1817 }
1818
1819 static int fimc_runtime_resume(struct device *dev)
1820 {
1821         struct fimc_context *ctx = get_fimc_context(dev);
1822
1823         DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1824
1825         return  fimc_clk_ctrl(ctx, true);
1826 }
1827 #endif
1828
1829 static const struct dev_pm_ops fimc_pm_ops = {
1830         SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume)
1831         SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL)
1832 };
1833
1834 static const struct of_device_id fimc_of_match[] = {
1835         { .compatible = "samsung,exynos4210-fimc" },
1836         { .compatible = "samsung,exynos4212-fimc" },
1837         { },
1838 };
1839 MODULE_DEVICE_TABLE(of, fimc_of_match);
1840
1841 struct platform_driver fimc_driver = {
1842         .probe          = fimc_probe,
1843         .remove         = fimc_remove,
1844         .driver         = {
1845                 .of_match_table = fimc_of_match,
1846                 .name   = "exynos-drm-fimc",
1847                 .owner  = THIS_MODULE,
1848                 .pm     = &fimc_pm_ops,
1849         },
1850 };
1851