1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "intel_bios.h"
38 #include "intel_ringbuffer.h"
39 #include "intel_lrc.h"
40 #include "i915_gem_gtt.h"
41 #include "i915_gem_render_state.h"
42 #include <linux/io-mapping.h>
43 #include <linux/i2c.h>
44 #include <linux/i2c-algo-bit.h>
45 #include <drm/intel-gtt.h>
46 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
47 #include <drm/drm_gem.h>
48 #include <linux/backlight.h>
49 #include <linux/hashtable.h>
50 #include <linux/intel-iommu.h>
51 #include <linux/kref.h>
52 #include <linux/pm_qos.h>
54 /* General customization:
57 #define DRIVER_NAME "i915"
58 #define DRIVER_DESC "Intel Graphics"
59 #define DRIVER_DATE "20150731"
62 /* Many gcc seem to no see through this and fall over :( */
64 #define WARN_ON(x) ({ \
65 bool __i915_warn_cond = (x); \
66 if (__builtin_constant_p(__i915_warn_cond)) \
67 BUILD_BUG_ON(__i915_warn_cond); \
68 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
70 #define WARN_ON(x) WARN((x), "WARN_ON(" #x ")")
74 #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(" #x ")")
76 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
77 (long) (x), __func__);
79 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
80 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
81 * which may not necessarily be a user visible problem. This will either
82 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
83 * enable distros and users to tailor their preferred amount of i915 abrt
86 #define I915_STATE_WARN(condition, format...) ({ \
87 int __ret_warn_on = !!(condition); \
88 if (unlikely(__ret_warn_on)) { \
89 if (i915.verbose_state_checks) \
94 unlikely(__ret_warn_on); \
97 #define I915_STATE_WARN_ON(condition) ({ \
98 int __ret_warn_on = !!(condition); \
99 if (unlikely(__ret_warn_on)) { \
100 if (i915.verbose_state_checks) \
101 WARN(1, "WARN_ON(" #condition ")\n"); \
103 DRM_ERROR("WARN_ON(" #condition ")\n"); \
105 unlikely(__ret_warn_on); \
114 I915_MAX_PIPES = _PIPE_EDP
116 #define pipe_name(p) ((p) + 'A')
125 #define transcoder_name(t) ((t) + 'A')
128 * This is the maximum (across all platforms) number of planes (primary +
129 * sprites) that can be active at the same time on one pipe.
131 * This value doesn't count the cursor plane.
133 #define I915_MAX_PLANES 4
140 #define plane_name(p) ((p) + 'A')
142 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
152 #define port_name(p) ((p) + 'A')
154 #define I915_NUM_PHYS_VLV 2
166 enum intel_display_power_domain {
170 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
171 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
172 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
173 POWER_DOMAIN_TRANSCODER_A,
174 POWER_DOMAIN_TRANSCODER_B,
175 POWER_DOMAIN_TRANSCODER_C,
176 POWER_DOMAIN_TRANSCODER_EDP,
177 POWER_DOMAIN_PORT_DDI_A_2_LANES,
178 POWER_DOMAIN_PORT_DDI_A_4_LANES,
179 POWER_DOMAIN_PORT_DDI_B_2_LANES,
180 POWER_DOMAIN_PORT_DDI_B_4_LANES,
181 POWER_DOMAIN_PORT_DDI_C_2_LANES,
182 POWER_DOMAIN_PORT_DDI_C_4_LANES,
183 POWER_DOMAIN_PORT_DDI_D_2_LANES,
184 POWER_DOMAIN_PORT_DDI_D_4_LANES,
185 POWER_DOMAIN_PORT_DDI_E_2_LANES,
186 POWER_DOMAIN_PORT_DSI,
187 POWER_DOMAIN_PORT_CRT,
188 POWER_DOMAIN_PORT_OTHER,
201 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
202 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
203 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
204 #define POWER_DOMAIN_TRANSCODER(tran) \
205 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
206 (tran) + POWER_DOMAIN_TRANSCODER_A)
210 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
222 #define for_each_hpd_pin(__pin) \
223 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
225 struct i915_hotplug {
226 struct work_struct hotplug_work;
229 unsigned long last_jiffies;
234 HPD_MARK_DISABLED = 2
236 } stats[HPD_NUM_PINS];
238 struct delayed_work reenable_work;
240 struct intel_digital_port *irq_port[I915_MAX_PORTS];
243 struct work_struct dig_port_work;
246 * if we get a HPD irq from DP and a HPD irq from non-DP
247 * the non-DP HPD could block the workqueue on a mode config
248 * mutex getting, that userspace may have taken. However
249 * userspace is waiting on the DP workqueue to run which is
250 * blocked behind the non-DP one.
252 struct workqueue_struct *dp_wq;
255 #define I915_GEM_GPU_DOMAINS \
256 (I915_GEM_DOMAIN_RENDER | \
257 I915_GEM_DOMAIN_SAMPLER | \
258 I915_GEM_DOMAIN_COMMAND | \
259 I915_GEM_DOMAIN_INSTRUCTION | \
260 I915_GEM_DOMAIN_VERTEX)
262 #define for_each_pipe(__dev_priv, __p) \
263 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
264 #define for_each_plane(__dev_priv, __pipe, __p) \
266 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
268 #define for_each_sprite(__dev_priv, __p, __s) \
270 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
273 #define for_each_crtc(dev, crtc) \
274 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
276 #define for_each_intel_plane(dev, intel_plane) \
277 list_for_each_entry(intel_plane, \
278 &dev->mode_config.plane_list, \
281 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
282 list_for_each_entry(intel_plane, \
283 &(dev)->mode_config.plane_list, \
285 if ((intel_plane)->pipe == (intel_crtc)->pipe)
287 #define for_each_intel_crtc(dev, intel_crtc) \
288 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
290 #define for_each_intel_encoder(dev, intel_encoder) \
291 list_for_each_entry(intel_encoder, \
292 &(dev)->mode_config.encoder_list, \
295 #define for_each_intel_connector(dev, intel_connector) \
296 list_for_each_entry(intel_connector, \
297 &dev->mode_config.connector_list, \
300 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
301 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
302 if ((intel_encoder)->base.crtc == (__crtc))
304 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
305 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
306 if ((intel_connector)->base.encoder == (__encoder))
308 #define for_each_power_domain(domain, mask) \
309 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
310 if ((1 << (domain)) & (mask))
312 struct drm_i915_private;
313 struct i915_mm_struct;
314 struct i915_mmu_object;
316 struct drm_i915_file_private {
317 struct drm_i915_private *dev_priv;
318 struct drm_file *file;
322 struct list_head request_list;
323 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
324 * chosen to prevent the CPU getting more than a frame ahead of the GPU
325 * (when using lax throttling for the frontbuffer). We also use it to
326 * offer free GPU waitboosts for severely congested workloads.
328 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
330 struct idr context_idr;
332 struct intel_rps_client {
333 struct list_head link;
337 struct intel_engine_cs *bsd_ring;
341 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
342 /* real shared dpll ids must be >= 0 */
343 DPLL_ID_PCH_PLL_A = 0,
344 DPLL_ID_PCH_PLL_B = 1,
349 DPLL_ID_SKL_DPLL1 = 0,
350 DPLL_ID_SKL_DPLL2 = 1,
351 DPLL_ID_SKL_DPLL3 = 2,
353 #define I915_NUM_PLLS 3
355 struct intel_dpll_hw_state {
367 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
368 * lower part of ctrl1 and they get shifted into position when writing
369 * the register. This allows us to easily compare the state to share
373 /* HDMI only, 0 when used for DP */
374 uint32_t cfgcr1, cfgcr2;
377 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
381 struct intel_shared_dpll_config {
382 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
383 struct intel_dpll_hw_state hw_state;
386 struct intel_shared_dpll {
387 struct intel_shared_dpll_config config;
389 int active; /* count of number of active CRTCs (i.e. DPMS on) */
390 bool on; /* is the PLL actually active? Disabled during modeset */
392 /* should match the index in the dev_priv->shared_dplls array */
393 enum intel_dpll_id id;
394 /* The mode_set hook is optional and should be used together with the
395 * intel_prepare_shared_dpll function. */
396 void (*mode_set)(struct drm_i915_private *dev_priv,
397 struct intel_shared_dpll *pll);
398 void (*enable)(struct drm_i915_private *dev_priv,
399 struct intel_shared_dpll *pll);
400 void (*disable)(struct drm_i915_private *dev_priv,
401 struct intel_shared_dpll *pll);
402 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
403 struct intel_shared_dpll *pll,
404 struct intel_dpll_hw_state *hw_state);
412 /* Used by dp and fdi links */
413 struct intel_link_m_n {
421 void intel_link_compute_m_n(int bpp, int nlanes,
422 int pixel_clock, int link_clock,
423 struct intel_link_m_n *m_n);
425 /* Interface history:
428 * 1.2: Add Power Management
429 * 1.3: Add vblank support
430 * 1.4: Fix cmdbuffer path, add heap destroy
431 * 1.5: Add vblank pipe configuration
432 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
433 * - Support vertical blank on secondary display pipe
435 #define DRIVER_MAJOR 1
436 #define DRIVER_MINOR 6
437 #define DRIVER_PATCHLEVEL 0
439 #define WATCH_LISTS 0
441 struct opregion_header;
442 struct opregion_acpi;
443 struct opregion_swsci;
444 struct opregion_asle;
446 struct intel_opregion {
447 struct opregion_header __iomem *header;
448 struct opregion_acpi __iomem *acpi;
449 struct opregion_swsci __iomem *swsci;
450 u32 swsci_gbda_sub_functions;
451 u32 swsci_sbcb_sub_functions;
452 struct opregion_asle __iomem *asle;
454 u32 __iomem *lid_state;
455 struct work_struct asle_work;
457 #define OPREGION_SIZE (8*1024)
459 struct intel_overlay;
460 struct intel_overlay_error_state;
462 #define I915_FENCE_REG_NONE -1
463 #define I915_MAX_NUM_FENCES 32
464 /* 32 fences + sign bit for FENCE_REG_NONE */
465 #define I915_MAX_NUM_FENCE_BITS 6
467 struct drm_i915_fence_reg {
468 struct list_head lru_list;
469 struct drm_i915_gem_object *obj;
473 struct sdvo_device_mapping {
482 struct intel_display_error_state;
484 struct drm_i915_error_state {
493 /* Generic register state */
501 u32 error; /* gen6+ */
502 u32 err_int; /* gen7 */
503 u32 fault_data0; /* gen8, gen9 */
504 u32 fault_data1; /* gen8, gen9 */
510 u32 extra_instdone[I915_NUM_INSTDONE_REG];
511 u64 fence[I915_MAX_NUM_FENCES];
512 struct intel_overlay_error_state *overlay;
513 struct intel_display_error_state *display;
514 struct drm_i915_error_object *semaphore_obj;
516 struct drm_i915_error_ring {
518 /* Software tracked state */
521 enum intel_ring_hangcheck_action hangcheck_action;
524 /* our own tracking of ring head and tail */
528 u32 semaphore_seqno[I915_NUM_RINGS - 1];
547 u32 rc_psmi; /* sleep state */
548 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
550 struct drm_i915_error_object {
554 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
556 struct drm_i915_error_request {
571 char comm[TASK_COMM_LEN];
572 } ring[I915_NUM_RINGS];
574 struct drm_i915_error_buffer {
577 u32 rseqno[I915_NUM_RINGS], wseqno;
581 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
589 } **active_bo, **pinned_bo;
591 u32 *active_bo_count, *pinned_bo_count;
595 struct intel_connector;
596 struct intel_encoder;
597 struct intel_crtc_state;
598 struct intel_initial_plane_config;
603 struct drm_i915_display_funcs {
604 int (*get_display_clock_speed)(struct drm_device *dev);
605 int (*get_fifo_size)(struct drm_device *dev, int plane);
607 * find_dpll() - Find the best values for the PLL
608 * @limit: limits for the PLL
609 * @crtc: current CRTC
610 * @target: target frequency in kHz
611 * @refclk: reference clock frequency in kHz
612 * @match_clock: if provided, @best_clock P divider must
613 * match the P divider from @match_clock
614 * used for LVDS downclocking
615 * @best_clock: best PLL values found
617 * Returns true on success, false on failure.
619 bool (*find_dpll)(const struct intel_limit *limit,
620 struct intel_crtc_state *crtc_state,
621 int target, int refclk,
622 struct dpll *match_clock,
623 struct dpll *best_clock);
624 void (*update_wm)(struct drm_crtc *crtc);
625 void (*update_sprite_wm)(struct drm_plane *plane,
626 struct drm_crtc *crtc,
627 uint32_t sprite_width, uint32_t sprite_height,
628 int pixel_size, bool enable, bool scaled);
629 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
630 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
631 /* Returns the active state of the crtc, and if the crtc is active,
632 * fills out the pipe-config with the hw state. */
633 bool (*get_pipe_config)(struct intel_crtc *,
634 struct intel_crtc_state *);
635 void (*get_initial_plane_config)(struct intel_crtc *,
636 struct intel_initial_plane_config *);
637 int (*crtc_compute_clock)(struct intel_crtc *crtc,
638 struct intel_crtc_state *crtc_state);
639 void (*crtc_enable)(struct drm_crtc *crtc);
640 void (*crtc_disable)(struct drm_crtc *crtc);
641 void (*audio_codec_enable)(struct drm_connector *connector,
642 struct intel_encoder *encoder,
643 struct drm_display_mode *mode);
644 void (*audio_codec_disable)(struct intel_encoder *encoder);
645 void (*fdi_link_train)(struct drm_crtc *crtc);
646 void (*init_clock_gating)(struct drm_device *dev);
647 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
648 struct drm_framebuffer *fb,
649 struct drm_i915_gem_object *obj,
650 struct drm_i915_gem_request *req,
652 void (*update_primary_plane)(struct drm_crtc *crtc,
653 struct drm_framebuffer *fb,
655 void (*hpd_irq_setup)(struct drm_device *dev);
656 /* clock updates for mode set */
658 /* render clock increase/decrease */
659 /* display clock increase/decrease */
660 /* pll clock increase/decrease */
662 int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe);
663 uint32_t (*get_backlight)(struct intel_connector *connector);
664 void (*set_backlight)(struct intel_connector *connector,
666 void (*disable_backlight)(struct intel_connector *connector);
667 void (*enable_backlight)(struct intel_connector *connector);
670 enum forcewake_domain_id {
671 FW_DOMAIN_ID_RENDER = 0,
672 FW_DOMAIN_ID_BLITTER,
678 enum forcewake_domains {
679 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
680 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
681 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
682 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
687 struct intel_uncore_funcs {
688 void (*force_wake_get)(struct drm_i915_private *dev_priv,
689 enum forcewake_domains domains);
690 void (*force_wake_put)(struct drm_i915_private *dev_priv,
691 enum forcewake_domains domains);
693 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
694 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
695 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
696 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
698 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
699 uint8_t val, bool trace);
700 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
701 uint16_t val, bool trace);
702 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
703 uint32_t val, bool trace);
704 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
705 uint64_t val, bool trace);
708 struct intel_uncore {
709 spinlock_t lock; /** lock is also taken in irq contexts. */
711 struct intel_uncore_funcs funcs;
714 enum forcewake_domains fw_domains;
716 struct intel_uncore_forcewake_domain {
717 struct drm_i915_private *i915;
718 enum forcewake_domain_id id;
720 struct timer_list timer;
727 } fw_domain[FW_DOMAIN_ID_COUNT];
730 /* Iterate over initialised fw domains */
731 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
732 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
733 (i__) < FW_DOMAIN_ID_COUNT; \
734 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
735 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
737 #define for_each_fw_domain(domain__, dev_priv__, i__) \
738 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
741 FW_UNINITIALIZED = 0,
748 uint32_t *dmc_payload;
749 uint32_t dmc_fw_size;
751 uint32_t mmioaddr[8];
752 uint32_t mmiodata[8];
753 enum csr_state state;
756 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
757 func(is_mobile) sep \
760 func(is_i945gm) sep \
762 func(need_gfx_hws) sep \
764 func(is_pineview) sep \
765 func(is_broadwater) sep \
766 func(is_crestline) sep \
767 func(is_ivybridge) sep \
768 func(is_valleyview) sep \
769 func(is_haswell) sep \
770 func(is_skylake) sep \
771 func(is_preliminary) sep \
773 func(has_pipe_cxsr) sep \
774 func(has_hotplug) sep \
775 func(cursor_needs_physical) sep \
776 func(has_overlay) sep \
777 func(overlay_needs_physical) sep \
778 func(supports_tv) sep \
783 #define DEFINE_FLAG(name) u8 name:1
784 #define SEP_SEMICOLON ;
786 struct intel_device_info {
787 u32 display_mmio_offset;
790 u8 num_sprites[I915_MAX_PIPES];
792 u8 ring_mask; /* Rings supported by the HW */
793 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
794 /* Register offsets for the various display pipes and transcoders */
795 int pipe_offsets[I915_MAX_TRANSCODERS];
796 int trans_offsets[I915_MAX_TRANSCODERS];
797 int palette_offsets[I915_MAX_PIPES];
798 int cursor_offsets[I915_MAX_PIPES];
800 /* Slice/subslice/EU info */
803 u8 subslice_per_slice;
806 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
809 u8 has_subslice_pg:1;
816 enum i915_cache_level {
818 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
819 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
820 caches, eg sampler/render caches, and the
821 large Last-Level-Cache. LLC is coherent with
822 the CPU, but L3 is only visible to the GPU. */
823 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
826 struct i915_ctx_hang_stats {
827 /* This context had batch pending when hang was declared */
828 unsigned batch_pending;
830 /* This context had batch active when hang was declared */
831 unsigned batch_active;
833 /* Time when this context was last blamed for a GPU reset */
834 unsigned long guilty_ts;
836 /* If the contexts causes a second GPU hang within this time,
837 * it is permanently banned from submitting any more work.
839 unsigned long ban_period_seconds;
841 /* This context is banned to submit more work */
845 /* This must match up with the value previously used for execbuf2.rsvd1. */
846 #define DEFAULT_CONTEXT_HANDLE 0
848 #define CONTEXT_NO_ZEROMAP (1<<0)
850 * struct intel_context - as the name implies, represents a context.
851 * @ref: reference count.
852 * @user_handle: userspace tracking identity for this context.
853 * @remap_slice: l3 row remapping information.
854 * @flags: context specific flags:
855 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
856 * @file_priv: filp associated with this context (NULL for global default
858 * @hang_stats: information about the role of this context in possible GPU
860 * @ppgtt: virtual memory space used by this context.
861 * @legacy_hw_ctx: render context backing object and whether it is correctly
862 * initialized (legacy ring submission mechanism only).
863 * @link: link in the global list of contexts.
865 * Contexts are memory images used by the hardware to store copies of their
868 struct intel_context {
872 struct drm_i915_private *i915;
874 struct drm_i915_file_private *file_priv;
875 struct i915_ctx_hang_stats hang_stats;
876 struct i915_hw_ppgtt *ppgtt;
878 /* Legacy ring buffer submission */
880 struct drm_i915_gem_object *rcs_state;
885 bool rcs_initialized;
887 struct drm_i915_gem_object *state;
888 struct intel_ringbuffer *ringbuf;
890 } engine[I915_NUM_RINGS];
892 struct list_head link;
904 /* This is always the inner lock when overlapping with struct_mutex and
905 * it's the outer lock when overlapping with stolen_lock. */
907 unsigned long uncompressed_size;
910 unsigned int possible_framebuffer_bits;
911 unsigned int busy_bits;
912 struct intel_crtc *crtc;
915 struct drm_mm_node compressed_fb;
916 struct drm_mm_node *compressed_llb;
920 /* Tracks whether the HW is actually enabled, not whether the feature is
924 struct intel_fbc_work {
925 struct delayed_work work;
926 struct intel_crtc *crtc;
927 struct drm_framebuffer *fb;
931 FBC_OK, /* FBC is enabled */
932 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
933 FBC_NO_OUTPUT, /* no outputs enabled to compress */
934 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
935 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
936 FBC_MODE_TOO_LARGE, /* mode too large for compression */
937 FBC_BAD_PLANE, /* fbc not supported on plane */
938 FBC_NOT_TILED, /* buffer not tiled */
939 FBC_MULTIPLE_PIPES, /* more than one pipe active */
941 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
942 FBC_ROTATION, /* rotation is not supported */
943 FBC_IN_DBG_MASTER, /* kernel debugger is active */
946 bool (*fbc_enabled)(struct drm_i915_private *dev_priv);
947 void (*enable_fbc)(struct intel_crtc *crtc);
948 void (*disable_fbc)(struct drm_i915_private *dev_priv);
952 * HIGH_RR is the highest eDP panel refresh rate read from EDID
953 * LOW_RR is the lowest eDP panel refresh rate found from EDID
954 * parsing for same resolution.
956 enum drrs_refresh_rate_type {
959 DRRS_MAX_RR, /* RR count */
962 enum drrs_support_type {
963 DRRS_NOT_SUPPORTED = 0,
964 STATIC_DRRS_SUPPORT = 1,
965 SEAMLESS_DRRS_SUPPORT = 2
971 struct delayed_work work;
973 unsigned busy_frontbuffer_bits;
974 enum drrs_refresh_rate_type refresh_rate_type;
975 enum drrs_support_type type;
982 struct intel_dp *enabled;
984 struct delayed_work work;
985 unsigned busy_frontbuffer_bits;
991 PCH_NONE = 0, /* No PCH present */
992 PCH_IBX, /* Ibexpeak PCH */
993 PCH_CPT, /* Cougarpoint PCH */
994 PCH_LPT, /* Lynxpoint PCH */
995 PCH_SPT, /* Sunrisepoint PCH */
999 enum intel_sbi_destination {
1004 #define QUIRK_PIPEA_FORCE (1<<0)
1005 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1006 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1007 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1008 #define QUIRK_PIPEB_FORCE (1<<4)
1009 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1012 struct intel_fbc_work;
1014 struct intel_gmbus {
1015 struct i2c_adapter adapter;
1019 struct i2c_algo_bit_data bit_algo;
1020 struct drm_i915_private *dev_priv;
1023 struct i915_suspend_saved_registers {
1026 u32 savePP_ON_DELAYS;
1027 u32 savePP_OFF_DELAYS;
1032 u32 saveFBC_CONTROL;
1033 u32 saveCACHE_MODE_0;
1034 u32 saveMI_ARB_STATE;
1038 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1039 u32 savePCH_PORT_HOTPLUG;
1043 struct vlv_s0ix_state {
1050 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1051 u32 media_max_req_count;
1052 u32 gfx_max_req_count;
1078 u32 rp_down_timeout;
1084 /* Display 1 CZ domain */
1089 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1091 /* GT SA CZ domain */
1098 /* Display 2 CZ domain */
1102 u32 clock_gate_dis2;
1105 struct intel_rps_ei {
1111 struct intel_gen6_power_mgmt {
1113 * work, interrupts_enabled and pm_iir are protected by
1114 * dev_priv->irq_lock
1116 struct work_struct work;
1117 bool interrupts_enabled;
1120 /* Frequencies are stored in potentially platform dependent multiples.
1121 * In other words, *_freq needs to be multiplied by X to be interesting.
1122 * Soft limits are those which are used for the dynamic reclocking done
1123 * by the driver (raise frequencies under heavy loads, and lower for
1124 * lighter loads). Hard limits are those imposed by the hardware.
1126 * A distinction is made for overclocking, which is never enabled by
1127 * default, and is considered to be above the hard limit if it's
1130 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1131 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1132 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1133 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1134 u8 min_freq; /* AKA RPn. Minimum frequency */
1135 u8 idle_freq; /* Frequency to request when we are idle */
1136 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1137 u8 rp1_freq; /* "less than" RP0 power/freqency */
1138 u8 rp0_freq; /* Non-overclocked max frequency. */
1141 u8 up_threshold; /* Current %busy required to uplock */
1142 u8 down_threshold; /* Current %busy required to downclock */
1145 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1147 spinlock_t client_lock;
1148 struct list_head clients;
1152 struct delayed_work delayed_resume_work;
1155 struct intel_rps_client semaphores, mmioflips;
1157 /* manual wa residency calculations */
1158 struct intel_rps_ei up_ei, down_ei;
1161 * Protects RPS/RC6 register access and PCU communication.
1162 * Must be taken after struct_mutex if nested. Note that
1163 * this lock may be held for long periods of time when
1164 * talking to hw - so only take it when talking to hw!
1166 struct mutex hw_lock;
1169 /* defined intel_pm.c */
1170 extern spinlock_t mchdev_lock;
1172 struct intel_ilk_power_mgmt {
1180 unsigned long last_time1;
1181 unsigned long chipset_power;
1184 unsigned long gfx_power;
1191 struct drm_i915_private;
1192 struct i915_power_well;
1194 struct i915_power_well_ops {
1196 * Synchronize the well's hw state to match the current sw state, for
1197 * example enable/disable it based on the current refcount. Called
1198 * during driver init and resume time, possibly after first calling
1199 * the enable/disable handlers.
1201 void (*sync_hw)(struct drm_i915_private *dev_priv,
1202 struct i915_power_well *power_well);
1204 * Enable the well and resources that depend on it (for example
1205 * interrupts located on the well). Called after the 0->1 refcount
1208 void (*enable)(struct drm_i915_private *dev_priv,
1209 struct i915_power_well *power_well);
1211 * Disable the well and resources that depend on it. Called after
1212 * the 1->0 refcount transition.
1214 void (*disable)(struct drm_i915_private *dev_priv,
1215 struct i915_power_well *power_well);
1216 /* Returns the hw enabled state. */
1217 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1218 struct i915_power_well *power_well);
1221 /* Power well structure for haswell */
1222 struct i915_power_well {
1225 /* power well enable/disable usage count */
1227 /* cached hw enabled state */
1229 unsigned long domains;
1231 const struct i915_power_well_ops *ops;
1234 struct i915_power_domains {
1236 * Power wells needed for initialization at driver init and suspend
1237 * time are on. They are kept on until after the first modeset.
1241 int power_well_count;
1244 int domain_use_count[POWER_DOMAIN_NUM];
1245 struct i915_power_well *power_wells;
1248 #define MAX_L3_SLICES 2
1249 struct intel_l3_parity {
1250 u32 *remap_info[MAX_L3_SLICES];
1251 struct work_struct error_work;
1255 struct i915_gem_mm {
1256 /** Memory allocator for GTT stolen memory */
1257 struct drm_mm stolen;
1258 /** Protects the usage of the GTT stolen memory allocator. This is
1259 * always the inner lock when overlapping with struct_mutex. */
1260 struct mutex stolen_lock;
1262 /** List of all objects in gtt_space. Used to restore gtt
1263 * mappings on resume */
1264 struct list_head bound_list;
1266 * List of objects which are not bound to the GTT (thus
1267 * are idle and not used by the GPU) but still have
1268 * (presumably uncached) pages still attached.
1270 struct list_head unbound_list;
1272 /** Usable portion of the GTT for GEM */
1273 unsigned long stolen_base; /* limited to low memory (32-bit) */
1275 /** PPGTT used for aliasing the PPGTT with the GTT */
1276 struct i915_hw_ppgtt *aliasing_ppgtt;
1278 struct notifier_block oom_notifier;
1279 struct shrinker shrinker;
1280 bool shrinker_no_lock_stealing;
1282 /** LRU list of objects with fence regs on them. */
1283 struct list_head fence_list;
1286 * We leave the user IRQ off as much as possible,
1287 * but this means that requests will finish and never
1288 * be retired once the system goes idle. Set a timer to
1289 * fire periodically while the ring is running. When it
1290 * fires, go retire requests.
1292 struct delayed_work retire_work;
1295 * When we detect an idle GPU, we want to turn on
1296 * powersaving features. So once we see that there
1297 * are no more requests outstanding and no more
1298 * arrive within a small period of time, we fire
1299 * off the idle_work.
1301 struct delayed_work idle_work;
1304 * Are we in a non-interruptible section of code like
1310 * Is the GPU currently considered idle, or busy executing userspace
1311 * requests? Whilst idle, we attempt to power down the hardware and
1312 * display clocks. In order to reduce the effect on performance, there
1313 * is a slight delay before we do so.
1317 /* the indicator for dispatch video commands on two BSD rings */
1318 int bsd_ring_dispatch_index;
1320 /** Bit 6 swizzling required for X tiling */
1321 uint32_t bit_6_swizzle_x;
1322 /** Bit 6 swizzling required for Y tiling */
1323 uint32_t bit_6_swizzle_y;
1325 /* accounting, useful for userland debugging */
1326 spinlock_t object_stat_lock;
1327 size_t object_memory;
1331 struct drm_i915_error_state_buf {
1332 struct drm_i915_private *i915;
1341 struct i915_error_state_file_priv {
1342 struct drm_device *dev;
1343 struct drm_i915_error_state *error;
1346 struct i915_gpu_error {
1347 /* For hangcheck timer */
1348 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1349 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1350 /* Hang gpu twice in this window and your context gets banned */
1351 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1353 struct workqueue_struct *hangcheck_wq;
1354 struct delayed_work hangcheck_work;
1356 /* For reset and error_state handling. */
1358 /* Protected by the above dev->gpu_error.lock. */
1359 struct drm_i915_error_state *first_error;
1361 unsigned long missed_irq_rings;
1364 * State variable controlling the reset flow and count
1366 * This is a counter which gets incremented when reset is triggered,
1367 * and again when reset has been handled. So odd values (lowest bit set)
1368 * means that reset is in progress and even values that
1369 * (reset_counter >> 1):th reset was successfully completed.
1371 * If reset is not completed succesfully, the I915_WEDGE bit is
1372 * set meaning that hardware is terminally sour and there is no
1373 * recovery. All waiters on the reset_queue will be woken when
1376 * This counter is used by the wait_seqno code to notice that reset
1377 * event happened and it needs to restart the entire ioctl (since most
1378 * likely the seqno it waited for won't ever signal anytime soon).
1380 * This is important for lock-free wait paths, where no contended lock
1381 * naturally enforces the correct ordering between the bail-out of the
1382 * waiter and the gpu reset work code.
1384 atomic_t reset_counter;
1386 #define I915_RESET_IN_PROGRESS_FLAG 1
1387 #define I915_WEDGED (1 << 31)
1390 * Waitqueue to signal when the reset has completed. Used by clients
1391 * that wait for dev_priv->mm.wedged to settle.
1393 wait_queue_head_t reset_queue;
1395 /* Userspace knobs for gpu hang simulation;
1396 * combines both a ring mask, and extra flags
1399 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1400 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1402 /* For missed irq/seqno simulation. */
1403 unsigned int test_irq_rings;
1405 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1406 bool reload_in_reset;
1409 enum modeset_restore {
1410 MODESET_ON_LID_OPEN,
1415 #define DP_AUX_A 0x40
1416 #define DP_AUX_B 0x10
1417 #define DP_AUX_C 0x20
1418 #define DP_AUX_D 0x30
1420 #define DDC_PIN_B 0x05
1421 #define DDC_PIN_C 0x04
1422 #define DDC_PIN_D 0x06
1424 struct ddi_vbt_port_info {
1426 * This is an index in the HDMI/DVI DDI buffer translation table.
1427 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1428 * populate this field.
1430 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1431 uint8_t hdmi_level_shift;
1433 uint8_t supports_dvi:1;
1434 uint8_t supports_hdmi:1;
1435 uint8_t supports_dp:1;
1437 uint8_t alternate_aux_channel;
1438 uint8_t alternate_ddc_pin;
1440 uint8_t dp_boost_level;
1441 uint8_t hdmi_boost_level;
1444 enum psr_lines_to_wait {
1445 PSR_0_LINES_TO_WAIT = 0,
1447 PSR_4_LINES_TO_WAIT,
1451 struct intel_vbt_data {
1452 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1453 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1456 unsigned int int_tv_support:1;
1457 unsigned int lvds_dither:1;
1458 unsigned int lvds_vbt:1;
1459 unsigned int int_crt_support:1;
1460 unsigned int lvds_use_ssc:1;
1461 unsigned int display_clock_mode:1;
1462 unsigned int fdi_rx_polarity_inverted:1;
1463 unsigned int has_mipi:1;
1465 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1467 enum drrs_support_type drrs_type;
1472 int edp_preemphasis;
1474 bool edp_initialized;
1477 struct edp_power_seq edp_pps;
1481 bool require_aux_wakeup;
1483 enum psr_lines_to_wait lines_to_wait;
1484 int tp1_wakeup_time;
1485 int tp2_tp3_wakeup_time;
1491 bool active_low_pwm;
1492 u8 min_brightness; /* min_brightness/255 of max */
1499 struct mipi_config *config;
1500 struct mipi_pps_data *pps;
1504 u8 *sequence[MIPI_SEQ_MAX];
1510 union child_device_config *child_dev;
1512 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1515 enum intel_ddb_partitioning {
1517 INTEL_DDB_PART_5_6, /* IVB+ */
1520 struct intel_wm_level {
1528 struct ilk_wm_values {
1529 uint32_t wm_pipe[3];
1531 uint32_t wm_lp_spr[3];
1532 uint32_t wm_linetime[3];
1534 enum intel_ddb_partitioning partitioning;
1537 struct vlv_pipe_wm {
1548 struct vlv_wm_values {
1549 struct vlv_pipe_wm pipe[3];
1550 struct vlv_sr_wm sr;
1560 struct skl_ddb_entry {
1561 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1564 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1566 return entry->end - entry->start;
1569 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1570 const struct skl_ddb_entry *e2)
1572 if (e1->start == e2->start && e1->end == e2->end)
1578 struct skl_ddb_allocation {
1579 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1580 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1581 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* y-plane */
1582 struct skl_ddb_entry cursor[I915_MAX_PIPES];
1585 struct skl_wm_values {
1586 bool dirty[I915_MAX_PIPES];
1587 struct skl_ddb_allocation ddb;
1588 uint32_t wm_linetime[I915_MAX_PIPES];
1589 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1590 uint32_t cursor[I915_MAX_PIPES][8];
1591 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1592 uint32_t cursor_trans[I915_MAX_PIPES];
1595 struct skl_wm_level {
1596 bool plane_en[I915_MAX_PLANES];
1598 uint16_t plane_res_b[I915_MAX_PLANES];
1599 uint8_t plane_res_l[I915_MAX_PLANES];
1600 uint16_t cursor_res_b;
1601 uint8_t cursor_res_l;
1605 * This struct helps tracking the state needed for runtime PM, which puts the
1606 * device in PCI D3 state. Notice that when this happens, nothing on the
1607 * graphics device works, even register access, so we don't get interrupts nor
1610 * Every piece of our code that needs to actually touch the hardware needs to
1611 * either call intel_runtime_pm_get or call intel_display_power_get with the
1612 * appropriate power domain.
1614 * Our driver uses the autosuspend delay feature, which means we'll only really
1615 * suspend if we stay with zero refcount for a certain amount of time. The
1616 * default value is currently very conservative (see intel_runtime_pm_enable), but
1617 * it can be changed with the standard runtime PM files from sysfs.
1619 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1620 * goes back to false exactly before we reenable the IRQs. We use this variable
1621 * to check if someone is trying to enable/disable IRQs while they're supposed
1622 * to be disabled. This shouldn't happen and we'll print some error messages in
1625 * For more, read the Documentation/power/runtime_pm.txt.
1627 struct i915_runtime_pm {
1632 enum intel_pipe_crc_source {
1633 INTEL_PIPE_CRC_SOURCE_NONE,
1634 INTEL_PIPE_CRC_SOURCE_PLANE1,
1635 INTEL_PIPE_CRC_SOURCE_PLANE2,
1636 INTEL_PIPE_CRC_SOURCE_PF,
1637 INTEL_PIPE_CRC_SOURCE_PIPE,
1638 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1639 INTEL_PIPE_CRC_SOURCE_TV,
1640 INTEL_PIPE_CRC_SOURCE_DP_B,
1641 INTEL_PIPE_CRC_SOURCE_DP_C,
1642 INTEL_PIPE_CRC_SOURCE_DP_D,
1643 INTEL_PIPE_CRC_SOURCE_AUTO,
1644 INTEL_PIPE_CRC_SOURCE_MAX,
1647 struct intel_pipe_crc_entry {
1652 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1653 struct intel_pipe_crc {
1655 bool opened; /* exclusive access to the result file */
1656 struct intel_pipe_crc_entry *entries;
1657 enum intel_pipe_crc_source source;
1659 wait_queue_head_t wq;
1662 struct i915_frontbuffer_tracking {
1666 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1673 struct i915_wa_reg {
1676 /* bitmask representing WA bits */
1680 #define I915_MAX_WA_REGS 16
1682 struct i915_workarounds {
1683 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1687 struct i915_virtual_gpu {
1691 struct i915_execbuffer_params {
1692 struct drm_device *dev;
1693 struct drm_file *file;
1694 uint32_t dispatch_flags;
1695 uint32_t args_batch_start_offset;
1696 uint32_t batch_obj_vm_offset;
1697 struct intel_engine_cs *ring;
1698 struct drm_i915_gem_object *batch_obj;
1699 struct intel_context *ctx;
1700 struct drm_i915_gem_request *request;
1703 struct drm_i915_private {
1704 struct drm_device *dev;
1705 struct kmem_cache *objects;
1706 struct kmem_cache *vmas;
1707 struct kmem_cache *requests;
1709 const struct intel_device_info info;
1711 int relative_constants_mode;
1715 struct intel_uncore uncore;
1717 struct i915_virtual_gpu vgpu;
1719 struct intel_csr csr;
1721 /* Display CSR-related protection */
1722 struct mutex csr_lock;
1724 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1726 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1727 * controller on different i2c buses. */
1728 struct mutex gmbus_mutex;
1731 * Base address of the gmbus and gpio block.
1733 uint32_t gpio_mmio_base;
1735 /* MMIO base address for MIPI regs */
1736 uint32_t mipi_mmio_base;
1738 wait_queue_head_t gmbus_wait_queue;
1740 struct pci_dev *bridge_dev;
1741 struct intel_engine_cs ring[I915_NUM_RINGS];
1742 struct drm_i915_gem_object *semaphore_obj;
1743 uint32_t last_seqno, next_seqno;
1745 struct drm_dma_handle *status_page_dmah;
1746 struct resource mch_res;
1748 /* protects the irq masks */
1749 spinlock_t irq_lock;
1751 /* protects the mmio flip data */
1752 spinlock_t mmio_flip_lock;
1754 bool display_irqs_enabled;
1756 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1757 struct pm_qos_request pm_qos;
1759 /* Sideband mailbox protection */
1760 struct mutex sb_lock;
1762 /** Cached value of IMR to avoid reads in updating the bitfield */
1765 u32 de_irq_mask[I915_MAX_PIPES];
1770 u32 pipestat_irq_mask[I915_MAX_PIPES];
1772 struct i915_hotplug hotplug;
1773 struct i915_fbc fbc;
1774 struct i915_drrs drrs;
1775 struct intel_opregion opregion;
1776 struct intel_vbt_data vbt;
1778 bool preserve_bios_swizzle;
1781 struct intel_overlay *overlay;
1783 /* backlight registers and fields in struct intel_panel */
1784 struct mutex backlight_lock;
1787 bool no_aux_handshake;
1789 /* protects panel power sequencer state */
1790 struct mutex pps_mutex;
1792 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1793 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1794 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1796 unsigned int fsb_freq, mem_freq, is_ddr3;
1797 unsigned int skl_boot_cdclk;
1798 unsigned int cdclk_freq, max_cdclk_freq;
1799 unsigned int hpll_freq;
1802 * wq - Driver workqueue for GEM.
1804 * NOTE: Work items scheduled here are not allowed to grab any modeset
1805 * locks, for otherwise the flushing done in the pageflip code will
1806 * result in deadlocks.
1808 struct workqueue_struct *wq;
1810 /* Display functions */
1811 struct drm_i915_display_funcs display;
1813 /* PCH chipset type */
1814 enum intel_pch pch_type;
1815 unsigned short pch_id;
1817 unsigned long quirks;
1819 enum modeset_restore modeset_restore;
1820 struct mutex modeset_restore_lock;
1822 struct list_head vm_list; /* Global list of all address spaces */
1823 struct i915_gtt gtt; /* VM representing the global address space */
1825 struct i915_gem_mm mm;
1826 DECLARE_HASHTABLE(mm_structs, 7);
1827 struct mutex mm_lock;
1829 /* Kernel Modesetting */
1831 struct sdvo_device_mapping sdvo_mappings[2];
1833 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1834 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1835 wait_queue_head_t pending_flip_queue;
1837 #ifdef CONFIG_DEBUG_FS
1838 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1841 int num_shared_dpll;
1842 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1843 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1845 struct i915_workarounds workarounds;
1847 /* Reclocking support */
1848 bool render_reclock_avail;
1850 struct i915_frontbuffer_tracking fb_tracking;
1854 bool mchbar_need_disable;
1856 struct intel_l3_parity l3_parity;
1858 /* Cannot be determined by PCIID. You must always read a register. */
1861 /* gen6+ rps state */
1862 struct intel_gen6_power_mgmt rps;
1864 /* ilk-only ips/rps state. Everything in here is protected by the global
1865 * mchdev_lock in intel_pm.c */
1866 struct intel_ilk_power_mgmt ips;
1868 struct i915_power_domains power_domains;
1870 struct i915_psr psr;
1872 struct i915_gpu_error gpu_error;
1874 struct drm_i915_gem_object *vlv_pctx;
1876 #ifdef CONFIG_DRM_FBDEV_EMULATION
1877 /* list of fbdev register on this device */
1878 struct intel_fbdev *fbdev;
1879 struct work_struct fbdev_suspend_work;
1882 struct drm_property *broadcast_rgb_property;
1883 struct drm_property *force_audio_property;
1885 /* hda/i915 audio component */
1886 struct i915_audio_component *audio_component;
1887 bool audio_component_registered;
1889 * av_mutex - mutex for audio/video sync
1892 struct mutex av_mutex;
1894 uint32_t hw_context_size;
1895 struct list_head context_list;
1899 u32 chv_phy_control;
1902 struct i915_suspend_saved_registers regfile;
1903 struct vlv_s0ix_state vlv_s0ix_state;
1907 * Raw watermark latency values:
1908 * in 0.1us units for WM0,
1909 * in 0.5us units for WM1+.
1912 uint16_t pri_latency[5];
1914 uint16_t spr_latency[5];
1916 uint16_t cur_latency[5];
1918 * Raw watermark memory latency values
1919 * for SKL for all 8 levels
1922 uint16_t skl_latency[8];
1925 * The skl_wm_values structure is a bit too big for stack
1926 * allocation, so we keep the staging struct where we store
1927 * intermediate results here instead.
1929 struct skl_wm_values skl_results;
1931 /* current hardware state */
1933 struct ilk_wm_values hw;
1934 struct skl_wm_values skl_hw;
1935 struct vlv_wm_values vlv;
1941 struct i915_runtime_pm pm;
1943 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1945 int (*execbuf_submit)(struct i915_execbuffer_params *params,
1946 struct drm_i915_gem_execbuffer2 *args,
1947 struct list_head *vmas);
1948 int (*init_rings)(struct drm_device *dev);
1949 void (*cleanup_ring)(struct intel_engine_cs *ring);
1950 void (*stop_ring)(struct intel_engine_cs *ring);
1953 bool edp_low_vswing;
1956 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1957 * will be rejected. Instead look for a better place.
1961 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1963 return dev->dev_private;
1966 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1968 return to_i915(dev_get_drvdata(dev));
1971 /* Iterate over initialised rings */
1972 #define for_each_ring(ring__, dev_priv__, i__) \
1973 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1974 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1976 enum hdmi_force_audio {
1977 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1978 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1979 HDMI_AUDIO_AUTO, /* trust EDID */
1980 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1983 #define I915_GTT_OFFSET_NONE ((u32)-1)
1985 struct drm_i915_gem_object_ops {
1986 /* Interface between the GEM object and its backing storage.
1987 * get_pages() is called once prior to the use of the associated set
1988 * of pages before to binding them into the GTT, and put_pages() is
1989 * called after we no longer need them. As we expect there to be
1990 * associated cost with migrating pages between the backing storage
1991 * and making them available for the GPU (e.g. clflush), we may hold
1992 * onto the pages after they are no longer referenced by the GPU
1993 * in case they may be used again shortly (for example migrating the
1994 * pages to a different memory domain within the GTT). put_pages()
1995 * will therefore most likely be called when the object itself is
1996 * being released or under memory pressure (where we attempt to
1997 * reap pages for the shrinker).
1999 int (*get_pages)(struct drm_i915_gem_object *);
2000 void (*put_pages)(struct drm_i915_gem_object *);
2001 int (*dmabuf_export)(struct drm_i915_gem_object *);
2002 void (*release)(struct drm_i915_gem_object *);
2006 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2007 * considered to be the frontbuffer for the given plane interface-vise. This
2008 * doesn't mean that the hw necessarily already scans it out, but that any
2009 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2011 * We have one bit per pipe and per scanout plane type.
2013 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
2014 #define INTEL_FRONTBUFFER_BITS \
2015 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2016 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2017 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2018 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2019 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2020 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
2021 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2022 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2023 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2024 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2025 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2027 struct drm_i915_gem_object {
2028 struct drm_gem_object base;
2030 const struct drm_i915_gem_object_ops *ops;
2032 /** List of VMAs backed by this object */
2033 struct list_head vma_list;
2035 /** Stolen memory for this object, instead of being backed by shmem. */
2036 struct drm_mm_node *stolen;
2037 struct list_head global_list;
2039 struct list_head ring_list[I915_NUM_RINGS];
2040 /** Used in execbuf to temporarily hold a ref */
2041 struct list_head obj_exec_link;
2043 struct list_head batch_pool_link;
2046 * This is set if the object is on the active lists (has pending
2047 * rendering and so a non-zero seqno), and is not set if it i s on
2048 * inactive (ready to be unbound) list.
2050 unsigned int active:I915_NUM_RINGS;
2053 * This is set if the object has been written to since last bound
2056 unsigned int dirty:1;
2059 * Fence register bits (if any) for this object. Will be set
2060 * as needed when mapped into the GTT.
2061 * Protected by dev->struct_mutex.
2063 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2066 * Advice: are the backing pages purgeable?
2068 unsigned int madv:2;
2071 * Current tiling mode for the object.
2073 unsigned int tiling_mode:2;
2075 * Whether the tiling parameters for the currently associated fence
2076 * register have changed. Note that for the purposes of tracking
2077 * tiling changes we also treat the unfenced register, the register
2078 * slot that the object occupies whilst it executes a fenced
2079 * command (such as BLT on gen2/3), as a "fence".
2081 unsigned int fence_dirty:1;
2084 * Is the object at the current location in the gtt mappable and
2085 * fenceable? Used to avoid costly recalculations.
2087 unsigned int map_and_fenceable:1;
2090 * Whether the current gtt mapping needs to be mappable (and isn't just
2091 * mappable by accident). Track pin and fault separate for a more
2092 * accurate mappable working set.
2094 unsigned int fault_mappable:1;
2097 * Is the object to be mapped as read-only to the GPU
2098 * Only honoured if hardware has relevant pte bit
2100 unsigned long gt_ro:1;
2101 unsigned int cache_level:3;
2102 unsigned int cache_dirty:1;
2104 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2106 unsigned int pin_display;
2108 struct sg_table *pages;
2109 int pages_pin_count;
2111 struct scatterlist *sg;
2115 /* prime dma-buf support */
2116 void *dma_buf_vmapping;
2119 /** Breadcrumb of last rendering to the buffer.
2120 * There can only be one writer, but we allow for multiple readers.
2121 * If there is a writer that necessarily implies that all other
2122 * read requests are complete - but we may only be lazily clearing
2123 * the read requests. A read request is naturally the most recent
2124 * request on a ring, so we may have two different write and read
2125 * requests on one ring where the write request is older than the
2126 * read request. This allows for the CPU to read from an active
2127 * buffer by only waiting for the write to complete.
2129 struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
2130 struct drm_i915_gem_request *last_write_req;
2131 /** Breadcrumb of last fenced GPU access to the buffer. */
2132 struct drm_i915_gem_request *last_fenced_req;
2134 /** Current tiling stride for the object, if it's tiled. */
2137 /** References from framebuffers, locks out tiling changes. */
2138 unsigned long framebuffer_references;
2140 /** Record of address bit 17 of each page at last unbind. */
2141 unsigned long *bit_17;
2144 /** for phy allocated objects */
2145 struct drm_dma_handle *phys_handle;
2147 struct i915_gem_userptr {
2149 unsigned read_only :1;
2150 unsigned workers :4;
2151 #define I915_GEM_USERPTR_MAX_WORKERS 15
2153 struct i915_mm_struct *mm;
2154 struct i915_mmu_object *mmu_object;
2155 struct work_struct *work;
2159 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2161 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2162 struct drm_i915_gem_object *new,
2163 unsigned frontbuffer_bits);
2166 * Request queue structure.
2168 * The request queue allows us to note sequence numbers that have been emitted
2169 * and may be associated with active buffers to be retired.
2171 * By keeping this list, we can avoid having to do questionable sequence
2172 * number comparisons on buffer last_read|write_seqno. It also allows an
2173 * emission time to be associated with the request for tracking how far ahead
2174 * of the GPU the submission is.
2176 * The requests are reference counted, so upon creation they should have an
2177 * initial reference taken using kref_init
2179 struct drm_i915_gem_request {
2182 /** On Which ring this request was generated */
2183 struct drm_i915_private *i915;
2184 struct intel_engine_cs *ring;
2186 /** GEM sequence number associated with this request. */
2189 /** Position in the ringbuffer of the start of the request */
2193 * Position in the ringbuffer of the start of the postfix.
2194 * This is required to calculate the maximum available ringbuffer
2195 * space without overwriting the postfix.
2199 /** Position in the ringbuffer of the end of the whole request */
2203 * Context and ring buffer related to this request
2204 * Contexts are refcounted, so when this request is associated with a
2205 * context, we must increment the context's refcount, to guarantee that
2206 * it persists while any request is linked to it. Requests themselves
2207 * are also refcounted, so the request will only be freed when the last
2208 * reference to it is dismissed, and the code in
2209 * i915_gem_request_free() will then decrement the refcount on the
2212 struct intel_context *ctx;
2213 struct intel_ringbuffer *ringbuf;
2215 /** Batch buffer related to this request if any (used for
2216 error state dump only) */
2217 struct drm_i915_gem_object *batch_obj;
2219 /** Time at which this request was emitted, in jiffies. */
2220 unsigned long emitted_jiffies;
2222 /** global list entry for this request */
2223 struct list_head list;
2225 struct drm_i915_file_private *file_priv;
2226 /** file_priv list entry for this request */
2227 struct list_head client_list;
2229 /** process identifier submitting this request */
2233 * The ELSP only accepts two elements at a time, so we queue
2234 * context/tail pairs on a given queue (ring->execlist_queue) until the
2235 * hardware is available. The queue serves a double purpose: we also use
2236 * it to keep track of the up to 2 contexts currently in the hardware
2237 * (usually one in execution and the other queued up by the GPU): We
2238 * only remove elements from the head of the queue when the hardware
2239 * informs us that an element has been completed.
2241 * All accesses to the queue are mediated by a spinlock
2242 * (ring->execlist_lock).
2245 /** Execlist link in the submission queue.*/
2246 struct list_head execlist_link;
2248 /** Execlists no. of times this request has been sent to the ELSP */
2253 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2254 struct intel_context *ctx,
2255 struct drm_i915_gem_request **req_out);
2256 void i915_gem_request_cancel(struct drm_i915_gem_request *req);
2257 void i915_gem_request_free(struct kref *req_ref);
2258 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2259 struct drm_file *file);
2261 static inline uint32_t
2262 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2264 return req ? req->seqno : 0;
2267 static inline struct intel_engine_cs *
2268 i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2270 return req ? req->ring : NULL;
2273 static inline struct drm_i915_gem_request *
2274 i915_gem_request_reference(struct drm_i915_gem_request *req)
2277 kref_get(&req->ref);
2282 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2284 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2285 kref_put(&req->ref, i915_gem_request_free);
2289 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2291 struct drm_device *dev;
2296 dev = req->ring->dev;
2297 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2298 mutex_unlock(&dev->struct_mutex);
2301 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2302 struct drm_i915_gem_request *src)
2305 i915_gem_request_reference(src);
2308 i915_gem_request_unreference(*pdst);
2314 * XXX: i915_gem_request_completed should be here but currently needs the
2315 * definition of i915_seqno_passed() which is below. It will be moved in
2316 * a later patch when the call to i915_seqno_passed() is obsoleted...
2320 * A command that requires special handling by the command parser.
2322 struct drm_i915_cmd_descriptor {
2324 * Flags describing how the command parser processes the command.
2326 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2327 * a length mask if not set
2328 * CMD_DESC_SKIP: The command is allowed but does not follow the
2329 * standard length encoding for the opcode range in
2331 * CMD_DESC_REJECT: The command is never allowed
2332 * CMD_DESC_REGISTER: The command should be checked against the
2333 * register whitelist for the appropriate ring
2334 * CMD_DESC_MASTER: The command is allowed if the submitting process
2338 #define CMD_DESC_FIXED (1<<0)
2339 #define CMD_DESC_SKIP (1<<1)
2340 #define CMD_DESC_REJECT (1<<2)
2341 #define CMD_DESC_REGISTER (1<<3)
2342 #define CMD_DESC_BITMASK (1<<4)
2343 #define CMD_DESC_MASTER (1<<5)
2346 * The command's unique identification bits and the bitmask to get them.
2347 * This isn't strictly the opcode field as defined in the spec and may
2348 * also include type, subtype, and/or subop fields.
2356 * The command's length. The command is either fixed length (i.e. does
2357 * not include a length field) or has a length field mask. The flag
2358 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2359 * a length mask. All command entries in a command table must include
2360 * length information.
2368 * Describes where to find a register address in the command to check
2369 * against the ring's register whitelist. Only valid if flags has the
2370 * CMD_DESC_REGISTER bit set.
2372 * A non-zero step value implies that the command may access multiple
2373 * registers in sequence (e.g. LRI), in that case step gives the
2374 * distance in dwords between individual offset fields.
2382 #define MAX_CMD_DESC_BITMASKS 3
2384 * Describes command checks where a particular dword is masked and
2385 * compared against an expected value. If the command does not match
2386 * the expected value, the parser rejects it. Only valid if flags has
2387 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2390 * If the check specifies a non-zero condition_mask then the parser
2391 * only performs the check when the bits specified by condition_mask
2398 u32 condition_offset;
2400 } bits[MAX_CMD_DESC_BITMASKS];
2404 * A table of commands requiring special handling by the command parser.
2406 * Each ring has an array of tables. Each table consists of an array of command
2407 * descriptors, which must be sorted with command opcodes in ascending order.
2409 struct drm_i915_cmd_table {
2410 const struct drm_i915_cmd_descriptor *table;
2414 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2415 #define __I915__(p) ({ \
2416 struct drm_i915_private *__p; \
2417 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2418 __p = (struct drm_i915_private *)p; \
2419 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2420 __p = to_i915((struct drm_device *)p); \
2425 #define INTEL_INFO(p) (&__I915__(p)->info)
2426 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2427 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2429 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2430 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2431 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2432 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2433 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2434 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2435 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2436 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2437 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2438 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2439 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2440 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2441 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2442 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2443 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2444 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2445 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2446 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2447 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2448 INTEL_DEVID(dev) == 0x0152 || \
2449 INTEL_DEVID(dev) == 0x015a)
2450 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2451 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2452 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2453 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2454 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2455 #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
2456 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2457 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2458 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2459 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2460 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2461 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2462 (INTEL_DEVID(dev) & 0xf) == 0xe))
2463 /* ULX machines are also considered ULT. */
2464 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2465 (INTEL_DEVID(dev) & 0xf) == 0xe)
2466 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2467 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2468 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2469 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2470 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2471 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2472 /* ULX machines are also considered ULT. */
2473 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2474 INTEL_DEVID(dev) == 0x0A1E)
2475 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2476 INTEL_DEVID(dev) == 0x1913 || \
2477 INTEL_DEVID(dev) == 0x1916 || \
2478 INTEL_DEVID(dev) == 0x1921 || \
2479 INTEL_DEVID(dev) == 0x1926)
2480 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2481 INTEL_DEVID(dev) == 0x1915 || \
2482 INTEL_DEVID(dev) == 0x191E)
2483 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2485 #define SKL_REVID_A0 (0x0)
2486 #define SKL_REVID_B0 (0x1)
2487 #define SKL_REVID_C0 (0x2)
2488 #define SKL_REVID_D0 (0x3)
2489 #define SKL_REVID_E0 (0x4)
2490 #define SKL_REVID_F0 (0x5)
2492 #define BXT_REVID_A0 (0x0)
2493 #define BXT_REVID_B0 (0x3)
2494 #define BXT_REVID_C0 (0x6)
2497 * The genX designation typically refers to the render engine, so render
2498 * capability related checks should use IS_GEN, while display and other checks
2499 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2502 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2503 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2504 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2505 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2506 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2507 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2508 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2509 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2511 #define RENDER_RING (1<<RCS)
2512 #define BSD_RING (1<<VCS)
2513 #define BLT_RING (1<<BCS)
2514 #define VEBOX_RING (1<<VECS)
2515 #define BSD2_RING (1<<VCS2)
2516 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2517 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2518 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2519 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2520 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2521 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2522 __I915__(dev)->ellc_size)
2523 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2525 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2526 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2527 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2528 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2530 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2531 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2533 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2534 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2536 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2537 * even when in MSI mode. This results in spurious interrupt warnings if the
2538 * legacy irq no. is shared with another device. The kernel then disables that
2539 * interrupt source and so prevents the other device from working properly.
2541 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2542 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2544 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2545 * rows, which changed the alignment requirements and fence programming.
2547 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2549 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2550 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2552 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2553 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2554 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2556 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2558 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2559 INTEL_INFO(dev)->gen >= 9)
2561 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2562 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2563 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2564 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2566 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2567 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2569 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2570 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2572 #define HAS_CSR(dev) (IS_SKYLAKE(dev))
2574 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2575 INTEL_INFO(dev)->gen >= 8)
2577 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2578 !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
2580 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2581 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2582 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2583 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2584 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2585 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2586 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2587 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2589 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2590 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2591 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2592 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2593 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2594 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2595 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2597 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2599 /* DPF == dynamic parity feature */
2600 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2601 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2603 #define GT_FREQUENCY_MULTIPLIER 50
2604 #define GEN9_FREQ_SCALER 3
2606 #include "i915_trace.h"
2608 extern const struct drm_ioctl_desc i915_ioctls[];
2609 extern int i915_max_ioctl;
2611 extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state);
2612 extern int i915_resume_legacy(struct drm_device *dev);
2615 struct i915_params {
2617 int panel_ignore_lid;
2619 int lvds_channel_mode;
2621 int vbt_sdvo_panel_type;
2625 int enable_execlists;
2627 unsigned int preliminary_hw_support;
2628 int disable_power_well;
2630 int invert_brightness;
2631 int enable_cmd_parser;
2632 /* leave bools at the end to not create holes */
2633 bool enable_hangcheck;
2635 bool prefault_disable;
2636 bool load_detect_test;
2638 bool disable_display;
2639 bool disable_vtd_wa;
2640 bool enable_guc_submission;
2644 bool verbose_state_checks;
2647 extern struct i915_params i915 __read_mostly;
2650 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2651 extern int i915_driver_unload(struct drm_device *);
2652 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2653 extern void i915_driver_lastclose(struct drm_device * dev);
2654 extern void i915_driver_preclose(struct drm_device *dev,
2655 struct drm_file *file);
2656 extern void i915_driver_postclose(struct drm_device *dev,
2657 struct drm_file *file);
2658 #ifdef CONFIG_COMPAT
2659 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2662 extern int intel_gpu_reset(struct drm_device *dev);
2663 extern bool intel_has_gpu_reset(struct drm_device *dev);
2664 extern int i915_reset(struct drm_device *dev);
2665 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2666 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2667 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2668 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2669 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2670 void i915_firmware_load_error_print(const char *fw_path, int err);
2672 /* intel_hotplug.c */
2673 void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
2674 void intel_hpd_init(struct drm_i915_private *dev_priv);
2675 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2676 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2677 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2680 void i915_queue_hangcheck(struct drm_device *dev);
2682 void i915_handle_error(struct drm_device *dev, bool wedged,
2683 const char *fmt, ...);
2685 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2686 int intel_irq_install(struct drm_i915_private *dev_priv);
2687 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2689 extern void intel_uncore_sanitize(struct drm_device *dev);
2690 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2691 bool restore_forcewake);
2692 extern void intel_uncore_init(struct drm_device *dev);
2693 extern void intel_uncore_check_errors(struct drm_device *dev);
2694 extern void intel_uncore_fini(struct drm_device *dev);
2695 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2696 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2697 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2698 enum forcewake_domains domains);
2699 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2700 enum forcewake_domains domains);
2701 /* Like above but the caller must manage the uncore.lock itself.
2702 * Must be used with I915_READ_FW and friends.
2704 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2705 enum forcewake_domains domains);
2706 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2707 enum forcewake_domains domains);
2708 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2709 static inline bool intel_vgpu_active(struct drm_device *dev)
2711 return to_i915(dev)->vgpu.active;
2715 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2719 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2722 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2723 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2725 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2727 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2728 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2729 uint32_t interrupt_mask,
2730 uint32_t enabled_irq_mask);
2731 #define ibx_enable_display_interrupt(dev_priv, bits) \
2732 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2733 #define ibx_disable_display_interrupt(dev_priv, bits) \
2734 ibx_display_interrupt_update((dev_priv), (bits), 0)
2737 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2738 struct drm_file *file_priv);
2739 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2740 struct drm_file *file_priv);
2741 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2742 struct drm_file *file_priv);
2743 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2744 struct drm_file *file_priv);
2745 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2746 struct drm_file *file_priv);
2747 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2748 struct drm_file *file_priv);
2749 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2750 struct drm_file *file_priv);
2751 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2752 struct drm_i915_gem_request *req);
2753 void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
2754 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
2755 struct drm_i915_gem_execbuffer2 *args,
2756 struct list_head *vmas);
2757 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2758 struct drm_file *file_priv);
2759 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2760 struct drm_file *file_priv);
2761 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2762 struct drm_file *file_priv);
2763 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2764 struct drm_file *file);
2765 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2766 struct drm_file *file);
2767 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2768 struct drm_file *file_priv);
2769 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2770 struct drm_file *file_priv);
2771 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2772 struct drm_file *file_priv);
2773 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2774 struct drm_file *file_priv);
2775 int i915_gem_init_userptr(struct drm_device *dev);
2776 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2777 struct drm_file *file);
2778 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2779 struct drm_file *file_priv);
2780 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2781 struct drm_file *file_priv);
2782 void i915_gem_load(struct drm_device *dev);
2783 void *i915_gem_object_alloc(struct drm_device *dev);
2784 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2785 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2786 const struct drm_i915_gem_object_ops *ops);
2787 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2789 struct drm_i915_gem_object *i915_gem_object_create_from_data(
2790 struct drm_device *dev, const void *data, size_t size);
2791 void i915_init_vm(struct drm_i915_private *dev_priv,
2792 struct i915_address_space *vm);
2793 void i915_gem_free_object(struct drm_gem_object *obj);
2794 void i915_gem_vma_destroy(struct i915_vma *vma);
2796 /* Flags used by pin/bind&friends. */
2797 #define PIN_MAPPABLE (1<<0)
2798 #define PIN_NONBLOCK (1<<1)
2799 #define PIN_GLOBAL (1<<2)
2800 #define PIN_OFFSET_BIAS (1<<3)
2801 #define PIN_USER (1<<4)
2802 #define PIN_UPDATE (1<<5)
2803 #define PIN_OFFSET_MASK (~4095)
2805 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2806 struct i915_address_space *vm,
2810 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2811 const struct i915_ggtt_view *view,
2815 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2817 int __must_check i915_vma_unbind(struct i915_vma *vma);
2818 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2819 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2820 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2822 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2823 int *needs_clflush);
2825 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2827 static inline int __sg_page_count(struct scatterlist *sg)
2829 return sg->length >> PAGE_SHIFT;
2832 static inline struct page *
2833 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2835 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2838 if (n < obj->get_page.last) {
2839 obj->get_page.sg = obj->pages->sgl;
2840 obj->get_page.last = 0;
2843 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2844 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2845 if (unlikely(sg_is_chain(obj->get_page.sg)))
2846 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2849 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2852 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2854 BUG_ON(obj->pages == NULL);
2855 obj->pages_pin_count++;
2857 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2859 BUG_ON(obj->pages_pin_count == 0);
2860 obj->pages_pin_count--;
2863 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2864 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2865 struct intel_engine_cs *to,
2866 struct drm_i915_gem_request **to_req);
2867 void i915_vma_move_to_active(struct i915_vma *vma,
2868 struct drm_i915_gem_request *req);
2869 int i915_gem_dumb_create(struct drm_file *file_priv,
2870 struct drm_device *dev,
2871 struct drm_mode_create_dumb *args);
2872 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2873 uint32_t handle, uint64_t *offset);
2875 * Returns true if seq1 is later than seq2.
2878 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2880 return (int32_t)(seq1 - seq2) >= 0;
2883 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2884 bool lazy_coherency)
2888 BUG_ON(req == NULL);
2890 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2892 return i915_seqno_passed(seqno, req->seqno);
2895 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2896 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2898 struct drm_i915_gem_request *
2899 i915_gem_find_active_request(struct intel_engine_cs *ring);
2901 bool i915_gem_retire_requests(struct drm_device *dev);
2902 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2903 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2904 bool interruptible);
2906 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2908 return unlikely(atomic_read(&error->reset_counter)
2909 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2912 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2914 return atomic_read(&error->reset_counter) & I915_WEDGED;
2917 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2919 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2922 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2924 return dev_priv->gpu_error.stop_rings == 0 ||
2925 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2928 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2930 return dev_priv->gpu_error.stop_rings == 0 ||
2931 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2934 void i915_gem_reset(struct drm_device *dev);
2935 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2936 int __must_check i915_gem_init(struct drm_device *dev);
2937 int i915_gem_init_rings(struct drm_device *dev);
2938 int __must_check i915_gem_init_hw(struct drm_device *dev);
2939 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
2940 void i915_gem_init_swizzling(struct drm_device *dev);
2941 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2942 int __must_check i915_gpu_idle(struct drm_device *dev);
2943 int __must_check i915_gem_suspend(struct drm_device *dev);
2944 void __i915_add_request(struct drm_i915_gem_request *req,
2945 struct drm_i915_gem_object *batch_obj,
2947 #define i915_add_request(req) \
2948 __i915_add_request(req, NULL, true)
2949 #define i915_add_request_no_flush(req) \
2950 __i915_add_request(req, NULL, false)
2951 int __i915_wait_request(struct drm_i915_gem_request *req,
2952 unsigned reset_counter,
2955 struct intel_rps_client *rps);
2956 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
2957 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2959 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
2962 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2965 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2967 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2969 struct intel_engine_cs *pipelined,
2970 struct drm_i915_gem_request **pipelined_request,
2971 const struct i915_ggtt_view *view);
2972 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
2973 const struct i915_ggtt_view *view);
2974 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2976 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2977 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2980 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2982 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2983 int tiling_mode, bool fenced);
2985 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2986 enum i915_cache_level cache_level);
2988 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2989 struct dma_buf *dma_buf);
2991 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2992 struct drm_gem_object *gem_obj, int flags);
2995 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
2996 const struct i915_ggtt_view *view);
2998 i915_gem_obj_offset(struct drm_i915_gem_object *o,
2999 struct i915_address_space *vm);
3000 static inline unsigned long
3001 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3003 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3006 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3007 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3008 const struct i915_ggtt_view *view);
3009 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3010 struct i915_address_space *vm);
3012 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
3013 struct i915_address_space *vm);
3015 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3016 struct i915_address_space *vm);
3018 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3019 const struct i915_ggtt_view *view);
3022 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3023 struct i915_address_space *vm);
3025 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3026 const struct i915_ggtt_view *view);
3028 static inline struct i915_vma *
3029 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3031 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
3033 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3035 /* Some GGTT VM helpers */
3036 #define i915_obj_to_ggtt(obj) \
3037 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
3038 static inline bool i915_is_ggtt(struct i915_address_space *vm)
3040 struct i915_address_space *ggtt =
3041 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
3045 static inline struct i915_hw_ppgtt *
3046 i915_vm_to_ppgtt(struct i915_address_space *vm)
3048 WARN_ON(i915_is_ggtt(vm));
3050 return container_of(vm, struct i915_hw_ppgtt, base);
3054 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3056 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3059 static inline unsigned long
3060 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
3062 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
3065 static inline int __must_check
3066 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3070 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
3071 alignment, flags | PIN_GLOBAL);
3075 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
3077 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
3080 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3081 const struct i915_ggtt_view *view);
3083 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3085 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3088 /* i915_gem_fence.c */
3089 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3090 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3092 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3093 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3095 void i915_gem_restore_fences(struct drm_device *dev);
3097 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3098 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3099 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3101 /* i915_gem_context.c */
3102 int __must_check i915_gem_context_init(struct drm_device *dev);
3103 void i915_gem_context_fini(struct drm_device *dev);
3104 void i915_gem_context_reset(struct drm_device *dev);
3105 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3106 int i915_gem_context_enable(struct drm_i915_gem_request *req);
3107 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3108 int i915_switch_context(struct drm_i915_gem_request *req);
3109 struct intel_context *
3110 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3111 void i915_gem_context_free(struct kref *ctx_ref);
3112 struct drm_i915_gem_object *
3113 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3114 static inline void i915_gem_context_reference(struct intel_context *ctx)
3116 kref_get(&ctx->ref);
3119 static inline void i915_gem_context_unreference(struct intel_context *ctx)
3121 kref_put(&ctx->ref, i915_gem_context_free);
3124 static inline bool i915_gem_context_is_default(const struct intel_context *c)
3126 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3129 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3130 struct drm_file *file);
3131 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3132 struct drm_file *file);
3133 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3134 struct drm_file *file_priv);
3135 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3136 struct drm_file *file_priv);
3138 /* i915_gem_evict.c */
3139 int __must_check i915_gem_evict_something(struct drm_device *dev,
3140 struct i915_address_space *vm,
3143 unsigned cache_level,
3144 unsigned long start,
3147 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3148 int i915_gem_evict_everything(struct drm_device *dev);
3150 /* belongs in i915_gem_gtt.h */
3151 static inline void i915_gem_chipset_flush(struct drm_device *dev)
3153 if (INTEL_INFO(dev)->gen < 6)
3154 intel_gtt_chipset_flush();
3157 /* i915_gem_stolen.c */
3158 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3159 struct drm_mm_node *node, u64 size,
3160 unsigned alignment);
3161 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3162 struct drm_mm_node *node);
3163 int i915_gem_init_stolen(struct drm_device *dev);
3164 void i915_gem_cleanup_stolen(struct drm_device *dev);
3165 struct drm_i915_gem_object *
3166 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3167 struct drm_i915_gem_object *
3168 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3173 /* i915_gem_shrinker.c */
3174 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3177 #define I915_SHRINK_PURGEABLE 0x1
3178 #define I915_SHRINK_UNBOUND 0x2
3179 #define I915_SHRINK_BOUND 0x4
3180 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3181 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3184 /* i915_gem_tiling.c */
3185 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3187 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3189 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3190 obj->tiling_mode != I915_TILING_NONE;
3193 /* i915_gem_debug.c */
3195 int i915_verify_lists(struct drm_device *dev);
3197 #define i915_verify_lists(dev) 0
3200 /* i915_debugfs.c */
3201 int i915_debugfs_init(struct drm_minor *minor);
3202 void i915_debugfs_cleanup(struct drm_minor *minor);
3203 #ifdef CONFIG_DEBUG_FS
3204 int i915_debugfs_connector_add(struct drm_connector *connector);
3205 void intel_display_crc_init(struct drm_device *dev);
3207 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3209 static inline void intel_display_crc_init(struct drm_device *dev) {}
3212 /* i915_gpu_error.c */
3214 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3215 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3216 const struct i915_error_state_file_priv *error);
3217 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3218 struct drm_i915_private *i915,
3219 size_t count, loff_t pos);
3220 static inline void i915_error_state_buf_release(
3221 struct drm_i915_error_state_buf *eb)
3225 void i915_capture_error_state(struct drm_device *dev, bool wedge,
3226 const char *error_msg);
3227 void i915_error_state_get(struct drm_device *dev,
3228 struct i915_error_state_file_priv *error_priv);
3229 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3230 void i915_destroy_error_state(struct drm_device *dev);
3232 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3233 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3235 /* i915_cmd_parser.c */
3236 int i915_cmd_parser_get_version(void);
3237 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3238 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3239 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3240 int i915_parse_cmds(struct intel_engine_cs *ring,
3241 struct drm_i915_gem_object *batch_obj,
3242 struct drm_i915_gem_object *shadow_batch_obj,
3243 u32 batch_start_offset,
3247 /* i915_suspend.c */
3248 extern int i915_save_state(struct drm_device *dev);
3249 extern int i915_restore_state(struct drm_device *dev);
3252 void i915_setup_sysfs(struct drm_device *dev_priv);
3253 void i915_teardown_sysfs(struct drm_device *dev_priv);
3256 extern int intel_setup_gmbus(struct drm_device *dev);
3257 extern void intel_teardown_gmbus(struct drm_device *dev);
3258 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3261 extern struct i2c_adapter *
3262 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3263 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3264 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3265 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3267 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3269 extern void intel_i2c_reset(struct drm_device *dev);
3271 /* intel_opregion.c */
3273 extern int intel_opregion_setup(struct drm_device *dev);
3274 extern void intel_opregion_init(struct drm_device *dev);
3275 extern void intel_opregion_fini(struct drm_device *dev);
3276 extern void intel_opregion_asle_intr(struct drm_device *dev);
3277 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3279 extern int intel_opregion_notify_adapter(struct drm_device *dev,
3282 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3283 static inline void intel_opregion_init(struct drm_device *dev) { return; }
3284 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3285 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3287 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3292 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3300 extern void intel_register_dsm_handler(void);
3301 extern void intel_unregister_dsm_handler(void);
3303 static inline void intel_register_dsm_handler(void) { return; }
3304 static inline void intel_unregister_dsm_handler(void) { return; }
3305 #endif /* CONFIG_ACPI */
3308 extern void intel_modeset_init_hw(struct drm_device *dev);
3309 extern void intel_modeset_init(struct drm_device *dev);
3310 extern void intel_modeset_gem_init(struct drm_device *dev);
3311 extern void intel_modeset_cleanup(struct drm_device *dev);
3312 extern void intel_connector_unregister(struct intel_connector *);
3313 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3314 extern void intel_display_resume(struct drm_device *dev);
3315 extern void i915_redisable_vga(struct drm_device *dev);
3316 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3317 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3318 extern void intel_init_pch_refclk(struct drm_device *dev);
3319 extern void intel_set_rps(struct drm_device *dev, u8 val);
3320 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3322 extern void intel_detect_pch(struct drm_device *dev);
3323 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
3324 extern int intel_enable_rc6(const struct drm_device *dev);
3326 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3327 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3328 struct drm_file *file);
3329 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3330 struct drm_file *file);
3333 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3334 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3335 struct intel_overlay_error_state *error);
3337 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3338 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3339 struct drm_device *dev,
3340 struct intel_display_error_state *error);
3342 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3343 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3345 /* intel_sideband.c */
3346 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3347 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3348 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3349 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3350 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3351 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3352 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3353 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3354 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3355 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3356 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3357 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3358 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3359 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3360 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3361 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3362 enum intel_sbi_destination destination);
3363 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3364 enum intel_sbi_destination destination);
3365 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3366 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3368 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3369 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3371 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3372 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3374 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3375 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3376 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3377 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3379 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3380 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3381 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3382 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3384 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3385 * will be implemented using 2 32-bit writes in an arbitrary order with
3386 * an arbitrary delay between them. This can cause the hardware to
3387 * act upon the intermediate value, possibly leading to corruption and
3388 * machine death. You have been warned.
3390 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3391 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3393 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3394 u32 upper, lower, old_upper, loop = 0; \
3395 upper = I915_READ(upper_reg); \
3397 old_upper = upper; \
3398 lower = I915_READ(lower_reg); \
3399 upper = I915_READ(upper_reg); \
3400 } while (upper != old_upper && loop++ < 2); \
3401 (u64)upper << 32 | lower; })
3403 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3404 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3406 /* These are untraced mmio-accessors that are only valid to be used inside
3407 * criticial sections inside IRQ handlers where forcewake is explicitly
3409 * Think twice, and think again, before using these.
3410 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3411 * intel_uncore_forcewake_irqunlock().
3413 #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
3414 #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
3415 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3417 /* "Broadcast RGB" property */
3418 #define INTEL_BROADCAST_RGB_AUTO 0
3419 #define INTEL_BROADCAST_RGB_FULL 1
3420 #define INTEL_BROADCAST_RGB_LIMITED 2
3422 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
3424 if (IS_VALLEYVIEW(dev))
3425 return VLV_VGACNTRL;
3426 else if (INTEL_INFO(dev)->gen >= 5)
3427 return CPU_VGACNTRL;
3432 static inline void __user *to_user_ptr(u64 address)
3434 return (void __user *)(uintptr_t)address;
3437 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3439 unsigned long j = msecs_to_jiffies(m);
3441 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3444 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3446 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3449 static inline unsigned long
3450 timespec_to_jiffies_timeout(const struct timespec *value)
3452 unsigned long j = timespec_to_jiffies(value);
3454 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3458 * If you need to wait X milliseconds between events A and B, but event B
3459 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3460 * when event A happened, then just before event B you call this function and
3461 * pass the timestamp as the first argument, and X as the second argument.
3464 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3466 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3469 * Don't re-read the value of "jiffies" every time since it may change
3470 * behind our back and break the math.
3472 tmp_jiffies = jiffies;
3473 target_jiffies = timestamp_jiffies +
3474 msecs_to_jiffies_timeout(to_wait_ms);
3476 if (time_after(target_jiffies, tmp_jiffies)) {
3477 remaining_jiffies = target_jiffies - tmp_jiffies;
3478 while (remaining_jiffies)
3480 schedule_timeout_uninterruptible(remaining_jiffies);
3484 static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3485 struct drm_i915_gem_request *req)
3487 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3488 i915_gem_request_assign(&ring->trace_irq_req, req);