2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
66 static const uint32_t skl_primary_formats[] = {
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
82 static const uint32_t intel_cursor_formats[] = {
86 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
89 struct intel_crtc_state *pipe_config);
90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
91 struct intel_crtc_state *pipe_config);
93 static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
100 struct intel_link_m_n *m_n,
101 struct intel_link_m_n *m2_n2);
102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
105 static void vlv_prepare_pll(struct intel_crtc *crtc,
106 const struct intel_crtc_state *pipe_config);
107 static void chv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
126 int p2_slow, p2_fast;
129 typedef struct intel_limit intel_limit_t;
131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
135 /* returns HPLL frequency in kHz */
136 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
138 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
140 /* Obtain SKU information */
141 mutex_lock(&dev_priv->sb_lock);
142 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
143 CCK_FUSE_HPLL_FREQ_MASK;
144 mutex_unlock(&dev_priv->sb_lock);
146 return vco_freq[hpll_freq] * 1000;
149 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
150 const char *name, u32 reg)
155 if (dev_priv->hpll_freq == 0)
156 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
158 mutex_lock(&dev_priv->sb_lock);
159 val = vlv_cck_read(dev_priv, reg);
160 mutex_unlock(&dev_priv->sb_lock);
162 divider = val & CCK_FREQUENCY_VALUES;
164 WARN((val & CCK_FREQUENCY_STATUS) !=
165 (divider << CCK_FREQUENCY_STATUS_SHIFT),
166 "%s change in progress\n", name);
168 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
172 intel_pch_rawclk(struct drm_device *dev)
174 struct drm_i915_private *dev_priv = dev->dev_private;
176 WARN_ON(!HAS_PCH_SPLIT(dev));
178 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
181 /* hrawclock is 1/4 the FSB frequency */
182 int intel_hrawclk(struct drm_device *dev)
184 struct drm_i915_private *dev_priv = dev->dev_private;
187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev))
191 clkcfg = I915_READ(CLKCFG);
192 switch (clkcfg & CLKCFG_FSB_MASK) {
201 case CLKCFG_FSB_1067:
203 case CLKCFG_FSB_1333:
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600:
207 case CLKCFG_FSB_1600_ALT:
214 static void intel_update_czclk(struct drm_i915_private *dev_priv)
216 if (!IS_VALLEYVIEW(dev_priv))
219 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
220 CCK_CZ_CLOCK_CONTROL);
222 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
225 static inline u32 /* units of 100MHz */
226 intel_fdi_link_freq(struct drm_device *dev)
229 struct drm_i915_private *dev_priv = dev->dev_private;
230 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
235 static const intel_limit_t intel_limits_i8xx_dac = {
236 .dot = { .min = 25000, .max = 350000 },
237 .vco = { .min = 908000, .max = 1512000 },
238 .n = { .min = 2, .max = 16 },
239 .m = { .min = 96, .max = 140 },
240 .m1 = { .min = 18, .max = 26 },
241 .m2 = { .min = 6, .max = 16 },
242 .p = { .min = 4, .max = 128 },
243 .p1 = { .min = 2, .max = 33 },
244 .p2 = { .dot_limit = 165000,
245 .p2_slow = 4, .p2_fast = 2 },
248 static const intel_limit_t intel_limits_i8xx_dvo = {
249 .dot = { .min = 25000, .max = 350000 },
250 .vco = { .min = 908000, .max = 1512000 },
251 .n = { .min = 2, .max = 16 },
252 .m = { .min = 96, .max = 140 },
253 .m1 = { .min = 18, .max = 26 },
254 .m2 = { .min = 6, .max = 16 },
255 .p = { .min = 4, .max = 128 },
256 .p1 = { .min = 2, .max = 33 },
257 .p2 = { .dot_limit = 165000,
258 .p2_slow = 4, .p2_fast = 4 },
261 static const intel_limit_t intel_limits_i8xx_lvds = {
262 .dot = { .min = 25000, .max = 350000 },
263 .vco = { .min = 908000, .max = 1512000 },
264 .n = { .min = 2, .max = 16 },
265 .m = { .min = 96, .max = 140 },
266 .m1 = { .min = 18, .max = 26 },
267 .m2 = { .min = 6, .max = 16 },
268 .p = { .min = 4, .max = 128 },
269 .p1 = { .min = 1, .max = 6 },
270 .p2 = { .dot_limit = 165000,
271 .p2_slow = 14, .p2_fast = 7 },
274 static const intel_limit_t intel_limits_i9xx_sdvo = {
275 .dot = { .min = 20000, .max = 400000 },
276 .vco = { .min = 1400000, .max = 2800000 },
277 .n = { .min = 1, .max = 6 },
278 .m = { .min = 70, .max = 120 },
279 .m1 = { .min = 8, .max = 18 },
280 .m2 = { .min = 3, .max = 7 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
283 .p2 = { .dot_limit = 200000,
284 .p2_slow = 10, .p2_fast = 5 },
287 static const intel_limit_t intel_limits_i9xx_lvds = {
288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1400000, .max = 2800000 },
290 .n = { .min = 1, .max = 6 },
291 .m = { .min = 70, .max = 120 },
292 .m1 = { .min = 8, .max = 18 },
293 .m2 = { .min = 3, .max = 7 },
294 .p = { .min = 7, .max = 98 },
295 .p1 = { .min = 1, .max = 8 },
296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 7 },
301 static const intel_limit_t intel_limits_g4x_sdvo = {
302 .dot = { .min = 25000, .max = 270000 },
303 .vco = { .min = 1750000, .max = 3500000},
304 .n = { .min = 1, .max = 4 },
305 .m = { .min = 104, .max = 138 },
306 .m1 = { .min = 17, .max = 23 },
307 .m2 = { .min = 5, .max = 11 },
308 .p = { .min = 10, .max = 30 },
309 .p1 = { .min = 1, .max = 3},
310 .p2 = { .dot_limit = 270000,
316 static const intel_limit_t intel_limits_g4x_hdmi = {
317 .dot = { .min = 22000, .max = 400000 },
318 .vco = { .min = 1750000, .max = 3500000},
319 .n = { .min = 1, .max = 4 },
320 .m = { .min = 104, .max = 138 },
321 .m1 = { .min = 16, .max = 23 },
322 .m2 = { .min = 5, .max = 11 },
323 .p = { .min = 5, .max = 80 },
324 .p1 = { .min = 1, .max = 8},
325 .p2 = { .dot_limit = 165000,
326 .p2_slow = 10, .p2_fast = 5 },
329 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
330 .dot = { .min = 20000, .max = 115000 },
331 .vco = { .min = 1750000, .max = 3500000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 28, .max = 112 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 0,
339 .p2_slow = 14, .p2_fast = 14
343 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
344 .dot = { .min = 80000, .max = 224000 },
345 .vco = { .min = 1750000, .max = 3500000 },
346 .n = { .min = 1, .max = 3 },
347 .m = { .min = 104, .max = 138 },
348 .m1 = { .min = 17, .max = 23 },
349 .m2 = { .min = 5, .max = 11 },
350 .p = { .min = 14, .max = 42 },
351 .p1 = { .min = 2, .max = 6 },
352 .p2 = { .dot_limit = 0,
353 .p2_slow = 7, .p2_fast = 7
357 static const intel_limit_t intel_limits_pineview_sdvo = {
358 .dot = { .min = 20000, .max = 400000},
359 .vco = { .min = 1700000, .max = 3500000 },
360 /* Pineview's Ncounter is a ring counter */
361 .n = { .min = 3, .max = 6 },
362 .m = { .min = 2, .max = 256 },
363 /* Pineview only has one combined m divider, which we treat as m2. */
364 .m1 = { .min = 0, .max = 0 },
365 .m2 = { .min = 0, .max = 254 },
366 .p = { .min = 5, .max = 80 },
367 .p1 = { .min = 1, .max = 8 },
368 .p2 = { .dot_limit = 200000,
369 .p2_slow = 10, .p2_fast = 5 },
372 static const intel_limit_t intel_limits_pineview_lvds = {
373 .dot = { .min = 20000, .max = 400000 },
374 .vco = { .min = 1700000, .max = 3500000 },
375 .n = { .min = 3, .max = 6 },
376 .m = { .min = 2, .max = 256 },
377 .m1 = { .min = 0, .max = 0 },
378 .m2 = { .min = 0, .max = 254 },
379 .p = { .min = 7, .max = 112 },
380 .p1 = { .min = 1, .max = 8 },
381 .p2 = { .dot_limit = 112000,
382 .p2_slow = 14, .p2_fast = 14 },
385 /* Ironlake / Sandybridge
387 * We calculate clock using (register_value + 2) for N/M1/M2, so here
388 * the range value for them is (actual_value - 2).
390 static const intel_limit_t intel_limits_ironlake_dac = {
391 .dot = { .min = 25000, .max = 350000 },
392 .vco = { .min = 1760000, .max = 3510000 },
393 .n = { .min = 1, .max = 5 },
394 .m = { .min = 79, .max = 127 },
395 .m1 = { .min = 12, .max = 22 },
396 .m2 = { .min = 5, .max = 9 },
397 .p = { .min = 5, .max = 80 },
398 .p1 = { .min = 1, .max = 8 },
399 .p2 = { .dot_limit = 225000,
400 .p2_slow = 10, .p2_fast = 5 },
403 static const intel_limit_t intel_limits_ironlake_single_lvds = {
404 .dot = { .min = 25000, .max = 350000 },
405 .vco = { .min = 1760000, .max = 3510000 },
406 .n = { .min = 1, .max = 3 },
407 .m = { .min = 79, .max = 118 },
408 .m1 = { .min = 12, .max = 22 },
409 .m2 = { .min = 5, .max = 9 },
410 .p = { .min = 28, .max = 112 },
411 .p1 = { .min = 2, .max = 8 },
412 .p2 = { .dot_limit = 225000,
413 .p2_slow = 14, .p2_fast = 14 },
416 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
417 .dot = { .min = 25000, .max = 350000 },
418 .vco = { .min = 1760000, .max = 3510000 },
419 .n = { .min = 1, .max = 3 },
420 .m = { .min = 79, .max = 127 },
421 .m1 = { .min = 12, .max = 22 },
422 .m2 = { .min = 5, .max = 9 },
423 .p = { .min = 14, .max = 56 },
424 .p1 = { .min = 2, .max = 8 },
425 .p2 = { .dot_limit = 225000,
426 .p2_slow = 7, .p2_fast = 7 },
429 /* LVDS 100mhz refclk limits. */
430 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
431 .dot = { .min = 25000, .max = 350000 },
432 .vco = { .min = 1760000, .max = 3510000 },
433 .n = { .min = 1, .max = 2 },
434 .m = { .min = 79, .max = 126 },
435 .m1 = { .min = 12, .max = 22 },
436 .m2 = { .min = 5, .max = 9 },
437 .p = { .min = 28, .max = 112 },
438 .p1 = { .min = 2, .max = 8 },
439 .p2 = { .dot_limit = 225000,
440 .p2_slow = 14, .p2_fast = 14 },
443 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
444 .dot = { .min = 25000, .max = 350000 },
445 .vco = { .min = 1760000, .max = 3510000 },
446 .n = { .min = 1, .max = 3 },
447 .m = { .min = 79, .max = 126 },
448 .m1 = { .min = 12, .max = 22 },
449 .m2 = { .min = 5, .max = 9 },
450 .p = { .min = 14, .max = 42 },
451 .p1 = { .min = 2, .max = 6 },
452 .p2 = { .dot_limit = 225000,
453 .p2_slow = 7, .p2_fast = 7 },
456 static const intel_limit_t intel_limits_vlv = {
458 * These are the data rate limits (measured in fast clocks)
459 * since those are the strictest limits we have. The fast
460 * clock and actual rate limits are more relaxed, so checking
461 * them would make no difference.
463 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
464 .vco = { .min = 4000000, .max = 6000000 },
465 .n = { .min = 1, .max = 7 },
466 .m1 = { .min = 2, .max = 3 },
467 .m2 = { .min = 11, .max = 156 },
468 .p1 = { .min = 2, .max = 3 },
469 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
472 static const intel_limit_t intel_limits_chv = {
474 * These are the data rate limits (measured in fast clocks)
475 * since those are the strictest limits we have. The fast
476 * clock and actual rate limits are more relaxed, so checking
477 * them would make no difference.
479 .dot = { .min = 25000 * 5, .max = 540000 * 5},
480 .vco = { .min = 4800000, .max = 6480000 },
481 .n = { .min = 1, .max = 1 },
482 .m1 = { .min = 2, .max = 2 },
483 .m2 = { .min = 24 << 22, .max = 175 << 22 },
484 .p1 = { .min = 2, .max = 4 },
485 .p2 = { .p2_slow = 1, .p2_fast = 14 },
488 static const intel_limit_t intel_limits_bxt = {
489 /* FIXME: find real dot limits */
490 .dot = { .min = 0, .max = INT_MAX },
491 .vco = { .min = 4800000, .max = 6700000 },
492 .n = { .min = 1, .max = 1 },
493 .m1 = { .min = 2, .max = 2 },
494 /* FIXME: find real m2 limits */
495 .m2 = { .min = 2 << 22, .max = 255 << 22 },
496 .p1 = { .min = 2, .max = 4 },
497 .p2 = { .p2_slow = 1, .p2_fast = 20 },
501 needs_modeset(struct drm_crtc_state *state)
503 return drm_atomic_crtc_needs_modeset(state);
507 * Returns whether any output on the specified pipe is of the specified type
509 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
511 struct drm_device *dev = crtc->base.dev;
512 struct intel_encoder *encoder;
514 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
515 if (encoder->type == type)
522 * Returns whether any output on the specified pipe will have the specified
523 * type after a staged modeset is complete, i.e., the same as
524 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
527 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
530 struct drm_atomic_state *state = crtc_state->base.state;
531 struct drm_connector *connector;
532 struct drm_connector_state *connector_state;
533 struct intel_encoder *encoder;
534 int i, num_connectors = 0;
536 for_each_connector_in_state(state, connector, connector_state, i) {
537 if (connector_state->crtc != crtc_state->base.crtc)
542 encoder = to_intel_encoder(connector_state->best_encoder);
543 if (encoder->type == type)
547 WARN_ON(num_connectors == 0);
552 static const intel_limit_t *
553 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
555 struct drm_device *dev = crtc_state->base.crtc->dev;
556 const intel_limit_t *limit;
558 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
559 if (intel_is_dual_link_lvds(dev)) {
560 if (refclk == 100000)
561 limit = &intel_limits_ironlake_dual_lvds_100m;
563 limit = &intel_limits_ironlake_dual_lvds;
565 if (refclk == 100000)
566 limit = &intel_limits_ironlake_single_lvds_100m;
568 limit = &intel_limits_ironlake_single_lvds;
571 limit = &intel_limits_ironlake_dac;
576 static const intel_limit_t *
577 intel_g4x_limit(struct intel_crtc_state *crtc_state)
579 struct drm_device *dev = crtc_state->base.crtc->dev;
580 const intel_limit_t *limit;
582 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
583 if (intel_is_dual_link_lvds(dev))
584 limit = &intel_limits_g4x_dual_channel_lvds;
586 limit = &intel_limits_g4x_single_channel_lvds;
587 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
588 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
589 limit = &intel_limits_g4x_hdmi;
590 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
591 limit = &intel_limits_g4x_sdvo;
592 } else /* The option is for other outputs */
593 limit = &intel_limits_i9xx_sdvo;
598 static const intel_limit_t *
599 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
601 struct drm_device *dev = crtc_state->base.crtc->dev;
602 const intel_limit_t *limit;
605 limit = &intel_limits_bxt;
606 else if (HAS_PCH_SPLIT(dev))
607 limit = intel_ironlake_limit(crtc_state, refclk);
608 else if (IS_G4X(dev)) {
609 limit = intel_g4x_limit(crtc_state);
610 } else if (IS_PINEVIEW(dev)) {
611 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
612 limit = &intel_limits_pineview_lvds;
614 limit = &intel_limits_pineview_sdvo;
615 } else if (IS_CHERRYVIEW(dev)) {
616 limit = &intel_limits_chv;
617 } else if (IS_VALLEYVIEW(dev)) {
618 limit = &intel_limits_vlv;
619 } else if (!IS_GEN2(dev)) {
620 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
621 limit = &intel_limits_i9xx_lvds;
623 limit = &intel_limits_i9xx_sdvo;
625 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
626 limit = &intel_limits_i8xx_lvds;
627 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
628 limit = &intel_limits_i8xx_dvo;
630 limit = &intel_limits_i8xx_dac;
636 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
637 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
638 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
639 * The helpers' return value is the rate of the clock that is fed to the
640 * display engine's pipe which can be the above fast dot clock rate or a
641 * divided-down version of it.
643 /* m1 is reserved as 0 in Pineview, n is a ring counter */
644 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
646 clock->m = clock->m2 + 2;
647 clock->p = clock->p1 * clock->p2;
648 if (WARN_ON(clock->n == 0 || clock->p == 0))
650 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
651 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
656 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
658 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
661 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
663 clock->m = i9xx_dpll_compute_m(clock);
664 clock->p = clock->p1 * clock->p2;
665 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
667 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
668 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
673 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
675 clock->m = clock->m1 * clock->m2;
676 clock->p = clock->p1 * clock->p2;
677 if (WARN_ON(clock->n == 0 || clock->p == 0))
679 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
680 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
682 return clock->dot / 5;
685 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
687 clock->m = clock->m1 * clock->m2;
688 clock->p = clock->p1 * clock->p2;
689 if (WARN_ON(clock->n == 0 || clock->p == 0))
691 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
693 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
695 return clock->dot / 5;
698 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
700 * Returns whether the given set of divisors are valid for a given refclk with
701 * the given connectors.
704 static bool intel_PLL_is_valid(struct drm_device *dev,
705 const intel_limit_t *limit,
706 const intel_clock_t *clock)
708 if (clock->n < limit->n.min || limit->n.max < clock->n)
709 INTELPllInvalid("n out of range\n");
710 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
711 INTELPllInvalid("p1 out of range\n");
712 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
713 INTELPllInvalid("m2 out of range\n");
714 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
715 INTELPllInvalid("m1 out of range\n");
717 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
718 if (clock->m1 <= clock->m2)
719 INTELPllInvalid("m1 <= m2\n");
721 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
722 if (clock->p < limit->p.min || limit->p.max < clock->p)
723 INTELPllInvalid("p out of range\n");
724 if (clock->m < limit->m.min || limit->m.max < clock->m)
725 INTELPllInvalid("m out of range\n");
728 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
729 INTELPllInvalid("vco out of range\n");
730 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
731 * connector, etc., rather than just a single range.
733 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
734 INTELPllInvalid("dot out of range\n");
740 i9xx_select_p2_div(const intel_limit_t *limit,
741 const struct intel_crtc_state *crtc_state,
744 struct drm_device *dev = crtc_state->base.crtc->dev;
746 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
748 * For LVDS just rely on its current settings for dual-channel.
749 * We haven't figured out how to reliably set up different
750 * single/dual channel state, if we even can.
752 if (intel_is_dual_link_lvds(dev))
753 return limit->p2.p2_fast;
755 return limit->p2.p2_slow;
757 if (target < limit->p2.dot_limit)
758 return limit->p2.p2_slow;
760 return limit->p2.p2_fast;
765 i9xx_find_best_dpll(const intel_limit_t *limit,
766 struct intel_crtc_state *crtc_state,
767 int target, int refclk, intel_clock_t *match_clock,
768 intel_clock_t *best_clock)
770 struct drm_device *dev = crtc_state->base.crtc->dev;
774 memset(best_clock, 0, sizeof(*best_clock));
776 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
778 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
780 for (clock.m2 = limit->m2.min;
781 clock.m2 <= limit->m2.max; clock.m2++) {
782 if (clock.m2 >= clock.m1)
784 for (clock.n = limit->n.min;
785 clock.n <= limit->n.max; clock.n++) {
786 for (clock.p1 = limit->p1.min;
787 clock.p1 <= limit->p1.max; clock.p1++) {
790 i9xx_calc_dpll_params(refclk, &clock);
791 if (!intel_PLL_is_valid(dev, limit,
795 clock.p != match_clock->p)
798 this_err = abs(clock.dot - target);
799 if (this_err < err) {
808 return (err != target);
812 pnv_find_best_dpll(const intel_limit_t *limit,
813 struct intel_crtc_state *crtc_state,
814 int target, int refclk, intel_clock_t *match_clock,
815 intel_clock_t *best_clock)
817 struct drm_device *dev = crtc_state->base.crtc->dev;
821 memset(best_clock, 0, sizeof(*best_clock));
823 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
825 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
827 for (clock.m2 = limit->m2.min;
828 clock.m2 <= limit->m2.max; clock.m2++) {
829 for (clock.n = limit->n.min;
830 clock.n <= limit->n.max; clock.n++) {
831 for (clock.p1 = limit->p1.min;
832 clock.p1 <= limit->p1.max; clock.p1++) {
835 pnv_calc_dpll_params(refclk, &clock);
836 if (!intel_PLL_is_valid(dev, limit,
840 clock.p != match_clock->p)
843 this_err = abs(clock.dot - target);
844 if (this_err < err) {
853 return (err != target);
857 g4x_find_best_dpll(const intel_limit_t *limit,
858 struct intel_crtc_state *crtc_state,
859 int target, int refclk, intel_clock_t *match_clock,
860 intel_clock_t *best_clock)
862 struct drm_device *dev = crtc_state->base.crtc->dev;
866 /* approximately equals target * 0.00585 */
867 int err_most = (target >> 8) + (target >> 9);
869 memset(best_clock, 0, sizeof(*best_clock));
871 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
873 max_n = limit->n.max;
874 /* based on hardware requirement, prefer smaller n to precision */
875 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
876 /* based on hardware requirement, prefere larger m1,m2 */
877 for (clock.m1 = limit->m1.max;
878 clock.m1 >= limit->m1.min; clock.m1--) {
879 for (clock.m2 = limit->m2.max;
880 clock.m2 >= limit->m2.min; clock.m2--) {
881 for (clock.p1 = limit->p1.max;
882 clock.p1 >= limit->p1.min; clock.p1--) {
885 i9xx_calc_dpll_params(refclk, &clock);
886 if (!intel_PLL_is_valid(dev, limit,
890 this_err = abs(clock.dot - target);
891 if (this_err < err_most) {
905 * Check if the calculated PLL configuration is more optimal compared to the
906 * best configuration and error found so far. Return the calculated error.
908 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
909 const intel_clock_t *calculated_clock,
910 const intel_clock_t *best_clock,
911 unsigned int best_error_ppm,
912 unsigned int *error_ppm)
915 * For CHV ignore the error and consider only the P value.
916 * Prefer a bigger P value based on HW requirements.
918 if (IS_CHERRYVIEW(dev)) {
921 return calculated_clock->p > best_clock->p;
924 if (WARN_ON_ONCE(!target_freq))
927 *error_ppm = div_u64(1000000ULL *
928 abs(target_freq - calculated_clock->dot),
931 * Prefer a better P value over a better (smaller) error if the error
932 * is small. Ensure this preference for future configurations too by
933 * setting the error to 0.
935 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
941 return *error_ppm + 10 < best_error_ppm;
945 vlv_find_best_dpll(const intel_limit_t *limit,
946 struct intel_crtc_state *crtc_state,
947 int target, int refclk, intel_clock_t *match_clock,
948 intel_clock_t *best_clock)
950 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
951 struct drm_device *dev = crtc->base.dev;
953 unsigned int bestppm = 1000000;
954 /* min update 19.2 MHz */
955 int max_n = min(limit->n.max, refclk / 19200);
958 target *= 5; /* fast clock */
960 memset(best_clock, 0, sizeof(*best_clock));
962 /* based on hardware requirement, prefer smaller n to precision */
963 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
964 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
965 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
966 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
967 clock.p = clock.p1 * clock.p2;
968 /* based on hardware requirement, prefer bigger m1,m2 values */
969 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
972 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
975 vlv_calc_dpll_params(refclk, &clock);
977 if (!intel_PLL_is_valid(dev, limit,
981 if (!vlv_PLL_is_optimal(dev, target,
999 chv_find_best_dpll(const intel_limit_t *limit,
1000 struct intel_crtc_state *crtc_state,
1001 int target, int refclk, intel_clock_t *match_clock,
1002 intel_clock_t *best_clock)
1004 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1005 struct drm_device *dev = crtc->base.dev;
1006 unsigned int best_error_ppm;
1007 intel_clock_t clock;
1011 memset(best_clock, 0, sizeof(*best_clock));
1012 best_error_ppm = 1000000;
1015 * Based on hardware doc, the n always set to 1, and m1 always
1016 * set to 2. If requires to support 200Mhz refclk, we need to
1017 * revisit this because n may not 1 anymore.
1019 clock.n = 1, clock.m1 = 2;
1020 target *= 5; /* fast clock */
1022 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023 for (clock.p2 = limit->p2.p2_fast;
1024 clock.p2 >= limit->p2.p2_slow;
1025 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1026 unsigned int error_ppm;
1028 clock.p = clock.p1 * clock.p2;
1030 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1031 clock.n) << 22, refclk * clock.m1);
1033 if (m2 > INT_MAX/clock.m1)
1038 chv_calc_dpll_params(refclk, &clock);
1040 if (!intel_PLL_is_valid(dev, limit, &clock))
1043 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1044 best_error_ppm, &error_ppm))
1047 *best_clock = clock;
1048 best_error_ppm = error_ppm;
1056 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1057 intel_clock_t *best_clock)
1059 int refclk = i9xx_get_refclk(crtc_state, 0);
1061 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1062 target_clock, refclk, NULL, best_clock);
1065 bool intel_crtc_active(struct drm_crtc *crtc)
1067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1069 /* Be paranoid as we can arrive here with only partial
1070 * state retrieved from the hardware during setup.
1072 * We can ditch the adjusted_mode.crtc_clock check as soon
1073 * as Haswell has gained clock readout/fastboot support.
1075 * We can ditch the crtc->primary->fb check as soon as we can
1076 * properly reconstruct framebuffers.
1078 * FIXME: The intel_crtc->active here should be switched to
1079 * crtc->state->active once we have proper CRTC states wired up
1082 return intel_crtc->active && crtc->primary->state->fb &&
1083 intel_crtc->config->base.adjusted_mode.crtc_clock;
1086 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1089 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1092 return intel_crtc->config->cpu_transcoder;
1095 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1097 struct drm_i915_private *dev_priv = dev->dev_private;
1098 u32 reg = PIPEDSL(pipe);
1103 line_mask = DSL_LINEMASK_GEN2;
1105 line_mask = DSL_LINEMASK_GEN3;
1107 line1 = I915_READ(reg) & line_mask;
1109 line2 = I915_READ(reg) & line_mask;
1111 return line1 == line2;
1115 * intel_wait_for_pipe_off - wait for pipe to turn off
1116 * @crtc: crtc whose pipe to wait for
1118 * After disabling a pipe, we can't wait for vblank in the usual way,
1119 * spinning on the vblank interrupt status bit, since we won't actually
1120 * see an interrupt when the pipe is disabled.
1122 * On Gen4 and above:
1123 * wait for the pipe register state bit to turn off
1126 * wait for the display line value to settle (it usually
1127 * ends up stopping at the start of the next frame).
1130 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1132 struct drm_device *dev = crtc->base.dev;
1133 struct drm_i915_private *dev_priv = dev->dev_private;
1134 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1135 enum pipe pipe = crtc->pipe;
1137 if (INTEL_INFO(dev)->gen >= 4) {
1138 int reg = PIPECONF(cpu_transcoder);
1140 /* Wait for the Pipe State to go off */
1141 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1143 WARN(1, "pipe_off wait timed out\n");
1145 /* Wait for the display line to settle */
1146 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1147 WARN(1, "pipe_off wait timed out\n");
1151 static const char *state_string(bool enabled)
1153 return enabled ? "on" : "off";
1156 /* Only for pre-ILK configs */
1157 void assert_pll(struct drm_i915_private *dev_priv,
1158 enum pipe pipe, bool state)
1163 val = I915_READ(DPLL(pipe));
1164 cur_state = !!(val & DPLL_VCO_ENABLE);
1165 I915_STATE_WARN(cur_state != state,
1166 "PLL state assertion failure (expected %s, current %s)\n",
1167 state_string(state), state_string(cur_state));
1170 /* XXX: the dsi pll is shared between MIPI DSI ports */
1171 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1176 mutex_lock(&dev_priv->sb_lock);
1177 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1178 mutex_unlock(&dev_priv->sb_lock);
1180 cur_state = val & DSI_PLL_VCO_EN;
1181 I915_STATE_WARN(cur_state != state,
1182 "DSI PLL state assertion failure (expected %s, current %s)\n",
1183 state_string(state), state_string(cur_state));
1185 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1186 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1188 struct intel_shared_dpll *
1189 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1191 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1193 if (crtc->config->shared_dpll < 0)
1196 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1200 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1201 struct intel_shared_dpll *pll,
1205 struct intel_dpll_hw_state hw_state;
1208 "asserting DPLL %s with no DPLL\n", state_string(state)))
1211 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1212 I915_STATE_WARN(cur_state != state,
1213 "%s assertion failure (expected %s, current %s)\n",
1214 pll->name, state_string(state), state_string(cur_state));
1217 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1221 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224 if (HAS_DDI(dev_priv->dev)) {
1225 /* DDI does not have a specific FDI_TX register */
1226 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1227 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1229 u32 val = I915_READ(FDI_TX_CTL(pipe));
1230 cur_state = !!(val & FDI_TX_ENABLE);
1232 I915_STATE_WARN(cur_state != state,
1233 "FDI TX state assertion failure (expected %s, current %s)\n",
1234 state_string(state), state_string(cur_state));
1236 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1237 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1239 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, bool state)
1245 val = I915_READ(FDI_RX_CTL(pipe));
1246 cur_state = !!(val & FDI_RX_ENABLE);
1247 I915_STATE_WARN(cur_state != state,
1248 "FDI RX state assertion failure (expected %s, current %s)\n",
1249 state_string(state), state_string(cur_state));
1251 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1252 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1254 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1259 /* ILK FDI PLL is always enabled */
1260 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1263 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1264 if (HAS_DDI(dev_priv->dev))
1267 val = I915_READ(FDI_TX_CTL(pipe));
1268 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1271 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1272 enum pipe pipe, bool state)
1277 val = I915_READ(FDI_RX_CTL(pipe));
1278 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1279 I915_STATE_WARN(cur_state != state,
1280 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1281 state_string(state), state_string(cur_state));
1284 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1287 struct drm_device *dev = dev_priv->dev;
1290 enum pipe panel_pipe = PIPE_A;
1293 if (WARN_ON(HAS_DDI(dev)))
1296 if (HAS_PCH_SPLIT(dev)) {
1299 pp_reg = PCH_PP_CONTROL;
1300 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1302 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1303 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1304 panel_pipe = PIPE_B;
1305 /* XXX: else fix for eDP */
1306 } else if (IS_VALLEYVIEW(dev)) {
1307 /* presumably write lock depends on pipe, not port select */
1308 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1311 pp_reg = PP_CONTROL;
1312 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1313 panel_pipe = PIPE_B;
1316 val = I915_READ(pp_reg);
1317 if (!(val & PANEL_POWER_ON) ||
1318 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1321 I915_STATE_WARN(panel_pipe == pipe && locked,
1322 "panel assertion failure, pipe %c regs locked\n",
1326 static void assert_cursor(struct drm_i915_private *dev_priv,
1327 enum pipe pipe, bool state)
1329 struct drm_device *dev = dev_priv->dev;
1332 if (IS_845G(dev) || IS_I865G(dev))
1333 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1335 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1337 I915_STATE_WARN(cur_state != state,
1338 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1339 pipe_name(pipe), state_string(state), state_string(cur_state));
1341 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1342 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1344 void assert_pipe(struct drm_i915_private *dev_priv,
1345 enum pipe pipe, bool state)
1348 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1351 /* if we need the pipe quirk it must be always on */
1352 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1353 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1356 if (!intel_display_power_is_enabled(dev_priv,
1357 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1360 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1361 cur_state = !!(val & PIPECONF_ENABLE);
1364 I915_STATE_WARN(cur_state != state,
1365 "pipe %c assertion failure (expected %s, current %s)\n",
1366 pipe_name(pipe), state_string(state), state_string(cur_state));
1369 static void assert_plane(struct drm_i915_private *dev_priv,
1370 enum plane plane, bool state)
1375 val = I915_READ(DSPCNTR(plane));
1376 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1377 I915_STATE_WARN(cur_state != state,
1378 "plane %c assertion failure (expected %s, current %s)\n",
1379 plane_name(plane), state_string(state), state_string(cur_state));
1382 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1383 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1385 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1388 struct drm_device *dev = dev_priv->dev;
1391 /* Primary planes are fixed to pipes on gen4+ */
1392 if (INTEL_INFO(dev)->gen >= 4) {
1393 u32 val = I915_READ(DSPCNTR(pipe));
1394 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1395 "plane %c assertion failure, should be disabled but not\n",
1400 /* Need to check both planes against the pipe */
1401 for_each_pipe(dev_priv, i) {
1402 u32 val = I915_READ(DSPCNTR(i));
1403 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1404 DISPPLANE_SEL_PIPE_SHIFT;
1405 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1406 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1407 plane_name(i), pipe_name(pipe));
1411 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1414 struct drm_device *dev = dev_priv->dev;
1417 if (INTEL_INFO(dev)->gen >= 9) {
1418 for_each_sprite(dev_priv, pipe, sprite) {
1419 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1420 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1421 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1422 sprite, pipe_name(pipe));
1424 } else if (IS_VALLEYVIEW(dev)) {
1425 for_each_sprite(dev_priv, pipe, sprite) {
1426 u32 val = I915_READ(SPCNTR(pipe, sprite));
1427 I915_STATE_WARN(val & SP_ENABLE,
1428 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1429 sprite_name(pipe, sprite), pipe_name(pipe));
1431 } else if (INTEL_INFO(dev)->gen >= 7) {
1432 u32 val = I915_READ(SPRCTL(pipe));
1433 I915_STATE_WARN(val & SPRITE_ENABLE,
1434 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1435 plane_name(pipe), pipe_name(pipe));
1436 } else if (INTEL_INFO(dev)->gen >= 5) {
1437 u32 val = I915_READ(DVSCNTR(pipe));
1438 I915_STATE_WARN(val & DVS_ENABLE,
1439 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1440 plane_name(pipe), pipe_name(pipe));
1444 static void assert_vblank_disabled(struct drm_crtc *crtc)
1446 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1447 drm_crtc_vblank_put(crtc);
1450 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1455 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1457 val = I915_READ(PCH_DREF_CONTROL);
1458 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1459 DREF_SUPERSPREAD_SOURCE_MASK));
1460 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1463 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1469 val = I915_READ(PCH_TRANSCONF(pipe));
1470 enabled = !!(val & TRANS_ENABLE);
1471 I915_STATE_WARN(enabled,
1472 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1476 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1477 enum pipe pipe, u32 port_sel, u32 val)
1479 if ((val & DP_PORT_EN) == 0)
1482 if (HAS_PCH_CPT(dev_priv->dev)) {
1483 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1484 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1485 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1487 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1488 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1491 if ((val & DP_PIPE_MASK) != (pipe << 30))
1497 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1498 enum pipe pipe, u32 val)
1500 if ((val & SDVO_ENABLE) == 0)
1503 if (HAS_PCH_CPT(dev_priv->dev)) {
1504 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1506 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1507 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1510 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1516 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1517 enum pipe pipe, u32 val)
1519 if ((val & LVDS_PORT_EN) == 0)
1522 if (HAS_PCH_CPT(dev_priv->dev)) {
1523 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1526 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1532 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1533 enum pipe pipe, u32 val)
1535 if ((val & ADPA_DAC_ENABLE) == 0)
1537 if (HAS_PCH_CPT(dev_priv->dev)) {
1538 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1541 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1547 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1548 enum pipe pipe, int reg, u32 port_sel)
1550 u32 val = I915_READ(reg);
1551 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1552 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1553 reg, pipe_name(pipe));
1555 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1556 && (val & DP_PIPEB_SELECT),
1557 "IBX PCH dp port still using transcoder B\n");
1560 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1561 enum pipe pipe, int reg)
1563 u32 val = I915_READ(reg);
1564 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1565 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1566 reg, pipe_name(pipe));
1568 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1569 && (val & SDVO_PIPE_B_SELECT),
1570 "IBX PCH hdmi port still using transcoder B\n");
1573 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1578 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1579 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1580 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1582 val = I915_READ(PCH_ADPA);
1583 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1584 "PCH VGA enabled on transcoder %c, should be disabled\n",
1587 val = I915_READ(PCH_LVDS);
1588 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1589 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1592 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1597 static void vlv_enable_pll(struct intel_crtc *crtc,
1598 const struct intel_crtc_state *pipe_config)
1600 struct drm_device *dev = crtc->base.dev;
1601 struct drm_i915_private *dev_priv = dev->dev_private;
1602 int reg = DPLL(crtc->pipe);
1603 u32 dpll = pipe_config->dpll_hw_state.dpll;
1605 assert_pipe_disabled(dev_priv, crtc->pipe);
1607 /* No really, not for ILK+ */
1608 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1610 /* PLL is protected by panel, make sure we can write it */
1611 if (IS_MOBILE(dev_priv->dev))
1612 assert_panel_unlocked(dev_priv, crtc->pipe);
1614 I915_WRITE(reg, dpll);
1618 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1621 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1622 POSTING_READ(DPLL_MD(crtc->pipe));
1624 /* We do this three times for luck */
1625 I915_WRITE(reg, dpll);
1627 udelay(150); /* wait for warmup */
1628 I915_WRITE(reg, dpll);
1630 udelay(150); /* wait for warmup */
1631 I915_WRITE(reg, dpll);
1633 udelay(150); /* wait for warmup */
1636 static void chv_enable_pll(struct intel_crtc *crtc,
1637 const struct intel_crtc_state *pipe_config)
1639 struct drm_device *dev = crtc->base.dev;
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 int pipe = crtc->pipe;
1642 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1645 assert_pipe_disabled(dev_priv, crtc->pipe);
1647 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1649 mutex_lock(&dev_priv->sb_lock);
1651 /* Enable back the 10bit clock to display controller */
1652 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1653 tmp |= DPIO_DCLKP_EN;
1654 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1656 mutex_unlock(&dev_priv->sb_lock);
1659 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1664 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1666 /* Check PLL is locked */
1667 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1668 DRM_ERROR("PLL %d failed to lock\n", pipe);
1670 /* not sure when this should be written */
1671 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1672 POSTING_READ(DPLL_MD(pipe));
1675 static int intel_num_dvo_pipes(struct drm_device *dev)
1677 struct intel_crtc *crtc;
1680 for_each_intel_crtc(dev, crtc)
1681 count += crtc->base.state->active &&
1682 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1687 static void i9xx_enable_pll(struct intel_crtc *crtc)
1689 struct drm_device *dev = crtc->base.dev;
1690 struct drm_i915_private *dev_priv = dev->dev_private;
1691 int reg = DPLL(crtc->pipe);
1692 u32 dpll = crtc->config->dpll_hw_state.dpll;
1694 assert_pipe_disabled(dev_priv, crtc->pipe);
1696 /* No really, not for ILK+ */
1697 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1699 /* PLL is protected by panel, make sure we can write it */
1700 if (IS_MOBILE(dev) && !IS_I830(dev))
1701 assert_panel_unlocked(dev_priv, crtc->pipe);
1703 /* Enable DVO 2x clock on both PLLs if necessary */
1704 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1706 * It appears to be important that we don't enable this
1707 * for the current pipe before otherwise configuring the
1708 * PLL. No idea how this should be handled if multiple
1709 * DVO outputs are enabled simultaneosly.
1711 dpll |= DPLL_DVO_2X_MODE;
1712 I915_WRITE(DPLL(!crtc->pipe),
1713 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1716 /* Wait for the clocks to stabilize. */
1720 if (INTEL_INFO(dev)->gen >= 4) {
1721 I915_WRITE(DPLL_MD(crtc->pipe),
1722 crtc->config->dpll_hw_state.dpll_md);
1724 /* The pixel multiplier can only be updated once the
1725 * DPLL is enabled and the clocks are stable.
1727 * So write it again.
1729 I915_WRITE(reg, dpll);
1732 /* We do this three times for luck */
1733 I915_WRITE(reg, dpll);
1735 udelay(150); /* wait for warmup */
1736 I915_WRITE(reg, dpll);
1738 udelay(150); /* wait for warmup */
1739 I915_WRITE(reg, dpll);
1741 udelay(150); /* wait for warmup */
1745 * i9xx_disable_pll - disable a PLL
1746 * @dev_priv: i915 private structure
1747 * @pipe: pipe PLL to disable
1749 * Disable the PLL for @pipe, making sure the pipe is off first.
1751 * Note! This is for pre-ILK only.
1753 static void i9xx_disable_pll(struct intel_crtc *crtc)
1755 struct drm_device *dev = crtc->base.dev;
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757 enum pipe pipe = crtc->pipe;
1759 /* Disable DVO 2x clock on both PLLs if necessary */
1761 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1762 !intel_num_dvo_pipes(dev)) {
1763 I915_WRITE(DPLL(PIPE_B),
1764 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1765 I915_WRITE(DPLL(PIPE_A),
1766 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1769 /* Don't disable pipe or pipe PLLs if needed */
1770 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1771 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1774 /* Make sure the pipe isn't still relying on us */
1775 assert_pipe_disabled(dev_priv, pipe);
1777 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1778 POSTING_READ(DPLL(pipe));
1781 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
1789 * Leave integrated clock source and reference clock enabled for pipe B.
1790 * The latter is needed for VGA hotplug / manual detection.
1792 val = DPLL_VGA_MODE_DIS;
1794 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1795 I915_WRITE(DPLL(pipe), val);
1796 POSTING_READ(DPLL(pipe));
1800 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1802 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1805 /* Make sure the pipe isn't still relying on us */
1806 assert_pipe_disabled(dev_priv, pipe);
1808 /* Set PLL en = 0 */
1809 val = DPLL_SSC_REF_CLK_CHV |
1810 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1812 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1813 I915_WRITE(DPLL(pipe), val);
1814 POSTING_READ(DPLL(pipe));
1816 mutex_lock(&dev_priv->sb_lock);
1818 /* Disable 10bit clock to display controller */
1819 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1820 val &= ~DPIO_DCLKP_EN;
1821 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1823 mutex_unlock(&dev_priv->sb_lock);
1826 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1827 struct intel_digital_port *dport,
1828 unsigned int expected_mask)
1833 switch (dport->port) {
1835 port_mask = DPLL_PORTB_READY_MASK;
1839 port_mask = DPLL_PORTC_READY_MASK;
1841 expected_mask <<= 4;
1844 port_mask = DPLL_PORTD_READY_MASK;
1845 dpll_reg = DPIO_PHY_STATUS;
1851 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1852 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1853 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1856 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1858 struct drm_device *dev = crtc->base.dev;
1859 struct drm_i915_private *dev_priv = dev->dev_private;
1860 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1862 if (WARN_ON(pll == NULL))
1865 WARN_ON(!pll->config.crtc_mask);
1866 if (pll->active == 0) {
1867 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1869 assert_shared_dpll_disabled(dev_priv, pll);
1871 pll->mode_set(dev_priv, pll);
1876 * intel_enable_shared_dpll - enable PCH PLL
1877 * @dev_priv: i915 private structure
1878 * @pipe: pipe PLL to enable
1880 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1881 * drives the transcoder clock.
1883 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1885 struct drm_device *dev = crtc->base.dev;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
1887 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1889 if (WARN_ON(pll == NULL))
1892 if (WARN_ON(pll->config.crtc_mask == 0))
1895 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1896 pll->name, pll->active, pll->on,
1897 crtc->base.base.id);
1899 if (pll->active++) {
1901 assert_shared_dpll_enabled(dev_priv, pll);
1906 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1908 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1909 pll->enable(dev_priv, pll);
1913 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1915 struct drm_device *dev = crtc->base.dev;
1916 struct drm_i915_private *dev_priv = dev->dev_private;
1917 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1919 /* PCH only available on ILK+ */
1920 if (INTEL_INFO(dev)->gen < 5)
1926 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1929 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1930 pll->name, pll->active, pll->on,
1931 crtc->base.base.id);
1933 if (WARN_ON(pll->active == 0)) {
1934 assert_shared_dpll_disabled(dev_priv, pll);
1938 assert_shared_dpll_enabled(dev_priv, pll);
1943 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1944 pll->disable(dev_priv, pll);
1947 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1950 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1953 struct drm_device *dev = dev_priv->dev;
1954 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1956 uint32_t reg, val, pipeconf_val;
1958 /* PCH only available on ILK+ */
1959 BUG_ON(!HAS_PCH_SPLIT(dev));
1961 /* Make sure PCH DPLL is enabled */
1962 assert_shared_dpll_enabled(dev_priv,
1963 intel_crtc_to_shared_dpll(intel_crtc));
1965 /* FDI must be feeding us bits for PCH ports */
1966 assert_fdi_tx_enabled(dev_priv, pipe);
1967 assert_fdi_rx_enabled(dev_priv, pipe);
1969 if (HAS_PCH_CPT(dev)) {
1970 /* Workaround: Set the timing override bit before enabling the
1971 * pch transcoder. */
1972 reg = TRANS_CHICKEN2(pipe);
1973 val = I915_READ(reg);
1974 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1975 I915_WRITE(reg, val);
1978 reg = PCH_TRANSCONF(pipe);
1979 val = I915_READ(reg);
1980 pipeconf_val = I915_READ(PIPECONF(pipe));
1982 if (HAS_PCH_IBX(dev_priv->dev)) {
1984 * Make the BPC in transcoder be consistent with
1985 * that in pipeconf reg. For HDMI we must use 8bpc
1986 * here for both 8bpc and 12bpc.
1988 val &= ~PIPECONF_BPC_MASK;
1989 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1990 val |= PIPECONF_8BPC;
1992 val |= pipeconf_val & PIPECONF_BPC_MASK;
1995 val &= ~TRANS_INTERLACE_MASK;
1996 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1997 if (HAS_PCH_IBX(dev_priv->dev) &&
1998 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1999 val |= TRANS_LEGACY_INTERLACED_ILK;
2001 val |= TRANS_INTERLACED;
2003 val |= TRANS_PROGRESSIVE;
2005 I915_WRITE(reg, val | TRANS_ENABLE);
2006 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2007 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2010 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2011 enum transcoder cpu_transcoder)
2013 u32 val, pipeconf_val;
2015 /* PCH only available on ILK+ */
2016 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2018 /* FDI must be feeding us bits for PCH ports */
2019 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2020 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2022 /* Workaround: set timing override bit. */
2023 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2024 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2025 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2028 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2030 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2031 PIPECONF_INTERLACED_ILK)
2032 val |= TRANS_INTERLACED;
2034 val |= TRANS_PROGRESSIVE;
2036 I915_WRITE(LPT_TRANSCONF, val);
2037 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2038 DRM_ERROR("Failed to enable PCH transcoder\n");
2041 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2044 struct drm_device *dev = dev_priv->dev;
2047 /* FDI relies on the transcoder */
2048 assert_fdi_tx_disabled(dev_priv, pipe);
2049 assert_fdi_rx_disabled(dev_priv, pipe);
2051 /* Ports must be off as well */
2052 assert_pch_ports_disabled(dev_priv, pipe);
2054 reg = PCH_TRANSCONF(pipe);
2055 val = I915_READ(reg);
2056 val &= ~TRANS_ENABLE;
2057 I915_WRITE(reg, val);
2058 /* wait for PCH transcoder off, transcoder state */
2059 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2060 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2062 if (!HAS_PCH_IBX(dev)) {
2063 /* Workaround: Clear the timing override chicken bit again. */
2064 reg = TRANS_CHICKEN2(pipe);
2065 val = I915_READ(reg);
2066 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2067 I915_WRITE(reg, val);
2071 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2075 val = I915_READ(LPT_TRANSCONF);
2076 val &= ~TRANS_ENABLE;
2077 I915_WRITE(LPT_TRANSCONF, val);
2078 /* wait for PCH transcoder off, transcoder state */
2079 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2080 DRM_ERROR("Failed to disable PCH transcoder\n");
2082 /* Workaround: clear timing override bit. */
2083 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2084 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2085 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2089 * intel_enable_pipe - enable a pipe, asserting requirements
2090 * @crtc: crtc responsible for the pipe
2092 * Enable @crtc's pipe, making sure that various hardware specific requirements
2093 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2095 static void intel_enable_pipe(struct intel_crtc *crtc)
2097 struct drm_device *dev = crtc->base.dev;
2098 struct drm_i915_private *dev_priv = dev->dev_private;
2099 enum pipe pipe = crtc->pipe;
2100 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2102 enum pipe pch_transcoder;
2106 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2108 assert_planes_disabled(dev_priv, pipe);
2109 assert_cursor_disabled(dev_priv, pipe);
2110 assert_sprites_disabled(dev_priv, pipe);
2112 if (HAS_PCH_LPT(dev_priv->dev))
2113 pch_transcoder = TRANSCODER_A;
2115 pch_transcoder = pipe;
2118 * A pipe without a PLL won't actually be able to drive bits from
2119 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2122 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2123 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2124 assert_dsi_pll_enabled(dev_priv);
2126 assert_pll_enabled(dev_priv, pipe);
2128 if (crtc->config->has_pch_encoder) {
2129 /* if driving the PCH, we need FDI enabled */
2130 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2131 assert_fdi_tx_pll_enabled(dev_priv,
2132 (enum pipe) cpu_transcoder);
2134 /* FIXME: assert CPU port conditions for SNB+ */
2137 reg = PIPECONF(cpu_transcoder);
2138 val = I915_READ(reg);
2139 if (val & PIPECONF_ENABLE) {
2140 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2141 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2145 I915_WRITE(reg, val | PIPECONF_ENABLE);
2150 * intel_disable_pipe - disable a pipe, asserting requirements
2151 * @crtc: crtc whose pipes is to be disabled
2153 * Disable the pipe of @crtc, making sure that various hardware
2154 * specific requirements are met, if applicable, e.g. plane
2155 * disabled, panel fitter off, etc.
2157 * Will wait until the pipe has shut down before returning.
2159 static void intel_disable_pipe(struct intel_crtc *crtc)
2161 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2162 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2163 enum pipe pipe = crtc->pipe;
2167 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2170 * Make sure planes won't keep trying to pump pixels to us,
2171 * or we might hang the display.
2173 assert_planes_disabled(dev_priv, pipe);
2174 assert_cursor_disabled(dev_priv, pipe);
2175 assert_sprites_disabled(dev_priv, pipe);
2177 reg = PIPECONF(cpu_transcoder);
2178 val = I915_READ(reg);
2179 if ((val & PIPECONF_ENABLE) == 0)
2183 * Double wide has implications for planes
2184 * so best keep it disabled when not needed.
2186 if (crtc->config->double_wide)
2187 val &= ~PIPECONF_DOUBLE_WIDE;
2189 /* Don't disable pipe or pipe PLLs if needed */
2190 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2191 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2192 val &= ~PIPECONF_ENABLE;
2194 I915_WRITE(reg, val);
2195 if ((val & PIPECONF_ENABLE) == 0)
2196 intel_wait_for_pipe_off(crtc);
2199 static bool need_vtd_wa(struct drm_device *dev)
2201 #ifdef CONFIG_INTEL_IOMMU
2202 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2209 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2210 uint64_t fb_format_modifier, unsigned int plane)
2212 unsigned int tile_height;
2213 uint32_t pixel_bytes;
2215 switch (fb_format_modifier) {
2216 case DRM_FORMAT_MOD_NONE:
2219 case I915_FORMAT_MOD_X_TILED:
2220 tile_height = IS_GEN2(dev) ? 16 : 8;
2222 case I915_FORMAT_MOD_Y_TILED:
2225 case I915_FORMAT_MOD_Yf_TILED:
2226 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2227 switch (pixel_bytes) {
2241 "128-bit pixels are not supported for display!");
2247 MISSING_CASE(fb_format_modifier);
2256 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2257 uint32_t pixel_format, uint64_t fb_format_modifier)
2259 return ALIGN(height, intel_tile_height(dev, pixel_format,
2260 fb_format_modifier, 0));
2264 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2265 const struct drm_plane_state *plane_state)
2267 struct intel_rotation_info *info = &view->rotation_info;
2268 unsigned int tile_height, tile_pitch;
2270 *view = i915_ggtt_view_normal;
2275 if (!intel_rotation_90_or_270(plane_state->rotation))
2278 *view = i915_ggtt_view_rotated;
2280 info->height = fb->height;
2281 info->pixel_format = fb->pixel_format;
2282 info->pitch = fb->pitches[0];
2283 info->uv_offset = fb->offsets[1];
2284 info->fb_modifier = fb->modifier[0];
2286 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2287 fb->modifier[0], 0);
2288 tile_pitch = PAGE_SIZE / tile_height;
2289 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2290 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2291 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2293 if (info->pixel_format == DRM_FORMAT_NV12) {
2294 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2295 fb->modifier[0], 1);
2296 tile_pitch = PAGE_SIZE / tile_height;
2297 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2298 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2300 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2307 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2309 if (INTEL_INFO(dev_priv)->gen >= 9)
2311 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2312 IS_VALLEYVIEW(dev_priv))
2314 else if (INTEL_INFO(dev_priv)->gen >= 4)
2321 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2322 struct drm_framebuffer *fb,
2323 const struct drm_plane_state *plane_state,
2324 struct intel_engine_cs *pipelined,
2325 struct drm_i915_gem_request **pipelined_request)
2327 struct drm_device *dev = fb->dev;
2328 struct drm_i915_private *dev_priv = dev->dev_private;
2329 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2330 struct i915_ggtt_view view;
2334 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2336 switch (fb->modifier[0]) {
2337 case DRM_FORMAT_MOD_NONE:
2338 alignment = intel_linear_alignment(dev_priv);
2340 case I915_FORMAT_MOD_X_TILED:
2341 if (INTEL_INFO(dev)->gen >= 9)
2342 alignment = 256 * 1024;
2344 /* pin() will align the object as required by fence */
2348 case I915_FORMAT_MOD_Y_TILED:
2349 case I915_FORMAT_MOD_Yf_TILED:
2350 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2351 "Y tiling bo slipped through, driver bug!\n"))
2353 alignment = 1 * 1024 * 1024;
2356 MISSING_CASE(fb->modifier[0]);
2360 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2364 /* Note that the w/a also requires 64 PTE of padding following the
2365 * bo. We currently fill all unused PTE with the shadow page and so
2366 * we should always have valid PTE following the scanout preventing
2369 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2370 alignment = 256 * 1024;
2373 * Global gtt pte registers are special registers which actually forward
2374 * writes to a chunk of system memory. Which means that there is no risk
2375 * that the register values disappear as soon as we call
2376 * intel_runtime_pm_put(), so it is correct to wrap only the
2377 * pin/unpin/fence and not more.
2379 intel_runtime_pm_get(dev_priv);
2381 dev_priv->mm.interruptible = false;
2382 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2383 pipelined_request, &view);
2385 goto err_interruptible;
2387 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2388 * fence, whereas 965+ only requires a fence if using
2389 * framebuffer compression. For simplicity, we always install
2390 * a fence as the cost is not that onerous.
2392 ret = i915_gem_object_get_fence(obj);
2393 if (ret == -EDEADLK) {
2395 * -EDEADLK means there are no free fences
2398 * This is propagated to atomic, but it uses
2399 * -EDEADLK to force a locking recovery, so
2400 * change the returned error to -EBUSY.
2407 i915_gem_object_pin_fence(obj);
2409 dev_priv->mm.interruptible = true;
2410 intel_runtime_pm_put(dev_priv);
2414 i915_gem_object_unpin_from_display_plane(obj, &view);
2416 dev_priv->mm.interruptible = true;
2417 intel_runtime_pm_put(dev_priv);
2421 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2422 const struct drm_plane_state *plane_state)
2424 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2425 struct i915_ggtt_view view;
2428 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2430 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2431 WARN_ONCE(ret, "Couldn't get view from plane state!");
2433 i915_gem_object_unpin_fence(obj);
2434 i915_gem_object_unpin_from_display_plane(obj, &view);
2437 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2438 * is assumed to be a power-of-two. */
2439 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2441 unsigned int tiling_mode,
2445 if (tiling_mode != I915_TILING_NONE) {
2446 unsigned int tile_rows, tiles;
2451 tiles = *x / (512/cpp);
2454 return tile_rows * pitch * 8 + tiles * 4096;
2456 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2457 unsigned int offset;
2459 offset = *y * pitch + *x * cpp;
2460 *y = (offset & alignment) / pitch;
2461 *x = ((offset & alignment) - *y * pitch) / cpp;
2462 return offset & ~alignment;
2466 static int i9xx_format_to_fourcc(int format)
2469 case DISPPLANE_8BPP:
2470 return DRM_FORMAT_C8;
2471 case DISPPLANE_BGRX555:
2472 return DRM_FORMAT_XRGB1555;
2473 case DISPPLANE_BGRX565:
2474 return DRM_FORMAT_RGB565;
2476 case DISPPLANE_BGRX888:
2477 return DRM_FORMAT_XRGB8888;
2478 case DISPPLANE_RGBX888:
2479 return DRM_FORMAT_XBGR8888;
2480 case DISPPLANE_BGRX101010:
2481 return DRM_FORMAT_XRGB2101010;
2482 case DISPPLANE_RGBX101010:
2483 return DRM_FORMAT_XBGR2101010;
2487 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2490 case PLANE_CTL_FORMAT_RGB_565:
2491 return DRM_FORMAT_RGB565;
2493 case PLANE_CTL_FORMAT_XRGB_8888:
2496 return DRM_FORMAT_ABGR8888;
2498 return DRM_FORMAT_XBGR8888;
2501 return DRM_FORMAT_ARGB8888;
2503 return DRM_FORMAT_XRGB8888;
2505 case PLANE_CTL_FORMAT_XRGB_2101010:
2507 return DRM_FORMAT_XBGR2101010;
2509 return DRM_FORMAT_XRGB2101010;
2514 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2515 struct intel_initial_plane_config *plane_config)
2517 struct drm_device *dev = crtc->base.dev;
2518 struct drm_i915_private *dev_priv = to_i915(dev);
2519 struct drm_i915_gem_object *obj = NULL;
2520 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2521 struct drm_framebuffer *fb = &plane_config->fb->base;
2522 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2523 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2526 size_aligned -= base_aligned;
2528 if (plane_config->size == 0)
2531 /* If the FB is too big, just don't use it since fbdev is not very
2532 * important and we should probably use that space with FBC or other
2534 if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2537 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2544 obj->tiling_mode = plane_config->tiling;
2545 if (obj->tiling_mode == I915_TILING_X)
2546 obj->stride = fb->pitches[0];
2548 mode_cmd.pixel_format = fb->pixel_format;
2549 mode_cmd.width = fb->width;
2550 mode_cmd.height = fb->height;
2551 mode_cmd.pitches[0] = fb->pitches[0];
2552 mode_cmd.modifier[0] = fb->modifier[0];
2553 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2555 mutex_lock(&dev->struct_mutex);
2556 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2558 DRM_DEBUG_KMS("intel fb init failed\n");
2561 mutex_unlock(&dev->struct_mutex);
2563 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2567 drm_gem_object_unreference(&obj->base);
2568 mutex_unlock(&dev->struct_mutex);
2572 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2574 update_state_fb(struct drm_plane *plane)
2576 if (plane->fb == plane->state->fb)
2579 if (plane->state->fb)
2580 drm_framebuffer_unreference(plane->state->fb);
2581 plane->state->fb = plane->fb;
2582 if (plane->state->fb)
2583 drm_framebuffer_reference(plane->state->fb);
2587 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2588 struct intel_initial_plane_config *plane_config)
2590 struct drm_device *dev = intel_crtc->base.dev;
2591 struct drm_i915_private *dev_priv = dev->dev_private;
2593 struct intel_crtc *i;
2594 struct drm_i915_gem_object *obj;
2595 struct drm_plane *primary = intel_crtc->base.primary;
2596 struct drm_plane_state *plane_state = primary->state;
2597 struct drm_framebuffer *fb;
2599 if (!plane_config->fb)
2602 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2603 fb = &plane_config->fb->base;
2607 kfree(plane_config->fb);
2610 * Failed to alloc the obj, check to see if we should share
2611 * an fb with another CRTC instead
2613 for_each_crtc(dev, c) {
2614 i = to_intel_crtc(c);
2616 if (c == &intel_crtc->base)
2622 fb = c->primary->fb;
2626 obj = intel_fb_obj(fb);
2627 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2628 drm_framebuffer_reference(fb);
2636 plane_state->src_x = plane_state->src_y = 0;
2637 plane_state->src_w = fb->width << 16;
2638 plane_state->src_h = fb->height << 16;
2640 plane_state->crtc_x = plane_state->src_y = 0;
2641 plane_state->crtc_w = fb->width;
2642 plane_state->crtc_h = fb->height;
2644 obj = intel_fb_obj(fb);
2645 if (obj->tiling_mode != I915_TILING_NONE)
2646 dev_priv->preserve_bios_swizzle = true;
2648 drm_framebuffer_reference(fb);
2649 primary->fb = primary->state->fb = fb;
2650 primary->crtc = primary->state->crtc = &intel_crtc->base;
2651 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2652 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2655 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2656 struct drm_framebuffer *fb,
2659 struct drm_device *dev = crtc->dev;
2660 struct drm_i915_private *dev_priv = dev->dev_private;
2661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2662 struct drm_plane *primary = crtc->primary;
2663 bool visible = to_intel_plane_state(primary->state)->visible;
2664 struct drm_i915_gem_object *obj;
2665 int plane = intel_crtc->plane;
2666 unsigned long linear_offset;
2668 u32 reg = DSPCNTR(plane);
2671 if (!visible || !fb) {
2673 if (INTEL_INFO(dev)->gen >= 4)
2674 I915_WRITE(DSPSURF(plane), 0);
2676 I915_WRITE(DSPADDR(plane), 0);
2681 obj = intel_fb_obj(fb);
2682 if (WARN_ON(obj == NULL))
2685 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2687 dspcntr = DISPPLANE_GAMMA_ENABLE;
2689 dspcntr |= DISPLAY_PLANE_ENABLE;
2691 if (INTEL_INFO(dev)->gen < 4) {
2692 if (intel_crtc->pipe == PIPE_B)
2693 dspcntr |= DISPPLANE_SEL_PIPE_B;
2695 /* pipesrc and dspsize control the size that is scaled from,
2696 * which should always be the user's requested size.
2698 I915_WRITE(DSPSIZE(plane),
2699 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2700 (intel_crtc->config->pipe_src_w - 1));
2701 I915_WRITE(DSPPOS(plane), 0);
2702 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2703 I915_WRITE(PRIMSIZE(plane),
2704 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2705 (intel_crtc->config->pipe_src_w - 1));
2706 I915_WRITE(PRIMPOS(plane), 0);
2707 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2710 switch (fb->pixel_format) {
2712 dspcntr |= DISPPLANE_8BPP;
2714 case DRM_FORMAT_XRGB1555:
2715 dspcntr |= DISPPLANE_BGRX555;
2717 case DRM_FORMAT_RGB565:
2718 dspcntr |= DISPPLANE_BGRX565;
2720 case DRM_FORMAT_XRGB8888:
2721 dspcntr |= DISPPLANE_BGRX888;
2723 case DRM_FORMAT_XBGR8888:
2724 dspcntr |= DISPPLANE_RGBX888;
2726 case DRM_FORMAT_XRGB2101010:
2727 dspcntr |= DISPPLANE_BGRX101010;
2729 case DRM_FORMAT_XBGR2101010:
2730 dspcntr |= DISPPLANE_RGBX101010;
2736 if (INTEL_INFO(dev)->gen >= 4 &&
2737 obj->tiling_mode != I915_TILING_NONE)
2738 dspcntr |= DISPPLANE_TILED;
2741 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2743 linear_offset = y * fb->pitches[0] + x * pixel_size;
2745 if (INTEL_INFO(dev)->gen >= 4) {
2746 intel_crtc->dspaddr_offset =
2747 intel_gen4_compute_page_offset(dev_priv,
2748 &x, &y, obj->tiling_mode,
2751 linear_offset -= intel_crtc->dspaddr_offset;
2753 intel_crtc->dspaddr_offset = linear_offset;
2756 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2757 dspcntr |= DISPPLANE_ROTATE_180;
2759 x += (intel_crtc->config->pipe_src_w - 1);
2760 y += (intel_crtc->config->pipe_src_h - 1);
2762 /* Finding the last pixel of the last line of the display
2763 data and adding to linear_offset*/
2765 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2766 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2769 intel_crtc->adjusted_x = x;
2770 intel_crtc->adjusted_y = y;
2772 I915_WRITE(reg, dspcntr);
2774 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2775 if (INTEL_INFO(dev)->gen >= 4) {
2776 I915_WRITE(DSPSURF(plane),
2777 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2778 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2779 I915_WRITE(DSPLINOFF(plane), linear_offset);
2781 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2785 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2786 struct drm_framebuffer *fb,
2789 struct drm_device *dev = crtc->dev;
2790 struct drm_i915_private *dev_priv = dev->dev_private;
2791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2792 struct drm_plane *primary = crtc->primary;
2793 bool visible = to_intel_plane_state(primary->state)->visible;
2794 struct drm_i915_gem_object *obj;
2795 int plane = intel_crtc->plane;
2796 unsigned long linear_offset;
2798 u32 reg = DSPCNTR(plane);
2801 if (!visible || !fb) {
2803 I915_WRITE(DSPSURF(plane), 0);
2808 obj = intel_fb_obj(fb);
2809 if (WARN_ON(obj == NULL))
2812 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2814 dspcntr = DISPPLANE_GAMMA_ENABLE;
2816 dspcntr |= DISPLAY_PLANE_ENABLE;
2818 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2819 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2821 switch (fb->pixel_format) {
2823 dspcntr |= DISPPLANE_8BPP;
2825 case DRM_FORMAT_RGB565:
2826 dspcntr |= DISPPLANE_BGRX565;
2828 case DRM_FORMAT_XRGB8888:
2829 dspcntr |= DISPPLANE_BGRX888;
2831 case DRM_FORMAT_XBGR8888:
2832 dspcntr |= DISPPLANE_RGBX888;
2834 case DRM_FORMAT_XRGB2101010:
2835 dspcntr |= DISPPLANE_BGRX101010;
2837 case DRM_FORMAT_XBGR2101010:
2838 dspcntr |= DISPPLANE_RGBX101010;
2844 if (obj->tiling_mode != I915_TILING_NONE)
2845 dspcntr |= DISPPLANE_TILED;
2847 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2848 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2850 linear_offset = y * fb->pitches[0] + x * pixel_size;
2851 intel_crtc->dspaddr_offset =
2852 intel_gen4_compute_page_offset(dev_priv,
2853 &x, &y, obj->tiling_mode,
2856 linear_offset -= intel_crtc->dspaddr_offset;
2857 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2858 dspcntr |= DISPPLANE_ROTATE_180;
2860 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2861 x += (intel_crtc->config->pipe_src_w - 1);
2862 y += (intel_crtc->config->pipe_src_h - 1);
2864 /* Finding the last pixel of the last line of the display
2865 data and adding to linear_offset*/
2867 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2868 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2872 intel_crtc->adjusted_x = x;
2873 intel_crtc->adjusted_y = y;
2875 I915_WRITE(reg, dspcntr);
2877 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2878 I915_WRITE(DSPSURF(plane),
2879 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2880 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2881 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2883 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2884 I915_WRITE(DSPLINOFF(plane), linear_offset);
2889 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2890 uint32_t pixel_format)
2892 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2895 * The stride is either expressed as a multiple of 64 bytes
2896 * chunks for linear buffers or in number of tiles for tiled
2899 switch (fb_modifier) {
2900 case DRM_FORMAT_MOD_NONE:
2902 case I915_FORMAT_MOD_X_TILED:
2903 if (INTEL_INFO(dev)->gen == 2)
2906 case I915_FORMAT_MOD_Y_TILED:
2907 /* No need to check for old gens and Y tiling since this is
2908 * about the display engine and those will be blocked before
2912 case I915_FORMAT_MOD_Yf_TILED:
2913 if (bits_per_pixel == 8)
2918 MISSING_CASE(fb_modifier);
2923 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2924 struct drm_i915_gem_object *obj,
2927 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2928 struct i915_vma *vma;
2929 unsigned char *offset;
2931 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2932 view = &i915_ggtt_view_rotated;
2934 vma = i915_gem_obj_to_ggtt_view(obj, view);
2935 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2939 offset = (unsigned char *)vma->node.start;
2942 offset += vma->ggtt_view.rotation_info.uv_start_page *
2946 return (unsigned long)offset;
2949 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2951 struct drm_device *dev = intel_crtc->base.dev;
2952 struct drm_i915_private *dev_priv = dev->dev_private;
2954 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2955 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2956 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2960 * This function detaches (aka. unbinds) unused scalers in hardware
2962 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2964 struct intel_crtc_scaler_state *scaler_state;
2967 scaler_state = &intel_crtc->config->scaler_state;
2969 /* loop through and disable scalers that aren't in use */
2970 for (i = 0; i < intel_crtc->num_scalers; i++) {
2971 if (!scaler_state->scalers[i].in_use)
2972 skl_detach_scaler(intel_crtc, i);
2976 u32 skl_plane_ctl_format(uint32_t pixel_format)
2978 switch (pixel_format) {
2980 return PLANE_CTL_FORMAT_INDEXED;
2981 case DRM_FORMAT_RGB565:
2982 return PLANE_CTL_FORMAT_RGB_565;
2983 case DRM_FORMAT_XBGR8888:
2984 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2985 case DRM_FORMAT_XRGB8888:
2986 return PLANE_CTL_FORMAT_XRGB_8888;
2988 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2989 * to be already pre-multiplied. We need to add a knob (or a different
2990 * DRM_FORMAT) for user-space to configure that.
2992 case DRM_FORMAT_ABGR8888:
2993 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2994 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2995 case DRM_FORMAT_ARGB8888:
2996 return PLANE_CTL_FORMAT_XRGB_8888 |
2997 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2998 case DRM_FORMAT_XRGB2101010:
2999 return PLANE_CTL_FORMAT_XRGB_2101010;
3000 case DRM_FORMAT_XBGR2101010:
3001 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3002 case DRM_FORMAT_YUYV:
3003 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3004 case DRM_FORMAT_YVYU:
3005 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3006 case DRM_FORMAT_UYVY:
3007 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3008 case DRM_FORMAT_VYUY:
3009 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3011 MISSING_CASE(pixel_format);
3017 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3019 switch (fb_modifier) {
3020 case DRM_FORMAT_MOD_NONE:
3022 case I915_FORMAT_MOD_X_TILED:
3023 return PLANE_CTL_TILED_X;
3024 case I915_FORMAT_MOD_Y_TILED:
3025 return PLANE_CTL_TILED_Y;
3026 case I915_FORMAT_MOD_Yf_TILED:
3027 return PLANE_CTL_TILED_YF;
3029 MISSING_CASE(fb_modifier);
3035 u32 skl_plane_ctl_rotation(unsigned int rotation)
3038 case BIT(DRM_ROTATE_0):
3041 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3042 * while i915 HW rotation is clockwise, thats why this swapping.
3044 case BIT(DRM_ROTATE_90):
3045 return PLANE_CTL_ROTATE_270;
3046 case BIT(DRM_ROTATE_180):
3047 return PLANE_CTL_ROTATE_180;
3048 case BIT(DRM_ROTATE_270):
3049 return PLANE_CTL_ROTATE_90;
3051 MISSING_CASE(rotation);
3057 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3058 struct drm_framebuffer *fb,
3061 struct drm_device *dev = crtc->dev;
3062 struct drm_i915_private *dev_priv = dev->dev_private;
3063 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3064 struct drm_plane *plane = crtc->primary;
3065 bool visible = to_intel_plane_state(plane->state)->visible;
3066 struct drm_i915_gem_object *obj;
3067 int pipe = intel_crtc->pipe;
3068 u32 plane_ctl, stride_div, stride;
3069 u32 tile_height, plane_offset, plane_size;
3070 unsigned int rotation;
3071 int x_offset, y_offset;
3072 unsigned long surf_addr;
3073 struct intel_crtc_state *crtc_state = intel_crtc->config;
3074 struct intel_plane_state *plane_state;
3075 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3076 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3079 plane_state = to_intel_plane_state(plane->state);
3081 if (!visible || !fb) {
3082 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3083 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3084 POSTING_READ(PLANE_CTL(pipe, 0));
3088 plane_ctl = PLANE_CTL_ENABLE |
3089 PLANE_CTL_PIPE_GAMMA_ENABLE |
3090 PLANE_CTL_PIPE_CSC_ENABLE;
3092 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3093 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3094 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3096 rotation = plane->state->rotation;
3097 plane_ctl |= skl_plane_ctl_rotation(rotation);
3099 obj = intel_fb_obj(fb);
3100 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3102 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3104 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3106 scaler_id = plane_state->scaler_id;
3107 src_x = plane_state->src.x1 >> 16;
3108 src_y = plane_state->src.y1 >> 16;
3109 src_w = drm_rect_width(&plane_state->src) >> 16;
3110 src_h = drm_rect_height(&plane_state->src) >> 16;
3111 dst_x = plane_state->dst.x1;
3112 dst_y = plane_state->dst.y1;
3113 dst_w = drm_rect_width(&plane_state->dst);
3114 dst_h = drm_rect_height(&plane_state->dst);
3116 WARN_ON(x != src_x || y != src_y);
3118 if (intel_rotation_90_or_270(rotation)) {
3119 /* stride = Surface height in tiles */
3120 tile_height = intel_tile_height(dev, fb->pixel_format,
3121 fb->modifier[0], 0);
3122 stride = DIV_ROUND_UP(fb->height, tile_height);
3123 x_offset = stride * tile_height - y - src_h;
3125 plane_size = (src_w - 1) << 16 | (src_h - 1);
3127 stride = fb->pitches[0] / stride_div;
3130 plane_size = (src_h - 1) << 16 | (src_w - 1);
3132 plane_offset = y_offset << 16 | x_offset;
3134 intel_crtc->adjusted_x = x_offset;
3135 intel_crtc->adjusted_y = y_offset;
3137 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3138 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3139 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3140 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3142 if (scaler_id >= 0) {
3143 uint32_t ps_ctrl = 0;
3145 WARN_ON(!dst_w || !dst_h);
3146 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3147 crtc_state->scaler_state.scalers[scaler_id].mode;
3148 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3149 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3150 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3151 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3152 I915_WRITE(PLANE_POS(pipe, 0), 0);
3154 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3157 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3159 POSTING_READ(PLANE_SURF(pipe, 0));
3162 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3164 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3165 int x, int y, enum mode_set_atomic state)
3167 struct drm_device *dev = crtc->dev;
3168 struct drm_i915_private *dev_priv = dev->dev_private;
3170 if (dev_priv->fbc.disable_fbc)
3171 dev_priv->fbc.disable_fbc(dev_priv);
3173 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3178 static void intel_complete_page_flips(struct drm_device *dev)
3180 struct drm_crtc *crtc;
3182 for_each_crtc(dev, crtc) {
3183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3184 enum plane plane = intel_crtc->plane;
3186 intel_prepare_page_flip(dev, plane);
3187 intel_finish_page_flip_plane(dev, plane);
3191 static void intel_update_primary_planes(struct drm_device *dev)
3193 struct drm_crtc *crtc;
3195 for_each_crtc(dev, crtc) {
3196 struct intel_plane *plane = to_intel_plane(crtc->primary);
3197 struct intel_plane_state *plane_state;
3199 drm_modeset_lock_crtc(crtc, &plane->base);
3201 plane_state = to_intel_plane_state(plane->base.state);
3203 if (plane_state->base.fb)
3204 plane->commit_plane(&plane->base, plane_state);
3206 drm_modeset_unlock_crtc(crtc);
3210 void intel_prepare_reset(struct drm_device *dev)
3212 /* no reset support for gen2 */
3216 /* reset doesn't touch the display */
3217 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3220 drm_modeset_lock_all(dev);
3222 * Disabling the crtcs gracefully seems nicer. Also the
3223 * g33 docs say we should at least disable all the planes.
3225 intel_display_suspend(dev);
3228 void intel_finish_reset(struct drm_device *dev)
3230 struct drm_i915_private *dev_priv = to_i915(dev);
3233 * Flips in the rings will be nuked by the reset,
3234 * so complete all pending flips so that user space
3235 * will get its events and not get stuck.
3237 intel_complete_page_flips(dev);
3239 /* no reset support for gen2 */
3243 /* reset doesn't touch the display */
3244 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3246 * Flips in the rings have been nuked by the reset,
3247 * so update the base address of all primary
3248 * planes to the the last fb to make sure we're
3249 * showing the correct fb after a reset.
3251 * FIXME: Atomic will make this obsolete since we won't schedule
3252 * CS-based flips (which might get lost in gpu resets) any more.
3254 intel_update_primary_planes(dev);
3259 * The display has been reset as well,
3260 * so need a full re-initialization.
3262 intel_runtime_pm_disable_interrupts(dev_priv);
3263 intel_runtime_pm_enable_interrupts(dev_priv);
3265 intel_modeset_init_hw(dev);
3267 spin_lock_irq(&dev_priv->irq_lock);
3268 if (dev_priv->display.hpd_irq_setup)
3269 dev_priv->display.hpd_irq_setup(dev);
3270 spin_unlock_irq(&dev_priv->irq_lock);
3272 intel_display_resume(dev);
3274 intel_hpd_init(dev_priv);
3276 drm_modeset_unlock_all(dev);
3280 intel_finish_fb(struct drm_framebuffer *old_fb)
3282 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3283 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3284 bool was_interruptible = dev_priv->mm.interruptible;
3287 /* Big Hammer, we also need to ensure that any pending
3288 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3289 * current scanout is retired before unpinning the old
3290 * framebuffer. Note that we rely on userspace rendering
3291 * into the buffer attached to the pipe they are waiting
3292 * on. If not, userspace generates a GPU hang with IPEHR
3293 * point to the MI_WAIT_FOR_EVENT.
3295 * This should only fail upon a hung GPU, in which case we
3296 * can safely continue.
3298 dev_priv->mm.interruptible = false;
3299 ret = i915_gem_object_wait_rendering(obj, true);
3300 dev_priv->mm.interruptible = was_interruptible;
3305 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3307 struct drm_device *dev = crtc->dev;
3308 struct drm_i915_private *dev_priv = dev->dev_private;
3309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3312 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3313 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3316 spin_lock_irq(&dev->event_lock);
3317 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3318 spin_unlock_irq(&dev->event_lock);
3323 static void intel_update_pipe_config(struct intel_crtc *crtc,
3324 struct intel_crtc_state *old_crtc_state)
3326 struct drm_device *dev = crtc->base.dev;
3327 struct drm_i915_private *dev_priv = dev->dev_private;
3328 struct intel_crtc_state *pipe_config =
3329 to_intel_crtc_state(crtc->base.state);
3331 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3332 crtc->base.mode = crtc->base.state->mode;
3334 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3335 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3336 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3339 intel_set_pipe_csc(&crtc->base);
3342 * Update pipe size and adjust fitter if needed: the reason for this is
3343 * that in compute_mode_changes we check the native mode (not the pfit
3344 * mode) to see if we can flip rather than do a full mode set. In the
3345 * fastboot case, we'll flip, but if we don't update the pipesrc and
3346 * pfit state, we'll end up with a big fb scanned out into the wrong
3350 I915_WRITE(PIPESRC(crtc->pipe),
3351 ((pipe_config->pipe_src_w - 1) << 16) |
3352 (pipe_config->pipe_src_h - 1));
3354 /* on skylake this is done by detaching scalers */
3355 if (INTEL_INFO(dev)->gen >= 9) {
3356 skl_detach_scalers(crtc);
3358 if (pipe_config->pch_pfit.enabled)
3359 skylake_pfit_enable(crtc);
3360 } else if (HAS_PCH_SPLIT(dev)) {
3361 if (pipe_config->pch_pfit.enabled)
3362 ironlake_pfit_enable(crtc);
3363 else if (old_crtc_state->pch_pfit.enabled)
3364 ironlake_pfit_disable(crtc, true);
3368 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3370 struct drm_device *dev = crtc->dev;
3371 struct drm_i915_private *dev_priv = dev->dev_private;
3372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3373 int pipe = intel_crtc->pipe;
3376 /* enable normal train */
3377 reg = FDI_TX_CTL(pipe);
3378 temp = I915_READ(reg);
3379 if (IS_IVYBRIDGE(dev)) {
3380 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3381 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3383 temp &= ~FDI_LINK_TRAIN_NONE;
3384 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3386 I915_WRITE(reg, temp);
3388 reg = FDI_RX_CTL(pipe);
3389 temp = I915_READ(reg);
3390 if (HAS_PCH_CPT(dev)) {
3391 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3392 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3394 temp &= ~FDI_LINK_TRAIN_NONE;
3395 temp |= FDI_LINK_TRAIN_NONE;
3397 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3399 /* wait one idle pattern time */
3403 /* IVB wants error correction enabled */
3404 if (IS_IVYBRIDGE(dev))
3405 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3406 FDI_FE_ERRC_ENABLE);
3409 /* The FDI link training functions for ILK/Ibexpeak. */
3410 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3412 struct drm_device *dev = crtc->dev;
3413 struct drm_i915_private *dev_priv = dev->dev_private;
3414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3415 int pipe = intel_crtc->pipe;
3416 u32 reg, temp, tries;
3418 /* FDI needs bits from pipe first */
3419 assert_pipe_enabled(dev_priv, pipe);
3421 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3423 reg = FDI_RX_IMR(pipe);
3424 temp = I915_READ(reg);
3425 temp &= ~FDI_RX_SYMBOL_LOCK;
3426 temp &= ~FDI_RX_BIT_LOCK;
3427 I915_WRITE(reg, temp);
3431 /* enable CPU FDI TX and PCH FDI RX */
3432 reg = FDI_TX_CTL(pipe);
3433 temp = I915_READ(reg);
3434 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3435 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3436 temp &= ~FDI_LINK_TRAIN_NONE;
3437 temp |= FDI_LINK_TRAIN_PATTERN_1;
3438 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3440 reg = FDI_RX_CTL(pipe);
3441 temp = I915_READ(reg);
3442 temp &= ~FDI_LINK_TRAIN_NONE;
3443 temp |= FDI_LINK_TRAIN_PATTERN_1;
3444 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3449 /* Ironlake workaround, enable clock pointer after FDI enable*/
3450 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3451 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3452 FDI_RX_PHASE_SYNC_POINTER_EN);
3454 reg = FDI_RX_IIR(pipe);
3455 for (tries = 0; tries < 5; tries++) {
3456 temp = I915_READ(reg);
3457 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3459 if ((temp & FDI_RX_BIT_LOCK)) {
3460 DRM_DEBUG_KMS("FDI train 1 done.\n");
3461 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3466 DRM_ERROR("FDI train 1 fail!\n");
3469 reg = FDI_TX_CTL(pipe);
3470 temp = I915_READ(reg);
3471 temp &= ~FDI_LINK_TRAIN_NONE;
3472 temp |= FDI_LINK_TRAIN_PATTERN_2;
3473 I915_WRITE(reg, temp);
3475 reg = FDI_RX_CTL(pipe);
3476 temp = I915_READ(reg);
3477 temp &= ~FDI_LINK_TRAIN_NONE;
3478 temp |= FDI_LINK_TRAIN_PATTERN_2;
3479 I915_WRITE(reg, temp);
3484 reg = FDI_RX_IIR(pipe);
3485 for (tries = 0; tries < 5; tries++) {
3486 temp = I915_READ(reg);
3487 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3489 if (temp & FDI_RX_SYMBOL_LOCK) {
3490 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3491 DRM_DEBUG_KMS("FDI train 2 done.\n");
3496 DRM_ERROR("FDI train 2 fail!\n");
3498 DRM_DEBUG_KMS("FDI train done\n");
3502 static const int snb_b_fdi_train_param[] = {
3503 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3504 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3505 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3506 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3509 /* The FDI link training functions for SNB/Cougarpoint. */
3510 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3512 struct drm_device *dev = crtc->dev;
3513 struct drm_i915_private *dev_priv = dev->dev_private;
3514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3515 int pipe = intel_crtc->pipe;
3516 u32 reg, temp, i, retry;
3518 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3520 reg = FDI_RX_IMR(pipe);
3521 temp = I915_READ(reg);
3522 temp &= ~FDI_RX_SYMBOL_LOCK;
3523 temp &= ~FDI_RX_BIT_LOCK;
3524 I915_WRITE(reg, temp);
3529 /* enable CPU FDI TX and PCH FDI RX */
3530 reg = FDI_TX_CTL(pipe);
3531 temp = I915_READ(reg);
3532 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3533 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3534 temp &= ~FDI_LINK_TRAIN_NONE;
3535 temp |= FDI_LINK_TRAIN_PATTERN_1;
3536 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3538 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3539 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3541 I915_WRITE(FDI_RX_MISC(pipe),
3542 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3544 reg = FDI_RX_CTL(pipe);
3545 temp = I915_READ(reg);
3546 if (HAS_PCH_CPT(dev)) {
3547 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3548 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3550 temp &= ~FDI_LINK_TRAIN_NONE;
3551 temp |= FDI_LINK_TRAIN_PATTERN_1;
3553 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3558 for (i = 0; i < 4; i++) {
3559 reg = FDI_TX_CTL(pipe);
3560 temp = I915_READ(reg);
3561 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3562 temp |= snb_b_fdi_train_param[i];
3563 I915_WRITE(reg, temp);
3568 for (retry = 0; retry < 5; retry++) {
3569 reg = FDI_RX_IIR(pipe);
3570 temp = I915_READ(reg);
3571 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3572 if (temp & FDI_RX_BIT_LOCK) {
3573 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3574 DRM_DEBUG_KMS("FDI train 1 done.\n");
3583 DRM_ERROR("FDI train 1 fail!\n");
3586 reg = FDI_TX_CTL(pipe);
3587 temp = I915_READ(reg);
3588 temp &= ~FDI_LINK_TRAIN_NONE;
3589 temp |= FDI_LINK_TRAIN_PATTERN_2;
3591 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3593 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3595 I915_WRITE(reg, temp);
3597 reg = FDI_RX_CTL(pipe);
3598 temp = I915_READ(reg);
3599 if (HAS_PCH_CPT(dev)) {
3600 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3601 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3603 temp &= ~FDI_LINK_TRAIN_NONE;
3604 temp |= FDI_LINK_TRAIN_PATTERN_2;
3606 I915_WRITE(reg, temp);
3611 for (i = 0; i < 4; i++) {
3612 reg = FDI_TX_CTL(pipe);
3613 temp = I915_READ(reg);
3614 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3615 temp |= snb_b_fdi_train_param[i];
3616 I915_WRITE(reg, temp);
3621 for (retry = 0; retry < 5; retry++) {
3622 reg = FDI_RX_IIR(pipe);
3623 temp = I915_READ(reg);
3624 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3625 if (temp & FDI_RX_SYMBOL_LOCK) {
3626 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3627 DRM_DEBUG_KMS("FDI train 2 done.\n");
3636 DRM_ERROR("FDI train 2 fail!\n");
3638 DRM_DEBUG_KMS("FDI train done.\n");
3641 /* Manual link training for Ivy Bridge A0 parts */
3642 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3644 struct drm_device *dev = crtc->dev;
3645 struct drm_i915_private *dev_priv = dev->dev_private;
3646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3647 int pipe = intel_crtc->pipe;
3648 u32 reg, temp, i, j;
3650 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3652 reg = FDI_RX_IMR(pipe);
3653 temp = I915_READ(reg);
3654 temp &= ~FDI_RX_SYMBOL_LOCK;
3655 temp &= ~FDI_RX_BIT_LOCK;
3656 I915_WRITE(reg, temp);
3661 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3662 I915_READ(FDI_RX_IIR(pipe)));
3664 /* Try each vswing and preemphasis setting twice before moving on */
3665 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3666 /* disable first in case we need to retry */
3667 reg = FDI_TX_CTL(pipe);
3668 temp = I915_READ(reg);
3669 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3670 temp &= ~FDI_TX_ENABLE;
3671 I915_WRITE(reg, temp);
3673 reg = FDI_RX_CTL(pipe);
3674 temp = I915_READ(reg);
3675 temp &= ~FDI_LINK_TRAIN_AUTO;
3676 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3677 temp &= ~FDI_RX_ENABLE;
3678 I915_WRITE(reg, temp);
3680 /* enable CPU FDI TX and PCH FDI RX */
3681 reg = FDI_TX_CTL(pipe);
3682 temp = I915_READ(reg);
3683 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3684 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3685 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3686 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3687 temp |= snb_b_fdi_train_param[j/2];
3688 temp |= FDI_COMPOSITE_SYNC;
3689 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3691 I915_WRITE(FDI_RX_MISC(pipe),
3692 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3694 reg = FDI_RX_CTL(pipe);
3695 temp = I915_READ(reg);
3696 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3697 temp |= FDI_COMPOSITE_SYNC;
3698 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3701 udelay(1); /* should be 0.5us */
3703 for (i = 0; i < 4; i++) {
3704 reg = FDI_RX_IIR(pipe);
3705 temp = I915_READ(reg);
3706 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3708 if (temp & FDI_RX_BIT_LOCK ||
3709 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3710 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3711 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3715 udelay(1); /* should be 0.5us */
3718 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3723 reg = FDI_TX_CTL(pipe);
3724 temp = I915_READ(reg);
3725 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3726 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3727 I915_WRITE(reg, temp);
3729 reg = FDI_RX_CTL(pipe);
3730 temp = I915_READ(reg);
3731 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3732 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3733 I915_WRITE(reg, temp);
3736 udelay(2); /* should be 1.5us */
3738 for (i = 0; i < 4; i++) {
3739 reg = FDI_RX_IIR(pipe);
3740 temp = I915_READ(reg);
3741 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3743 if (temp & FDI_RX_SYMBOL_LOCK ||
3744 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3745 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3746 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3750 udelay(2); /* should be 1.5us */
3753 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3757 DRM_DEBUG_KMS("FDI train done.\n");
3760 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3762 struct drm_device *dev = intel_crtc->base.dev;
3763 struct drm_i915_private *dev_priv = dev->dev_private;
3764 int pipe = intel_crtc->pipe;
3768 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3769 reg = FDI_RX_CTL(pipe);
3770 temp = I915_READ(reg);
3771 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3772 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3773 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3774 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3779 /* Switch from Rawclk to PCDclk */
3780 temp = I915_READ(reg);
3781 I915_WRITE(reg, temp | FDI_PCDCLK);
3786 /* Enable CPU FDI TX PLL, always on for Ironlake */
3787 reg = FDI_TX_CTL(pipe);
3788 temp = I915_READ(reg);
3789 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3790 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3797 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3799 struct drm_device *dev = intel_crtc->base.dev;
3800 struct drm_i915_private *dev_priv = dev->dev_private;
3801 int pipe = intel_crtc->pipe;
3804 /* Switch from PCDclk to Rawclk */
3805 reg = FDI_RX_CTL(pipe);
3806 temp = I915_READ(reg);
3807 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3809 /* Disable CPU FDI TX PLL */
3810 reg = FDI_TX_CTL(pipe);
3811 temp = I915_READ(reg);
3812 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3817 reg = FDI_RX_CTL(pipe);
3818 temp = I915_READ(reg);
3819 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3821 /* Wait for the clocks to turn off. */
3826 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3828 struct drm_device *dev = crtc->dev;
3829 struct drm_i915_private *dev_priv = dev->dev_private;
3830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3831 int pipe = intel_crtc->pipe;
3834 /* disable CPU FDI tx and PCH FDI rx */
3835 reg = FDI_TX_CTL(pipe);
3836 temp = I915_READ(reg);
3837 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3840 reg = FDI_RX_CTL(pipe);
3841 temp = I915_READ(reg);
3842 temp &= ~(0x7 << 16);
3843 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3844 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3849 /* Ironlake workaround, disable clock pointer after downing FDI */
3850 if (HAS_PCH_IBX(dev))
3851 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3853 /* still set train pattern 1 */
3854 reg = FDI_TX_CTL(pipe);
3855 temp = I915_READ(reg);
3856 temp &= ~FDI_LINK_TRAIN_NONE;
3857 temp |= FDI_LINK_TRAIN_PATTERN_1;
3858 I915_WRITE(reg, temp);
3860 reg = FDI_RX_CTL(pipe);
3861 temp = I915_READ(reg);
3862 if (HAS_PCH_CPT(dev)) {
3863 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3864 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3866 temp &= ~FDI_LINK_TRAIN_NONE;
3867 temp |= FDI_LINK_TRAIN_PATTERN_1;
3869 /* BPC in FDI rx is consistent with that in PIPECONF */
3870 temp &= ~(0x07 << 16);
3871 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3872 I915_WRITE(reg, temp);
3878 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3880 struct intel_crtc *crtc;
3882 /* Note that we don't need to be called with mode_config.lock here
3883 * as our list of CRTC objects is static for the lifetime of the
3884 * device and so cannot disappear as we iterate. Similarly, we can
3885 * happily treat the predicates as racy, atomic checks as userspace
3886 * cannot claim and pin a new fb without at least acquring the
3887 * struct_mutex and so serialising with us.
3889 for_each_intel_crtc(dev, crtc) {
3890 if (atomic_read(&crtc->unpin_work_count) == 0)
3893 if (crtc->unpin_work)
3894 intel_wait_for_vblank(dev, crtc->pipe);
3902 static void page_flip_completed(struct intel_crtc *intel_crtc)
3904 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3905 struct intel_unpin_work *work = intel_crtc->unpin_work;
3907 /* ensure that the unpin work is consistent wrt ->pending. */
3909 intel_crtc->unpin_work = NULL;
3912 drm_send_vblank_event(intel_crtc->base.dev,
3916 drm_crtc_vblank_put(&intel_crtc->base);
3918 wake_up_all(&dev_priv->pending_flip_queue);
3919 queue_work(dev_priv->wq, &work->work);
3921 trace_i915_flip_complete(intel_crtc->plane,
3922 work->pending_flip_obj);
3925 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3927 struct drm_device *dev = crtc->dev;
3928 struct drm_i915_private *dev_priv = dev->dev_private;
3930 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3931 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3932 !intel_crtc_has_pending_flip(crtc),
3934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3936 spin_lock_irq(&dev->event_lock);
3937 if (intel_crtc->unpin_work) {
3938 WARN_ONCE(1, "Removing stuck page flip\n");
3939 page_flip_completed(intel_crtc);
3941 spin_unlock_irq(&dev->event_lock);
3944 if (crtc->primary->fb) {
3945 mutex_lock(&dev->struct_mutex);
3946 intel_finish_fb(crtc->primary->fb);
3947 mutex_unlock(&dev->struct_mutex);
3951 /* Program iCLKIP clock to the desired frequency */
3952 static void lpt_program_iclkip(struct drm_crtc *crtc)
3954 struct drm_device *dev = crtc->dev;
3955 struct drm_i915_private *dev_priv = dev->dev_private;
3956 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3957 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3960 mutex_lock(&dev_priv->sb_lock);
3962 /* It is necessary to ungate the pixclk gate prior to programming
3963 * the divisors, and gate it back when it is done.
3965 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3967 /* Disable SSCCTL */
3968 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3969 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3973 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3974 if (clock == 20000) {
3979 /* The iCLK virtual clock root frequency is in MHz,
3980 * but the adjusted_mode->crtc_clock in in KHz. To get the
3981 * divisors, it is necessary to divide one by another, so we
3982 * convert the virtual clock precision to KHz here for higher
3985 u32 iclk_virtual_root_freq = 172800 * 1000;
3986 u32 iclk_pi_range = 64;
3987 u32 desired_divisor, msb_divisor_value, pi_value;
3989 desired_divisor = (iclk_virtual_root_freq / clock);
3990 msb_divisor_value = desired_divisor / iclk_pi_range;
3991 pi_value = desired_divisor % iclk_pi_range;
3994 divsel = msb_divisor_value - 2;
3995 phaseinc = pi_value;
3998 /* This should not happen with any sane values */
3999 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4000 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4001 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4002 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4004 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4011 /* Program SSCDIVINTPHASE6 */
4012 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4013 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4014 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4015 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4016 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4017 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4018 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4019 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4021 /* Program SSCAUXDIV */
4022 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4023 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4024 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4025 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4027 /* Enable modulator and associated divider */
4028 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4029 temp &= ~SBI_SSCCTL_DISABLE;
4030 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4032 /* Wait for initialization time */
4035 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4037 mutex_unlock(&dev_priv->sb_lock);
4040 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4041 enum pipe pch_transcoder)
4043 struct drm_device *dev = crtc->base.dev;
4044 struct drm_i915_private *dev_priv = dev->dev_private;
4045 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4047 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4048 I915_READ(HTOTAL(cpu_transcoder)));
4049 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4050 I915_READ(HBLANK(cpu_transcoder)));
4051 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4052 I915_READ(HSYNC(cpu_transcoder)));
4054 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4055 I915_READ(VTOTAL(cpu_transcoder)));
4056 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4057 I915_READ(VBLANK(cpu_transcoder)));
4058 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4059 I915_READ(VSYNC(cpu_transcoder)));
4060 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4061 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4064 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4066 struct drm_i915_private *dev_priv = dev->dev_private;
4069 temp = I915_READ(SOUTH_CHICKEN1);
4070 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4073 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4074 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4076 temp &= ~FDI_BC_BIFURCATION_SELECT;
4078 temp |= FDI_BC_BIFURCATION_SELECT;
4080 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4081 I915_WRITE(SOUTH_CHICKEN1, temp);
4082 POSTING_READ(SOUTH_CHICKEN1);
4085 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4087 struct drm_device *dev = intel_crtc->base.dev;
4089 switch (intel_crtc->pipe) {
4093 if (intel_crtc->config->fdi_lanes > 2)
4094 cpt_set_fdi_bc_bifurcation(dev, false);
4096 cpt_set_fdi_bc_bifurcation(dev, true);
4100 cpt_set_fdi_bc_bifurcation(dev, true);
4109 * Enable PCH resources required for PCH ports:
4111 * - FDI training & RX/TX
4112 * - update transcoder timings
4113 * - DP transcoding bits
4116 static void ironlake_pch_enable(struct drm_crtc *crtc)
4118 struct drm_device *dev = crtc->dev;
4119 struct drm_i915_private *dev_priv = dev->dev_private;
4120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4121 int pipe = intel_crtc->pipe;
4124 assert_pch_transcoder_disabled(dev_priv, pipe);
4126 if (IS_IVYBRIDGE(dev))
4127 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4129 /* Write the TU size bits before fdi link training, so that error
4130 * detection works. */
4131 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4132 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4134 /* For PCH output, training FDI link */
4135 dev_priv->display.fdi_link_train(crtc);
4137 /* We need to program the right clock selection before writing the pixel
4138 * mutliplier into the DPLL. */
4139 if (HAS_PCH_CPT(dev)) {
4142 temp = I915_READ(PCH_DPLL_SEL);
4143 temp |= TRANS_DPLL_ENABLE(pipe);
4144 sel = TRANS_DPLLB_SEL(pipe);
4145 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4149 I915_WRITE(PCH_DPLL_SEL, temp);
4152 /* XXX: pch pll's can be enabled any time before we enable the PCH
4153 * transcoder, and we actually should do this to not upset any PCH
4154 * transcoder that already use the clock when we share it.
4156 * Note that enable_shared_dpll tries to do the right thing, but
4157 * get_shared_dpll unconditionally resets the pll - we need that to have
4158 * the right LVDS enable sequence. */
4159 intel_enable_shared_dpll(intel_crtc);
4161 /* set transcoder timing, panel must allow it */
4162 assert_panel_unlocked(dev_priv, pipe);
4163 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4165 intel_fdi_normal_train(crtc);
4167 /* For PCH DP, enable TRANS_DP_CTL */
4168 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4169 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4170 reg = TRANS_DP_CTL(pipe);
4171 temp = I915_READ(reg);
4172 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4173 TRANS_DP_SYNC_MASK |
4175 temp |= TRANS_DP_OUTPUT_ENABLE;
4176 temp |= bpc << 9; /* same format but at 11:9 */
4178 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4179 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4180 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4181 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4183 switch (intel_trans_dp_port_sel(crtc)) {
4185 temp |= TRANS_DP_PORT_SEL_B;
4188 temp |= TRANS_DP_PORT_SEL_C;
4191 temp |= TRANS_DP_PORT_SEL_D;
4197 I915_WRITE(reg, temp);
4200 ironlake_enable_pch_transcoder(dev_priv, pipe);
4203 static void lpt_pch_enable(struct drm_crtc *crtc)
4205 struct drm_device *dev = crtc->dev;
4206 struct drm_i915_private *dev_priv = dev->dev_private;
4207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4208 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4210 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4212 lpt_program_iclkip(crtc);
4214 /* Set transcoder timing. */
4215 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4217 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4220 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4221 struct intel_crtc_state *crtc_state)
4223 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4224 struct intel_shared_dpll *pll;
4225 struct intel_shared_dpll_config *shared_dpll;
4226 enum intel_dpll_id i;
4228 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4230 if (HAS_PCH_IBX(dev_priv->dev)) {
4231 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4232 i = (enum intel_dpll_id) crtc->pipe;
4233 pll = &dev_priv->shared_dplls[i];
4235 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4236 crtc->base.base.id, pll->name);
4238 WARN_ON(shared_dpll[i].crtc_mask);
4243 if (IS_BROXTON(dev_priv->dev)) {
4244 /* PLL is attached to port in bxt */
4245 struct intel_encoder *encoder;
4246 struct intel_digital_port *intel_dig_port;
4248 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4249 if (WARN_ON(!encoder))
4252 intel_dig_port = enc_to_dig_port(&encoder->base);
4253 /* 1:1 mapping between ports and PLLs */
4254 i = (enum intel_dpll_id)intel_dig_port->port;
4255 pll = &dev_priv->shared_dplls[i];
4256 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4257 crtc->base.base.id, pll->name);
4258 WARN_ON(shared_dpll[i].crtc_mask);
4263 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4264 pll = &dev_priv->shared_dplls[i];
4266 /* Only want to check enabled timings first */
4267 if (shared_dpll[i].crtc_mask == 0)
4270 if (memcmp(&crtc_state->dpll_hw_state,
4271 &shared_dpll[i].hw_state,
4272 sizeof(crtc_state->dpll_hw_state)) == 0) {
4273 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4274 crtc->base.base.id, pll->name,
4275 shared_dpll[i].crtc_mask,
4281 /* Ok no matching timings, maybe there's a free one? */
4282 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4283 pll = &dev_priv->shared_dplls[i];
4284 if (shared_dpll[i].crtc_mask == 0) {
4285 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4286 crtc->base.base.id, pll->name);
4294 if (shared_dpll[i].crtc_mask == 0)
4295 shared_dpll[i].hw_state =
4296 crtc_state->dpll_hw_state;
4298 crtc_state->shared_dpll = i;
4299 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4300 pipe_name(crtc->pipe));
4302 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4307 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4309 struct drm_i915_private *dev_priv = to_i915(state->dev);
4310 struct intel_shared_dpll_config *shared_dpll;
4311 struct intel_shared_dpll *pll;
4312 enum intel_dpll_id i;
4314 if (!to_intel_atomic_state(state)->dpll_set)
4317 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4318 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4319 pll = &dev_priv->shared_dplls[i];
4320 pll->config = shared_dpll[i];
4324 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4326 struct drm_i915_private *dev_priv = dev->dev_private;
4327 int dslreg = PIPEDSL(pipe);
4330 temp = I915_READ(dslreg);
4332 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4333 if (wait_for(I915_READ(dslreg) != temp, 5))
4334 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4339 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4340 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4341 int src_w, int src_h, int dst_w, int dst_h)
4343 struct intel_crtc_scaler_state *scaler_state =
4344 &crtc_state->scaler_state;
4345 struct intel_crtc *intel_crtc =
4346 to_intel_crtc(crtc_state->base.crtc);
4349 need_scaling = intel_rotation_90_or_270(rotation) ?
4350 (src_h != dst_w || src_w != dst_h):
4351 (src_w != dst_w || src_h != dst_h);
4354 * if plane is being disabled or scaler is no more required or force detach
4355 * - free scaler binded to this plane/crtc
4356 * - in order to do this, update crtc->scaler_usage
4358 * Here scaler state in crtc_state is set free so that
4359 * scaler can be assigned to other user. Actual register
4360 * update to free the scaler is done in plane/panel-fit programming.
4361 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4363 if (force_detach || !need_scaling) {
4364 if (*scaler_id >= 0) {
4365 scaler_state->scaler_users &= ~(1 << scaler_user);
4366 scaler_state->scalers[*scaler_id].in_use = 0;
4368 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4369 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4370 intel_crtc->pipe, scaler_user, *scaler_id,
4371 scaler_state->scaler_users);
4378 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4379 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4381 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4382 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4383 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4384 "size is out of scaler range\n",
4385 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4389 /* mark this plane as a scaler user in crtc_state */
4390 scaler_state->scaler_users |= (1 << scaler_user);
4391 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4392 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4393 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4394 scaler_state->scaler_users);
4400 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4402 * @state: crtc's scaler state
4405 * 0 - scaler_usage updated successfully
4406 * error - requested scaling cannot be supported or other error condition
4408 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4410 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4411 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4413 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4414 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4416 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4417 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4418 state->pipe_src_w, state->pipe_src_h,
4419 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4423 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4425 * @state: crtc's scaler state
4426 * @plane_state: atomic plane state to update
4429 * 0 - scaler_usage updated successfully
4430 * error - requested scaling cannot be supported or other error condition
4432 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4433 struct intel_plane_state *plane_state)
4436 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4437 struct intel_plane *intel_plane =
4438 to_intel_plane(plane_state->base.plane);
4439 struct drm_framebuffer *fb = plane_state->base.fb;
4442 bool force_detach = !fb || !plane_state->visible;
4444 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4445 intel_plane->base.base.id, intel_crtc->pipe,
4446 drm_plane_index(&intel_plane->base));
4448 ret = skl_update_scaler(crtc_state, force_detach,
4449 drm_plane_index(&intel_plane->base),
4450 &plane_state->scaler_id,
4451 plane_state->base.rotation,
4452 drm_rect_width(&plane_state->src) >> 16,
4453 drm_rect_height(&plane_state->src) >> 16,
4454 drm_rect_width(&plane_state->dst),
4455 drm_rect_height(&plane_state->dst));
4457 if (ret || plane_state->scaler_id < 0)
4460 /* check colorkey */
4461 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4462 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4463 intel_plane->base.base.id);
4467 /* Check src format */
4468 switch (fb->pixel_format) {
4469 case DRM_FORMAT_RGB565:
4470 case DRM_FORMAT_XBGR8888:
4471 case DRM_FORMAT_XRGB8888:
4472 case DRM_FORMAT_ABGR8888:
4473 case DRM_FORMAT_ARGB8888:
4474 case DRM_FORMAT_XRGB2101010:
4475 case DRM_FORMAT_XBGR2101010:
4476 case DRM_FORMAT_YUYV:
4477 case DRM_FORMAT_YVYU:
4478 case DRM_FORMAT_UYVY:
4479 case DRM_FORMAT_VYUY:
4482 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4483 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4490 static void skylake_scaler_disable(struct intel_crtc *crtc)
4494 for (i = 0; i < crtc->num_scalers; i++)
4495 skl_detach_scaler(crtc, i);
4498 static void skylake_pfit_enable(struct intel_crtc *crtc)
4500 struct drm_device *dev = crtc->base.dev;
4501 struct drm_i915_private *dev_priv = dev->dev_private;
4502 int pipe = crtc->pipe;
4503 struct intel_crtc_scaler_state *scaler_state =
4504 &crtc->config->scaler_state;
4506 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4508 if (crtc->config->pch_pfit.enabled) {
4511 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4512 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4516 id = scaler_state->scaler_id;
4517 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4518 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4519 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4520 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4522 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4526 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4528 struct drm_device *dev = crtc->base.dev;
4529 struct drm_i915_private *dev_priv = dev->dev_private;
4530 int pipe = crtc->pipe;
4532 if (crtc->config->pch_pfit.enabled) {
4533 /* Force use of hard-coded filter coefficients
4534 * as some pre-programmed values are broken,
4537 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4538 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4539 PF_PIPE_SEL_IVB(pipe));
4541 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4542 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4543 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4547 void hsw_enable_ips(struct intel_crtc *crtc)
4549 struct drm_device *dev = crtc->base.dev;
4550 struct drm_i915_private *dev_priv = dev->dev_private;
4552 if (!crtc->config->ips_enabled)
4555 /* We can only enable IPS after we enable a plane and wait for a vblank */
4556 intel_wait_for_vblank(dev, crtc->pipe);
4558 assert_plane_enabled(dev_priv, crtc->plane);
4559 if (IS_BROADWELL(dev)) {
4560 mutex_lock(&dev_priv->rps.hw_lock);
4561 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4562 mutex_unlock(&dev_priv->rps.hw_lock);
4563 /* Quoting Art Runyan: "its not safe to expect any particular
4564 * value in IPS_CTL bit 31 after enabling IPS through the
4565 * mailbox." Moreover, the mailbox may return a bogus state,
4566 * so we need to just enable it and continue on.
4569 I915_WRITE(IPS_CTL, IPS_ENABLE);
4570 /* The bit only becomes 1 in the next vblank, so this wait here
4571 * is essentially intel_wait_for_vblank. If we don't have this
4572 * and don't wait for vblanks until the end of crtc_enable, then
4573 * the HW state readout code will complain that the expected
4574 * IPS_CTL value is not the one we read. */
4575 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4576 DRM_ERROR("Timed out waiting for IPS enable\n");
4580 void hsw_disable_ips(struct intel_crtc *crtc)
4582 struct drm_device *dev = crtc->base.dev;
4583 struct drm_i915_private *dev_priv = dev->dev_private;
4585 if (!crtc->config->ips_enabled)
4588 assert_plane_enabled(dev_priv, crtc->plane);
4589 if (IS_BROADWELL(dev)) {
4590 mutex_lock(&dev_priv->rps.hw_lock);
4591 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4592 mutex_unlock(&dev_priv->rps.hw_lock);
4593 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4594 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4595 DRM_ERROR("Timed out waiting for IPS disable\n");
4597 I915_WRITE(IPS_CTL, 0);
4598 POSTING_READ(IPS_CTL);
4601 /* We need to wait for a vblank before we can disable the plane. */
4602 intel_wait_for_vblank(dev, crtc->pipe);
4605 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4606 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4608 struct drm_device *dev = crtc->dev;
4609 struct drm_i915_private *dev_priv = dev->dev_private;
4610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4611 enum pipe pipe = intel_crtc->pipe;
4613 bool reenable_ips = false;
4615 /* The clocks have to be on to load the palette. */
4616 if (!crtc->state->active)
4619 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4620 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4621 assert_dsi_pll_enabled(dev_priv);
4623 assert_pll_enabled(dev_priv, pipe);
4626 /* Workaround : Do not read or write the pipe palette/gamma data while
4627 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4629 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4630 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4631 GAMMA_MODE_MODE_SPLIT)) {
4632 hsw_disable_ips(intel_crtc);
4633 reenable_ips = true;
4636 for (i = 0; i < 256; i++) {
4639 if (HAS_GMCH_DISPLAY(dev))
4640 palreg = PALETTE(pipe, i);
4642 palreg = LGC_PALETTE(pipe, i);
4645 (intel_crtc->lut_r[i] << 16) |
4646 (intel_crtc->lut_g[i] << 8) |
4647 intel_crtc->lut_b[i]);
4651 hsw_enable_ips(intel_crtc);
4654 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4656 if (intel_crtc->overlay) {
4657 struct drm_device *dev = intel_crtc->base.dev;
4658 struct drm_i915_private *dev_priv = dev->dev_private;
4660 mutex_lock(&dev->struct_mutex);
4661 dev_priv->mm.interruptible = false;
4662 (void) intel_overlay_switch_off(intel_crtc->overlay);
4663 dev_priv->mm.interruptible = true;
4664 mutex_unlock(&dev->struct_mutex);
4667 /* Let userspace switch the overlay on again. In most cases userspace
4668 * has to recompute where to put it anyway.
4673 * intel_post_enable_primary - Perform operations after enabling primary plane
4674 * @crtc: the CRTC whose primary plane was just enabled
4676 * Performs potentially sleeping operations that must be done after the primary
4677 * plane is enabled, such as updating FBC and IPS. Note that this may be
4678 * called due to an explicit primary plane update, or due to an implicit
4679 * re-enable that is caused when a sprite plane is updated to no longer
4680 * completely hide the primary plane.
4683 intel_post_enable_primary(struct drm_crtc *crtc)
4685 struct drm_device *dev = crtc->dev;
4686 struct drm_i915_private *dev_priv = dev->dev_private;
4687 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4688 int pipe = intel_crtc->pipe;
4691 * BDW signals flip done immediately if the plane
4692 * is disabled, even if the plane enable is already
4693 * armed to occur at the next vblank :(
4695 if (IS_BROADWELL(dev))
4696 intel_wait_for_vblank(dev, pipe);
4699 * FIXME IPS should be fine as long as one plane is
4700 * enabled, but in practice it seems to have problems
4701 * when going from primary only to sprite only and vice
4704 hsw_enable_ips(intel_crtc);
4707 * Gen2 reports pipe underruns whenever all planes are disabled.
4708 * So don't enable underrun reporting before at least some planes
4710 * FIXME: Need to fix the logic to work when we turn off all planes
4711 * but leave the pipe running.
4714 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4716 /* Underruns don't raise interrupts, so check manually. */
4717 if (HAS_GMCH_DISPLAY(dev))
4718 i9xx_check_fifo_underruns(dev_priv);
4722 * intel_pre_disable_primary - Perform operations before disabling primary plane
4723 * @crtc: the CRTC whose primary plane is to be disabled
4725 * Performs potentially sleeping operations that must be done before the
4726 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4727 * be called due to an explicit primary plane update, or due to an implicit
4728 * disable that is caused when a sprite plane completely hides the primary
4732 intel_pre_disable_primary(struct drm_crtc *crtc)
4734 struct drm_device *dev = crtc->dev;
4735 struct drm_i915_private *dev_priv = dev->dev_private;
4736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4737 int pipe = intel_crtc->pipe;
4740 * Gen2 reports pipe underruns whenever all planes are disabled.
4741 * So diasble underrun reporting before all the planes get disabled.
4742 * FIXME: Need to fix the logic to work when we turn off all planes
4743 * but leave the pipe running.
4746 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4749 * Vblank time updates from the shadow to live plane control register
4750 * are blocked if the memory self-refresh mode is active at that
4751 * moment. So to make sure the plane gets truly disabled, disable
4752 * first the self-refresh mode. The self-refresh enable bit in turn
4753 * will be checked/applied by the HW only at the next frame start
4754 * event which is after the vblank start event, so we need to have a
4755 * wait-for-vblank between disabling the plane and the pipe.
4757 if (HAS_GMCH_DISPLAY(dev)) {
4758 intel_set_memory_cxsr(dev_priv, false);
4759 dev_priv->wm.vlv.cxsr = false;
4760 intel_wait_for_vblank(dev, pipe);
4764 * FIXME IPS should be fine as long as one plane is
4765 * enabled, but in practice it seems to have problems
4766 * when going from primary only to sprite only and vice
4769 hsw_disable_ips(intel_crtc);
4772 static void intel_post_plane_update(struct intel_crtc *crtc)
4774 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4775 struct drm_device *dev = crtc->base.dev;
4776 struct drm_i915_private *dev_priv = dev->dev_private;
4777 struct drm_plane *plane;
4779 if (atomic->wait_vblank)
4780 intel_wait_for_vblank(dev, crtc->pipe);
4782 intel_frontbuffer_flip(dev, atomic->fb_bits);
4784 if (atomic->disable_cxsr)
4785 crtc->wm.cxsr_allowed = true;
4787 if (crtc->atomic.update_wm_post)
4788 intel_update_watermarks(&crtc->base);
4790 if (atomic->update_fbc)
4791 intel_fbc_update(dev_priv);
4793 if (atomic->post_enable_primary)
4794 intel_post_enable_primary(&crtc->base);
4796 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4797 intel_update_sprite_watermarks(plane, &crtc->base,
4798 0, 0, 0, false, false);
4800 memset(atomic, 0, sizeof(*atomic));
4803 static void intel_pre_plane_update(struct intel_crtc *crtc)
4805 struct drm_device *dev = crtc->base.dev;
4806 struct drm_i915_private *dev_priv = dev->dev_private;
4807 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4808 struct drm_plane *p;
4810 /* Track fb's for any planes being disabled */
4811 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4812 struct intel_plane *plane = to_intel_plane(p);
4814 mutex_lock(&dev->struct_mutex);
4815 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4816 plane->frontbuffer_bit);
4817 mutex_unlock(&dev->struct_mutex);
4820 if (atomic->wait_for_flips)
4821 intel_crtc_wait_for_pending_flips(&crtc->base);
4823 if (atomic->disable_fbc)
4824 intel_fbc_disable_crtc(crtc);
4826 if (crtc->atomic.disable_ips)
4827 hsw_disable_ips(crtc);
4829 if (atomic->pre_disable_primary)
4830 intel_pre_disable_primary(&crtc->base);
4832 if (atomic->disable_cxsr) {
4833 crtc->wm.cxsr_allowed = false;
4834 intel_set_memory_cxsr(dev_priv, false);
4838 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4840 struct drm_device *dev = crtc->dev;
4841 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4842 struct drm_plane *p;
4843 int pipe = intel_crtc->pipe;
4845 intel_crtc_dpms_overlay_disable(intel_crtc);
4847 drm_for_each_plane_mask(p, dev, plane_mask)
4848 to_intel_plane(p)->disable_plane(p, crtc);
4851 * FIXME: Once we grow proper nuclear flip support out of this we need
4852 * to compute the mask of flip planes precisely. For the time being
4853 * consider this a flip to a NULL plane.
4855 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4858 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4860 struct drm_device *dev = crtc->dev;
4861 struct drm_i915_private *dev_priv = dev->dev_private;
4862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4863 struct intel_encoder *encoder;
4864 int pipe = intel_crtc->pipe;
4866 if (WARN_ON(intel_crtc->active))
4869 if (intel_crtc->config->has_pch_encoder)
4870 intel_prepare_shared_dpll(intel_crtc);
4872 if (intel_crtc->config->has_dp_encoder)
4873 intel_dp_set_m_n(intel_crtc, M1_N1);
4875 intel_set_pipe_timings(intel_crtc);
4877 if (intel_crtc->config->has_pch_encoder) {
4878 intel_cpu_transcoder_set_m_n(intel_crtc,
4879 &intel_crtc->config->fdi_m_n, NULL);
4882 ironlake_set_pipeconf(crtc);
4884 intel_crtc->active = true;
4886 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4887 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4889 for_each_encoder_on_crtc(dev, crtc, encoder)
4890 if (encoder->pre_enable)
4891 encoder->pre_enable(encoder);
4893 if (intel_crtc->config->has_pch_encoder) {
4894 /* Note: FDI PLL enabling _must_ be done before we enable the
4895 * cpu pipes, hence this is separate from all the other fdi/pch
4897 ironlake_fdi_pll_enable(intel_crtc);
4899 assert_fdi_tx_disabled(dev_priv, pipe);
4900 assert_fdi_rx_disabled(dev_priv, pipe);
4903 ironlake_pfit_enable(intel_crtc);
4906 * On ILK+ LUT must be loaded before the pipe is running but with
4909 intel_crtc_load_lut(crtc);
4911 intel_update_watermarks(crtc);
4912 intel_enable_pipe(intel_crtc);
4914 if (intel_crtc->config->has_pch_encoder)
4915 ironlake_pch_enable(crtc);
4917 assert_vblank_disabled(crtc);
4918 drm_crtc_vblank_on(crtc);
4920 for_each_encoder_on_crtc(dev, crtc, encoder)
4921 encoder->enable(encoder);
4923 if (HAS_PCH_CPT(dev))
4924 cpt_verify_modeset(dev, intel_crtc->pipe);
4927 /* IPS only exists on ULT machines and is tied to pipe A. */
4928 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4930 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4933 static void haswell_crtc_enable(struct drm_crtc *crtc)
4935 struct drm_device *dev = crtc->dev;
4936 struct drm_i915_private *dev_priv = dev->dev_private;
4937 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4938 struct intel_encoder *encoder;
4939 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4940 struct intel_crtc_state *pipe_config =
4941 to_intel_crtc_state(crtc->state);
4942 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4944 if (WARN_ON(intel_crtc->active))
4947 if (intel_crtc_to_shared_dpll(intel_crtc))
4948 intel_enable_shared_dpll(intel_crtc);
4950 if (intel_crtc->config->has_dp_encoder)
4951 intel_dp_set_m_n(intel_crtc, M1_N1);
4953 intel_set_pipe_timings(intel_crtc);
4955 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4956 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4957 intel_crtc->config->pixel_multiplier - 1);
4960 if (intel_crtc->config->has_pch_encoder) {
4961 intel_cpu_transcoder_set_m_n(intel_crtc,
4962 &intel_crtc->config->fdi_m_n, NULL);
4965 haswell_set_pipeconf(crtc);
4967 intel_set_pipe_csc(crtc);
4969 intel_crtc->active = true;
4971 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4972 for_each_encoder_on_crtc(dev, crtc, encoder) {
4973 if (encoder->pre_pll_enable)
4974 encoder->pre_pll_enable(encoder);
4975 if (encoder->pre_enable)
4976 encoder->pre_enable(encoder);
4979 if (intel_crtc->config->has_pch_encoder) {
4980 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4982 dev_priv->display.fdi_link_train(crtc);
4986 intel_ddi_enable_pipe_clock(intel_crtc);
4988 if (INTEL_INFO(dev)->gen >= 9)
4989 skylake_pfit_enable(intel_crtc);
4991 ironlake_pfit_enable(intel_crtc);
4994 * On ILK+ LUT must be loaded before the pipe is running but with
4997 intel_crtc_load_lut(crtc);
4999 intel_ddi_set_pipe_settings(crtc);
5001 intel_ddi_enable_transcoder_func(crtc);
5003 intel_update_watermarks(crtc);
5004 intel_enable_pipe(intel_crtc);
5006 if (intel_crtc->config->has_pch_encoder)
5007 lpt_pch_enable(crtc);
5009 if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
5010 intel_ddi_set_vc_payload_alloc(crtc, true);
5012 assert_vblank_disabled(crtc);
5013 drm_crtc_vblank_on(crtc);
5015 for_each_encoder_on_crtc(dev, crtc, encoder) {
5016 encoder->enable(encoder);
5017 intel_opregion_notify_encoder(encoder, true);
5020 /* If we change the relative order between pipe/planes enabling, we need
5021 * to change the workaround. */
5022 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5023 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5024 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5025 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5029 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5031 struct drm_device *dev = crtc->base.dev;
5032 struct drm_i915_private *dev_priv = dev->dev_private;
5033 int pipe = crtc->pipe;
5035 /* To avoid upsetting the power well on haswell only disable the pfit if
5036 * it's in use. The hw state code will make sure we get this right. */
5037 if (force || crtc->config->pch_pfit.enabled) {
5038 I915_WRITE(PF_CTL(pipe), 0);
5039 I915_WRITE(PF_WIN_POS(pipe), 0);
5040 I915_WRITE(PF_WIN_SZ(pipe), 0);
5044 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5046 struct drm_device *dev = crtc->dev;
5047 struct drm_i915_private *dev_priv = dev->dev_private;
5048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5049 struct intel_encoder *encoder;
5050 int pipe = intel_crtc->pipe;
5053 for_each_encoder_on_crtc(dev, crtc, encoder)
5054 encoder->disable(encoder);
5056 drm_crtc_vblank_off(crtc);
5057 assert_vblank_disabled(crtc);
5059 if (intel_crtc->config->has_pch_encoder)
5060 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5062 intel_disable_pipe(intel_crtc);
5064 ironlake_pfit_disable(intel_crtc, false);
5066 if (intel_crtc->config->has_pch_encoder)
5067 ironlake_fdi_disable(crtc);
5069 for_each_encoder_on_crtc(dev, crtc, encoder)
5070 if (encoder->post_disable)
5071 encoder->post_disable(encoder);
5073 if (intel_crtc->config->has_pch_encoder) {
5074 ironlake_disable_pch_transcoder(dev_priv, pipe);
5076 if (HAS_PCH_CPT(dev)) {
5077 /* disable TRANS_DP_CTL */
5078 reg = TRANS_DP_CTL(pipe);
5079 temp = I915_READ(reg);
5080 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5081 TRANS_DP_PORT_SEL_MASK);
5082 temp |= TRANS_DP_PORT_SEL_NONE;
5083 I915_WRITE(reg, temp);
5085 /* disable DPLL_SEL */
5086 temp = I915_READ(PCH_DPLL_SEL);
5087 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5088 I915_WRITE(PCH_DPLL_SEL, temp);
5091 ironlake_fdi_pll_disable(intel_crtc);
5095 static void haswell_crtc_disable(struct drm_crtc *crtc)
5097 struct drm_device *dev = crtc->dev;
5098 struct drm_i915_private *dev_priv = dev->dev_private;
5099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5100 struct intel_encoder *encoder;
5101 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5102 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5104 for_each_encoder_on_crtc(dev, crtc, encoder) {
5105 intel_opregion_notify_encoder(encoder, false);
5106 encoder->disable(encoder);
5109 drm_crtc_vblank_off(crtc);
5110 assert_vblank_disabled(crtc);
5112 if (intel_crtc->config->has_pch_encoder)
5113 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5115 intel_disable_pipe(intel_crtc);
5117 if (intel_crtc->config->dp_encoder_is_mst)
5118 intel_ddi_set_vc_payload_alloc(crtc, false);
5121 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5123 if (INTEL_INFO(dev)->gen >= 9)
5124 skylake_scaler_disable(intel_crtc);
5126 ironlake_pfit_disable(intel_crtc, false);
5129 intel_ddi_disable_pipe_clock(intel_crtc);
5131 if (intel_crtc->config->has_pch_encoder) {
5132 lpt_disable_pch_transcoder(dev_priv);
5133 intel_ddi_fdi_disable(crtc);
5136 for_each_encoder_on_crtc(dev, crtc, encoder)
5137 if (encoder->post_disable)
5138 encoder->post_disable(encoder);
5141 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5143 struct drm_device *dev = crtc->base.dev;
5144 struct drm_i915_private *dev_priv = dev->dev_private;
5145 struct intel_crtc_state *pipe_config = crtc->config;
5147 if (!pipe_config->gmch_pfit.control)
5151 * The panel fitter should only be adjusted whilst the pipe is disabled,
5152 * according to register description and PRM.
5154 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5155 assert_pipe_disabled(dev_priv, crtc->pipe);
5157 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5158 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5160 /* Border color in case we don't scale up to the full screen. Black by
5161 * default, change to something else for debugging. */
5162 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5165 static enum intel_display_power_domain port_to_power_domain(enum port port)
5169 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5171 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5173 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5175 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5177 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
5180 return POWER_DOMAIN_PORT_OTHER;
5184 #define for_each_power_domain(domain, mask) \
5185 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5186 if ((1 << (domain)) & (mask))
5188 enum intel_display_power_domain
5189 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5191 struct drm_device *dev = intel_encoder->base.dev;
5192 struct intel_digital_port *intel_dig_port;
5194 switch (intel_encoder->type) {
5195 case INTEL_OUTPUT_UNKNOWN:
5196 /* Only DDI platforms should ever use this output type */
5197 WARN_ON_ONCE(!HAS_DDI(dev));
5198 case INTEL_OUTPUT_DISPLAYPORT:
5199 case INTEL_OUTPUT_HDMI:
5200 case INTEL_OUTPUT_EDP:
5201 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5202 return port_to_power_domain(intel_dig_port->port);
5203 case INTEL_OUTPUT_DP_MST:
5204 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5205 return port_to_power_domain(intel_dig_port->port);
5206 case INTEL_OUTPUT_ANALOG:
5207 return POWER_DOMAIN_PORT_CRT;
5208 case INTEL_OUTPUT_DSI:
5209 return POWER_DOMAIN_PORT_DSI;
5211 return POWER_DOMAIN_PORT_OTHER;
5215 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5217 struct drm_device *dev = crtc->dev;
5218 struct intel_encoder *intel_encoder;
5219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5220 enum pipe pipe = intel_crtc->pipe;
5222 enum transcoder transcoder;
5224 if (!crtc->state->active)
5227 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5229 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5230 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5231 if (intel_crtc->config->pch_pfit.enabled ||
5232 intel_crtc->config->pch_pfit.force_thru)
5233 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5235 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5236 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5241 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5243 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5245 enum intel_display_power_domain domain;
5246 unsigned long domains, new_domains, old_domains;
5248 old_domains = intel_crtc->enabled_power_domains;
5249 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5251 domains = new_domains & ~old_domains;
5253 for_each_power_domain(domain, domains)
5254 intel_display_power_get(dev_priv, domain);
5256 return old_domains & ~new_domains;
5259 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5260 unsigned long domains)
5262 enum intel_display_power_domain domain;
5264 for_each_power_domain(domain, domains)
5265 intel_display_power_put(dev_priv, domain);
5268 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5270 struct drm_device *dev = state->dev;
5271 struct drm_i915_private *dev_priv = dev->dev_private;
5272 unsigned long put_domains[I915_MAX_PIPES] = {};
5273 struct drm_crtc_state *crtc_state;
5274 struct drm_crtc *crtc;
5277 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5278 if (needs_modeset(crtc->state))
5279 put_domains[to_intel_crtc(crtc)->pipe] =
5280 modeset_get_crtc_power_domains(crtc);
5283 if (dev_priv->display.modeset_commit_cdclk) {
5284 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5286 if (cdclk != dev_priv->cdclk_freq &&
5287 !WARN_ON(!state->allow_modeset))
5288 dev_priv->display.modeset_commit_cdclk(state);
5291 for (i = 0; i < I915_MAX_PIPES; i++)
5293 modeset_put_power_domains(dev_priv, put_domains[i]);
5296 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5298 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5300 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5301 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5302 return max_cdclk_freq;
5303 else if (IS_CHERRYVIEW(dev_priv))
5304 return max_cdclk_freq*95/100;
5305 else if (INTEL_INFO(dev_priv)->gen < 4)
5306 return 2*max_cdclk_freq*90/100;
5308 return max_cdclk_freq*90/100;
5311 static void intel_update_max_cdclk(struct drm_device *dev)
5313 struct drm_i915_private *dev_priv = dev->dev_private;
5315 if (IS_SKYLAKE(dev)) {
5316 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5318 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5319 dev_priv->max_cdclk_freq = 675000;
5320 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5321 dev_priv->max_cdclk_freq = 540000;
5322 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5323 dev_priv->max_cdclk_freq = 450000;
5325 dev_priv->max_cdclk_freq = 337500;
5326 } else if (IS_BROADWELL(dev)) {
5328 * FIXME with extra cooling we can allow
5329 * 540 MHz for ULX and 675 Mhz for ULT.
5330 * How can we know if extra cooling is
5331 * available? PCI ID, VTB, something else?
5333 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5334 dev_priv->max_cdclk_freq = 450000;
5335 else if (IS_BDW_ULX(dev))
5336 dev_priv->max_cdclk_freq = 450000;
5337 else if (IS_BDW_ULT(dev))
5338 dev_priv->max_cdclk_freq = 540000;
5340 dev_priv->max_cdclk_freq = 675000;
5341 } else if (IS_CHERRYVIEW(dev)) {
5342 dev_priv->max_cdclk_freq = 320000;
5343 } else if (IS_VALLEYVIEW(dev)) {
5344 dev_priv->max_cdclk_freq = 400000;
5346 /* otherwise assume cdclk is fixed */
5347 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5350 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5352 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5353 dev_priv->max_cdclk_freq);
5355 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5356 dev_priv->max_dotclk_freq);
5359 static void intel_update_cdclk(struct drm_device *dev)
5361 struct drm_i915_private *dev_priv = dev->dev_private;
5363 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5364 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5365 dev_priv->cdclk_freq);
5368 * Program the gmbus_freq based on the cdclk frequency.
5369 * BSpec erroneously claims we should aim for 4MHz, but
5370 * in fact 1MHz is the correct frequency.
5372 if (IS_VALLEYVIEW(dev)) {
5374 * Program the gmbus_freq based on the cdclk frequency.
5375 * BSpec erroneously claims we should aim for 4MHz, but
5376 * in fact 1MHz is the correct frequency.
5378 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5381 if (dev_priv->max_cdclk_freq == 0)
5382 intel_update_max_cdclk(dev);
5385 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5387 struct drm_i915_private *dev_priv = dev->dev_private;
5390 uint32_t current_freq;
5393 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5394 switch (frequency) {
5396 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5397 ratio = BXT_DE_PLL_RATIO(60);
5400 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5401 ratio = BXT_DE_PLL_RATIO(60);
5404 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5405 ratio = BXT_DE_PLL_RATIO(60);
5408 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5409 ratio = BXT_DE_PLL_RATIO(60);
5412 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5413 ratio = BXT_DE_PLL_RATIO(65);
5417 * Bypass frequency with DE PLL disabled. Init ratio, divider
5418 * to suppress GCC warning.
5424 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5429 mutex_lock(&dev_priv->rps.hw_lock);
5430 /* Inform power controller of upcoming frequency change */
5431 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5433 mutex_unlock(&dev_priv->rps.hw_lock);
5436 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5441 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5442 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5443 current_freq = current_freq * 500 + 1000;
5446 * DE PLL has to be disabled when
5447 * - setting to 19.2MHz (bypass, PLL isn't used)
5448 * - before setting to 624MHz (PLL needs toggling)
5449 * - before setting to any frequency from 624MHz (PLL needs toggling)
5451 if (frequency == 19200 || frequency == 624000 ||
5452 current_freq == 624000) {
5453 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5455 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5457 DRM_ERROR("timout waiting for DE PLL unlock\n");
5460 if (frequency != 19200) {
5463 val = I915_READ(BXT_DE_PLL_CTL);
5464 val &= ~BXT_DE_PLL_RATIO_MASK;
5466 I915_WRITE(BXT_DE_PLL_CTL, val);
5468 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5470 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5471 DRM_ERROR("timeout waiting for DE PLL lock\n");
5473 val = I915_READ(CDCLK_CTL);
5474 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5477 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5480 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5481 if (frequency >= 500000)
5482 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5484 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5485 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5486 val |= (frequency - 1000) / 500;
5487 I915_WRITE(CDCLK_CTL, val);
5490 mutex_lock(&dev_priv->rps.hw_lock);
5491 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5492 DIV_ROUND_UP(frequency, 25000));
5493 mutex_unlock(&dev_priv->rps.hw_lock);
5496 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5501 intel_update_cdclk(dev);
5504 void broxton_init_cdclk(struct drm_device *dev)
5506 struct drm_i915_private *dev_priv = dev->dev_private;
5510 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5511 * or else the reset will hang because there is no PCH to respond.
5512 * Move the handshake programming to initialization sequence.
5513 * Previously was left up to BIOS.
5515 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5516 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5517 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5519 /* Enable PG1 for cdclk */
5520 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5522 /* check if cd clock is enabled */
5523 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5524 DRM_DEBUG_KMS("Display already initialized\n");
5530 * - The initial CDCLK needs to be read from VBT.
5531 * Need to make this change after VBT has changes for BXT.
5532 * - check if setting the max (or any) cdclk freq is really necessary
5533 * here, it belongs to modeset time
5535 broxton_set_cdclk(dev, 624000);
5537 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5538 POSTING_READ(DBUF_CTL);
5542 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5543 DRM_ERROR("DBuf power enable timeout!\n");
5546 void broxton_uninit_cdclk(struct drm_device *dev)
5548 struct drm_i915_private *dev_priv = dev->dev_private;
5550 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5551 POSTING_READ(DBUF_CTL);
5555 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5556 DRM_ERROR("DBuf power disable timeout!\n");
5558 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5559 broxton_set_cdclk(dev, 19200);
5561 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5564 static const struct skl_cdclk_entry {
5567 } skl_cdclk_frequencies[] = {
5568 { .freq = 308570, .vco = 8640 },
5569 { .freq = 337500, .vco = 8100 },
5570 { .freq = 432000, .vco = 8640 },
5571 { .freq = 450000, .vco = 8100 },
5572 { .freq = 540000, .vco = 8100 },
5573 { .freq = 617140, .vco = 8640 },
5574 { .freq = 675000, .vco = 8100 },
5577 static unsigned int skl_cdclk_decimal(unsigned int freq)
5579 return (freq - 1000) / 500;
5582 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5586 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5587 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5589 if (e->freq == freq)
5597 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5599 unsigned int min_freq;
5602 /* select the minimum CDCLK before enabling DPLL 0 */
5603 val = I915_READ(CDCLK_CTL);
5604 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5605 val |= CDCLK_FREQ_337_308;
5607 if (required_vco == 8640)
5612 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5614 I915_WRITE(CDCLK_CTL, val);
5615 POSTING_READ(CDCLK_CTL);
5618 * We always enable DPLL0 with the lowest link rate possible, but still
5619 * taking into account the VCO required to operate the eDP panel at the
5620 * desired frequency. The usual DP link rates operate with a VCO of
5621 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5622 * The modeset code is responsible for the selection of the exact link
5623 * rate later on, with the constraint of choosing a frequency that
5624 * works with required_vco.
5626 val = I915_READ(DPLL_CTRL1);
5628 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5629 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5630 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5631 if (required_vco == 8640)
5632 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5635 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5638 I915_WRITE(DPLL_CTRL1, val);
5639 POSTING_READ(DPLL_CTRL1);
5641 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5643 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5644 DRM_ERROR("DPLL0 not locked\n");
5647 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5652 /* inform PCU we want to change CDCLK */
5653 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5654 mutex_lock(&dev_priv->rps.hw_lock);
5655 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5656 mutex_unlock(&dev_priv->rps.hw_lock);
5658 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5661 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5665 for (i = 0; i < 15; i++) {
5666 if (skl_cdclk_pcu_ready(dev_priv))
5674 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5676 struct drm_device *dev = dev_priv->dev;
5677 u32 freq_select, pcu_ack;
5679 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5681 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5682 DRM_ERROR("failed to inform PCU about cdclk change\n");
5690 freq_select = CDCLK_FREQ_450_432;
5694 freq_select = CDCLK_FREQ_540;
5700 freq_select = CDCLK_FREQ_337_308;
5705 freq_select = CDCLK_FREQ_675_617;
5710 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5711 POSTING_READ(CDCLK_CTL);
5713 /* inform PCU of the change */
5714 mutex_lock(&dev_priv->rps.hw_lock);
5715 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5716 mutex_unlock(&dev_priv->rps.hw_lock);
5718 intel_update_cdclk(dev);
5721 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5723 /* disable DBUF power */
5724 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5725 POSTING_READ(DBUF_CTL);
5729 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5730 DRM_ERROR("DBuf power disable timeout\n");
5733 * DMC assumes ownership of LCPLL and will get confused if we touch it.
5735 if (dev_priv->csr.dmc_payload) {
5737 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
5739 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5740 DRM_ERROR("Couldn't disable DPLL0\n");
5743 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5746 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5749 unsigned int required_vco;
5751 /* enable PCH reset handshake */
5752 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5753 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5755 /* enable PG1 and Misc I/O */
5756 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5758 /* DPLL0 not enabled (happens on early BIOS versions) */
5759 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5761 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5762 skl_dpll0_enable(dev_priv, required_vco);
5765 /* set CDCLK to the frequency the BIOS chose */
5766 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5768 /* enable DBUF power */
5769 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5770 POSTING_READ(DBUF_CTL);
5774 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5775 DRM_ERROR("DBuf power enable timeout\n");
5778 /* Adjust CDclk dividers to allow high res or save power if possible */
5779 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5781 struct drm_i915_private *dev_priv = dev->dev_private;
5784 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5785 != dev_priv->cdclk_freq);
5787 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5789 else if (cdclk == 266667)
5794 mutex_lock(&dev_priv->rps.hw_lock);
5795 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5796 val &= ~DSPFREQGUAR_MASK;
5797 val |= (cmd << DSPFREQGUAR_SHIFT);
5798 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5799 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5800 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5802 DRM_ERROR("timed out waiting for CDclk change\n");
5804 mutex_unlock(&dev_priv->rps.hw_lock);
5806 mutex_lock(&dev_priv->sb_lock);
5808 if (cdclk == 400000) {
5811 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5813 /* adjust cdclk divider */
5814 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5815 val &= ~CCK_FREQUENCY_VALUES;
5817 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5819 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5820 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5822 DRM_ERROR("timed out waiting for CDclk change\n");
5825 /* adjust self-refresh exit latency value */
5826 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5830 * For high bandwidth configs, we set a higher latency in the bunit
5831 * so that the core display fetch happens in time to avoid underruns.
5833 if (cdclk == 400000)
5834 val |= 4500 / 250; /* 4.5 usec */
5836 val |= 3000 / 250; /* 3.0 usec */
5837 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5839 mutex_unlock(&dev_priv->sb_lock);
5841 intel_update_cdclk(dev);
5844 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5846 struct drm_i915_private *dev_priv = dev->dev_private;
5849 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5850 != dev_priv->cdclk_freq);
5859 MISSING_CASE(cdclk);
5864 * Specs are full of misinformation, but testing on actual
5865 * hardware has shown that we just need to write the desired
5866 * CCK divider into the Punit register.
5868 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5870 mutex_lock(&dev_priv->rps.hw_lock);
5871 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5872 val &= ~DSPFREQGUAR_MASK_CHV;
5873 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5874 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5875 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5876 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5878 DRM_ERROR("timed out waiting for CDclk change\n");
5880 mutex_unlock(&dev_priv->rps.hw_lock);
5882 intel_update_cdclk(dev);
5885 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5888 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5889 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5892 * Really only a few cases to deal with, as only 4 CDclks are supported:
5895 * 320/333MHz (depends on HPLL freq)
5897 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5898 * of the lower bin and adjust if needed.
5900 * We seem to get an unstable or solid color picture at 200MHz.
5901 * Not sure what's wrong. For now use 200MHz only when all pipes
5904 if (!IS_CHERRYVIEW(dev_priv) &&
5905 max_pixclk > freq_320*limit/100)
5907 else if (max_pixclk > 266667*limit/100)
5909 else if (max_pixclk > 0)
5915 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5920 * - remove the guardband, it's not needed on BXT
5921 * - set 19.2MHz bypass frequency if there are no active pipes
5923 if (max_pixclk > 576000*9/10)
5925 else if (max_pixclk > 384000*9/10)
5927 else if (max_pixclk > 288000*9/10)
5929 else if (max_pixclk > 144000*9/10)
5935 /* Compute the max pixel clock for new configuration. Uses atomic state if
5936 * that's non-NULL, look at current state otherwise. */
5937 static int intel_mode_max_pixclk(struct drm_device *dev,
5938 struct drm_atomic_state *state)
5940 struct intel_crtc *intel_crtc;
5941 struct intel_crtc_state *crtc_state;
5944 for_each_intel_crtc(dev, intel_crtc) {
5945 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5946 if (IS_ERR(crtc_state))
5947 return PTR_ERR(crtc_state);
5949 if (!crtc_state->base.enable)
5952 max_pixclk = max(max_pixclk,
5953 crtc_state->base.adjusted_mode.crtc_clock);
5959 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5961 struct drm_device *dev = state->dev;
5962 struct drm_i915_private *dev_priv = dev->dev_private;
5963 int max_pixclk = intel_mode_max_pixclk(dev, state);
5968 to_intel_atomic_state(state)->cdclk =
5969 valleyview_calc_cdclk(dev_priv, max_pixclk);
5974 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5976 struct drm_device *dev = state->dev;
5977 struct drm_i915_private *dev_priv = dev->dev_private;
5978 int max_pixclk = intel_mode_max_pixclk(dev, state);
5983 to_intel_atomic_state(state)->cdclk =
5984 broxton_calc_cdclk(dev_priv, max_pixclk);
5989 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5991 unsigned int credits, default_credits;
5993 if (IS_CHERRYVIEW(dev_priv))
5994 default_credits = PFI_CREDIT(12);
5996 default_credits = PFI_CREDIT(8);
5998 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
5999 /* CHV suggested value is 31 or 63 */
6000 if (IS_CHERRYVIEW(dev_priv))
6001 credits = PFI_CREDIT_63;
6003 credits = PFI_CREDIT(15);
6005 credits = default_credits;
6009 * WA - write default credits before re-programming
6010 * FIXME: should we also set the resend bit here?
6012 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6015 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6016 credits | PFI_CREDIT_RESEND);
6019 * FIXME is this guaranteed to clear
6020 * immediately or should we poll for it?
6022 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6025 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6027 struct drm_device *dev = old_state->dev;
6028 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6029 struct drm_i915_private *dev_priv = dev->dev_private;
6032 * FIXME: We can end up here with all power domains off, yet
6033 * with a CDCLK frequency other than the minimum. To account
6034 * for this take the PIPE-A power domain, which covers the HW
6035 * blocks needed for the following programming. This can be
6036 * removed once it's guaranteed that we get here either with
6037 * the minimum CDCLK set, or the required power domains
6040 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6042 if (IS_CHERRYVIEW(dev))
6043 cherryview_set_cdclk(dev, req_cdclk);
6045 valleyview_set_cdclk(dev, req_cdclk);
6047 vlv_program_pfi_credits(dev_priv);
6049 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6052 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6054 struct drm_device *dev = crtc->dev;
6055 struct drm_i915_private *dev_priv = to_i915(dev);
6056 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6057 struct intel_encoder *encoder;
6058 int pipe = intel_crtc->pipe;
6061 if (WARN_ON(intel_crtc->active))
6064 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6066 if (intel_crtc->config->has_dp_encoder)
6067 intel_dp_set_m_n(intel_crtc, M1_N1);
6069 intel_set_pipe_timings(intel_crtc);
6071 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6072 struct drm_i915_private *dev_priv = dev->dev_private;
6074 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6075 I915_WRITE(CHV_CANVAS(pipe), 0);
6078 i9xx_set_pipeconf(intel_crtc);
6080 intel_crtc->active = true;
6082 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6084 for_each_encoder_on_crtc(dev, crtc, encoder)
6085 if (encoder->pre_pll_enable)
6086 encoder->pre_pll_enable(encoder);
6089 if (IS_CHERRYVIEW(dev)) {
6090 chv_prepare_pll(intel_crtc, intel_crtc->config);
6091 chv_enable_pll(intel_crtc, intel_crtc->config);
6093 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6094 vlv_enable_pll(intel_crtc, intel_crtc->config);
6098 for_each_encoder_on_crtc(dev, crtc, encoder)
6099 if (encoder->pre_enable)
6100 encoder->pre_enable(encoder);
6102 i9xx_pfit_enable(intel_crtc);
6104 intel_crtc_load_lut(crtc);
6106 intel_enable_pipe(intel_crtc);
6108 assert_vblank_disabled(crtc);
6109 drm_crtc_vblank_on(crtc);
6111 for_each_encoder_on_crtc(dev, crtc, encoder)
6112 encoder->enable(encoder);
6115 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6117 struct drm_device *dev = crtc->base.dev;
6118 struct drm_i915_private *dev_priv = dev->dev_private;
6120 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6121 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6124 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6126 struct drm_device *dev = crtc->dev;
6127 struct drm_i915_private *dev_priv = to_i915(dev);
6128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6129 struct intel_encoder *encoder;
6130 int pipe = intel_crtc->pipe;
6132 if (WARN_ON(intel_crtc->active))
6135 i9xx_set_pll_dividers(intel_crtc);
6137 if (intel_crtc->config->has_dp_encoder)
6138 intel_dp_set_m_n(intel_crtc, M1_N1);
6140 intel_set_pipe_timings(intel_crtc);
6142 i9xx_set_pipeconf(intel_crtc);
6144 intel_crtc->active = true;
6147 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6149 for_each_encoder_on_crtc(dev, crtc, encoder)
6150 if (encoder->pre_enable)
6151 encoder->pre_enable(encoder);
6153 i9xx_enable_pll(intel_crtc);
6155 i9xx_pfit_enable(intel_crtc);
6157 intel_crtc_load_lut(crtc);
6159 intel_update_watermarks(crtc);
6160 intel_enable_pipe(intel_crtc);
6162 assert_vblank_disabled(crtc);
6163 drm_crtc_vblank_on(crtc);
6165 for_each_encoder_on_crtc(dev, crtc, encoder)
6166 encoder->enable(encoder);
6169 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6171 struct drm_device *dev = crtc->base.dev;
6172 struct drm_i915_private *dev_priv = dev->dev_private;
6174 if (!crtc->config->gmch_pfit.control)
6177 assert_pipe_disabled(dev_priv, crtc->pipe);
6179 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6180 I915_READ(PFIT_CONTROL));
6181 I915_WRITE(PFIT_CONTROL, 0);
6184 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6186 struct drm_device *dev = crtc->dev;
6187 struct drm_i915_private *dev_priv = dev->dev_private;
6188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6189 struct intel_encoder *encoder;
6190 int pipe = intel_crtc->pipe;
6193 * On gen2 planes are double buffered but the pipe isn't, so we must
6194 * wait for planes to fully turn off before disabling the pipe.
6195 * We also need to wait on all gmch platforms because of the
6196 * self-refresh mode constraint explained above.
6198 intel_wait_for_vblank(dev, pipe);
6200 for_each_encoder_on_crtc(dev, crtc, encoder)
6201 encoder->disable(encoder);
6203 drm_crtc_vblank_off(crtc);
6204 assert_vblank_disabled(crtc);
6206 intel_disable_pipe(intel_crtc);
6208 i9xx_pfit_disable(intel_crtc);
6210 for_each_encoder_on_crtc(dev, crtc, encoder)
6211 if (encoder->post_disable)
6212 encoder->post_disable(encoder);
6214 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6215 if (IS_CHERRYVIEW(dev))
6216 chv_disable_pll(dev_priv, pipe);
6217 else if (IS_VALLEYVIEW(dev))
6218 vlv_disable_pll(dev_priv, pipe);
6220 i9xx_disable_pll(intel_crtc);
6223 for_each_encoder_on_crtc(dev, crtc, encoder)
6224 if (encoder->post_pll_disable)
6225 encoder->post_pll_disable(encoder);
6228 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6231 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6234 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6235 enum intel_display_power_domain domain;
6236 unsigned long domains;
6238 if (!intel_crtc->active)
6241 if (to_intel_plane_state(crtc->primary->state)->visible) {
6242 intel_crtc_wait_for_pending_flips(crtc);
6243 intel_pre_disable_primary(crtc);
6246 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6247 dev_priv->display.crtc_disable(crtc);
6248 intel_crtc->active = false;
6249 intel_update_watermarks(crtc);
6250 intel_disable_shared_dpll(intel_crtc);
6252 domains = intel_crtc->enabled_power_domains;
6253 for_each_power_domain(domain, domains)
6254 intel_display_power_put(dev_priv, domain);
6255 intel_crtc->enabled_power_domains = 0;
6259 * turn all crtc's off, but do not adjust state
6260 * This has to be paired with a call to intel_modeset_setup_hw_state.
6262 int intel_display_suspend(struct drm_device *dev)
6264 struct drm_mode_config *config = &dev->mode_config;
6265 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6266 struct drm_atomic_state *state;
6267 struct drm_crtc *crtc;
6268 unsigned crtc_mask = 0;
6274 lockdep_assert_held(&ctx->ww_ctx);
6275 state = drm_atomic_state_alloc(dev);
6276 if (WARN_ON(!state))
6279 state->acquire_ctx = ctx;
6280 state->allow_modeset = true;
6282 for_each_crtc(dev, crtc) {
6283 struct drm_crtc_state *crtc_state =
6284 drm_atomic_get_crtc_state(state, crtc);
6286 ret = PTR_ERR_OR_ZERO(crtc_state);
6290 if (!crtc_state->active)
6293 crtc_state->active = false;
6294 crtc_mask |= 1 << drm_crtc_index(crtc);
6298 ret = drm_atomic_commit(state);
6301 for_each_crtc(dev, crtc)
6302 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6303 crtc->state->active = true;
6311 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6312 drm_atomic_state_free(state);
6316 void intel_encoder_destroy(struct drm_encoder *encoder)
6318 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6320 drm_encoder_cleanup(encoder);
6321 kfree(intel_encoder);
6324 /* Cross check the actual hw state with our own modeset state tracking (and it's
6325 * internal consistency). */
6326 static void intel_connector_check_state(struct intel_connector *connector)
6328 struct drm_crtc *crtc = connector->base.state->crtc;
6330 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6331 connector->base.base.id,
6332 connector->base.name);
6334 if (connector->get_hw_state(connector)) {
6335 struct intel_encoder *encoder = connector->encoder;
6336 struct drm_connector_state *conn_state = connector->base.state;
6338 I915_STATE_WARN(!crtc,
6339 "connector enabled without attached crtc\n");
6344 I915_STATE_WARN(!crtc->state->active,
6345 "connector is active, but attached crtc isn't\n");
6347 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6350 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6351 "atomic encoder doesn't match attached encoder\n");
6353 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6354 "attached encoder crtc differs from connector crtc\n");
6356 I915_STATE_WARN(crtc && crtc->state->active,
6357 "attached crtc is active, but connector isn't\n");
6358 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6359 "best encoder set without crtc!\n");
6363 int intel_connector_init(struct intel_connector *connector)
6365 struct drm_connector_state *connector_state;
6367 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6368 if (!connector_state)
6371 connector->base.state = connector_state;
6375 struct intel_connector *intel_connector_alloc(void)
6377 struct intel_connector *connector;
6379 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6383 if (intel_connector_init(connector) < 0) {
6391 /* Simple connector->get_hw_state implementation for encoders that support only
6392 * one connector and no cloning and hence the encoder state determines the state
6393 * of the connector. */
6394 bool intel_connector_get_hw_state(struct intel_connector *connector)
6397 struct intel_encoder *encoder = connector->encoder;
6399 return encoder->get_hw_state(encoder, &pipe);
6402 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6404 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6405 return crtc_state->fdi_lanes;
6410 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6411 struct intel_crtc_state *pipe_config)
6413 struct drm_atomic_state *state = pipe_config->base.state;
6414 struct intel_crtc *other_crtc;
6415 struct intel_crtc_state *other_crtc_state;
6417 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6418 pipe_name(pipe), pipe_config->fdi_lanes);
6419 if (pipe_config->fdi_lanes > 4) {
6420 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6421 pipe_name(pipe), pipe_config->fdi_lanes);
6425 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6426 if (pipe_config->fdi_lanes > 2) {
6427 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6428 pipe_config->fdi_lanes);
6435 if (INTEL_INFO(dev)->num_pipes == 2)
6438 /* Ivybridge 3 pipe is really complicated */
6443 if (pipe_config->fdi_lanes <= 2)
6446 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6448 intel_atomic_get_crtc_state(state, other_crtc);
6449 if (IS_ERR(other_crtc_state))
6450 return PTR_ERR(other_crtc_state);
6452 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6453 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6454 pipe_name(pipe), pipe_config->fdi_lanes);
6459 if (pipe_config->fdi_lanes > 2) {
6460 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6461 pipe_name(pipe), pipe_config->fdi_lanes);
6465 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6467 intel_atomic_get_crtc_state(state, other_crtc);
6468 if (IS_ERR(other_crtc_state))
6469 return PTR_ERR(other_crtc_state);
6471 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6472 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6482 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6483 struct intel_crtc_state *pipe_config)
6485 struct drm_device *dev = intel_crtc->base.dev;
6486 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6487 int lane, link_bw, fdi_dotclock, ret;
6488 bool needs_recompute = false;
6491 /* FDI is a binary signal running at ~2.7GHz, encoding
6492 * each output octet as 10 bits. The actual frequency
6493 * is stored as a divider into a 100MHz clock, and the
6494 * mode pixel clock is stored in units of 1KHz.
6495 * Hence the bw of each lane in terms of the mode signal
6498 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6500 fdi_dotclock = adjusted_mode->crtc_clock;
6502 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6503 pipe_config->pipe_bpp);
6505 pipe_config->fdi_lanes = lane;
6507 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6508 link_bw, &pipe_config->fdi_m_n);
6510 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6511 intel_crtc->pipe, pipe_config);
6512 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6513 pipe_config->pipe_bpp -= 2*3;
6514 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6515 pipe_config->pipe_bpp);
6516 needs_recompute = true;
6517 pipe_config->bw_constrained = true;
6522 if (needs_recompute)
6528 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6529 struct intel_crtc_state *pipe_config)
6531 if (pipe_config->pipe_bpp > 24)
6534 /* HSW can handle pixel rate up to cdclk? */
6535 if (IS_HASWELL(dev_priv->dev))
6539 * We compare against max which means we must take
6540 * the increased cdclk requirement into account when
6541 * calculating the new cdclk.
6543 * Should measure whether using a lower cdclk w/o IPS
6545 return ilk_pipe_pixel_rate(pipe_config) <=
6546 dev_priv->max_cdclk_freq * 95 / 100;
6549 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6550 struct intel_crtc_state *pipe_config)
6552 struct drm_device *dev = crtc->base.dev;
6553 struct drm_i915_private *dev_priv = dev->dev_private;
6555 pipe_config->ips_enabled = i915.enable_ips &&
6556 hsw_crtc_supports_ips(crtc) &&
6557 pipe_config_supports_ips(dev_priv, pipe_config);
6560 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6561 struct intel_crtc_state *pipe_config)
6563 struct drm_device *dev = crtc->base.dev;
6564 struct drm_i915_private *dev_priv = dev->dev_private;
6565 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6567 /* FIXME should check pixel clock limits on all platforms */
6568 if (INTEL_INFO(dev)->gen < 4) {
6569 int clock_limit = dev_priv->max_cdclk_freq;
6572 * Enable pixel doubling when the dot clock
6573 * is > 90% of the (display) core speed.
6575 * GDG double wide on either pipe,
6576 * otherwise pipe A only.
6578 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6579 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6581 pipe_config->double_wide = true;
6584 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6589 * Pipe horizontal size must be even in:
6591 * - LVDS dual channel mode
6592 * - Double wide pipe
6594 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6595 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6596 pipe_config->pipe_src_w &= ~1;
6598 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6599 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6601 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6602 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6606 hsw_compute_ips_config(crtc, pipe_config);
6608 if (pipe_config->has_pch_encoder)
6609 return ironlake_fdi_compute_config(crtc, pipe_config);
6614 static int skylake_get_display_clock_speed(struct drm_device *dev)
6616 struct drm_i915_private *dev_priv = to_i915(dev);
6617 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6618 uint32_t cdctl = I915_READ(CDCLK_CTL);
6621 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6622 return 24000; /* 24MHz is the cd freq with NSSC ref */
6624 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6627 linkrate = (I915_READ(DPLL_CTRL1) &
6628 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6630 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6631 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6633 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6634 case CDCLK_FREQ_450_432:
6636 case CDCLK_FREQ_337_308:
6638 case CDCLK_FREQ_675_617:
6641 WARN(1, "Unknown cd freq selection\n");
6645 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6646 case CDCLK_FREQ_450_432:
6648 case CDCLK_FREQ_337_308:
6650 case CDCLK_FREQ_675_617:
6653 WARN(1, "Unknown cd freq selection\n");
6657 /* error case, do as if DPLL0 isn't enabled */
6661 static int broxton_get_display_clock_speed(struct drm_device *dev)
6663 struct drm_i915_private *dev_priv = to_i915(dev);
6664 uint32_t cdctl = I915_READ(CDCLK_CTL);
6665 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6666 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6669 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6672 cdclk = 19200 * pll_ratio / 2;
6674 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6675 case BXT_CDCLK_CD2X_DIV_SEL_1:
6676 return cdclk; /* 576MHz or 624MHz */
6677 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6678 return cdclk * 2 / 3; /* 384MHz */
6679 case BXT_CDCLK_CD2X_DIV_SEL_2:
6680 return cdclk / 2; /* 288MHz */
6681 case BXT_CDCLK_CD2X_DIV_SEL_4:
6682 return cdclk / 4; /* 144MHz */
6685 /* error case, do as if DE PLL isn't enabled */
6689 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6691 struct drm_i915_private *dev_priv = dev->dev_private;
6692 uint32_t lcpll = I915_READ(LCPLL_CTL);
6693 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6695 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6697 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6699 else if (freq == LCPLL_CLK_FREQ_450)
6701 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6703 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6709 static int haswell_get_display_clock_speed(struct drm_device *dev)
6711 struct drm_i915_private *dev_priv = dev->dev_private;
6712 uint32_t lcpll = I915_READ(LCPLL_CTL);
6713 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6715 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6717 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6719 else if (freq == LCPLL_CLK_FREQ_450)
6721 else if (IS_HSW_ULT(dev))
6727 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6729 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6730 CCK_DISPLAY_CLOCK_CONTROL);
6733 static int ilk_get_display_clock_speed(struct drm_device *dev)
6738 static int i945_get_display_clock_speed(struct drm_device *dev)
6743 static int i915_get_display_clock_speed(struct drm_device *dev)
6748 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6753 static int pnv_get_display_clock_speed(struct drm_device *dev)
6757 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6759 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6760 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6762 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6764 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6766 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6769 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6770 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6772 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6777 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6781 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6783 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6786 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6787 case GC_DISPLAY_CLOCK_333_MHZ:
6790 case GC_DISPLAY_CLOCK_190_200_MHZ:
6796 static int i865_get_display_clock_speed(struct drm_device *dev)
6801 static int i85x_get_display_clock_speed(struct drm_device *dev)
6806 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6807 * encoding is different :(
6808 * FIXME is this the right way to detect 852GM/852GMV?
6810 if (dev->pdev->revision == 0x1)
6813 pci_bus_read_config_word(dev->pdev->bus,
6814 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6816 /* Assume that the hardware is in the high speed state. This
6817 * should be the default.
6819 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6820 case GC_CLOCK_133_200:
6821 case GC_CLOCK_133_200_2:
6822 case GC_CLOCK_100_200:
6824 case GC_CLOCK_166_250:
6826 case GC_CLOCK_100_133:
6828 case GC_CLOCK_133_266:
6829 case GC_CLOCK_133_266_2:
6830 case GC_CLOCK_166_266:
6834 /* Shouldn't happen */
6838 static int i830_get_display_clock_speed(struct drm_device *dev)
6843 static unsigned int intel_hpll_vco(struct drm_device *dev)
6845 struct drm_i915_private *dev_priv = dev->dev_private;
6846 static const unsigned int blb_vco[8] = {
6853 static const unsigned int pnv_vco[8] = {
6860 static const unsigned int cl_vco[8] = {
6869 static const unsigned int elk_vco[8] = {
6875 static const unsigned int ctg_vco[8] = {
6883 const unsigned int *vco_table;
6887 /* FIXME other chipsets? */
6889 vco_table = ctg_vco;
6890 else if (IS_G4X(dev))
6891 vco_table = elk_vco;
6892 else if (IS_CRESTLINE(dev))
6894 else if (IS_PINEVIEW(dev))
6895 vco_table = pnv_vco;
6896 else if (IS_G33(dev))
6897 vco_table = blb_vco;
6901 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6903 vco = vco_table[tmp & 0x7];
6905 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6907 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6912 static int gm45_get_display_clock_speed(struct drm_device *dev)
6914 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6917 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6919 cdclk_sel = (tmp >> 12) & 0x1;
6925 return cdclk_sel ? 333333 : 222222;
6927 return cdclk_sel ? 320000 : 228571;
6929 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6934 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6936 static const uint8_t div_3200[] = { 16, 10, 8 };
6937 static const uint8_t div_4000[] = { 20, 12, 10 };
6938 static const uint8_t div_5333[] = { 24, 16, 14 };
6939 const uint8_t *div_table;
6940 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6943 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6945 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6947 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6952 div_table = div_3200;
6955 div_table = div_4000;
6958 div_table = div_5333;
6964 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6967 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6971 static int g33_get_display_clock_speed(struct drm_device *dev)
6973 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6974 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6975 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6976 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6977 const uint8_t *div_table;
6978 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6981 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6983 cdclk_sel = (tmp >> 4) & 0x7;
6985 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6990 div_table = div_3200;
6993 div_table = div_4000;
6996 div_table = div_4800;
6999 div_table = div_5333;
7005 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7008 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7013 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7015 while (*num > DATA_LINK_M_N_MASK ||
7016 *den > DATA_LINK_M_N_MASK) {
7022 static void compute_m_n(unsigned int m, unsigned int n,
7023 uint32_t *ret_m, uint32_t *ret_n)
7025 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7026 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7027 intel_reduce_m_n_ratio(ret_m, ret_n);
7031 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7032 int pixel_clock, int link_clock,
7033 struct intel_link_m_n *m_n)
7037 compute_m_n(bits_per_pixel * pixel_clock,
7038 link_clock * nlanes * 8,
7039 &m_n->gmch_m, &m_n->gmch_n);
7041 compute_m_n(pixel_clock, link_clock,
7042 &m_n->link_m, &m_n->link_n);
7045 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7047 if (i915.panel_use_ssc >= 0)
7048 return i915.panel_use_ssc != 0;
7049 return dev_priv->vbt.lvds_use_ssc
7050 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7053 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7056 struct drm_device *dev = crtc_state->base.crtc->dev;
7057 struct drm_i915_private *dev_priv = dev->dev_private;
7060 WARN_ON(!crtc_state->base.state);
7062 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7064 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7065 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7066 refclk = dev_priv->vbt.lvds_ssc_freq;
7067 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7068 } else if (!IS_GEN2(dev)) {
7077 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7079 return (1 << dpll->n) << 16 | dpll->m2;
7082 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7084 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7087 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7088 struct intel_crtc_state *crtc_state,
7089 intel_clock_t *reduced_clock)
7091 struct drm_device *dev = crtc->base.dev;
7094 if (IS_PINEVIEW(dev)) {
7095 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7097 fp2 = pnv_dpll_compute_fp(reduced_clock);
7099 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7101 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7104 crtc_state->dpll_hw_state.fp0 = fp;
7106 crtc->lowfreq_avail = false;
7107 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7109 crtc_state->dpll_hw_state.fp1 = fp2;
7110 crtc->lowfreq_avail = true;
7112 crtc_state->dpll_hw_state.fp1 = fp;
7116 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7122 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7123 * and set it to a reasonable value instead.
7125 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7126 reg_val &= 0xffffff00;
7127 reg_val |= 0x00000030;
7128 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7130 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7131 reg_val &= 0x8cffffff;
7132 reg_val = 0x8c000000;
7133 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7135 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7136 reg_val &= 0xffffff00;
7137 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7139 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7140 reg_val &= 0x00ffffff;
7141 reg_val |= 0xb0000000;
7142 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7145 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7146 struct intel_link_m_n *m_n)
7148 struct drm_device *dev = crtc->base.dev;
7149 struct drm_i915_private *dev_priv = dev->dev_private;
7150 int pipe = crtc->pipe;
7152 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7153 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7154 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7155 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7158 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7159 struct intel_link_m_n *m_n,
7160 struct intel_link_m_n *m2_n2)
7162 struct drm_device *dev = crtc->base.dev;
7163 struct drm_i915_private *dev_priv = dev->dev_private;
7164 int pipe = crtc->pipe;
7165 enum transcoder transcoder = crtc->config->cpu_transcoder;
7167 if (INTEL_INFO(dev)->gen >= 5) {
7168 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7169 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7170 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7171 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7172 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7173 * for gen < 8) and if DRRS is supported (to make sure the
7174 * registers are not unnecessarily accessed).
7176 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7177 crtc->config->has_drrs) {
7178 I915_WRITE(PIPE_DATA_M2(transcoder),
7179 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7180 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7181 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7182 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7185 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7186 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7187 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7188 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7192 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7194 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7197 dp_m_n = &crtc->config->dp_m_n;
7198 dp_m2_n2 = &crtc->config->dp_m2_n2;
7199 } else if (m_n == M2_N2) {
7202 * M2_N2 registers are not supported. Hence m2_n2 divider value
7203 * needs to be programmed into M1_N1.
7205 dp_m_n = &crtc->config->dp_m2_n2;
7207 DRM_ERROR("Unsupported divider value\n");
7211 if (crtc->config->has_pch_encoder)
7212 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7214 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7217 static void vlv_compute_dpll(struct intel_crtc *crtc,
7218 struct intel_crtc_state *pipe_config)
7223 * Enable DPIO clock input. We should never disable the reference
7224 * clock for pipe B, since VGA hotplug / manual detection depends
7227 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7228 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7229 /* We should never disable this, set it here for state tracking */
7230 if (crtc->pipe == PIPE_B)
7231 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7232 dpll |= DPLL_VCO_ENABLE;
7233 pipe_config->dpll_hw_state.dpll = dpll;
7235 dpll_md = (pipe_config->pixel_multiplier - 1)
7236 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7237 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7240 static void vlv_prepare_pll(struct intel_crtc *crtc,
7241 const struct intel_crtc_state *pipe_config)
7243 struct drm_device *dev = crtc->base.dev;
7244 struct drm_i915_private *dev_priv = dev->dev_private;
7245 int pipe = crtc->pipe;
7247 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7248 u32 coreclk, reg_val;
7250 mutex_lock(&dev_priv->sb_lock);
7252 bestn = pipe_config->dpll.n;
7253 bestm1 = pipe_config->dpll.m1;
7254 bestm2 = pipe_config->dpll.m2;
7255 bestp1 = pipe_config->dpll.p1;
7256 bestp2 = pipe_config->dpll.p2;
7258 /* See eDP HDMI DPIO driver vbios notes doc */
7260 /* PLL B needs special handling */
7262 vlv_pllb_recal_opamp(dev_priv, pipe);
7264 /* Set up Tx target for periodic Rcomp update */
7265 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7267 /* Disable target IRef on PLL */
7268 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7269 reg_val &= 0x00ffffff;
7270 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7272 /* Disable fast lock */
7273 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7275 /* Set idtafcrecal before PLL is enabled */
7276 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7277 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7278 mdiv |= ((bestn << DPIO_N_SHIFT));
7279 mdiv |= (1 << DPIO_K_SHIFT);
7282 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7283 * but we don't support that).
7284 * Note: don't use the DAC post divider as it seems unstable.
7286 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7287 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7289 mdiv |= DPIO_ENABLE_CALIBRATION;
7290 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7292 /* Set HBR and RBR LPF coefficients */
7293 if (pipe_config->port_clock == 162000 ||
7294 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7295 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7296 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7299 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7302 if (pipe_config->has_dp_encoder) {
7303 /* Use SSC source */
7305 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7308 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7310 } else { /* HDMI or VGA */
7311 /* Use bend source */
7313 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7316 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7320 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7321 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7322 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7323 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7324 coreclk |= 0x01000000;
7325 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7327 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7328 mutex_unlock(&dev_priv->sb_lock);
7331 static void chv_compute_dpll(struct intel_crtc *crtc,
7332 struct intel_crtc_state *pipe_config)
7334 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7335 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7337 if (crtc->pipe != PIPE_A)
7338 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7340 pipe_config->dpll_hw_state.dpll_md =
7341 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7344 static void chv_prepare_pll(struct intel_crtc *crtc,
7345 const struct intel_crtc_state *pipe_config)
7347 struct drm_device *dev = crtc->base.dev;
7348 struct drm_i915_private *dev_priv = dev->dev_private;
7349 int pipe = crtc->pipe;
7350 int dpll_reg = DPLL(crtc->pipe);
7351 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7352 u32 loopfilter, tribuf_calcntr;
7353 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7357 bestn = pipe_config->dpll.n;
7358 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7359 bestm1 = pipe_config->dpll.m1;
7360 bestm2 = pipe_config->dpll.m2 >> 22;
7361 bestp1 = pipe_config->dpll.p1;
7362 bestp2 = pipe_config->dpll.p2;
7363 vco = pipe_config->dpll.vco;
7368 * Enable Refclk and SSC
7370 I915_WRITE(dpll_reg,
7371 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7373 mutex_lock(&dev_priv->sb_lock);
7375 /* p1 and p2 divider */
7376 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7377 5 << DPIO_CHV_S1_DIV_SHIFT |
7378 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7379 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7380 1 << DPIO_CHV_K_DIV_SHIFT);
7382 /* Feedback post-divider - m2 */
7383 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7385 /* Feedback refclk divider - n and m1 */
7386 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7387 DPIO_CHV_M1_DIV_BY_2 |
7388 1 << DPIO_CHV_N_DIV_SHIFT);
7390 /* M2 fraction division */
7391 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7393 /* M2 fraction division enable */
7394 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7395 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7396 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7398 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7399 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7401 /* Program digital lock detect threshold */
7402 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7403 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7404 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7405 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7407 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7408 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7411 if (vco == 5400000) {
7412 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7413 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7414 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7415 tribuf_calcntr = 0x9;
7416 } else if (vco <= 6200000) {
7417 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7418 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7419 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7420 tribuf_calcntr = 0x9;
7421 } else if (vco <= 6480000) {
7422 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7423 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7424 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7425 tribuf_calcntr = 0x8;
7427 /* Not supported. Apply the same limits as in the max case */
7428 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7429 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7430 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7433 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7435 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7436 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7437 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7438 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7441 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7442 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7445 mutex_unlock(&dev_priv->sb_lock);
7449 * vlv_force_pll_on - forcibly enable just the PLL
7450 * @dev_priv: i915 private structure
7451 * @pipe: pipe PLL to enable
7452 * @dpll: PLL configuration
7454 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7455 * in cases where we need the PLL enabled even when @pipe is not going to
7458 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7459 const struct dpll *dpll)
7461 struct intel_crtc *crtc =
7462 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7463 struct intel_crtc_state pipe_config = {
7464 .base.crtc = &crtc->base,
7465 .pixel_multiplier = 1,
7469 if (IS_CHERRYVIEW(dev)) {
7470 chv_compute_dpll(crtc, &pipe_config);
7471 chv_prepare_pll(crtc, &pipe_config);
7472 chv_enable_pll(crtc, &pipe_config);
7474 vlv_compute_dpll(crtc, &pipe_config);
7475 vlv_prepare_pll(crtc, &pipe_config);
7476 vlv_enable_pll(crtc, &pipe_config);
7481 * vlv_force_pll_off - forcibly disable just the PLL
7482 * @dev_priv: i915 private structure
7483 * @pipe: pipe PLL to disable
7485 * Disable the PLL for @pipe. To be used in cases where we need
7486 * the PLL enabled even when @pipe is not going to be enabled.
7488 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7490 if (IS_CHERRYVIEW(dev))
7491 chv_disable_pll(to_i915(dev), pipe);
7493 vlv_disable_pll(to_i915(dev), pipe);
7496 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7497 struct intel_crtc_state *crtc_state,
7498 intel_clock_t *reduced_clock,
7501 struct drm_device *dev = crtc->base.dev;
7502 struct drm_i915_private *dev_priv = dev->dev_private;
7505 struct dpll *clock = &crtc_state->dpll;
7507 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7509 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7510 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7512 dpll = DPLL_VGA_MODE_DIS;
7514 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7515 dpll |= DPLLB_MODE_LVDS;
7517 dpll |= DPLLB_MODE_DAC_SERIAL;
7519 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7520 dpll |= (crtc_state->pixel_multiplier - 1)
7521 << SDVO_MULTIPLIER_SHIFT_HIRES;
7525 dpll |= DPLL_SDVO_HIGH_SPEED;
7527 if (crtc_state->has_dp_encoder)
7528 dpll |= DPLL_SDVO_HIGH_SPEED;
7530 /* compute bitmask from p1 value */
7531 if (IS_PINEVIEW(dev))
7532 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7534 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7535 if (IS_G4X(dev) && reduced_clock)
7536 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7538 switch (clock->p2) {
7540 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7543 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7546 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7549 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7552 if (INTEL_INFO(dev)->gen >= 4)
7553 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7555 if (crtc_state->sdvo_tv_clock)
7556 dpll |= PLL_REF_INPUT_TVCLKINBC;
7557 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7558 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7559 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7561 dpll |= PLL_REF_INPUT_DREFCLK;
7563 dpll |= DPLL_VCO_ENABLE;
7564 crtc_state->dpll_hw_state.dpll = dpll;
7566 if (INTEL_INFO(dev)->gen >= 4) {
7567 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7568 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7569 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7573 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7574 struct intel_crtc_state *crtc_state,
7575 intel_clock_t *reduced_clock,
7578 struct drm_device *dev = crtc->base.dev;
7579 struct drm_i915_private *dev_priv = dev->dev_private;
7581 struct dpll *clock = &crtc_state->dpll;
7583 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7585 dpll = DPLL_VGA_MODE_DIS;
7587 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7588 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7591 dpll |= PLL_P1_DIVIDE_BY_TWO;
7593 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7595 dpll |= PLL_P2_DIVIDE_BY_4;
7598 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7599 dpll |= DPLL_DVO_2X_MODE;
7601 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7602 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7603 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7605 dpll |= PLL_REF_INPUT_DREFCLK;
7607 dpll |= DPLL_VCO_ENABLE;
7608 crtc_state->dpll_hw_state.dpll = dpll;
7611 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7613 struct drm_device *dev = intel_crtc->base.dev;
7614 struct drm_i915_private *dev_priv = dev->dev_private;
7615 enum pipe pipe = intel_crtc->pipe;
7616 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7617 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7618 uint32_t crtc_vtotal, crtc_vblank_end;
7621 /* We need to be careful not to changed the adjusted mode, for otherwise
7622 * the hw state checker will get angry at the mismatch. */
7623 crtc_vtotal = adjusted_mode->crtc_vtotal;
7624 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7626 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7627 /* the chip adds 2 halflines automatically */
7629 crtc_vblank_end -= 1;
7631 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7632 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7634 vsyncshift = adjusted_mode->crtc_hsync_start -
7635 adjusted_mode->crtc_htotal / 2;
7637 vsyncshift += adjusted_mode->crtc_htotal;
7640 if (INTEL_INFO(dev)->gen > 3)
7641 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7643 I915_WRITE(HTOTAL(cpu_transcoder),
7644 (adjusted_mode->crtc_hdisplay - 1) |
7645 ((adjusted_mode->crtc_htotal - 1) << 16));
7646 I915_WRITE(HBLANK(cpu_transcoder),
7647 (adjusted_mode->crtc_hblank_start - 1) |
7648 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7649 I915_WRITE(HSYNC(cpu_transcoder),
7650 (adjusted_mode->crtc_hsync_start - 1) |
7651 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7653 I915_WRITE(VTOTAL(cpu_transcoder),
7654 (adjusted_mode->crtc_vdisplay - 1) |
7655 ((crtc_vtotal - 1) << 16));
7656 I915_WRITE(VBLANK(cpu_transcoder),
7657 (adjusted_mode->crtc_vblank_start - 1) |
7658 ((crtc_vblank_end - 1) << 16));
7659 I915_WRITE(VSYNC(cpu_transcoder),
7660 (adjusted_mode->crtc_vsync_start - 1) |
7661 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7663 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7664 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7665 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7667 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7668 (pipe == PIPE_B || pipe == PIPE_C))
7669 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7671 /* pipesrc controls the size that is scaled from, which should
7672 * always be the user's requested size.
7674 I915_WRITE(PIPESRC(pipe),
7675 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7676 (intel_crtc->config->pipe_src_h - 1));
7679 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7680 struct intel_crtc_state *pipe_config)
7682 struct drm_device *dev = crtc->base.dev;
7683 struct drm_i915_private *dev_priv = dev->dev_private;
7684 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7687 tmp = I915_READ(HTOTAL(cpu_transcoder));
7688 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7689 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7690 tmp = I915_READ(HBLANK(cpu_transcoder));
7691 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7692 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7693 tmp = I915_READ(HSYNC(cpu_transcoder));
7694 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7695 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7697 tmp = I915_READ(VTOTAL(cpu_transcoder));
7698 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7699 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7700 tmp = I915_READ(VBLANK(cpu_transcoder));
7701 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7702 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7703 tmp = I915_READ(VSYNC(cpu_transcoder));
7704 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7705 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7707 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7708 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7709 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7710 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7713 tmp = I915_READ(PIPESRC(crtc->pipe));
7714 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7715 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7717 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7718 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7721 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7722 struct intel_crtc_state *pipe_config)
7724 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7725 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7726 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7727 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7729 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7730 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7731 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7732 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7734 mode->flags = pipe_config->base.adjusted_mode.flags;
7735 mode->type = DRM_MODE_TYPE_DRIVER;
7737 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7738 mode->flags |= pipe_config->base.adjusted_mode.flags;
7740 mode->hsync = drm_mode_hsync(mode);
7741 mode->vrefresh = drm_mode_vrefresh(mode);
7742 drm_mode_set_name(mode);
7745 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7747 struct drm_device *dev = intel_crtc->base.dev;
7748 struct drm_i915_private *dev_priv = dev->dev_private;
7753 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7754 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7755 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7757 if (intel_crtc->config->double_wide)
7758 pipeconf |= PIPECONF_DOUBLE_WIDE;
7760 /* only g4x and later have fancy bpc/dither controls */
7761 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7762 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7763 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7764 pipeconf |= PIPECONF_DITHER_EN |
7765 PIPECONF_DITHER_TYPE_SP;
7767 switch (intel_crtc->config->pipe_bpp) {
7769 pipeconf |= PIPECONF_6BPC;
7772 pipeconf |= PIPECONF_8BPC;
7775 pipeconf |= PIPECONF_10BPC;
7778 /* Case prevented by intel_choose_pipe_bpp_dither. */
7783 if (HAS_PIPE_CXSR(dev)) {
7784 if (intel_crtc->lowfreq_avail) {
7785 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7786 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7788 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7792 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7793 if (INTEL_INFO(dev)->gen < 4 ||
7794 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7795 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7797 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7799 pipeconf |= PIPECONF_PROGRESSIVE;
7801 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7802 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7804 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7805 POSTING_READ(PIPECONF(intel_crtc->pipe));
7808 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7809 struct intel_crtc_state *crtc_state)
7811 struct drm_device *dev = crtc->base.dev;
7812 struct drm_i915_private *dev_priv = dev->dev_private;
7813 int refclk, num_connectors = 0;
7814 intel_clock_t clock;
7816 bool is_dsi = false;
7817 struct intel_encoder *encoder;
7818 const intel_limit_t *limit;
7819 struct drm_atomic_state *state = crtc_state->base.state;
7820 struct drm_connector *connector;
7821 struct drm_connector_state *connector_state;
7824 memset(&crtc_state->dpll_hw_state, 0,
7825 sizeof(crtc_state->dpll_hw_state));
7827 for_each_connector_in_state(state, connector, connector_state, i) {
7828 if (connector_state->crtc != &crtc->base)
7831 encoder = to_intel_encoder(connector_state->best_encoder);
7833 switch (encoder->type) {
7834 case INTEL_OUTPUT_DSI:
7847 if (!crtc_state->clock_set) {
7848 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7851 * Returns a set of divisors for the desired target clock with
7852 * the given refclk, or FALSE. The returned values represent
7853 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7856 limit = intel_limit(crtc_state, refclk);
7857 ok = dev_priv->display.find_dpll(limit, crtc_state,
7858 crtc_state->port_clock,
7859 refclk, NULL, &clock);
7861 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7865 /* Compat-code for transition, will disappear. */
7866 crtc_state->dpll.n = clock.n;
7867 crtc_state->dpll.m1 = clock.m1;
7868 crtc_state->dpll.m2 = clock.m2;
7869 crtc_state->dpll.p1 = clock.p1;
7870 crtc_state->dpll.p2 = clock.p2;
7874 i8xx_compute_dpll(crtc, crtc_state, NULL,
7876 } else if (IS_CHERRYVIEW(dev)) {
7877 chv_compute_dpll(crtc, crtc_state);
7878 } else if (IS_VALLEYVIEW(dev)) {
7879 vlv_compute_dpll(crtc, crtc_state);
7881 i9xx_compute_dpll(crtc, crtc_state, NULL,
7888 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7889 struct intel_crtc_state *pipe_config)
7891 struct drm_device *dev = crtc->base.dev;
7892 struct drm_i915_private *dev_priv = dev->dev_private;
7895 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7898 tmp = I915_READ(PFIT_CONTROL);
7899 if (!(tmp & PFIT_ENABLE))
7902 /* Check whether the pfit is attached to our pipe. */
7903 if (INTEL_INFO(dev)->gen < 4) {
7904 if (crtc->pipe != PIPE_B)
7907 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7911 pipe_config->gmch_pfit.control = tmp;
7912 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7913 if (INTEL_INFO(dev)->gen < 5)
7914 pipe_config->gmch_pfit.lvds_border_bits =
7915 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7918 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7919 struct intel_crtc_state *pipe_config)
7921 struct drm_device *dev = crtc->base.dev;
7922 struct drm_i915_private *dev_priv = dev->dev_private;
7923 int pipe = pipe_config->cpu_transcoder;
7924 intel_clock_t clock;
7926 int refclk = 100000;
7928 /* In case of MIPI DPLL will not even be used */
7929 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7932 mutex_lock(&dev_priv->sb_lock);
7933 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7934 mutex_unlock(&dev_priv->sb_lock);
7936 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7937 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7938 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7939 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7940 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7942 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7946 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7947 struct intel_initial_plane_config *plane_config)
7949 struct drm_device *dev = crtc->base.dev;
7950 struct drm_i915_private *dev_priv = dev->dev_private;
7951 u32 val, base, offset;
7952 int pipe = crtc->pipe, plane = crtc->plane;
7953 int fourcc, pixel_format;
7954 unsigned int aligned_height;
7955 struct drm_framebuffer *fb;
7956 struct intel_framebuffer *intel_fb;
7958 val = I915_READ(DSPCNTR(plane));
7959 if (!(val & DISPLAY_PLANE_ENABLE))
7962 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7964 DRM_DEBUG_KMS("failed to alloc fb\n");
7968 fb = &intel_fb->base;
7970 if (INTEL_INFO(dev)->gen >= 4) {
7971 if (val & DISPPLANE_TILED) {
7972 plane_config->tiling = I915_TILING_X;
7973 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7977 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7978 fourcc = i9xx_format_to_fourcc(pixel_format);
7979 fb->pixel_format = fourcc;
7980 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7982 if (INTEL_INFO(dev)->gen >= 4) {
7983 if (plane_config->tiling)
7984 offset = I915_READ(DSPTILEOFF(plane));
7986 offset = I915_READ(DSPLINOFF(plane));
7987 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7989 base = I915_READ(DSPADDR(plane));
7991 plane_config->base = base;
7993 val = I915_READ(PIPESRC(pipe));
7994 fb->width = ((val >> 16) & 0xfff) + 1;
7995 fb->height = ((val >> 0) & 0xfff) + 1;
7997 val = I915_READ(DSPSTRIDE(pipe));
7998 fb->pitches[0] = val & 0xffffffc0;
8000 aligned_height = intel_fb_align_height(dev, fb->height,
8004 plane_config->size = fb->pitches[0] * aligned_height;
8006 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8007 pipe_name(pipe), plane, fb->width, fb->height,
8008 fb->bits_per_pixel, base, fb->pitches[0],
8009 plane_config->size);
8011 plane_config->fb = intel_fb;
8014 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8015 struct intel_crtc_state *pipe_config)
8017 struct drm_device *dev = crtc->base.dev;
8018 struct drm_i915_private *dev_priv = dev->dev_private;
8019 int pipe = pipe_config->cpu_transcoder;
8020 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8021 intel_clock_t clock;
8022 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8023 int refclk = 100000;
8025 mutex_lock(&dev_priv->sb_lock);
8026 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8027 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8028 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8029 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8030 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8031 mutex_unlock(&dev_priv->sb_lock);
8033 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8034 clock.m2 = (pll_dw0 & 0xff) << 22;
8035 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8036 clock.m2 |= pll_dw2 & 0x3fffff;
8037 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8038 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8039 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8041 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8044 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8045 struct intel_crtc_state *pipe_config)
8047 struct drm_device *dev = crtc->base.dev;
8048 struct drm_i915_private *dev_priv = dev->dev_private;
8051 if (!intel_display_power_is_enabled(dev_priv,
8052 POWER_DOMAIN_PIPE(crtc->pipe)))
8055 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8056 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8058 tmp = I915_READ(PIPECONF(crtc->pipe));
8059 if (!(tmp & PIPECONF_ENABLE))
8062 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8063 switch (tmp & PIPECONF_BPC_MASK) {
8065 pipe_config->pipe_bpp = 18;
8068 pipe_config->pipe_bpp = 24;
8070 case PIPECONF_10BPC:
8071 pipe_config->pipe_bpp = 30;
8078 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8079 pipe_config->limited_color_range = true;
8081 if (INTEL_INFO(dev)->gen < 4)
8082 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8084 intel_get_pipe_timings(crtc, pipe_config);
8086 i9xx_get_pfit_config(crtc, pipe_config);
8088 if (INTEL_INFO(dev)->gen >= 4) {
8089 tmp = I915_READ(DPLL_MD(crtc->pipe));
8090 pipe_config->pixel_multiplier =
8091 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8092 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8093 pipe_config->dpll_hw_state.dpll_md = tmp;
8094 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8095 tmp = I915_READ(DPLL(crtc->pipe));
8096 pipe_config->pixel_multiplier =
8097 ((tmp & SDVO_MULTIPLIER_MASK)
8098 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8100 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8101 * port and will be fixed up in the encoder->get_config
8103 pipe_config->pixel_multiplier = 1;
8105 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8106 if (!IS_VALLEYVIEW(dev)) {
8108 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8109 * on 830. Filter it out here so that we don't
8110 * report errors due to that.
8113 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8115 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8116 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8118 /* Mask out read-only status bits. */
8119 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8120 DPLL_PORTC_READY_MASK |
8121 DPLL_PORTB_READY_MASK);
8124 if (IS_CHERRYVIEW(dev))
8125 chv_crtc_clock_get(crtc, pipe_config);
8126 else if (IS_VALLEYVIEW(dev))
8127 vlv_crtc_clock_get(crtc, pipe_config);
8129 i9xx_crtc_clock_get(crtc, pipe_config);
8132 * Normally the dotclock is filled in by the encoder .get_config()
8133 * but in case the pipe is enabled w/o any ports we need a sane
8136 pipe_config->base.adjusted_mode.crtc_clock =
8137 pipe_config->port_clock / pipe_config->pixel_multiplier;
8142 static void ironlake_init_pch_refclk(struct drm_device *dev)
8144 struct drm_i915_private *dev_priv = dev->dev_private;
8145 struct intel_encoder *encoder;
8147 bool has_lvds = false;
8148 bool has_cpu_edp = false;
8149 bool has_panel = false;
8150 bool has_ck505 = false;
8151 bool can_ssc = false;
8153 /* We need to take the global config into account */
8154 for_each_intel_encoder(dev, encoder) {
8155 switch (encoder->type) {
8156 case INTEL_OUTPUT_LVDS:
8160 case INTEL_OUTPUT_EDP:
8162 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8170 if (HAS_PCH_IBX(dev)) {
8171 has_ck505 = dev_priv->vbt.display_clock_mode;
8172 can_ssc = has_ck505;
8178 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8179 has_panel, has_lvds, has_ck505);
8181 /* Ironlake: try to setup display ref clock before DPLL
8182 * enabling. This is only under driver's control after
8183 * PCH B stepping, previous chipset stepping should be
8184 * ignoring this setting.
8186 val = I915_READ(PCH_DREF_CONTROL);
8188 /* As we must carefully and slowly disable/enable each source in turn,
8189 * compute the final state we want first and check if we need to
8190 * make any changes at all.
8193 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8195 final |= DREF_NONSPREAD_CK505_ENABLE;
8197 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8199 final &= ~DREF_SSC_SOURCE_MASK;
8200 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8201 final &= ~DREF_SSC1_ENABLE;
8204 final |= DREF_SSC_SOURCE_ENABLE;
8206 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8207 final |= DREF_SSC1_ENABLE;
8210 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8211 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8213 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8215 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8217 final |= DREF_SSC_SOURCE_DISABLE;
8218 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8224 /* Always enable nonspread source */
8225 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8228 val |= DREF_NONSPREAD_CK505_ENABLE;
8230 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8233 val &= ~DREF_SSC_SOURCE_MASK;
8234 val |= DREF_SSC_SOURCE_ENABLE;
8236 /* SSC must be turned on before enabling the CPU output */
8237 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8238 DRM_DEBUG_KMS("Using SSC on panel\n");
8239 val |= DREF_SSC1_ENABLE;
8241 val &= ~DREF_SSC1_ENABLE;
8243 /* Get SSC going before enabling the outputs */
8244 I915_WRITE(PCH_DREF_CONTROL, val);
8245 POSTING_READ(PCH_DREF_CONTROL);
8248 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8250 /* Enable CPU source on CPU attached eDP */
8252 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8253 DRM_DEBUG_KMS("Using SSC on eDP\n");
8254 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8256 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8258 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8260 I915_WRITE(PCH_DREF_CONTROL, val);
8261 POSTING_READ(PCH_DREF_CONTROL);
8264 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8266 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8268 /* Turn off CPU output */
8269 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8271 I915_WRITE(PCH_DREF_CONTROL, val);
8272 POSTING_READ(PCH_DREF_CONTROL);
8275 /* Turn off the SSC source */
8276 val &= ~DREF_SSC_SOURCE_MASK;
8277 val |= DREF_SSC_SOURCE_DISABLE;
8280 val &= ~DREF_SSC1_ENABLE;
8282 I915_WRITE(PCH_DREF_CONTROL, val);
8283 POSTING_READ(PCH_DREF_CONTROL);
8287 BUG_ON(val != final);
8290 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8294 tmp = I915_READ(SOUTH_CHICKEN2);
8295 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8296 I915_WRITE(SOUTH_CHICKEN2, tmp);
8298 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8299 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8300 DRM_ERROR("FDI mPHY reset assert timeout\n");
8302 tmp = I915_READ(SOUTH_CHICKEN2);
8303 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8304 I915_WRITE(SOUTH_CHICKEN2, tmp);
8306 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8307 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8308 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8311 /* WaMPhyProgramming:hsw */
8312 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8316 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8317 tmp &= ~(0xFF << 24);
8318 tmp |= (0x12 << 24);
8319 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8321 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8323 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8325 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8327 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8329 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8330 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8331 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8333 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8334 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8335 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8337 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8340 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8342 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8345 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8347 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8350 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8352 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8355 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8357 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8358 tmp &= ~(0xFF << 16);
8359 tmp |= (0x1C << 16);
8360 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8362 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8363 tmp &= ~(0xFF << 16);
8364 tmp |= (0x1C << 16);
8365 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8367 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8369 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8371 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8373 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8375 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8376 tmp &= ~(0xF << 28);
8378 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8380 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8381 tmp &= ~(0xF << 28);
8383 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8386 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8387 * Programming" based on the parameters passed:
8388 * - Sequence to enable CLKOUT_DP
8389 * - Sequence to enable CLKOUT_DP without spread
8390 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8392 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8395 struct drm_i915_private *dev_priv = dev->dev_private;
8398 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8400 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8403 mutex_lock(&dev_priv->sb_lock);
8405 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8406 tmp &= ~SBI_SSCCTL_DISABLE;
8407 tmp |= SBI_SSCCTL_PATHALT;
8408 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8413 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8414 tmp &= ~SBI_SSCCTL_PATHALT;
8415 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8418 lpt_reset_fdi_mphy(dev_priv);
8419 lpt_program_fdi_mphy(dev_priv);
8423 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8424 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8425 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8426 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8428 mutex_unlock(&dev_priv->sb_lock);
8431 /* Sequence to disable CLKOUT_DP */
8432 static void lpt_disable_clkout_dp(struct drm_device *dev)
8434 struct drm_i915_private *dev_priv = dev->dev_private;
8437 mutex_lock(&dev_priv->sb_lock);
8439 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8440 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8441 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8442 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8444 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8445 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8446 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8447 tmp |= SBI_SSCCTL_PATHALT;
8448 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8451 tmp |= SBI_SSCCTL_DISABLE;
8452 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8455 mutex_unlock(&dev_priv->sb_lock);
8458 static void lpt_init_pch_refclk(struct drm_device *dev)
8460 struct intel_encoder *encoder;
8461 bool has_vga = false;
8463 for_each_intel_encoder(dev, encoder) {
8464 switch (encoder->type) {
8465 case INTEL_OUTPUT_ANALOG:
8474 lpt_enable_clkout_dp(dev, true, true);
8476 lpt_disable_clkout_dp(dev);
8480 * Initialize reference clocks when the driver loads
8482 void intel_init_pch_refclk(struct drm_device *dev)
8484 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8485 ironlake_init_pch_refclk(dev);
8486 else if (HAS_PCH_LPT(dev))
8487 lpt_init_pch_refclk(dev);
8490 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8492 struct drm_device *dev = crtc_state->base.crtc->dev;
8493 struct drm_i915_private *dev_priv = dev->dev_private;
8494 struct drm_atomic_state *state = crtc_state->base.state;
8495 struct drm_connector *connector;
8496 struct drm_connector_state *connector_state;
8497 struct intel_encoder *encoder;
8498 int num_connectors = 0, i;
8499 bool is_lvds = false;
8501 for_each_connector_in_state(state, connector, connector_state, i) {
8502 if (connector_state->crtc != crtc_state->base.crtc)
8505 encoder = to_intel_encoder(connector_state->best_encoder);
8507 switch (encoder->type) {
8508 case INTEL_OUTPUT_LVDS:
8517 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8518 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8519 dev_priv->vbt.lvds_ssc_freq);
8520 return dev_priv->vbt.lvds_ssc_freq;
8526 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8528 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8529 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8530 int pipe = intel_crtc->pipe;
8535 switch (intel_crtc->config->pipe_bpp) {
8537 val |= PIPECONF_6BPC;
8540 val |= PIPECONF_8BPC;
8543 val |= PIPECONF_10BPC;
8546 val |= PIPECONF_12BPC;
8549 /* Case prevented by intel_choose_pipe_bpp_dither. */
8553 if (intel_crtc->config->dither)
8554 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8556 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8557 val |= PIPECONF_INTERLACED_ILK;
8559 val |= PIPECONF_PROGRESSIVE;
8561 if (intel_crtc->config->limited_color_range)
8562 val |= PIPECONF_COLOR_RANGE_SELECT;
8564 I915_WRITE(PIPECONF(pipe), val);
8565 POSTING_READ(PIPECONF(pipe));
8569 * Set up the pipe CSC unit.
8571 * Currently only full range RGB to limited range RGB conversion
8572 * is supported, but eventually this should handle various
8573 * RGB<->YCbCr scenarios as well.
8575 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8577 struct drm_device *dev = crtc->dev;
8578 struct drm_i915_private *dev_priv = dev->dev_private;
8579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8580 int pipe = intel_crtc->pipe;
8581 uint16_t coeff = 0x7800; /* 1.0 */
8584 * TODO: Check what kind of values actually come out of the pipe
8585 * with these coeff/postoff values and adjust to get the best
8586 * accuracy. Perhaps we even need to take the bpc value into
8590 if (intel_crtc->config->limited_color_range)
8591 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8594 * GY/GU and RY/RU should be the other way around according
8595 * to BSpec, but reality doesn't agree. Just set them up in
8596 * a way that results in the correct picture.
8598 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8599 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8601 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8602 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8604 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8605 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8607 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8608 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8609 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8611 if (INTEL_INFO(dev)->gen > 6) {
8612 uint16_t postoff = 0;
8614 if (intel_crtc->config->limited_color_range)
8615 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8617 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8618 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8619 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8621 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8623 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8625 if (intel_crtc->config->limited_color_range)
8626 mode |= CSC_BLACK_SCREEN_OFFSET;
8628 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8632 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8634 struct drm_device *dev = crtc->dev;
8635 struct drm_i915_private *dev_priv = dev->dev_private;
8636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8637 enum pipe pipe = intel_crtc->pipe;
8638 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8643 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8644 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8646 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8647 val |= PIPECONF_INTERLACED_ILK;
8649 val |= PIPECONF_PROGRESSIVE;
8651 I915_WRITE(PIPECONF(cpu_transcoder), val);
8652 POSTING_READ(PIPECONF(cpu_transcoder));
8654 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8655 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8657 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8660 switch (intel_crtc->config->pipe_bpp) {
8662 val |= PIPEMISC_DITHER_6_BPC;
8665 val |= PIPEMISC_DITHER_8_BPC;
8668 val |= PIPEMISC_DITHER_10_BPC;
8671 val |= PIPEMISC_DITHER_12_BPC;
8674 /* Case prevented by pipe_config_set_bpp. */
8678 if (intel_crtc->config->dither)
8679 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8681 I915_WRITE(PIPEMISC(pipe), val);
8685 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8686 struct intel_crtc_state *crtc_state,
8687 intel_clock_t *clock,
8688 bool *has_reduced_clock,
8689 intel_clock_t *reduced_clock)
8691 struct drm_device *dev = crtc->dev;
8692 struct drm_i915_private *dev_priv = dev->dev_private;
8694 const intel_limit_t *limit;
8697 refclk = ironlake_get_refclk(crtc_state);
8700 * Returns a set of divisors for the desired target clock with the given
8701 * refclk, or FALSE. The returned values represent the clock equation:
8702 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8704 limit = intel_limit(crtc_state, refclk);
8705 ret = dev_priv->display.find_dpll(limit, crtc_state,
8706 crtc_state->port_clock,
8707 refclk, NULL, clock);
8714 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8717 * Account for spread spectrum to avoid
8718 * oversubscribing the link. Max center spread
8719 * is 2.5%; use 5% for safety's sake.
8721 u32 bps = target_clock * bpp * 21 / 20;
8722 return DIV_ROUND_UP(bps, link_bw * 8);
8725 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8727 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8730 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8731 struct intel_crtc_state *crtc_state,
8733 intel_clock_t *reduced_clock, u32 *fp2)
8735 struct drm_crtc *crtc = &intel_crtc->base;
8736 struct drm_device *dev = crtc->dev;
8737 struct drm_i915_private *dev_priv = dev->dev_private;
8738 struct drm_atomic_state *state = crtc_state->base.state;
8739 struct drm_connector *connector;
8740 struct drm_connector_state *connector_state;
8741 struct intel_encoder *encoder;
8743 int factor, num_connectors = 0, i;
8744 bool is_lvds = false, is_sdvo = false;
8746 for_each_connector_in_state(state, connector, connector_state, i) {
8747 if (connector_state->crtc != crtc_state->base.crtc)
8750 encoder = to_intel_encoder(connector_state->best_encoder);
8752 switch (encoder->type) {
8753 case INTEL_OUTPUT_LVDS:
8756 case INTEL_OUTPUT_SDVO:
8757 case INTEL_OUTPUT_HDMI:
8767 /* Enable autotuning of the PLL clock (if permissible) */
8770 if ((intel_panel_use_ssc(dev_priv) &&
8771 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8772 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8774 } else if (crtc_state->sdvo_tv_clock)
8777 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8780 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8786 dpll |= DPLLB_MODE_LVDS;
8788 dpll |= DPLLB_MODE_DAC_SERIAL;
8790 dpll |= (crtc_state->pixel_multiplier - 1)
8791 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8794 dpll |= DPLL_SDVO_HIGH_SPEED;
8795 if (crtc_state->has_dp_encoder)
8796 dpll |= DPLL_SDVO_HIGH_SPEED;
8798 /* compute bitmask from p1 value */
8799 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8801 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8803 switch (crtc_state->dpll.p2) {
8805 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8808 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8811 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8814 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8818 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8819 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8821 dpll |= PLL_REF_INPUT_DREFCLK;
8823 return dpll | DPLL_VCO_ENABLE;
8826 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8827 struct intel_crtc_state *crtc_state)
8829 struct drm_device *dev = crtc->base.dev;
8830 intel_clock_t clock, reduced_clock;
8831 u32 dpll = 0, fp = 0, fp2 = 0;
8832 bool ok, has_reduced_clock = false;
8833 bool is_lvds = false;
8834 struct intel_shared_dpll *pll;
8836 memset(&crtc_state->dpll_hw_state, 0,
8837 sizeof(crtc_state->dpll_hw_state));
8839 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8841 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8842 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8844 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8845 &has_reduced_clock, &reduced_clock);
8846 if (!ok && !crtc_state->clock_set) {
8847 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8850 /* Compat-code for transition, will disappear. */
8851 if (!crtc_state->clock_set) {
8852 crtc_state->dpll.n = clock.n;
8853 crtc_state->dpll.m1 = clock.m1;
8854 crtc_state->dpll.m2 = clock.m2;
8855 crtc_state->dpll.p1 = clock.p1;
8856 crtc_state->dpll.p2 = clock.p2;
8859 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8860 if (crtc_state->has_pch_encoder) {
8861 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8862 if (has_reduced_clock)
8863 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8865 dpll = ironlake_compute_dpll(crtc, crtc_state,
8866 &fp, &reduced_clock,
8867 has_reduced_clock ? &fp2 : NULL);
8869 crtc_state->dpll_hw_state.dpll = dpll;
8870 crtc_state->dpll_hw_state.fp0 = fp;
8871 if (has_reduced_clock)
8872 crtc_state->dpll_hw_state.fp1 = fp2;
8874 crtc_state->dpll_hw_state.fp1 = fp;
8876 pll = intel_get_shared_dpll(crtc, crtc_state);
8878 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8879 pipe_name(crtc->pipe));
8884 if (is_lvds && has_reduced_clock)
8885 crtc->lowfreq_avail = true;
8887 crtc->lowfreq_avail = false;
8892 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8893 struct intel_link_m_n *m_n)
8895 struct drm_device *dev = crtc->base.dev;
8896 struct drm_i915_private *dev_priv = dev->dev_private;
8897 enum pipe pipe = crtc->pipe;
8899 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8900 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8901 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8903 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8904 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8905 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8908 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8909 enum transcoder transcoder,
8910 struct intel_link_m_n *m_n,
8911 struct intel_link_m_n *m2_n2)
8913 struct drm_device *dev = crtc->base.dev;
8914 struct drm_i915_private *dev_priv = dev->dev_private;
8915 enum pipe pipe = crtc->pipe;
8917 if (INTEL_INFO(dev)->gen >= 5) {
8918 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8919 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8920 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8922 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8923 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8924 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8925 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8926 * gen < 8) and if DRRS is supported (to make sure the
8927 * registers are not unnecessarily read).
8929 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8930 crtc->config->has_drrs) {
8931 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8932 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8933 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8935 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8936 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8937 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8940 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8941 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8942 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8944 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8945 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8946 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8950 void intel_dp_get_m_n(struct intel_crtc *crtc,
8951 struct intel_crtc_state *pipe_config)
8953 if (pipe_config->has_pch_encoder)
8954 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8956 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8957 &pipe_config->dp_m_n,
8958 &pipe_config->dp_m2_n2);
8961 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8962 struct intel_crtc_state *pipe_config)
8964 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8965 &pipe_config->fdi_m_n, NULL);
8968 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8969 struct intel_crtc_state *pipe_config)
8971 struct drm_device *dev = crtc->base.dev;
8972 struct drm_i915_private *dev_priv = dev->dev_private;
8973 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8974 uint32_t ps_ctrl = 0;
8978 /* find scaler attached to this pipe */
8979 for (i = 0; i < crtc->num_scalers; i++) {
8980 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8981 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8983 pipe_config->pch_pfit.enabled = true;
8984 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8985 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8990 scaler_state->scaler_id = id;
8992 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8994 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8999 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9000 struct intel_initial_plane_config *plane_config)
9002 struct drm_device *dev = crtc->base.dev;
9003 struct drm_i915_private *dev_priv = dev->dev_private;
9004 u32 val, base, offset, stride_mult, tiling;
9005 int pipe = crtc->pipe;
9006 int fourcc, pixel_format;
9007 unsigned int aligned_height;
9008 struct drm_framebuffer *fb;
9009 struct intel_framebuffer *intel_fb;
9011 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9013 DRM_DEBUG_KMS("failed to alloc fb\n");
9017 fb = &intel_fb->base;
9019 val = I915_READ(PLANE_CTL(pipe, 0));
9020 if (!(val & PLANE_CTL_ENABLE))
9023 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9024 fourcc = skl_format_to_fourcc(pixel_format,
9025 val & PLANE_CTL_ORDER_RGBX,
9026 val & PLANE_CTL_ALPHA_MASK);
9027 fb->pixel_format = fourcc;
9028 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9030 tiling = val & PLANE_CTL_TILED_MASK;
9032 case PLANE_CTL_TILED_LINEAR:
9033 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9035 case PLANE_CTL_TILED_X:
9036 plane_config->tiling = I915_TILING_X;
9037 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9039 case PLANE_CTL_TILED_Y:
9040 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9042 case PLANE_CTL_TILED_YF:
9043 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9046 MISSING_CASE(tiling);
9050 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9051 plane_config->base = base;
9053 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9055 val = I915_READ(PLANE_SIZE(pipe, 0));
9056 fb->height = ((val >> 16) & 0xfff) + 1;
9057 fb->width = ((val >> 0) & 0x1fff) + 1;
9059 val = I915_READ(PLANE_STRIDE(pipe, 0));
9060 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9062 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9064 aligned_height = intel_fb_align_height(dev, fb->height,
9068 plane_config->size = fb->pitches[0] * aligned_height;
9070 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9071 pipe_name(pipe), fb->width, fb->height,
9072 fb->bits_per_pixel, base, fb->pitches[0],
9073 plane_config->size);
9075 plane_config->fb = intel_fb;
9082 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9083 struct intel_crtc_state *pipe_config)
9085 struct drm_device *dev = crtc->base.dev;
9086 struct drm_i915_private *dev_priv = dev->dev_private;
9089 tmp = I915_READ(PF_CTL(crtc->pipe));
9091 if (tmp & PF_ENABLE) {
9092 pipe_config->pch_pfit.enabled = true;
9093 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9094 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9096 /* We currently do not free assignements of panel fitters on
9097 * ivb/hsw (since we don't use the higher upscaling modes which
9098 * differentiates them) so just WARN about this case for now. */
9100 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9101 PF_PIPE_SEL_IVB(crtc->pipe));
9107 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9108 struct intel_initial_plane_config *plane_config)
9110 struct drm_device *dev = crtc->base.dev;
9111 struct drm_i915_private *dev_priv = dev->dev_private;
9112 u32 val, base, offset;
9113 int pipe = crtc->pipe;
9114 int fourcc, pixel_format;
9115 unsigned int aligned_height;
9116 struct drm_framebuffer *fb;
9117 struct intel_framebuffer *intel_fb;
9119 val = I915_READ(DSPCNTR(pipe));
9120 if (!(val & DISPLAY_PLANE_ENABLE))
9123 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9125 DRM_DEBUG_KMS("failed to alloc fb\n");
9129 fb = &intel_fb->base;
9131 if (INTEL_INFO(dev)->gen >= 4) {
9132 if (val & DISPPLANE_TILED) {
9133 plane_config->tiling = I915_TILING_X;
9134 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9138 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9139 fourcc = i9xx_format_to_fourcc(pixel_format);
9140 fb->pixel_format = fourcc;
9141 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9143 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9144 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9145 offset = I915_READ(DSPOFFSET(pipe));
9147 if (plane_config->tiling)
9148 offset = I915_READ(DSPTILEOFF(pipe));
9150 offset = I915_READ(DSPLINOFF(pipe));
9152 plane_config->base = base;
9154 val = I915_READ(PIPESRC(pipe));
9155 fb->width = ((val >> 16) & 0xfff) + 1;
9156 fb->height = ((val >> 0) & 0xfff) + 1;
9158 val = I915_READ(DSPSTRIDE(pipe));
9159 fb->pitches[0] = val & 0xffffffc0;
9161 aligned_height = intel_fb_align_height(dev, fb->height,
9165 plane_config->size = fb->pitches[0] * aligned_height;
9167 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9168 pipe_name(pipe), fb->width, fb->height,
9169 fb->bits_per_pixel, base, fb->pitches[0],
9170 plane_config->size);
9172 plane_config->fb = intel_fb;
9175 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9176 struct intel_crtc_state *pipe_config)
9178 struct drm_device *dev = crtc->base.dev;
9179 struct drm_i915_private *dev_priv = dev->dev_private;
9182 if (!intel_display_power_is_enabled(dev_priv,
9183 POWER_DOMAIN_PIPE(crtc->pipe)))
9186 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9187 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9189 tmp = I915_READ(PIPECONF(crtc->pipe));
9190 if (!(tmp & PIPECONF_ENABLE))
9193 switch (tmp & PIPECONF_BPC_MASK) {
9195 pipe_config->pipe_bpp = 18;
9198 pipe_config->pipe_bpp = 24;
9200 case PIPECONF_10BPC:
9201 pipe_config->pipe_bpp = 30;
9203 case PIPECONF_12BPC:
9204 pipe_config->pipe_bpp = 36;
9210 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9211 pipe_config->limited_color_range = true;
9213 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9214 struct intel_shared_dpll *pll;
9216 pipe_config->has_pch_encoder = true;
9218 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9219 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9220 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9222 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9224 if (HAS_PCH_IBX(dev_priv->dev)) {
9225 pipe_config->shared_dpll =
9226 (enum intel_dpll_id) crtc->pipe;
9228 tmp = I915_READ(PCH_DPLL_SEL);
9229 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9230 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9232 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9235 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9237 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9238 &pipe_config->dpll_hw_state));
9240 tmp = pipe_config->dpll_hw_state.dpll;
9241 pipe_config->pixel_multiplier =
9242 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9243 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9245 ironlake_pch_clock_get(crtc, pipe_config);
9247 pipe_config->pixel_multiplier = 1;
9250 intel_get_pipe_timings(crtc, pipe_config);
9252 ironlake_get_pfit_config(crtc, pipe_config);
9257 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9259 struct drm_device *dev = dev_priv->dev;
9260 struct intel_crtc *crtc;
9262 for_each_intel_crtc(dev, crtc)
9263 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9264 pipe_name(crtc->pipe));
9266 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9267 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9268 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9269 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9270 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9271 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9272 "CPU PWM1 enabled\n");
9273 if (IS_HASWELL(dev))
9274 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9275 "CPU PWM2 enabled\n");
9276 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9277 "PCH PWM1 enabled\n");
9278 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9279 "Utility pin enabled\n");
9280 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9283 * In theory we can still leave IRQs enabled, as long as only the HPD
9284 * interrupts remain enabled. We used to check for that, but since it's
9285 * gen-specific and since we only disable LCPLL after we fully disable
9286 * the interrupts, the check below should be enough.
9288 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9291 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9293 struct drm_device *dev = dev_priv->dev;
9295 if (IS_HASWELL(dev))
9296 return I915_READ(D_COMP_HSW);
9298 return I915_READ(D_COMP_BDW);
9301 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9303 struct drm_device *dev = dev_priv->dev;
9305 if (IS_HASWELL(dev)) {
9306 mutex_lock(&dev_priv->rps.hw_lock);
9307 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9309 DRM_ERROR("Failed to write to D_COMP\n");
9310 mutex_unlock(&dev_priv->rps.hw_lock);
9312 I915_WRITE(D_COMP_BDW, val);
9313 POSTING_READ(D_COMP_BDW);
9318 * This function implements pieces of two sequences from BSpec:
9319 * - Sequence for display software to disable LCPLL
9320 * - Sequence for display software to allow package C8+
9321 * The steps implemented here are just the steps that actually touch the LCPLL
9322 * register. Callers should take care of disabling all the display engine
9323 * functions, doing the mode unset, fixing interrupts, etc.
9325 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9326 bool switch_to_fclk, bool allow_power_down)
9330 assert_can_disable_lcpll(dev_priv);
9332 val = I915_READ(LCPLL_CTL);
9334 if (switch_to_fclk) {
9335 val |= LCPLL_CD_SOURCE_FCLK;
9336 I915_WRITE(LCPLL_CTL, val);
9338 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9339 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9340 DRM_ERROR("Switching to FCLK failed\n");
9342 val = I915_READ(LCPLL_CTL);
9345 val |= LCPLL_PLL_DISABLE;
9346 I915_WRITE(LCPLL_CTL, val);
9347 POSTING_READ(LCPLL_CTL);
9349 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9350 DRM_ERROR("LCPLL still locked\n");
9352 val = hsw_read_dcomp(dev_priv);
9353 val |= D_COMP_COMP_DISABLE;
9354 hsw_write_dcomp(dev_priv, val);
9357 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9359 DRM_ERROR("D_COMP RCOMP still in progress\n");
9361 if (allow_power_down) {
9362 val = I915_READ(LCPLL_CTL);
9363 val |= LCPLL_POWER_DOWN_ALLOW;
9364 I915_WRITE(LCPLL_CTL, val);
9365 POSTING_READ(LCPLL_CTL);
9370 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9373 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9377 val = I915_READ(LCPLL_CTL);
9379 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9380 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9384 * Make sure we're not on PC8 state before disabling PC8, otherwise
9385 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9387 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9389 if (val & LCPLL_POWER_DOWN_ALLOW) {
9390 val &= ~LCPLL_POWER_DOWN_ALLOW;
9391 I915_WRITE(LCPLL_CTL, val);
9392 POSTING_READ(LCPLL_CTL);
9395 val = hsw_read_dcomp(dev_priv);
9396 val |= D_COMP_COMP_FORCE;
9397 val &= ~D_COMP_COMP_DISABLE;
9398 hsw_write_dcomp(dev_priv, val);
9400 val = I915_READ(LCPLL_CTL);
9401 val &= ~LCPLL_PLL_DISABLE;
9402 I915_WRITE(LCPLL_CTL, val);
9404 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9405 DRM_ERROR("LCPLL not locked yet\n");
9407 if (val & LCPLL_CD_SOURCE_FCLK) {
9408 val = I915_READ(LCPLL_CTL);
9409 val &= ~LCPLL_CD_SOURCE_FCLK;
9410 I915_WRITE(LCPLL_CTL, val);
9412 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9413 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9414 DRM_ERROR("Switching back to LCPLL failed\n");
9417 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9418 intel_update_cdclk(dev_priv->dev);
9422 * Package states C8 and deeper are really deep PC states that can only be
9423 * reached when all the devices on the system allow it, so even if the graphics
9424 * device allows PC8+, it doesn't mean the system will actually get to these
9425 * states. Our driver only allows PC8+ when going into runtime PM.
9427 * The requirements for PC8+ are that all the outputs are disabled, the power
9428 * well is disabled and most interrupts are disabled, and these are also
9429 * requirements for runtime PM. When these conditions are met, we manually do
9430 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9431 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9434 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9435 * the state of some registers, so when we come back from PC8+ we need to
9436 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9437 * need to take care of the registers kept by RC6. Notice that this happens even
9438 * if we don't put the device in PCI D3 state (which is what currently happens
9439 * because of the runtime PM support).
9441 * For more, read "Display Sequences for Package C8" on the hardware
9444 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9446 struct drm_device *dev = dev_priv->dev;
9449 DRM_DEBUG_KMS("Enabling package C8+\n");
9451 if (HAS_PCH_LPT_LP(dev)) {
9452 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9453 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9454 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9457 lpt_disable_clkout_dp(dev);
9458 hsw_disable_lcpll(dev_priv, true, true);
9461 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9463 struct drm_device *dev = dev_priv->dev;
9466 DRM_DEBUG_KMS("Disabling package C8+\n");
9468 hsw_restore_lcpll(dev_priv);
9469 lpt_init_pch_refclk(dev);
9471 if (HAS_PCH_LPT_LP(dev)) {
9472 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9473 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9474 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9477 intel_prepare_ddi(dev);
9480 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9482 struct drm_device *dev = old_state->dev;
9483 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9485 broxton_set_cdclk(dev, req_cdclk);
9488 /* compute the max rate for new configuration */
9489 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9491 struct intel_crtc *intel_crtc;
9492 struct intel_crtc_state *crtc_state;
9493 int max_pixel_rate = 0;
9495 for_each_intel_crtc(state->dev, intel_crtc) {
9498 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9499 if (IS_ERR(crtc_state))
9500 return PTR_ERR(crtc_state);
9502 if (!crtc_state->base.enable)
9505 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9507 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9508 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9509 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9511 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9514 return max_pixel_rate;
9517 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9519 struct drm_i915_private *dev_priv = dev->dev_private;
9523 if (WARN((I915_READ(LCPLL_CTL) &
9524 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9525 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9526 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9527 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9528 "trying to change cdclk frequency with cdclk not enabled\n"))
9531 mutex_lock(&dev_priv->rps.hw_lock);
9532 ret = sandybridge_pcode_write(dev_priv,
9533 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9534 mutex_unlock(&dev_priv->rps.hw_lock);
9536 DRM_ERROR("failed to inform pcode about cdclk change\n");
9540 val = I915_READ(LCPLL_CTL);
9541 val |= LCPLL_CD_SOURCE_FCLK;
9542 I915_WRITE(LCPLL_CTL, val);
9544 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9545 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9546 DRM_ERROR("Switching to FCLK failed\n");
9548 val = I915_READ(LCPLL_CTL);
9549 val &= ~LCPLL_CLK_FREQ_MASK;
9553 val |= LCPLL_CLK_FREQ_450;
9557 val |= LCPLL_CLK_FREQ_54O_BDW;
9561 val |= LCPLL_CLK_FREQ_337_5_BDW;
9565 val |= LCPLL_CLK_FREQ_675_BDW;
9569 WARN(1, "invalid cdclk frequency\n");
9573 I915_WRITE(LCPLL_CTL, val);
9575 val = I915_READ(LCPLL_CTL);
9576 val &= ~LCPLL_CD_SOURCE_FCLK;
9577 I915_WRITE(LCPLL_CTL, val);
9579 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9580 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9581 DRM_ERROR("Switching back to LCPLL failed\n");
9583 mutex_lock(&dev_priv->rps.hw_lock);
9584 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9585 mutex_unlock(&dev_priv->rps.hw_lock);
9587 intel_update_cdclk(dev);
9589 WARN(cdclk != dev_priv->cdclk_freq,
9590 "cdclk requested %d kHz but got %d kHz\n",
9591 cdclk, dev_priv->cdclk_freq);
9594 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9596 struct drm_i915_private *dev_priv = to_i915(state->dev);
9597 int max_pixclk = ilk_max_pixel_rate(state);
9601 * FIXME should also account for plane ratio
9602 * once 64bpp pixel formats are supported.
9604 if (max_pixclk > 540000)
9606 else if (max_pixclk > 450000)
9608 else if (max_pixclk > 337500)
9614 * FIXME move the cdclk caclulation to
9615 * compute_config() so we can fail gracegully.
9617 if (cdclk > dev_priv->max_cdclk_freq) {
9618 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9619 cdclk, dev_priv->max_cdclk_freq);
9620 cdclk = dev_priv->max_cdclk_freq;
9623 to_intel_atomic_state(state)->cdclk = cdclk;
9628 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9630 struct drm_device *dev = old_state->dev;
9631 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9633 broadwell_set_cdclk(dev, req_cdclk);
9636 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9637 struct intel_crtc_state *crtc_state)
9639 if (!intel_ddi_pll_select(crtc, crtc_state))
9642 crtc->lowfreq_avail = false;
9647 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9649 struct intel_crtc_state *pipe_config)
9653 pipe_config->ddi_pll_sel = SKL_DPLL0;
9654 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9657 pipe_config->ddi_pll_sel = SKL_DPLL1;
9658 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9661 pipe_config->ddi_pll_sel = SKL_DPLL2;
9662 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9665 DRM_ERROR("Incorrect port type\n");
9669 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9671 struct intel_crtc_state *pipe_config)
9673 u32 temp, dpll_ctl1;
9675 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9676 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9678 switch (pipe_config->ddi_pll_sel) {
9681 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9682 * of the shared DPLL framework and thus needs to be read out
9685 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9686 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9689 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9692 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9695 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9700 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9702 struct intel_crtc_state *pipe_config)
9704 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9706 switch (pipe_config->ddi_pll_sel) {
9707 case PORT_CLK_SEL_WRPLL1:
9708 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9710 case PORT_CLK_SEL_WRPLL2:
9711 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9716 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9717 struct intel_crtc_state *pipe_config)
9719 struct drm_device *dev = crtc->base.dev;
9720 struct drm_i915_private *dev_priv = dev->dev_private;
9721 struct intel_shared_dpll *pll;
9725 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9727 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9729 if (IS_SKYLAKE(dev))
9730 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9731 else if (IS_BROXTON(dev))
9732 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9734 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9736 if (pipe_config->shared_dpll >= 0) {
9737 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9739 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9740 &pipe_config->dpll_hw_state));
9744 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9745 * DDI E. So just check whether this pipe is wired to DDI E and whether
9746 * the PCH transcoder is on.
9748 if (INTEL_INFO(dev)->gen < 9 &&
9749 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9750 pipe_config->has_pch_encoder = true;
9752 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9753 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9754 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9756 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9760 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9761 struct intel_crtc_state *pipe_config)
9763 struct drm_device *dev = crtc->base.dev;
9764 struct drm_i915_private *dev_priv = dev->dev_private;
9765 enum intel_display_power_domain pfit_domain;
9768 if (!intel_display_power_is_enabled(dev_priv,
9769 POWER_DOMAIN_PIPE(crtc->pipe)))
9772 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9773 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9775 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9776 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9777 enum pipe trans_edp_pipe;
9778 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9780 WARN(1, "unknown pipe linked to edp transcoder\n");
9781 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9782 case TRANS_DDI_EDP_INPUT_A_ON:
9783 trans_edp_pipe = PIPE_A;
9785 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9786 trans_edp_pipe = PIPE_B;
9788 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9789 trans_edp_pipe = PIPE_C;
9793 if (trans_edp_pipe == crtc->pipe)
9794 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9797 if (!intel_display_power_is_enabled(dev_priv,
9798 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9801 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9802 if (!(tmp & PIPECONF_ENABLE))
9805 haswell_get_ddi_port_state(crtc, pipe_config);
9807 intel_get_pipe_timings(crtc, pipe_config);
9809 if (INTEL_INFO(dev)->gen >= 9) {
9810 skl_init_scalers(dev, crtc, pipe_config);
9813 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9815 if (INTEL_INFO(dev)->gen >= 9) {
9816 pipe_config->scaler_state.scaler_id = -1;
9817 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9820 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9821 if (INTEL_INFO(dev)->gen >= 9)
9822 skylake_get_pfit_config(crtc, pipe_config);
9824 ironlake_get_pfit_config(crtc, pipe_config);
9827 if (IS_HASWELL(dev))
9828 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9829 (I915_READ(IPS_CTL) & IPS_ENABLE);
9831 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9832 pipe_config->pixel_multiplier =
9833 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9835 pipe_config->pixel_multiplier = 1;
9841 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9843 struct drm_device *dev = crtc->dev;
9844 struct drm_i915_private *dev_priv = dev->dev_private;
9845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9846 uint32_t cntl = 0, size = 0;
9849 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9850 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9851 unsigned int stride = roundup_pow_of_two(width) * 4;
9855 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9866 cntl |= CURSOR_ENABLE |
9867 CURSOR_GAMMA_ENABLE |
9868 CURSOR_FORMAT_ARGB |
9869 CURSOR_STRIDE(stride);
9871 size = (height << 12) | width;
9874 if (intel_crtc->cursor_cntl != 0 &&
9875 (intel_crtc->cursor_base != base ||
9876 intel_crtc->cursor_size != size ||
9877 intel_crtc->cursor_cntl != cntl)) {
9878 /* On these chipsets we can only modify the base/size/stride
9879 * whilst the cursor is disabled.
9881 I915_WRITE(CURCNTR(PIPE_A), 0);
9882 POSTING_READ(CURCNTR(PIPE_A));
9883 intel_crtc->cursor_cntl = 0;
9886 if (intel_crtc->cursor_base != base) {
9887 I915_WRITE(CURBASE(PIPE_A), base);
9888 intel_crtc->cursor_base = base;
9891 if (intel_crtc->cursor_size != size) {
9892 I915_WRITE(CURSIZE, size);
9893 intel_crtc->cursor_size = size;
9896 if (intel_crtc->cursor_cntl != cntl) {
9897 I915_WRITE(CURCNTR(PIPE_A), cntl);
9898 POSTING_READ(CURCNTR(PIPE_A));
9899 intel_crtc->cursor_cntl = cntl;
9903 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9905 struct drm_device *dev = crtc->dev;
9906 struct drm_i915_private *dev_priv = dev->dev_private;
9907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9908 int pipe = intel_crtc->pipe;
9913 cntl = MCURSOR_GAMMA_ENABLE;
9914 switch (intel_crtc->base.cursor->state->crtc_w) {
9916 cntl |= CURSOR_MODE_64_ARGB_AX;
9919 cntl |= CURSOR_MODE_128_ARGB_AX;
9922 cntl |= CURSOR_MODE_256_ARGB_AX;
9925 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9928 cntl |= pipe << 28; /* Connect to correct pipe */
9931 cntl |= CURSOR_PIPE_CSC_ENABLE;
9934 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9935 cntl |= CURSOR_ROTATE_180;
9937 if (intel_crtc->cursor_cntl != cntl) {
9938 I915_WRITE(CURCNTR(pipe), cntl);
9939 POSTING_READ(CURCNTR(pipe));
9940 intel_crtc->cursor_cntl = cntl;
9943 /* and commit changes on next vblank */
9944 I915_WRITE(CURBASE(pipe), base);
9945 POSTING_READ(CURBASE(pipe));
9947 intel_crtc->cursor_base = base;
9950 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9951 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9954 struct drm_device *dev = crtc->dev;
9955 struct drm_i915_private *dev_priv = dev->dev_private;
9956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9957 int pipe = intel_crtc->pipe;
9958 struct drm_plane_state *cursor_state = crtc->cursor->state;
9959 int x = cursor_state->crtc_x;
9960 int y = cursor_state->crtc_y;
9961 u32 base = 0, pos = 0;
9964 base = intel_crtc->cursor_addr;
9966 if (x >= intel_crtc->config->pipe_src_w)
9969 if (y >= intel_crtc->config->pipe_src_h)
9973 if (x + cursor_state->crtc_w <= 0)
9976 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9979 pos |= x << CURSOR_X_SHIFT;
9982 if (y + cursor_state->crtc_h <= 0)
9985 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9988 pos |= y << CURSOR_Y_SHIFT;
9990 if (base == 0 && intel_crtc->cursor_base == 0)
9993 I915_WRITE(CURPOS(pipe), pos);
9995 /* ILK+ do this automagically */
9996 if (HAS_GMCH_DISPLAY(dev) &&
9997 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9998 base += (cursor_state->crtc_h *
9999 cursor_state->crtc_w - 1) * 4;
10002 if (IS_845G(dev) || IS_I865G(dev))
10003 i845_update_cursor(crtc, base);
10005 i9xx_update_cursor(crtc, base);
10008 static bool cursor_size_ok(struct drm_device *dev,
10009 uint32_t width, uint32_t height)
10011 if (width == 0 || height == 0)
10015 * 845g/865g are special in that they are only limited by
10016 * the width of their cursors, the height is arbitrary up to
10017 * the precision of the register. Everything else requires
10018 * square cursors, limited to a few power-of-two sizes.
10020 if (IS_845G(dev) || IS_I865G(dev)) {
10021 if ((width & 63) != 0)
10024 if (width > (IS_845G(dev) ? 64 : 512))
10030 switch (width | height) {
10045 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10046 u16 *blue, uint32_t start, uint32_t size)
10048 int end = (start + size > 256) ? 256 : start + size, i;
10049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10051 for (i = start; i < end; i++) {
10052 intel_crtc->lut_r[i] = red[i] >> 8;
10053 intel_crtc->lut_g[i] = green[i] >> 8;
10054 intel_crtc->lut_b[i] = blue[i] >> 8;
10057 intel_crtc_load_lut(crtc);
10060 /* VESA 640x480x72Hz mode to set on the pipe */
10061 static struct drm_display_mode load_detect_mode = {
10062 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10063 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10066 struct drm_framebuffer *
10067 __intel_framebuffer_create(struct drm_device *dev,
10068 struct drm_mode_fb_cmd2 *mode_cmd,
10069 struct drm_i915_gem_object *obj)
10071 struct intel_framebuffer *intel_fb;
10074 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10076 drm_gem_object_unreference(&obj->base);
10077 return ERR_PTR(-ENOMEM);
10080 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10084 return &intel_fb->base;
10086 drm_gem_object_unreference(&obj->base);
10089 return ERR_PTR(ret);
10092 static struct drm_framebuffer *
10093 intel_framebuffer_create(struct drm_device *dev,
10094 struct drm_mode_fb_cmd2 *mode_cmd,
10095 struct drm_i915_gem_object *obj)
10097 struct drm_framebuffer *fb;
10100 ret = i915_mutex_lock_interruptible(dev);
10102 return ERR_PTR(ret);
10103 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10104 mutex_unlock(&dev->struct_mutex);
10110 intel_framebuffer_pitch_for_width(int width, int bpp)
10112 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10113 return ALIGN(pitch, 64);
10117 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10119 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10120 return PAGE_ALIGN(pitch * mode->vdisplay);
10123 static struct drm_framebuffer *
10124 intel_framebuffer_create_for_mode(struct drm_device *dev,
10125 struct drm_display_mode *mode,
10126 int depth, int bpp)
10128 struct drm_i915_gem_object *obj;
10129 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10131 obj = i915_gem_alloc_object(dev,
10132 intel_framebuffer_size_for_mode(mode, bpp));
10134 return ERR_PTR(-ENOMEM);
10136 mode_cmd.width = mode->hdisplay;
10137 mode_cmd.height = mode->vdisplay;
10138 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10140 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10142 return intel_framebuffer_create(dev, &mode_cmd, obj);
10145 static struct drm_framebuffer *
10146 mode_fits_in_fbdev(struct drm_device *dev,
10147 struct drm_display_mode *mode)
10149 #ifdef CONFIG_DRM_FBDEV_EMULATION
10150 struct drm_i915_private *dev_priv = dev->dev_private;
10151 struct drm_i915_gem_object *obj;
10152 struct drm_framebuffer *fb;
10154 if (!dev_priv->fbdev)
10157 if (!dev_priv->fbdev->fb)
10160 obj = dev_priv->fbdev->fb->obj;
10163 fb = &dev_priv->fbdev->fb->base;
10164 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10165 fb->bits_per_pixel))
10168 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10177 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10178 struct drm_crtc *crtc,
10179 struct drm_display_mode *mode,
10180 struct drm_framebuffer *fb,
10183 struct drm_plane_state *plane_state;
10184 int hdisplay, vdisplay;
10187 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10188 if (IS_ERR(plane_state))
10189 return PTR_ERR(plane_state);
10192 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10194 hdisplay = vdisplay = 0;
10196 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10199 drm_atomic_set_fb_for_plane(plane_state, fb);
10200 plane_state->crtc_x = 0;
10201 plane_state->crtc_y = 0;
10202 plane_state->crtc_w = hdisplay;
10203 plane_state->crtc_h = vdisplay;
10204 plane_state->src_x = x << 16;
10205 plane_state->src_y = y << 16;
10206 plane_state->src_w = hdisplay << 16;
10207 plane_state->src_h = vdisplay << 16;
10212 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10213 struct drm_display_mode *mode,
10214 struct intel_load_detect_pipe *old,
10215 struct drm_modeset_acquire_ctx *ctx)
10217 struct intel_crtc *intel_crtc;
10218 struct intel_encoder *intel_encoder =
10219 intel_attached_encoder(connector);
10220 struct drm_crtc *possible_crtc;
10221 struct drm_encoder *encoder = &intel_encoder->base;
10222 struct drm_crtc *crtc = NULL;
10223 struct drm_device *dev = encoder->dev;
10224 struct drm_framebuffer *fb;
10225 struct drm_mode_config *config = &dev->mode_config;
10226 struct drm_atomic_state *state = NULL;
10227 struct drm_connector_state *connector_state;
10228 struct intel_crtc_state *crtc_state;
10231 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10232 connector->base.id, connector->name,
10233 encoder->base.id, encoder->name);
10236 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10241 * Algorithm gets a little messy:
10243 * - if the connector already has an assigned crtc, use it (but make
10244 * sure it's on first)
10246 * - try to find the first unused crtc that can drive this connector,
10247 * and use that if we find one
10250 /* See if we already have a CRTC for this connector */
10251 if (encoder->crtc) {
10252 crtc = encoder->crtc;
10254 ret = drm_modeset_lock(&crtc->mutex, ctx);
10257 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10261 old->dpms_mode = connector->dpms;
10262 old->load_detect_temp = false;
10264 /* Make sure the crtc and connector are running */
10265 if (connector->dpms != DRM_MODE_DPMS_ON)
10266 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10271 /* Find an unused one (if possible) */
10272 for_each_crtc(dev, possible_crtc) {
10274 if (!(encoder->possible_crtcs & (1 << i)))
10276 if (possible_crtc->state->enable)
10279 crtc = possible_crtc;
10284 * If we didn't find an unused CRTC, don't use any.
10287 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10291 ret = drm_modeset_lock(&crtc->mutex, ctx);
10294 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10298 intel_crtc = to_intel_crtc(crtc);
10299 old->dpms_mode = connector->dpms;
10300 old->load_detect_temp = true;
10301 old->release_fb = NULL;
10303 state = drm_atomic_state_alloc(dev);
10307 state->acquire_ctx = ctx;
10309 connector_state = drm_atomic_get_connector_state(state, connector);
10310 if (IS_ERR(connector_state)) {
10311 ret = PTR_ERR(connector_state);
10315 connector_state->crtc = crtc;
10316 connector_state->best_encoder = &intel_encoder->base;
10318 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10319 if (IS_ERR(crtc_state)) {
10320 ret = PTR_ERR(crtc_state);
10324 crtc_state->base.active = crtc_state->base.enable = true;
10327 mode = &load_detect_mode;
10329 /* We need a framebuffer large enough to accommodate all accesses
10330 * that the plane may generate whilst we perform load detection.
10331 * We can not rely on the fbcon either being present (we get called
10332 * during its initialisation to detect all boot displays, or it may
10333 * not even exist) or that it is large enough to satisfy the
10336 fb = mode_fits_in_fbdev(dev, mode);
10338 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10339 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10340 old->release_fb = fb;
10342 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10344 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10348 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10352 drm_mode_copy(&crtc_state->base.mode, mode);
10354 if (drm_atomic_commit(state)) {
10355 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10356 if (old->release_fb)
10357 old->release_fb->funcs->destroy(old->release_fb);
10360 crtc->primary->crtc = crtc;
10362 /* let the connector get through one full cycle before testing */
10363 intel_wait_for_vblank(dev, intel_crtc->pipe);
10367 drm_atomic_state_free(state);
10370 if (ret == -EDEADLK) {
10371 drm_modeset_backoff(ctx);
10378 void intel_release_load_detect_pipe(struct drm_connector *connector,
10379 struct intel_load_detect_pipe *old,
10380 struct drm_modeset_acquire_ctx *ctx)
10382 struct drm_device *dev = connector->dev;
10383 struct intel_encoder *intel_encoder =
10384 intel_attached_encoder(connector);
10385 struct drm_encoder *encoder = &intel_encoder->base;
10386 struct drm_crtc *crtc = encoder->crtc;
10387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10388 struct drm_atomic_state *state;
10389 struct drm_connector_state *connector_state;
10390 struct intel_crtc_state *crtc_state;
10393 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10394 connector->base.id, connector->name,
10395 encoder->base.id, encoder->name);
10397 if (old->load_detect_temp) {
10398 state = drm_atomic_state_alloc(dev);
10402 state->acquire_ctx = ctx;
10404 connector_state = drm_atomic_get_connector_state(state, connector);
10405 if (IS_ERR(connector_state))
10408 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10409 if (IS_ERR(crtc_state))
10412 connector_state->best_encoder = NULL;
10413 connector_state->crtc = NULL;
10415 crtc_state->base.enable = crtc_state->base.active = false;
10417 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10422 ret = drm_atomic_commit(state);
10426 if (old->release_fb) {
10427 drm_framebuffer_unregister_private(old->release_fb);
10428 drm_framebuffer_unreference(old->release_fb);
10434 /* Switch crtc and encoder back off if necessary */
10435 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10436 connector->funcs->dpms(connector, old->dpms_mode);
10440 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10441 drm_atomic_state_free(state);
10444 static int i9xx_pll_refclk(struct drm_device *dev,
10445 const struct intel_crtc_state *pipe_config)
10447 struct drm_i915_private *dev_priv = dev->dev_private;
10448 u32 dpll = pipe_config->dpll_hw_state.dpll;
10450 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10451 return dev_priv->vbt.lvds_ssc_freq;
10452 else if (HAS_PCH_SPLIT(dev))
10454 else if (!IS_GEN2(dev))
10460 /* Returns the clock of the currently programmed mode of the given pipe. */
10461 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10462 struct intel_crtc_state *pipe_config)
10464 struct drm_device *dev = crtc->base.dev;
10465 struct drm_i915_private *dev_priv = dev->dev_private;
10466 int pipe = pipe_config->cpu_transcoder;
10467 u32 dpll = pipe_config->dpll_hw_state.dpll;
10469 intel_clock_t clock;
10471 int refclk = i9xx_pll_refclk(dev, pipe_config);
10473 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10474 fp = pipe_config->dpll_hw_state.fp0;
10476 fp = pipe_config->dpll_hw_state.fp1;
10478 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10479 if (IS_PINEVIEW(dev)) {
10480 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10481 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10483 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10484 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10487 if (!IS_GEN2(dev)) {
10488 if (IS_PINEVIEW(dev))
10489 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10490 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10492 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10493 DPLL_FPA01_P1_POST_DIV_SHIFT);
10495 switch (dpll & DPLL_MODE_MASK) {
10496 case DPLLB_MODE_DAC_SERIAL:
10497 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10500 case DPLLB_MODE_LVDS:
10501 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10505 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10506 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10510 if (IS_PINEVIEW(dev))
10511 port_clock = pnv_calc_dpll_params(refclk, &clock);
10513 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10515 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10516 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10519 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10520 DPLL_FPA01_P1_POST_DIV_SHIFT);
10522 if (lvds & LVDS_CLKB_POWER_UP)
10527 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10530 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10531 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10533 if (dpll & PLL_P2_DIVIDE_BY_4)
10539 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10543 * This value includes pixel_multiplier. We will use
10544 * port_clock to compute adjusted_mode.crtc_clock in the
10545 * encoder's get_config() function.
10547 pipe_config->port_clock = port_clock;
10550 int intel_dotclock_calculate(int link_freq,
10551 const struct intel_link_m_n *m_n)
10554 * The calculation for the data clock is:
10555 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10556 * But we want to avoid losing precison if possible, so:
10557 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10559 * and the link clock is simpler:
10560 * link_clock = (m * link_clock) / n
10566 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10569 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10570 struct intel_crtc_state *pipe_config)
10572 struct drm_device *dev = crtc->base.dev;
10574 /* read out port_clock from the DPLL */
10575 i9xx_crtc_clock_get(crtc, pipe_config);
10578 * This value does not include pixel_multiplier.
10579 * We will check that port_clock and adjusted_mode.crtc_clock
10580 * agree once we know their relationship in the encoder's
10581 * get_config() function.
10583 pipe_config->base.adjusted_mode.crtc_clock =
10584 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10585 &pipe_config->fdi_m_n);
10588 /** Returns the currently programmed mode of the given pipe. */
10589 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10590 struct drm_crtc *crtc)
10592 struct drm_i915_private *dev_priv = dev->dev_private;
10593 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10594 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10595 struct drm_display_mode *mode;
10596 struct intel_crtc_state pipe_config;
10597 int htot = I915_READ(HTOTAL(cpu_transcoder));
10598 int hsync = I915_READ(HSYNC(cpu_transcoder));
10599 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10600 int vsync = I915_READ(VSYNC(cpu_transcoder));
10601 enum pipe pipe = intel_crtc->pipe;
10603 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10608 * Construct a pipe_config sufficient for getting the clock info
10609 * back out of crtc_clock_get.
10611 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10612 * to use a real value here instead.
10614 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10615 pipe_config.pixel_multiplier = 1;
10616 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10617 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10618 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10619 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10621 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10622 mode->hdisplay = (htot & 0xffff) + 1;
10623 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10624 mode->hsync_start = (hsync & 0xffff) + 1;
10625 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10626 mode->vdisplay = (vtot & 0xffff) + 1;
10627 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10628 mode->vsync_start = (vsync & 0xffff) + 1;
10629 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10631 drm_mode_set_name(mode);
10636 void intel_mark_busy(struct drm_device *dev)
10638 struct drm_i915_private *dev_priv = dev->dev_private;
10640 if (dev_priv->mm.busy)
10643 intel_runtime_pm_get(dev_priv);
10644 i915_update_gfx_val(dev_priv);
10645 if (INTEL_INFO(dev)->gen >= 6)
10646 gen6_rps_busy(dev_priv);
10647 dev_priv->mm.busy = true;
10650 void intel_mark_idle(struct drm_device *dev)
10652 struct drm_i915_private *dev_priv = dev->dev_private;
10654 if (!dev_priv->mm.busy)
10657 dev_priv->mm.busy = false;
10659 if (INTEL_INFO(dev)->gen >= 6)
10660 gen6_rps_idle(dev->dev_private);
10662 intel_runtime_pm_put(dev_priv);
10665 static void intel_crtc_destroy(struct drm_crtc *crtc)
10667 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10668 struct drm_device *dev = crtc->dev;
10669 struct intel_unpin_work *work;
10671 spin_lock_irq(&dev->event_lock);
10672 work = intel_crtc->unpin_work;
10673 intel_crtc->unpin_work = NULL;
10674 spin_unlock_irq(&dev->event_lock);
10677 cancel_work_sync(&work->work);
10681 drm_crtc_cleanup(crtc);
10686 static void intel_unpin_work_fn(struct work_struct *__work)
10688 struct intel_unpin_work *work =
10689 container_of(__work, struct intel_unpin_work, work);
10690 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10691 struct drm_device *dev = crtc->base.dev;
10692 struct drm_plane *primary = crtc->base.primary;
10694 mutex_lock(&dev->struct_mutex);
10695 intel_unpin_fb_obj(work->old_fb, primary->state);
10696 drm_gem_object_unreference(&work->pending_flip_obj->base);
10698 if (work->flip_queued_req)
10699 i915_gem_request_assign(&work->flip_queued_req, NULL);
10700 mutex_unlock(&dev->struct_mutex);
10702 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10703 drm_framebuffer_unreference(work->old_fb);
10705 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10706 atomic_dec(&crtc->unpin_work_count);
10711 static void do_intel_finish_page_flip(struct drm_device *dev,
10712 struct drm_crtc *crtc)
10714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10715 struct intel_unpin_work *work;
10716 unsigned long flags;
10718 /* Ignore early vblank irqs */
10719 if (intel_crtc == NULL)
10723 * This is called both by irq handlers and the reset code (to complete
10724 * lost pageflips) so needs the full irqsave spinlocks.
10726 spin_lock_irqsave(&dev->event_lock, flags);
10727 work = intel_crtc->unpin_work;
10729 /* Ensure we don't miss a work->pending update ... */
10732 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10733 spin_unlock_irqrestore(&dev->event_lock, flags);
10737 page_flip_completed(intel_crtc);
10739 spin_unlock_irqrestore(&dev->event_lock, flags);
10742 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10744 struct drm_i915_private *dev_priv = dev->dev_private;
10745 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10747 do_intel_finish_page_flip(dev, crtc);
10750 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10752 struct drm_i915_private *dev_priv = dev->dev_private;
10753 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10755 do_intel_finish_page_flip(dev, crtc);
10758 /* Is 'a' after or equal to 'b'? */
10759 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10761 return !((a - b) & 0x80000000);
10764 static bool page_flip_finished(struct intel_crtc *crtc)
10766 struct drm_device *dev = crtc->base.dev;
10767 struct drm_i915_private *dev_priv = dev->dev_private;
10769 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10770 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10774 * The relevant registers doen't exist on pre-ctg.
10775 * As the flip done interrupt doesn't trigger for mmio
10776 * flips on gmch platforms, a flip count check isn't
10777 * really needed there. But since ctg has the registers,
10778 * include it in the check anyway.
10780 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10784 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10785 * used the same base address. In that case the mmio flip might
10786 * have completed, but the CS hasn't even executed the flip yet.
10788 * A flip count check isn't enough as the CS might have updated
10789 * the base address just after start of vblank, but before we
10790 * managed to process the interrupt. This means we'd complete the
10791 * CS flip too soon.
10793 * Combining both checks should get us a good enough result. It may
10794 * still happen that the CS flip has been executed, but has not
10795 * yet actually completed. But in case the base address is the same
10796 * anyway, we don't really care.
10798 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10799 crtc->unpin_work->gtt_offset &&
10800 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10801 crtc->unpin_work->flip_count);
10804 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10806 struct drm_i915_private *dev_priv = dev->dev_private;
10807 struct intel_crtc *intel_crtc =
10808 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10809 unsigned long flags;
10813 * This is called both by irq handlers and the reset code (to complete
10814 * lost pageflips) so needs the full irqsave spinlocks.
10816 * NB: An MMIO update of the plane base pointer will also
10817 * generate a page-flip completion irq, i.e. every modeset
10818 * is also accompanied by a spurious intel_prepare_page_flip().
10820 spin_lock_irqsave(&dev->event_lock, flags);
10821 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10822 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10823 spin_unlock_irqrestore(&dev->event_lock, flags);
10826 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10828 /* Ensure that the work item is consistent when activating it ... */
10830 atomic_set(&work->pending, INTEL_FLIP_PENDING);
10831 /* and that it is marked active as soon as the irq could fire. */
10835 static int intel_gen2_queue_flip(struct drm_device *dev,
10836 struct drm_crtc *crtc,
10837 struct drm_framebuffer *fb,
10838 struct drm_i915_gem_object *obj,
10839 struct drm_i915_gem_request *req,
10842 struct intel_engine_cs *ring = req->ring;
10843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10847 ret = intel_ring_begin(req, 6);
10851 /* Can't queue multiple flips, so wait for the previous
10852 * one to finish before executing the next.
10854 if (intel_crtc->plane)
10855 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10857 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10858 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10859 intel_ring_emit(ring, MI_NOOP);
10860 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10861 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10862 intel_ring_emit(ring, fb->pitches[0]);
10863 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10864 intel_ring_emit(ring, 0); /* aux display base address, unused */
10866 intel_mark_page_flip_active(intel_crtc->unpin_work);
10870 static int intel_gen3_queue_flip(struct drm_device *dev,
10871 struct drm_crtc *crtc,
10872 struct drm_framebuffer *fb,
10873 struct drm_i915_gem_object *obj,
10874 struct drm_i915_gem_request *req,
10877 struct intel_engine_cs *ring = req->ring;
10878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10882 ret = intel_ring_begin(req, 6);
10886 if (intel_crtc->plane)
10887 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10889 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10890 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10891 intel_ring_emit(ring, MI_NOOP);
10892 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10893 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10894 intel_ring_emit(ring, fb->pitches[0]);
10895 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10896 intel_ring_emit(ring, MI_NOOP);
10898 intel_mark_page_flip_active(intel_crtc->unpin_work);
10902 static int intel_gen4_queue_flip(struct drm_device *dev,
10903 struct drm_crtc *crtc,
10904 struct drm_framebuffer *fb,
10905 struct drm_i915_gem_object *obj,
10906 struct drm_i915_gem_request *req,
10909 struct intel_engine_cs *ring = req->ring;
10910 struct drm_i915_private *dev_priv = dev->dev_private;
10911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10912 uint32_t pf, pipesrc;
10915 ret = intel_ring_begin(req, 4);
10919 /* i965+ uses the linear or tiled offsets from the
10920 * Display Registers (which do not change across a page-flip)
10921 * so we need only reprogram the base address.
10923 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10924 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10925 intel_ring_emit(ring, fb->pitches[0]);
10926 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10929 /* XXX Enabling the panel-fitter across page-flip is so far
10930 * untested on non-native modes, so ignore it for now.
10931 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10934 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10935 intel_ring_emit(ring, pf | pipesrc);
10937 intel_mark_page_flip_active(intel_crtc->unpin_work);
10941 static int intel_gen6_queue_flip(struct drm_device *dev,
10942 struct drm_crtc *crtc,
10943 struct drm_framebuffer *fb,
10944 struct drm_i915_gem_object *obj,
10945 struct drm_i915_gem_request *req,
10948 struct intel_engine_cs *ring = req->ring;
10949 struct drm_i915_private *dev_priv = dev->dev_private;
10950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10951 uint32_t pf, pipesrc;
10954 ret = intel_ring_begin(req, 4);
10958 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10959 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10960 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10961 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10963 /* Contrary to the suggestions in the documentation,
10964 * "Enable Panel Fitter" does not seem to be required when page
10965 * flipping with a non-native mode, and worse causes a normal
10967 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10970 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10971 intel_ring_emit(ring, pf | pipesrc);
10973 intel_mark_page_flip_active(intel_crtc->unpin_work);
10977 static int intel_gen7_queue_flip(struct drm_device *dev,
10978 struct drm_crtc *crtc,
10979 struct drm_framebuffer *fb,
10980 struct drm_i915_gem_object *obj,
10981 struct drm_i915_gem_request *req,
10984 struct intel_engine_cs *ring = req->ring;
10985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10986 uint32_t plane_bit = 0;
10989 switch (intel_crtc->plane) {
10991 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10994 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10997 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11000 WARN_ONCE(1, "unknown plane in flip command\n");
11005 if (ring->id == RCS) {
11008 * On Gen 8, SRM is now taking an extra dword to accommodate
11009 * 48bits addresses, and we need a NOOP for the batch size to
11017 * BSpec MI_DISPLAY_FLIP for IVB:
11018 * "The full packet must be contained within the same cache line."
11020 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11021 * cacheline, if we ever start emitting more commands before
11022 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11023 * then do the cacheline alignment, and finally emit the
11026 ret = intel_ring_cacheline_align(req);
11030 ret = intel_ring_begin(req, len);
11034 /* Unmask the flip-done completion message. Note that the bspec says that
11035 * we should do this for both the BCS and RCS, and that we must not unmask
11036 * more than one flip event at any time (or ensure that one flip message
11037 * can be sent by waiting for flip-done prior to queueing new flips).
11038 * Experimentation says that BCS works despite DERRMR masking all
11039 * flip-done completion events and that unmasking all planes at once
11040 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11041 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11043 if (ring->id == RCS) {
11044 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11045 intel_ring_emit(ring, DERRMR);
11046 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11047 DERRMR_PIPEB_PRI_FLIP_DONE |
11048 DERRMR_PIPEC_PRI_FLIP_DONE));
11050 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11051 MI_SRM_LRM_GLOBAL_GTT);
11053 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11054 MI_SRM_LRM_GLOBAL_GTT);
11055 intel_ring_emit(ring, DERRMR);
11056 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11057 if (IS_GEN8(dev)) {
11058 intel_ring_emit(ring, 0);
11059 intel_ring_emit(ring, MI_NOOP);
11063 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11064 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11065 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11066 intel_ring_emit(ring, (MI_NOOP));
11068 intel_mark_page_flip_active(intel_crtc->unpin_work);
11072 static bool use_mmio_flip(struct intel_engine_cs *ring,
11073 struct drm_i915_gem_object *obj)
11076 * This is not being used for older platforms, because
11077 * non-availability of flip done interrupt forces us to use
11078 * CS flips. Older platforms derive flip done using some clever
11079 * tricks involving the flip_pending status bits and vblank irqs.
11080 * So using MMIO flips there would disrupt this mechanism.
11086 if (INTEL_INFO(ring->dev)->gen < 5)
11089 if (i915.use_mmio_flip < 0)
11091 else if (i915.use_mmio_flip > 0)
11093 else if (i915.enable_execlists)
11096 return ring != i915_gem_request_get_ring(obj->last_write_req);
11099 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11100 struct intel_unpin_work *work)
11102 struct drm_device *dev = intel_crtc->base.dev;
11103 struct drm_i915_private *dev_priv = dev->dev_private;
11104 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11105 const enum pipe pipe = intel_crtc->pipe;
11108 ctl = I915_READ(PLANE_CTL(pipe, 0));
11109 ctl &= ~PLANE_CTL_TILED_MASK;
11110 switch (fb->modifier[0]) {
11111 case DRM_FORMAT_MOD_NONE:
11113 case I915_FORMAT_MOD_X_TILED:
11114 ctl |= PLANE_CTL_TILED_X;
11116 case I915_FORMAT_MOD_Y_TILED:
11117 ctl |= PLANE_CTL_TILED_Y;
11119 case I915_FORMAT_MOD_Yf_TILED:
11120 ctl |= PLANE_CTL_TILED_YF;
11123 MISSING_CASE(fb->modifier[0]);
11127 * The stride is either expressed as a multiple of 64 bytes chunks for
11128 * linear buffers or in number of tiles for tiled buffers.
11130 stride = fb->pitches[0] /
11131 intel_fb_stride_alignment(dev, fb->modifier[0],
11135 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11136 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11138 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11139 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11141 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11142 POSTING_READ(PLANE_SURF(pipe, 0));
11145 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11146 struct intel_unpin_work *work)
11148 struct drm_device *dev = intel_crtc->base.dev;
11149 struct drm_i915_private *dev_priv = dev->dev_private;
11150 struct intel_framebuffer *intel_fb =
11151 to_intel_framebuffer(intel_crtc->base.primary->fb);
11152 struct drm_i915_gem_object *obj = intel_fb->obj;
11156 reg = DSPCNTR(intel_crtc->plane);
11157 dspcntr = I915_READ(reg);
11159 if (obj->tiling_mode != I915_TILING_NONE)
11160 dspcntr |= DISPPLANE_TILED;
11162 dspcntr &= ~DISPPLANE_TILED;
11164 I915_WRITE(reg, dspcntr);
11166 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11167 POSTING_READ(DSPSURF(intel_crtc->plane));
11171 * XXX: This is the temporary way to update the plane registers until we get
11172 * around to using the usual plane update functions for MMIO flips
11174 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11176 struct intel_crtc *crtc = mmio_flip->crtc;
11177 struct intel_unpin_work *work;
11179 spin_lock_irq(&crtc->base.dev->event_lock);
11180 work = crtc->unpin_work;
11181 spin_unlock_irq(&crtc->base.dev->event_lock);
11185 intel_mark_page_flip_active(work);
11187 intel_pipe_update_start(crtc);
11189 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11190 skl_do_mmio_flip(crtc, work);
11192 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11193 ilk_do_mmio_flip(crtc, work);
11195 intel_pipe_update_end(crtc);
11198 static void intel_mmio_flip_work_func(struct work_struct *work)
11200 struct intel_mmio_flip *mmio_flip =
11201 container_of(work, struct intel_mmio_flip, work);
11203 if (mmio_flip->req) {
11204 WARN_ON(__i915_wait_request(mmio_flip->req,
11205 mmio_flip->crtc->reset_counter,
11207 &mmio_flip->i915->rps.mmioflips));
11208 i915_gem_request_unreference__unlocked(mmio_flip->req);
11211 intel_do_mmio_flip(mmio_flip);
11215 static int intel_queue_mmio_flip(struct drm_device *dev,
11216 struct drm_crtc *crtc,
11217 struct drm_framebuffer *fb,
11218 struct drm_i915_gem_object *obj,
11219 struct intel_engine_cs *ring,
11222 struct intel_mmio_flip *mmio_flip;
11224 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11225 if (mmio_flip == NULL)
11228 mmio_flip->i915 = to_i915(dev);
11229 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11230 mmio_flip->crtc = to_intel_crtc(crtc);
11232 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11233 schedule_work(&mmio_flip->work);
11238 static int intel_default_queue_flip(struct drm_device *dev,
11239 struct drm_crtc *crtc,
11240 struct drm_framebuffer *fb,
11241 struct drm_i915_gem_object *obj,
11242 struct drm_i915_gem_request *req,
11248 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11249 struct drm_crtc *crtc)
11251 struct drm_i915_private *dev_priv = dev->dev_private;
11252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11253 struct intel_unpin_work *work = intel_crtc->unpin_work;
11256 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11259 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11262 if (!work->enable_stall_check)
11265 if (work->flip_ready_vblank == 0) {
11266 if (work->flip_queued_req &&
11267 !i915_gem_request_completed(work->flip_queued_req, true))
11270 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11273 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11276 /* Potential stall - if we see that the flip has happened,
11277 * assume a missed interrupt. */
11278 if (INTEL_INFO(dev)->gen >= 4)
11279 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11281 addr = I915_READ(DSPADDR(intel_crtc->plane));
11283 /* There is a potential issue here with a false positive after a flip
11284 * to the same address. We could address this by checking for a
11285 * non-incrementing frame counter.
11287 return addr == work->gtt_offset;
11290 void intel_check_page_flip(struct drm_device *dev, int pipe)
11292 struct drm_i915_private *dev_priv = dev->dev_private;
11293 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11294 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11295 struct intel_unpin_work *work;
11297 WARN_ON(!in_interrupt());
11302 spin_lock(&dev->event_lock);
11303 work = intel_crtc->unpin_work;
11304 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11305 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11306 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11307 page_flip_completed(intel_crtc);
11310 if (work != NULL &&
11311 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11312 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11313 spin_unlock(&dev->event_lock);
11316 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11317 struct drm_framebuffer *fb,
11318 struct drm_pending_vblank_event *event,
11319 uint32_t page_flip_flags)
11321 struct drm_device *dev = crtc->dev;
11322 struct drm_i915_private *dev_priv = dev->dev_private;
11323 struct drm_framebuffer *old_fb = crtc->primary->fb;
11324 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11325 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11326 struct drm_plane *primary = crtc->primary;
11327 enum pipe pipe = intel_crtc->pipe;
11328 struct intel_unpin_work *work;
11329 struct intel_engine_cs *ring;
11331 struct drm_i915_gem_request *request = NULL;
11335 * drm_mode_page_flip_ioctl() should already catch this, but double
11336 * check to be safe. In the future we may enable pageflipping from
11337 * a disabled primary plane.
11339 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11342 /* Can't change pixel format via MI display flips. */
11343 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11347 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11348 * Note that pitch changes could also affect these register.
11350 if (INTEL_INFO(dev)->gen > 3 &&
11351 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11352 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11355 if (i915_terminally_wedged(&dev_priv->gpu_error))
11358 work = kzalloc(sizeof(*work), GFP_KERNEL);
11362 work->event = event;
11364 work->old_fb = old_fb;
11365 INIT_WORK(&work->work, intel_unpin_work_fn);
11367 ret = drm_crtc_vblank_get(crtc);
11371 /* We borrow the event spin lock for protecting unpin_work */
11372 spin_lock_irq(&dev->event_lock);
11373 if (intel_crtc->unpin_work) {
11374 /* Before declaring the flip queue wedged, check if
11375 * the hardware completed the operation behind our backs.
11377 if (__intel_pageflip_stall_check(dev, crtc)) {
11378 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11379 page_flip_completed(intel_crtc);
11381 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11382 spin_unlock_irq(&dev->event_lock);
11384 drm_crtc_vblank_put(crtc);
11389 intel_crtc->unpin_work = work;
11390 spin_unlock_irq(&dev->event_lock);
11392 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11393 flush_workqueue(dev_priv->wq);
11395 /* Reference the objects for the scheduled work. */
11396 drm_framebuffer_reference(work->old_fb);
11397 drm_gem_object_reference(&obj->base);
11399 crtc->primary->fb = fb;
11400 update_state_fb(crtc->primary);
11402 work->pending_flip_obj = obj;
11404 ret = i915_mutex_lock_interruptible(dev);
11408 atomic_inc(&intel_crtc->unpin_work_count);
11409 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11411 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11412 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11414 if (IS_VALLEYVIEW(dev)) {
11415 ring = &dev_priv->ring[BCS];
11416 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11417 /* vlv: DISPLAY_FLIP fails to change tiling */
11419 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11420 ring = &dev_priv->ring[BCS];
11421 } else if (INTEL_INFO(dev)->gen >= 7) {
11422 ring = i915_gem_request_get_ring(obj->last_write_req);
11423 if (ring == NULL || ring->id != RCS)
11424 ring = &dev_priv->ring[BCS];
11426 ring = &dev_priv->ring[RCS];
11429 mmio_flip = use_mmio_flip(ring, obj);
11431 /* When using CS flips, we want to emit semaphores between rings.
11432 * However, when using mmio flips we will create a task to do the
11433 * synchronisation, so all we want here is to pin the framebuffer
11434 * into the display plane and skip any waits.
11436 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11437 crtc->primary->state,
11438 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11440 goto cleanup_pending;
11442 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11444 work->gtt_offset += intel_crtc->dspaddr_offset;
11447 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11450 goto cleanup_unpin;
11452 i915_gem_request_assign(&work->flip_queued_req,
11453 obj->last_write_req);
11456 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11458 goto cleanup_unpin;
11461 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11464 goto cleanup_unpin;
11466 i915_gem_request_assign(&work->flip_queued_req, request);
11470 i915_add_request_no_flush(request);
11472 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11473 work->enable_stall_check = true;
11475 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11476 to_intel_plane(primary)->frontbuffer_bit);
11477 mutex_unlock(&dev->struct_mutex);
11479 intel_fbc_disable_crtc(intel_crtc);
11480 intel_frontbuffer_flip_prepare(dev,
11481 to_intel_plane(primary)->frontbuffer_bit);
11483 trace_i915_flip_request(intel_crtc->plane, obj);
11488 intel_unpin_fb_obj(fb, crtc->primary->state);
11491 i915_gem_request_cancel(request);
11492 atomic_dec(&intel_crtc->unpin_work_count);
11493 mutex_unlock(&dev->struct_mutex);
11495 crtc->primary->fb = old_fb;
11496 update_state_fb(crtc->primary);
11498 drm_gem_object_unreference_unlocked(&obj->base);
11499 drm_framebuffer_unreference(work->old_fb);
11501 spin_lock_irq(&dev->event_lock);
11502 intel_crtc->unpin_work = NULL;
11503 spin_unlock_irq(&dev->event_lock);
11505 drm_crtc_vblank_put(crtc);
11510 struct drm_atomic_state *state;
11511 struct drm_plane_state *plane_state;
11514 state = drm_atomic_state_alloc(dev);
11517 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11520 plane_state = drm_atomic_get_plane_state(state, primary);
11521 ret = PTR_ERR_OR_ZERO(plane_state);
11523 drm_atomic_set_fb_for_plane(plane_state, fb);
11525 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11527 ret = drm_atomic_commit(state);
11530 if (ret == -EDEADLK) {
11531 drm_modeset_backoff(state->acquire_ctx);
11532 drm_atomic_state_clear(state);
11537 drm_atomic_state_free(state);
11539 if (ret == 0 && event) {
11540 spin_lock_irq(&dev->event_lock);
11541 drm_send_vblank_event(dev, pipe, event);
11542 spin_unlock_irq(&dev->event_lock);
11550 * intel_wm_need_update - Check whether watermarks need updating
11551 * @plane: drm plane
11552 * @state: new plane state
11554 * Check current plane state versus the new one to determine whether
11555 * watermarks need to be recalculated.
11557 * Returns true or false.
11559 static bool intel_wm_need_update(struct drm_plane *plane,
11560 struct drm_plane_state *state)
11562 /* Update watermarks on tiling changes. */
11563 if (!plane->state->fb || !state->fb ||
11564 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11565 plane->state->rotation != state->rotation)
11568 if (plane->state->crtc_w != state->crtc_w)
11574 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11575 struct drm_plane_state *plane_state)
11577 struct drm_crtc *crtc = crtc_state->crtc;
11578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11579 struct drm_plane *plane = plane_state->plane;
11580 struct drm_device *dev = crtc->dev;
11581 struct drm_i915_private *dev_priv = dev->dev_private;
11582 struct intel_plane_state *old_plane_state =
11583 to_intel_plane_state(plane->state);
11584 int idx = intel_crtc->base.base.id, ret;
11585 int i = drm_plane_index(plane);
11586 bool mode_changed = needs_modeset(crtc_state);
11587 bool was_crtc_enabled = crtc->state->active;
11588 bool is_crtc_enabled = crtc_state->active;
11590 bool turn_off, turn_on, visible, was_visible;
11591 struct drm_framebuffer *fb = plane_state->fb;
11593 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11594 plane->type != DRM_PLANE_TYPE_CURSOR) {
11595 ret = skl_update_scaler_plane(
11596 to_intel_crtc_state(crtc_state),
11597 to_intel_plane_state(plane_state));
11603 * Disabling a plane is always okay; we just need to update
11604 * fb tracking in a special way since cleanup_fb() won't
11605 * get called by the plane helpers.
11607 if (old_plane_state->base.fb && !fb)
11608 intel_crtc->atomic.disabled_planes |= 1 << i;
11610 was_visible = old_plane_state->visible;
11611 visible = to_intel_plane_state(plane_state)->visible;
11613 if (!was_crtc_enabled && WARN_ON(was_visible))
11614 was_visible = false;
11616 if (!is_crtc_enabled && WARN_ON(visible))
11619 if (!was_visible && !visible)
11622 turn_off = was_visible && (!visible || mode_changed);
11623 turn_on = visible && (!was_visible || mode_changed);
11625 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11626 plane->base.id, fb ? fb->base.id : -1);
11628 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11629 plane->base.id, was_visible, visible,
11630 turn_off, turn_on, mode_changed);
11633 intel_crtc->atomic.update_wm_pre = true;
11634 /* must disable cxsr around plane enable/disable */
11635 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11636 intel_crtc->atomic.disable_cxsr = true;
11637 /* to potentially re-enable cxsr */
11638 intel_crtc->atomic.wait_vblank = true;
11639 intel_crtc->atomic.update_wm_post = true;
11641 } else if (turn_off) {
11642 intel_crtc->atomic.update_wm_post = true;
11643 /* must disable cxsr around plane enable/disable */
11644 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11645 if (is_crtc_enabled)
11646 intel_crtc->atomic.wait_vblank = true;
11647 intel_crtc->atomic.disable_cxsr = true;
11649 } else if (intel_wm_need_update(plane, plane_state)) {
11650 intel_crtc->atomic.update_wm_pre = true;
11653 if (visible || was_visible)
11654 intel_crtc->atomic.fb_bits |=
11655 to_intel_plane(plane)->frontbuffer_bit;
11657 switch (plane->type) {
11658 case DRM_PLANE_TYPE_PRIMARY:
11659 intel_crtc->atomic.wait_for_flips = true;
11660 intel_crtc->atomic.pre_disable_primary = turn_off;
11661 intel_crtc->atomic.post_enable_primary = turn_on;
11665 * FIXME: Actually if we will still have any other
11666 * plane enabled on the pipe we could let IPS enabled
11667 * still, but for now lets consider that when we make
11668 * primary invisible by setting DSPCNTR to 0 on
11669 * update_primary_plane function IPS needs to be
11672 intel_crtc->atomic.disable_ips = true;
11674 intel_crtc->atomic.disable_fbc = true;
11678 * FBC does not work on some platforms for rotated
11679 * planes, so disable it when rotation is not 0 and
11680 * update it when rotation is set back to 0.
11682 * FIXME: This is redundant with the fbc update done in
11683 * the primary plane enable function except that that
11684 * one is done too late. We eventually need to unify
11689 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11690 dev_priv->fbc.crtc == intel_crtc &&
11691 plane_state->rotation != BIT(DRM_ROTATE_0))
11692 intel_crtc->atomic.disable_fbc = true;
11695 * BDW signals flip done immediately if the plane
11696 * is disabled, even if the plane enable is already
11697 * armed to occur at the next vblank :(
11699 if (turn_on && IS_BROADWELL(dev))
11700 intel_crtc->atomic.wait_vblank = true;
11702 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11704 case DRM_PLANE_TYPE_CURSOR:
11706 case DRM_PLANE_TYPE_OVERLAY:
11707 if (turn_off && !mode_changed) {
11708 intel_crtc->atomic.wait_vblank = true;
11709 intel_crtc->atomic.update_sprite_watermarks |=
11716 static bool encoders_cloneable(const struct intel_encoder *a,
11717 const struct intel_encoder *b)
11719 /* masks could be asymmetric, so check both ways */
11720 return a == b || (a->cloneable & (1 << b->type) &&
11721 b->cloneable & (1 << a->type));
11724 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11725 struct intel_crtc *crtc,
11726 struct intel_encoder *encoder)
11728 struct intel_encoder *source_encoder;
11729 struct drm_connector *connector;
11730 struct drm_connector_state *connector_state;
11733 for_each_connector_in_state(state, connector, connector_state, i) {
11734 if (connector_state->crtc != &crtc->base)
11738 to_intel_encoder(connector_state->best_encoder);
11739 if (!encoders_cloneable(encoder, source_encoder))
11746 static bool check_encoder_cloning(struct drm_atomic_state *state,
11747 struct intel_crtc *crtc)
11749 struct intel_encoder *encoder;
11750 struct drm_connector *connector;
11751 struct drm_connector_state *connector_state;
11754 for_each_connector_in_state(state, connector, connector_state, i) {
11755 if (connector_state->crtc != &crtc->base)
11758 encoder = to_intel_encoder(connector_state->best_encoder);
11759 if (!check_single_encoder_cloning(state, crtc, encoder))
11766 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11767 struct drm_crtc_state *crtc_state)
11769 struct drm_device *dev = crtc->dev;
11770 struct drm_i915_private *dev_priv = dev->dev_private;
11771 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11772 struct intel_crtc_state *pipe_config =
11773 to_intel_crtc_state(crtc_state);
11774 struct drm_atomic_state *state = crtc_state->state;
11776 bool mode_changed = needs_modeset(crtc_state);
11778 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11779 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11783 if (mode_changed && !crtc_state->active)
11784 intel_crtc->atomic.update_wm_post = true;
11786 if (mode_changed && crtc_state->enable &&
11787 dev_priv->display.crtc_compute_clock &&
11788 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11789 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11796 if (INTEL_INFO(dev)->gen >= 9) {
11798 ret = skl_update_scaler_crtc(pipe_config);
11801 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11808 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11809 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11810 .load_lut = intel_crtc_load_lut,
11811 .atomic_begin = intel_begin_crtc_commit,
11812 .atomic_flush = intel_finish_crtc_commit,
11813 .atomic_check = intel_crtc_atomic_check,
11816 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11818 struct intel_connector *connector;
11820 for_each_intel_connector(dev, connector) {
11821 if (connector->base.encoder) {
11822 connector->base.state->best_encoder =
11823 connector->base.encoder;
11824 connector->base.state->crtc =
11825 connector->base.encoder->crtc;
11827 connector->base.state->best_encoder = NULL;
11828 connector->base.state->crtc = NULL;
11834 connected_sink_compute_bpp(struct intel_connector *connector,
11835 struct intel_crtc_state *pipe_config)
11837 int bpp = pipe_config->pipe_bpp;
11839 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11840 connector->base.base.id,
11841 connector->base.name);
11843 /* Don't use an invalid EDID bpc value */
11844 if (connector->base.display_info.bpc &&
11845 connector->base.display_info.bpc * 3 < bpp) {
11846 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11847 bpp, connector->base.display_info.bpc*3);
11848 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11851 /* Clamp bpp to 8 on screens without EDID 1.4 */
11852 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11853 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11855 pipe_config->pipe_bpp = 24;
11860 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11861 struct intel_crtc_state *pipe_config)
11863 struct drm_device *dev = crtc->base.dev;
11864 struct drm_atomic_state *state;
11865 struct drm_connector *connector;
11866 struct drm_connector_state *connector_state;
11869 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11871 else if (INTEL_INFO(dev)->gen >= 5)
11877 pipe_config->pipe_bpp = bpp;
11879 state = pipe_config->base.state;
11881 /* Clamp display bpp to EDID value */
11882 for_each_connector_in_state(state, connector, connector_state, i) {
11883 if (connector_state->crtc != &crtc->base)
11886 connected_sink_compute_bpp(to_intel_connector(connector),
11893 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11895 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11896 "type: 0x%x flags: 0x%x\n",
11898 mode->crtc_hdisplay, mode->crtc_hsync_start,
11899 mode->crtc_hsync_end, mode->crtc_htotal,
11900 mode->crtc_vdisplay, mode->crtc_vsync_start,
11901 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11904 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11905 struct intel_crtc_state *pipe_config,
11906 const char *context)
11908 struct drm_device *dev = crtc->base.dev;
11909 struct drm_plane *plane;
11910 struct intel_plane *intel_plane;
11911 struct intel_plane_state *state;
11912 struct drm_framebuffer *fb;
11914 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11915 context, pipe_config, pipe_name(crtc->pipe));
11917 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11918 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11919 pipe_config->pipe_bpp, pipe_config->dither);
11920 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11921 pipe_config->has_pch_encoder,
11922 pipe_config->fdi_lanes,
11923 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11924 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11925 pipe_config->fdi_m_n.tu);
11926 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11927 pipe_config->has_dp_encoder,
11928 pipe_config->lane_count,
11929 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11930 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11931 pipe_config->dp_m_n.tu);
11933 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11934 pipe_config->has_dp_encoder,
11935 pipe_config->lane_count,
11936 pipe_config->dp_m2_n2.gmch_m,
11937 pipe_config->dp_m2_n2.gmch_n,
11938 pipe_config->dp_m2_n2.link_m,
11939 pipe_config->dp_m2_n2.link_n,
11940 pipe_config->dp_m2_n2.tu);
11942 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11943 pipe_config->has_audio,
11944 pipe_config->has_infoframe);
11946 DRM_DEBUG_KMS("requested mode:\n");
11947 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11948 DRM_DEBUG_KMS("adjusted mode:\n");
11949 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11950 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11951 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11952 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11953 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11954 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11956 pipe_config->scaler_state.scaler_users,
11957 pipe_config->scaler_state.scaler_id);
11958 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11959 pipe_config->gmch_pfit.control,
11960 pipe_config->gmch_pfit.pgm_ratios,
11961 pipe_config->gmch_pfit.lvds_border_bits);
11962 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11963 pipe_config->pch_pfit.pos,
11964 pipe_config->pch_pfit.size,
11965 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11966 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11967 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11969 if (IS_BROXTON(dev)) {
11970 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11971 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11972 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11973 pipe_config->ddi_pll_sel,
11974 pipe_config->dpll_hw_state.ebb0,
11975 pipe_config->dpll_hw_state.ebb4,
11976 pipe_config->dpll_hw_state.pll0,
11977 pipe_config->dpll_hw_state.pll1,
11978 pipe_config->dpll_hw_state.pll2,
11979 pipe_config->dpll_hw_state.pll3,
11980 pipe_config->dpll_hw_state.pll6,
11981 pipe_config->dpll_hw_state.pll8,
11982 pipe_config->dpll_hw_state.pll9,
11983 pipe_config->dpll_hw_state.pll10,
11984 pipe_config->dpll_hw_state.pcsdw12);
11985 } else if (IS_SKYLAKE(dev)) {
11986 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11987 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11988 pipe_config->ddi_pll_sel,
11989 pipe_config->dpll_hw_state.ctrl1,
11990 pipe_config->dpll_hw_state.cfgcr1,
11991 pipe_config->dpll_hw_state.cfgcr2);
11992 } else if (HAS_DDI(dev)) {
11993 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11994 pipe_config->ddi_pll_sel,
11995 pipe_config->dpll_hw_state.wrpll);
11997 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11998 "fp0: 0x%x, fp1: 0x%x\n",
11999 pipe_config->dpll_hw_state.dpll,
12000 pipe_config->dpll_hw_state.dpll_md,
12001 pipe_config->dpll_hw_state.fp0,
12002 pipe_config->dpll_hw_state.fp1);
12005 DRM_DEBUG_KMS("planes on this crtc\n");
12006 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12007 intel_plane = to_intel_plane(plane);
12008 if (intel_plane->pipe != crtc->pipe)
12011 state = to_intel_plane_state(plane->state);
12012 fb = state->base.fb;
12014 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12015 "disabled, scaler_id = %d\n",
12016 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12017 plane->base.id, intel_plane->pipe,
12018 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12019 drm_plane_index(plane), state->scaler_id);
12023 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12024 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12025 plane->base.id, intel_plane->pipe,
12026 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12027 drm_plane_index(plane));
12028 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12029 fb->base.id, fb->width, fb->height, fb->pixel_format);
12030 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12032 state->src.x1 >> 16, state->src.y1 >> 16,
12033 drm_rect_width(&state->src) >> 16,
12034 drm_rect_height(&state->src) >> 16,
12035 state->dst.x1, state->dst.y1,
12036 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12040 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12042 struct drm_device *dev = state->dev;
12043 struct intel_encoder *encoder;
12044 struct drm_connector *connector;
12045 struct drm_connector_state *connector_state;
12046 unsigned int used_ports = 0;
12050 * Walk the connector list instead of the encoder
12051 * list to detect the problem on ddi platforms
12052 * where there's just one encoder per digital port.
12054 for_each_connector_in_state(state, connector, connector_state, i) {
12055 if (!connector_state->best_encoder)
12058 encoder = to_intel_encoder(connector_state->best_encoder);
12060 WARN_ON(!connector_state->crtc);
12062 switch (encoder->type) {
12063 unsigned int port_mask;
12064 case INTEL_OUTPUT_UNKNOWN:
12065 if (WARN_ON(!HAS_DDI(dev)))
12067 case INTEL_OUTPUT_DISPLAYPORT:
12068 case INTEL_OUTPUT_HDMI:
12069 case INTEL_OUTPUT_EDP:
12070 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12072 /* the same port mustn't appear more than once */
12073 if (used_ports & port_mask)
12076 used_ports |= port_mask;
12086 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12088 struct drm_crtc_state tmp_state;
12089 struct intel_crtc_scaler_state scaler_state;
12090 struct intel_dpll_hw_state dpll_hw_state;
12091 enum intel_dpll_id shared_dpll;
12092 uint32_t ddi_pll_sel;
12095 /* FIXME: before the switch to atomic started, a new pipe_config was
12096 * kzalloc'd. Code that depends on any field being zero should be
12097 * fixed, so that the crtc_state can be safely duplicated. For now,
12098 * only fields that are know to not cause problems are preserved. */
12100 tmp_state = crtc_state->base;
12101 scaler_state = crtc_state->scaler_state;
12102 shared_dpll = crtc_state->shared_dpll;
12103 dpll_hw_state = crtc_state->dpll_hw_state;
12104 ddi_pll_sel = crtc_state->ddi_pll_sel;
12105 force_thru = crtc_state->pch_pfit.force_thru;
12107 memset(crtc_state, 0, sizeof *crtc_state);
12109 crtc_state->base = tmp_state;
12110 crtc_state->scaler_state = scaler_state;
12111 crtc_state->shared_dpll = shared_dpll;
12112 crtc_state->dpll_hw_state = dpll_hw_state;
12113 crtc_state->ddi_pll_sel = ddi_pll_sel;
12114 crtc_state->pch_pfit.force_thru = force_thru;
12118 intel_modeset_pipe_config(struct drm_crtc *crtc,
12119 struct intel_crtc_state *pipe_config)
12121 struct drm_atomic_state *state = pipe_config->base.state;
12122 struct intel_encoder *encoder;
12123 struct drm_connector *connector;
12124 struct drm_connector_state *connector_state;
12125 int base_bpp, ret = -EINVAL;
12129 clear_intel_crtc_state(pipe_config);
12131 pipe_config->cpu_transcoder =
12132 (enum transcoder) to_intel_crtc(crtc)->pipe;
12135 * Sanitize sync polarity flags based on requested ones. If neither
12136 * positive or negative polarity is requested, treat this as meaning
12137 * negative polarity.
12139 if (!(pipe_config->base.adjusted_mode.flags &
12140 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12141 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12143 if (!(pipe_config->base.adjusted_mode.flags &
12144 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12145 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12147 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12153 * Determine the real pipe dimensions. Note that stereo modes can
12154 * increase the actual pipe size due to the frame doubling and
12155 * insertion of additional space for blanks between the frame. This
12156 * is stored in the crtc timings. We use the requested mode to do this
12157 * computation to clearly distinguish it from the adjusted mode, which
12158 * can be changed by the connectors in the below retry loop.
12160 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12161 &pipe_config->pipe_src_w,
12162 &pipe_config->pipe_src_h);
12165 /* Ensure the port clock defaults are reset when retrying. */
12166 pipe_config->port_clock = 0;
12167 pipe_config->pixel_multiplier = 1;
12169 /* Fill in default crtc timings, allow encoders to overwrite them. */
12170 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12171 CRTC_STEREO_DOUBLE);
12173 /* Pass our mode to the connectors and the CRTC to give them a chance to
12174 * adjust it according to limitations or connector properties, and also
12175 * a chance to reject the mode entirely.
12177 for_each_connector_in_state(state, connector, connector_state, i) {
12178 if (connector_state->crtc != crtc)
12181 encoder = to_intel_encoder(connector_state->best_encoder);
12183 if (!(encoder->compute_config(encoder, pipe_config))) {
12184 DRM_DEBUG_KMS("Encoder config failure\n");
12189 /* Set default port clock if not overwritten by the encoder. Needs to be
12190 * done afterwards in case the encoder adjusts the mode. */
12191 if (!pipe_config->port_clock)
12192 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12193 * pipe_config->pixel_multiplier;
12195 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12197 DRM_DEBUG_KMS("CRTC fixup failed\n");
12201 if (ret == RETRY) {
12202 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12207 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12209 goto encoder_retry;
12212 /* Dithering seems to not pass-through bits correctly when it should, so
12213 * only enable it on 6bpc panels. */
12214 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12215 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12216 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12223 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12225 struct drm_crtc *crtc;
12226 struct drm_crtc_state *crtc_state;
12229 /* Double check state. */
12230 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12231 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12233 /* Update hwmode for vblank functions */
12234 if (crtc->state->active)
12235 crtc->hwmode = crtc->state->adjusted_mode;
12237 crtc->hwmode.crtc_clock = 0;
12241 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12245 if (clock1 == clock2)
12248 if (!clock1 || !clock2)
12251 diff = abs(clock1 - clock2);
12253 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12259 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12260 list_for_each_entry((intel_crtc), \
12261 &(dev)->mode_config.crtc_list, \
12263 if (mask & (1 <<(intel_crtc)->pipe))
12266 intel_compare_m_n(unsigned int m, unsigned int n,
12267 unsigned int m2, unsigned int n2,
12270 if (m == m2 && n == n2)
12273 if (exact || !m || !n || !m2 || !n2)
12276 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12283 } else if (m < m2) {
12290 return m == m2 && n == n2;
12294 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12295 struct intel_link_m_n *m2_n2,
12298 if (m_n->tu == m2_n2->tu &&
12299 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12300 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12301 intel_compare_m_n(m_n->link_m, m_n->link_n,
12302 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12313 intel_pipe_config_compare(struct drm_device *dev,
12314 struct intel_crtc_state *current_config,
12315 struct intel_crtc_state *pipe_config,
12320 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12323 DRM_ERROR(fmt, ##__VA_ARGS__); \
12325 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12328 #define PIPE_CONF_CHECK_X(name) \
12329 if (current_config->name != pipe_config->name) { \
12330 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12331 "(expected 0x%08x, found 0x%08x)\n", \
12332 current_config->name, \
12333 pipe_config->name); \
12337 #define PIPE_CONF_CHECK_I(name) \
12338 if (current_config->name != pipe_config->name) { \
12339 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12340 "(expected %i, found %i)\n", \
12341 current_config->name, \
12342 pipe_config->name); \
12346 #define PIPE_CONF_CHECK_M_N(name) \
12347 if (!intel_compare_link_m_n(¤t_config->name, \
12348 &pipe_config->name,\
12350 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12351 "(expected tu %i gmch %i/%i link %i/%i, " \
12352 "found tu %i, gmch %i/%i link %i/%i)\n", \
12353 current_config->name.tu, \
12354 current_config->name.gmch_m, \
12355 current_config->name.gmch_n, \
12356 current_config->name.link_m, \
12357 current_config->name.link_n, \
12358 pipe_config->name.tu, \
12359 pipe_config->name.gmch_m, \
12360 pipe_config->name.gmch_n, \
12361 pipe_config->name.link_m, \
12362 pipe_config->name.link_n); \
12366 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12367 if (!intel_compare_link_m_n(¤t_config->name, \
12368 &pipe_config->name, adjust) && \
12369 !intel_compare_link_m_n(¤t_config->alt_name, \
12370 &pipe_config->name, adjust)) { \
12371 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12372 "(expected tu %i gmch %i/%i link %i/%i, " \
12373 "or tu %i gmch %i/%i link %i/%i, " \
12374 "found tu %i, gmch %i/%i link %i/%i)\n", \
12375 current_config->name.tu, \
12376 current_config->name.gmch_m, \
12377 current_config->name.gmch_n, \
12378 current_config->name.link_m, \
12379 current_config->name.link_n, \
12380 current_config->alt_name.tu, \
12381 current_config->alt_name.gmch_m, \
12382 current_config->alt_name.gmch_n, \
12383 current_config->alt_name.link_m, \
12384 current_config->alt_name.link_n, \
12385 pipe_config->name.tu, \
12386 pipe_config->name.gmch_m, \
12387 pipe_config->name.gmch_n, \
12388 pipe_config->name.link_m, \
12389 pipe_config->name.link_n); \
12393 /* This is required for BDW+ where there is only one set of registers for
12394 * switching between high and low RR.
12395 * This macro can be used whenever a comparison has to be made between one
12396 * hw state and multiple sw state variables.
12398 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12399 if ((current_config->name != pipe_config->name) && \
12400 (current_config->alt_name != pipe_config->name)) { \
12401 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12402 "(expected %i or %i, found %i)\n", \
12403 current_config->name, \
12404 current_config->alt_name, \
12405 pipe_config->name); \
12409 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12410 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12411 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12412 "(expected %i, found %i)\n", \
12413 current_config->name & (mask), \
12414 pipe_config->name & (mask)); \
12418 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12419 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12420 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12421 "(expected %i, found %i)\n", \
12422 current_config->name, \
12423 pipe_config->name); \
12427 #define PIPE_CONF_QUIRK(quirk) \
12428 ((current_config->quirks | pipe_config->quirks) & (quirk))
12430 PIPE_CONF_CHECK_I(cpu_transcoder);
12432 PIPE_CONF_CHECK_I(has_pch_encoder);
12433 PIPE_CONF_CHECK_I(fdi_lanes);
12434 PIPE_CONF_CHECK_M_N(fdi_m_n);
12436 PIPE_CONF_CHECK_I(has_dp_encoder);
12437 PIPE_CONF_CHECK_I(lane_count);
12439 if (INTEL_INFO(dev)->gen < 8) {
12440 PIPE_CONF_CHECK_M_N(dp_m_n);
12442 PIPE_CONF_CHECK_I(has_drrs);
12443 if (current_config->has_drrs)
12444 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12446 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12448 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12449 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12450 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12451 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12452 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12453 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12455 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12456 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12457 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12458 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12459 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12460 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12462 PIPE_CONF_CHECK_I(pixel_multiplier);
12463 PIPE_CONF_CHECK_I(has_hdmi_sink);
12464 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12465 IS_VALLEYVIEW(dev))
12466 PIPE_CONF_CHECK_I(limited_color_range);
12467 PIPE_CONF_CHECK_I(has_infoframe);
12469 PIPE_CONF_CHECK_I(has_audio);
12471 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12472 DRM_MODE_FLAG_INTERLACE);
12474 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12475 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12476 DRM_MODE_FLAG_PHSYNC);
12477 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12478 DRM_MODE_FLAG_NHSYNC);
12479 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12480 DRM_MODE_FLAG_PVSYNC);
12481 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12482 DRM_MODE_FLAG_NVSYNC);
12485 PIPE_CONF_CHECK_X(gmch_pfit.control);
12486 /* pfit ratios are autocomputed by the hw on gen4+ */
12487 if (INTEL_INFO(dev)->gen < 4)
12488 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12489 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12492 PIPE_CONF_CHECK_I(pipe_src_w);
12493 PIPE_CONF_CHECK_I(pipe_src_h);
12495 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12496 if (current_config->pch_pfit.enabled) {
12497 PIPE_CONF_CHECK_X(pch_pfit.pos);
12498 PIPE_CONF_CHECK_X(pch_pfit.size);
12501 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12504 /* BDW+ don't expose a synchronous way to read the state */
12505 if (IS_HASWELL(dev))
12506 PIPE_CONF_CHECK_I(ips_enabled);
12508 PIPE_CONF_CHECK_I(double_wide);
12510 PIPE_CONF_CHECK_X(ddi_pll_sel);
12512 PIPE_CONF_CHECK_I(shared_dpll);
12513 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12514 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12515 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12516 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12517 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12518 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12519 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12520 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12522 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12523 PIPE_CONF_CHECK_I(pipe_bpp);
12525 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12526 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12528 #undef PIPE_CONF_CHECK_X
12529 #undef PIPE_CONF_CHECK_I
12530 #undef PIPE_CONF_CHECK_I_ALT
12531 #undef PIPE_CONF_CHECK_FLAGS
12532 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12533 #undef PIPE_CONF_QUIRK
12534 #undef INTEL_ERR_OR_DBG_KMS
12539 static void check_wm_state(struct drm_device *dev)
12541 struct drm_i915_private *dev_priv = dev->dev_private;
12542 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12543 struct intel_crtc *intel_crtc;
12546 if (INTEL_INFO(dev)->gen < 9)
12549 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12550 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12552 for_each_intel_crtc(dev, intel_crtc) {
12553 struct skl_ddb_entry *hw_entry, *sw_entry;
12554 const enum pipe pipe = intel_crtc->pipe;
12556 if (!intel_crtc->active)
12560 for_each_plane(dev_priv, pipe, plane) {
12561 hw_entry = &hw_ddb.plane[pipe][plane];
12562 sw_entry = &sw_ddb->plane[pipe][plane];
12564 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12567 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12568 "(expected (%u,%u), found (%u,%u))\n",
12569 pipe_name(pipe), plane + 1,
12570 sw_entry->start, sw_entry->end,
12571 hw_entry->start, hw_entry->end);
12575 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12576 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12578 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12581 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12582 "(expected (%u,%u), found (%u,%u))\n",
12584 sw_entry->start, sw_entry->end,
12585 hw_entry->start, hw_entry->end);
12590 check_connector_state(struct drm_device *dev,
12591 struct drm_atomic_state *old_state)
12593 struct drm_connector_state *old_conn_state;
12594 struct drm_connector *connector;
12597 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12598 struct drm_encoder *encoder = connector->encoder;
12599 struct drm_connector_state *state = connector->state;
12601 /* This also checks the encoder/connector hw state with the
12602 * ->get_hw_state callbacks. */
12603 intel_connector_check_state(to_intel_connector(connector));
12605 I915_STATE_WARN(state->best_encoder != encoder,
12606 "connector's atomic encoder doesn't match legacy encoder\n");
12611 check_encoder_state(struct drm_device *dev)
12613 struct intel_encoder *encoder;
12614 struct intel_connector *connector;
12616 for_each_intel_encoder(dev, encoder) {
12617 bool enabled = false;
12620 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12621 encoder->base.base.id,
12622 encoder->base.name);
12624 for_each_intel_connector(dev, connector) {
12625 if (connector->base.state->best_encoder != &encoder->base)
12629 I915_STATE_WARN(connector->base.state->crtc !=
12630 encoder->base.crtc,
12631 "connector's crtc doesn't match encoder crtc\n");
12634 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12635 "encoder's enabled state mismatch "
12636 "(expected %i, found %i)\n",
12637 !!encoder->base.crtc, enabled);
12639 if (!encoder->base.crtc) {
12642 active = encoder->get_hw_state(encoder, &pipe);
12643 I915_STATE_WARN(active,
12644 "encoder detached but still enabled on pipe %c.\n",
12651 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12653 struct drm_i915_private *dev_priv = dev->dev_private;
12654 struct intel_encoder *encoder;
12655 struct drm_crtc_state *old_crtc_state;
12656 struct drm_crtc *crtc;
12659 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12661 struct intel_crtc_state *pipe_config, *sw_config;
12664 if (!needs_modeset(crtc->state) &&
12665 !to_intel_crtc_state(crtc->state)->update_pipe)
12668 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12669 pipe_config = to_intel_crtc_state(old_crtc_state);
12670 memset(pipe_config, 0, sizeof(*pipe_config));
12671 pipe_config->base.crtc = crtc;
12672 pipe_config->base.state = old_state;
12674 DRM_DEBUG_KMS("[CRTC:%d]\n",
12677 active = dev_priv->display.get_pipe_config(intel_crtc,
12680 /* hw state is inconsistent with the pipe quirk */
12681 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12682 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12683 active = crtc->state->active;
12685 I915_STATE_WARN(crtc->state->active != active,
12686 "crtc active state doesn't match with hw state "
12687 "(expected %i, found %i)\n", crtc->state->active, active);
12689 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12690 "transitional active state does not match atomic hw state "
12691 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12693 for_each_encoder_on_crtc(dev, crtc, encoder) {
12696 active = encoder->get_hw_state(encoder, &pipe);
12697 I915_STATE_WARN(active != crtc->state->active,
12698 "[ENCODER:%i] active %i with crtc active %i\n",
12699 encoder->base.base.id, active, crtc->state->active);
12701 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12702 "Encoder connected to wrong pipe %c\n",
12706 encoder->get_config(encoder, pipe_config);
12709 if (!crtc->state->active)
12712 sw_config = to_intel_crtc_state(crtc->state);
12713 if (!intel_pipe_config_compare(dev, sw_config,
12714 pipe_config, false)) {
12715 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12716 intel_dump_pipe_config(intel_crtc, pipe_config,
12718 intel_dump_pipe_config(intel_crtc, sw_config,
12725 check_shared_dpll_state(struct drm_device *dev)
12727 struct drm_i915_private *dev_priv = dev->dev_private;
12728 struct intel_crtc *crtc;
12729 struct intel_dpll_hw_state dpll_hw_state;
12732 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12733 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12734 int enabled_crtcs = 0, active_crtcs = 0;
12737 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12739 DRM_DEBUG_KMS("%s\n", pll->name);
12741 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12743 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12744 "more active pll users than references: %i vs %i\n",
12745 pll->active, hweight32(pll->config.crtc_mask));
12746 I915_STATE_WARN(pll->active && !pll->on,
12747 "pll in active use but not on in sw tracking\n");
12748 I915_STATE_WARN(pll->on && !pll->active,
12749 "pll in on but not on in use in sw tracking\n");
12750 I915_STATE_WARN(pll->on != active,
12751 "pll on state mismatch (expected %i, found %i)\n",
12754 for_each_intel_crtc(dev, crtc) {
12755 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12757 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12760 I915_STATE_WARN(pll->active != active_crtcs,
12761 "pll active crtcs mismatch (expected %i, found %i)\n",
12762 pll->active, active_crtcs);
12763 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12764 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12765 hweight32(pll->config.crtc_mask), enabled_crtcs);
12767 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12768 sizeof(dpll_hw_state)),
12769 "pll hw state mismatch\n");
12774 intel_modeset_check_state(struct drm_device *dev,
12775 struct drm_atomic_state *old_state)
12777 check_wm_state(dev);
12778 check_connector_state(dev, old_state);
12779 check_encoder_state(dev);
12780 check_crtc_state(dev, old_state);
12781 check_shared_dpll_state(dev);
12784 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12788 * FDI already provided one idea for the dotclock.
12789 * Yell if the encoder disagrees.
12791 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12792 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12793 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12796 static void update_scanline_offset(struct intel_crtc *crtc)
12798 struct drm_device *dev = crtc->base.dev;
12801 * The scanline counter increments at the leading edge of hsync.
12803 * On most platforms it starts counting from vtotal-1 on the
12804 * first active line. That means the scanline counter value is
12805 * always one less than what we would expect. Ie. just after
12806 * start of vblank, which also occurs at start of hsync (on the
12807 * last active line), the scanline counter will read vblank_start-1.
12809 * On gen2 the scanline counter starts counting from 1 instead
12810 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12811 * to keep the value positive), instead of adding one.
12813 * On HSW+ the behaviour of the scanline counter depends on the output
12814 * type. For DP ports it behaves like most other platforms, but on HDMI
12815 * there's an extra 1 line difference. So we need to add two instead of
12816 * one to the value.
12818 if (IS_GEN2(dev)) {
12819 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12822 vtotal = adjusted_mode->crtc_vtotal;
12823 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12826 crtc->scanline_offset = vtotal - 1;
12827 } else if (HAS_DDI(dev) &&
12828 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12829 crtc->scanline_offset = 2;
12831 crtc->scanline_offset = 1;
12834 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12836 struct drm_device *dev = state->dev;
12837 struct drm_i915_private *dev_priv = to_i915(dev);
12838 struct intel_shared_dpll_config *shared_dpll = NULL;
12839 struct intel_crtc *intel_crtc;
12840 struct intel_crtc_state *intel_crtc_state;
12841 struct drm_crtc *crtc;
12842 struct drm_crtc_state *crtc_state;
12845 if (!dev_priv->display.crtc_compute_clock)
12848 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12851 intel_crtc = to_intel_crtc(crtc);
12852 intel_crtc_state = to_intel_crtc_state(crtc_state);
12853 dpll = intel_crtc_state->shared_dpll;
12855 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12858 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12861 shared_dpll = intel_atomic_get_shared_dpll_state(state);
12863 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12868 * This implements the workaround described in the "notes" section of the mode
12869 * set sequence documentation. When going from no pipes or single pipe to
12870 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12871 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12873 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12875 struct drm_crtc_state *crtc_state;
12876 struct intel_crtc *intel_crtc;
12877 struct drm_crtc *crtc;
12878 struct intel_crtc_state *first_crtc_state = NULL;
12879 struct intel_crtc_state *other_crtc_state = NULL;
12880 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12883 /* look at all crtc's that are going to be enabled in during modeset */
12884 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12885 intel_crtc = to_intel_crtc(crtc);
12887 if (!crtc_state->active || !needs_modeset(crtc_state))
12890 if (first_crtc_state) {
12891 other_crtc_state = to_intel_crtc_state(crtc_state);
12894 first_crtc_state = to_intel_crtc_state(crtc_state);
12895 first_pipe = intel_crtc->pipe;
12899 /* No workaround needed? */
12900 if (!first_crtc_state)
12903 /* w/a possibly needed, check how many crtc's are already enabled. */
12904 for_each_intel_crtc(state->dev, intel_crtc) {
12905 struct intel_crtc_state *pipe_config;
12907 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12908 if (IS_ERR(pipe_config))
12909 return PTR_ERR(pipe_config);
12911 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12913 if (!pipe_config->base.active ||
12914 needs_modeset(&pipe_config->base))
12917 /* 2 or more enabled crtcs means no need for w/a */
12918 if (enabled_pipe != INVALID_PIPE)
12921 enabled_pipe = intel_crtc->pipe;
12924 if (enabled_pipe != INVALID_PIPE)
12925 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12926 else if (other_crtc_state)
12927 other_crtc_state->hsw_workaround_pipe = first_pipe;
12932 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12934 struct drm_crtc *crtc;
12935 struct drm_crtc_state *crtc_state;
12938 /* add all active pipes to the state */
12939 for_each_crtc(state->dev, crtc) {
12940 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12941 if (IS_ERR(crtc_state))
12942 return PTR_ERR(crtc_state);
12944 if (!crtc_state->active || needs_modeset(crtc_state))
12947 crtc_state->mode_changed = true;
12949 ret = drm_atomic_add_affected_connectors(state, crtc);
12953 ret = drm_atomic_add_affected_planes(state, crtc);
12961 static int intel_modeset_checks(struct drm_atomic_state *state)
12963 struct drm_device *dev = state->dev;
12964 struct drm_i915_private *dev_priv = dev->dev_private;
12967 if (!check_digital_port_conflicts(state)) {
12968 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12973 * See if the config requires any additional preparation, e.g.
12974 * to adjust global state with pipes off. We need to do this
12975 * here so we can get the modeset_pipe updated config for the new
12976 * mode set on this crtc. For other crtcs we need to use the
12977 * adjusted_mode bits in the crtc directly.
12979 if (dev_priv->display.modeset_calc_cdclk) {
12980 unsigned int cdclk;
12982 ret = dev_priv->display.modeset_calc_cdclk(state);
12984 cdclk = to_intel_atomic_state(state)->cdclk;
12985 if (!ret && cdclk != dev_priv->cdclk_freq)
12986 ret = intel_modeset_all_pipes(state);
12991 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
12993 intel_modeset_clear_plls(state);
12995 if (IS_HASWELL(dev))
12996 return haswell_mode_set_planes_workaround(state);
13002 * intel_atomic_check - validate state object
13004 * @state: state to validate
13006 static int intel_atomic_check(struct drm_device *dev,
13007 struct drm_atomic_state *state)
13009 struct drm_crtc *crtc;
13010 struct drm_crtc_state *crtc_state;
13012 bool any_ms = false;
13014 ret = drm_atomic_helper_check_modeset(dev, state);
13018 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13019 struct intel_crtc_state *pipe_config =
13020 to_intel_crtc_state(crtc_state);
13022 /* Catch I915_MODE_FLAG_INHERITED */
13023 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13024 crtc_state->mode_changed = true;
13026 if (!crtc_state->enable) {
13027 if (needs_modeset(crtc_state))
13032 if (!needs_modeset(crtc_state))
13035 /* FIXME: For only active_changed we shouldn't need to do any
13036 * state recomputation at all. */
13038 ret = drm_atomic_add_affected_connectors(state, crtc);
13042 ret = intel_modeset_pipe_config(crtc, pipe_config);
13046 if (intel_pipe_config_compare(state->dev,
13047 to_intel_crtc_state(crtc->state),
13048 pipe_config, true)) {
13049 crtc_state->mode_changed = false;
13050 to_intel_crtc_state(crtc_state)->update_pipe = true;
13053 if (needs_modeset(crtc_state)) {
13056 ret = drm_atomic_add_affected_planes(state, crtc);
13061 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13062 needs_modeset(crtc_state) ?
13063 "[modeset]" : "[fastset]");
13067 ret = intel_modeset_checks(state);
13072 to_intel_atomic_state(state)->cdclk =
13073 to_i915(state->dev)->cdclk_freq;
13075 return drm_atomic_helper_check_planes(state->dev, state);
13079 * intel_atomic_commit - commit validated state object
13081 * @state: the top-level driver state object
13082 * @async: asynchronous commit
13084 * This function commits a top-level state object that has been validated
13085 * with drm_atomic_helper_check().
13087 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13088 * we can only handle plane-related operations and do not yet support
13089 * asynchronous commit.
13092 * Zero for success or -errno.
13094 static int intel_atomic_commit(struct drm_device *dev,
13095 struct drm_atomic_state *state,
13098 struct drm_i915_private *dev_priv = dev->dev_private;
13099 struct drm_crtc *crtc;
13100 struct drm_crtc_state *crtc_state;
13103 bool any_ms = false;
13106 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13110 ret = drm_atomic_helper_prepare_planes(dev, state);
13114 drm_atomic_helper_swap_state(dev, state);
13116 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13119 if (!needs_modeset(crtc->state))
13123 intel_pre_plane_update(intel_crtc);
13125 if (crtc_state->active) {
13126 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13127 dev_priv->display.crtc_disable(crtc);
13128 intel_crtc->active = false;
13129 intel_disable_shared_dpll(intel_crtc);
13133 /* Only after disabling all output pipelines that will be changed can we
13134 * update the the output configuration. */
13135 intel_modeset_update_crtc_state(state);
13138 intel_shared_dpll_commit(state);
13140 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13141 modeset_update_crtc_power_domains(state);
13144 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13145 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13146 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13147 bool modeset = needs_modeset(crtc->state);
13148 bool update_pipe = !modeset &&
13149 to_intel_crtc_state(crtc->state)->update_pipe;
13150 unsigned long put_domains = 0;
13152 if (modeset && crtc->state->active) {
13153 update_scanline_offset(to_intel_crtc(crtc));
13154 dev_priv->display.crtc_enable(crtc);
13158 put_domains = modeset_get_crtc_power_domains(crtc);
13160 /* make sure intel_modeset_check_state runs */
13165 intel_pre_plane_update(intel_crtc);
13167 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13170 modeset_put_power_domains(dev_priv, put_domains);
13172 intel_post_plane_update(intel_crtc);
13175 /* FIXME: add subpixel order */
13177 drm_atomic_helper_wait_for_vblanks(dev, state);
13178 drm_atomic_helper_cleanup_planes(dev, state);
13181 intel_modeset_check_state(dev, state);
13183 drm_atomic_state_free(state);
13188 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13190 struct drm_device *dev = crtc->dev;
13191 struct drm_atomic_state *state;
13192 struct drm_crtc_state *crtc_state;
13195 state = drm_atomic_state_alloc(dev);
13197 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13202 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13205 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13206 ret = PTR_ERR_OR_ZERO(crtc_state);
13208 if (!crtc_state->active)
13211 crtc_state->mode_changed = true;
13212 ret = drm_atomic_commit(state);
13215 if (ret == -EDEADLK) {
13216 drm_atomic_state_clear(state);
13217 drm_modeset_backoff(state->acquire_ctx);
13223 drm_atomic_state_free(state);
13226 #undef for_each_intel_crtc_masked
13228 static const struct drm_crtc_funcs intel_crtc_funcs = {
13229 .gamma_set = intel_crtc_gamma_set,
13230 .set_config = drm_atomic_helper_set_config,
13231 .destroy = intel_crtc_destroy,
13232 .page_flip = intel_crtc_page_flip,
13233 .atomic_duplicate_state = intel_crtc_duplicate_state,
13234 .atomic_destroy_state = intel_crtc_destroy_state,
13237 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13238 struct intel_shared_dpll *pll,
13239 struct intel_dpll_hw_state *hw_state)
13243 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13246 val = I915_READ(PCH_DPLL(pll->id));
13247 hw_state->dpll = val;
13248 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13249 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13251 return val & DPLL_VCO_ENABLE;
13254 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13255 struct intel_shared_dpll *pll)
13257 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13258 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13261 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13262 struct intel_shared_dpll *pll)
13264 /* PCH refclock must be enabled first */
13265 ibx_assert_pch_refclk_enabled(dev_priv);
13267 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13269 /* Wait for the clocks to stabilize. */
13270 POSTING_READ(PCH_DPLL(pll->id));
13273 /* The pixel multiplier can only be updated once the
13274 * DPLL is enabled and the clocks are stable.
13276 * So write it again.
13278 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13279 POSTING_READ(PCH_DPLL(pll->id));
13283 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13284 struct intel_shared_dpll *pll)
13286 struct drm_device *dev = dev_priv->dev;
13287 struct intel_crtc *crtc;
13289 /* Make sure no transcoder isn't still depending on us. */
13290 for_each_intel_crtc(dev, crtc) {
13291 if (intel_crtc_to_shared_dpll(crtc) == pll)
13292 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13295 I915_WRITE(PCH_DPLL(pll->id), 0);
13296 POSTING_READ(PCH_DPLL(pll->id));
13300 static char *ibx_pch_dpll_names[] = {
13305 static void ibx_pch_dpll_init(struct drm_device *dev)
13307 struct drm_i915_private *dev_priv = dev->dev_private;
13310 dev_priv->num_shared_dpll = 2;
13312 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13313 dev_priv->shared_dplls[i].id = i;
13314 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13315 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13316 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13317 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13318 dev_priv->shared_dplls[i].get_hw_state =
13319 ibx_pch_dpll_get_hw_state;
13323 static void intel_shared_dpll_init(struct drm_device *dev)
13325 struct drm_i915_private *dev_priv = dev->dev_private;
13328 intel_ddi_pll_init(dev);
13329 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13330 ibx_pch_dpll_init(dev);
13332 dev_priv->num_shared_dpll = 0;
13334 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13338 * intel_prepare_plane_fb - Prepare fb for usage on plane
13339 * @plane: drm plane to prepare for
13340 * @fb: framebuffer to prepare for presentation
13342 * Prepares a framebuffer for usage on a display plane. Generally this
13343 * involves pinning the underlying object and updating the frontbuffer tracking
13344 * bits. Some older platforms need special physical address handling for
13347 * Returns 0 on success, negative error code on failure.
13350 intel_prepare_plane_fb(struct drm_plane *plane,
13351 const struct drm_plane_state *new_state)
13353 struct drm_device *dev = plane->dev;
13354 struct drm_framebuffer *fb = new_state->fb;
13355 struct intel_plane *intel_plane = to_intel_plane(plane);
13356 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13357 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13363 mutex_lock(&dev->struct_mutex);
13365 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13366 INTEL_INFO(dev)->cursor_needs_physical) {
13367 int align = IS_I830(dev) ? 16 * 1024 : 256;
13368 ret = i915_gem_object_attach_phys(obj, align);
13370 DRM_DEBUG_KMS("failed to attach phys object\n");
13372 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13376 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13378 mutex_unlock(&dev->struct_mutex);
13384 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13385 * @plane: drm plane to clean up for
13386 * @fb: old framebuffer that was on plane
13388 * Cleans up a framebuffer that has just been removed from a plane.
13391 intel_cleanup_plane_fb(struct drm_plane *plane,
13392 const struct drm_plane_state *old_state)
13394 struct drm_device *dev = plane->dev;
13395 struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb);
13400 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13401 !INTEL_INFO(dev)->cursor_needs_physical) {
13402 mutex_lock(&dev->struct_mutex);
13403 intel_unpin_fb_obj(old_state->fb, old_state);
13404 mutex_unlock(&dev->struct_mutex);
13409 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13412 struct drm_device *dev;
13413 struct drm_i915_private *dev_priv;
13414 int crtc_clock, cdclk;
13416 if (!intel_crtc || !crtc_state)
13417 return DRM_PLANE_HELPER_NO_SCALING;
13419 dev = intel_crtc->base.dev;
13420 dev_priv = dev->dev_private;
13421 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13422 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13424 if (!crtc_clock || !cdclk)
13425 return DRM_PLANE_HELPER_NO_SCALING;
13428 * skl max scale is lower of:
13429 * close to 3 but not 3, -1 is for that purpose
13433 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13439 intel_check_primary_plane(struct drm_plane *plane,
13440 struct intel_crtc_state *crtc_state,
13441 struct intel_plane_state *state)
13443 struct drm_crtc *crtc = state->base.crtc;
13444 struct drm_framebuffer *fb = state->base.fb;
13445 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13446 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13447 bool can_position = false;
13449 /* use scaler when colorkey is not required */
13450 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13451 state->ckey.flags == I915_SET_COLORKEY_NONE) {
13453 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13454 can_position = true;
13457 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13458 &state->dst, &state->clip,
13459 min_scale, max_scale,
13460 can_position, true,
13465 intel_commit_primary_plane(struct drm_plane *plane,
13466 struct intel_plane_state *state)
13468 struct drm_crtc *crtc = state->base.crtc;
13469 struct drm_framebuffer *fb = state->base.fb;
13470 struct drm_device *dev = plane->dev;
13471 struct drm_i915_private *dev_priv = dev->dev_private;
13472 struct intel_crtc *intel_crtc;
13473 struct drm_rect *src = &state->src;
13475 crtc = crtc ? crtc : plane->crtc;
13476 intel_crtc = to_intel_crtc(crtc);
13479 crtc->x = src->x1 >> 16;
13480 crtc->y = src->y1 >> 16;
13482 if (!crtc->state->active)
13485 dev_priv->display.update_primary_plane(crtc, fb,
13486 state->src.x1 >> 16,
13487 state->src.y1 >> 16);
13491 intel_disable_primary_plane(struct drm_plane *plane,
13492 struct drm_crtc *crtc)
13494 struct drm_device *dev = plane->dev;
13495 struct drm_i915_private *dev_priv = dev->dev_private;
13497 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13500 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13501 struct drm_crtc_state *old_crtc_state)
13503 struct drm_device *dev = crtc->dev;
13504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13505 struct intel_crtc_state *old_intel_state =
13506 to_intel_crtc_state(old_crtc_state);
13507 bool modeset = needs_modeset(crtc->state);
13509 if (intel_crtc->atomic.update_wm_pre)
13510 intel_update_watermarks(crtc);
13512 /* Perform vblank evasion around commit operation */
13513 if (crtc->state->active)
13514 intel_pipe_update_start(intel_crtc);
13519 if (to_intel_crtc_state(crtc->state)->update_pipe)
13520 intel_update_pipe_config(intel_crtc, old_intel_state);
13521 else if (INTEL_INFO(dev)->gen >= 9)
13522 skl_detach_scalers(intel_crtc);
13525 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13526 struct drm_crtc_state *old_crtc_state)
13528 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13530 if (crtc->state->active)
13531 intel_pipe_update_end(intel_crtc);
13535 * intel_plane_destroy - destroy a plane
13536 * @plane: plane to destroy
13538 * Common destruction function for all types of planes (primary, cursor,
13541 void intel_plane_destroy(struct drm_plane *plane)
13543 struct intel_plane *intel_plane = to_intel_plane(plane);
13544 drm_plane_cleanup(plane);
13545 kfree(intel_plane);
13548 const struct drm_plane_funcs intel_plane_funcs = {
13549 .update_plane = drm_atomic_helper_update_plane,
13550 .disable_plane = drm_atomic_helper_disable_plane,
13551 .destroy = intel_plane_destroy,
13552 .set_property = drm_atomic_helper_plane_set_property,
13553 .atomic_get_property = intel_plane_atomic_get_property,
13554 .atomic_set_property = intel_plane_atomic_set_property,
13555 .atomic_duplicate_state = intel_plane_duplicate_state,
13556 .atomic_destroy_state = intel_plane_destroy_state,
13560 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13563 struct intel_plane *primary;
13564 struct intel_plane_state *state;
13565 const uint32_t *intel_primary_formats;
13566 unsigned int num_formats;
13568 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13569 if (primary == NULL)
13572 state = intel_create_plane_state(&primary->base);
13577 primary->base.state = &state->base;
13579 primary->can_scale = false;
13580 primary->max_downscale = 1;
13581 if (INTEL_INFO(dev)->gen >= 9) {
13582 primary->can_scale = true;
13583 state->scaler_id = -1;
13585 primary->pipe = pipe;
13586 primary->plane = pipe;
13587 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13588 primary->check_plane = intel_check_primary_plane;
13589 primary->commit_plane = intel_commit_primary_plane;
13590 primary->disable_plane = intel_disable_primary_plane;
13591 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13592 primary->plane = !pipe;
13594 if (INTEL_INFO(dev)->gen >= 9) {
13595 intel_primary_formats = skl_primary_formats;
13596 num_formats = ARRAY_SIZE(skl_primary_formats);
13597 } else if (INTEL_INFO(dev)->gen >= 4) {
13598 intel_primary_formats = i965_primary_formats;
13599 num_formats = ARRAY_SIZE(i965_primary_formats);
13601 intel_primary_formats = i8xx_primary_formats;
13602 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13605 drm_universal_plane_init(dev, &primary->base, 0,
13606 &intel_plane_funcs,
13607 intel_primary_formats, num_formats,
13608 DRM_PLANE_TYPE_PRIMARY);
13610 if (INTEL_INFO(dev)->gen >= 4)
13611 intel_create_rotation_property(dev, primary);
13613 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13615 return &primary->base;
13618 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13620 if (!dev->mode_config.rotation_property) {
13621 unsigned long flags = BIT(DRM_ROTATE_0) |
13622 BIT(DRM_ROTATE_180);
13624 if (INTEL_INFO(dev)->gen >= 9)
13625 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13627 dev->mode_config.rotation_property =
13628 drm_mode_create_rotation_property(dev, flags);
13630 if (dev->mode_config.rotation_property)
13631 drm_object_attach_property(&plane->base.base,
13632 dev->mode_config.rotation_property,
13633 plane->base.state->rotation);
13637 intel_check_cursor_plane(struct drm_plane *plane,
13638 struct intel_crtc_state *crtc_state,
13639 struct intel_plane_state *state)
13641 struct drm_crtc *crtc = crtc_state->base.crtc;
13642 struct drm_framebuffer *fb = state->base.fb;
13643 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13647 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13648 &state->dst, &state->clip,
13649 DRM_PLANE_HELPER_NO_SCALING,
13650 DRM_PLANE_HELPER_NO_SCALING,
13651 true, true, &state->visible);
13655 /* if we want to turn off the cursor ignore width and height */
13659 /* Check for which cursor types we support */
13660 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13661 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13662 state->base.crtc_w, state->base.crtc_h);
13666 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13667 if (obj->base.size < stride * state->base.crtc_h) {
13668 DRM_DEBUG_KMS("buffer is too small\n");
13672 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13673 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13681 intel_disable_cursor_plane(struct drm_plane *plane,
13682 struct drm_crtc *crtc)
13684 intel_crtc_update_cursor(crtc, false);
13688 intel_commit_cursor_plane(struct drm_plane *plane,
13689 struct intel_plane_state *state)
13691 struct drm_crtc *crtc = state->base.crtc;
13692 struct drm_device *dev = plane->dev;
13693 struct intel_crtc *intel_crtc;
13694 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13697 crtc = crtc ? crtc : plane->crtc;
13698 intel_crtc = to_intel_crtc(crtc);
13700 if (intel_crtc->cursor_bo == obj)
13705 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13706 addr = i915_gem_obj_ggtt_offset(obj);
13708 addr = obj->phys_handle->busaddr;
13710 intel_crtc->cursor_addr = addr;
13711 intel_crtc->cursor_bo = obj;
13714 if (crtc->state->active)
13715 intel_crtc_update_cursor(crtc, state->visible);
13718 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13721 struct intel_plane *cursor;
13722 struct intel_plane_state *state;
13724 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13725 if (cursor == NULL)
13728 state = intel_create_plane_state(&cursor->base);
13733 cursor->base.state = &state->base;
13735 cursor->can_scale = false;
13736 cursor->max_downscale = 1;
13737 cursor->pipe = pipe;
13738 cursor->plane = pipe;
13739 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13740 cursor->check_plane = intel_check_cursor_plane;
13741 cursor->commit_plane = intel_commit_cursor_plane;
13742 cursor->disable_plane = intel_disable_cursor_plane;
13744 drm_universal_plane_init(dev, &cursor->base, 0,
13745 &intel_plane_funcs,
13746 intel_cursor_formats,
13747 ARRAY_SIZE(intel_cursor_formats),
13748 DRM_PLANE_TYPE_CURSOR);
13750 if (INTEL_INFO(dev)->gen >= 4) {
13751 if (!dev->mode_config.rotation_property)
13752 dev->mode_config.rotation_property =
13753 drm_mode_create_rotation_property(dev,
13754 BIT(DRM_ROTATE_0) |
13755 BIT(DRM_ROTATE_180));
13756 if (dev->mode_config.rotation_property)
13757 drm_object_attach_property(&cursor->base.base,
13758 dev->mode_config.rotation_property,
13759 state->base.rotation);
13762 if (INTEL_INFO(dev)->gen >=9)
13763 state->scaler_id = -1;
13765 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13767 return &cursor->base;
13770 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13771 struct intel_crtc_state *crtc_state)
13774 struct intel_scaler *intel_scaler;
13775 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13777 for (i = 0; i < intel_crtc->num_scalers; i++) {
13778 intel_scaler = &scaler_state->scalers[i];
13779 intel_scaler->in_use = 0;
13780 intel_scaler->mode = PS_SCALER_MODE_DYN;
13783 scaler_state->scaler_id = -1;
13786 static void intel_crtc_init(struct drm_device *dev, int pipe)
13788 struct drm_i915_private *dev_priv = dev->dev_private;
13789 struct intel_crtc *intel_crtc;
13790 struct intel_crtc_state *crtc_state = NULL;
13791 struct drm_plane *primary = NULL;
13792 struct drm_plane *cursor = NULL;
13795 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13796 if (intel_crtc == NULL)
13799 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13802 intel_crtc->config = crtc_state;
13803 intel_crtc->base.state = &crtc_state->base;
13804 crtc_state->base.crtc = &intel_crtc->base;
13806 /* initialize shared scalers */
13807 if (INTEL_INFO(dev)->gen >= 9) {
13808 if (pipe == PIPE_C)
13809 intel_crtc->num_scalers = 1;
13811 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13813 skl_init_scalers(dev, intel_crtc, crtc_state);
13816 primary = intel_primary_plane_create(dev, pipe);
13820 cursor = intel_cursor_plane_create(dev, pipe);
13824 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13825 cursor, &intel_crtc_funcs);
13829 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13830 for (i = 0; i < 256; i++) {
13831 intel_crtc->lut_r[i] = i;
13832 intel_crtc->lut_g[i] = i;
13833 intel_crtc->lut_b[i] = i;
13837 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13838 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13840 intel_crtc->pipe = pipe;
13841 intel_crtc->plane = pipe;
13842 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13843 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13844 intel_crtc->plane = !pipe;
13847 intel_crtc->cursor_base = ~0;
13848 intel_crtc->cursor_cntl = ~0;
13849 intel_crtc->cursor_size = ~0;
13851 intel_crtc->wm.cxsr_allowed = true;
13853 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13854 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13855 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13856 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13858 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13860 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13865 drm_plane_cleanup(primary);
13867 drm_plane_cleanup(cursor);
13872 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13874 struct drm_encoder *encoder = connector->base.encoder;
13875 struct drm_device *dev = connector->base.dev;
13877 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13879 if (!encoder || WARN_ON(!encoder->crtc))
13880 return INVALID_PIPE;
13882 return to_intel_crtc(encoder->crtc)->pipe;
13885 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13886 struct drm_file *file)
13888 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13889 struct drm_crtc *drmmode_crtc;
13890 struct intel_crtc *crtc;
13892 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13894 if (!drmmode_crtc) {
13895 DRM_ERROR("no such CRTC id\n");
13899 crtc = to_intel_crtc(drmmode_crtc);
13900 pipe_from_crtc_id->pipe = crtc->pipe;
13905 static int intel_encoder_clones(struct intel_encoder *encoder)
13907 struct drm_device *dev = encoder->base.dev;
13908 struct intel_encoder *source_encoder;
13909 int index_mask = 0;
13912 for_each_intel_encoder(dev, source_encoder) {
13913 if (encoders_cloneable(encoder, source_encoder))
13914 index_mask |= (1 << entry);
13922 static bool has_edp_a(struct drm_device *dev)
13924 struct drm_i915_private *dev_priv = dev->dev_private;
13926 if (!IS_MOBILE(dev))
13929 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13932 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13938 static bool intel_crt_present(struct drm_device *dev)
13940 struct drm_i915_private *dev_priv = dev->dev_private;
13942 if (INTEL_INFO(dev)->gen >= 9)
13945 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13948 if (IS_CHERRYVIEW(dev))
13951 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13957 static void intel_setup_outputs(struct drm_device *dev)
13959 struct drm_i915_private *dev_priv = dev->dev_private;
13960 struct intel_encoder *encoder;
13961 bool dpd_is_edp = false;
13963 intel_lvds_init(dev);
13965 if (intel_crt_present(dev))
13966 intel_crt_init(dev);
13968 if (IS_BROXTON(dev)) {
13970 * FIXME: Broxton doesn't support port detection via the
13971 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13972 * detect the ports.
13974 intel_ddi_init(dev, PORT_A);
13975 intel_ddi_init(dev, PORT_B);
13976 intel_ddi_init(dev, PORT_C);
13977 } else if (HAS_DDI(dev)) {
13981 * Haswell uses DDI functions to detect digital outputs.
13982 * On SKL pre-D0 the strap isn't connected, so we assume
13985 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13986 /* WaIgnoreDDIAStrap: skl */
13987 if (found || IS_SKYLAKE(dev))
13988 intel_ddi_init(dev, PORT_A);
13990 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13992 found = I915_READ(SFUSE_STRAP);
13994 if (found & SFUSE_STRAP_DDIB_DETECTED)
13995 intel_ddi_init(dev, PORT_B);
13996 if (found & SFUSE_STRAP_DDIC_DETECTED)
13997 intel_ddi_init(dev, PORT_C);
13998 if (found & SFUSE_STRAP_DDID_DETECTED)
13999 intel_ddi_init(dev, PORT_D);
14001 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14003 if (IS_SKYLAKE(dev) &&
14004 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14005 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14006 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14007 intel_ddi_init(dev, PORT_E);
14009 } else if (HAS_PCH_SPLIT(dev)) {
14011 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14013 if (has_edp_a(dev))
14014 intel_dp_init(dev, DP_A, PORT_A);
14016 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14017 /* PCH SDVOB multiplex with HDMIB */
14018 found = intel_sdvo_init(dev, PCH_SDVOB, true);
14020 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14021 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14022 intel_dp_init(dev, PCH_DP_B, PORT_B);
14025 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14026 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14028 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14029 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14031 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14032 intel_dp_init(dev, PCH_DP_C, PORT_C);
14034 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14035 intel_dp_init(dev, PCH_DP_D, PORT_D);
14036 } else if (IS_VALLEYVIEW(dev)) {
14038 * The DP_DETECTED bit is the latched state of the DDC
14039 * SDA pin at boot. However since eDP doesn't require DDC
14040 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14041 * eDP ports may have been muxed to an alternate function.
14042 * Thus we can't rely on the DP_DETECTED bit alone to detect
14043 * eDP ports. Consult the VBT as well as DP_DETECTED to
14044 * detect eDP ports.
14046 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14047 !intel_dp_is_edp(dev, PORT_B))
14048 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14049 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14050 intel_dp_is_edp(dev, PORT_B))
14051 intel_dp_init(dev, VLV_DP_B, PORT_B);
14053 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14054 !intel_dp_is_edp(dev, PORT_C))
14055 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14056 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14057 intel_dp_is_edp(dev, PORT_C))
14058 intel_dp_init(dev, VLV_DP_C, PORT_C);
14060 if (IS_CHERRYVIEW(dev)) {
14061 /* eDP not supported on port D, so don't check VBT */
14062 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14063 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14064 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14065 intel_dp_init(dev, CHV_DP_D, PORT_D);
14068 intel_dsi_init(dev);
14069 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14070 bool found = false;
14072 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14073 DRM_DEBUG_KMS("probing SDVOB\n");
14074 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14075 if (!found && IS_G4X(dev)) {
14076 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14077 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14080 if (!found && IS_G4X(dev))
14081 intel_dp_init(dev, DP_B, PORT_B);
14084 /* Before G4X SDVOC doesn't have its own detect register */
14086 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14087 DRM_DEBUG_KMS("probing SDVOC\n");
14088 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14091 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14094 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14095 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14098 intel_dp_init(dev, DP_C, PORT_C);
14102 (I915_READ(DP_D) & DP_DETECTED))
14103 intel_dp_init(dev, DP_D, PORT_D);
14104 } else if (IS_GEN2(dev))
14105 intel_dvo_init(dev);
14107 if (SUPPORTS_TV(dev))
14108 intel_tv_init(dev);
14110 intel_psr_init(dev);
14112 for_each_intel_encoder(dev, encoder) {
14113 encoder->base.possible_crtcs = encoder->crtc_mask;
14114 encoder->base.possible_clones =
14115 intel_encoder_clones(encoder);
14118 intel_init_pch_refclk(dev);
14120 drm_helper_move_panel_connectors_to_head(dev);
14123 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14125 struct drm_device *dev = fb->dev;
14126 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14128 drm_framebuffer_cleanup(fb);
14129 mutex_lock(&dev->struct_mutex);
14130 WARN_ON(!intel_fb->obj->framebuffer_references--);
14131 drm_gem_object_unreference(&intel_fb->obj->base);
14132 mutex_unlock(&dev->struct_mutex);
14136 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14137 struct drm_file *file,
14138 unsigned int *handle)
14140 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14141 struct drm_i915_gem_object *obj = intel_fb->obj;
14143 return drm_gem_handle_create(file, &obj->base, handle);
14146 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14147 struct drm_file *file,
14148 unsigned flags, unsigned color,
14149 struct drm_clip_rect *clips,
14150 unsigned num_clips)
14152 struct drm_device *dev = fb->dev;
14153 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14154 struct drm_i915_gem_object *obj = intel_fb->obj;
14156 mutex_lock(&dev->struct_mutex);
14157 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14158 mutex_unlock(&dev->struct_mutex);
14163 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14164 .destroy = intel_user_framebuffer_destroy,
14165 .create_handle = intel_user_framebuffer_create_handle,
14166 .dirty = intel_user_framebuffer_dirty,
14170 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14171 uint32_t pixel_format)
14173 u32 gen = INTEL_INFO(dev)->gen;
14176 /* "The stride in bytes must not exceed the of the size of 8K
14177 * pixels and 32K bytes."
14179 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14180 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14182 } else if (gen >= 4) {
14183 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14187 } else if (gen >= 3) {
14188 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14193 /* XXX DSPC is limited to 4k tiled */
14198 static int intel_framebuffer_init(struct drm_device *dev,
14199 struct intel_framebuffer *intel_fb,
14200 struct drm_mode_fb_cmd2 *mode_cmd,
14201 struct drm_i915_gem_object *obj)
14203 unsigned int aligned_height;
14205 u32 pitch_limit, stride_alignment;
14207 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14209 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14210 /* Enforce that fb modifier and tiling mode match, but only for
14211 * X-tiled. This is needed for FBC. */
14212 if (!!(obj->tiling_mode == I915_TILING_X) !=
14213 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14214 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14218 if (obj->tiling_mode == I915_TILING_X)
14219 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14220 else if (obj->tiling_mode == I915_TILING_Y) {
14221 DRM_DEBUG("No Y tiling for legacy addfb\n");
14226 /* Passed in modifier sanity checking. */
14227 switch (mode_cmd->modifier[0]) {
14228 case I915_FORMAT_MOD_Y_TILED:
14229 case I915_FORMAT_MOD_Yf_TILED:
14230 if (INTEL_INFO(dev)->gen < 9) {
14231 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14232 mode_cmd->modifier[0]);
14235 case DRM_FORMAT_MOD_NONE:
14236 case I915_FORMAT_MOD_X_TILED:
14239 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14240 mode_cmd->modifier[0]);
14244 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14245 mode_cmd->pixel_format);
14246 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14247 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14248 mode_cmd->pitches[0], stride_alignment);
14252 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14253 mode_cmd->pixel_format);
14254 if (mode_cmd->pitches[0] > pitch_limit) {
14255 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14256 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14257 "tiled" : "linear",
14258 mode_cmd->pitches[0], pitch_limit);
14262 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14263 mode_cmd->pitches[0] != obj->stride) {
14264 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14265 mode_cmd->pitches[0], obj->stride);
14269 /* Reject formats not supported by any plane early. */
14270 switch (mode_cmd->pixel_format) {
14271 case DRM_FORMAT_C8:
14272 case DRM_FORMAT_RGB565:
14273 case DRM_FORMAT_XRGB8888:
14274 case DRM_FORMAT_ARGB8888:
14276 case DRM_FORMAT_XRGB1555:
14277 if (INTEL_INFO(dev)->gen > 3) {
14278 DRM_DEBUG("unsupported pixel format: %s\n",
14279 drm_get_format_name(mode_cmd->pixel_format));
14283 case DRM_FORMAT_ABGR8888:
14284 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14285 DRM_DEBUG("unsupported pixel format: %s\n",
14286 drm_get_format_name(mode_cmd->pixel_format));
14290 case DRM_FORMAT_XBGR8888:
14291 case DRM_FORMAT_XRGB2101010:
14292 case DRM_FORMAT_XBGR2101010:
14293 if (INTEL_INFO(dev)->gen < 4) {
14294 DRM_DEBUG("unsupported pixel format: %s\n",
14295 drm_get_format_name(mode_cmd->pixel_format));
14299 case DRM_FORMAT_ABGR2101010:
14300 if (!IS_VALLEYVIEW(dev)) {
14301 DRM_DEBUG("unsupported pixel format: %s\n",
14302 drm_get_format_name(mode_cmd->pixel_format));
14306 case DRM_FORMAT_YUYV:
14307 case DRM_FORMAT_UYVY:
14308 case DRM_FORMAT_YVYU:
14309 case DRM_FORMAT_VYUY:
14310 if (INTEL_INFO(dev)->gen < 5) {
14311 DRM_DEBUG("unsupported pixel format: %s\n",
14312 drm_get_format_name(mode_cmd->pixel_format));
14317 DRM_DEBUG("unsupported pixel format: %s\n",
14318 drm_get_format_name(mode_cmd->pixel_format));
14322 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14323 if (mode_cmd->offsets[0] != 0)
14326 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14327 mode_cmd->pixel_format,
14328 mode_cmd->modifier[0]);
14329 /* FIXME drm helper for size checks (especially planar formats)? */
14330 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14333 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14334 intel_fb->obj = obj;
14335 intel_fb->obj->framebuffer_references++;
14337 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14339 DRM_ERROR("framebuffer init failed %d\n", ret);
14346 static struct drm_framebuffer *
14347 intel_user_framebuffer_create(struct drm_device *dev,
14348 struct drm_file *filp,
14349 struct drm_mode_fb_cmd2 *mode_cmd)
14351 struct drm_i915_gem_object *obj;
14353 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14354 mode_cmd->handles[0]));
14355 if (&obj->base == NULL)
14356 return ERR_PTR(-ENOENT);
14358 return intel_framebuffer_create(dev, mode_cmd, obj);
14361 #ifndef CONFIG_DRM_FBDEV_EMULATION
14362 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14367 static const struct drm_mode_config_funcs intel_mode_funcs = {
14368 .fb_create = intel_user_framebuffer_create,
14369 .output_poll_changed = intel_fbdev_output_poll_changed,
14370 .atomic_check = intel_atomic_check,
14371 .atomic_commit = intel_atomic_commit,
14372 .atomic_state_alloc = intel_atomic_state_alloc,
14373 .atomic_state_clear = intel_atomic_state_clear,
14376 /* Set up chip specific display functions */
14377 static void intel_init_display(struct drm_device *dev)
14379 struct drm_i915_private *dev_priv = dev->dev_private;
14381 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14382 dev_priv->display.find_dpll = g4x_find_best_dpll;
14383 else if (IS_CHERRYVIEW(dev))
14384 dev_priv->display.find_dpll = chv_find_best_dpll;
14385 else if (IS_VALLEYVIEW(dev))
14386 dev_priv->display.find_dpll = vlv_find_best_dpll;
14387 else if (IS_PINEVIEW(dev))
14388 dev_priv->display.find_dpll = pnv_find_best_dpll;
14390 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14392 if (INTEL_INFO(dev)->gen >= 9) {
14393 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14394 dev_priv->display.get_initial_plane_config =
14395 skylake_get_initial_plane_config;
14396 dev_priv->display.crtc_compute_clock =
14397 haswell_crtc_compute_clock;
14398 dev_priv->display.crtc_enable = haswell_crtc_enable;
14399 dev_priv->display.crtc_disable = haswell_crtc_disable;
14400 dev_priv->display.update_primary_plane =
14401 skylake_update_primary_plane;
14402 } else if (HAS_DDI(dev)) {
14403 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14404 dev_priv->display.get_initial_plane_config =
14405 ironlake_get_initial_plane_config;
14406 dev_priv->display.crtc_compute_clock =
14407 haswell_crtc_compute_clock;
14408 dev_priv->display.crtc_enable = haswell_crtc_enable;
14409 dev_priv->display.crtc_disable = haswell_crtc_disable;
14410 dev_priv->display.update_primary_plane =
14411 ironlake_update_primary_plane;
14412 } else if (HAS_PCH_SPLIT(dev)) {
14413 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14414 dev_priv->display.get_initial_plane_config =
14415 ironlake_get_initial_plane_config;
14416 dev_priv->display.crtc_compute_clock =
14417 ironlake_crtc_compute_clock;
14418 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14419 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14420 dev_priv->display.update_primary_plane =
14421 ironlake_update_primary_plane;
14422 } else if (IS_VALLEYVIEW(dev)) {
14423 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14424 dev_priv->display.get_initial_plane_config =
14425 i9xx_get_initial_plane_config;
14426 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14427 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14428 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14429 dev_priv->display.update_primary_plane =
14430 i9xx_update_primary_plane;
14432 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14433 dev_priv->display.get_initial_plane_config =
14434 i9xx_get_initial_plane_config;
14435 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14436 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14437 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14438 dev_priv->display.update_primary_plane =
14439 i9xx_update_primary_plane;
14442 /* Returns the core display clock speed */
14443 if (IS_SKYLAKE(dev))
14444 dev_priv->display.get_display_clock_speed =
14445 skylake_get_display_clock_speed;
14446 else if (IS_BROXTON(dev))
14447 dev_priv->display.get_display_clock_speed =
14448 broxton_get_display_clock_speed;
14449 else if (IS_BROADWELL(dev))
14450 dev_priv->display.get_display_clock_speed =
14451 broadwell_get_display_clock_speed;
14452 else if (IS_HASWELL(dev))
14453 dev_priv->display.get_display_clock_speed =
14454 haswell_get_display_clock_speed;
14455 else if (IS_VALLEYVIEW(dev))
14456 dev_priv->display.get_display_clock_speed =
14457 valleyview_get_display_clock_speed;
14458 else if (IS_GEN5(dev))
14459 dev_priv->display.get_display_clock_speed =
14460 ilk_get_display_clock_speed;
14461 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14462 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14463 dev_priv->display.get_display_clock_speed =
14464 i945_get_display_clock_speed;
14465 else if (IS_GM45(dev))
14466 dev_priv->display.get_display_clock_speed =
14467 gm45_get_display_clock_speed;
14468 else if (IS_CRESTLINE(dev))
14469 dev_priv->display.get_display_clock_speed =
14470 i965gm_get_display_clock_speed;
14471 else if (IS_PINEVIEW(dev))
14472 dev_priv->display.get_display_clock_speed =
14473 pnv_get_display_clock_speed;
14474 else if (IS_G33(dev) || IS_G4X(dev))
14475 dev_priv->display.get_display_clock_speed =
14476 g33_get_display_clock_speed;
14477 else if (IS_I915G(dev))
14478 dev_priv->display.get_display_clock_speed =
14479 i915_get_display_clock_speed;
14480 else if (IS_I945GM(dev) || IS_845G(dev))
14481 dev_priv->display.get_display_clock_speed =
14482 i9xx_misc_get_display_clock_speed;
14483 else if (IS_PINEVIEW(dev))
14484 dev_priv->display.get_display_clock_speed =
14485 pnv_get_display_clock_speed;
14486 else if (IS_I915GM(dev))
14487 dev_priv->display.get_display_clock_speed =
14488 i915gm_get_display_clock_speed;
14489 else if (IS_I865G(dev))
14490 dev_priv->display.get_display_clock_speed =
14491 i865_get_display_clock_speed;
14492 else if (IS_I85X(dev))
14493 dev_priv->display.get_display_clock_speed =
14494 i85x_get_display_clock_speed;
14496 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14497 dev_priv->display.get_display_clock_speed =
14498 i830_get_display_clock_speed;
14501 if (IS_GEN5(dev)) {
14502 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14503 } else if (IS_GEN6(dev)) {
14504 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14505 } else if (IS_IVYBRIDGE(dev)) {
14506 /* FIXME: detect B0+ stepping and use auto training */
14507 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14508 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14509 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14510 if (IS_BROADWELL(dev)) {
14511 dev_priv->display.modeset_commit_cdclk =
14512 broadwell_modeset_commit_cdclk;
14513 dev_priv->display.modeset_calc_cdclk =
14514 broadwell_modeset_calc_cdclk;
14516 } else if (IS_VALLEYVIEW(dev)) {
14517 dev_priv->display.modeset_commit_cdclk =
14518 valleyview_modeset_commit_cdclk;
14519 dev_priv->display.modeset_calc_cdclk =
14520 valleyview_modeset_calc_cdclk;
14521 } else if (IS_BROXTON(dev)) {
14522 dev_priv->display.modeset_commit_cdclk =
14523 broxton_modeset_commit_cdclk;
14524 dev_priv->display.modeset_calc_cdclk =
14525 broxton_modeset_calc_cdclk;
14528 switch (INTEL_INFO(dev)->gen) {
14530 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14534 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14539 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14543 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14546 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14547 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14550 /* Drop through - unsupported since execlist only. */
14552 /* Default just returns -ENODEV to indicate unsupported */
14553 dev_priv->display.queue_flip = intel_default_queue_flip;
14556 mutex_init(&dev_priv->pps_mutex);
14560 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14561 * resume, or other times. This quirk makes sure that's the case for
14562 * affected systems.
14564 static void quirk_pipea_force(struct drm_device *dev)
14566 struct drm_i915_private *dev_priv = dev->dev_private;
14568 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14569 DRM_INFO("applying pipe a force quirk\n");
14572 static void quirk_pipeb_force(struct drm_device *dev)
14574 struct drm_i915_private *dev_priv = dev->dev_private;
14576 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14577 DRM_INFO("applying pipe b force quirk\n");
14581 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14583 static void quirk_ssc_force_disable(struct drm_device *dev)
14585 struct drm_i915_private *dev_priv = dev->dev_private;
14586 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14587 DRM_INFO("applying lvds SSC disable quirk\n");
14591 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14594 static void quirk_invert_brightness(struct drm_device *dev)
14596 struct drm_i915_private *dev_priv = dev->dev_private;
14597 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14598 DRM_INFO("applying inverted panel brightness quirk\n");
14601 /* Some VBT's incorrectly indicate no backlight is present */
14602 static void quirk_backlight_present(struct drm_device *dev)
14604 struct drm_i915_private *dev_priv = dev->dev_private;
14605 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14606 DRM_INFO("applying backlight present quirk\n");
14609 struct intel_quirk {
14611 int subsystem_vendor;
14612 int subsystem_device;
14613 void (*hook)(struct drm_device *dev);
14616 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14617 struct intel_dmi_quirk {
14618 void (*hook)(struct drm_device *dev);
14619 const struct dmi_system_id (*dmi_id_list)[];
14622 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14624 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14628 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14630 .dmi_id_list = &(const struct dmi_system_id[]) {
14632 .callback = intel_dmi_reverse_brightness,
14633 .ident = "NCR Corporation",
14634 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14635 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14638 { } /* terminating entry */
14640 .hook = quirk_invert_brightness,
14644 static struct intel_quirk intel_quirks[] = {
14645 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14646 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14648 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14649 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14651 /* 830 needs to leave pipe A & dpll A up */
14652 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14654 /* 830 needs to leave pipe B & dpll B up */
14655 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14657 /* Lenovo U160 cannot use SSC on LVDS */
14658 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14660 /* Sony Vaio Y cannot use SSC on LVDS */
14661 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14663 /* Acer Aspire 5734Z must invert backlight brightness */
14664 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14666 /* Acer/eMachines G725 */
14667 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14669 /* Acer/eMachines e725 */
14670 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14672 /* Acer/Packard Bell NCL20 */
14673 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14675 /* Acer Aspire 4736Z */
14676 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14678 /* Acer Aspire 5336 */
14679 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14681 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14682 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14684 /* Acer C720 Chromebook (Core i3 4005U) */
14685 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14687 /* Apple Macbook 2,1 (Core 2 T7400) */
14688 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14690 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14691 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14693 /* HP Chromebook 14 (Celeron 2955U) */
14694 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14696 /* Dell Chromebook 11 */
14697 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14700 static void intel_init_quirks(struct drm_device *dev)
14702 struct pci_dev *d = dev->pdev;
14705 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14706 struct intel_quirk *q = &intel_quirks[i];
14708 if (d->device == q->device &&
14709 (d->subsystem_vendor == q->subsystem_vendor ||
14710 q->subsystem_vendor == PCI_ANY_ID) &&
14711 (d->subsystem_device == q->subsystem_device ||
14712 q->subsystem_device == PCI_ANY_ID))
14715 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14716 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14717 intel_dmi_quirks[i].hook(dev);
14721 /* Disable the VGA plane that we never use */
14722 static void i915_disable_vga(struct drm_device *dev)
14724 struct drm_i915_private *dev_priv = dev->dev_private;
14726 u32 vga_reg = i915_vgacntrl_reg(dev);
14728 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14729 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14730 outb(SR01, VGA_SR_INDEX);
14731 sr1 = inb(VGA_SR_DATA);
14732 outb(sr1 | 1<<5, VGA_SR_DATA);
14733 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14736 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14737 POSTING_READ(vga_reg);
14740 void intel_modeset_init_hw(struct drm_device *dev)
14742 intel_update_cdclk(dev);
14743 intel_prepare_ddi(dev);
14744 intel_init_clock_gating(dev);
14745 intel_enable_gt_powersave(dev);
14748 void intel_modeset_init(struct drm_device *dev)
14750 struct drm_i915_private *dev_priv = dev->dev_private;
14753 struct intel_crtc *crtc;
14755 drm_mode_config_init(dev);
14757 dev->mode_config.min_width = 0;
14758 dev->mode_config.min_height = 0;
14760 dev->mode_config.preferred_depth = 24;
14761 dev->mode_config.prefer_shadow = 1;
14763 dev->mode_config.allow_fb_modifiers = true;
14765 dev->mode_config.funcs = &intel_mode_funcs;
14767 intel_init_quirks(dev);
14769 intel_init_pm(dev);
14771 if (INTEL_INFO(dev)->num_pipes == 0)
14775 * There may be no VBT; and if the BIOS enabled SSC we can
14776 * just keep using it to avoid unnecessary flicker. Whereas if the
14777 * BIOS isn't using it, don't assume it will work even if the VBT
14778 * indicates as much.
14780 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14781 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14784 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14785 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14786 bios_lvds_use_ssc ? "en" : "dis",
14787 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14788 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14792 intel_init_display(dev);
14793 intel_init_audio(dev);
14795 if (IS_GEN2(dev)) {
14796 dev->mode_config.max_width = 2048;
14797 dev->mode_config.max_height = 2048;
14798 } else if (IS_GEN3(dev)) {
14799 dev->mode_config.max_width = 4096;
14800 dev->mode_config.max_height = 4096;
14802 dev->mode_config.max_width = 8192;
14803 dev->mode_config.max_height = 8192;
14806 if (IS_845G(dev) || IS_I865G(dev)) {
14807 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14808 dev->mode_config.cursor_height = 1023;
14809 } else if (IS_GEN2(dev)) {
14810 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14811 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14813 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14814 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14817 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14819 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14820 INTEL_INFO(dev)->num_pipes,
14821 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14823 for_each_pipe(dev_priv, pipe) {
14824 intel_crtc_init(dev, pipe);
14825 for_each_sprite(dev_priv, pipe, sprite) {
14826 ret = intel_plane_init(dev, pipe, sprite);
14828 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14829 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14833 intel_update_czclk(dev_priv);
14834 intel_update_cdclk(dev);
14836 intel_shared_dpll_init(dev);
14838 /* Just disable it once at startup */
14839 i915_disable_vga(dev);
14840 intel_setup_outputs(dev);
14842 /* Just in case the BIOS is doing something questionable. */
14843 intel_fbc_disable(dev_priv);
14845 drm_modeset_lock_all(dev);
14846 intel_modeset_setup_hw_state(dev);
14847 drm_modeset_unlock_all(dev);
14849 for_each_intel_crtc(dev, crtc) {
14850 struct intel_initial_plane_config plane_config = {};
14856 * Note that reserving the BIOS fb up front prevents us
14857 * from stuffing other stolen allocations like the ring
14858 * on top. This prevents some ugliness at boot time, and
14859 * can even allow for smooth boot transitions if the BIOS
14860 * fb is large enough for the active pipe configuration.
14862 dev_priv->display.get_initial_plane_config(crtc,
14866 * If the fb is shared between multiple heads, we'll
14867 * just get the first one.
14869 intel_find_initial_plane_obj(crtc, &plane_config);
14873 static void intel_enable_pipe_a(struct drm_device *dev)
14875 struct intel_connector *connector;
14876 struct drm_connector *crt = NULL;
14877 struct intel_load_detect_pipe load_detect_temp;
14878 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14880 /* We can't just switch on the pipe A, we need to set things up with a
14881 * proper mode and output configuration. As a gross hack, enable pipe A
14882 * by enabling the load detect pipe once. */
14883 for_each_intel_connector(dev, connector) {
14884 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14885 crt = &connector->base;
14893 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14894 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14898 intel_check_plane_mapping(struct intel_crtc *crtc)
14900 struct drm_device *dev = crtc->base.dev;
14901 struct drm_i915_private *dev_priv = dev->dev_private;
14904 if (INTEL_INFO(dev)->num_pipes == 1)
14907 val = I915_READ(DSPCNTR(!crtc->plane));
14909 if ((val & DISPLAY_PLANE_ENABLE) &&
14910 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14916 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14918 struct drm_device *dev = crtc->base.dev;
14919 struct intel_encoder *encoder;
14921 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14927 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14929 struct drm_device *dev = crtc->base.dev;
14930 struct drm_i915_private *dev_priv = dev->dev_private;
14933 /* Clear any frame start delays used for debugging left by the BIOS */
14934 reg = PIPECONF(crtc->config->cpu_transcoder);
14935 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14937 /* restore vblank interrupts to correct state */
14938 drm_crtc_vblank_reset(&crtc->base);
14939 if (crtc->active) {
14940 struct intel_plane *plane;
14942 drm_crtc_vblank_on(&crtc->base);
14944 /* Disable everything but the primary plane */
14945 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14946 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14949 plane->disable_plane(&plane->base, &crtc->base);
14953 /* We need to sanitize the plane -> pipe mapping first because this will
14954 * disable the crtc (and hence change the state) if it is wrong. Note
14955 * that gen4+ has a fixed plane -> pipe mapping. */
14956 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14959 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14960 crtc->base.base.id);
14962 /* Pipe has the wrong plane attached and the plane is active.
14963 * Temporarily change the plane mapping and disable everything
14965 plane = crtc->plane;
14966 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14967 crtc->plane = !plane;
14968 intel_crtc_disable_noatomic(&crtc->base);
14969 crtc->plane = plane;
14972 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14973 crtc->pipe == PIPE_A && !crtc->active) {
14974 /* BIOS forgot to enable pipe A, this mostly happens after
14975 * resume. Force-enable the pipe to fix this, the update_dpms
14976 * call below we restore the pipe to the right state, but leave
14977 * the required bits on. */
14978 intel_enable_pipe_a(dev);
14981 /* Adjust the state of the output pipe according to whether we
14982 * have active connectors/encoders. */
14983 if (!intel_crtc_has_encoders(crtc))
14984 intel_crtc_disable_noatomic(&crtc->base);
14986 if (crtc->active != crtc->base.state->active) {
14987 struct intel_encoder *encoder;
14989 /* This can happen either due to bugs in the get_hw_state
14990 * functions or because of calls to intel_crtc_disable_noatomic,
14991 * or because the pipe is force-enabled due to the
14993 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14994 crtc->base.base.id,
14995 crtc->base.state->enable ? "enabled" : "disabled",
14996 crtc->active ? "enabled" : "disabled");
14998 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
14999 crtc->base.state->active = crtc->active;
15000 crtc->base.enabled = crtc->active;
15002 /* Because we only establish the connector -> encoder ->
15003 * crtc links if something is active, this means the
15004 * crtc is now deactivated. Break the links. connector
15005 * -> encoder links are only establish when things are
15006 * actually up, hence no need to break them. */
15007 WARN_ON(crtc->active);
15009 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15010 encoder->base.crtc = NULL;
15013 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15015 * We start out with underrun reporting disabled to avoid races.
15016 * For correct bookkeeping mark this on active crtcs.
15018 * Also on gmch platforms we dont have any hardware bits to
15019 * disable the underrun reporting. Which means we need to start
15020 * out with underrun reporting disabled also on inactive pipes,
15021 * since otherwise we'll complain about the garbage we read when
15022 * e.g. coming up after runtime pm.
15024 * No protection against concurrent access is required - at
15025 * worst a fifo underrun happens which also sets this to false.
15027 crtc->cpu_fifo_underrun_disabled = true;
15028 crtc->pch_fifo_underrun_disabled = true;
15032 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15034 struct intel_connector *connector;
15035 struct drm_device *dev = encoder->base.dev;
15036 bool active = false;
15038 /* We need to check both for a crtc link (meaning that the
15039 * encoder is active and trying to read from a pipe) and the
15040 * pipe itself being active. */
15041 bool has_active_crtc = encoder->base.crtc &&
15042 to_intel_crtc(encoder->base.crtc)->active;
15044 for_each_intel_connector(dev, connector) {
15045 if (connector->base.encoder != &encoder->base)
15052 if (active && !has_active_crtc) {
15053 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15054 encoder->base.base.id,
15055 encoder->base.name);
15057 /* Connector is active, but has no active pipe. This is
15058 * fallout from our resume register restoring. Disable
15059 * the encoder manually again. */
15060 if (encoder->base.crtc) {
15061 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15062 encoder->base.base.id,
15063 encoder->base.name);
15064 encoder->disable(encoder);
15065 if (encoder->post_disable)
15066 encoder->post_disable(encoder);
15068 encoder->base.crtc = NULL;
15070 /* Inconsistent output/port/pipe state happens presumably due to
15071 * a bug in one of the get_hw_state functions. Or someplace else
15072 * in our code, like the register restore mess on resume. Clamp
15073 * things to off as a safer default. */
15074 for_each_intel_connector(dev, connector) {
15075 if (connector->encoder != encoder)
15077 connector->base.dpms = DRM_MODE_DPMS_OFF;
15078 connector->base.encoder = NULL;
15081 /* Enabled encoders without active connectors will be fixed in
15082 * the crtc fixup. */
15085 void i915_redisable_vga_power_on(struct drm_device *dev)
15087 struct drm_i915_private *dev_priv = dev->dev_private;
15088 u32 vga_reg = i915_vgacntrl_reg(dev);
15090 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15091 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15092 i915_disable_vga(dev);
15096 void i915_redisable_vga(struct drm_device *dev)
15098 struct drm_i915_private *dev_priv = dev->dev_private;
15100 /* This function can be called both from intel_modeset_setup_hw_state or
15101 * at a very early point in our resume sequence, where the power well
15102 * structures are not yet restored. Since this function is at a very
15103 * paranoid "someone might have enabled VGA while we were not looking"
15104 * level, just check if the power well is enabled instead of trying to
15105 * follow the "don't touch the power well if we don't need it" policy
15106 * the rest of the driver uses. */
15107 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15110 i915_redisable_vga_power_on(dev);
15113 static bool primary_get_hw_state(struct intel_plane *plane)
15115 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15117 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15120 /* FIXME read out full plane state for all planes */
15121 static void readout_plane_state(struct intel_crtc *crtc)
15123 struct drm_plane *primary = crtc->base.primary;
15124 struct intel_plane_state *plane_state =
15125 to_intel_plane_state(primary->state);
15127 plane_state->visible =
15128 primary_get_hw_state(to_intel_plane(primary));
15130 if (plane_state->visible)
15131 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15134 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15136 struct drm_i915_private *dev_priv = dev->dev_private;
15138 struct intel_crtc *crtc;
15139 struct intel_encoder *encoder;
15140 struct intel_connector *connector;
15143 for_each_intel_crtc(dev, crtc) {
15144 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15145 memset(crtc->config, 0, sizeof(*crtc->config));
15146 crtc->config->base.crtc = &crtc->base;
15148 crtc->active = dev_priv->display.get_pipe_config(crtc,
15151 crtc->base.state->active = crtc->active;
15152 crtc->base.enabled = crtc->active;
15154 readout_plane_state(crtc);
15156 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15157 crtc->base.base.id,
15158 crtc->active ? "enabled" : "disabled");
15161 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15162 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15164 pll->on = pll->get_hw_state(dev_priv, pll,
15165 &pll->config.hw_state);
15167 pll->config.crtc_mask = 0;
15168 for_each_intel_crtc(dev, crtc) {
15169 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15171 pll->config.crtc_mask |= 1 << crtc->pipe;
15175 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15176 pll->name, pll->config.crtc_mask, pll->on);
15178 if (pll->config.crtc_mask)
15179 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15182 for_each_intel_encoder(dev, encoder) {
15185 if (encoder->get_hw_state(encoder, &pipe)) {
15186 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15187 encoder->base.crtc = &crtc->base;
15188 encoder->get_config(encoder, crtc->config);
15190 encoder->base.crtc = NULL;
15193 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15194 encoder->base.base.id,
15195 encoder->base.name,
15196 encoder->base.crtc ? "enabled" : "disabled",
15200 for_each_intel_connector(dev, connector) {
15201 if (connector->get_hw_state(connector)) {
15202 connector->base.dpms = DRM_MODE_DPMS_ON;
15203 connector->base.encoder = &connector->encoder->base;
15205 connector->base.dpms = DRM_MODE_DPMS_OFF;
15206 connector->base.encoder = NULL;
15208 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15209 connector->base.base.id,
15210 connector->base.name,
15211 connector->base.encoder ? "enabled" : "disabled");
15214 for_each_intel_crtc(dev, crtc) {
15215 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15217 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15218 if (crtc->base.state->active) {
15219 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15220 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15221 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15224 * The initial mode needs to be set in order to keep
15225 * the atomic core happy. It wants a valid mode if the
15226 * crtc's enabled, so we do the above call.
15228 * At this point some state updated by the connectors
15229 * in their ->detect() callback has not run yet, so
15230 * no recalculation can be done yet.
15232 * Even if we could do a recalculation and modeset
15233 * right now it would cause a double modeset if
15234 * fbdev or userspace chooses a different initial mode.
15236 * If that happens, someone indicated they wanted a
15237 * mode change, which means it's safe to do a full
15240 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15242 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15243 update_scanline_offset(crtc);
15248 /* Scan out the current hw modeset state,
15249 * and sanitizes it to the current state
15252 intel_modeset_setup_hw_state(struct drm_device *dev)
15254 struct drm_i915_private *dev_priv = dev->dev_private;
15256 struct intel_crtc *crtc;
15257 struct intel_encoder *encoder;
15260 intel_modeset_readout_hw_state(dev);
15262 /* HW state is read out, now we need to sanitize this mess. */
15263 for_each_intel_encoder(dev, encoder) {
15264 intel_sanitize_encoder(encoder);
15267 for_each_pipe(dev_priv, pipe) {
15268 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15269 intel_sanitize_crtc(crtc);
15270 intel_dump_pipe_config(crtc, crtc->config,
15271 "[setup_hw_state]");
15274 intel_modeset_update_connector_atomic_state(dev);
15276 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15277 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15279 if (!pll->on || pll->active)
15282 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15284 pll->disable(dev_priv, pll);
15288 if (IS_VALLEYVIEW(dev))
15289 vlv_wm_get_hw_state(dev);
15290 else if (IS_GEN9(dev))
15291 skl_wm_get_hw_state(dev);
15292 else if (HAS_PCH_SPLIT(dev))
15293 ilk_wm_get_hw_state(dev);
15295 for_each_intel_crtc(dev, crtc) {
15296 unsigned long put_domains;
15298 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15299 if (WARN_ON(put_domains))
15300 modeset_put_power_domains(dev_priv, put_domains);
15302 intel_display_set_init_power(dev_priv, false);
15305 void intel_display_resume(struct drm_device *dev)
15307 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15308 struct intel_connector *conn;
15309 struct intel_plane *plane;
15310 struct drm_crtc *crtc;
15316 state->acquire_ctx = dev->mode_config.acquire_ctx;
15318 /* preserve complete old state, including dpll */
15319 intel_atomic_get_shared_dpll_state(state);
15321 for_each_crtc(dev, crtc) {
15322 struct drm_crtc_state *crtc_state =
15323 drm_atomic_get_crtc_state(state, crtc);
15325 ret = PTR_ERR_OR_ZERO(crtc_state);
15329 /* force a restore */
15330 crtc_state->mode_changed = true;
15333 for_each_intel_plane(dev, plane) {
15334 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15339 for_each_intel_connector(dev, conn) {
15340 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15345 intel_modeset_setup_hw_state(dev);
15347 i915_redisable_vga(dev);
15348 ret = drm_atomic_commit(state);
15353 DRM_ERROR("Restoring old state failed with %i\n", ret);
15354 drm_atomic_state_free(state);
15357 void intel_modeset_gem_init(struct drm_device *dev)
15359 struct drm_crtc *c;
15360 struct drm_i915_gem_object *obj;
15363 mutex_lock(&dev->struct_mutex);
15364 intel_init_gt_powersave(dev);
15365 mutex_unlock(&dev->struct_mutex);
15367 intel_modeset_init_hw(dev);
15369 intel_setup_overlay(dev);
15372 * Make sure any fbs we allocated at startup are properly
15373 * pinned & fenced. When we do the allocation it's too early
15376 for_each_crtc(dev, c) {
15377 obj = intel_fb_obj(c->primary->fb);
15381 mutex_lock(&dev->struct_mutex);
15382 ret = intel_pin_and_fence_fb_obj(c->primary,
15386 mutex_unlock(&dev->struct_mutex);
15388 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15389 to_intel_crtc(c)->pipe);
15390 drm_framebuffer_unreference(c->primary->fb);
15391 c->primary->fb = NULL;
15392 c->primary->crtc = c->primary->state->crtc = NULL;
15393 update_state_fb(c->primary);
15394 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15398 intel_backlight_register(dev);
15401 void intel_connector_unregister(struct intel_connector *intel_connector)
15403 struct drm_connector *connector = &intel_connector->base;
15405 intel_panel_destroy_backlight(connector);
15406 drm_connector_unregister(connector);
15409 void intel_modeset_cleanup(struct drm_device *dev)
15411 struct drm_i915_private *dev_priv = dev->dev_private;
15412 struct drm_connector *connector;
15414 intel_disable_gt_powersave(dev);
15416 intel_backlight_unregister(dev);
15419 * Interrupts and polling as the first thing to avoid creating havoc.
15420 * Too much stuff here (turning of connectors, ...) would
15421 * experience fancy races otherwise.
15423 intel_irq_uninstall(dev_priv);
15426 * Due to the hpd irq storm handling the hotplug work can re-arm the
15427 * poll handlers. Hence disable polling after hpd handling is shut down.
15429 drm_kms_helper_poll_fini(dev);
15431 intel_unregister_dsm_handler();
15433 intel_fbc_disable(dev_priv);
15435 /* flush any delayed tasks or pending work */
15436 flush_scheduled_work();
15438 /* destroy the backlight and sysfs files before encoders/connectors */
15439 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15440 struct intel_connector *intel_connector;
15442 intel_connector = to_intel_connector(connector);
15443 intel_connector->unregister(intel_connector);
15446 drm_mode_config_cleanup(dev);
15448 intel_cleanup_overlay(dev);
15450 mutex_lock(&dev->struct_mutex);
15451 intel_cleanup_gt_powersave(dev);
15452 mutex_unlock(&dev->struct_mutex);
15456 * Return which encoder is currently attached for connector.
15458 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15460 return &intel_attached_encoder(connector)->base;
15463 void intel_connector_attach_encoder(struct intel_connector *connector,
15464 struct intel_encoder *encoder)
15466 connector->encoder = encoder;
15467 drm_mode_connector_attach_encoder(&connector->base,
15472 * set vga decode state - true == enable VGA decode
15474 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15476 struct drm_i915_private *dev_priv = dev->dev_private;
15477 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15480 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15481 DRM_ERROR("failed to read control word\n");
15485 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15489 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15491 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15493 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15494 DRM_ERROR("failed to write control word\n");
15501 struct intel_display_error_state {
15503 u32 power_well_driver;
15505 int num_transcoders;
15507 struct intel_cursor_error_state {
15512 } cursor[I915_MAX_PIPES];
15514 struct intel_pipe_error_state {
15515 bool power_domain_on;
15518 } pipe[I915_MAX_PIPES];
15520 struct intel_plane_error_state {
15528 } plane[I915_MAX_PIPES];
15530 struct intel_transcoder_error_state {
15531 bool power_domain_on;
15532 enum transcoder cpu_transcoder;
15545 struct intel_display_error_state *
15546 intel_display_capture_error_state(struct drm_device *dev)
15548 struct drm_i915_private *dev_priv = dev->dev_private;
15549 struct intel_display_error_state *error;
15550 int transcoders[] = {
15558 if (INTEL_INFO(dev)->num_pipes == 0)
15561 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15565 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15566 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15568 for_each_pipe(dev_priv, i) {
15569 error->pipe[i].power_domain_on =
15570 __intel_display_power_is_enabled(dev_priv,
15571 POWER_DOMAIN_PIPE(i));
15572 if (!error->pipe[i].power_domain_on)
15575 error->cursor[i].control = I915_READ(CURCNTR(i));
15576 error->cursor[i].position = I915_READ(CURPOS(i));
15577 error->cursor[i].base = I915_READ(CURBASE(i));
15579 error->plane[i].control = I915_READ(DSPCNTR(i));
15580 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15581 if (INTEL_INFO(dev)->gen <= 3) {
15582 error->plane[i].size = I915_READ(DSPSIZE(i));
15583 error->plane[i].pos = I915_READ(DSPPOS(i));
15585 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15586 error->plane[i].addr = I915_READ(DSPADDR(i));
15587 if (INTEL_INFO(dev)->gen >= 4) {
15588 error->plane[i].surface = I915_READ(DSPSURF(i));
15589 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15592 error->pipe[i].source = I915_READ(PIPESRC(i));
15594 if (HAS_GMCH_DISPLAY(dev))
15595 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15598 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15599 if (HAS_DDI(dev_priv->dev))
15600 error->num_transcoders++; /* Account for eDP. */
15602 for (i = 0; i < error->num_transcoders; i++) {
15603 enum transcoder cpu_transcoder = transcoders[i];
15605 error->transcoder[i].power_domain_on =
15606 __intel_display_power_is_enabled(dev_priv,
15607 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15608 if (!error->transcoder[i].power_domain_on)
15611 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15613 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15614 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15615 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15616 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15617 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15618 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15619 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15625 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15628 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15629 struct drm_device *dev,
15630 struct intel_display_error_state *error)
15632 struct drm_i915_private *dev_priv = dev->dev_private;
15638 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15639 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15640 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15641 error->power_well_driver);
15642 for_each_pipe(dev_priv, i) {
15643 err_printf(m, "Pipe [%d]:\n", i);
15644 err_printf(m, " Power: %s\n",
15645 error->pipe[i].power_domain_on ? "on" : "off");
15646 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15647 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15649 err_printf(m, "Plane [%d]:\n", i);
15650 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15651 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15652 if (INTEL_INFO(dev)->gen <= 3) {
15653 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15654 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15656 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15657 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15658 if (INTEL_INFO(dev)->gen >= 4) {
15659 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15660 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15663 err_printf(m, "Cursor [%d]:\n", i);
15664 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15665 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15666 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15669 for (i = 0; i < error->num_transcoders; i++) {
15670 err_printf(m, "CPU transcoder: %c\n",
15671 transcoder_name(error->transcoder[i].cpu_transcoder));
15672 err_printf(m, " Power: %s\n",
15673 error->transcoder[i].power_domain_on ? "on" : "off");
15674 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15675 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15676 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15677 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15678 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15679 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15680 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15684 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15686 struct intel_crtc *crtc;
15688 for_each_intel_crtc(dev, crtc) {
15689 struct intel_unpin_work *work;
15691 spin_lock_irq(&dev->event_lock);
15693 work = crtc->unpin_work;
15695 if (work && work->event &&
15696 work->event->base.file_priv == file) {
15697 kfree(work->event);
15698 work->event = NULL;
15701 spin_unlock_irq(&dev->event_lock);