drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats for gen <= 3 */
  49 static const uint32_t i8xx_primary_formats[] = {
  50         DRM_FORMAT_C8,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_XRGB1555,
  53         DRM_FORMAT_XRGB8888,
  54 };
  55
  56 /* Primary plane formats for gen >= 4 */
  57 static const uint32_t i965_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB8888,
  61         DRM_FORMAT_XBGR8888,
  62         DRM_FORMAT_XRGB2101010,
  63         DRM_FORMAT_XBGR2101010,
  64 };
  65
  66 static const uint32_t skl_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_ARGB8888,
  72         DRM_FORMAT_ABGR8888,
  73         DRM_FORMAT_XRGB2101010,
  74         DRM_FORMAT_XBGR2101010,
  75 };
  76
  77 /* Cursor formats */
  78 static const uint32_t intel_cursor_formats[] = {
  79         DRM_FORMAT_ARGB8888,
  80 };
  81
  82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  83
  84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  85                                 struct intel_crtc_state *pipe_config);
  86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  87                                    struct intel_crtc_state *pipe_config);
  88
  89 static int intel_framebuffer_init(struct drm_device *dev,
  90                                   struct intel_framebuffer *ifb,
  91                                   struct drm_mode_fb_cmd2 *mode_cmd,
  92                                   struct drm_i915_gem_object *obj);
  93 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  94 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  95 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  96                                          struct intel_link_m_n *m_n,
  97                                          struct intel_link_m_n *m2_n2);
  98 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  99 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 100 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 101 static void vlv_prepare_pll(struct intel_crtc *crtc,
 102                             const struct intel_crtc_state *pipe_config);
 103 static void chv_prepare_pll(struct intel_crtc *crtc,
 104                             const struct intel_crtc_state *pipe_config);
 105 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 106 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 107 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 108         struct intel_crtc_state *crtc_state);
 109 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 110                            int num_connectors);
 111 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 112
 113 typedef struct {
 114         int     min, max;
 115 } intel_range_t;
 116
 117 typedef struct {
 118         int     dot_limit;
 119         int     p2_slow, p2_fast;
 120 } intel_p2_t;
 121
 122 typedef struct intel_limit intel_limit_t;
 123 struct intel_limit {
 124         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 125         intel_p2_t          p2;
 126 };
 127
 128 int
 129 intel_pch_rawclk(struct drm_device *dev)
 130 {
 131         struct drm_i915_private *dev_priv = dev->dev_private;
 132
 133         WARN_ON(!HAS_PCH_SPLIT(dev));
 134
 135         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 136 }
 137
 138 static inline u32 /* units of 100MHz */
 139 intel_fdi_link_freq(struct drm_device *dev)
 140 {
 141         if (IS_GEN5(dev)) {
 142                 struct drm_i915_private *dev_priv = dev->dev_private;
 143                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 144         } else
 145                 return 27;
 146 }
 147
 148 static const intel_limit_t intel_limits_i8xx_dac = {
 149         .dot = { .min = 25000, .max = 350000 },
 150         .vco = { .min = 908000, .max = 1512000 },
 151         .n = { .min = 2, .max = 16 },
 152         .m = { .min = 96, .max = 140 },
 153         .m1 = { .min = 18, .max = 26 },
 154         .m2 = { .min = 6, .max = 16 },
 155         .p = { .min = 4, .max = 128 },
 156         .p1 = { .min = 2, .max = 33 },
 157         .p2 = { .dot_limit = 165000,
 158                 .p2_slow = 4, .p2_fast = 2 },
 159 };
 160
 161 static const intel_limit_t intel_limits_i8xx_dvo = {
 162         .dot = { .min = 25000, .max = 350000 },
 163         .vco = { .min = 908000, .max = 1512000 },
 164         .n = { .min = 2, .max = 16 },
 165         .m = { .min = 96, .max = 140 },
 166         .m1 = { .min = 18, .max = 26 },
 167         .m2 = { .min = 6, .max = 16 },
 168         .p = { .min = 4, .max = 128 },
 169         .p1 = { .min = 2, .max = 33 },
 170         .p2 = { .dot_limit = 165000,
 171                 .p2_slow = 4, .p2_fast = 4 },
 172 };
 173
 174 static const intel_limit_t intel_limits_i8xx_lvds = {
 175         .dot = { .min = 25000, .max = 350000 },
 176         .vco = { .min = 908000, .max = 1512000 },
 177         .n = { .min = 2, .max = 16 },
 178         .m = { .min = 96, .max = 140 },
 179         .m1 = { .min = 18, .max = 26 },
 180         .m2 = { .min = 6, .max = 16 },
 181         .p = { .min = 4, .max = 128 },
 182         .p1 = { .min = 1, .max = 6 },
 183         .p2 = { .dot_limit = 165000,
 184                 .p2_slow = 14, .p2_fast = 7 },
 185 };
 186
 187 static const intel_limit_t intel_limits_i9xx_sdvo = {
 188         .dot = { .min = 20000, .max = 400000 },
 189         .vco = { .min = 1400000, .max = 2800000 },
 190         .n = { .min = 1, .max = 6 },
 191         .m = { .min = 70, .max = 120 },
 192         .m1 = { .min = 8, .max = 18 },
 193         .m2 = { .min = 3, .max = 7 },
 194         .p = { .min = 5, .max = 80 },
 195         .p1 = { .min = 1, .max = 8 },
 196         .p2 = { .dot_limit = 200000,
 197                 .p2_slow = 10, .p2_fast = 5 },
 198 };
 199
 200 static const intel_limit_t intel_limits_i9xx_lvds = {
 201         .dot = { .min = 20000, .max = 400000 },
 202         .vco = { .min = 1400000, .max = 2800000 },
 203         .n = { .min = 1, .max = 6 },
 204         .m = { .min = 70, .max = 120 },
 205         .m1 = { .min = 8, .max = 18 },
 206         .m2 = { .min = 3, .max = 7 },
 207         .p = { .min = 7, .max = 98 },
 208         .p1 = { .min = 1, .max = 8 },
 209         .p2 = { .dot_limit = 112000,
 210                 .p2_slow = 14, .p2_fast = 7 },
 211 };
 212
 213
 214 static const intel_limit_t intel_limits_g4x_sdvo = {
 215         .dot = { .min = 25000, .max = 270000 },
 216         .vco = { .min = 1750000, .max = 3500000},
 217         .n = { .min = 1, .max = 4 },
 218         .m = { .min = 104, .max = 138 },
 219         .m1 = { .min = 17, .max = 23 },
 220         .m2 = { .min = 5, .max = 11 },
 221         .p = { .min = 10, .max = 30 },
 222         .p1 = { .min = 1, .max = 3},
 223         .p2 = { .dot_limit = 270000,
 224                 .p2_slow = 10,
 225                 .p2_fast = 10
 226         },
 227 };
 228
 229 static const intel_limit_t intel_limits_g4x_hdmi = {
 230         .dot = { .min = 22000, .max = 400000 },
 231         .vco = { .min = 1750000, .max = 3500000},
 232         .n = { .min = 1, .max = 4 },
 233         .m = { .min = 104, .max = 138 },
 234         .m1 = { .min = 16, .max = 23 },
 235         .m2 = { .min = 5, .max = 11 },
 236         .p = { .min = 5, .max = 80 },
 237         .p1 = { .min = 1, .max = 8},
 238         .p2 = { .dot_limit = 165000,
 239                 .p2_slow = 10, .p2_fast = 5 },
 240 };
 241
 242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 243         .dot = { .min = 20000, .max = 115000 },
 244         .vco = { .min = 1750000, .max = 3500000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 104, .max = 138 },
 247         .m1 = { .min = 17, .max = 23 },
 248         .m2 = { .min = 5, .max = 11 },
 249         .p = { .min = 28, .max = 112 },
 250         .p1 = { .min = 2, .max = 8 },
 251         .p2 = { .dot_limit = 0,
 252                 .p2_slow = 14, .p2_fast = 14
 253         },
 254 };
 255
 256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 257         .dot = { .min = 80000, .max = 224000 },
 258         .vco = { .min = 1750000, .max = 3500000 },
 259         .n = { .min = 1, .max = 3 },
 260         .m = { .min = 104, .max = 138 },
 261         .m1 = { .min = 17, .max = 23 },
 262         .m2 = { .min = 5, .max = 11 },
 263         .p = { .min = 14, .max = 42 },
 264         .p1 = { .min = 2, .max = 6 },
 265         .p2 = { .dot_limit = 0,
 266                 .p2_slow = 7, .p2_fast = 7
 267         },
 268 };
 269
 270 static const intel_limit_t intel_limits_pineview_sdvo = {
 271         .dot = { .min = 20000, .max = 400000},
 272         .vco = { .min = 1700000, .max = 3500000 },
 273         /* Pineview's Ncounter is a ring counter */
 274         .n = { .min = 3, .max = 6 },
 275         .m = { .min = 2, .max = 256 },
 276         /* Pineview only has one combined m divider, which we treat as m2. */
 277         .m1 = { .min = 0, .max = 0 },
 278         .m2 = { .min = 0, .max = 254 },
 279         .p = { .min = 5, .max = 80 },
 280         .p1 = { .min = 1, .max = 8 },
 281         .p2 = { .dot_limit = 200000,
 282                 .p2_slow = 10, .p2_fast = 5 },
 283 };
 284
 285 static const intel_limit_t intel_limits_pineview_lvds = {
 286         .dot = { .min = 20000, .max = 400000 },
 287         .vco = { .min = 1700000, .max = 3500000 },
 288         .n = { .min = 3, .max = 6 },
 289         .m = { .min = 2, .max = 256 },
 290         .m1 = { .min = 0, .max = 0 },
 291         .m2 = { .min = 0, .max = 254 },
 292         .p = { .min = 7, .max = 112 },
 293         .p1 = { .min = 1, .max = 8 },
 294         .p2 = { .dot_limit = 112000,
 295                 .p2_slow = 14, .p2_fast = 14 },
 296 };
 297
 298 /* Ironlake / Sandybridge
 299  *
 300  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 301  * the range value for them is (actual_value - 2).
 302  */
 303 static const intel_limit_t intel_limits_ironlake_dac = {
 304         .dot = { .min = 25000, .max = 350000 },
 305         .vco = { .min = 1760000, .max = 3510000 },
 306         .n = { .min = 1, .max = 5 },
 307         .m = { .min = 79, .max = 127 },
 308         .m1 = { .min = 12, .max = 22 },
 309         .m2 = { .min = 5, .max = 9 },
 310         .p = { .min = 5, .max = 80 },
 311         .p1 = { .min = 1, .max = 8 },
 312         .p2 = { .dot_limit = 225000,
 313                 .p2_slow = 10, .p2_fast = 5 },
 314 };
 315
 316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 317         .dot = { .min = 25000, .max = 350000 },
 318         .vco = { .min = 1760000, .max = 3510000 },
 319         .n = { .min = 1, .max = 3 },
 320         .m = { .min = 79, .max = 118 },
 321         .m1 = { .min = 12, .max = 22 },
 322         .m2 = { .min = 5, .max = 9 },
 323         .p = { .min = 28, .max = 112 },
 324         .p1 = { .min = 2, .max = 8 },
 325         .p2 = { .dot_limit = 225000,
 326                 .p2_slow = 14, .p2_fast = 14 },
 327 };
 328
 329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 330         .dot = { .min = 25000, .max = 350000 },
 331         .vco = { .min = 1760000, .max = 3510000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 79, .max = 127 },
 334         .m1 = { .min = 12, .max = 22 },
 335         .m2 = { .min = 5, .max = 9 },
 336         .p = { .min = 14, .max = 56 },
 337         .p1 = { .min = 2, .max = 8 },
 338         .p2 = { .dot_limit = 225000,
 339                 .p2_slow = 7, .p2_fast = 7 },
 340 };
 341
 342 /* LVDS 100mhz refclk limits. */
 343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 344         .dot = { .min = 25000, .max = 350000 },
 345         .vco = { .min = 1760000, .max = 3510000 },
 346         .n = { .min = 1, .max = 2 },
 347         .m = { .min = 79, .max = 126 },
 348         .m1 = { .min = 12, .max = 22 },
 349         .m2 = { .min = 5, .max = 9 },
 350         .p = { .min = 28, .max = 112 },
 351         .p1 = { .min = 2, .max = 8 },
 352         .p2 = { .dot_limit = 225000,
 353                 .p2_slow = 14, .p2_fast = 14 },
 354 };
 355
 356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 357         .dot = { .min = 25000, .max = 350000 },
 358         .vco = { .min = 1760000, .max = 3510000 },
 359         .n = { .min = 1, .max = 3 },
 360         .m = { .min = 79, .max = 126 },
 361         .m1 = { .min = 12, .max = 22 },
 362         .m2 = { .min = 5, .max = 9 },
 363         .p = { .min = 14, .max = 42 },
 364         .p1 = { .min = 2, .max = 6 },
 365         .p2 = { .dot_limit = 225000,
 366                 .p2_slow = 7, .p2_fast = 7 },
 367 };
 368
 369 static const intel_limit_t intel_limits_vlv = {
 370          /*
 371           * These are the data rate limits (measured in fast clocks)
 372           * since those are the strictest limits we have. The fast
 373           * clock and actual rate limits are more relaxed, so checking
 374           * them would make no difference.
 375           */
 376         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 377         .vco = { .min = 4000000, .max = 6000000 },
 378         .n = { .min = 1, .max = 7 },
 379         .m1 = { .min = 2, .max = 3 },
 380         .m2 = { .min = 11, .max = 156 },
 381         .p1 = { .min = 2, .max = 3 },
 382         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 383 };
 384
 385 static const intel_limit_t intel_limits_chv = {
 386         /*
 387          * These are the data rate limits (measured in fast clocks)
 388          * since those are the strictest limits we have.  The fast
 389          * clock and actual rate limits are more relaxed, so checking
 390          * them would make no difference.
 391          */
 392         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 393         .vco = { .min = 4800000, .max = 6480000 },
 394         .n = { .min = 1, .max = 1 },
 395         .m1 = { .min = 2, .max = 2 },
 396         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 397         .p1 = { .min = 2, .max = 4 },
 398         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 399 };
 400
 401 static const intel_limit_t intel_limits_bxt = {
 402         /* FIXME: find real dot limits */
 403         .dot = { .min = 0, .max = INT_MAX },
 404         .vco = { .min = 4800000, .max = 6700000 },
 405         .n = { .min = 1, .max = 1 },
 406         .m1 = { .min = 2, .max = 2 },
 407         /* FIXME: find real m2 limits */
 408         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 409         .p1 = { .min = 2, .max = 4 },
 410         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 411 };
 412
 413 static bool
 414 needs_modeset(struct drm_crtc_state *state)
 415 {
 416         return drm_atomic_crtc_needs_modeset(state);
 417 }
 418
 419 /**
 420  * Returns whether any output on the specified pipe is of the specified type
 421  */
 422 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 423 {
 424         struct drm_device *dev = crtc->base.dev;
 425         struct intel_encoder *encoder;
 426
 427         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 428                 if (encoder->type == type)
 429                         return true;
 430
 431         return false;
 432 }
 433
 434 /**
 435  * Returns whether any output on the specified pipe will have the specified
 436  * type after a staged modeset is complete, i.e., the same as
 437  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 438  * encoder->crtc.
 439  */
 440 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 441                                       int type)
 442 {
 443         struct drm_atomic_state *state = crtc_state->base.state;
 444         struct drm_connector *connector;
 445         struct drm_connector_state *connector_state;
 446         struct intel_encoder *encoder;
 447         int i, num_connectors = 0;
 448
 449         for_each_connector_in_state(state, connector, connector_state, i) {
 450                 if (connector_state->crtc != crtc_state->base.crtc)
 451                         continue;
 452
 453                 num_connectors++;
 454
 455                 encoder = to_intel_encoder(connector_state->best_encoder);
 456                 if (encoder->type == type)
 457                         return true;
 458         }
 459
 460         WARN_ON(num_connectors == 0);
 461
 462         return false;
 463 }
 464
 465 static const intel_limit_t *
 466 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 467 {
 468         struct drm_device *dev = crtc_state->base.crtc->dev;
 469         const intel_limit_t *limit;
 470
 471         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 472                 if (intel_is_dual_link_lvds(dev)) {
 473                         if (refclk == 100000)
 474                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 475                         else
 476                                 limit = &intel_limits_ironlake_dual_lvds;
 477                 } else {
 478                         if (refclk == 100000)
 479                                 limit = &intel_limits_ironlake_single_lvds_100m;
 480                         else
 481                                 limit = &intel_limits_ironlake_single_lvds;
 482                 }
 483         } else
 484                 limit = &intel_limits_ironlake_dac;
 485
 486         return limit;
 487 }
 488
 489 static const intel_limit_t *
 490 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 491 {
 492         struct drm_device *dev = crtc_state->base.crtc->dev;
 493         const intel_limit_t *limit;
 494
 495         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 496                 if (intel_is_dual_link_lvds(dev))
 497                         limit = &intel_limits_g4x_dual_channel_lvds;
 498                 else
 499                         limit = &intel_limits_g4x_single_channel_lvds;
 500         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 501                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 502                 limit = &intel_limits_g4x_hdmi;
 503         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 504                 limit = &intel_limits_g4x_sdvo;
 505         } else /* The option is for other outputs */
 506                 limit = &intel_limits_i9xx_sdvo;
 507
 508         return limit;
 509 }
 510
 511 static const intel_limit_t *
 512 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 513 {
 514         struct drm_device *dev = crtc_state->base.crtc->dev;
 515         const intel_limit_t *limit;
 516
 517         if (IS_BROXTON(dev))
 518                 limit = &intel_limits_bxt;
 519         else if (HAS_PCH_SPLIT(dev))
 520                 limit = intel_ironlake_limit(crtc_state, refclk);
 521         else if (IS_G4X(dev)) {
 522                 limit = intel_g4x_limit(crtc_state);
 523         } else if (IS_PINEVIEW(dev)) {
 524                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 525                         limit = &intel_limits_pineview_lvds;
 526                 else
 527                         limit = &intel_limits_pineview_sdvo;
 528         } else if (IS_CHERRYVIEW(dev)) {
 529                 limit = &intel_limits_chv;
 530         } else if (IS_VALLEYVIEW(dev)) {
 531                 limit = &intel_limits_vlv;
 532         } else if (!IS_GEN2(dev)) {
 533                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 534                         limit = &intel_limits_i9xx_lvds;
 535                 else
 536                         limit = &intel_limits_i9xx_sdvo;
 537         } else {
 538                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 539                         limit = &intel_limits_i8xx_lvds;
 540                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 541                         limit = &intel_limits_i8xx_dvo;
 542                 else
 543                         limit = &intel_limits_i8xx_dac;
 544         }
 545         return limit;
 546 }
 547
 548 /*
 549  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 550  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 551  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 552  * The helpers' return value is the rate of the clock that is fed to the
 553  * display engine's pipe which can be the above fast dot clock rate or a
 554  * divided-down version of it.
 555  */
 556 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 557 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 558 {
 559         clock->m = clock->m2 + 2;
 560         clock->p = clock->p1 * clock->p2;
 561         if (WARN_ON(clock->n == 0 || clock->p == 0))
 562                 return 0;
 563         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 564         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 565
 566         return clock->dot;
 567 }
 568
 569 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 570 {
 571         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 572 }
 573
 574 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 575 {
 576         clock->m = i9xx_dpll_compute_m(clock);
 577         clock->p = clock->p1 * clock->p2;
 578         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 579                 return 0;
 580         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 581         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 582
 583         return clock->dot;
 584 }
 585
 586 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 587 {
 588         clock->m = clock->m1 * clock->m2;
 589         clock->p = clock->p1 * clock->p2;
 590         if (WARN_ON(clock->n == 0 || clock->p == 0))
 591                 return 0;
 592         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 593         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 594
 595         return clock->dot / 5;
 596 }
 597
 598 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 599 {
 600         clock->m = clock->m1 * clock->m2;
 601         clock->p = clock->p1 * clock->p2;
 602         if (WARN_ON(clock->n == 0 || clock->p == 0))
 603                 return 0;
 604         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 605                         clock->n << 22);
 606         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 607
 608         return clock->dot / 5;
 609 }
 610
 611 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 612 /**
 613  * Returns whether the given set of divisors are valid for a given refclk with
 614  * the given connectors.
 615  */
 616
 617 static bool intel_PLL_is_valid(struct drm_device *dev,
 618                                const intel_limit_t *limit,
 619                                const intel_clock_t *clock)
 620 {
 621         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 622                 INTELPllInvalid("n out of range\n");
 623         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 624                 INTELPllInvalid("p1 out of range\n");
 625         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 626                 INTELPllInvalid("m2 out of range\n");
 627         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 628                 INTELPllInvalid("m1 out of range\n");
 629
 630         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 631                 if (clock->m1 <= clock->m2)
 632                         INTELPllInvalid("m1 <= m2\n");
 633
 634         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 635                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 636                         INTELPllInvalid("p out of range\n");
 637                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 638                         INTELPllInvalid("m out of range\n");
 639         }
 640
 641         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 642                 INTELPllInvalid("vco out of range\n");
 643         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 644          * connector, etc., rather than just a single range.
 645          */
 646         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 647                 INTELPllInvalid("dot out of range\n");
 648
 649         return true;
 650 }
 651
 652 static int
 653 i9xx_select_p2_div(const intel_limit_t *limit,
 654                    const struct intel_crtc_state *crtc_state,
 655                    int target)
 656 {
 657         struct drm_device *dev = crtc_state->base.crtc->dev;
 658
 659         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 660                 /*
 661                  * For LVDS just rely on its current settings for dual-channel.
 662                  * We haven't figured out how to reliably set up different
 663                  * single/dual channel state, if we even can.
 664                  */
 665                 if (intel_is_dual_link_lvds(dev))
 666                         return limit->p2.p2_fast;
 667                 else
 668                         return limit->p2.p2_slow;
 669         } else {
 670                 if (target < limit->p2.dot_limit)
 671                         return limit->p2.p2_slow;
 672                 else
 673                         return limit->p2.p2_fast;
 674         }
 675 }
 676
 677 static bool
 678 i9xx_find_best_dpll(const intel_limit_t *limit,
 679                     struct intel_crtc_state *crtc_state,
 680                     int target, int refclk, intel_clock_t *match_clock,
 681                     intel_clock_t *best_clock)
 682 {
 683         struct drm_device *dev = crtc_state->base.crtc->dev;
 684         intel_clock_t clock;
 685         int err = target;
 686
 687         memset(best_clock, 0, sizeof(*best_clock));
 688
 689         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 690
 691         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 692              clock.m1++) {
 693                 for (clock.m2 = limit->m2.min;
 694                      clock.m2 <= limit->m2.max; clock.m2++) {
 695                         if (clock.m2 >= clock.m1)
 696                                 break;
 697                         for (clock.n = limit->n.min;
 698                              clock.n <= limit->n.max; clock.n++) {
 699                                 for (clock.p1 = limit->p1.min;
 700                                         clock.p1 <= limit->p1.max; clock.p1++) {
 701                                         int this_err;
 702
 703                                         i9xx_calc_dpll_params(refclk, &clock);
 704                                         if (!intel_PLL_is_valid(dev, limit,
 705                                                                 &clock))
 706                                                 continue;
 707                                         if (match_clock &&
 708                                             clock.p != match_clock->p)
 709                                                 continue;
 710
 711                                         this_err = abs(clock.dot - target);
 712                                         if (this_err < err) {
 713                                                 *best_clock = clock;
 714                                                 err = this_err;
 715                                         }
 716                                 }
 717                         }
 718                 }
 719         }
 720
 721         return (err != target);
 722 }
 723
 724 static bool
 725 pnv_find_best_dpll(const intel_limit_t *limit,
 726                    struct intel_crtc_state *crtc_state,
 727                    int target, int refclk, intel_clock_t *match_clock,
 728                    intel_clock_t *best_clock)
 729 {
 730         struct drm_device *dev = crtc_state->base.crtc->dev;
 731         intel_clock_t clock;
 732         int err = target;
 733
 734         memset(best_clock, 0, sizeof(*best_clock));
 735
 736         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 737
 738         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 739              clock.m1++) {
 740                 for (clock.m2 = limit->m2.min;
 741                      clock.m2 <= limit->m2.max; clock.m2++) {
 742                         for (clock.n = limit->n.min;
 743                              clock.n <= limit->n.max; clock.n++) {
 744                                 for (clock.p1 = limit->p1.min;
 745                                         clock.p1 <= limit->p1.max; clock.p1++) {
 746                                         int this_err;
 747
 748                                         pnv_calc_dpll_params(refclk, &clock);
 749                                         if (!intel_PLL_is_valid(dev, limit,
 750                                                                 &clock))
 751                                                 continue;
 752                                         if (match_clock &&
 753                                             clock.p != match_clock->p)
 754                                                 continue;
 755
 756                                         this_err = abs(clock.dot - target);
 757                                         if (this_err < err) {
 758                                                 *best_clock = clock;
 759                                                 err = this_err;
 760                                         }
 761                                 }
 762                         }
 763                 }
 764         }
 765
 766         return (err != target);
 767 }
 768
 769 static bool
 770 g4x_find_best_dpll(const intel_limit_t *limit,
 771                    struct intel_crtc_state *crtc_state,
 772                    int target, int refclk, intel_clock_t *match_clock,
 773                    intel_clock_t *best_clock)
 774 {
 775         struct drm_device *dev = crtc_state->base.crtc->dev;
 776         intel_clock_t clock;
 777         int max_n;
 778         bool found = false;
 779         /* approximately equals target * 0.00585 */
 780         int err_most = (target >> 8) + (target >> 9);
 781
 782         memset(best_clock, 0, sizeof(*best_clock));
 783
 784         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 785
 786         max_n = limit->n.max;
 787         /* based on hardware requirement, prefer smaller n to precision */
 788         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 789                 /* based on hardware requirement, prefere larger m1,m2 */
 790                 for (clock.m1 = limit->m1.max;
 791                      clock.m1 >= limit->m1.min; clock.m1--) {
 792                         for (clock.m2 = limit->m2.max;
 793                              clock.m2 >= limit->m2.min; clock.m2--) {
 794                                 for (clock.p1 = limit->p1.max;
 795                                      clock.p1 >= limit->p1.min; clock.p1--) {
 796                                         int this_err;
 797
 798                                         i9xx_calc_dpll_params(refclk, &clock);
 799                                         if (!intel_PLL_is_valid(dev, limit,
 800                                                                 &clock))
 801                                                 continue;
 802
 803                                         this_err = abs(clock.dot - target);
 804                                         if (this_err < err_most) {
 805                                                 *best_clock = clock;
 806                                                 err_most = this_err;
 807                                                 max_n = clock.n;
 808                                                 found = true;
 809                                         }
 810                                 }
 811                         }
 812                 }
 813         }
 814         return found;
 815 }
 816
 817 /*
 818  * Check if the calculated PLL configuration is more optimal compared to the
 819  * best configuration and error found so far. Return the calculated error.
 820  */
 821 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 822                                const intel_clock_t *calculated_clock,
 823                                const intel_clock_t *best_clock,
 824                                unsigned int best_error_ppm,
 825                                unsigned int *error_ppm)
 826 {
 827         /*
 828          * For CHV ignore the error and consider only the P value.
 829          * Prefer a bigger P value based on HW requirements.
 830          */
 831         if (IS_CHERRYVIEW(dev)) {
 832                 *error_ppm = 0;
 833
 834                 return calculated_clock->p > best_clock->p;
 835         }
 836
 837         if (WARN_ON_ONCE(!target_freq))
 838                 return false;
 839
 840         *error_ppm = div_u64(1000000ULL *
 841                                 abs(target_freq - calculated_clock->dot),
 842                              target_freq);
 843         /*
 844          * Prefer a better P value over a better (smaller) error if the error
 845          * is small. Ensure this preference for future configurations too by
 846          * setting the error to 0.
 847          */
 848         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 849                 *error_ppm = 0;
 850
 851                 return true;
 852         }
 853
 854         return *error_ppm + 10 < best_error_ppm;
 855 }
 856
 857 static bool
 858 vlv_find_best_dpll(const intel_limit_t *limit,
 859                    struct intel_crtc_state *crtc_state,
 860                    int target, int refclk, intel_clock_t *match_clock,
 861                    intel_clock_t *best_clock)
 862 {
 863         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 864         struct drm_device *dev = crtc->base.dev;
 865         intel_clock_t clock;
 866         unsigned int bestppm = 1000000;
 867         /* min update 19.2 MHz */
 868         int max_n = min(limit->n.max, refclk / 19200);
 869         bool found = false;
 870
 871         target *= 5; /* fast clock */
 872
 873         memset(best_clock, 0, sizeof(*best_clock));
 874
 875         /* based on hardware requirement, prefer smaller n to precision */
 876         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 877                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 878                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 879                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 880                                 clock.p = clock.p1 * clock.p2;
 881                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 882                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 883                                         unsigned int ppm;
 884
 885                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 886                                                                      refclk * clock.m1);
 887
 888                                         vlv_calc_dpll_params(refclk, &clock);
 889
 890                                         if (!intel_PLL_is_valid(dev, limit,
 891                                                                 &clock))
 892                                                 continue;
 893
 894                                         if (!vlv_PLL_is_optimal(dev, target,
 895                                                                 &clock,
 896                                                                 best_clock,
 897                                                                 bestppm, &ppm))
 898                                                 continue;
 899
 900                                         *best_clock = clock;
 901                                         bestppm = ppm;
 902                                         found = true;
 903                                 }
 904                         }
 905                 }
 906         }
 907
 908         return found;
 909 }
 910
 911 static bool
 912 chv_find_best_dpll(const intel_limit_t *limit,
 913                    struct intel_crtc_state *crtc_state,
 914                    int target, int refclk, intel_clock_t *match_clock,
 915                    intel_clock_t *best_clock)
 916 {
 917         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 918         struct drm_device *dev = crtc->base.dev;
 919         unsigned int best_error_ppm;
 920         intel_clock_t clock;
 921         uint64_t m2;
 922         int found = false;
 923
 924         memset(best_clock, 0, sizeof(*best_clock));
 925         best_error_ppm = 1000000;
 926
 927         /*
 928          * Based on hardware doc, the n always set to 1, and m1 always
 929          * set to 2.  If requires to support 200Mhz refclk, we need to
 930          * revisit this because n may not 1 anymore.
 931          */
 932         clock.n = 1, clock.m1 = 2;
 933         target *= 5;    /* fast clock */
 934
 935         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 936                 for (clock.p2 = limit->p2.p2_fast;
 937                                 clock.p2 >= limit->p2.p2_slow;
 938                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 939                         unsigned int error_ppm;
 940
 941                         clock.p = clock.p1 * clock.p2;
 942
 943                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 944                                         clock.n) << 22, refclk * clock.m1);
 945
 946                         if (m2 > INT_MAX/clock.m1)
 947                                 continue;
 948
 949                         clock.m2 = m2;
 950
 951                         chv_calc_dpll_params(refclk, &clock);
 952
 953                         if (!intel_PLL_is_valid(dev, limit, &clock))
 954                                 continue;
 955
 956                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 957                                                 best_error_ppm, &error_ppm))
 958                                 continue;
 959
 960                         *best_clock = clock;
 961                         best_error_ppm = error_ppm;
 962                         found = true;
 963                 }
 964         }
 965
 966         return found;
 967 }
 968
 969 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 970                         intel_clock_t *best_clock)
 971 {
 972         int refclk = i9xx_get_refclk(crtc_state, 0);
 973
 974         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
 975                                   target_clock, refclk, NULL, best_clock);
 976 }
 977
 978 bool intel_crtc_active(struct drm_crtc *crtc)
 979 {
 980         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 981
 982         /* Be paranoid as we can arrive here with only partial
 983          * state retrieved from the hardware during setup.
 984          *
 985          * We can ditch the adjusted_mode.crtc_clock check as soon
 986          * as Haswell has gained clock readout/fastboot support.
 987          *
 988          * We can ditch the crtc->primary->fb check as soon as we can
 989          * properly reconstruct framebuffers.
 990          *
 991          * FIXME: The intel_crtc->active here should be switched to
 992          * crtc->state->active once we have proper CRTC states wired up
 993          * for atomic.
 994          */
 995         return intel_crtc->active && crtc->primary->state->fb &&
 996                 intel_crtc->config->base.adjusted_mode.crtc_clock;
 997 }
 998
 999 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1000                                              enum pipe pipe)
1001 {
1002         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1003         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1004
1005         return intel_crtc->config->cpu_transcoder;
1006 }
1007
1008 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1009 {
1010         struct drm_i915_private *dev_priv = dev->dev_private;
1011         u32 reg = PIPEDSL(pipe);
1012         u32 line1, line2;
1013         u32 line_mask;
1014
1015         if (IS_GEN2(dev))
1016                 line_mask = DSL_LINEMASK_GEN2;
1017         else
1018                 line_mask = DSL_LINEMASK_GEN3;
1019
1020         line1 = I915_READ(reg) & line_mask;
1021         msleep(5);
1022         line2 = I915_READ(reg) & line_mask;
1023
1024         return line1 == line2;
1025 }
1026
1027 /*
1028  * intel_wait_for_pipe_off - wait for pipe to turn off
1029  * @crtc: crtc whose pipe to wait for
1030  *
1031  * After disabling a pipe, we can't wait for vblank in the usual way,
1032  * spinning on the vblank interrupt status bit, since we won't actually
1033  * see an interrupt when the pipe is disabled.
1034  *
1035  * On Gen4 and above:
1036  *   wait for the pipe register state bit to turn off
1037  *
1038  * Otherwise:
1039  *   wait for the display line value to settle (it usually
1040  *   ends up stopping at the start of the next frame).
1041  *
1042  */
1043 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1044 {
1045         struct drm_device *dev = crtc->base.dev;
1046         struct drm_i915_private *dev_priv = dev->dev_private;
1047         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1048         enum pipe pipe = crtc->pipe;
1049
1050         if (INTEL_INFO(dev)->gen >= 4) {
1051                 int reg = PIPECONF(cpu_transcoder);
1052
1053                 /* Wait for the Pipe State to go off */
1054                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1055                              100))
1056                         WARN(1, "pipe_off wait timed out\n");
1057         } else {
1058                 /* Wait for the display line to settle */
1059                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1060                         WARN(1, "pipe_off wait timed out\n");
1061         }
1062 }
1063
1064 /*
1065  * ibx_digital_port_connected - is the specified port connected?
1066  * @dev_priv: i915 private structure
1067  * @port: the port to test
1068  *
1069  * Returns true if @port is connected, false otherwise.
1070  */
1071 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1072                                 struct intel_digital_port *port)
1073 {
1074         u32 bit;
1075
1076         if (HAS_PCH_IBX(dev_priv->dev)) {
1077                 switch (port->port) {
1078                 case PORT_B:
1079                         bit = SDE_PORTB_HOTPLUG;
1080                         break;
1081                 case PORT_C:
1082                         bit = SDE_PORTC_HOTPLUG;
1083                         break;
1084                 case PORT_D:
1085                         bit = SDE_PORTD_HOTPLUG;
1086                         break;
1087                 default:
1088                         return true;
1089                 }
1090         } else {
1091                 switch (port->port) {
1092                 case PORT_B:
1093                         bit = SDE_PORTB_HOTPLUG_CPT;
1094                         break;
1095                 case PORT_C:
1096                         bit = SDE_PORTC_HOTPLUG_CPT;
1097                         break;
1098                 case PORT_D:
1099                         bit = SDE_PORTD_HOTPLUG_CPT;
1100                         break;
1101                 case PORT_E:
1102                         bit = SDE_PORTE_HOTPLUG_SPT;
1103                         break;
1104                 default:
1105                         return true;
1106                 }
1107         }
1108
1109         return I915_READ(SDEISR) & bit;
1110 }
1111
1112 static const char *state_string(bool enabled)
1113 {
1114         return enabled ? "on" : "off";
1115 }
1116
1117 /* Only for pre-ILK configs */
1118 void assert_pll(struct drm_i915_private *dev_priv,
1119                 enum pipe pipe, bool state)
1120 {
1121         int reg;
1122         u32 val;
1123         bool cur_state;
1124
1125         reg = DPLL(pipe);
1126         val = I915_READ(reg);
1127         cur_state = !!(val & DPLL_VCO_ENABLE);
1128         I915_STATE_WARN(cur_state != state,
1129              "PLL state assertion failure (expected %s, current %s)\n",
1130              state_string(state), state_string(cur_state));
1131 }
1132
1133 /* XXX: the dsi pll is shared between MIPI DSI ports */
1134 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1135 {
1136         u32 val;
1137         bool cur_state;
1138
1139         mutex_lock(&dev_priv->sb_lock);
1140         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1141         mutex_unlock(&dev_priv->sb_lock);
1142
1143         cur_state = val & DSI_PLL_VCO_EN;
1144         I915_STATE_WARN(cur_state != state,
1145              "DSI PLL state assertion failure (expected %s, current %s)\n",
1146              state_string(state), state_string(cur_state));
1147 }
1148 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1149 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1150
1151 struct intel_shared_dpll *
1152 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1153 {
1154         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1155
1156         if (crtc->config->shared_dpll < 0)
1157                 return NULL;
1158
1159         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1160 }
1161
1162 /* For ILK+ */
1163 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1164                         struct intel_shared_dpll *pll,
1165                         bool state)
1166 {
1167         bool cur_state;
1168         struct intel_dpll_hw_state hw_state;
1169
1170         if (WARN (!pll,
1171                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1172                 return;
1173
1174         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1175         I915_STATE_WARN(cur_state != state,
1176              "%s assertion failure (expected %s, current %s)\n",
1177              pll->name, state_string(state), state_string(cur_state));
1178 }
1179
1180 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1181                           enum pipe pipe, bool state)
1182 {
1183         int reg;
1184         u32 val;
1185         bool cur_state;
1186         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1187                                                                       pipe);
1188
1189         if (HAS_DDI(dev_priv->dev)) {
1190                 /* DDI does not have a specific FDI_TX register */
1191                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1192                 val = I915_READ(reg);
1193                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1194         } else {
1195                 reg = FDI_TX_CTL(pipe);
1196                 val = I915_READ(reg);
1197                 cur_state = !!(val & FDI_TX_ENABLE);
1198         }
1199         I915_STATE_WARN(cur_state != state,
1200              "FDI TX state assertion failure (expected %s, current %s)\n",
1201              state_string(state), state_string(cur_state));
1202 }
1203 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1204 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1205
1206 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1207                           enum pipe pipe, bool state)
1208 {
1209         int reg;
1210         u32 val;
1211         bool cur_state;
1212
1213         reg = FDI_RX_CTL(pipe);
1214         val = I915_READ(reg);
1215         cur_state = !!(val & FDI_RX_ENABLE);
1216         I915_STATE_WARN(cur_state != state,
1217              "FDI RX state assertion failure (expected %s, current %s)\n",
1218              state_string(state), state_string(cur_state));
1219 }
1220 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1221 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1222
1223 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1224                                       enum pipe pipe)
1225 {
1226         int reg;
1227         u32 val;
1228
1229         /* ILK FDI PLL is always enabled */
1230         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1231                 return;
1232
1233         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1234         if (HAS_DDI(dev_priv->dev))
1235                 return;
1236
1237         reg = FDI_TX_CTL(pipe);
1238         val = I915_READ(reg);
1239         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1240 }
1241
1242 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1243                        enum pipe pipe, bool state)
1244 {
1245         int reg;
1246         u32 val;
1247         bool cur_state;
1248
1249         reg = FDI_RX_CTL(pipe);
1250         val = I915_READ(reg);
1251         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1252         I915_STATE_WARN(cur_state != state,
1253              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1254              state_string(state), state_string(cur_state));
1255 }
1256
1257 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1258                            enum pipe pipe)
1259 {
1260         struct drm_device *dev = dev_priv->dev;
1261         int pp_reg;
1262         u32 val;
1263         enum pipe panel_pipe = PIPE_A;
1264         bool locked = true;
1265
1266         if (WARN_ON(HAS_DDI(dev)))
1267                 return;
1268
1269         if (HAS_PCH_SPLIT(dev)) {
1270                 u32 port_sel;
1271
1272                 pp_reg = PCH_PP_CONTROL;
1273                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1274
1275                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1276                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1277                         panel_pipe = PIPE_B;
1278                 /* XXX: else fix for eDP */
1279         } else if (IS_VALLEYVIEW(dev)) {
1280                 /* presumably write lock depends on pipe, not port select */
1281                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1282                 panel_pipe = pipe;
1283         } else {
1284                 pp_reg = PP_CONTROL;
1285                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1286                         panel_pipe = PIPE_B;
1287         }
1288
1289         val = I915_READ(pp_reg);
1290         if (!(val & PANEL_POWER_ON) ||
1291             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1292                 locked = false;
1293
1294         I915_STATE_WARN(panel_pipe == pipe && locked,
1295              "panel assertion failure, pipe %c regs locked\n",
1296              pipe_name(pipe));
1297 }
1298
1299 static void assert_cursor(struct drm_i915_private *dev_priv,
1300                           enum pipe pipe, bool state)
1301 {
1302         struct drm_device *dev = dev_priv->dev;
1303         bool cur_state;
1304
1305         if (IS_845G(dev) || IS_I865G(dev))
1306                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1307         else
1308                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1309
1310         I915_STATE_WARN(cur_state != state,
1311              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1312              pipe_name(pipe), state_string(state), state_string(cur_state));
1313 }
1314 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1315 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1316
1317 void assert_pipe(struct drm_i915_private *dev_priv,
1318                  enum pipe pipe, bool state)
1319 {
1320         int reg;
1321         u32 val;
1322         bool cur_state;
1323         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1324                                                                       pipe);
1325
1326         /* if we need the pipe quirk it must be always on */
1327         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1328             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1329                 state = true;
1330
1331         if (!intel_display_power_is_enabled(dev_priv,
1332                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1333                 cur_state = false;
1334         } else {
1335                 reg = PIPECONF(cpu_transcoder);
1336                 val = I915_READ(reg);
1337                 cur_state = !!(val & PIPECONF_ENABLE);
1338         }
1339
1340         I915_STATE_WARN(cur_state != state,
1341              "pipe %c assertion failure (expected %s, current %s)\n",
1342              pipe_name(pipe), state_string(state), state_string(cur_state));
1343 }
1344
1345 static void assert_plane(struct drm_i915_private *dev_priv,
1346                          enum plane plane, bool state)
1347 {
1348         int reg;
1349         u32 val;
1350         bool cur_state;
1351
1352         reg = DSPCNTR(plane);
1353         val = I915_READ(reg);
1354         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1355         I915_STATE_WARN(cur_state != state,
1356              "plane %c assertion failure (expected %s, current %s)\n",
1357              plane_name(plane), state_string(state), state_string(cur_state));
1358 }
1359
1360 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1361 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1362
1363 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1364                                    enum pipe pipe)
1365 {
1366         struct drm_device *dev = dev_priv->dev;
1367         int reg, i;
1368         u32 val;
1369         int cur_pipe;
1370
1371         /* Primary planes are fixed to pipes on gen4+ */
1372         if (INTEL_INFO(dev)->gen >= 4) {
1373                 reg = DSPCNTR(pipe);
1374                 val = I915_READ(reg);
1375                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1376                      "plane %c assertion failure, should be disabled but not\n",
1377                      plane_name(pipe));
1378                 return;
1379         }
1380
1381         /* Need to check both planes against the pipe */
1382         for_each_pipe(dev_priv, i) {
1383                 reg = DSPCNTR(i);
1384                 val = I915_READ(reg);
1385                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1386                         DISPPLANE_SEL_PIPE_SHIFT;
1387                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1388                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1389                      plane_name(i), pipe_name(pipe));
1390         }
1391 }
1392
1393 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1394                                     enum pipe pipe)
1395 {
1396         struct drm_device *dev = dev_priv->dev;
1397         int reg, sprite;
1398         u32 val;
1399
1400         if (INTEL_INFO(dev)->gen >= 9) {
1401                 for_each_sprite(dev_priv, pipe, sprite) {
1402                         val = I915_READ(PLANE_CTL(pipe, sprite));
1403                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1404                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1405                              sprite, pipe_name(pipe));
1406                 }
1407         } else if (IS_VALLEYVIEW(dev)) {
1408                 for_each_sprite(dev_priv, pipe, sprite) {
1409                         reg = SPCNTR(pipe, sprite);
1410                         val = I915_READ(reg);
1411                         I915_STATE_WARN(val & SP_ENABLE,
1412                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1413                              sprite_name(pipe, sprite), pipe_name(pipe));
1414                 }
1415         } else if (INTEL_INFO(dev)->gen >= 7) {
1416                 reg = SPRCTL(pipe);
1417                 val = I915_READ(reg);
1418                 I915_STATE_WARN(val & SPRITE_ENABLE,
1419                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1420                      plane_name(pipe), pipe_name(pipe));
1421         } else if (INTEL_INFO(dev)->gen >= 5) {
1422                 reg = DVSCNTR(pipe);
1423                 val = I915_READ(reg);
1424                 I915_STATE_WARN(val & DVS_ENABLE,
1425                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1426                      plane_name(pipe), pipe_name(pipe));
1427         }
1428 }
1429
1430 static void assert_vblank_disabled(struct drm_crtc *crtc)
1431 {
1432         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1433                 drm_crtc_vblank_put(crtc);
1434 }
1435
1436 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1437 {
1438         u32 val;
1439         bool enabled;
1440
1441         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1442
1443         val = I915_READ(PCH_DREF_CONTROL);
1444         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1445                             DREF_SUPERSPREAD_SOURCE_MASK));
1446         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1447 }
1448
1449 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1450                                            enum pipe pipe)
1451 {
1452         int reg;
1453         u32 val;
1454         bool enabled;
1455
1456         reg = PCH_TRANSCONF(pipe);
1457         val = I915_READ(reg);
1458         enabled = !!(val & TRANS_ENABLE);
1459         I915_STATE_WARN(enabled,
1460              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1461              pipe_name(pipe));
1462 }
1463
1464 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1465                             enum pipe pipe, u32 port_sel, u32 val)
1466 {
1467         if ((val & DP_PORT_EN) == 0)
1468                 return false;
1469
1470         if (HAS_PCH_CPT(dev_priv->dev)) {
1471                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1472                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1473                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1474                         return false;
1475         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1476                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1477                         return false;
1478         } else {
1479                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1480                         return false;
1481         }
1482         return true;
1483 }
1484
1485 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1486                               enum pipe pipe, u32 val)
1487 {
1488         if ((val & SDVO_ENABLE) == 0)
1489                 return false;
1490
1491         if (HAS_PCH_CPT(dev_priv->dev)) {
1492                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1493                         return false;
1494         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1495                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1496                         return false;
1497         } else {
1498                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1499                         return false;
1500         }
1501         return true;
1502 }
1503
1504 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1505                               enum pipe pipe, u32 val)
1506 {
1507         if ((val & LVDS_PORT_EN) == 0)
1508                 return false;
1509
1510         if (HAS_PCH_CPT(dev_priv->dev)) {
1511                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1512                         return false;
1513         } else {
1514                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1515                         return false;
1516         }
1517         return true;
1518 }
1519
1520 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1521                               enum pipe pipe, u32 val)
1522 {
1523         if ((val & ADPA_DAC_ENABLE) == 0)
1524                 return false;
1525         if (HAS_PCH_CPT(dev_priv->dev)) {
1526                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1527                         return false;
1528         } else {
1529                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1530                         return false;
1531         }
1532         return true;
1533 }
1534
1535 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1536                                    enum pipe pipe, int reg, u32 port_sel)
1537 {
1538         u32 val = I915_READ(reg);
1539         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1540              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1541              reg, pipe_name(pipe));
1542
1543         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1544              && (val & DP_PIPEB_SELECT),
1545              "IBX PCH dp port still using transcoder B\n");
1546 }
1547
1548 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1549                                      enum pipe pipe, int reg)
1550 {
1551         u32 val = I915_READ(reg);
1552         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1553              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1554              reg, pipe_name(pipe));
1555
1556         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1557              && (val & SDVO_PIPE_B_SELECT),
1558              "IBX PCH hdmi port still using transcoder B\n");
1559 }
1560
1561 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1562                                       enum pipe pipe)
1563 {
1564         int reg;
1565         u32 val;
1566
1567         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1568         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1569         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1570
1571         reg = PCH_ADPA;
1572         val = I915_READ(reg);
1573         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1574              "PCH VGA enabled on transcoder %c, should be disabled\n",
1575              pipe_name(pipe));
1576
1577         reg = PCH_LVDS;
1578         val = I915_READ(reg);
1579         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1580              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1581              pipe_name(pipe));
1582
1583         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1584         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1585         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1586 }
1587
1588 static void intel_init_dpio(struct drm_device *dev)
1589 {
1590         struct drm_i915_private *dev_priv = dev->dev_private;
1591
1592         if (!IS_VALLEYVIEW(dev))
1593                 return;
1594
1595         /*
1596          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1597          * CHV x1 PHY (DP/HDMI D)
1598          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1599          */
1600         if (IS_CHERRYVIEW(dev)) {
1601                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1602                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1603         } else {
1604                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1605         }
1606 }
1607
1608 static void vlv_enable_pll(struct intel_crtc *crtc,
1609                            const struct intel_crtc_state *pipe_config)
1610 {
1611         struct drm_device *dev = crtc->base.dev;
1612         struct drm_i915_private *dev_priv = dev->dev_private;
1613         int reg = DPLL(crtc->pipe);
1614         u32 dpll = pipe_config->dpll_hw_state.dpll;
1615
1616         assert_pipe_disabled(dev_priv, crtc->pipe);
1617
1618         /* No really, not for ILK+ */
1619         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1620
1621         /* PLL is protected by panel, make sure we can write it */
1622         if (IS_MOBILE(dev_priv->dev))
1623                 assert_panel_unlocked(dev_priv, crtc->pipe);
1624
1625         I915_WRITE(reg, dpll);
1626         POSTING_READ(reg);
1627         udelay(150);
1628
1629         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1630                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1631
1632         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1633         POSTING_READ(DPLL_MD(crtc->pipe));
1634
1635         /* We do this three times for luck */
1636         I915_WRITE(reg, dpll);
1637         POSTING_READ(reg);
1638         udelay(150); /* wait for warmup */
1639         I915_WRITE(reg, dpll);
1640         POSTING_READ(reg);
1641         udelay(150); /* wait for warmup */
1642         I915_WRITE(reg, dpll);
1643         POSTING_READ(reg);
1644         udelay(150); /* wait for warmup */
1645 }
1646
1647 static void chv_enable_pll(struct intel_crtc *crtc,
1648                            const struct intel_crtc_state *pipe_config)
1649 {
1650         struct drm_device *dev = crtc->base.dev;
1651         struct drm_i915_private *dev_priv = dev->dev_private;
1652         int pipe = crtc->pipe;
1653         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1654         u32 tmp;
1655
1656         assert_pipe_disabled(dev_priv, crtc->pipe);
1657
1658         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1659
1660         mutex_lock(&dev_priv->sb_lock);
1661
1662         /* Enable back the 10bit clock to display controller */
1663         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1664         tmp |= DPIO_DCLKP_EN;
1665         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1666
1667         mutex_unlock(&dev_priv->sb_lock);
1668
1669         /*
1670          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1671          */
1672         udelay(1);
1673
1674         /* Enable PLL */
1675         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1676
1677         /* Check PLL is locked */
1678         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1679                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1680
1681         /* not sure when this should be written */
1682         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1683         POSTING_READ(DPLL_MD(pipe));
1684 }
1685
1686 static int intel_num_dvo_pipes(struct drm_device *dev)
1687 {
1688         struct intel_crtc *crtc;
1689         int count = 0;
1690
1691         for_each_intel_crtc(dev, crtc)
1692                 count += crtc->base.state->active &&
1693                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1694
1695         return count;
1696 }
1697
1698 static void i9xx_enable_pll(struct intel_crtc *crtc)
1699 {
1700         struct drm_device *dev = crtc->base.dev;
1701         struct drm_i915_private *dev_priv = dev->dev_private;
1702         int reg = DPLL(crtc->pipe);
1703         u32 dpll = crtc->config->dpll_hw_state.dpll;
1704
1705         assert_pipe_disabled(dev_priv, crtc->pipe);
1706
1707         /* No really, not for ILK+ */
1708         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1709
1710         /* PLL is protected by panel, make sure we can write it */
1711         if (IS_MOBILE(dev) && !IS_I830(dev))
1712                 assert_panel_unlocked(dev_priv, crtc->pipe);
1713
1714         /* Enable DVO 2x clock on both PLLs if necessary */
1715         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1716                 /*
1717                  * It appears to be important that we don't enable this
1718                  * for the current pipe before otherwise configuring the
1719                  * PLL. No idea how this should be handled if multiple
1720                  * DVO outputs are enabled simultaneosly.
1721                  */
1722                 dpll |= DPLL_DVO_2X_MODE;
1723                 I915_WRITE(DPLL(!crtc->pipe),
1724                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1725         }
1726
1727         /*
1728          * Apparently we need to have VGA mode enabled prior to changing
1729          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1730          * dividers, even though the register value does change.
1731          */
1732         I915_WRITE(reg, 0);
1733
1734         I915_WRITE(reg, dpll);
1735
1736         /* Wait for the clocks to stabilize. */
1737         POSTING_READ(reg);
1738         udelay(150);
1739
1740         if (INTEL_INFO(dev)->gen >= 4) {
1741                 I915_WRITE(DPLL_MD(crtc->pipe),
1742                            crtc->config->dpll_hw_state.dpll_md);
1743         } else {
1744                 /* The pixel multiplier can only be updated once the
1745                  * DPLL is enabled and the clocks are stable.
1746                  *
1747                  * So write it again.
1748                  */
1749                 I915_WRITE(reg, dpll);
1750         }
1751
1752         /* We do this three times for luck */
1753         I915_WRITE(reg, dpll);
1754         POSTING_READ(reg);
1755         udelay(150); /* wait for warmup */
1756         I915_WRITE(reg, dpll);
1757         POSTING_READ(reg);
1758         udelay(150); /* wait for warmup */
1759         I915_WRITE(reg, dpll);
1760         POSTING_READ(reg);
1761         udelay(150); /* wait for warmup */
1762 }
1763
1764 /**
1765  * i9xx_disable_pll - disable a PLL
1766  * @dev_priv: i915 private structure
1767  * @pipe: pipe PLL to disable
1768  *
1769  * Disable the PLL for @pipe, making sure the pipe is off first.
1770  *
1771  * Note!  This is for pre-ILK only.
1772  */
1773 static void i9xx_disable_pll(struct intel_crtc *crtc)
1774 {
1775         struct drm_device *dev = crtc->base.dev;
1776         struct drm_i915_private *dev_priv = dev->dev_private;
1777         enum pipe pipe = crtc->pipe;
1778
1779         /* Disable DVO 2x clock on both PLLs if necessary */
1780         if (IS_I830(dev) &&
1781             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1782             !intel_num_dvo_pipes(dev)) {
1783                 I915_WRITE(DPLL(PIPE_B),
1784                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1785                 I915_WRITE(DPLL(PIPE_A),
1786                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1787         }
1788
1789         /* Don't disable pipe or pipe PLLs if needed */
1790         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1791             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1792                 return;
1793
1794         /* Make sure the pipe isn't still relying on us */
1795         assert_pipe_disabled(dev_priv, pipe);
1796
1797         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1798         POSTING_READ(DPLL(pipe));
1799 }
1800
1801 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1802 {
1803         u32 val;
1804
1805         /* Make sure the pipe isn't still relying on us */
1806         assert_pipe_disabled(dev_priv, pipe);
1807
1808         /*
1809          * Leave integrated clock source and reference clock enabled for pipe B.
1810          * The latter is needed for VGA hotplug / manual detection.
1811          */
1812         val = DPLL_VGA_MODE_DIS;
1813         if (pipe == PIPE_B)
1814                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1815         I915_WRITE(DPLL(pipe), val);
1816         POSTING_READ(DPLL(pipe));
1817
1818 }
1819
1820 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1821 {
1822         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1823         u32 val;
1824
1825         /* Make sure the pipe isn't still relying on us */
1826         assert_pipe_disabled(dev_priv, pipe);
1827
1828         /* Set PLL en = 0 */
1829         val = DPLL_SSC_REF_CLK_CHV |
1830                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1831         if (pipe != PIPE_A)
1832                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1833         I915_WRITE(DPLL(pipe), val);
1834         POSTING_READ(DPLL(pipe));
1835
1836         mutex_lock(&dev_priv->sb_lock);
1837
1838         /* Disable 10bit clock to display controller */
1839         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1840         val &= ~DPIO_DCLKP_EN;
1841         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1842
1843         /* disable left/right clock distribution */
1844         if (pipe != PIPE_B) {
1845                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1846                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1847                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1848         } else {
1849                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1850                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1851                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1852         }
1853
1854         mutex_unlock(&dev_priv->sb_lock);
1855 }
1856
1857 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1858                          struct intel_digital_port *dport,
1859                          unsigned int expected_mask)
1860 {
1861         u32 port_mask;
1862         int dpll_reg;
1863
1864         switch (dport->port) {
1865         case PORT_B:
1866                 port_mask = DPLL_PORTB_READY_MASK;
1867                 dpll_reg = DPLL(0);
1868                 break;
1869         case PORT_C:
1870                 port_mask = DPLL_PORTC_READY_MASK;
1871                 dpll_reg = DPLL(0);
1872                 expected_mask <<= 4;
1873                 break;
1874         case PORT_D:
1875                 port_mask = DPLL_PORTD_READY_MASK;
1876                 dpll_reg = DPIO_PHY_STATUS;
1877                 break;
1878         default:
1879                 BUG();
1880         }
1881
1882         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1883                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1884                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1885 }
1886
1887 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1888 {
1889         struct drm_device *dev = crtc->base.dev;
1890         struct drm_i915_private *dev_priv = dev->dev_private;
1891         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1892
1893         if (WARN_ON(pll == NULL))
1894                 return;
1895
1896         WARN_ON(!pll->config.crtc_mask);
1897         if (pll->active == 0) {
1898                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1899                 WARN_ON(pll->on);
1900                 assert_shared_dpll_disabled(dev_priv, pll);
1901
1902                 pll->mode_set(dev_priv, pll);
1903         }
1904 }
1905
1906 /**
1907  * intel_enable_shared_dpll - enable PCH PLL
1908  * @dev_priv: i915 private structure
1909  * @pipe: pipe PLL to enable
1910  *
1911  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1912  * drives the transcoder clock.
1913  */
1914 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1915 {
1916         struct drm_device *dev = crtc->base.dev;
1917         struct drm_i915_private *dev_priv = dev->dev_private;
1918         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1919
1920         if (WARN_ON(pll == NULL))
1921                 return;
1922
1923         if (WARN_ON(pll->config.crtc_mask == 0))
1924                 return;
1925
1926         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1927                       pll->name, pll->active, pll->on,
1928                       crtc->base.base.id);
1929
1930         if (pll->active++) {
1931                 WARN_ON(!pll->on);
1932                 assert_shared_dpll_enabled(dev_priv, pll);
1933                 return;
1934         }
1935         WARN_ON(pll->on);
1936
1937         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1938
1939         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1940         pll->enable(dev_priv, pll);
1941         pll->on = true;
1942 }
1943
1944 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1945 {
1946         struct drm_device *dev = crtc->base.dev;
1947         struct drm_i915_private *dev_priv = dev->dev_private;
1948         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1949
1950         /* PCH only available on ILK+ */
1951         if (INTEL_INFO(dev)->gen < 5)
1952                 return;
1953
1954         if (pll == NULL)
1955                 return;
1956
1957         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1958                 return;
1959
1960         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1961                       pll->name, pll->active, pll->on,
1962                       crtc->base.base.id);
1963
1964         if (WARN_ON(pll->active == 0)) {
1965                 assert_shared_dpll_disabled(dev_priv, pll);
1966                 return;
1967         }
1968
1969         assert_shared_dpll_enabled(dev_priv, pll);
1970         WARN_ON(!pll->on);
1971         if (--pll->active)
1972                 return;
1973
1974         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1975         pll->disable(dev_priv, pll);
1976         pll->on = false;
1977
1978         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1979 }
1980
1981 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1982                                            enum pipe pipe)
1983 {
1984         struct drm_device *dev = dev_priv->dev;
1985         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1986         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1987         uint32_t reg, val, pipeconf_val;
1988
1989         /* PCH only available on ILK+ */
1990         BUG_ON(!HAS_PCH_SPLIT(dev));
1991
1992         /* Make sure PCH DPLL is enabled */
1993         assert_shared_dpll_enabled(dev_priv,
1994                                    intel_crtc_to_shared_dpll(intel_crtc));
1995
1996         /* FDI must be feeding us bits for PCH ports */
1997         assert_fdi_tx_enabled(dev_priv, pipe);
1998         assert_fdi_rx_enabled(dev_priv, pipe);
1999
2000         if (HAS_PCH_CPT(dev)) {
2001                 /* Workaround: Set the timing override bit before enabling the
2002                  * pch transcoder. */
2003                 reg = TRANS_CHICKEN2(pipe);
2004                 val = I915_READ(reg);
2005                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2006                 I915_WRITE(reg, val);
2007         }
2008
2009         reg = PCH_TRANSCONF(pipe);
2010         val = I915_READ(reg);
2011         pipeconf_val = I915_READ(PIPECONF(pipe));
2012
2013         if (HAS_PCH_IBX(dev_priv->dev)) {
2014                 /*
2015                  * Make the BPC in transcoder be consistent with
2016                  * that in pipeconf reg. For HDMI we must use 8bpc
2017                  * here for both 8bpc and 12bpc.
2018                  */
2019                 val &= ~PIPECONF_BPC_MASK;
2020                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2021                         val |= PIPECONF_8BPC;
2022                 else
2023                         val |= pipeconf_val & PIPECONF_BPC_MASK;
2024         }
2025
2026         val &= ~TRANS_INTERLACE_MASK;
2027         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2028                 if (HAS_PCH_IBX(dev_priv->dev) &&
2029                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2030                         val |= TRANS_LEGACY_INTERLACED_ILK;
2031                 else
2032                         val |= TRANS_INTERLACED;
2033         else
2034                 val |= TRANS_PROGRESSIVE;
2035
2036         I915_WRITE(reg, val | TRANS_ENABLE);
2037         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2038                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2039 }
2040
2041 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2042                                       enum transcoder cpu_transcoder)
2043 {
2044         u32 val, pipeconf_val;
2045
2046         /* PCH only available on ILK+ */
2047         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2048
2049         /* FDI must be feeding us bits for PCH ports */
2050         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2051         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2052
2053         /* Workaround: set timing override bit. */
2054         val = I915_READ(_TRANSA_CHICKEN2);
2055         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2056         I915_WRITE(_TRANSA_CHICKEN2, val);
2057
2058         val = TRANS_ENABLE;
2059         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2060
2061         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2062             PIPECONF_INTERLACED_ILK)
2063                 val |= TRANS_INTERLACED;
2064         else
2065                 val |= TRANS_PROGRESSIVE;
2066
2067         I915_WRITE(LPT_TRANSCONF, val);
2068         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2069                 DRM_ERROR("Failed to enable PCH transcoder\n");
2070 }
2071
2072 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2073                                             enum pipe pipe)
2074 {
2075         struct drm_device *dev = dev_priv->dev;
2076         uint32_t reg, val;
2077
2078         /* FDI relies on the transcoder */
2079         assert_fdi_tx_disabled(dev_priv, pipe);
2080         assert_fdi_rx_disabled(dev_priv, pipe);
2081
2082         /* Ports must be off as well */
2083         assert_pch_ports_disabled(dev_priv, pipe);
2084
2085         reg = PCH_TRANSCONF(pipe);
2086         val = I915_READ(reg);
2087         val &= ~TRANS_ENABLE;
2088         I915_WRITE(reg, val);
2089         /* wait for PCH transcoder off, transcoder state */
2090         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2091                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2092
2093         if (!HAS_PCH_IBX(dev)) {
2094                 /* Workaround: Clear the timing override chicken bit again. */
2095                 reg = TRANS_CHICKEN2(pipe);
2096                 val = I915_READ(reg);
2097                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2098                 I915_WRITE(reg, val);
2099         }
2100 }
2101
2102 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2103 {
2104         u32 val;
2105
2106         val = I915_READ(LPT_TRANSCONF);
2107         val &= ~TRANS_ENABLE;
2108         I915_WRITE(LPT_TRANSCONF, val);
2109         /* wait for PCH transcoder off, transcoder state */
2110         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2111                 DRM_ERROR("Failed to disable PCH transcoder\n");
2112
2113         /* Workaround: clear timing override bit. */
2114         val = I915_READ(_TRANSA_CHICKEN2);
2115         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2116         I915_WRITE(_TRANSA_CHICKEN2, val);
2117 }
2118
2119 /**
2120  * intel_enable_pipe - enable a pipe, asserting requirements
2121  * @crtc: crtc responsible for the pipe
2122  *
2123  * Enable @crtc's pipe, making sure that various hardware specific requirements
2124  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2125  */
2126 static void intel_enable_pipe(struct intel_crtc *crtc)
2127 {
2128         struct drm_device *dev = crtc->base.dev;
2129         struct drm_i915_private *dev_priv = dev->dev_private;
2130         enum pipe pipe = crtc->pipe;
2131         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2132                                                                       pipe);
2133         enum pipe pch_transcoder;
2134         int reg;
2135         u32 val;
2136
2137         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2138
2139         assert_planes_disabled(dev_priv, pipe);
2140         assert_cursor_disabled(dev_priv, pipe);
2141         assert_sprites_disabled(dev_priv, pipe);
2142
2143         if (HAS_PCH_LPT(dev_priv->dev))
2144                 pch_transcoder = TRANSCODER_A;
2145         else
2146                 pch_transcoder = pipe;
2147
2148         /*
2149          * A pipe without a PLL won't actually be able to drive bits from
2150          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2151          * need the check.
2152          */
2153         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2154                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2155                         assert_dsi_pll_enabled(dev_priv);
2156                 else
2157                         assert_pll_enabled(dev_priv, pipe);
2158         else {
2159                 if (crtc->config->has_pch_encoder) {
2160                         /* if driving the PCH, we need FDI enabled */
2161                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2162                         assert_fdi_tx_pll_enabled(dev_priv,
2163                                                   (enum pipe) cpu_transcoder);
2164                 }
2165                 /* FIXME: assert CPU port conditions for SNB+ */
2166         }
2167
2168         reg = PIPECONF(cpu_transcoder);
2169         val = I915_READ(reg);
2170         if (val & PIPECONF_ENABLE) {
2171                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2172                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2173                 return;
2174         }
2175
2176         I915_WRITE(reg, val | PIPECONF_ENABLE);
2177         POSTING_READ(reg);
2178 }
2179
2180 /**
2181  * intel_disable_pipe - disable a pipe, asserting requirements
2182  * @crtc: crtc whose pipes is to be disabled
2183  *
2184  * Disable the pipe of @crtc, making sure that various hardware
2185  * specific requirements are met, if applicable, e.g. plane
2186  * disabled, panel fitter off, etc.
2187  *
2188  * Will wait until the pipe has shut down before returning.
2189  */
2190 static void intel_disable_pipe(struct intel_crtc *crtc)
2191 {
2192         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2193         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2194         enum pipe pipe = crtc->pipe;
2195         int reg;
2196         u32 val;
2197
2198         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2199
2200         /*
2201          * Make sure planes won't keep trying to pump pixels to us,
2202          * or we might hang the display.
2203          */
2204         assert_planes_disabled(dev_priv, pipe);
2205         assert_cursor_disabled(dev_priv, pipe);
2206         assert_sprites_disabled(dev_priv, pipe);
2207
2208         reg = PIPECONF(cpu_transcoder);
2209         val = I915_READ(reg);
2210         if ((val & PIPECONF_ENABLE) == 0)
2211                 return;
2212
2213         /*
2214          * Double wide has implications for planes
2215          * so best keep it disabled when not needed.
2216          */
2217         if (crtc->config->double_wide)
2218                 val &= ~PIPECONF_DOUBLE_WIDE;
2219
2220         /* Don't disable pipe or pipe PLLs if needed */
2221         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2222             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2223                 val &= ~PIPECONF_ENABLE;
2224
2225         I915_WRITE(reg, val);
2226         if ((val & PIPECONF_ENABLE) == 0)
2227                 intel_wait_for_pipe_off(crtc);
2228 }
2229
2230 static bool need_vtd_wa(struct drm_device *dev)
2231 {
2232 #ifdef CONFIG_INTEL_IOMMU
2233         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2234                 return true;
2235 #endif
2236         return false;
2237 }
2238
2239 unsigned int
2240 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2241                   uint64_t fb_format_modifier)
2242 {
2243         unsigned int tile_height;
2244         uint32_t pixel_bytes;
2245
2246         switch (fb_format_modifier) {
2247         case DRM_FORMAT_MOD_NONE:
2248                 tile_height = 1;
2249                 break;
2250         case I915_FORMAT_MOD_X_TILED:
2251                 tile_height = IS_GEN2(dev) ? 16 : 8;
2252                 break;
2253         case I915_FORMAT_MOD_Y_TILED:
2254                 tile_height = 32;
2255                 break;
2256         case I915_FORMAT_MOD_Yf_TILED:
2257                 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2258                 switch (pixel_bytes) {
2259                 default:
2260                 case 1:
2261                         tile_height = 64;
2262                         break;
2263                 case 2:
2264                 case 4:
2265                         tile_height = 32;
2266                         break;
2267                 case 8:
2268                         tile_height = 16;
2269                         break;
2270                 case 16:
2271                         WARN_ONCE(1,
2272                                   "128-bit pixels are not supported for display!");
2273                         tile_height = 16;
2274                         break;
2275                 }
2276                 break;
2277         default:
2278                 MISSING_CASE(fb_format_modifier);
2279                 tile_height = 1;
2280                 break;
2281         }
2282
2283         return tile_height;
2284 }
2285
2286 unsigned int
2287 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2288                       uint32_t pixel_format, uint64_t fb_format_modifier)
2289 {
2290         return ALIGN(height, intel_tile_height(dev, pixel_format,
2291                                                fb_format_modifier));
2292 }
2293
2294 static int
2295 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2296                         const struct drm_plane_state *plane_state)
2297 {
2298         struct intel_rotation_info *info = &view->rotation_info;
2299         unsigned int tile_height, tile_pitch;
2300
2301         *view = i915_ggtt_view_normal;
2302
2303         if (!plane_state)
2304                 return 0;
2305
2306         if (!intel_rotation_90_or_270(plane_state->rotation))
2307                 return 0;
2308
2309         *view = i915_ggtt_view_rotated;
2310
2311         info->height = fb->height;
2312         info->pixel_format = fb->pixel_format;
2313         info->pitch = fb->pitches[0];
2314         info->fb_modifier = fb->modifier[0];
2315
2316         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2317                                         fb->modifier[0]);
2318         tile_pitch = PAGE_SIZE / tile_height;
2319         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2320         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2321         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2322
2323         return 0;
2324 }
2325
2326 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2327 {
2328         if (INTEL_INFO(dev_priv)->gen >= 9)
2329                 return 256 * 1024;
2330         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2331                  IS_VALLEYVIEW(dev_priv))
2332                 return 128 * 1024;
2333         else if (INTEL_INFO(dev_priv)->gen >= 4)
2334                 return 4 * 1024;
2335         else
2336                 return 0;
2337 }
2338
2339 int
2340 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2341                            struct drm_framebuffer *fb,
2342                            const struct drm_plane_state *plane_state,
2343                            struct intel_engine_cs *pipelined,
2344                            struct drm_i915_gem_request **pipelined_request)
2345 {
2346         struct drm_device *dev = fb->dev;
2347         struct drm_i915_private *dev_priv = dev->dev_private;
2348         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2349         struct i915_ggtt_view view;
2350         u32 alignment;
2351         int ret;
2352
2353         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2354
2355         switch (fb->modifier[0]) {
2356         case DRM_FORMAT_MOD_NONE:
2357                 alignment = intel_linear_alignment(dev_priv);
2358                 break;
2359         case I915_FORMAT_MOD_X_TILED:
2360                 if (INTEL_INFO(dev)->gen >= 9)
2361                         alignment = 256 * 1024;
2362                 else {
2363                         /* pin() will align the object as required by fence */
2364                         alignment = 0;
2365                 }
2366                 break;
2367         case I915_FORMAT_MOD_Y_TILED:
2368         case I915_FORMAT_MOD_Yf_TILED:
2369                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2370                           "Y tiling bo slipped through, driver bug!\n"))
2371                         return -EINVAL;
2372                 alignment = 1 * 1024 * 1024;
2373                 break;
2374         default:
2375                 MISSING_CASE(fb->modifier[0]);
2376                 return -EINVAL;
2377         }
2378
2379         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2380         if (ret)
2381                 return ret;
2382
2383         /* Note that the w/a also requires 64 PTE of padding following the
2384          * bo. We currently fill all unused PTE with the shadow page and so
2385          * we should always have valid PTE following the scanout preventing
2386          * the VT-d warning.
2387          */
2388         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2389                 alignment = 256 * 1024;
2390
2391         /*
2392          * Global gtt pte registers are special registers which actually forward
2393          * writes to a chunk of system memory. Which means that there is no risk
2394          * that the register values disappear as soon as we call
2395          * intel_runtime_pm_put(), so it is correct to wrap only the
2396          * pin/unpin/fence and not more.
2397          */
2398         intel_runtime_pm_get(dev_priv);
2399
2400         dev_priv->mm.interruptible = false;
2401         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2402                                                    pipelined_request, &view);
2403         if (ret)
2404                 goto err_interruptible;
2405
2406         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2407          * fence, whereas 965+ only requires a fence if using
2408          * framebuffer compression.  For simplicity, we always install
2409          * a fence as the cost is not that onerous.
2410          */
2411         ret = i915_gem_object_get_fence(obj);
2412         if (ret == -EDEADLK) {
2413                 /*
2414                  * -EDEADLK means there are no free fences
2415                  * no pending flips.
2416                  *
2417                  * This is propagated to atomic, but it uses
2418                  * -EDEADLK to force a locking recovery, so
2419                  * change the returned error to -EBUSY.
2420                  */
2421                 ret = -EBUSY;
2422                 goto err_unpin;
2423         } else if (ret)
2424                 goto err_unpin;
2425
2426         i915_gem_object_pin_fence(obj);
2427
2428         dev_priv->mm.interruptible = true;
2429         intel_runtime_pm_put(dev_priv);
2430         return 0;
2431
2432 err_unpin:
2433         i915_gem_object_unpin_from_display_plane(obj, &view);
2434 err_interruptible:
2435         dev_priv->mm.interruptible = true;
2436         intel_runtime_pm_put(dev_priv);
2437         return ret;
2438 }
2439
2440 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2441                                const struct drm_plane_state *plane_state)
2442 {
2443         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2444         struct i915_ggtt_view view;
2445         int ret;
2446
2447         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2448
2449         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2450         WARN_ONCE(ret, "Couldn't get view from plane state!");
2451
2452         i915_gem_object_unpin_fence(obj);
2453         i915_gem_object_unpin_from_display_plane(obj, &view);
2454 }
2455
2456 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2457  * is assumed to be a power-of-two. */
2458 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2459                                              int *x, int *y,
2460                                              unsigned int tiling_mode,
2461                                              unsigned int cpp,
2462                                              unsigned int pitch)
2463 {
2464         if (tiling_mode != I915_TILING_NONE) {
2465                 unsigned int tile_rows, tiles;
2466
2467                 tile_rows = *y / 8;
2468                 *y %= 8;
2469
2470                 tiles = *x / (512/cpp);
2471                 *x %= 512/cpp;
2472
2473                 return tile_rows * pitch * 8 + tiles * 4096;
2474         } else {
2475                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2476                 unsigned int offset;
2477
2478                 offset = *y * pitch + *x * cpp;
2479                 *y = (offset & alignment) / pitch;
2480                 *x = ((offset & alignment) - *y * pitch) / cpp;
2481                 return offset & ~alignment;
2482         }
2483 }
2484
2485 static int i9xx_format_to_fourcc(int format)
2486 {
2487         switch (format) {
2488         case DISPPLANE_8BPP:
2489                 return DRM_FORMAT_C8;
2490         case DISPPLANE_BGRX555:
2491                 return DRM_FORMAT_XRGB1555;
2492         case DISPPLANE_BGRX565:
2493                 return DRM_FORMAT_RGB565;
2494         default:
2495         case DISPPLANE_BGRX888:
2496                 return DRM_FORMAT_XRGB8888;
2497         case DISPPLANE_RGBX888:
2498                 return DRM_FORMAT_XBGR8888;
2499         case DISPPLANE_BGRX101010:
2500                 return DRM_FORMAT_XRGB2101010;
2501         case DISPPLANE_RGBX101010:
2502                 return DRM_FORMAT_XBGR2101010;
2503         }
2504 }
2505
2506 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2507 {
2508         switch (format) {
2509         case PLANE_CTL_FORMAT_RGB_565:
2510                 return DRM_FORMAT_RGB565;
2511         default:
2512         case PLANE_CTL_FORMAT_XRGB_8888:
2513                 if (rgb_order) {
2514                         if (alpha)
2515                                 return DRM_FORMAT_ABGR8888;
2516                         else
2517                                 return DRM_FORMAT_XBGR8888;
2518                 } else {
2519                         if (alpha)
2520                                 return DRM_FORMAT_ARGB8888;
2521                         else
2522                                 return DRM_FORMAT_XRGB8888;
2523                 }
2524         case PLANE_CTL_FORMAT_XRGB_2101010:
2525                 if (rgb_order)
2526                         return DRM_FORMAT_XBGR2101010;
2527                 else
2528                         return DRM_FORMAT_XRGB2101010;
2529         }
2530 }
2531
2532 static bool
2533 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2534                               struct intel_initial_plane_config *plane_config)
2535 {
2536         struct drm_device *dev = crtc->base.dev;
2537         struct drm_i915_gem_object *obj = NULL;
2538         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2539         struct drm_framebuffer *fb = &plane_config->fb->base;
2540         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2541         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2542                                     PAGE_SIZE);
2543
2544         size_aligned -= base_aligned;
2545
2546         if (plane_config->size == 0)
2547                 return false;
2548
2549         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2550                                                              base_aligned,
2551                                                              base_aligned,
2552                                                              size_aligned);
2553         if (!obj)
2554                 return false;
2555
2556         obj->tiling_mode = plane_config->tiling;
2557         if (obj->tiling_mode == I915_TILING_X)
2558                 obj->stride = fb->pitches[0];
2559
2560         mode_cmd.pixel_format = fb->pixel_format;
2561         mode_cmd.width = fb->width;
2562         mode_cmd.height = fb->height;
2563         mode_cmd.pitches[0] = fb->pitches[0];
2564         mode_cmd.modifier[0] = fb->modifier[0];
2565         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2566
2567         mutex_lock(&dev->struct_mutex);
2568         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2569                                    &mode_cmd, obj)) {
2570                 DRM_DEBUG_KMS("intel fb init failed\n");
2571                 goto out_unref_obj;
2572         }
2573         mutex_unlock(&dev->struct_mutex);
2574
2575         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2576         return true;
2577
2578 out_unref_obj:
2579         drm_gem_object_unreference(&obj->base);
2580         mutex_unlock(&dev->struct_mutex);
2581         return false;
2582 }
2583
2584 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2585 static void
2586 update_state_fb(struct drm_plane *plane)
2587 {
2588         if (plane->fb == plane->state->fb)
2589                 return;
2590
2591         if (plane->state->fb)
2592                 drm_framebuffer_unreference(plane->state->fb);
2593         plane->state->fb = plane->fb;
2594         if (plane->state->fb)
2595                 drm_framebuffer_reference(plane->state->fb);
2596 }
2597
2598 static void
2599 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2600                              struct intel_initial_plane_config *plane_config)
2601 {
2602         struct drm_device *dev = intel_crtc->base.dev;
2603         struct drm_i915_private *dev_priv = dev->dev_private;
2604         struct drm_crtc *c;
2605         struct intel_crtc *i;
2606         struct drm_i915_gem_object *obj;
2607         struct drm_plane *primary = intel_crtc->base.primary;
2608         struct drm_plane_state *plane_state = primary->state;
2609         struct drm_framebuffer *fb;
2610
2611         if (!plane_config->fb)
2612                 return;
2613
2614         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2615                 fb = &plane_config->fb->base;
2616                 goto valid_fb;
2617         }
2618
2619         kfree(plane_config->fb);
2620
2621         /*
2622          * Failed to alloc the obj, check to see if we should share
2623          * an fb with another CRTC instead
2624          */
2625         for_each_crtc(dev, c) {
2626                 i = to_intel_crtc(c);
2627
2628                 if (c == &intel_crtc->base)
2629                         continue;
2630
2631                 if (!i->active)
2632                         continue;
2633
2634                 fb = c->primary->fb;
2635                 if (!fb)
2636                         continue;
2637
2638                 obj = intel_fb_obj(fb);
2639                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2640                         drm_framebuffer_reference(fb);
2641                         goto valid_fb;
2642                 }
2643         }
2644
2645         return;
2646
2647 valid_fb:
2648         plane_state->src_x = plane_state->src_y = 0;
2649         plane_state->src_w = fb->width << 16;
2650         plane_state->src_h = fb->height << 16;
2651
2652         plane_state->crtc_x = plane_state->src_y = 0;
2653         plane_state->crtc_w = fb->width;
2654         plane_state->crtc_h = fb->height;
2655
2656         obj = intel_fb_obj(fb);
2657         if (obj->tiling_mode != I915_TILING_NONE)
2658                 dev_priv->preserve_bios_swizzle = true;
2659
2660         drm_framebuffer_reference(fb);
2661         primary->fb = primary->state->fb = fb;
2662         primary->crtc = primary->state->crtc = &intel_crtc->base;
2663         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2664         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2665 }
2666
2667 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2668                                       struct drm_framebuffer *fb,
2669                                       int x, int y)
2670 {
2671         struct drm_device *dev = crtc->dev;
2672         struct drm_i915_private *dev_priv = dev->dev_private;
2673         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2674         struct drm_plane *primary = crtc->primary;
2675         bool visible = to_intel_plane_state(primary->state)->visible;
2676         struct drm_i915_gem_object *obj;
2677         int plane = intel_crtc->plane;
2678         unsigned long linear_offset;
2679         u32 dspcntr;
2680         u32 reg = DSPCNTR(plane);
2681         int pixel_size;
2682
2683         if (!visible || !fb) {
2684                 I915_WRITE(reg, 0);
2685                 if (INTEL_INFO(dev)->gen >= 4)
2686                         I915_WRITE(DSPSURF(plane), 0);
2687                 else
2688                         I915_WRITE(DSPADDR(plane), 0);
2689                 POSTING_READ(reg);
2690                 return;
2691         }
2692
2693         obj = intel_fb_obj(fb);
2694         if (WARN_ON(obj == NULL))
2695                 return;
2696
2697         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2698
2699         dspcntr = DISPPLANE_GAMMA_ENABLE;
2700
2701         dspcntr |= DISPLAY_PLANE_ENABLE;
2702
2703         if (INTEL_INFO(dev)->gen < 4) {
2704                 if (intel_crtc->pipe == PIPE_B)
2705                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2706
2707                 /* pipesrc and dspsize control the size that is scaled from,
2708                  * which should always be the user's requested size.
2709                  */
2710                 I915_WRITE(DSPSIZE(plane),
2711                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2712                            (intel_crtc->config->pipe_src_w - 1));
2713                 I915_WRITE(DSPPOS(plane), 0);
2714         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2715                 I915_WRITE(PRIMSIZE(plane),
2716                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2717                            (intel_crtc->config->pipe_src_w - 1));
2718                 I915_WRITE(PRIMPOS(plane), 0);
2719                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2720         }
2721
2722         switch (fb->pixel_format) {
2723         case DRM_FORMAT_C8:
2724                 dspcntr |= DISPPLANE_8BPP;
2725                 break;
2726         case DRM_FORMAT_XRGB1555:
2727                 dspcntr |= DISPPLANE_BGRX555;
2728                 break;
2729         case DRM_FORMAT_RGB565:
2730                 dspcntr |= DISPPLANE_BGRX565;
2731                 break;
2732         case DRM_FORMAT_XRGB8888:
2733                 dspcntr |= DISPPLANE_BGRX888;
2734                 break;
2735         case DRM_FORMAT_XBGR8888:
2736                 dspcntr |= DISPPLANE_RGBX888;
2737                 break;
2738         case DRM_FORMAT_XRGB2101010:
2739                 dspcntr |= DISPPLANE_BGRX101010;
2740                 break;
2741         case DRM_FORMAT_XBGR2101010:
2742                 dspcntr |= DISPPLANE_RGBX101010;
2743                 break;
2744         default:
2745                 BUG();
2746         }
2747
2748         if (INTEL_INFO(dev)->gen >= 4 &&
2749             obj->tiling_mode != I915_TILING_NONE)
2750                 dspcntr |= DISPPLANE_TILED;
2751
2752         if (IS_G4X(dev))
2753                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2754
2755         linear_offset = y * fb->pitches[0] + x * pixel_size;
2756
2757         if (INTEL_INFO(dev)->gen >= 4) {
2758                 intel_crtc->dspaddr_offset =
2759                         intel_gen4_compute_page_offset(dev_priv,
2760                                                        &x, &y, obj->tiling_mode,
2761                                                        pixel_size,
2762                                                        fb->pitches[0]);
2763                 linear_offset -= intel_crtc->dspaddr_offset;
2764         } else {
2765                 intel_crtc->dspaddr_offset = linear_offset;
2766         }
2767
2768         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2769                 dspcntr |= DISPPLANE_ROTATE_180;
2770
2771                 x += (intel_crtc->config->pipe_src_w - 1);
2772                 y += (intel_crtc->config->pipe_src_h - 1);
2773
2774                 /* Finding the last pixel of the last line of the display
2775                 data and adding to linear_offset*/
2776                 linear_offset +=
2777                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2778                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2779         }
2780
2781         I915_WRITE(reg, dspcntr);
2782
2783         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2784         if (INTEL_INFO(dev)->gen >= 4) {
2785                 I915_WRITE(DSPSURF(plane),
2786                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2787                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2788                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2789         } else
2790                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2791         POSTING_READ(reg);
2792 }
2793
2794 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2795                                           struct drm_framebuffer *fb,
2796                                           int x, int y)
2797 {
2798         struct drm_device *dev = crtc->dev;
2799         struct drm_i915_private *dev_priv = dev->dev_private;
2800         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2801         struct drm_plane *primary = crtc->primary;
2802         bool visible = to_intel_plane_state(primary->state)->visible;
2803         struct drm_i915_gem_object *obj;
2804         int plane = intel_crtc->plane;
2805         unsigned long linear_offset;
2806         u32 dspcntr;
2807         u32 reg = DSPCNTR(plane);
2808         int pixel_size;
2809
2810         if (!visible || !fb) {
2811                 I915_WRITE(reg, 0);
2812                 I915_WRITE(DSPSURF(plane), 0);
2813                 POSTING_READ(reg);
2814                 return;
2815         }
2816
2817         obj = intel_fb_obj(fb);
2818         if (WARN_ON(obj == NULL))
2819                 return;
2820
2821         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2822
2823         dspcntr = DISPPLANE_GAMMA_ENABLE;
2824
2825         dspcntr |= DISPLAY_PLANE_ENABLE;
2826
2827         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2828                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2829
2830         switch (fb->pixel_format) {
2831         case DRM_FORMAT_C8:
2832                 dspcntr |= DISPPLANE_8BPP;
2833                 break;
2834         case DRM_FORMAT_RGB565:
2835                 dspcntr |= DISPPLANE_BGRX565;
2836                 break;
2837         case DRM_FORMAT_XRGB8888:
2838                 dspcntr |= DISPPLANE_BGRX888;
2839                 break;
2840         case DRM_FORMAT_XBGR8888:
2841                 dspcntr |= DISPPLANE_RGBX888;
2842                 break;
2843         case DRM_FORMAT_XRGB2101010:
2844                 dspcntr |= DISPPLANE_BGRX101010;
2845                 break;
2846         case DRM_FORMAT_XBGR2101010:
2847                 dspcntr |= DISPPLANE_RGBX101010;
2848                 break;
2849         default:
2850                 BUG();
2851         }
2852
2853         if (obj->tiling_mode != I915_TILING_NONE)
2854                 dspcntr |= DISPPLANE_TILED;
2855
2856         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2857                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2858
2859         linear_offset = y * fb->pitches[0] + x * pixel_size;
2860         intel_crtc->dspaddr_offset =
2861                 intel_gen4_compute_page_offset(dev_priv,
2862                                                &x, &y, obj->tiling_mode,
2863                                                pixel_size,
2864                                                fb->pitches[0]);
2865         linear_offset -= intel_crtc->dspaddr_offset;
2866         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2867                 dspcntr |= DISPPLANE_ROTATE_180;
2868
2869                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2870                         x += (intel_crtc->config->pipe_src_w - 1);
2871                         y += (intel_crtc->config->pipe_src_h - 1);
2872
2873                         /* Finding the last pixel of the last line of the display
2874                         data and adding to linear_offset*/
2875                         linear_offset +=
2876                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2877                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2878                 }
2879         }
2880
2881         I915_WRITE(reg, dspcntr);
2882
2883         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2884         I915_WRITE(DSPSURF(plane),
2885                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2886         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2887                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2888         } else {
2889                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2890                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2891         }
2892         POSTING_READ(reg);
2893 }
2894
2895 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2896                               uint32_t pixel_format)
2897 {
2898         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2899
2900         /*
2901          * The stride is either expressed as a multiple of 64 bytes
2902          * chunks for linear buffers or in number of tiles for tiled
2903          * buffers.
2904          */
2905         switch (fb_modifier) {
2906         case DRM_FORMAT_MOD_NONE:
2907                 return 64;
2908         case I915_FORMAT_MOD_X_TILED:
2909                 if (INTEL_INFO(dev)->gen == 2)
2910                         return 128;
2911                 return 512;
2912         case I915_FORMAT_MOD_Y_TILED:
2913                 /* No need to check for old gens and Y tiling since this is
2914                  * about the display engine and those will be blocked before
2915                  * we get here.
2916                  */
2917                 return 128;
2918         case I915_FORMAT_MOD_Yf_TILED:
2919                 if (bits_per_pixel == 8)
2920                         return 64;
2921                 else
2922                         return 128;
2923         default:
2924                 MISSING_CASE(fb_modifier);
2925                 return 64;
2926         }
2927 }
2928
2929 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2930                                      struct drm_i915_gem_object *obj)
2931 {
2932         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2933
2934         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2935                 view = &i915_ggtt_view_rotated;
2936
2937         return i915_gem_obj_ggtt_offset_view(obj, view);
2938 }
2939
2940 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2941 {
2942         struct drm_device *dev = intel_crtc->base.dev;
2943         struct drm_i915_private *dev_priv = dev->dev_private;
2944
2945         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2946         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2947         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2948         DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2949                 intel_crtc->base.base.id, intel_crtc->pipe, id);
2950 }
2951
2952 /*
2953  * This function detaches (aka. unbinds) unused scalers in hardware
2954  */
2955 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2956 {
2957         struct intel_crtc_scaler_state *scaler_state;
2958         int i;
2959
2960         scaler_state = &intel_crtc->config->scaler_state;
2961
2962         /* loop through and disable scalers that aren't in use */
2963         for (i = 0; i < intel_crtc->num_scalers; i++) {
2964                 if (!scaler_state->scalers[i].in_use)
2965                         skl_detach_scaler(intel_crtc, i);
2966         }
2967 }
2968
2969 u32 skl_plane_ctl_format(uint32_t pixel_format)
2970 {
2971         switch (pixel_format) {
2972         case DRM_FORMAT_C8:
2973                 return PLANE_CTL_FORMAT_INDEXED;
2974         case DRM_FORMAT_RGB565:
2975                 return PLANE_CTL_FORMAT_RGB_565;
2976         case DRM_FORMAT_XBGR8888:
2977                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2978         case DRM_FORMAT_XRGB8888:
2979                 return PLANE_CTL_FORMAT_XRGB_8888;
2980         /*
2981          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2982          * to be already pre-multiplied. We need to add a knob (or a different
2983          * DRM_FORMAT) for user-space to configure that.
2984          */
2985         case DRM_FORMAT_ABGR8888:
2986                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2987                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2988         case DRM_FORMAT_ARGB8888:
2989                 return PLANE_CTL_FORMAT_XRGB_8888 |
2990                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2991         case DRM_FORMAT_XRGB2101010:
2992                 return PLANE_CTL_FORMAT_XRGB_2101010;
2993         case DRM_FORMAT_XBGR2101010:
2994                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2995         case DRM_FORMAT_YUYV:
2996                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2997         case DRM_FORMAT_YVYU:
2998                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2999         case DRM_FORMAT_UYVY:
3000                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3001         case DRM_FORMAT_VYUY:
3002                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3003         default:
3004                 MISSING_CASE(pixel_format);
3005         }
3006
3007         return 0;
3008 }
3009
3010 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3011 {
3012         switch (fb_modifier) {
3013         case DRM_FORMAT_MOD_NONE:
3014                 break;
3015         case I915_FORMAT_MOD_X_TILED:
3016                 return PLANE_CTL_TILED_X;
3017         case I915_FORMAT_MOD_Y_TILED:
3018                 return PLANE_CTL_TILED_Y;
3019         case I915_FORMAT_MOD_Yf_TILED:
3020                 return PLANE_CTL_TILED_YF;
3021         default:
3022                 MISSING_CASE(fb_modifier);
3023         }
3024
3025         return 0;
3026 }
3027
3028 u32 skl_plane_ctl_rotation(unsigned int rotation)
3029 {
3030         switch (rotation) {
3031         case BIT(DRM_ROTATE_0):
3032                 break;
3033         /*
3034          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3035          * while i915 HW rotation is clockwise, thats why this swapping.
3036          */
3037         case BIT(DRM_ROTATE_90):
3038                 return PLANE_CTL_ROTATE_270;
3039         case BIT(DRM_ROTATE_180):
3040                 return PLANE_CTL_ROTATE_180;
3041         case BIT(DRM_ROTATE_270):
3042                 return PLANE_CTL_ROTATE_90;
3043         default:
3044                 MISSING_CASE(rotation);
3045         }
3046
3047         return 0;
3048 }
3049
3050 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3051                                          struct drm_framebuffer *fb,
3052                                          int x, int y)
3053 {
3054         struct drm_device *dev = crtc->dev;
3055         struct drm_i915_private *dev_priv = dev->dev_private;
3056         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3057         struct drm_plane *plane = crtc->primary;
3058         bool visible = to_intel_plane_state(plane->state)->visible;
3059         struct drm_i915_gem_object *obj;
3060         int pipe = intel_crtc->pipe;
3061         u32 plane_ctl, stride_div, stride;
3062         u32 tile_height, plane_offset, plane_size;
3063         unsigned int rotation;
3064         int x_offset, y_offset;
3065         unsigned long surf_addr;
3066         struct intel_crtc_state *crtc_state = intel_crtc->config;
3067         struct intel_plane_state *plane_state;
3068         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3069         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3070         int scaler_id = -1;
3071
3072         plane_state = to_intel_plane_state(plane->state);
3073
3074         if (!visible || !fb) {
3075                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3076                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3077                 POSTING_READ(PLANE_CTL(pipe, 0));
3078                 return;
3079         }
3080
3081         plane_ctl = PLANE_CTL_ENABLE |
3082                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3083                     PLANE_CTL_PIPE_CSC_ENABLE;
3084
3085         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3086         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3087         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3088
3089         rotation = plane->state->rotation;
3090         plane_ctl |= skl_plane_ctl_rotation(rotation);
3091
3092         obj = intel_fb_obj(fb);
3093         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3094                                                fb->pixel_format);
3095         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3096
3097         /*
3098          * FIXME: intel_plane_state->src, dst aren't set when transitional
3099          * update_plane helpers are called from legacy paths.
3100          * Once full atomic crtc is available, below check can be avoided.
3101          */
3102         if (drm_rect_width(&plane_state->src)) {
3103                 scaler_id = plane_state->scaler_id;
3104                 src_x = plane_state->src.x1 >> 16;
3105                 src_y = plane_state->src.y1 >> 16;
3106                 src_w = drm_rect_width(&plane_state->src) >> 16;
3107                 src_h = drm_rect_height(&plane_state->src) >> 16;
3108                 dst_x = plane_state->dst.x1;
3109                 dst_y = plane_state->dst.y1;
3110                 dst_w = drm_rect_width(&plane_state->dst);
3111                 dst_h = drm_rect_height(&plane_state->dst);
3112
3113                 WARN_ON(x != src_x || y != src_y);
3114         } else {
3115                 src_w = intel_crtc->config->pipe_src_w;
3116                 src_h = intel_crtc->config->pipe_src_h;
3117         }
3118
3119         if (intel_rotation_90_or_270(rotation)) {
3120                 /* stride = Surface height in tiles */
3121                 tile_height = intel_tile_height(dev, fb->pixel_format,
3122                                                 fb->modifier[0]);
3123                 stride = DIV_ROUND_UP(fb->height, tile_height);
3124                 x_offset = stride * tile_height - y - src_h;
3125                 y_offset = x;
3126                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3127         } else {
3128                 stride = fb->pitches[0] / stride_div;
3129                 x_offset = x;
3130                 y_offset = y;
3131                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3132         }
3133         plane_offset = y_offset << 16 | x_offset;
3134
3135         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3136         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3137         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3138         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3139
3140         if (scaler_id >= 0) {
3141                 uint32_t ps_ctrl = 0;
3142
3143                 WARN_ON(!dst_w || !dst_h);
3144                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3145                         crtc_state->scaler_state.scalers[scaler_id].mode;
3146                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3147                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3148                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3149                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3150                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3151         } else {
3152                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3153         }
3154
3155         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3156
3157         POSTING_READ(PLANE_SURF(pipe, 0));
3158 }
3159
3160 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3161 static int
3162 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3163                            int x, int y, enum mode_set_atomic state)
3164 {
3165         struct drm_device *dev = crtc->dev;
3166         struct drm_i915_private *dev_priv = dev->dev_private;
3167
3168         if (dev_priv->fbc.disable_fbc)
3169                 dev_priv->fbc.disable_fbc(dev_priv);
3170
3171         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3172
3173         return 0;
3174 }
3175
3176 static void intel_complete_page_flips(struct drm_device *dev)
3177 {
3178         struct drm_crtc *crtc;
3179
3180         for_each_crtc(dev, crtc) {
3181                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3182                 enum plane plane = intel_crtc->plane;
3183
3184                 intel_prepare_page_flip(dev, plane);
3185                 intel_finish_page_flip_plane(dev, plane);
3186         }
3187 }
3188
3189 static void intel_update_primary_planes(struct drm_device *dev)
3190 {
3191         struct drm_i915_private *dev_priv = dev->dev_private;
3192         struct drm_crtc *crtc;
3193
3194         for_each_crtc(dev, crtc) {
3195                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3196
3197                 drm_modeset_lock(&crtc->mutex, NULL);
3198                 /*
3199                  * FIXME: Once we have proper support for primary planes (and
3200                  * disabling them without disabling the entire crtc) allow again
3201                  * a NULL crtc->primary->fb.
3202                  */
3203                 if (intel_crtc->active && crtc->primary->fb)
3204                         dev_priv->display.update_primary_plane(crtc,
3205                                                                crtc->primary->fb,
3206                                                                crtc->x,
3207                                                                crtc->y);
3208                 drm_modeset_unlock(&crtc->mutex);
3209         }
3210 }
3211
3212 void intel_prepare_reset(struct drm_device *dev)
3213 {
3214         /* no reset support for gen2 */
3215         if (IS_GEN2(dev))
3216                 return;
3217
3218         /* reset doesn't touch the display */
3219         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3220                 return;
3221
3222         drm_modeset_lock_all(dev);
3223         /*
3224          * Disabling the crtcs gracefully seems nicer. Also the
3225          * g33 docs say we should at least disable all the planes.
3226          */
3227         intel_display_suspend(dev);
3228 }
3229
3230 void intel_finish_reset(struct drm_device *dev)
3231 {
3232         struct drm_i915_private *dev_priv = to_i915(dev);
3233
3234         /*
3235          * Flips in the rings will be nuked by the reset,
3236          * so complete all pending flips so that user space
3237          * will get its events and not get stuck.
3238          */
3239         intel_complete_page_flips(dev);
3240
3241         /* no reset support for gen2 */
3242         if (IS_GEN2(dev))
3243                 return;
3244
3245         /* reset doesn't touch the display */
3246         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3247                 /*
3248                  * Flips in the rings have been nuked by the reset,
3249                  * so update the base address of all primary
3250                  * planes to the the last fb to make sure we're
3251                  * showing the correct fb after a reset.
3252                  */
3253                 intel_update_primary_planes(dev);
3254                 return;
3255         }
3256
3257         /*
3258          * The display has been reset as well,
3259          * so need a full re-initialization.
3260          */
3261         intel_runtime_pm_disable_interrupts(dev_priv);
3262         intel_runtime_pm_enable_interrupts(dev_priv);
3263
3264         intel_modeset_init_hw(dev);
3265
3266         spin_lock_irq(&dev_priv->irq_lock);
3267         if (dev_priv->display.hpd_irq_setup)
3268                 dev_priv->display.hpd_irq_setup(dev);
3269         spin_unlock_irq(&dev_priv->irq_lock);
3270
3271         intel_display_resume(dev);
3272
3273         intel_hpd_init(dev_priv);
3274
3275         drm_modeset_unlock_all(dev);
3276 }
3277
3278 static void
3279 intel_finish_fb(struct drm_framebuffer *old_fb)
3280 {
3281         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3282         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3283         bool was_interruptible = dev_priv->mm.interruptible;
3284         int ret;
3285
3286         /* Big Hammer, we also need to ensure that any pending
3287          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3288          * current scanout is retired before unpinning the old
3289          * framebuffer. Note that we rely on userspace rendering
3290          * into the buffer attached to the pipe they are waiting
3291          * on. If not, userspace generates a GPU hang with IPEHR
3292          * point to the MI_WAIT_FOR_EVENT.
3293          *
3294          * This should only fail upon a hung GPU, in which case we
3295          * can safely continue.
3296          */
3297         dev_priv->mm.interruptible = false;
3298         ret = i915_gem_object_wait_rendering(obj, true);
3299         dev_priv->mm.interruptible = was_interruptible;
3300
3301         WARN_ON(ret);
3302 }
3303
3304 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3305 {
3306         struct drm_device *dev = crtc->dev;
3307         struct drm_i915_private *dev_priv = dev->dev_private;
3308         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3309         bool pending;
3310
3311         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3312             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3313                 return false;
3314
3315         spin_lock_irq(&dev->event_lock);
3316         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3317         spin_unlock_irq(&dev->event_lock);
3318
3319         return pending;
3320 }
3321
3322 static void intel_update_pipe_size(struct intel_crtc *crtc)
3323 {
3324         struct drm_device *dev = crtc->base.dev;
3325         struct drm_i915_private *dev_priv = dev->dev_private;
3326         const struct drm_display_mode *adjusted_mode;
3327
3328         if (!i915.fastboot)
3329                 return;
3330
3331         /*
3332          * Update pipe size and adjust fitter if needed: the reason for this is
3333          * that in compute_mode_changes we check the native mode (not the pfit
3334          * mode) to see if we can flip rather than do a full mode set. In the
3335          * fastboot case, we'll flip, but if we don't update the pipesrc and
3336          * pfit state, we'll end up with a big fb scanned out into the wrong
3337          * sized surface.
3338          *
3339          * To fix this properly, we need to hoist the checks up into
3340          * compute_mode_changes (or above), check the actual pfit state and
3341          * whether the platform allows pfit disable with pipe active, and only
3342          * then update the pipesrc and pfit state, even on the flip path.
3343          */
3344
3345         adjusted_mode = &crtc->config->base.adjusted_mode;
3346
3347         I915_WRITE(PIPESRC(crtc->pipe),
3348                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3349                    (adjusted_mode->crtc_vdisplay - 1));
3350         if (!crtc->config->pch_pfit.enabled &&
3351             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3352              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3353                 I915_WRITE(PF_CTL(crtc->pipe), 0);
3354                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3355                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3356         }
3357         crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3358         crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3359 }
3360
3361 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3362 {
3363         struct drm_device *dev = crtc->dev;
3364         struct drm_i915_private *dev_priv = dev->dev_private;
3365         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3366         int pipe = intel_crtc->pipe;
3367         u32 reg, temp;
3368
3369         /* enable normal train */
3370         reg = FDI_TX_CTL(pipe);
3371         temp = I915_READ(reg);
3372         if (IS_IVYBRIDGE(dev)) {
3373                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3374                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3375         } else {
3376                 temp &= ~FDI_LINK_TRAIN_NONE;
3377                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3378         }
3379         I915_WRITE(reg, temp);
3380
3381         reg = FDI_RX_CTL(pipe);
3382         temp = I915_READ(reg);
3383         if (HAS_PCH_CPT(dev)) {
3384                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3385                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3386         } else {
3387                 temp &= ~FDI_LINK_TRAIN_NONE;
3388                 temp |= FDI_LINK_TRAIN_NONE;
3389         }
3390         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3391
3392         /* wait one idle pattern time */
3393         POSTING_READ(reg);
3394         udelay(1000);
3395
3396         /* IVB wants error correction enabled */
3397         if (IS_IVYBRIDGE(dev))
3398                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3399                            FDI_FE_ERRC_ENABLE);
3400 }
3401
3402 /* The FDI link training functions for ILK/Ibexpeak. */
3403 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3404 {
3405         struct drm_device *dev = crtc->dev;
3406         struct drm_i915_private *dev_priv = dev->dev_private;
3407         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3408         int pipe = intel_crtc->pipe;
3409         u32 reg, temp, tries;
3410
3411         /* FDI needs bits from pipe first */
3412         assert_pipe_enabled(dev_priv, pipe);
3413
3414         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3415            for train result */
3416         reg = FDI_RX_IMR(pipe);
3417         temp = I915_READ(reg);
3418         temp &= ~FDI_RX_SYMBOL_LOCK;
3419         temp &= ~FDI_RX_BIT_LOCK;
3420         I915_WRITE(reg, temp);
3421         I915_READ(reg);
3422         udelay(150);
3423
3424         /* enable CPU FDI TX and PCH FDI RX */
3425         reg = FDI_TX_CTL(pipe);
3426         temp = I915_READ(reg);
3427         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3428         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3429         temp &= ~FDI_LINK_TRAIN_NONE;
3430         temp |= FDI_LINK_TRAIN_PATTERN_1;
3431         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3432
3433         reg = FDI_RX_CTL(pipe);
3434         temp = I915_READ(reg);
3435         temp &= ~FDI_LINK_TRAIN_NONE;
3436         temp |= FDI_LINK_TRAIN_PATTERN_1;
3437         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3438
3439         POSTING_READ(reg);
3440         udelay(150);
3441
3442         /* Ironlake workaround, enable clock pointer after FDI enable*/
3443         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3444         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3445                    FDI_RX_PHASE_SYNC_POINTER_EN);
3446
3447         reg = FDI_RX_IIR(pipe);
3448         for (tries = 0; tries < 5; tries++) {
3449                 temp = I915_READ(reg);
3450                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3451
3452                 if ((temp & FDI_RX_BIT_LOCK)) {
3453                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3454                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3455                         break;
3456                 }
3457         }
3458         if (tries == 5)
3459                 DRM_ERROR("FDI train 1 fail!\n");
3460
3461         /* Train 2 */
3462         reg = FDI_TX_CTL(pipe);
3463         temp = I915_READ(reg);
3464         temp &= ~FDI_LINK_TRAIN_NONE;
3465         temp |= FDI_LINK_TRAIN_PATTERN_2;
3466         I915_WRITE(reg, temp);
3467
3468         reg = FDI_RX_CTL(pipe);
3469         temp = I915_READ(reg);
3470         temp &= ~FDI_LINK_TRAIN_NONE;
3471         temp |= FDI_LINK_TRAIN_PATTERN_2;
3472         I915_WRITE(reg, temp);
3473
3474         POSTING_READ(reg);
3475         udelay(150);
3476
3477         reg = FDI_RX_IIR(pipe);
3478         for (tries = 0; tries < 5; tries++) {
3479                 temp = I915_READ(reg);
3480                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3481
3482                 if (temp & FDI_RX_SYMBOL_LOCK) {
3483                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3484                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3485                         break;
3486                 }
3487         }
3488         if (tries == 5)
3489                 DRM_ERROR("FDI train 2 fail!\n");
3490
3491         DRM_DEBUG_KMS("FDI train done\n");
3492
3493 }
3494
3495 static const int snb_b_fdi_train_param[] = {
3496         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3497         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3498         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3499         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3500 };
3501
3502 /* The FDI link training functions for SNB/Cougarpoint. */
3503 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3504 {
3505         struct drm_device *dev = crtc->dev;
3506         struct drm_i915_private *dev_priv = dev->dev_private;
3507         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3508         int pipe = intel_crtc->pipe;
3509         u32 reg, temp, i, retry;
3510
3511         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3512            for train result */
3513         reg = FDI_RX_IMR(pipe);
3514         temp = I915_READ(reg);
3515         temp &= ~FDI_RX_SYMBOL_LOCK;
3516         temp &= ~FDI_RX_BIT_LOCK;
3517         I915_WRITE(reg, temp);
3518
3519         POSTING_READ(reg);
3520         udelay(150);
3521
3522         /* enable CPU FDI TX and PCH FDI RX */
3523         reg = FDI_TX_CTL(pipe);
3524         temp = I915_READ(reg);
3525         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3526         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3527         temp &= ~FDI_LINK_TRAIN_NONE;
3528         temp |= FDI_LINK_TRAIN_PATTERN_1;
3529         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3530         /* SNB-B */
3531         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3532         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3533
3534         I915_WRITE(FDI_RX_MISC(pipe),
3535                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3536
3537         reg = FDI_RX_CTL(pipe);
3538         temp = I915_READ(reg);
3539         if (HAS_PCH_CPT(dev)) {
3540                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3541                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3542         } else {
3543                 temp &= ~FDI_LINK_TRAIN_NONE;
3544                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3545         }
3546         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3547
3548         POSTING_READ(reg);
3549         udelay(150);
3550
3551         for (i = 0; i < 4; i++) {
3552                 reg = FDI_TX_CTL(pipe);
3553                 temp = I915_READ(reg);
3554                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3555                 temp |= snb_b_fdi_train_param[i];
3556                 I915_WRITE(reg, temp);
3557
3558                 POSTING_READ(reg);
3559                 udelay(500);
3560
3561                 for (retry = 0; retry < 5; retry++) {
3562                         reg = FDI_RX_IIR(pipe);
3563                         temp = I915_READ(reg);
3564                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3565                         if (temp & FDI_RX_BIT_LOCK) {
3566                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3567                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3568                                 break;
3569                         }
3570                         udelay(50);
3571                 }
3572                 if (retry < 5)
3573                         break;
3574         }
3575         if (i == 4)
3576                 DRM_ERROR("FDI train 1 fail!\n");
3577
3578         /* Train 2 */
3579         reg = FDI_TX_CTL(pipe);
3580         temp = I915_READ(reg);
3581         temp &= ~FDI_LINK_TRAIN_NONE;
3582         temp |= FDI_LINK_TRAIN_PATTERN_2;
3583         if (IS_GEN6(dev)) {
3584                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3585                 /* SNB-B */
3586                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3587         }
3588         I915_WRITE(reg, temp);
3589
3590         reg = FDI_RX_CTL(pipe);
3591         temp = I915_READ(reg);
3592         if (HAS_PCH_CPT(dev)) {
3593                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3594                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3595         } else {
3596                 temp &= ~FDI_LINK_TRAIN_NONE;
3597                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3598         }
3599         I915_WRITE(reg, temp);
3600
3601         POSTING_READ(reg);
3602         udelay(150);
3603
3604         for (i = 0; i < 4; i++) {
3605                 reg = FDI_TX_CTL(pipe);
3606                 temp = I915_READ(reg);
3607                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3608                 temp |= snb_b_fdi_train_param[i];
3609                 I915_WRITE(reg, temp);
3610
3611                 POSTING_READ(reg);
3612                 udelay(500);
3613
3614                 for (retry = 0; retry < 5; retry++) {
3615                         reg = FDI_RX_IIR(pipe);
3616                         temp = I915_READ(reg);
3617                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3618                         if (temp & FDI_RX_SYMBOL_LOCK) {
3619                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3620                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3621                                 break;
3622                         }
3623                         udelay(50);
3624                 }
3625                 if (retry < 5)
3626                         break;
3627         }
3628         if (i == 4)
3629                 DRM_ERROR("FDI train 2 fail!\n");
3630
3631         DRM_DEBUG_KMS("FDI train done.\n");
3632 }
3633
3634 /* Manual link training for Ivy Bridge A0 parts */
3635 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3636 {
3637         struct drm_device *dev = crtc->dev;
3638         struct drm_i915_private *dev_priv = dev->dev_private;
3639         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3640         int pipe = intel_crtc->pipe;
3641         u32 reg, temp, i, j;
3642
3643         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3644            for train result */
3645         reg = FDI_RX_IMR(pipe);
3646         temp = I915_READ(reg);
3647         temp &= ~FDI_RX_SYMBOL_LOCK;
3648         temp &= ~FDI_RX_BIT_LOCK;
3649         I915_WRITE(reg, temp);
3650
3651         POSTING_READ(reg);
3652         udelay(150);
3653
3654         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3655                       I915_READ(FDI_RX_IIR(pipe)));
3656
3657         /* Try each vswing and preemphasis setting twice before moving on */
3658         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3659                 /* disable first in case we need to retry */
3660                 reg = FDI_TX_CTL(pipe);
3661                 temp = I915_READ(reg);
3662                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3663                 temp &= ~FDI_TX_ENABLE;
3664                 I915_WRITE(reg, temp);
3665
3666                 reg = FDI_RX_CTL(pipe);
3667                 temp = I915_READ(reg);
3668                 temp &= ~FDI_LINK_TRAIN_AUTO;
3669                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3670                 temp &= ~FDI_RX_ENABLE;
3671                 I915_WRITE(reg, temp);
3672
3673                 /* enable CPU FDI TX and PCH FDI RX */
3674                 reg = FDI_TX_CTL(pipe);
3675                 temp = I915_READ(reg);
3676                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3677                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3678                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3679                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3680                 temp |= snb_b_fdi_train_param[j/2];
3681                 temp |= FDI_COMPOSITE_SYNC;
3682                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3683
3684                 I915_WRITE(FDI_RX_MISC(pipe),
3685                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3686
3687                 reg = FDI_RX_CTL(pipe);
3688                 temp = I915_READ(reg);
3689                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3690                 temp |= FDI_COMPOSITE_SYNC;
3691                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3692
3693                 POSTING_READ(reg);
3694                 udelay(1); /* should be 0.5us */
3695
3696                 for (i = 0; i < 4; i++) {
3697                         reg = FDI_RX_IIR(pipe);
3698                         temp = I915_READ(reg);
3699                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3700
3701                         if (temp & FDI_RX_BIT_LOCK ||
3702                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3703                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3704                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3705                                               i);
3706                                 break;
3707                         }
3708                         udelay(1); /* should be 0.5us */
3709                 }
3710                 if (i == 4) {
3711                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3712                         continue;
3713                 }
3714
3715                 /* Train 2 */
3716                 reg = FDI_TX_CTL(pipe);
3717                 temp = I915_READ(reg);
3718                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3719                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3720                 I915_WRITE(reg, temp);
3721
3722                 reg = FDI_RX_CTL(pipe);
3723                 temp = I915_READ(reg);
3724                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3725                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3726                 I915_WRITE(reg, temp);
3727
3728                 POSTING_READ(reg);
3729                 udelay(2); /* should be 1.5us */
3730
3731                 for (i = 0; i < 4; i++) {
3732                         reg = FDI_RX_IIR(pipe);
3733                         temp = I915_READ(reg);
3734                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3735
3736                         if (temp & FDI_RX_SYMBOL_LOCK ||
3737                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3738                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3739                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3740                                               i);
3741                                 goto train_done;
3742                         }
3743                         udelay(2); /* should be 1.5us */
3744                 }
3745                 if (i == 4)
3746                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3747         }
3748
3749 train_done:
3750         DRM_DEBUG_KMS("FDI train done.\n");
3751 }
3752
3753 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3754 {
3755         struct drm_device *dev = intel_crtc->base.dev;
3756         struct drm_i915_private *dev_priv = dev->dev_private;
3757         int pipe = intel_crtc->pipe;
3758         u32 reg, temp;
3759
3760
3761         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3762         reg = FDI_RX_CTL(pipe);
3763         temp = I915_READ(reg);
3764         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3765         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3766         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3767         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3768
3769         POSTING_READ(reg);
3770         udelay(200);
3771
3772         /* Switch from Rawclk to PCDclk */
3773         temp = I915_READ(reg);
3774         I915_WRITE(reg, temp | FDI_PCDCLK);
3775
3776         POSTING_READ(reg);
3777         udelay(200);
3778
3779         /* Enable CPU FDI TX PLL, always on for Ironlake */
3780         reg = FDI_TX_CTL(pipe);
3781         temp = I915_READ(reg);
3782         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3783                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3784
3785                 POSTING_READ(reg);
3786                 udelay(100);
3787         }
3788 }
3789
3790 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3791 {
3792         struct drm_device *dev = intel_crtc->base.dev;
3793         struct drm_i915_private *dev_priv = dev->dev_private;
3794         int pipe = intel_crtc->pipe;
3795         u32 reg, temp;
3796
3797         /* Switch from PCDclk to Rawclk */
3798         reg = FDI_RX_CTL(pipe);
3799         temp = I915_READ(reg);
3800         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3801
3802         /* Disable CPU FDI TX PLL */
3803         reg = FDI_TX_CTL(pipe);
3804         temp = I915_READ(reg);
3805         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3806
3807         POSTING_READ(reg);
3808         udelay(100);
3809
3810         reg = FDI_RX_CTL(pipe);
3811         temp = I915_READ(reg);
3812         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3813
3814         /* Wait for the clocks to turn off. */
3815         POSTING_READ(reg);
3816         udelay(100);
3817 }
3818
3819 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3820 {
3821         struct drm_device *dev = crtc->dev;
3822         struct drm_i915_private *dev_priv = dev->dev_private;
3823         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3824         int pipe = intel_crtc->pipe;
3825         u32 reg, temp;
3826
3827         /* disable CPU FDI tx and PCH FDI rx */
3828         reg = FDI_TX_CTL(pipe);
3829         temp = I915_READ(reg);
3830         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3831         POSTING_READ(reg);
3832
3833         reg = FDI_RX_CTL(pipe);
3834         temp = I915_READ(reg);
3835         temp &= ~(0x7 << 16);
3836         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3837         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3838
3839         POSTING_READ(reg);
3840         udelay(100);
3841
3842         /* Ironlake workaround, disable clock pointer after downing FDI */
3843         if (HAS_PCH_IBX(dev))
3844                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3845
3846         /* still set train pattern 1 */
3847         reg = FDI_TX_CTL(pipe);
3848         temp = I915_READ(reg);
3849         temp &= ~FDI_LINK_TRAIN_NONE;
3850         temp |= FDI_LINK_TRAIN_PATTERN_1;
3851         I915_WRITE(reg, temp);
3852
3853         reg = FDI_RX_CTL(pipe);
3854         temp = I915_READ(reg);
3855         if (HAS_PCH_CPT(dev)) {
3856                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3857                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3858         } else {
3859                 temp &= ~FDI_LINK_TRAIN_NONE;
3860                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3861         }
3862         /* BPC in FDI rx is consistent with that in PIPECONF */
3863         temp &= ~(0x07 << 16);
3864         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3865         I915_WRITE(reg, temp);
3866
3867         POSTING_READ(reg);
3868         udelay(100);
3869 }
3870
3871 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3872 {
3873         struct intel_crtc *crtc;
3874
3875         /* Note that we don't need to be called with mode_config.lock here
3876          * as our list of CRTC objects is static for the lifetime of the
3877          * device and so cannot disappear as we iterate. Similarly, we can
3878          * happily treat the predicates as racy, atomic checks as userspace
3879          * cannot claim and pin a new fb without at least acquring the
3880          * struct_mutex and so serialising with us.
3881          */
3882         for_each_intel_crtc(dev, crtc) {
3883                 if (atomic_read(&crtc->unpin_work_count) == 0)
3884                         continue;
3885
3886                 if (crtc->unpin_work)
3887                         intel_wait_for_vblank(dev, crtc->pipe);
3888
3889                 return true;
3890         }
3891
3892         return false;
3893 }
3894
3895 static void page_flip_completed(struct intel_crtc *intel_crtc)
3896 {
3897         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3898         struct intel_unpin_work *work = intel_crtc->unpin_work;
3899
3900         /* ensure that the unpin work is consistent wrt ->pending. */
3901         smp_rmb();
3902         intel_crtc->unpin_work = NULL;
3903
3904         if (work->event)
3905                 drm_send_vblank_event(intel_crtc->base.dev,
3906                                       intel_crtc->pipe,
3907                                       work->event);
3908
3909         drm_crtc_vblank_put(&intel_crtc->base);
3910
3911         wake_up_all(&dev_priv->pending_flip_queue);
3912         queue_work(dev_priv->wq, &work->work);
3913
3914         trace_i915_flip_complete(intel_crtc->plane,
3915                                  work->pending_flip_obj);
3916 }
3917
3918 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3919 {
3920         struct drm_device *dev = crtc->dev;
3921         struct drm_i915_private *dev_priv = dev->dev_private;
3922
3923         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3924         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3925                                        !intel_crtc_has_pending_flip(crtc),
3926                                        60*HZ) == 0)) {
3927                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3928
3929                 spin_lock_irq(&dev->event_lock);
3930                 if (intel_crtc->unpin_work) {
3931                         WARN_ONCE(1, "Removing stuck page flip\n");
3932                         page_flip_completed(intel_crtc);
3933                 }
3934                 spin_unlock_irq(&dev->event_lock);
3935         }
3936
3937         if (crtc->primary->fb) {
3938                 mutex_lock(&dev->struct_mutex);
3939                 intel_finish_fb(crtc->primary->fb);
3940                 mutex_unlock(&dev->struct_mutex);
3941         }
3942 }
3943
3944 /* Program iCLKIP clock to the desired frequency */
3945 static void lpt_program_iclkip(struct drm_crtc *crtc)
3946 {
3947         struct drm_device *dev = crtc->dev;
3948         struct drm_i915_private *dev_priv = dev->dev_private;
3949         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3950         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3951         u32 temp;
3952
3953         mutex_lock(&dev_priv->sb_lock);
3954
3955         /* It is necessary to ungate the pixclk gate prior to programming
3956          * the divisors, and gate it back when it is done.
3957          */
3958         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3959
3960         /* Disable SSCCTL */
3961         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3962                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3963                                 SBI_SSCCTL_DISABLE,
3964                         SBI_ICLK);
3965
3966         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3967         if (clock == 20000) {
3968                 auxdiv = 1;
3969                 divsel = 0x41;
3970                 phaseinc = 0x20;
3971         } else {
3972                 /* The iCLK virtual clock root frequency is in MHz,
3973                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3974                  * divisors, it is necessary to divide one by another, so we
3975                  * convert the virtual clock precision to KHz here for higher
3976                  * precision.
3977                  */
3978                 u32 iclk_virtual_root_freq = 172800 * 1000;
3979                 u32 iclk_pi_range = 64;
3980                 u32 desired_divisor, msb_divisor_value, pi_value;
3981
3982                 desired_divisor = (iclk_virtual_root_freq / clock);
3983                 msb_divisor_value = desired_divisor / iclk_pi_range;
3984                 pi_value = desired_divisor % iclk_pi_range;
3985
3986                 auxdiv = 0;
3987                 divsel = msb_divisor_value - 2;
3988                 phaseinc = pi_value;
3989         }
3990
3991         /* This should not happen with any sane values */
3992         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3993                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3994         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3995                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3996
3997         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3998                         clock,
3999                         auxdiv,
4000                         divsel,
4001                         phasedir,
4002                         phaseinc);
4003
4004         /* Program SSCDIVINTPHASE6 */
4005         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4006         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4007         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4008         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4009         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4010         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4011         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4012         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4013
4014         /* Program SSCAUXDIV */
4015         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4016         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4017         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4018         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4019
4020         /* Enable modulator and associated divider */
4021         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4022         temp &= ~SBI_SSCCTL_DISABLE;
4023         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4024
4025         /* Wait for initialization time */
4026         udelay(24);
4027
4028         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4029
4030         mutex_unlock(&dev_priv->sb_lock);
4031 }
4032
4033 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4034                                                 enum pipe pch_transcoder)
4035 {
4036         struct drm_device *dev = crtc->base.dev;
4037         struct drm_i915_private *dev_priv = dev->dev_private;
4038         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4039
4040         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4041                    I915_READ(HTOTAL(cpu_transcoder)));
4042         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4043                    I915_READ(HBLANK(cpu_transcoder)));
4044         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4045                    I915_READ(HSYNC(cpu_transcoder)));
4046
4047         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4048                    I915_READ(VTOTAL(cpu_transcoder)));
4049         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4050                    I915_READ(VBLANK(cpu_transcoder)));
4051         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4052                    I915_READ(VSYNC(cpu_transcoder)));
4053         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4054                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4055 }
4056
4057 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4058 {
4059         struct drm_i915_private *dev_priv = dev->dev_private;
4060         uint32_t temp;
4061
4062         temp = I915_READ(SOUTH_CHICKEN1);
4063         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4064                 return;
4065
4066         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4067         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4068
4069         temp &= ~FDI_BC_BIFURCATION_SELECT;
4070         if (enable)
4071                 temp |= FDI_BC_BIFURCATION_SELECT;
4072
4073         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4074         I915_WRITE(SOUTH_CHICKEN1, temp);
4075         POSTING_READ(SOUTH_CHICKEN1);
4076 }
4077
4078 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4079 {
4080         struct drm_device *dev = intel_crtc->base.dev;
4081
4082         switch (intel_crtc->pipe) {
4083         case PIPE_A:
4084                 break;
4085         case PIPE_B:
4086                 if (intel_crtc->config->fdi_lanes > 2)
4087                         cpt_set_fdi_bc_bifurcation(dev, false);
4088                 else
4089                         cpt_set_fdi_bc_bifurcation(dev, true);
4090
4091                 break;
4092         case PIPE_C:
4093                 cpt_set_fdi_bc_bifurcation(dev, true);
4094
4095                 break;
4096         default:
4097                 BUG();
4098         }
4099 }
4100
4101 /*
4102  * Enable PCH resources required for PCH ports:
4103  *   - PCH PLLs
4104  *   - FDI training & RX/TX
4105  *   - update transcoder timings
4106  *   - DP transcoding bits
4107  *   - transcoder
4108  */
4109 static void ironlake_pch_enable(struct drm_crtc *crtc)
4110 {
4111         struct drm_device *dev = crtc->dev;
4112         struct drm_i915_private *dev_priv = dev->dev_private;
4113         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4114         int pipe = intel_crtc->pipe;
4115         u32 reg, temp;
4116
4117         assert_pch_transcoder_disabled(dev_priv, pipe);
4118
4119         if (IS_IVYBRIDGE(dev))
4120                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4121
4122         /* Write the TU size bits before fdi link training, so that error
4123          * detection works. */
4124         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4125                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4126
4127         /* For PCH output, training FDI link */
4128         dev_priv->display.fdi_link_train(crtc);
4129
4130         /* We need to program the right clock selection before writing the pixel
4131          * mutliplier into the DPLL. */
4132         if (HAS_PCH_CPT(dev)) {
4133                 u32 sel;
4134
4135                 temp = I915_READ(PCH_DPLL_SEL);
4136                 temp |= TRANS_DPLL_ENABLE(pipe);
4137                 sel = TRANS_DPLLB_SEL(pipe);
4138                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4139                         temp |= sel;
4140                 else
4141                         temp &= ~sel;
4142                 I915_WRITE(PCH_DPLL_SEL, temp);
4143         }
4144
4145         /* XXX: pch pll's can be enabled any time before we enable the PCH
4146          * transcoder, and we actually should do this to not upset any PCH
4147          * transcoder that already use the clock when we share it.
4148          *
4149          * Note that enable_shared_dpll tries to do the right thing, but
4150          * get_shared_dpll unconditionally resets the pll - we need that to have
4151          * the right LVDS enable sequence. */
4152         intel_enable_shared_dpll(intel_crtc);
4153
4154         /* set transcoder timing, panel must allow it */
4155         assert_panel_unlocked(dev_priv, pipe);
4156         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4157
4158         intel_fdi_normal_train(crtc);
4159
4160         /* For PCH DP, enable TRANS_DP_CTL */
4161         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4162                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4163                 reg = TRANS_DP_CTL(pipe);
4164                 temp = I915_READ(reg);
4165                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4166                           TRANS_DP_SYNC_MASK |
4167                           TRANS_DP_BPC_MASK);
4168                 temp |= TRANS_DP_OUTPUT_ENABLE;
4169                 temp |= bpc << 9; /* same format but at 11:9 */
4170
4171                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4172                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4173                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4174                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4175
4176                 switch (intel_trans_dp_port_sel(crtc)) {
4177                 case PCH_DP_B:
4178                         temp |= TRANS_DP_PORT_SEL_B;
4179                         break;
4180                 case PCH_DP_C:
4181                         temp |= TRANS_DP_PORT_SEL_C;
4182                         break;
4183                 case PCH_DP_D:
4184                         temp |= TRANS_DP_PORT_SEL_D;
4185                         break;
4186                 default:
4187                         BUG();
4188                 }
4189
4190                 I915_WRITE(reg, temp);
4191         }
4192
4193         ironlake_enable_pch_transcoder(dev_priv, pipe);
4194 }
4195
4196 static void lpt_pch_enable(struct drm_crtc *crtc)
4197 {
4198         struct drm_device *dev = crtc->dev;
4199         struct drm_i915_private *dev_priv = dev->dev_private;
4200         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4201         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4202
4203         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4204
4205         lpt_program_iclkip(crtc);
4206
4207         /* Set transcoder timing. */
4208         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4209
4210         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4211 }
4212
4213 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4214                                                 struct intel_crtc_state *crtc_state)
4215 {
4216         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4217         struct intel_shared_dpll *pll;
4218         struct intel_shared_dpll_config *shared_dpll;
4219         enum intel_dpll_id i;
4220
4221         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4222
4223         if (HAS_PCH_IBX(dev_priv->dev)) {
4224                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4225                 i = (enum intel_dpll_id) crtc->pipe;
4226                 pll = &dev_priv->shared_dplls[i];
4227
4228                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4229                               crtc->base.base.id, pll->name);
4230
4231                 WARN_ON(shared_dpll[i].crtc_mask);
4232
4233                 goto found;
4234         }
4235
4236         if (IS_BROXTON(dev_priv->dev)) {
4237                 /* PLL is attached to port in bxt */
4238                 struct intel_encoder *encoder;
4239                 struct intel_digital_port *intel_dig_port;
4240
4241                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4242                 if (WARN_ON(!encoder))
4243                         return NULL;
4244
4245                 intel_dig_port = enc_to_dig_port(&encoder->base);
4246                 /* 1:1 mapping between ports and PLLs */
4247                 i = (enum intel_dpll_id)intel_dig_port->port;
4248                 pll = &dev_priv->shared_dplls[i];
4249                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4250                         crtc->base.base.id, pll->name);
4251                 WARN_ON(shared_dpll[i].crtc_mask);
4252
4253                 goto found;
4254         }
4255
4256         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4257                 pll = &dev_priv->shared_dplls[i];
4258
4259                 /* Only want to check enabled timings first */
4260                 if (shared_dpll[i].crtc_mask == 0)
4261                         continue;
4262
4263                 if (memcmp(&crtc_state->dpll_hw_state,
4264                            &shared_dpll[i].hw_state,
4265                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4266                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4267                                       crtc->base.base.id, pll->name,
4268                                       shared_dpll[i].crtc_mask,
4269                                       pll->active);
4270                         goto found;
4271                 }
4272         }
4273
4274         /* Ok no matching timings, maybe there's a free one? */
4275         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4276                 pll = &dev_priv->shared_dplls[i];
4277                 if (shared_dpll[i].crtc_mask == 0) {
4278                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4279                                       crtc->base.base.id, pll->name);
4280                         goto found;
4281                 }
4282         }
4283
4284         return NULL;
4285
4286 found:
4287         if (shared_dpll[i].crtc_mask == 0)
4288                 shared_dpll[i].hw_state =
4289                         crtc_state->dpll_hw_state;
4290
4291         crtc_state->shared_dpll = i;
4292         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4293                          pipe_name(crtc->pipe));
4294
4295         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4296
4297         return pll;
4298 }
4299
4300 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4301 {
4302         struct drm_i915_private *dev_priv = to_i915(state->dev);
4303         struct intel_shared_dpll_config *shared_dpll;
4304         struct intel_shared_dpll *pll;
4305         enum intel_dpll_id i;
4306
4307         if (!to_intel_atomic_state(state)->dpll_set)
4308                 return;
4309
4310         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4311         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4312                 pll = &dev_priv->shared_dplls[i];
4313                 pll->config = shared_dpll[i];
4314         }
4315 }
4316
4317 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4318 {
4319         struct drm_i915_private *dev_priv = dev->dev_private;
4320         int dslreg = PIPEDSL(pipe);
4321         u32 temp;
4322
4323         temp = I915_READ(dslreg);
4324         udelay(500);
4325         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4326                 if (wait_for(I915_READ(dslreg) != temp, 5))
4327                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4328         }
4329 }
4330
4331 static int
4332 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4333                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4334                   int src_w, int src_h, int dst_w, int dst_h)
4335 {
4336         struct intel_crtc_scaler_state *scaler_state =
4337                 &crtc_state->scaler_state;
4338         struct intel_crtc *intel_crtc =
4339                 to_intel_crtc(crtc_state->base.crtc);
4340         int need_scaling;
4341
4342         need_scaling = intel_rotation_90_or_270(rotation) ?
4343                 (src_h != dst_w || src_w != dst_h):
4344                 (src_w != dst_w || src_h != dst_h);
4345
4346         /*
4347          * if plane is being disabled or scaler is no more required or force detach
4348          *  - free scaler binded to this plane/crtc
4349          *  - in order to do this, update crtc->scaler_usage
4350          *
4351          * Here scaler state in crtc_state is set free so that
4352          * scaler can be assigned to other user. Actual register
4353          * update to free the scaler is done in plane/panel-fit programming.
4354          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4355          */
4356         if (force_detach || !need_scaling) {
4357                 if (*scaler_id >= 0) {
4358                         scaler_state->scaler_users &= ~(1 << scaler_user);
4359                         scaler_state->scalers[*scaler_id].in_use = 0;
4360
4361                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4362                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4363                                 intel_crtc->pipe, scaler_user, *scaler_id,
4364                                 scaler_state->scaler_users);
4365                         *scaler_id = -1;
4366                 }
4367                 return 0;
4368         }
4369
4370         /* range checks */
4371         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4372                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4373
4374                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4375                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4376                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4377                         "size is out of scaler range\n",
4378                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4379                 return -EINVAL;
4380         }
4381
4382         /* mark this plane as a scaler user in crtc_state */
4383         scaler_state->scaler_users |= (1 << scaler_user);
4384         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4385                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4386                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4387                 scaler_state->scaler_users);
4388
4389         return 0;
4390 }
4391
4392 /**
4393  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4394  *
4395  * @state: crtc's scaler state
4396  *
4397  * Return
4398  *     0 - scaler_usage updated successfully
4399  *    error - requested scaling cannot be supported or other error condition
4400  */
4401 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4402 {
4403         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4404         struct drm_display_mode *adjusted_mode =
4405                 &state->base.adjusted_mode;
4406
4407         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4408                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4409
4410         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4411                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4412                 state->pipe_src_w, state->pipe_src_h,
4413                 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
4414 }
4415
4416 /**
4417  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4418  *
4419  * @state: crtc's scaler state
4420  * @plane_state: atomic plane state to update
4421  *
4422  * Return
4423  *     0 - scaler_usage updated successfully
4424  *    error - requested scaling cannot be supported or other error condition
4425  */
4426 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4427                                    struct intel_plane_state *plane_state)
4428 {
4429
4430         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4431         struct intel_plane *intel_plane =
4432                 to_intel_plane(plane_state->base.plane);
4433         struct drm_framebuffer *fb = plane_state->base.fb;
4434         int ret;
4435
4436         bool force_detach = !fb || !plane_state->visible;
4437
4438         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4439                       intel_plane->base.base.id, intel_crtc->pipe,
4440                       drm_plane_index(&intel_plane->base));
4441
4442         ret = skl_update_scaler(crtc_state, force_detach,
4443                                 drm_plane_index(&intel_plane->base),
4444                                 &plane_state->scaler_id,
4445                                 plane_state->base.rotation,
4446                                 drm_rect_width(&plane_state->src) >> 16,
4447                                 drm_rect_height(&plane_state->src) >> 16,
4448                                 drm_rect_width(&plane_state->dst),
4449                                 drm_rect_height(&plane_state->dst));
4450
4451         if (ret || plane_state->scaler_id < 0)
4452                 return ret;
4453
4454         /* check colorkey */
4455         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4456                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4457                               intel_plane->base.base.id);
4458                 return -EINVAL;
4459         }
4460
4461         /* Check src format */
4462         switch (fb->pixel_format) {
4463         case DRM_FORMAT_RGB565:
4464         case DRM_FORMAT_XBGR8888:
4465         case DRM_FORMAT_XRGB8888:
4466         case DRM_FORMAT_ABGR8888:
4467         case DRM_FORMAT_ARGB8888:
4468         case DRM_FORMAT_XRGB2101010:
4469         case DRM_FORMAT_XBGR2101010:
4470         case DRM_FORMAT_YUYV:
4471         case DRM_FORMAT_YVYU:
4472         case DRM_FORMAT_UYVY:
4473         case DRM_FORMAT_VYUY:
4474                 break;
4475         default:
4476                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4477                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4478                 return -EINVAL;
4479         }
4480
4481         return 0;
4482 }
4483
4484 static void skylake_scaler_disable(struct intel_crtc *crtc)
4485 {
4486         int i;
4487
4488         for (i = 0; i < crtc->num_scalers; i++)
4489                 skl_detach_scaler(crtc, i);
4490 }
4491
4492 static void skylake_pfit_enable(struct intel_crtc *crtc)
4493 {
4494         struct drm_device *dev = crtc->base.dev;
4495         struct drm_i915_private *dev_priv = dev->dev_private;
4496         int pipe = crtc->pipe;
4497         struct intel_crtc_scaler_state *scaler_state =
4498                 &crtc->config->scaler_state;
4499
4500         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4501
4502         if (crtc->config->pch_pfit.enabled) {
4503                 int id;
4504
4505                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4506                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4507                         return;
4508                 }
4509
4510                 id = scaler_state->scaler_id;
4511                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4512                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4513                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4514                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4515
4516                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4517         }
4518 }
4519
4520 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4521 {
4522         struct drm_device *dev = crtc->base.dev;
4523         struct drm_i915_private *dev_priv = dev->dev_private;
4524         int pipe = crtc->pipe;
4525
4526         if (crtc->config->pch_pfit.enabled) {
4527                 /* Force use of hard-coded filter coefficients
4528                  * as some pre-programmed values are broken,
4529                  * e.g. x201.
4530                  */
4531                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4532                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4533                                                  PF_PIPE_SEL_IVB(pipe));
4534                 else
4535                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4536                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4537                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4538         }
4539 }
4540
4541 void hsw_enable_ips(struct intel_crtc *crtc)
4542 {
4543         struct drm_device *dev = crtc->base.dev;
4544         struct drm_i915_private *dev_priv = dev->dev_private;
4545
4546         if (!crtc->config->ips_enabled)
4547                 return;
4548
4549         /* We can only enable IPS after we enable a plane and wait for a vblank */
4550         intel_wait_for_vblank(dev, crtc->pipe);
4551
4552         assert_plane_enabled(dev_priv, crtc->plane);
4553         if (IS_BROADWELL(dev)) {
4554                 mutex_lock(&dev_priv->rps.hw_lock);
4555                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4556                 mutex_unlock(&dev_priv->rps.hw_lock);
4557                 /* Quoting Art Runyan: "its not safe to expect any particular
4558                  * value in IPS_CTL bit 31 after enabling IPS through the
4559                  * mailbox." Moreover, the mailbox may return a bogus state,
4560                  * so we need to just enable it and continue on.
4561                  */
4562         } else {
4563                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4564                 /* The bit only becomes 1 in the next vblank, so this wait here
4565                  * is essentially intel_wait_for_vblank. If we don't have this
4566                  * and don't wait for vblanks until the end of crtc_enable, then
4567                  * the HW state readout code will complain that the expected
4568                  * IPS_CTL value is not the one we read. */
4569                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4570                         DRM_ERROR("Timed out waiting for IPS enable\n");
4571         }
4572 }
4573
4574 void hsw_disable_ips(struct intel_crtc *crtc)
4575 {
4576         struct drm_device *dev = crtc->base.dev;
4577         struct drm_i915_private *dev_priv = dev->dev_private;
4578
4579         if (!crtc->config->ips_enabled)
4580                 return;
4581
4582         assert_plane_enabled(dev_priv, crtc->plane);
4583         if (IS_BROADWELL(dev)) {
4584                 mutex_lock(&dev_priv->rps.hw_lock);
4585                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4586                 mutex_unlock(&dev_priv->rps.hw_lock);
4587                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4588                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4589                         DRM_ERROR("Timed out waiting for IPS disable\n");
4590         } else {
4591                 I915_WRITE(IPS_CTL, 0);
4592                 POSTING_READ(IPS_CTL);
4593         }
4594
4595         /* We need to wait for a vblank before we can disable the plane. */
4596         intel_wait_for_vblank(dev, crtc->pipe);
4597 }
4598
4599 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4600 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4601 {
4602         struct drm_device *dev = crtc->dev;
4603         struct drm_i915_private *dev_priv = dev->dev_private;
4604         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4605         enum pipe pipe = intel_crtc->pipe;
4606         int palreg = PALETTE(pipe);
4607         int i;
4608         bool reenable_ips = false;
4609
4610         /* The clocks have to be on to load the palette. */
4611         if (!crtc->state->active)
4612                 return;
4613
4614         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4615                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4616                         assert_dsi_pll_enabled(dev_priv);
4617                 else
4618                         assert_pll_enabled(dev_priv, pipe);
4619         }
4620
4621         /* use legacy palette for Ironlake */
4622         if (!HAS_GMCH_DISPLAY(dev))
4623                 palreg = LGC_PALETTE(pipe);
4624
4625         /* Workaround : Do not read or write the pipe palette/gamma data while
4626          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4627          */
4628         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4629             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4630              GAMMA_MODE_MODE_SPLIT)) {
4631                 hsw_disable_ips(intel_crtc);
4632                 reenable_ips = true;
4633         }
4634
4635         for (i = 0; i < 256; i++) {
4636                 I915_WRITE(palreg + 4 * i,
4637                            (intel_crtc->lut_r[i] << 16) |
4638                            (intel_crtc->lut_g[i] << 8) |
4639                            intel_crtc->lut_b[i]);
4640         }
4641
4642         if (reenable_ips)
4643                 hsw_enable_ips(intel_crtc);
4644 }
4645
4646 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4647 {
4648         if (intel_crtc->overlay) {
4649                 struct drm_device *dev = intel_crtc->base.dev;
4650                 struct drm_i915_private *dev_priv = dev->dev_private;
4651
4652                 mutex_lock(&dev->struct_mutex);
4653                 dev_priv->mm.interruptible = false;
4654                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4655                 dev_priv->mm.interruptible = true;
4656                 mutex_unlock(&dev->struct_mutex);
4657         }
4658
4659         /* Let userspace switch the overlay on again. In most cases userspace
4660          * has to recompute where to put it anyway.
4661          */
4662 }
4663
4664 /**
4665  * intel_post_enable_primary - Perform operations after enabling primary plane
4666  * @crtc: the CRTC whose primary plane was just enabled
4667  *
4668  * Performs potentially sleeping operations that must be done after the primary
4669  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4670  * called due to an explicit primary plane update, or due to an implicit
4671  * re-enable that is caused when a sprite plane is updated to no longer
4672  * completely hide the primary plane.
4673  */
4674 static void
4675 intel_post_enable_primary(struct drm_crtc *crtc)
4676 {
4677         struct drm_device *dev = crtc->dev;
4678         struct drm_i915_private *dev_priv = dev->dev_private;
4679         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4680         int pipe = intel_crtc->pipe;
4681
4682         /*
4683          * BDW signals flip done immediately if the plane
4684          * is disabled, even if the plane enable is already
4685          * armed to occur at the next vblank :(
4686          */
4687         if (IS_BROADWELL(dev))
4688                 intel_wait_for_vblank(dev, pipe);
4689
4690         /*
4691          * FIXME IPS should be fine as long as one plane is
4692          * enabled, but in practice it seems to have problems
4693          * when going from primary only to sprite only and vice
4694          * versa.
4695          */
4696         hsw_enable_ips(intel_crtc);
4697
4698         /*
4699          * Gen2 reports pipe underruns whenever all planes are disabled.
4700          * So don't enable underrun reporting before at least some planes
4701          * are enabled.
4702          * FIXME: Need to fix the logic to work when we turn off all planes
4703          * but leave the pipe running.
4704          */
4705         if (IS_GEN2(dev))
4706                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4707
4708         /* Underruns don't raise interrupts, so check manually. */
4709         if (HAS_GMCH_DISPLAY(dev))
4710                 i9xx_check_fifo_underruns(dev_priv);
4711 }
4712
4713 /**
4714  * intel_pre_disable_primary - Perform operations before disabling primary plane
4715  * @crtc: the CRTC whose primary plane is to be disabled
4716  *
4717  * Performs potentially sleeping operations that must be done before the
4718  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4719  * be called due to an explicit primary plane update, or due to an implicit
4720  * disable that is caused when a sprite plane completely hides the primary
4721  * plane.
4722  */
4723 static void
4724 intel_pre_disable_primary(struct drm_crtc *crtc)
4725 {
4726         struct drm_device *dev = crtc->dev;
4727         struct drm_i915_private *dev_priv = dev->dev_private;
4728         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4729         int pipe = intel_crtc->pipe;
4730
4731         /*
4732          * Gen2 reports pipe underruns whenever all planes are disabled.
4733          * So diasble underrun reporting before all the planes get disabled.
4734          * FIXME: Need to fix the logic to work when we turn off all planes
4735          * but leave the pipe running.
4736          */
4737         if (IS_GEN2(dev))
4738                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4739
4740         /*
4741          * Vblank time updates from the shadow to live plane control register
4742          * are blocked if the memory self-refresh mode is active at that
4743          * moment. So to make sure the plane gets truly disabled, disable
4744          * first the self-refresh mode. The self-refresh enable bit in turn
4745          * will be checked/applied by the HW only at the next frame start
4746          * event which is after the vblank start event, so we need to have a
4747          * wait-for-vblank between disabling the plane and the pipe.
4748          */
4749         if (HAS_GMCH_DISPLAY(dev)) {
4750                 intel_set_memory_cxsr(dev_priv, false);
4751                 dev_priv->wm.vlv.cxsr = false;
4752                 intel_wait_for_vblank(dev, pipe);
4753         }
4754
4755         /*
4756          * FIXME IPS should be fine as long as one plane is
4757          * enabled, but in practice it seems to have problems
4758          * when going from primary only to sprite only and vice
4759          * versa.
4760          */
4761         hsw_disable_ips(intel_crtc);
4762 }
4763
4764 static void intel_post_plane_update(struct intel_crtc *crtc)
4765 {
4766         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4767         struct drm_device *dev = crtc->base.dev;
4768         struct drm_i915_private *dev_priv = dev->dev_private;
4769         struct drm_plane *plane;
4770
4771         if (atomic->wait_vblank)
4772                 intel_wait_for_vblank(dev, crtc->pipe);
4773
4774         intel_frontbuffer_flip(dev, atomic->fb_bits);
4775
4776         if (atomic->disable_cxsr)
4777                 crtc->wm.cxsr_allowed = true;
4778
4779         if (crtc->atomic.update_wm_post)
4780                 intel_update_watermarks(&crtc->base);
4781
4782         if (atomic->update_fbc)
4783                 intel_fbc_update(dev_priv);
4784
4785         if (atomic->post_enable_primary)
4786                 intel_post_enable_primary(&crtc->base);
4787
4788         drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4789                 intel_update_sprite_watermarks(plane, &crtc->base,
4790                                                0, 0, 0, false, false);
4791
4792         memset(atomic, 0, sizeof(*atomic));
4793 }
4794
4795 static void intel_pre_plane_update(struct intel_crtc *crtc)
4796 {
4797         struct drm_device *dev = crtc->base.dev;
4798         struct drm_i915_private *dev_priv = dev->dev_private;
4799         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4800         struct drm_plane *p;
4801
4802         /* Track fb's for any planes being disabled */
4803         drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4804                 struct intel_plane *plane = to_intel_plane(p);
4805
4806                 mutex_lock(&dev->struct_mutex);
4807                 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4808                                   plane->frontbuffer_bit);
4809                 mutex_unlock(&dev->struct_mutex);
4810         }
4811
4812         if (atomic->wait_for_flips)
4813                 intel_crtc_wait_for_pending_flips(&crtc->base);
4814
4815         if (atomic->disable_fbc)
4816                 intel_fbc_disable_crtc(crtc);
4817
4818         if (crtc->atomic.disable_ips)
4819                 hsw_disable_ips(crtc);
4820
4821         if (atomic->pre_disable_primary)
4822                 intel_pre_disable_primary(&crtc->base);
4823
4824         if (atomic->disable_cxsr) {
4825                 crtc->wm.cxsr_allowed = false;
4826                 intel_set_memory_cxsr(dev_priv, false);
4827         }
4828 }
4829
4830 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4831 {
4832         struct drm_device *dev = crtc->dev;
4833         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4834         struct drm_plane *p;
4835         int pipe = intel_crtc->pipe;
4836
4837         intel_crtc_dpms_overlay_disable(intel_crtc);
4838
4839         drm_for_each_plane_mask(p, dev, plane_mask)
4840                 to_intel_plane(p)->disable_plane(p, crtc);
4841
4842         /*
4843          * FIXME: Once we grow proper nuclear flip support out of this we need
4844          * to compute the mask of flip planes precisely. For the time being
4845          * consider this a flip to a NULL plane.
4846          */
4847         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4848 }
4849
4850 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4851 {
4852         struct drm_device *dev = crtc->dev;
4853         struct drm_i915_private *dev_priv = dev->dev_private;
4854         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4855         struct intel_encoder *encoder;
4856         int pipe = intel_crtc->pipe;
4857
4858         if (WARN_ON(intel_crtc->active))
4859                 return;
4860
4861         if (intel_crtc->config->has_pch_encoder)
4862                 intel_prepare_shared_dpll(intel_crtc);
4863
4864         if (intel_crtc->config->has_dp_encoder)
4865                 intel_dp_set_m_n(intel_crtc, M1_N1);
4866
4867         intel_set_pipe_timings(intel_crtc);
4868
4869         if (intel_crtc->config->has_pch_encoder) {
4870                 intel_cpu_transcoder_set_m_n(intel_crtc,
4871                                      &intel_crtc->config->fdi_m_n, NULL);
4872         }
4873
4874         ironlake_set_pipeconf(crtc);
4875
4876         intel_crtc->active = true;
4877
4878         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4879         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4880
4881         for_each_encoder_on_crtc(dev, crtc, encoder)
4882                 if (encoder->pre_enable)
4883                         encoder->pre_enable(encoder);
4884
4885         if (intel_crtc->config->has_pch_encoder) {
4886                 /* Note: FDI PLL enabling _must_ be done before we enable the
4887                  * cpu pipes, hence this is separate from all the other fdi/pch
4888                  * enabling. */
4889                 ironlake_fdi_pll_enable(intel_crtc);
4890         } else {
4891                 assert_fdi_tx_disabled(dev_priv, pipe);
4892                 assert_fdi_rx_disabled(dev_priv, pipe);
4893         }
4894
4895         ironlake_pfit_enable(intel_crtc);
4896
4897         /*
4898          * On ILK+ LUT must be loaded before the pipe is running but with
4899          * clocks enabled
4900          */
4901         intel_crtc_load_lut(crtc);
4902
4903         intel_update_watermarks(crtc);
4904         intel_enable_pipe(intel_crtc);
4905
4906         if (intel_crtc->config->has_pch_encoder)
4907                 ironlake_pch_enable(crtc);
4908
4909         assert_vblank_disabled(crtc);
4910         drm_crtc_vblank_on(crtc);
4911
4912         for_each_encoder_on_crtc(dev, crtc, encoder)
4913                 encoder->enable(encoder);
4914
4915         if (HAS_PCH_CPT(dev))
4916                 cpt_verify_modeset(dev, intel_crtc->pipe);
4917 }
4918
4919 /* IPS only exists on ULT machines and is tied to pipe A. */
4920 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4921 {
4922         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4923 }
4924
4925 static void haswell_crtc_enable(struct drm_crtc *crtc)
4926 {
4927         struct drm_device *dev = crtc->dev;
4928         struct drm_i915_private *dev_priv = dev->dev_private;
4929         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4930         struct intel_encoder *encoder;
4931         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4932         struct intel_crtc_state *pipe_config =
4933                 to_intel_crtc_state(crtc->state);
4934
4935         if (WARN_ON(intel_crtc->active))
4936                 return;
4937
4938         if (intel_crtc_to_shared_dpll(intel_crtc))
4939                 intel_enable_shared_dpll(intel_crtc);
4940
4941         if (intel_crtc->config->has_dp_encoder)
4942                 intel_dp_set_m_n(intel_crtc, M1_N1);
4943
4944         intel_set_pipe_timings(intel_crtc);
4945
4946         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4947                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4948                            intel_crtc->config->pixel_multiplier - 1);
4949         }
4950
4951         if (intel_crtc->config->has_pch_encoder) {
4952                 intel_cpu_transcoder_set_m_n(intel_crtc,
4953                                      &intel_crtc->config->fdi_m_n, NULL);
4954         }
4955
4956         haswell_set_pipeconf(crtc);
4957
4958         intel_set_pipe_csc(crtc);
4959
4960         intel_crtc->active = true;
4961
4962         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4963         for_each_encoder_on_crtc(dev, crtc, encoder)
4964                 if (encoder->pre_enable)
4965                         encoder->pre_enable(encoder);
4966
4967         if (intel_crtc->config->has_pch_encoder) {
4968                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4969                                                       true);
4970                 dev_priv->display.fdi_link_train(crtc);
4971         }
4972
4973         intel_ddi_enable_pipe_clock(intel_crtc);
4974
4975         if (INTEL_INFO(dev)->gen == 9)
4976                 skylake_pfit_enable(intel_crtc);
4977         else if (INTEL_INFO(dev)->gen < 9)
4978                 ironlake_pfit_enable(intel_crtc);
4979         else
4980                 MISSING_CASE(INTEL_INFO(dev)->gen);
4981
4982         /*
4983          * On ILK+ LUT must be loaded before the pipe is running but with
4984          * clocks enabled
4985          */
4986         intel_crtc_load_lut(crtc);
4987
4988         intel_ddi_set_pipe_settings(crtc);
4989         intel_ddi_enable_transcoder_func(crtc);
4990
4991         intel_update_watermarks(crtc);
4992         intel_enable_pipe(intel_crtc);
4993
4994         if (intel_crtc->config->has_pch_encoder)
4995                 lpt_pch_enable(crtc);
4996
4997         if (intel_crtc->config->dp_encoder_is_mst)
4998                 intel_ddi_set_vc_payload_alloc(crtc, true);
4999
5000         assert_vblank_disabled(crtc);
5001         drm_crtc_vblank_on(crtc);
5002
5003         for_each_encoder_on_crtc(dev, crtc, encoder) {
5004                 encoder->enable(encoder);
5005                 intel_opregion_notify_encoder(encoder, true);
5006         }
5007
5008         /* If we change the relative order between pipe/planes enabling, we need
5009          * to change the workaround. */
5010         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5011         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5012                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5013                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5014         }
5015 }
5016
5017 static void ironlake_pfit_disable(struct intel_crtc *crtc)
5018 {
5019         struct drm_device *dev = crtc->base.dev;
5020         struct drm_i915_private *dev_priv = dev->dev_private;
5021         int pipe = crtc->pipe;
5022
5023         /* To avoid upsetting the power well on haswell only disable the pfit if
5024          * it's in use. The hw state code will make sure we get this right. */
5025         if (crtc->config->pch_pfit.enabled) {
5026                 I915_WRITE(PF_CTL(pipe), 0);
5027                 I915_WRITE(PF_WIN_POS(pipe), 0);
5028                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5029         }
5030 }
5031
5032 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5033 {
5034         struct drm_device *dev = crtc->dev;
5035         struct drm_i915_private *dev_priv = dev->dev_private;
5036         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5037         struct intel_encoder *encoder;
5038         int pipe = intel_crtc->pipe;
5039         u32 reg, temp;
5040
5041         for_each_encoder_on_crtc(dev, crtc, encoder)
5042                 encoder->disable(encoder);
5043
5044         drm_crtc_vblank_off(crtc);
5045         assert_vblank_disabled(crtc);
5046
5047         if (intel_crtc->config->has_pch_encoder)
5048                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5049
5050         intel_disable_pipe(intel_crtc);
5051
5052         ironlake_pfit_disable(intel_crtc);
5053
5054         if (intel_crtc->config->has_pch_encoder)
5055                 ironlake_fdi_disable(crtc);
5056
5057         for_each_encoder_on_crtc(dev, crtc, encoder)
5058                 if (encoder->post_disable)
5059                         encoder->post_disable(encoder);
5060
5061         if (intel_crtc->config->has_pch_encoder) {
5062                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5063
5064                 if (HAS_PCH_CPT(dev)) {
5065                         /* disable TRANS_DP_CTL */
5066                         reg = TRANS_DP_CTL(pipe);
5067                         temp = I915_READ(reg);
5068                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5069                                   TRANS_DP_PORT_SEL_MASK);
5070                         temp |= TRANS_DP_PORT_SEL_NONE;
5071                         I915_WRITE(reg, temp);
5072
5073                         /* disable DPLL_SEL */
5074                         temp = I915_READ(PCH_DPLL_SEL);
5075                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5076                         I915_WRITE(PCH_DPLL_SEL, temp);
5077                 }
5078
5079                 ironlake_fdi_pll_disable(intel_crtc);
5080         }
5081
5082         intel_crtc->active = false;
5083         intel_update_watermarks(crtc);
5084 }
5085
5086 static void haswell_crtc_disable(struct drm_crtc *crtc)
5087 {
5088         struct drm_device *dev = crtc->dev;
5089         struct drm_i915_private *dev_priv = dev->dev_private;
5090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5091         struct intel_encoder *encoder;
5092         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5093
5094         for_each_encoder_on_crtc(dev, crtc, encoder) {
5095                 intel_opregion_notify_encoder(encoder, false);
5096                 encoder->disable(encoder);
5097         }
5098
5099         drm_crtc_vblank_off(crtc);
5100         assert_vblank_disabled(crtc);
5101
5102         if (intel_crtc->config->has_pch_encoder)
5103                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5104                                                       false);
5105         intel_disable_pipe(intel_crtc);
5106
5107         if (intel_crtc->config->dp_encoder_is_mst)
5108                 intel_ddi_set_vc_payload_alloc(crtc, false);
5109
5110         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5111
5112         if (INTEL_INFO(dev)->gen == 9)
5113                 skylake_scaler_disable(intel_crtc);
5114         else if (INTEL_INFO(dev)->gen < 9)
5115                 ironlake_pfit_disable(intel_crtc);
5116         else
5117                 MISSING_CASE(INTEL_INFO(dev)->gen);
5118
5119         intel_ddi_disable_pipe_clock(intel_crtc);
5120
5121         if (intel_crtc->config->has_pch_encoder) {
5122                 lpt_disable_pch_transcoder(dev_priv);
5123                 intel_ddi_fdi_disable(crtc);
5124         }
5125
5126         for_each_encoder_on_crtc(dev, crtc, encoder)
5127                 if (encoder->post_disable)
5128                         encoder->post_disable(encoder);
5129
5130         intel_crtc->active = false;
5131         intel_update_watermarks(crtc);
5132 }
5133
5134 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5135 {
5136         struct drm_device *dev = crtc->base.dev;
5137         struct drm_i915_private *dev_priv = dev->dev_private;
5138         struct intel_crtc_state *pipe_config = crtc->config;
5139
5140         if (!pipe_config->gmch_pfit.control)
5141                 return;
5142
5143         /*
5144          * The panel fitter should only be adjusted whilst the pipe is disabled,
5145          * according to register description and PRM.
5146          */
5147         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5148         assert_pipe_disabled(dev_priv, crtc->pipe);
5149
5150         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5151         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5152
5153         /* Border color in case we don't scale up to the full screen. Black by
5154          * default, change to something else for debugging. */
5155         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5156 }
5157
5158 static enum intel_display_power_domain port_to_power_domain(enum port port)
5159 {
5160         switch (port) {
5161         case PORT_A:
5162                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5163         case PORT_B:
5164                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5165         case PORT_C:
5166                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5167         case PORT_D:
5168                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5169         case PORT_E:
5170                 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
5171         default:
5172                 WARN_ON_ONCE(1);
5173                 return POWER_DOMAIN_PORT_OTHER;
5174         }
5175 }
5176
5177 #define for_each_power_domain(domain, mask)                             \
5178         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
5179                 if ((1 << (domain)) & (mask))
5180
5181 enum intel_display_power_domain
5182 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5183 {
5184         struct drm_device *dev = intel_encoder->base.dev;
5185         struct intel_digital_port *intel_dig_port;
5186
5187         switch (intel_encoder->type) {
5188         case INTEL_OUTPUT_UNKNOWN:
5189                 /* Only DDI platforms should ever use this output type */
5190                 WARN_ON_ONCE(!HAS_DDI(dev));
5191         case INTEL_OUTPUT_DISPLAYPORT:
5192         case INTEL_OUTPUT_HDMI:
5193         case INTEL_OUTPUT_EDP:
5194                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5195                 return port_to_power_domain(intel_dig_port->port);
5196         case INTEL_OUTPUT_DP_MST:
5197                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5198                 return port_to_power_domain(intel_dig_port->port);
5199         case INTEL_OUTPUT_ANALOG:
5200                 return POWER_DOMAIN_PORT_CRT;
5201         case INTEL_OUTPUT_DSI:
5202                 return POWER_DOMAIN_PORT_DSI;
5203         default:
5204                 return POWER_DOMAIN_PORT_OTHER;
5205         }
5206 }
5207
5208 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5209 {
5210         struct drm_device *dev = crtc->dev;
5211         struct intel_encoder *intel_encoder;
5212         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5213         enum pipe pipe = intel_crtc->pipe;
5214         unsigned long mask;
5215         enum transcoder transcoder;
5216
5217         if (!crtc->state->active)
5218                 return 0;
5219
5220         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5221
5222         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5223         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5224         if (intel_crtc->config->pch_pfit.enabled ||
5225             intel_crtc->config->pch_pfit.force_thru)
5226                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5227
5228         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5229                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5230
5231         return mask;
5232 }
5233
5234 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5235 {
5236         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5237         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5238         enum intel_display_power_domain domain;
5239         unsigned long domains, new_domains, old_domains;
5240
5241         old_domains = intel_crtc->enabled_power_domains;
5242         intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5243
5244         domains = new_domains & ~old_domains;
5245
5246         for_each_power_domain(domain, domains)
5247                 intel_display_power_get(dev_priv, domain);
5248
5249         return old_domains & ~new_domains;
5250 }
5251
5252 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5253                                       unsigned long domains)
5254 {
5255         enum intel_display_power_domain domain;
5256
5257         for_each_power_domain(domain, domains)
5258                 intel_display_power_put(dev_priv, domain);
5259 }
5260
5261 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5262 {
5263         struct drm_device *dev = state->dev;
5264         struct drm_i915_private *dev_priv = dev->dev_private;
5265         unsigned long put_domains[I915_MAX_PIPES] = {};
5266         struct drm_crtc_state *crtc_state;
5267         struct drm_crtc *crtc;
5268         int i;
5269
5270         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5271                 if (needs_modeset(crtc->state))
5272                         put_domains[to_intel_crtc(crtc)->pipe] =
5273                                 modeset_get_crtc_power_domains(crtc);
5274         }
5275
5276         if (dev_priv->display.modeset_commit_cdclk) {
5277                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5278
5279                 if (cdclk != dev_priv->cdclk_freq &&
5280                     !WARN_ON(!state->allow_modeset))
5281                         dev_priv->display.modeset_commit_cdclk(state);
5282         }
5283
5284         for (i = 0; i < I915_MAX_PIPES; i++)
5285                 if (put_domains[i])
5286                         modeset_put_power_domains(dev_priv, put_domains[i]);
5287 }
5288
5289 static void intel_update_max_cdclk(struct drm_device *dev)
5290 {
5291         struct drm_i915_private *dev_priv = dev->dev_private;
5292
5293         if (IS_SKYLAKE(dev)) {
5294                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5295
5296                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5297                         dev_priv->max_cdclk_freq = 675000;
5298                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5299                         dev_priv->max_cdclk_freq = 540000;
5300                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5301                         dev_priv->max_cdclk_freq = 450000;
5302                 else
5303                         dev_priv->max_cdclk_freq = 337500;
5304         } else if (IS_BROADWELL(dev))  {
5305                 /*
5306                  * FIXME with extra cooling we can allow
5307                  * 540 MHz for ULX and 675 Mhz for ULT.
5308                  * How can we know if extra cooling is
5309                  * available? PCI ID, VTB, something else?
5310                  */
5311                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5312                         dev_priv->max_cdclk_freq = 450000;
5313                 else if (IS_BDW_ULX(dev))
5314                         dev_priv->max_cdclk_freq = 450000;
5315                 else if (IS_BDW_ULT(dev))
5316                         dev_priv->max_cdclk_freq = 540000;
5317                 else
5318                         dev_priv->max_cdclk_freq = 675000;
5319         } else if (IS_CHERRYVIEW(dev)) {
5320                 dev_priv->max_cdclk_freq = 320000;
5321         } else if (IS_VALLEYVIEW(dev)) {
5322                 dev_priv->max_cdclk_freq = 400000;
5323         } else {
5324                 /* otherwise assume cdclk is fixed */
5325                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5326         }
5327
5328         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5329                          dev_priv->max_cdclk_freq);
5330 }
5331
5332 static void intel_update_cdclk(struct drm_device *dev)
5333 {
5334         struct drm_i915_private *dev_priv = dev->dev_private;
5335
5336         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5337         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5338                          dev_priv->cdclk_freq);
5339
5340         /*
5341          * Program the gmbus_freq based on the cdclk frequency.
5342          * BSpec erroneously claims we should aim for 4MHz, but
5343          * in fact 1MHz is the correct frequency.
5344          */
5345         if (IS_VALLEYVIEW(dev)) {
5346                 /*
5347                  * Program the gmbus_freq based on the cdclk frequency.
5348                  * BSpec erroneously claims we should aim for 4MHz, but
5349                  * in fact 1MHz is the correct frequency.
5350                  */
5351                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5352         }
5353
5354         if (dev_priv->max_cdclk_freq == 0)
5355                 intel_update_max_cdclk(dev);
5356 }
5357
5358 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5359 {
5360         struct drm_i915_private *dev_priv = dev->dev_private;
5361         uint32_t divider;
5362         uint32_t ratio;
5363         uint32_t current_freq;
5364         int ret;
5365
5366         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5367         switch (frequency) {
5368         case 144000:
5369                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5370                 ratio = BXT_DE_PLL_RATIO(60);
5371                 break;
5372         case 288000:
5373                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5374                 ratio = BXT_DE_PLL_RATIO(60);
5375                 break;
5376         case 384000:
5377                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5378                 ratio = BXT_DE_PLL_RATIO(60);
5379                 break;
5380         case 576000:
5381                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5382                 ratio = BXT_DE_PLL_RATIO(60);
5383                 break;
5384         case 624000:
5385                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5386                 ratio = BXT_DE_PLL_RATIO(65);
5387                 break;
5388         case 19200:
5389                 /*
5390                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5391                  * to suppress GCC warning.
5392                  */
5393                 ratio = 0;
5394                 divider = 0;
5395                 break;
5396         default:
5397                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5398
5399                 return;
5400         }
5401
5402         mutex_lock(&dev_priv->rps.hw_lock);
5403         /* Inform power controller of upcoming frequency change */
5404         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5405                                       0x80000000);
5406         mutex_unlock(&dev_priv->rps.hw_lock);
5407
5408         if (ret) {
5409                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5410                           ret, frequency);
5411                 return;
5412         }
5413
5414         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5415         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5416         current_freq = current_freq * 500 + 1000;
5417
5418         /*
5419          * DE PLL has to be disabled when
5420          * - setting to 19.2MHz (bypass, PLL isn't used)
5421          * - before setting to 624MHz (PLL needs toggling)
5422          * - before setting to any frequency from 624MHz (PLL needs toggling)
5423          */
5424         if (frequency == 19200 || frequency == 624000 ||
5425             current_freq == 624000) {
5426                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5427                 /* Timeout 200us */
5428                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5429                              1))
5430                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5431         }
5432
5433         if (frequency != 19200) {
5434                 uint32_t val;
5435
5436                 val = I915_READ(BXT_DE_PLL_CTL);
5437                 val &= ~BXT_DE_PLL_RATIO_MASK;
5438                 val |= ratio;
5439                 I915_WRITE(BXT_DE_PLL_CTL, val);
5440
5441                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5442                 /* Timeout 200us */
5443                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5444                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5445
5446                 val = I915_READ(CDCLK_CTL);
5447                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5448                 val |= divider;
5449                 /*
5450                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5451                  * enable otherwise.
5452                  */
5453                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5454                 if (frequency >= 500000)
5455                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5456
5457                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5458                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5459                 val |= (frequency - 1000) / 500;
5460                 I915_WRITE(CDCLK_CTL, val);
5461         }
5462
5463         mutex_lock(&dev_priv->rps.hw_lock);
5464         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5465                                       DIV_ROUND_UP(frequency, 25000));
5466         mutex_unlock(&dev_priv->rps.hw_lock);
5467
5468         if (ret) {
5469                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5470                           ret, frequency);
5471                 return;
5472         }
5473
5474         intel_update_cdclk(dev);
5475 }
5476
5477 void broxton_init_cdclk(struct drm_device *dev)
5478 {
5479         struct drm_i915_private *dev_priv = dev->dev_private;
5480         uint32_t val;
5481
5482         /*
5483          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5484          * or else the reset will hang because there is no PCH to respond.
5485          * Move the handshake programming to initialization sequence.
5486          * Previously was left up to BIOS.
5487          */
5488         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5489         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5490         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5491
5492         /* Enable PG1 for cdclk */
5493         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5494
5495         /* check if cd clock is enabled */
5496         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5497                 DRM_DEBUG_KMS("Display already initialized\n");
5498                 return;
5499         }
5500
5501         /*
5502          * FIXME:
5503          * - The initial CDCLK needs to be read from VBT.
5504          *   Need to make this change after VBT has changes for BXT.
5505          * - check if setting the max (or any) cdclk freq is really necessary
5506          *   here, it belongs to modeset time
5507          */
5508         broxton_set_cdclk(dev, 624000);
5509
5510         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5511         POSTING_READ(DBUF_CTL);
5512
5513         udelay(10);
5514
5515         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5516                 DRM_ERROR("DBuf power enable timeout!\n");
5517 }
5518
5519 void broxton_uninit_cdclk(struct drm_device *dev)
5520 {
5521         struct drm_i915_private *dev_priv = dev->dev_private;
5522
5523         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5524         POSTING_READ(DBUF_CTL);
5525
5526         udelay(10);
5527
5528         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5529                 DRM_ERROR("DBuf power disable timeout!\n");
5530
5531         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5532         broxton_set_cdclk(dev, 19200);
5533
5534         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5535 }
5536
5537 static const struct skl_cdclk_entry {
5538         unsigned int freq;
5539         unsigned int vco;
5540 } skl_cdclk_frequencies[] = {
5541         { .freq = 308570, .vco = 8640 },
5542         { .freq = 337500, .vco = 8100 },
5543         { .freq = 432000, .vco = 8640 },
5544         { .freq = 450000, .vco = 8100 },
5545         { .freq = 540000, .vco = 8100 },
5546         { .freq = 617140, .vco = 8640 },
5547         { .freq = 675000, .vco = 8100 },
5548 };
5549
5550 static unsigned int skl_cdclk_decimal(unsigned int freq)
5551 {
5552         return (freq - 1000) / 500;
5553 }
5554
5555 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5556 {
5557         unsigned int i;
5558
5559         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5560                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5561
5562                 if (e->freq == freq)
5563                         return e->vco;
5564         }
5565
5566         return 8100;
5567 }
5568
5569 static void
5570 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5571 {
5572         unsigned int min_freq;
5573         u32 val;
5574
5575         /* select the minimum CDCLK before enabling DPLL 0 */
5576         val = I915_READ(CDCLK_CTL);
5577         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5578         val |= CDCLK_FREQ_337_308;
5579
5580         if (required_vco == 8640)
5581                 min_freq = 308570;
5582         else
5583                 min_freq = 337500;
5584
5585         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5586
5587         I915_WRITE(CDCLK_CTL, val);
5588         POSTING_READ(CDCLK_CTL);
5589
5590         /*
5591          * We always enable DPLL0 with the lowest link rate possible, but still
5592          * taking into account the VCO required to operate the eDP panel at the
5593          * desired frequency. The usual DP link rates operate with a VCO of
5594          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5595          * The modeset code is responsible for the selection of the exact link
5596          * rate later on, with the constraint of choosing a frequency that
5597          * works with required_vco.
5598          */
5599         val = I915_READ(DPLL_CTRL1);
5600
5601         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5602                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5603         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5604         if (required_vco == 8640)
5605                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5606                                             SKL_DPLL0);
5607         else
5608                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5609                                             SKL_DPLL0);
5610
5611         I915_WRITE(DPLL_CTRL1, val);
5612         POSTING_READ(DPLL_CTRL1);
5613
5614         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5615
5616         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5617                 DRM_ERROR("DPLL0 not locked\n");
5618 }
5619
5620 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5621 {
5622         int ret;
5623         u32 val;
5624
5625         /* inform PCU we want to change CDCLK */
5626         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5627         mutex_lock(&dev_priv->rps.hw_lock);
5628         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5629         mutex_unlock(&dev_priv->rps.hw_lock);
5630
5631         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5632 }
5633
5634 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5635 {
5636         unsigned int i;
5637
5638         for (i = 0; i < 15; i++) {
5639                 if (skl_cdclk_pcu_ready(dev_priv))
5640                         return true;
5641                 udelay(10);
5642         }
5643
5644         return false;
5645 }
5646
5647 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5648 {
5649         struct drm_device *dev = dev_priv->dev;
5650         u32 freq_select, pcu_ack;
5651
5652         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5653
5654         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5655                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5656                 return;
5657         }
5658
5659         /* set CDCLK_CTL */
5660         switch(freq) {
5661         case 450000:
5662         case 432000:
5663                 freq_select = CDCLK_FREQ_450_432;
5664                 pcu_ack = 1;
5665                 break;
5666         case 540000:
5667                 freq_select = CDCLK_FREQ_540;
5668                 pcu_ack = 2;
5669                 break;
5670         case 308570:
5671         case 337500:
5672         default:
5673                 freq_select = CDCLK_FREQ_337_308;
5674                 pcu_ack = 0;
5675                 break;
5676         case 617140:
5677         case 675000:
5678                 freq_select = CDCLK_FREQ_675_617;
5679                 pcu_ack = 3;
5680                 break;
5681         }
5682
5683         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5684         POSTING_READ(CDCLK_CTL);
5685
5686         /* inform PCU of the change */
5687         mutex_lock(&dev_priv->rps.hw_lock);
5688         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5689         mutex_unlock(&dev_priv->rps.hw_lock);
5690
5691         intel_update_cdclk(dev);
5692 }
5693
5694 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5695 {
5696         /* disable DBUF power */
5697         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5698         POSTING_READ(DBUF_CTL);
5699
5700         udelay(10);
5701
5702         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5703                 DRM_ERROR("DBuf power disable timeout\n");
5704
5705         /* disable DPLL0 */
5706         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5707         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5708                 DRM_ERROR("Couldn't disable DPLL0\n");
5709
5710         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5711 }
5712
5713 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5714 {
5715         u32 val;
5716         unsigned int required_vco;
5717
5718         /* enable PCH reset handshake */
5719         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5720         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5721
5722         /* enable PG1 and Misc I/O */
5723         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5724
5725         /* DPLL0 not enabled (happens on early BIOS versions) */
5726         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5727                 /* enable DPLL0 */
5728                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5729                 skl_dpll0_enable(dev_priv, required_vco);
5730         }
5731
5732         /* set CDCLK to the frequency the BIOS chose */
5733         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5734
5735         /* enable DBUF power */
5736         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5737         POSTING_READ(DBUF_CTL);
5738
5739         udelay(10);
5740
5741         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5742                 DRM_ERROR("DBuf power enable timeout\n");
5743 }
5744
5745 /* returns HPLL frequency in kHz */
5746 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5747 {
5748         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5749
5750         /* Obtain SKU information */
5751         mutex_lock(&dev_priv->sb_lock);
5752         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5753                 CCK_FUSE_HPLL_FREQ_MASK;
5754         mutex_unlock(&dev_priv->sb_lock);
5755
5756         return vco_freq[hpll_freq] * 1000;
5757 }
5758
5759 /* Adjust CDclk dividers to allow high res or save power if possible */
5760 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5761 {
5762         struct drm_i915_private *dev_priv = dev->dev_private;
5763         u32 val, cmd;
5764
5765         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5766                                         != dev_priv->cdclk_freq);
5767
5768         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5769                 cmd = 2;
5770         else if (cdclk == 266667)
5771                 cmd = 1;
5772         else
5773                 cmd = 0;
5774
5775         mutex_lock(&dev_priv->rps.hw_lock);
5776         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5777         val &= ~DSPFREQGUAR_MASK;
5778         val |= (cmd << DSPFREQGUAR_SHIFT);
5779         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5780         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5781                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5782                      50)) {
5783                 DRM_ERROR("timed out waiting for CDclk change\n");
5784         }
5785         mutex_unlock(&dev_priv->rps.hw_lock);
5786
5787         mutex_lock(&dev_priv->sb_lock);
5788
5789         if (cdclk == 400000) {
5790                 u32 divider;
5791
5792                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5793
5794                 /* adjust cdclk divider */
5795                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5796                 val &= ~DISPLAY_FREQUENCY_VALUES;
5797                 val |= divider;
5798                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5799
5800                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5801                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5802                              50))
5803                         DRM_ERROR("timed out waiting for CDclk change\n");
5804         }
5805
5806         /* adjust self-refresh exit latency value */
5807         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5808         val &= ~0x7f;
5809
5810         /*
5811          * For high bandwidth configs, we set a higher latency in the bunit
5812          * so that the core display fetch happens in time to avoid underruns.
5813          */
5814         if (cdclk == 400000)
5815                 val |= 4500 / 250; /* 4.5 usec */
5816         else
5817                 val |= 3000 / 250; /* 3.0 usec */
5818         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5819
5820         mutex_unlock(&dev_priv->sb_lock);
5821
5822         intel_update_cdclk(dev);
5823 }
5824
5825 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5826 {
5827         struct drm_i915_private *dev_priv = dev->dev_private;
5828         u32 val, cmd;
5829
5830         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5831                                                 != dev_priv->cdclk_freq);
5832
5833         switch (cdclk) {
5834         case 333333:
5835         case 320000:
5836         case 266667:
5837         case 200000:
5838                 break;
5839         default:
5840                 MISSING_CASE(cdclk);
5841                 return;
5842         }
5843
5844         /*
5845          * Specs are full of misinformation, but testing on actual
5846          * hardware has shown that we just need to write the desired
5847          * CCK divider into the Punit register.
5848          */
5849         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5850
5851         mutex_lock(&dev_priv->rps.hw_lock);
5852         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5853         val &= ~DSPFREQGUAR_MASK_CHV;
5854         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5855         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5856         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5857                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5858                      50)) {
5859                 DRM_ERROR("timed out waiting for CDclk change\n");
5860         }
5861         mutex_unlock(&dev_priv->rps.hw_lock);
5862
5863         intel_update_cdclk(dev);
5864 }
5865
5866 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5867                                  int max_pixclk)
5868 {
5869         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5870         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5871
5872         /*
5873          * Really only a few cases to deal with, as only 4 CDclks are supported:
5874          *   200MHz
5875          *   267MHz
5876          *   320/333MHz (depends on HPLL freq)
5877          *   400MHz (VLV only)
5878          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5879          * of the lower bin and adjust if needed.
5880          *
5881          * We seem to get an unstable or solid color picture at 200MHz.
5882          * Not sure what's wrong. For now use 200MHz only when all pipes
5883          * are off.
5884          */
5885         if (!IS_CHERRYVIEW(dev_priv) &&
5886             max_pixclk > freq_320*limit/100)
5887                 return 400000;
5888         else if (max_pixclk > 266667*limit/100)
5889                 return freq_320;
5890         else if (max_pixclk > 0)
5891                 return 266667;
5892         else
5893                 return 200000;
5894 }
5895
5896 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5897                               int max_pixclk)
5898 {
5899         /*
5900          * FIXME:
5901          * - remove the guardband, it's not needed on BXT
5902          * - set 19.2MHz bypass frequency if there are no active pipes
5903          */
5904         if (max_pixclk > 576000*9/10)
5905                 return 624000;
5906         else if (max_pixclk > 384000*9/10)
5907                 return 576000;
5908         else if (max_pixclk > 288000*9/10)
5909                 return 384000;
5910         else if (max_pixclk > 144000*9/10)
5911                 return 288000;
5912         else
5913                 return 144000;
5914 }
5915
5916 /* Compute the max pixel clock for new configuration. Uses atomic state if
5917  * that's non-NULL, look at current state otherwise. */
5918 static int intel_mode_max_pixclk(struct drm_device *dev,
5919                                  struct drm_atomic_state *state)
5920 {
5921         struct intel_crtc *intel_crtc;
5922         struct intel_crtc_state *crtc_state;
5923         int max_pixclk = 0;
5924
5925         for_each_intel_crtc(dev, intel_crtc) {
5926                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5927                 if (IS_ERR(crtc_state))
5928                         return PTR_ERR(crtc_state);
5929
5930                 if (!crtc_state->base.enable)
5931                         continue;
5932
5933                 max_pixclk = max(max_pixclk,
5934                                  crtc_state->base.adjusted_mode.crtc_clock);
5935         }
5936
5937         return max_pixclk;
5938 }
5939
5940 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5941 {
5942         struct drm_device *dev = state->dev;
5943         struct drm_i915_private *dev_priv = dev->dev_private;
5944         int max_pixclk = intel_mode_max_pixclk(dev, state);
5945
5946         if (max_pixclk < 0)
5947                 return max_pixclk;
5948
5949         to_intel_atomic_state(state)->cdclk =
5950                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5951
5952         return 0;
5953 }
5954
5955 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5956 {
5957         struct drm_device *dev = state->dev;
5958         struct drm_i915_private *dev_priv = dev->dev_private;
5959         int max_pixclk = intel_mode_max_pixclk(dev, state);
5960
5961         if (max_pixclk < 0)
5962                 return max_pixclk;
5963
5964         to_intel_atomic_state(state)->cdclk =
5965                 broxton_calc_cdclk(dev_priv, max_pixclk);
5966
5967         return 0;
5968 }
5969
5970 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5971 {
5972         unsigned int credits, default_credits;
5973
5974         if (IS_CHERRYVIEW(dev_priv))
5975                 default_credits = PFI_CREDIT(12);
5976         else
5977                 default_credits = PFI_CREDIT(8);
5978
5979         if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5980                 /* CHV suggested value is 31 or 63 */
5981                 if (IS_CHERRYVIEW(dev_priv))
5982                         credits = PFI_CREDIT_63;
5983                 else
5984                         credits = PFI_CREDIT(15);
5985         } else {
5986                 credits = default_credits;
5987         }
5988
5989         /*
5990          * WA - write default credits before re-programming
5991          * FIXME: should we also set the resend bit here?
5992          */
5993         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5994                    default_credits);
5995
5996         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5997                    credits | PFI_CREDIT_RESEND);
5998
5999         /*
6000          * FIXME is this guaranteed to clear
6001          * immediately or should we poll for it?
6002          */
6003         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6004 }
6005
6006 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6007 {
6008         struct drm_device *dev = old_state->dev;
6009         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6010         struct drm_i915_private *dev_priv = dev->dev_private;
6011
6012         /*
6013          * FIXME: We can end up here with all power domains off, yet
6014          * with a CDCLK frequency other than the minimum. To account
6015          * for this take the PIPE-A power domain, which covers the HW
6016          * blocks needed for the following programming. This can be
6017          * removed once it's guaranteed that we get here either with
6018          * the minimum CDCLK set, or the required power domains
6019          * enabled.
6020          */
6021         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6022
6023         if (IS_CHERRYVIEW(dev))
6024                 cherryview_set_cdclk(dev, req_cdclk);
6025         else
6026                 valleyview_set_cdclk(dev, req_cdclk);
6027
6028         vlv_program_pfi_credits(dev_priv);
6029
6030         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6031 }
6032
6033 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6034 {
6035         struct drm_device *dev = crtc->dev;
6036         struct drm_i915_private *dev_priv = to_i915(dev);
6037         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6038         struct intel_encoder *encoder;
6039         int pipe = intel_crtc->pipe;
6040         bool is_dsi;
6041
6042         if (WARN_ON(intel_crtc->active))
6043                 return;
6044
6045         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6046
6047         if (!is_dsi) {
6048                 if (IS_CHERRYVIEW(dev))
6049                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6050                 else
6051                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6052         }
6053
6054         if (intel_crtc->config->has_dp_encoder)
6055                 intel_dp_set_m_n(intel_crtc, M1_N1);
6056
6057         intel_set_pipe_timings(intel_crtc);
6058
6059         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6060                 struct drm_i915_private *dev_priv = dev->dev_private;
6061
6062                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6063                 I915_WRITE(CHV_CANVAS(pipe), 0);
6064         }
6065
6066         i9xx_set_pipeconf(intel_crtc);
6067
6068         intel_crtc->active = true;
6069
6070         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6071
6072         for_each_encoder_on_crtc(dev, crtc, encoder)
6073                 if (encoder->pre_pll_enable)
6074                         encoder->pre_pll_enable(encoder);
6075
6076         if (!is_dsi) {
6077                 if (IS_CHERRYVIEW(dev))
6078                         chv_enable_pll(intel_crtc, intel_crtc->config);
6079                 else
6080                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6081         }
6082
6083         for_each_encoder_on_crtc(dev, crtc, encoder)
6084                 if (encoder->pre_enable)
6085                         encoder->pre_enable(encoder);
6086
6087         i9xx_pfit_enable(intel_crtc);
6088
6089         intel_crtc_load_lut(crtc);
6090
6091         intel_enable_pipe(intel_crtc);
6092
6093         assert_vblank_disabled(crtc);
6094         drm_crtc_vblank_on(crtc);
6095
6096         for_each_encoder_on_crtc(dev, crtc, encoder)
6097                 encoder->enable(encoder);
6098 }
6099
6100 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6101 {
6102         struct drm_device *dev = crtc->base.dev;
6103         struct drm_i915_private *dev_priv = dev->dev_private;
6104
6105         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6106         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6107 }
6108
6109 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6110 {
6111         struct drm_device *dev = crtc->dev;
6112         struct drm_i915_private *dev_priv = to_i915(dev);
6113         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6114         struct intel_encoder *encoder;
6115         int pipe = intel_crtc->pipe;
6116
6117         if (WARN_ON(intel_crtc->active))
6118                 return;
6119
6120         i9xx_set_pll_dividers(intel_crtc);
6121
6122         if (intel_crtc->config->has_dp_encoder)
6123                 intel_dp_set_m_n(intel_crtc, M1_N1);
6124
6125         intel_set_pipe_timings(intel_crtc);
6126
6127         i9xx_set_pipeconf(intel_crtc);
6128
6129         intel_crtc->active = true;
6130
6131         if (!IS_GEN2(dev))
6132                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6133
6134         for_each_encoder_on_crtc(dev, crtc, encoder)
6135                 if (encoder->pre_enable)
6136                         encoder->pre_enable(encoder);
6137
6138         i9xx_enable_pll(intel_crtc);
6139
6140         i9xx_pfit_enable(intel_crtc);
6141
6142         intel_crtc_load_lut(crtc);
6143
6144         intel_update_watermarks(crtc);
6145         intel_enable_pipe(intel_crtc);
6146
6147         assert_vblank_disabled(crtc);
6148         drm_crtc_vblank_on(crtc);
6149
6150         for_each_encoder_on_crtc(dev, crtc, encoder)
6151                 encoder->enable(encoder);
6152 }
6153
6154 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6155 {
6156         struct drm_device *dev = crtc->base.dev;
6157         struct drm_i915_private *dev_priv = dev->dev_private;
6158
6159         if (!crtc->config->gmch_pfit.control)
6160                 return;
6161
6162         assert_pipe_disabled(dev_priv, crtc->pipe);
6163
6164         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6165                          I915_READ(PFIT_CONTROL));
6166         I915_WRITE(PFIT_CONTROL, 0);
6167 }
6168
6169 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6170 {
6171         struct drm_device *dev = crtc->dev;
6172         struct drm_i915_private *dev_priv = dev->dev_private;
6173         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6174         struct intel_encoder *encoder;
6175         int pipe = intel_crtc->pipe;
6176
6177         /*
6178          * On gen2 planes are double buffered but the pipe isn't, so we must
6179          * wait for planes to fully turn off before disabling the pipe.
6180          * We also need to wait on all gmch platforms because of the
6181          * self-refresh mode constraint explained above.
6182          */
6183         intel_wait_for_vblank(dev, pipe);
6184
6185         for_each_encoder_on_crtc(dev, crtc, encoder)
6186                 encoder->disable(encoder);
6187
6188         drm_crtc_vblank_off(crtc);
6189         assert_vblank_disabled(crtc);
6190
6191         intel_disable_pipe(intel_crtc);
6192
6193         i9xx_pfit_disable(intel_crtc);
6194
6195         for_each_encoder_on_crtc(dev, crtc, encoder)
6196                 if (encoder->post_disable)
6197                         encoder->post_disable(encoder);
6198
6199         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6200                 if (IS_CHERRYVIEW(dev))
6201                         chv_disable_pll(dev_priv, pipe);
6202                 else if (IS_VALLEYVIEW(dev))
6203                         vlv_disable_pll(dev_priv, pipe);
6204                 else
6205                         i9xx_disable_pll(intel_crtc);
6206         }
6207
6208         if (!IS_GEN2(dev))
6209                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6210
6211         intel_crtc->active = false;
6212         intel_update_watermarks(crtc);
6213 }
6214
6215 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6216 {
6217         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6218         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6219         enum intel_display_power_domain domain;
6220         unsigned long domains;
6221
6222         if (!intel_crtc->active)
6223                 return;
6224
6225         if (to_intel_plane_state(crtc->primary->state)->visible) {
6226                 intel_crtc_wait_for_pending_flips(crtc);
6227                 intel_pre_disable_primary(crtc);
6228         }
6229
6230         intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6231         dev_priv->display.crtc_disable(crtc);
6232         intel_disable_shared_dpll(intel_crtc);
6233
6234         domains = intel_crtc->enabled_power_domains;
6235         for_each_power_domain(domain, domains)
6236                 intel_display_power_put(dev_priv, domain);
6237         intel_crtc->enabled_power_domains = 0;
6238 }
6239
6240 /*
6241  * turn all crtc's off, but do not adjust state
6242  * This has to be paired with a call to intel_modeset_setup_hw_state.
6243  */
6244 int intel_display_suspend(struct drm_device *dev)
6245 {
6246         struct drm_mode_config *config = &dev->mode_config;
6247         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6248         struct drm_atomic_state *state;
6249         struct drm_crtc *crtc;
6250         unsigned crtc_mask = 0;
6251         int ret = 0;
6252
6253         if (WARN_ON(!ctx))
6254                 return 0;
6255
6256         lockdep_assert_held(&ctx->ww_ctx);
6257         state = drm_atomic_state_alloc(dev);
6258         if (WARN_ON(!state))
6259                 return -ENOMEM;
6260
6261         state->acquire_ctx = ctx;
6262         state->allow_modeset = true;
6263
6264         for_each_crtc(dev, crtc) {
6265                 struct drm_crtc_state *crtc_state =
6266                         drm_atomic_get_crtc_state(state, crtc);
6267
6268                 ret = PTR_ERR_OR_ZERO(crtc_state);
6269                 if (ret)
6270                         goto free;
6271
6272                 if (!crtc_state->active)
6273                         continue;
6274
6275                 crtc_state->active = false;
6276                 crtc_mask |= 1 << drm_crtc_index(crtc);
6277         }
6278
6279         if (crtc_mask) {
6280                 ret = drm_atomic_commit(state);
6281
6282                 if (!ret) {
6283                         for_each_crtc(dev, crtc)
6284                                 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6285                                         crtc->state->active = true;
6286
6287                         return ret;
6288                 }
6289         }
6290
6291 free:
6292         if (ret)
6293                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6294         drm_atomic_state_free(state);
6295         return ret;
6296 }
6297
6298 void intel_encoder_destroy(struct drm_encoder *encoder)
6299 {
6300         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6301
6302         drm_encoder_cleanup(encoder);
6303         kfree(intel_encoder);
6304 }
6305
6306 /* Cross check the actual hw state with our own modeset state tracking (and it's
6307  * internal consistency). */
6308 static void intel_connector_check_state(struct intel_connector *connector)
6309 {
6310         struct drm_crtc *crtc = connector->base.state->crtc;
6311
6312         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6313                       connector->base.base.id,
6314                       connector->base.name);
6315
6316         if (connector->get_hw_state(connector)) {
6317                 struct intel_encoder *encoder = connector->encoder;
6318                 struct drm_connector_state *conn_state = connector->base.state;
6319
6320                 I915_STATE_WARN(!crtc,
6321                          "connector enabled without attached crtc\n");
6322
6323                 if (!crtc)
6324                         return;
6325
6326                 I915_STATE_WARN(!crtc->state->active,
6327                       "connector is active, but attached crtc isn't\n");
6328
6329                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6330                         return;
6331
6332                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6333                         "atomic encoder doesn't match attached encoder\n");
6334
6335                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6336                         "attached encoder crtc differs from connector crtc\n");
6337         } else {
6338                 I915_STATE_WARN(crtc && crtc->state->active,
6339                         "attached crtc is active, but connector isn't\n");
6340                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6341                         "best encoder set without crtc!\n");
6342         }
6343 }
6344
6345 int intel_connector_init(struct intel_connector *connector)
6346 {
6347         struct drm_connector_state *connector_state;
6348
6349         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6350         if (!connector_state)
6351                 return -ENOMEM;
6352
6353         connector->base.state = connector_state;
6354         return 0;
6355 }
6356
6357 struct intel_connector *intel_connector_alloc(void)
6358 {
6359         struct intel_connector *connector;
6360
6361         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6362         if (!connector)
6363                 return NULL;
6364
6365         if (intel_connector_init(connector) < 0) {
6366                 kfree(connector);
6367                 return NULL;
6368         }
6369
6370         return connector;
6371 }
6372
6373 /* Simple connector->get_hw_state implementation for encoders that support only
6374  * one connector and no cloning and hence the encoder state determines the state
6375  * of the connector. */
6376 bool intel_connector_get_hw_state(struct intel_connector *connector)
6377 {
6378         enum pipe pipe = 0;
6379         struct intel_encoder *encoder = connector->encoder;
6380
6381         return encoder->get_hw_state(encoder, &pipe);
6382 }
6383
6384 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6385 {
6386         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6387                 return crtc_state->fdi_lanes;
6388
6389         return 0;
6390 }
6391
6392 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6393                                      struct intel_crtc_state *pipe_config)
6394 {
6395         struct drm_atomic_state *state = pipe_config->base.state;
6396         struct intel_crtc *other_crtc;
6397         struct intel_crtc_state *other_crtc_state;
6398
6399         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6400                       pipe_name(pipe), pipe_config->fdi_lanes);
6401         if (pipe_config->fdi_lanes > 4) {
6402                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6403                               pipe_name(pipe), pipe_config->fdi_lanes);
6404                 return -EINVAL;
6405         }
6406
6407         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6408                 if (pipe_config->fdi_lanes > 2) {
6409                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6410                                       pipe_config->fdi_lanes);
6411                         return -EINVAL;
6412                 } else {
6413                         return 0;
6414                 }
6415         }
6416
6417         if (INTEL_INFO(dev)->num_pipes == 2)
6418                 return 0;
6419
6420         /* Ivybridge 3 pipe is really complicated */
6421         switch (pipe) {
6422         case PIPE_A:
6423                 return 0;
6424         case PIPE_B:
6425                 if (pipe_config->fdi_lanes <= 2)
6426                         return 0;
6427
6428                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6429                 other_crtc_state =
6430                         intel_atomic_get_crtc_state(state, other_crtc);
6431                 if (IS_ERR(other_crtc_state))
6432                         return PTR_ERR(other_crtc_state);
6433
6434                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6435                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6436                                       pipe_name(pipe), pipe_config->fdi_lanes);
6437                         return -EINVAL;
6438                 }
6439                 return 0;
6440         case PIPE_C:
6441                 if (pipe_config->fdi_lanes > 2) {
6442                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6443                                       pipe_name(pipe), pipe_config->fdi_lanes);
6444                         return -EINVAL;
6445                 }
6446
6447                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6448                 other_crtc_state =
6449                         intel_atomic_get_crtc_state(state, other_crtc);
6450                 if (IS_ERR(other_crtc_state))
6451                         return PTR_ERR(other_crtc_state);
6452
6453                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6454                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6455                         return -EINVAL;
6456                 }
6457                 return 0;
6458         default:
6459                 BUG();
6460         }
6461 }
6462
6463 #define RETRY 1
6464 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6465                                        struct intel_crtc_state *pipe_config)
6466 {
6467         struct drm_device *dev = intel_crtc->base.dev;
6468         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6469         int lane, link_bw, fdi_dotclock, ret;
6470         bool needs_recompute = false;
6471
6472 retry:
6473         /* FDI is a binary signal running at ~2.7GHz, encoding
6474          * each output octet as 10 bits. The actual frequency
6475          * is stored as a divider into a 100MHz clock, and the
6476          * mode pixel clock is stored in units of 1KHz.
6477          * Hence the bw of each lane in terms of the mode signal
6478          * is:
6479          */
6480         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6481
6482         fdi_dotclock = adjusted_mode->crtc_clock;
6483
6484         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6485                                            pipe_config->pipe_bpp);
6486
6487         pipe_config->fdi_lanes = lane;
6488
6489         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6490                                link_bw, &pipe_config->fdi_m_n);
6491
6492         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6493                                        intel_crtc->pipe, pipe_config);
6494         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6495                 pipe_config->pipe_bpp -= 2*3;
6496                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6497                               pipe_config->pipe_bpp);
6498                 needs_recompute = true;
6499                 pipe_config->bw_constrained = true;
6500
6501                 goto retry;
6502         }
6503
6504         if (needs_recompute)
6505                 return RETRY;
6506
6507         return ret;
6508 }
6509
6510 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6511                                      struct intel_crtc_state *pipe_config)
6512 {
6513         if (pipe_config->pipe_bpp > 24)
6514                 return false;
6515
6516         /* HSW can handle pixel rate up to cdclk? */
6517         if (IS_HASWELL(dev_priv->dev))
6518                 return true;
6519
6520         /*
6521          * We compare against max which means we must take
6522          * the increased cdclk requirement into account when
6523          * calculating the new cdclk.
6524          *
6525          * Should measure whether using a lower cdclk w/o IPS
6526          */
6527         return ilk_pipe_pixel_rate(pipe_config) <=
6528                 dev_priv->max_cdclk_freq * 95 / 100;
6529 }
6530
6531 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6532                                    struct intel_crtc_state *pipe_config)
6533 {
6534         struct drm_device *dev = crtc->base.dev;
6535         struct drm_i915_private *dev_priv = dev->dev_private;
6536
6537         pipe_config->ips_enabled = i915.enable_ips &&
6538                 hsw_crtc_supports_ips(crtc) &&
6539                 pipe_config_supports_ips(dev_priv, pipe_config);
6540 }
6541
6542 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6543                                      struct intel_crtc_state *pipe_config)
6544 {
6545         struct drm_device *dev = crtc->base.dev;
6546         struct drm_i915_private *dev_priv = dev->dev_private;
6547         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6548
6549         /* FIXME should check pixel clock limits on all platforms */
6550         if (INTEL_INFO(dev)->gen < 4) {
6551                 int clock_limit = dev_priv->max_cdclk_freq;
6552
6553                 /*
6554                  * Enable pixel doubling when the dot clock
6555                  * is > 90% of the (display) core speed.
6556                  *
6557                  * GDG double wide on either pipe,
6558                  * otherwise pipe A only.
6559                  */
6560                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6561                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6562                         clock_limit *= 2;
6563                         pipe_config->double_wide = true;
6564                 }
6565
6566                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6567                         return -EINVAL;
6568         }
6569
6570         /*
6571          * Pipe horizontal size must be even in:
6572          * - DVO ganged mode
6573          * - LVDS dual channel mode
6574          * - Double wide pipe
6575          */
6576         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6577              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6578                 pipe_config->pipe_src_w &= ~1;
6579
6580         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6581          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6582          */
6583         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6584                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6585                 return -EINVAL;
6586
6587         if (HAS_IPS(dev))
6588                 hsw_compute_ips_config(crtc, pipe_config);
6589
6590         if (pipe_config->has_pch_encoder)
6591                 return ironlake_fdi_compute_config(crtc, pipe_config);
6592
6593         return 0;
6594 }
6595
6596 static int skylake_get_display_clock_speed(struct drm_device *dev)
6597 {
6598         struct drm_i915_private *dev_priv = to_i915(dev);
6599         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6600         uint32_t cdctl = I915_READ(CDCLK_CTL);
6601         uint32_t linkrate;
6602
6603         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6604                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6605
6606         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6607                 return 540000;
6608
6609         linkrate = (I915_READ(DPLL_CTRL1) &
6610                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6611
6612         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6613             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6614                 /* vco 8640 */
6615                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6616                 case CDCLK_FREQ_450_432:
6617                         return 432000;
6618                 case CDCLK_FREQ_337_308:
6619                         return 308570;
6620                 case CDCLK_FREQ_675_617:
6621                         return 617140;
6622                 default:
6623                         WARN(1, "Unknown cd freq selection\n");
6624                 }
6625         } else {
6626                 /* vco 8100 */
6627                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6628                 case CDCLK_FREQ_450_432:
6629                         return 450000;
6630                 case CDCLK_FREQ_337_308:
6631                         return 337500;
6632                 case CDCLK_FREQ_675_617:
6633                         return 675000;
6634                 default:
6635                         WARN(1, "Unknown cd freq selection\n");
6636                 }
6637         }
6638
6639         /* error case, do as if DPLL0 isn't enabled */
6640         return 24000;
6641 }
6642
6643 static int broxton_get_display_clock_speed(struct drm_device *dev)
6644 {
6645         struct drm_i915_private *dev_priv = to_i915(dev);
6646         uint32_t cdctl = I915_READ(CDCLK_CTL);
6647         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6648         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6649         int cdclk;
6650
6651         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6652                 return 19200;
6653
6654         cdclk = 19200 * pll_ratio / 2;
6655
6656         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6657         case BXT_CDCLK_CD2X_DIV_SEL_1:
6658                 return cdclk;  /* 576MHz or 624MHz */
6659         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6660                 return cdclk * 2 / 3; /* 384MHz */
6661         case BXT_CDCLK_CD2X_DIV_SEL_2:
6662                 return cdclk / 2; /* 288MHz */
6663         case BXT_CDCLK_CD2X_DIV_SEL_4:
6664                 return cdclk / 4; /* 144MHz */
6665         }
6666
6667         /* error case, do as if DE PLL isn't enabled */
6668         return 19200;
6669 }
6670
6671 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6672 {
6673         struct drm_i915_private *dev_priv = dev->dev_private;
6674         uint32_t lcpll = I915_READ(LCPLL_CTL);
6675         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6676
6677         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6678                 return 800000;
6679         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6680                 return 450000;
6681         else if (freq == LCPLL_CLK_FREQ_450)
6682                 return 450000;
6683         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6684                 return 540000;
6685         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6686                 return 337500;
6687         else
6688                 return 675000;
6689 }
6690
6691 static int haswell_get_display_clock_speed(struct drm_device *dev)
6692 {
6693         struct drm_i915_private *dev_priv = dev->dev_private;
6694         uint32_t lcpll = I915_READ(LCPLL_CTL);
6695         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6696
6697         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6698                 return 800000;
6699         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6700                 return 450000;
6701         else if (freq == LCPLL_CLK_FREQ_450)
6702                 return 450000;
6703         else if (IS_HSW_ULT(dev))
6704                 return 337500;
6705         else
6706                 return 540000;
6707 }
6708
6709 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6710 {
6711         struct drm_i915_private *dev_priv = dev->dev_private;
6712         u32 val;
6713         int divider;
6714
6715         if (dev_priv->hpll_freq == 0)
6716                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6717
6718         mutex_lock(&dev_priv->sb_lock);
6719         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6720         mutex_unlock(&dev_priv->sb_lock);
6721
6722         divider = val & DISPLAY_FREQUENCY_VALUES;
6723
6724         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6725              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6726              "cdclk change in progress\n");
6727
6728         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6729 }
6730
6731 static int ilk_get_display_clock_speed(struct drm_device *dev)
6732 {
6733         return 450000;
6734 }
6735
6736 static int i945_get_display_clock_speed(struct drm_device *dev)
6737 {
6738         return 400000;
6739 }
6740
6741 static int i915_get_display_clock_speed(struct drm_device *dev)
6742 {
6743         return 333333;
6744 }
6745
6746 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6747 {
6748         return 200000;
6749 }
6750
6751 static int pnv_get_display_clock_speed(struct drm_device *dev)
6752 {
6753         u16 gcfgc = 0;
6754
6755         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6756
6757         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6758         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6759                 return 266667;
6760         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6761                 return 333333;
6762         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6763                 return 444444;
6764         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6765                 return 200000;
6766         default:
6767                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6768         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6769                 return 133333;
6770         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6771                 return 166667;
6772         }
6773 }
6774
6775 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6776 {
6777         u16 gcfgc = 0;
6778
6779         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6780
6781         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6782                 return 133333;
6783         else {
6784                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6785                 case GC_DISPLAY_CLOCK_333_MHZ:
6786                         return 333333;
6787                 default:
6788                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6789                         return 190000;
6790                 }
6791         }
6792 }
6793
6794 static int i865_get_display_clock_speed(struct drm_device *dev)
6795 {
6796         return 266667;
6797 }
6798
6799 static int i85x_get_display_clock_speed(struct drm_device *dev)
6800 {
6801         u16 hpllcc = 0;
6802
6803         /*
6804          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6805          * encoding is different :(
6806          * FIXME is this the right way to detect 852GM/852GMV?
6807          */
6808         if (dev->pdev->revision == 0x1)
6809                 return 133333;
6810
6811         pci_bus_read_config_word(dev->pdev->bus,
6812                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6813
6814         /* Assume that the hardware is in the high speed state.  This
6815          * should be the default.
6816          */
6817         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6818         case GC_CLOCK_133_200:
6819         case GC_CLOCK_133_200_2:
6820         case GC_CLOCK_100_200:
6821                 return 200000;
6822         case GC_CLOCK_166_250:
6823                 return 250000;
6824         case GC_CLOCK_100_133:
6825                 return 133333;
6826         case GC_CLOCK_133_266:
6827         case GC_CLOCK_133_266_2:
6828         case GC_CLOCK_166_266:
6829                 return 266667;
6830         }
6831
6832         /* Shouldn't happen */
6833         return 0;
6834 }
6835
6836 static int i830_get_display_clock_speed(struct drm_device *dev)
6837 {
6838         return 133333;
6839 }
6840
6841 static unsigned int intel_hpll_vco(struct drm_device *dev)
6842 {
6843         struct drm_i915_private *dev_priv = dev->dev_private;
6844         static const unsigned int blb_vco[8] = {
6845                 [0] = 3200000,
6846                 [1] = 4000000,
6847                 [2] = 5333333,
6848                 [3] = 4800000,
6849                 [4] = 6400000,
6850         };
6851         static const unsigned int pnv_vco[8] = {
6852                 [0] = 3200000,
6853                 [1] = 4000000,
6854                 [2] = 5333333,
6855                 [3] = 4800000,
6856                 [4] = 2666667,
6857         };
6858         static const unsigned int cl_vco[8] = {
6859                 [0] = 3200000,
6860                 [1] = 4000000,
6861                 [2] = 5333333,
6862                 [3] = 6400000,
6863                 [4] = 3333333,
6864                 [5] = 3566667,
6865                 [6] = 4266667,
6866         };
6867         static const unsigned int elk_vco[8] = {
6868                 [0] = 3200000,
6869                 [1] = 4000000,
6870                 [2] = 5333333,
6871                 [3] = 4800000,
6872         };
6873         static const unsigned int ctg_vco[8] = {
6874                 [0] = 3200000,
6875                 [1] = 4000000,
6876                 [2] = 5333333,
6877                 [3] = 6400000,
6878                 [4] = 2666667,
6879                 [5] = 4266667,
6880         };
6881         const unsigned int *vco_table;
6882         unsigned int vco;
6883         uint8_t tmp = 0;
6884
6885         /* FIXME other chipsets? */
6886         if (IS_GM45(dev))
6887                 vco_table = ctg_vco;
6888         else if (IS_G4X(dev))
6889                 vco_table = elk_vco;
6890         else if (IS_CRESTLINE(dev))
6891                 vco_table = cl_vco;
6892         else if (IS_PINEVIEW(dev))
6893                 vco_table = pnv_vco;
6894         else if (IS_G33(dev))
6895                 vco_table = blb_vco;
6896         else
6897                 return 0;
6898
6899         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6900
6901         vco = vco_table[tmp & 0x7];
6902         if (vco == 0)
6903                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6904         else
6905                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6906
6907         return vco;
6908 }
6909
6910 static int gm45_get_display_clock_speed(struct drm_device *dev)
6911 {
6912         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6913         uint16_t tmp = 0;
6914
6915         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6916
6917         cdclk_sel = (tmp >> 12) & 0x1;
6918
6919         switch (vco) {
6920         case 2666667:
6921         case 4000000:
6922         case 5333333:
6923                 return cdclk_sel ? 333333 : 222222;
6924         case 3200000:
6925                 return cdclk_sel ? 320000 : 228571;
6926         default:
6927                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6928                 return 222222;
6929         }
6930 }
6931
6932 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6933 {
6934         static const uint8_t div_3200[] = { 16, 10,  8 };
6935         static const uint8_t div_4000[] = { 20, 12, 10 };
6936         static const uint8_t div_5333[] = { 24, 16, 14 };
6937         const uint8_t *div_table;
6938         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6939         uint16_t tmp = 0;
6940
6941         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6942
6943         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6944
6945         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6946                 goto fail;
6947
6948         switch (vco) {
6949         case 3200000:
6950                 div_table = div_3200;
6951                 break;
6952         case 4000000:
6953                 div_table = div_4000;
6954                 break;
6955         case 5333333:
6956                 div_table = div_5333;
6957                 break;
6958         default:
6959                 goto fail;
6960         }
6961
6962         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6963
6964 fail:
6965         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6966         return 200000;
6967 }
6968
6969 static int g33_get_display_clock_speed(struct drm_device *dev)
6970 {
6971         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
6972         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
6973         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6974         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6975         const uint8_t *div_table;
6976         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6977         uint16_t tmp = 0;
6978
6979         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6980
6981         cdclk_sel = (tmp >> 4) & 0x7;
6982
6983         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6984                 goto fail;
6985
6986         switch (vco) {
6987         case 3200000:
6988                 div_table = div_3200;
6989                 break;
6990         case 4000000:
6991                 div_table = div_4000;
6992                 break;
6993         case 4800000:
6994                 div_table = div_4800;
6995                 break;
6996         case 5333333:
6997                 div_table = div_5333;
6998                 break;
6999         default:
7000                 goto fail;
7001         }
7002
7003         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7004
7005 fail:
7006         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7007         return 190476;
7008 }
7009
7010 static void
7011 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7012 {
7013         while (*num > DATA_LINK_M_N_MASK ||
7014                *den > DATA_LINK_M_N_MASK) {
7015                 *num >>= 1;
7016                 *den >>= 1;
7017         }
7018 }
7019
7020 static void compute_m_n(unsigned int m, unsigned int n,
7021                         uint32_t *ret_m, uint32_t *ret_n)
7022 {
7023         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7024         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7025         intel_reduce_m_n_ratio(ret_m, ret_n);
7026 }
7027
7028 void
7029 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7030                        int pixel_clock, int link_clock,
7031                        struct intel_link_m_n *m_n)
7032 {
7033         m_n->tu = 64;
7034
7035         compute_m_n(bits_per_pixel * pixel_clock,
7036                     link_clock * nlanes * 8,
7037                     &m_n->gmch_m, &m_n->gmch_n);
7038
7039         compute_m_n(pixel_clock, link_clock,
7040                     &m_n->link_m, &m_n->link_n);
7041 }
7042
7043 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7044 {
7045         if (i915.panel_use_ssc >= 0)
7046                 return i915.panel_use_ssc != 0;
7047         return dev_priv->vbt.lvds_use_ssc
7048                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7049 }
7050
7051 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7052                            int num_connectors)
7053 {
7054         struct drm_device *dev = crtc_state->base.crtc->dev;
7055         struct drm_i915_private *dev_priv = dev->dev_private;
7056         int refclk;
7057
7058         WARN_ON(!crtc_state->base.state);
7059
7060         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7061                 refclk = 100000;
7062         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7063             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7064                 refclk = dev_priv->vbt.lvds_ssc_freq;
7065                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7066         } else if (!IS_GEN2(dev)) {
7067                 refclk = 96000;
7068         } else {
7069                 refclk = 48000;
7070         }
7071
7072         return refclk;
7073 }
7074
7075 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7076 {
7077         return (1 << dpll->n) << 16 | dpll->m2;
7078 }
7079
7080 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7081 {
7082         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7083 }
7084
7085 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7086                                      struct intel_crtc_state *crtc_state,
7087                                      intel_clock_t *reduced_clock)
7088 {
7089         struct drm_device *dev = crtc->base.dev;
7090         u32 fp, fp2 = 0;
7091
7092         if (IS_PINEVIEW(dev)) {
7093                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7094                 if (reduced_clock)
7095                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7096         } else {
7097                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7098                 if (reduced_clock)
7099                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7100         }
7101
7102         crtc_state->dpll_hw_state.fp0 = fp;
7103
7104         crtc->lowfreq_avail = false;
7105         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7106             reduced_clock) {
7107                 crtc_state->dpll_hw_state.fp1 = fp2;
7108                 crtc->lowfreq_avail = true;
7109         } else {
7110                 crtc_state->dpll_hw_state.fp1 = fp;
7111         }
7112 }
7113
7114 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7115                 pipe)
7116 {
7117         u32 reg_val;
7118
7119         /*
7120          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7121          * and set it to a reasonable value instead.
7122          */
7123         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7124         reg_val &= 0xffffff00;
7125         reg_val |= 0x00000030;
7126         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7127
7128         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7129         reg_val &= 0x8cffffff;
7130         reg_val = 0x8c000000;
7131         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7132
7133         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7134         reg_val &= 0xffffff00;
7135         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7136
7137         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7138         reg_val &= 0x00ffffff;
7139         reg_val |= 0xb0000000;
7140         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7141 }
7142
7143 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7144                                          struct intel_link_m_n *m_n)
7145 {
7146         struct drm_device *dev = crtc->base.dev;
7147         struct drm_i915_private *dev_priv = dev->dev_private;
7148         int pipe = crtc->pipe;
7149
7150         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7151         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7152         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7153         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7154 }
7155
7156 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7157                                          struct intel_link_m_n *m_n,
7158                                          struct intel_link_m_n *m2_n2)
7159 {
7160         struct drm_device *dev = crtc->base.dev;
7161         struct drm_i915_private *dev_priv = dev->dev_private;
7162         int pipe = crtc->pipe;
7163         enum transcoder transcoder = crtc->config->cpu_transcoder;
7164
7165         if (INTEL_INFO(dev)->gen >= 5) {
7166                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7167                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7168                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7169                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7170                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7171                  * for gen < 8) and if DRRS is supported (to make sure the
7172                  * registers are not unnecessarily accessed).
7173                  */
7174                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7175                         crtc->config->has_drrs) {
7176                         I915_WRITE(PIPE_DATA_M2(transcoder),
7177                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7178                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7179                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7180                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7181                 }
7182         } else {
7183                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7184                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7185                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7186                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7187         }
7188 }
7189
7190 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7191 {
7192         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7193
7194         if (m_n == M1_N1) {
7195                 dp_m_n = &crtc->config->dp_m_n;
7196                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7197         } else if (m_n == M2_N2) {
7198
7199                 /*
7200                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7201                  * needs to be programmed into M1_N1.
7202                  */
7203                 dp_m_n = &crtc->config->dp_m2_n2;
7204         } else {
7205                 DRM_ERROR("Unsupported divider value\n");
7206                 return;
7207         }
7208
7209         if (crtc->config->has_pch_encoder)
7210                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7211         else
7212                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7213 }
7214
7215 static void vlv_compute_dpll(struct intel_crtc *crtc,
7216                              struct intel_crtc_state *pipe_config)
7217 {
7218         u32 dpll, dpll_md;
7219
7220         /*
7221          * Enable DPIO clock input. We should never disable the reference
7222          * clock for pipe B, since VGA hotplug / manual detection depends
7223          * on it.
7224          */
7225         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7226                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7227         /* We should never disable this, set it here for state tracking */
7228         if (crtc->pipe == PIPE_B)
7229                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7230         dpll |= DPLL_VCO_ENABLE;
7231         pipe_config->dpll_hw_state.dpll = dpll;
7232
7233         dpll_md = (pipe_config->pixel_multiplier - 1)
7234                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7235         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7236 }
7237
7238 static void vlv_prepare_pll(struct intel_crtc *crtc,
7239                             const struct intel_crtc_state *pipe_config)
7240 {
7241         struct drm_device *dev = crtc->base.dev;
7242         struct drm_i915_private *dev_priv = dev->dev_private;
7243         int pipe = crtc->pipe;
7244         u32 mdiv;
7245         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7246         u32 coreclk, reg_val;
7247
7248         mutex_lock(&dev_priv->sb_lock);
7249
7250         bestn = pipe_config->dpll.n;
7251         bestm1 = pipe_config->dpll.m1;
7252         bestm2 = pipe_config->dpll.m2;
7253         bestp1 = pipe_config->dpll.p1;
7254         bestp2 = pipe_config->dpll.p2;
7255
7256         /* See eDP HDMI DPIO driver vbios notes doc */
7257
7258         /* PLL B needs special handling */
7259         if (pipe == PIPE_B)
7260                 vlv_pllb_recal_opamp(dev_priv, pipe);
7261
7262         /* Set up Tx target for periodic Rcomp update */
7263         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7264
7265         /* Disable target IRef on PLL */
7266         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7267         reg_val &= 0x00ffffff;
7268         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7269
7270         /* Disable fast lock */
7271         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7272
7273         /* Set idtafcrecal before PLL is enabled */
7274         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7275         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7276         mdiv |= ((bestn << DPIO_N_SHIFT));
7277         mdiv |= (1 << DPIO_K_SHIFT);
7278
7279         /*
7280          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7281          * but we don't support that).
7282          * Note: don't use the DAC post divider as it seems unstable.
7283          */
7284         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7285         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7286
7287         mdiv |= DPIO_ENABLE_CALIBRATION;
7288         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7289
7290         /* Set HBR and RBR LPF coefficients */
7291         if (pipe_config->port_clock == 162000 ||
7292             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7293             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7294                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7295                                  0x009f0003);
7296         else
7297                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7298                                  0x00d0000f);
7299
7300         if (pipe_config->has_dp_encoder) {
7301                 /* Use SSC source */
7302                 if (pipe == PIPE_A)
7303                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7304                                          0x0df40000);
7305                 else
7306                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7307                                          0x0df70000);
7308         } else { /* HDMI or VGA */
7309                 /* Use bend source */
7310                 if (pipe == PIPE_A)
7311                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7312                                          0x0df70000);
7313                 else
7314                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7315                                          0x0df40000);
7316         }
7317
7318         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7319         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7320         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7321             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7322                 coreclk |= 0x01000000;
7323         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7324
7325         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7326         mutex_unlock(&dev_priv->sb_lock);
7327 }
7328
7329 static void chv_compute_dpll(struct intel_crtc *crtc,
7330                              struct intel_crtc_state *pipe_config)
7331 {
7332         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7333                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7334                 DPLL_VCO_ENABLE;
7335         if (crtc->pipe != PIPE_A)
7336                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7337
7338         pipe_config->dpll_hw_state.dpll_md =
7339                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7340 }
7341
7342 static void chv_prepare_pll(struct intel_crtc *crtc,
7343                             const struct intel_crtc_state *pipe_config)
7344 {
7345         struct drm_device *dev = crtc->base.dev;
7346         struct drm_i915_private *dev_priv = dev->dev_private;
7347         int pipe = crtc->pipe;
7348         int dpll_reg = DPLL(crtc->pipe);
7349         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7350         u32 loopfilter, tribuf_calcntr;
7351         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7352         u32 dpio_val;
7353         int vco;
7354
7355         bestn = pipe_config->dpll.n;
7356         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7357         bestm1 = pipe_config->dpll.m1;
7358         bestm2 = pipe_config->dpll.m2 >> 22;
7359         bestp1 = pipe_config->dpll.p1;
7360         bestp2 = pipe_config->dpll.p2;
7361         vco = pipe_config->dpll.vco;
7362         dpio_val = 0;
7363         loopfilter = 0;
7364
7365         /*
7366          * Enable Refclk and SSC
7367          */
7368         I915_WRITE(dpll_reg,
7369                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7370
7371         mutex_lock(&dev_priv->sb_lock);
7372
7373         /* p1 and p2 divider */
7374         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7375                         5 << DPIO_CHV_S1_DIV_SHIFT |
7376                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7377                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7378                         1 << DPIO_CHV_K_DIV_SHIFT);
7379
7380         /* Feedback post-divider - m2 */
7381         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7382
7383         /* Feedback refclk divider - n and m1 */
7384         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7385                         DPIO_CHV_M1_DIV_BY_2 |
7386                         1 << DPIO_CHV_N_DIV_SHIFT);
7387
7388         /* M2 fraction division */
7389         if (bestm2_frac)
7390                 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7391
7392         /* M2 fraction division enable */
7393         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7394         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7395         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7396         if (bestm2_frac)
7397                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7398         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7399
7400         /* Program digital lock detect threshold */
7401         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7402         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7403                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7404         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7405         if (!bestm2_frac)
7406                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7407         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7408
7409         /* Loop filter */
7410         if (vco == 5400000) {
7411                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7412                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7413                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7414                 tribuf_calcntr = 0x9;
7415         } else if (vco <= 6200000) {
7416                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7417                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7418                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7419                 tribuf_calcntr = 0x9;
7420         } else if (vco <= 6480000) {
7421                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7422                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7423                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7424                 tribuf_calcntr = 0x8;
7425         } else {
7426                 /* Not supported. Apply the same limits as in the max case */
7427                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7428                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7429                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7430                 tribuf_calcntr = 0;
7431         }
7432         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7433
7434         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7435         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7436         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7437         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7438
7439         /* AFC Recal */
7440         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7441                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7442                         DPIO_AFC_RECAL);
7443
7444         mutex_unlock(&dev_priv->sb_lock);
7445 }
7446
7447 /**
7448  * vlv_force_pll_on - forcibly enable just the PLL
7449  * @dev_priv: i915 private structure
7450  * @pipe: pipe PLL to enable
7451  * @dpll: PLL configuration
7452  *
7453  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7454  * in cases where we need the PLL enabled even when @pipe is not going to
7455  * be enabled.
7456  */
7457 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7458                       const struct dpll *dpll)
7459 {
7460         struct intel_crtc *crtc =
7461                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7462         struct intel_crtc_state pipe_config = {
7463                 .base.crtc = &crtc->base,
7464                 .pixel_multiplier = 1,
7465                 .dpll = *dpll,
7466         };
7467
7468         if (IS_CHERRYVIEW(dev)) {
7469                 chv_compute_dpll(crtc, &pipe_config);
7470                 chv_prepare_pll(crtc, &pipe_config);
7471                 chv_enable_pll(crtc, &pipe_config);
7472         } else {
7473                 vlv_compute_dpll(crtc, &pipe_config);
7474                 vlv_prepare_pll(crtc, &pipe_config);
7475                 vlv_enable_pll(crtc, &pipe_config);
7476         }
7477 }
7478
7479 /**
7480  * vlv_force_pll_off - forcibly disable just the PLL
7481  * @dev_priv: i915 private structure
7482  * @pipe: pipe PLL to disable
7483  *
7484  * Disable the PLL for @pipe. To be used in cases where we need
7485  * the PLL enabled even when @pipe is not going to be enabled.
7486  */
7487 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7488 {
7489         if (IS_CHERRYVIEW(dev))
7490                 chv_disable_pll(to_i915(dev), pipe);
7491         else
7492                 vlv_disable_pll(to_i915(dev), pipe);
7493 }
7494
7495 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7496                               struct intel_crtc_state *crtc_state,
7497                               intel_clock_t *reduced_clock,
7498                               int num_connectors)
7499 {
7500         struct drm_device *dev = crtc->base.dev;
7501         struct drm_i915_private *dev_priv = dev->dev_private;
7502         u32 dpll;
7503         bool is_sdvo;
7504         struct dpll *clock = &crtc_state->dpll;
7505
7506         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7507
7508         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7509                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7510
7511         dpll = DPLL_VGA_MODE_DIS;
7512
7513         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7514                 dpll |= DPLLB_MODE_LVDS;
7515         else
7516                 dpll |= DPLLB_MODE_DAC_SERIAL;
7517
7518         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7519                 dpll |= (crtc_state->pixel_multiplier - 1)
7520                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7521         }
7522
7523         if (is_sdvo)
7524                 dpll |= DPLL_SDVO_HIGH_SPEED;
7525
7526         if (crtc_state->has_dp_encoder)
7527                 dpll |= DPLL_SDVO_HIGH_SPEED;
7528
7529         /* compute bitmask from p1 value */
7530         if (IS_PINEVIEW(dev))
7531                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7532         else {
7533                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7534                 if (IS_G4X(dev) && reduced_clock)
7535                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7536         }
7537         switch (clock->p2) {
7538         case 5:
7539                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7540                 break;
7541         case 7:
7542                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7543                 break;
7544         case 10:
7545                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7546                 break;
7547         case 14:
7548                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7549                 break;
7550         }
7551         if (INTEL_INFO(dev)->gen >= 4)
7552                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7553
7554         if (crtc_state->sdvo_tv_clock)
7555                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7556         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7557                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7558                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7559         else
7560                 dpll |= PLL_REF_INPUT_DREFCLK;
7561
7562         dpll |= DPLL_VCO_ENABLE;
7563         crtc_state->dpll_hw_state.dpll = dpll;
7564
7565         if (INTEL_INFO(dev)->gen >= 4) {
7566                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7567                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7568                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7569         }
7570 }
7571
7572 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7573                               struct intel_crtc_state *crtc_state,
7574                               intel_clock_t *reduced_clock,
7575                               int num_connectors)
7576 {
7577         struct drm_device *dev = crtc->base.dev;
7578         struct drm_i915_private *dev_priv = dev->dev_private;
7579         u32 dpll;
7580         struct dpll *clock = &crtc_state->dpll;
7581
7582         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7583
7584         dpll = DPLL_VGA_MODE_DIS;
7585
7586         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7587                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7588         } else {
7589                 if (clock->p1 == 2)
7590                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7591                 else
7592                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7593                 if (clock->p2 == 4)
7594                         dpll |= PLL_P2_DIVIDE_BY_4;
7595         }
7596
7597         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7598                 dpll |= DPLL_DVO_2X_MODE;
7599
7600         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7601                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7602                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7603         else
7604                 dpll |= PLL_REF_INPUT_DREFCLK;
7605
7606         dpll |= DPLL_VCO_ENABLE;
7607         crtc_state->dpll_hw_state.dpll = dpll;
7608 }
7609
7610 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7611 {
7612         struct drm_device *dev = intel_crtc->base.dev;
7613         struct drm_i915_private *dev_priv = dev->dev_private;
7614         enum pipe pipe = intel_crtc->pipe;
7615         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7616         struct drm_display_mode *adjusted_mode =
7617                 &intel_crtc->config->base.adjusted_mode;
7618         uint32_t crtc_vtotal, crtc_vblank_end;
7619         int vsyncshift = 0;
7620
7621         /* We need to be careful not to changed the adjusted mode, for otherwise
7622          * the hw state checker will get angry at the mismatch. */
7623         crtc_vtotal = adjusted_mode->crtc_vtotal;
7624         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7625
7626         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7627                 /* the chip adds 2 halflines automatically */
7628                 crtc_vtotal -= 1;
7629                 crtc_vblank_end -= 1;
7630
7631                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7632                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7633                 else
7634                         vsyncshift = adjusted_mode->crtc_hsync_start -
7635                                 adjusted_mode->crtc_htotal / 2;
7636                 if (vsyncshift < 0)
7637                         vsyncshift += adjusted_mode->crtc_htotal;
7638         }
7639
7640         if (INTEL_INFO(dev)->gen > 3)
7641                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7642
7643         I915_WRITE(HTOTAL(cpu_transcoder),
7644                    (adjusted_mode->crtc_hdisplay - 1) |
7645                    ((adjusted_mode->crtc_htotal - 1) << 16));
7646         I915_WRITE(HBLANK(cpu_transcoder),
7647                    (adjusted_mode->crtc_hblank_start - 1) |
7648                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7649         I915_WRITE(HSYNC(cpu_transcoder),
7650                    (adjusted_mode->crtc_hsync_start - 1) |
7651                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7652
7653         I915_WRITE(VTOTAL(cpu_transcoder),
7654                    (adjusted_mode->crtc_vdisplay - 1) |
7655                    ((crtc_vtotal - 1) << 16));
7656         I915_WRITE(VBLANK(cpu_transcoder),
7657                    (adjusted_mode->crtc_vblank_start - 1) |
7658                    ((crtc_vblank_end - 1) << 16));
7659         I915_WRITE(VSYNC(cpu_transcoder),
7660                    (adjusted_mode->crtc_vsync_start - 1) |
7661                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7662
7663         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7664          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7665          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7666          * bits. */
7667         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7668             (pipe == PIPE_B || pipe == PIPE_C))
7669                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7670
7671         /* pipesrc controls the size that is scaled from, which should
7672          * always be the user's requested size.
7673          */
7674         I915_WRITE(PIPESRC(pipe),
7675                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7676                    (intel_crtc->config->pipe_src_h - 1));
7677 }
7678
7679 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7680                                    struct intel_crtc_state *pipe_config)
7681 {
7682         struct drm_device *dev = crtc->base.dev;
7683         struct drm_i915_private *dev_priv = dev->dev_private;
7684         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7685         uint32_t tmp;
7686
7687         tmp = I915_READ(HTOTAL(cpu_transcoder));
7688         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7689         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7690         tmp = I915_READ(HBLANK(cpu_transcoder));
7691         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7692         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7693         tmp = I915_READ(HSYNC(cpu_transcoder));
7694         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7695         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7696
7697         tmp = I915_READ(VTOTAL(cpu_transcoder));
7698         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7699         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7700         tmp = I915_READ(VBLANK(cpu_transcoder));
7701         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7702         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7703         tmp = I915_READ(VSYNC(cpu_transcoder));
7704         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7705         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7706
7707         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7708                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7709                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7710                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7711         }
7712
7713         tmp = I915_READ(PIPESRC(crtc->pipe));
7714         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7715         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7716
7717         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7718         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7719 }
7720
7721 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7722                                  struct intel_crtc_state *pipe_config)
7723 {
7724         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7725         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7726         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7727         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7728
7729         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7730         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7731         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7732         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7733
7734         mode->flags = pipe_config->base.adjusted_mode.flags;
7735         mode->type = DRM_MODE_TYPE_DRIVER;
7736
7737         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7738         mode->flags |= pipe_config->base.adjusted_mode.flags;
7739
7740         mode->hsync = drm_mode_hsync(mode);
7741         mode->vrefresh = drm_mode_vrefresh(mode);
7742         drm_mode_set_name(mode);
7743 }
7744
7745 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7746 {
7747         struct drm_device *dev = intel_crtc->base.dev;
7748         struct drm_i915_private *dev_priv = dev->dev_private;
7749         uint32_t pipeconf;
7750
7751         pipeconf = 0;
7752
7753         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7754             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7755                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7756
7757         if (intel_crtc->config->double_wide)
7758                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7759
7760         /* only g4x and later have fancy bpc/dither controls */
7761         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7762                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7763                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7764                         pipeconf |= PIPECONF_DITHER_EN |
7765                                     PIPECONF_DITHER_TYPE_SP;
7766
7767                 switch (intel_crtc->config->pipe_bpp) {
7768                 case 18:
7769                         pipeconf |= PIPECONF_6BPC;
7770                         break;
7771                 case 24:
7772                         pipeconf |= PIPECONF_8BPC;
7773                         break;
7774                 case 30:
7775                         pipeconf |= PIPECONF_10BPC;
7776                         break;
7777                 default:
7778                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7779                         BUG();
7780                 }
7781         }
7782
7783         if (HAS_PIPE_CXSR(dev)) {
7784                 if (intel_crtc->lowfreq_avail) {
7785                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7786                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7787                 } else {
7788                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7789                 }
7790         }
7791
7792         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7793                 if (INTEL_INFO(dev)->gen < 4 ||
7794                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7795                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7796                 else
7797                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7798         } else
7799                 pipeconf |= PIPECONF_PROGRESSIVE;
7800
7801         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7802                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7803
7804         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7805         POSTING_READ(PIPECONF(intel_crtc->pipe));
7806 }
7807
7808 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7809                                    struct intel_crtc_state *crtc_state)
7810 {
7811         struct drm_device *dev = crtc->base.dev;
7812         struct drm_i915_private *dev_priv = dev->dev_private;
7813         int refclk, num_connectors = 0;
7814         intel_clock_t clock;
7815         bool ok;
7816         bool is_dsi = false;
7817         struct intel_encoder *encoder;
7818         const intel_limit_t *limit;
7819         struct drm_atomic_state *state = crtc_state->base.state;
7820         struct drm_connector *connector;
7821         struct drm_connector_state *connector_state;
7822         int i;
7823
7824         memset(&crtc_state->dpll_hw_state, 0,
7825                sizeof(crtc_state->dpll_hw_state));
7826
7827         for_each_connector_in_state(state, connector, connector_state, i) {
7828                 if (connector_state->crtc != &crtc->base)
7829                         continue;
7830
7831                 encoder = to_intel_encoder(connector_state->best_encoder);
7832
7833                 switch (encoder->type) {
7834                 case INTEL_OUTPUT_DSI:
7835                         is_dsi = true;
7836                         break;
7837                 default:
7838                         break;
7839                 }
7840
7841                 num_connectors++;
7842         }
7843
7844         if (is_dsi)
7845                 return 0;
7846
7847         if (!crtc_state->clock_set) {
7848                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7849
7850                 /*
7851                  * Returns a set of divisors for the desired target clock with
7852                  * the given refclk, or FALSE.  The returned values represent
7853                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7854                  * 2) / p1 / p2.
7855                  */
7856                 limit = intel_limit(crtc_state, refclk);
7857                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7858                                                  crtc_state->port_clock,
7859                                                  refclk, NULL, &clock);
7860                 if (!ok) {
7861                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7862                         return -EINVAL;
7863                 }
7864
7865                 /* Compat-code for transition, will disappear. */
7866                 crtc_state->dpll.n = clock.n;
7867                 crtc_state->dpll.m1 = clock.m1;
7868                 crtc_state->dpll.m2 = clock.m2;
7869                 crtc_state->dpll.p1 = clock.p1;
7870                 crtc_state->dpll.p2 = clock.p2;
7871         }
7872
7873         if (IS_GEN2(dev)) {
7874                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7875                                   num_connectors);
7876         } else if (IS_CHERRYVIEW(dev)) {
7877                 chv_compute_dpll(crtc, crtc_state);
7878         } else if (IS_VALLEYVIEW(dev)) {
7879                 vlv_compute_dpll(crtc, crtc_state);
7880         } else {
7881                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7882                                   num_connectors);
7883         }
7884
7885         return 0;
7886 }
7887
7888 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7889                                  struct intel_crtc_state *pipe_config)
7890 {
7891         struct drm_device *dev = crtc->base.dev;
7892         struct drm_i915_private *dev_priv = dev->dev_private;
7893         uint32_t tmp;
7894
7895         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7896                 return;
7897
7898         tmp = I915_READ(PFIT_CONTROL);
7899         if (!(tmp & PFIT_ENABLE))
7900                 return;
7901
7902         /* Check whether the pfit is attached to our pipe. */
7903         if (INTEL_INFO(dev)->gen < 4) {
7904                 if (crtc->pipe != PIPE_B)
7905                         return;
7906         } else {
7907                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7908                         return;
7909         }
7910
7911         pipe_config->gmch_pfit.control = tmp;
7912         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7913         if (INTEL_INFO(dev)->gen < 5)
7914                 pipe_config->gmch_pfit.lvds_border_bits =
7915                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7916 }
7917
7918 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7919                                struct intel_crtc_state *pipe_config)
7920 {
7921         struct drm_device *dev = crtc->base.dev;
7922         struct drm_i915_private *dev_priv = dev->dev_private;
7923         int pipe = pipe_config->cpu_transcoder;
7924         intel_clock_t clock;
7925         u32 mdiv;
7926         int refclk = 100000;
7927
7928         /* In case of MIPI DPLL will not even be used */
7929         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7930                 return;
7931
7932         mutex_lock(&dev_priv->sb_lock);
7933         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7934         mutex_unlock(&dev_priv->sb_lock);
7935
7936         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7937         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7938         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7939         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7940         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7941
7942         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7943 }
7944
7945 static void
7946 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7947                               struct intel_initial_plane_config *plane_config)
7948 {
7949         struct drm_device *dev = crtc->base.dev;
7950         struct drm_i915_private *dev_priv = dev->dev_private;
7951         u32 val, base, offset;
7952         int pipe = crtc->pipe, plane = crtc->plane;
7953         int fourcc, pixel_format;
7954         unsigned int aligned_height;
7955         struct drm_framebuffer *fb;
7956         struct intel_framebuffer *intel_fb;
7957
7958         val = I915_READ(DSPCNTR(plane));
7959         if (!(val & DISPLAY_PLANE_ENABLE))
7960                 return;
7961
7962         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7963         if (!intel_fb) {
7964                 DRM_DEBUG_KMS("failed to alloc fb\n");
7965                 return;
7966         }
7967
7968         fb = &intel_fb->base;
7969
7970         if (INTEL_INFO(dev)->gen >= 4) {
7971                 if (val & DISPPLANE_TILED) {
7972                         plane_config->tiling = I915_TILING_X;
7973                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7974                 }
7975         }
7976
7977         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7978         fourcc = i9xx_format_to_fourcc(pixel_format);
7979         fb->pixel_format = fourcc;
7980         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7981
7982         if (INTEL_INFO(dev)->gen >= 4) {
7983                 if (plane_config->tiling)
7984                         offset = I915_READ(DSPTILEOFF(plane));
7985                 else
7986                         offset = I915_READ(DSPLINOFF(plane));
7987                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7988         } else {
7989                 base = I915_READ(DSPADDR(plane));
7990         }
7991         plane_config->base = base;
7992
7993         val = I915_READ(PIPESRC(pipe));
7994         fb->width = ((val >> 16) & 0xfff) + 1;
7995         fb->height = ((val >> 0) & 0xfff) + 1;
7996
7997         val = I915_READ(DSPSTRIDE(pipe));
7998         fb->pitches[0] = val & 0xffffffc0;
7999
8000         aligned_height = intel_fb_align_height(dev, fb->height,
8001                                                fb->pixel_format,
8002                                                fb->modifier[0]);
8003
8004         plane_config->size = fb->pitches[0] * aligned_height;
8005
8006         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8007                       pipe_name(pipe), plane, fb->width, fb->height,
8008                       fb->bits_per_pixel, base, fb->pitches[0],
8009                       plane_config->size);
8010
8011         plane_config->fb = intel_fb;
8012 }
8013
8014 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8015                                struct intel_crtc_state *pipe_config)
8016 {
8017         struct drm_device *dev = crtc->base.dev;
8018         struct drm_i915_private *dev_priv = dev->dev_private;
8019         int pipe = pipe_config->cpu_transcoder;
8020         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8021         intel_clock_t clock;
8022         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8023         int refclk = 100000;
8024
8025         mutex_lock(&dev_priv->sb_lock);
8026         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8027         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8028         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8029         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8030         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8031         mutex_unlock(&dev_priv->sb_lock);
8032
8033         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8034         clock.m2 = (pll_dw0 & 0xff) << 22;
8035         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8036                 clock.m2 |= pll_dw2 & 0x3fffff;
8037         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8038         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8039         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8040
8041         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8042 }
8043
8044 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8045                                  struct intel_crtc_state *pipe_config)
8046 {
8047         struct drm_device *dev = crtc->base.dev;
8048         struct drm_i915_private *dev_priv = dev->dev_private;
8049         uint32_t tmp;
8050
8051         if (!intel_display_power_is_enabled(dev_priv,
8052                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8053                 return false;
8054
8055         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8056         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8057
8058         tmp = I915_READ(PIPECONF(crtc->pipe));
8059         if (!(tmp & PIPECONF_ENABLE))
8060                 return false;
8061
8062         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8063                 switch (tmp & PIPECONF_BPC_MASK) {
8064                 case PIPECONF_6BPC:
8065                         pipe_config->pipe_bpp = 18;
8066                         break;
8067                 case PIPECONF_8BPC:
8068                         pipe_config->pipe_bpp = 24;
8069                         break;
8070                 case PIPECONF_10BPC:
8071                         pipe_config->pipe_bpp = 30;
8072                         break;
8073                 default:
8074                         break;
8075                 }
8076         }
8077
8078         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8079                 pipe_config->limited_color_range = true;
8080
8081         if (INTEL_INFO(dev)->gen < 4)
8082                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8083
8084         intel_get_pipe_timings(crtc, pipe_config);
8085
8086         i9xx_get_pfit_config(crtc, pipe_config);
8087
8088         if (INTEL_INFO(dev)->gen >= 4) {
8089                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8090                 pipe_config->pixel_multiplier =
8091                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8092                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8093                 pipe_config->dpll_hw_state.dpll_md = tmp;
8094         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8095                 tmp = I915_READ(DPLL(crtc->pipe));
8096                 pipe_config->pixel_multiplier =
8097                         ((tmp & SDVO_MULTIPLIER_MASK)
8098                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8099         } else {
8100                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8101                  * port and will be fixed up in the encoder->get_config
8102                  * function. */
8103                 pipe_config->pixel_multiplier = 1;
8104         }
8105         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8106         if (!IS_VALLEYVIEW(dev)) {
8107                 /*
8108                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8109                  * on 830. Filter it out here so that we don't
8110                  * report errors due to that.
8111                  */
8112                 if (IS_I830(dev))
8113                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8114
8115                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8116                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8117         } else {
8118                 /* Mask out read-only status bits. */
8119                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8120                                                      DPLL_PORTC_READY_MASK |
8121                                                      DPLL_PORTB_READY_MASK);
8122         }
8123
8124         if (IS_CHERRYVIEW(dev))
8125                 chv_crtc_clock_get(crtc, pipe_config);
8126         else if (IS_VALLEYVIEW(dev))
8127                 vlv_crtc_clock_get(crtc, pipe_config);
8128         else
8129                 i9xx_crtc_clock_get(crtc, pipe_config);
8130
8131         return true;
8132 }
8133
8134 static void ironlake_init_pch_refclk(struct drm_device *dev)
8135 {
8136         struct drm_i915_private *dev_priv = dev->dev_private;
8137         struct intel_encoder *encoder;
8138         u32 val, final;
8139         bool has_lvds = false;
8140         bool has_cpu_edp = false;
8141         bool has_panel = false;
8142         bool has_ck505 = false;
8143         bool can_ssc = false;
8144
8145         /* We need to take the global config into account */
8146         for_each_intel_encoder(dev, encoder) {
8147                 switch (encoder->type) {
8148                 case INTEL_OUTPUT_LVDS:
8149                         has_panel = true;
8150                         has_lvds = true;
8151                         break;
8152                 case INTEL_OUTPUT_EDP:
8153                         has_panel = true;
8154                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8155                                 has_cpu_edp = true;
8156                         break;
8157                 default:
8158                         break;
8159                 }
8160         }
8161
8162         if (HAS_PCH_IBX(dev)) {
8163                 has_ck505 = dev_priv->vbt.display_clock_mode;
8164                 can_ssc = has_ck505;
8165         } else {
8166                 has_ck505 = false;
8167                 can_ssc = true;
8168         }
8169
8170         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8171                       has_panel, has_lvds, has_ck505);
8172
8173         /* Ironlake: try to setup display ref clock before DPLL
8174          * enabling. This is only under driver's control after
8175          * PCH B stepping, previous chipset stepping should be
8176          * ignoring this setting.
8177          */
8178         val = I915_READ(PCH_DREF_CONTROL);
8179
8180         /* As we must carefully and slowly disable/enable each source in turn,
8181          * compute the final state we want first and check if we need to
8182          * make any changes at all.
8183          */
8184         final = val;
8185         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8186         if (has_ck505)
8187                 final |= DREF_NONSPREAD_CK505_ENABLE;
8188         else
8189                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8190
8191         final &= ~DREF_SSC_SOURCE_MASK;
8192         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8193         final &= ~DREF_SSC1_ENABLE;
8194
8195         if (has_panel) {
8196                 final |= DREF_SSC_SOURCE_ENABLE;
8197
8198                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8199                         final |= DREF_SSC1_ENABLE;
8200
8201                 if (has_cpu_edp) {
8202                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8203                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8204                         else
8205                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8206                 } else
8207                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8208         } else {
8209                 final |= DREF_SSC_SOURCE_DISABLE;
8210                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8211         }
8212
8213         if (final == val)
8214                 return;
8215
8216         /* Always enable nonspread source */
8217         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8218
8219         if (has_ck505)
8220                 val |= DREF_NONSPREAD_CK505_ENABLE;
8221         else
8222                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8223
8224         if (has_panel) {
8225                 val &= ~DREF_SSC_SOURCE_MASK;
8226                 val |= DREF_SSC_SOURCE_ENABLE;
8227
8228                 /* SSC must be turned on before enabling the CPU output  */
8229                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8230                         DRM_DEBUG_KMS("Using SSC on panel\n");
8231                         val |= DREF_SSC1_ENABLE;
8232                 } else
8233                         val &= ~DREF_SSC1_ENABLE;
8234
8235                 /* Get SSC going before enabling the outputs */
8236                 I915_WRITE(PCH_DREF_CONTROL, val);
8237                 POSTING_READ(PCH_DREF_CONTROL);
8238                 udelay(200);
8239
8240                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8241
8242                 /* Enable CPU source on CPU attached eDP */
8243                 if (has_cpu_edp) {
8244                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8245                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8246                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8247                         } else
8248                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8249                 } else
8250                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8251
8252                 I915_WRITE(PCH_DREF_CONTROL, val);
8253                 POSTING_READ(PCH_DREF_CONTROL);
8254                 udelay(200);
8255         } else {
8256                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8257
8258                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8259
8260                 /* Turn off CPU output */
8261                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8262
8263                 I915_WRITE(PCH_DREF_CONTROL, val);
8264                 POSTING_READ(PCH_DREF_CONTROL);
8265                 udelay(200);
8266
8267                 /* Turn off the SSC source */
8268                 val &= ~DREF_SSC_SOURCE_MASK;
8269                 val |= DREF_SSC_SOURCE_DISABLE;
8270
8271                 /* Turn off SSC1 */
8272                 val &= ~DREF_SSC1_ENABLE;
8273
8274                 I915_WRITE(PCH_DREF_CONTROL, val);
8275                 POSTING_READ(PCH_DREF_CONTROL);
8276                 udelay(200);
8277         }
8278
8279         BUG_ON(val != final);
8280 }
8281
8282 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8283 {
8284         uint32_t tmp;
8285
8286         tmp = I915_READ(SOUTH_CHICKEN2);
8287         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8288         I915_WRITE(SOUTH_CHICKEN2, tmp);
8289
8290         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8291                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8292                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8293
8294         tmp = I915_READ(SOUTH_CHICKEN2);
8295         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8296         I915_WRITE(SOUTH_CHICKEN2, tmp);
8297
8298         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8299                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8300                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8301 }
8302
8303 /* WaMPhyProgramming:hsw */
8304 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8305 {
8306         uint32_t tmp;
8307
8308         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8309         tmp &= ~(0xFF << 24);
8310         tmp |= (0x12 << 24);
8311         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8312
8313         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8314         tmp |= (1 << 11);
8315         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8316
8317         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8318         tmp |= (1 << 11);
8319         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8320
8321         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8322         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8323         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8324
8325         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8326         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8327         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8328
8329         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8330         tmp &= ~(7 << 13);
8331         tmp |= (5 << 13);
8332         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8333
8334         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8335         tmp &= ~(7 << 13);
8336         tmp |= (5 << 13);
8337         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8338
8339         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8340         tmp &= ~0xFF;
8341         tmp |= 0x1C;
8342         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8343
8344         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8345         tmp &= ~0xFF;
8346         tmp |= 0x1C;
8347         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8348
8349         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8350         tmp &= ~(0xFF << 16);
8351         tmp |= (0x1C << 16);
8352         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8353
8354         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8355         tmp &= ~(0xFF << 16);
8356         tmp |= (0x1C << 16);
8357         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8358
8359         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8360         tmp |= (1 << 27);
8361         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8362
8363         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8364         tmp |= (1 << 27);
8365         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8366
8367         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8368         tmp &= ~(0xF << 28);
8369         tmp |= (4 << 28);
8370         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8371
8372         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8373         tmp &= ~(0xF << 28);
8374         tmp |= (4 << 28);
8375         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8376 }
8377
8378 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8379  * Programming" based on the parameters passed:
8380  * - Sequence to enable CLKOUT_DP
8381  * - Sequence to enable CLKOUT_DP without spread
8382  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8383  */
8384 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8385                                  bool with_fdi)
8386 {
8387         struct drm_i915_private *dev_priv = dev->dev_private;
8388         uint32_t reg, tmp;
8389
8390         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8391                 with_spread = true;
8392         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8393                  with_fdi, "LP PCH doesn't have FDI\n"))
8394                 with_fdi = false;
8395
8396         mutex_lock(&dev_priv->sb_lock);
8397
8398         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8399         tmp &= ~SBI_SSCCTL_DISABLE;
8400         tmp |= SBI_SSCCTL_PATHALT;
8401         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8402
8403         udelay(24);
8404
8405         if (with_spread) {
8406                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8407                 tmp &= ~SBI_SSCCTL_PATHALT;
8408                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8409
8410                 if (with_fdi) {
8411                         lpt_reset_fdi_mphy(dev_priv);
8412                         lpt_program_fdi_mphy(dev_priv);
8413                 }
8414         }
8415
8416         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8417                SBI_GEN0 : SBI_DBUFF0;
8418         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8419         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8420         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8421
8422         mutex_unlock(&dev_priv->sb_lock);
8423 }
8424
8425 /* Sequence to disable CLKOUT_DP */
8426 static void lpt_disable_clkout_dp(struct drm_device *dev)
8427 {
8428         struct drm_i915_private *dev_priv = dev->dev_private;
8429         uint32_t reg, tmp;
8430
8431         mutex_lock(&dev_priv->sb_lock);
8432
8433         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8434                SBI_GEN0 : SBI_DBUFF0;
8435         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8436         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8437         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8438
8439         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8440         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8441                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8442                         tmp |= SBI_SSCCTL_PATHALT;
8443                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8444                         udelay(32);
8445                 }
8446                 tmp |= SBI_SSCCTL_DISABLE;
8447                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8448         }
8449
8450         mutex_unlock(&dev_priv->sb_lock);
8451 }
8452
8453 static void lpt_init_pch_refclk(struct drm_device *dev)
8454 {
8455         struct intel_encoder *encoder;
8456         bool has_vga = false;
8457
8458         for_each_intel_encoder(dev, encoder) {
8459                 switch (encoder->type) {
8460                 case INTEL_OUTPUT_ANALOG:
8461                         has_vga = true;
8462                         break;
8463                 default:
8464                         break;
8465                 }
8466         }
8467
8468         if (has_vga)
8469                 lpt_enable_clkout_dp(dev, true, true);
8470         else
8471                 lpt_disable_clkout_dp(dev);
8472 }
8473
8474 /*
8475  * Initialize reference clocks when the driver loads
8476  */
8477 void intel_init_pch_refclk(struct drm_device *dev)
8478 {
8479         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8480                 ironlake_init_pch_refclk(dev);
8481         else if (HAS_PCH_LPT(dev))
8482                 lpt_init_pch_refclk(dev);
8483 }
8484
8485 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8486 {
8487         struct drm_device *dev = crtc_state->base.crtc->dev;
8488         struct drm_i915_private *dev_priv = dev->dev_private;
8489         struct drm_atomic_state *state = crtc_state->base.state;
8490         struct drm_connector *connector;
8491         struct drm_connector_state *connector_state;
8492         struct intel_encoder *encoder;
8493         int num_connectors = 0, i;
8494         bool is_lvds = false;
8495
8496         for_each_connector_in_state(state, connector, connector_state, i) {
8497                 if (connector_state->crtc != crtc_state->base.crtc)
8498                         continue;
8499
8500                 encoder = to_intel_encoder(connector_state->best_encoder);
8501
8502                 switch (encoder->type) {
8503                 case INTEL_OUTPUT_LVDS:
8504                         is_lvds = true;
8505                         break;
8506                 default:
8507                         break;
8508                 }
8509                 num_connectors++;
8510         }
8511
8512         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8513                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8514                               dev_priv->vbt.lvds_ssc_freq);
8515                 return dev_priv->vbt.lvds_ssc_freq;
8516         }
8517
8518         return 120000;
8519 }
8520
8521 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8522 {
8523         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8524         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8525         int pipe = intel_crtc->pipe;
8526         uint32_t val;
8527
8528         val = 0;
8529
8530         switch (intel_crtc->config->pipe_bpp) {
8531         case 18:
8532                 val |= PIPECONF_6BPC;
8533                 break;
8534         case 24:
8535                 val |= PIPECONF_8BPC;
8536                 break;
8537         case 30:
8538                 val |= PIPECONF_10BPC;
8539                 break;
8540         case 36:
8541                 val |= PIPECONF_12BPC;
8542                 break;
8543         default:
8544                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8545                 BUG();
8546         }
8547
8548         if (intel_crtc->config->dither)
8549                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8550
8551         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8552                 val |= PIPECONF_INTERLACED_ILK;
8553         else
8554                 val |= PIPECONF_PROGRESSIVE;
8555
8556         if (intel_crtc->config->limited_color_range)
8557                 val |= PIPECONF_COLOR_RANGE_SELECT;
8558
8559         I915_WRITE(PIPECONF(pipe), val);
8560         POSTING_READ(PIPECONF(pipe));
8561 }
8562
8563 /*
8564  * Set up the pipe CSC unit.
8565  *
8566  * Currently only full range RGB to limited range RGB conversion
8567  * is supported, but eventually this should handle various
8568  * RGB<->YCbCr scenarios as well.
8569  */
8570 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8571 {
8572         struct drm_device *dev = crtc->dev;
8573         struct drm_i915_private *dev_priv = dev->dev_private;
8574         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8575         int pipe = intel_crtc->pipe;
8576         uint16_t coeff = 0x7800; /* 1.0 */
8577
8578         /*
8579          * TODO: Check what kind of values actually come out of the pipe
8580          * with these coeff/postoff values and adjust to get the best
8581          * accuracy. Perhaps we even need to take the bpc value into
8582          * consideration.
8583          */
8584
8585         if (intel_crtc->config->limited_color_range)
8586                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8587
8588         /*
8589          * GY/GU and RY/RU should be the other way around according
8590          * to BSpec, but reality doesn't agree. Just set them up in
8591          * a way that results in the correct picture.
8592          */
8593         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8594         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8595
8596         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8597         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8598
8599         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8600         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8601
8602         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8603         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8604         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8605
8606         if (INTEL_INFO(dev)->gen > 6) {
8607                 uint16_t postoff = 0;
8608
8609                 if (intel_crtc->config->limited_color_range)
8610                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8611
8612                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8613                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8614                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8615
8616                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8617         } else {
8618                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8619
8620                 if (intel_crtc->config->limited_color_range)
8621                         mode |= CSC_BLACK_SCREEN_OFFSET;
8622
8623                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8624         }
8625 }
8626
8627 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8628 {
8629         struct drm_device *dev = crtc->dev;
8630         struct drm_i915_private *dev_priv = dev->dev_private;
8631         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8632         enum pipe pipe = intel_crtc->pipe;
8633         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8634         uint32_t val;
8635
8636         val = 0;
8637
8638         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8639                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8640
8641         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8642                 val |= PIPECONF_INTERLACED_ILK;
8643         else
8644                 val |= PIPECONF_PROGRESSIVE;
8645
8646         I915_WRITE(PIPECONF(cpu_transcoder), val);
8647         POSTING_READ(PIPECONF(cpu_transcoder));
8648
8649         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8650         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8651
8652         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8653                 val = 0;
8654
8655                 switch (intel_crtc->config->pipe_bpp) {
8656                 case 18:
8657                         val |= PIPEMISC_DITHER_6_BPC;
8658                         break;
8659                 case 24:
8660                         val |= PIPEMISC_DITHER_8_BPC;
8661                         break;
8662                 case 30:
8663                         val |= PIPEMISC_DITHER_10_BPC;
8664                         break;
8665                 case 36:
8666                         val |= PIPEMISC_DITHER_12_BPC;
8667                         break;
8668                 default:
8669                         /* Case prevented by pipe_config_set_bpp. */
8670                         BUG();
8671                 }
8672
8673                 if (intel_crtc->config->dither)
8674                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8675
8676                 I915_WRITE(PIPEMISC(pipe), val);
8677         }
8678 }
8679
8680 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8681                                     struct intel_crtc_state *crtc_state,
8682                                     intel_clock_t *clock,
8683                                     bool *has_reduced_clock,
8684                                     intel_clock_t *reduced_clock)
8685 {
8686         struct drm_device *dev = crtc->dev;
8687         struct drm_i915_private *dev_priv = dev->dev_private;
8688         int refclk;
8689         const intel_limit_t *limit;
8690         bool ret;
8691
8692         refclk = ironlake_get_refclk(crtc_state);
8693
8694         /*
8695          * Returns a set of divisors for the desired target clock with the given
8696          * refclk, or FALSE.  The returned values represent the clock equation:
8697          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8698          */
8699         limit = intel_limit(crtc_state, refclk);
8700         ret = dev_priv->display.find_dpll(limit, crtc_state,
8701                                           crtc_state->port_clock,
8702                                           refclk, NULL, clock);
8703         if (!ret)
8704                 return false;
8705
8706         return true;
8707 }
8708
8709 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8710 {
8711         /*
8712          * Account for spread spectrum to avoid
8713          * oversubscribing the link. Max center spread
8714          * is 2.5%; use 5% for safety's sake.
8715          */
8716         u32 bps = target_clock * bpp * 21 / 20;
8717         return DIV_ROUND_UP(bps, link_bw * 8);
8718 }
8719
8720 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8721 {
8722         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8723 }
8724
8725 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8726                                       struct intel_crtc_state *crtc_state,
8727                                       u32 *fp,
8728                                       intel_clock_t *reduced_clock, u32 *fp2)
8729 {
8730         struct drm_crtc *crtc = &intel_crtc->base;
8731         struct drm_device *dev = crtc->dev;
8732         struct drm_i915_private *dev_priv = dev->dev_private;
8733         struct drm_atomic_state *state = crtc_state->base.state;
8734         struct drm_connector *connector;
8735         struct drm_connector_state *connector_state;
8736         struct intel_encoder *encoder;
8737         uint32_t dpll;
8738         int factor, num_connectors = 0, i;
8739         bool is_lvds = false, is_sdvo = false;
8740
8741         for_each_connector_in_state(state, connector, connector_state, i) {
8742                 if (connector_state->crtc != crtc_state->base.crtc)
8743                         continue;
8744
8745                 encoder = to_intel_encoder(connector_state->best_encoder);
8746
8747                 switch (encoder->type) {
8748                 case INTEL_OUTPUT_LVDS:
8749                         is_lvds = true;
8750                         break;
8751                 case INTEL_OUTPUT_SDVO:
8752                 case INTEL_OUTPUT_HDMI:
8753                         is_sdvo = true;
8754                         break;
8755                 default:
8756                         break;
8757                 }
8758
8759                 num_connectors++;
8760         }
8761
8762         /* Enable autotuning of the PLL clock (if permissible) */
8763         factor = 21;
8764         if (is_lvds) {
8765                 if ((intel_panel_use_ssc(dev_priv) &&
8766                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8767                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8768                         factor = 25;
8769         } else if (crtc_state->sdvo_tv_clock)
8770                 factor = 20;
8771
8772         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8773                 *fp |= FP_CB_TUNE;
8774
8775         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8776                 *fp2 |= FP_CB_TUNE;
8777
8778         dpll = 0;
8779
8780         if (is_lvds)
8781                 dpll |= DPLLB_MODE_LVDS;
8782         else
8783                 dpll |= DPLLB_MODE_DAC_SERIAL;
8784
8785         dpll |= (crtc_state->pixel_multiplier - 1)
8786                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8787
8788         if (is_sdvo)
8789                 dpll |= DPLL_SDVO_HIGH_SPEED;
8790         if (crtc_state->has_dp_encoder)
8791                 dpll |= DPLL_SDVO_HIGH_SPEED;
8792
8793         /* compute bitmask from p1 value */
8794         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8795         /* also FPA1 */
8796         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8797
8798         switch (crtc_state->dpll.p2) {
8799         case 5:
8800                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8801                 break;
8802         case 7:
8803                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8804                 break;
8805         case 10:
8806                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8807                 break;
8808         case 14:
8809                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8810                 break;
8811         }
8812
8813         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8814                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8815         else
8816                 dpll |= PLL_REF_INPUT_DREFCLK;
8817
8818         return dpll | DPLL_VCO_ENABLE;
8819 }
8820
8821 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8822                                        struct intel_crtc_state *crtc_state)
8823 {
8824         struct drm_device *dev = crtc->base.dev;
8825         intel_clock_t clock, reduced_clock;
8826         u32 dpll = 0, fp = 0, fp2 = 0;
8827         bool ok, has_reduced_clock = false;
8828         bool is_lvds = false;
8829         struct intel_shared_dpll *pll;
8830
8831         memset(&crtc_state->dpll_hw_state, 0,
8832                sizeof(crtc_state->dpll_hw_state));
8833
8834         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8835
8836         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8837              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8838
8839         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8840                                      &has_reduced_clock, &reduced_clock);
8841         if (!ok && !crtc_state->clock_set) {
8842                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8843                 return -EINVAL;
8844         }
8845         /* Compat-code for transition, will disappear. */
8846         if (!crtc_state->clock_set) {
8847                 crtc_state->dpll.n = clock.n;
8848                 crtc_state->dpll.m1 = clock.m1;
8849                 crtc_state->dpll.m2 = clock.m2;
8850                 crtc_state->dpll.p1 = clock.p1;
8851                 crtc_state->dpll.p2 = clock.p2;
8852         }
8853
8854         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8855         if (crtc_state->has_pch_encoder) {
8856                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8857                 if (has_reduced_clock)
8858                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8859
8860                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8861                                              &fp, &reduced_clock,
8862                                              has_reduced_clock ? &fp2 : NULL);
8863
8864                 crtc_state->dpll_hw_state.dpll = dpll;
8865                 crtc_state->dpll_hw_state.fp0 = fp;
8866                 if (has_reduced_clock)
8867                         crtc_state->dpll_hw_state.fp1 = fp2;
8868                 else
8869                         crtc_state->dpll_hw_state.fp1 = fp;
8870
8871                 pll = intel_get_shared_dpll(crtc, crtc_state);
8872                 if (pll == NULL) {
8873                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8874                                          pipe_name(crtc->pipe));
8875                         return -EINVAL;
8876                 }
8877         }
8878
8879         if (is_lvds && has_reduced_clock)
8880                 crtc->lowfreq_avail = true;
8881         else
8882                 crtc->lowfreq_avail = false;
8883
8884         return 0;
8885 }
8886
8887 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8888                                          struct intel_link_m_n *m_n)
8889 {
8890         struct drm_device *dev = crtc->base.dev;
8891         struct drm_i915_private *dev_priv = dev->dev_private;
8892         enum pipe pipe = crtc->pipe;
8893
8894         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8895         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8896         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8897                 & ~TU_SIZE_MASK;
8898         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8899         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8900                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8901 }
8902
8903 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8904                                          enum transcoder transcoder,
8905                                          struct intel_link_m_n *m_n,
8906                                          struct intel_link_m_n *m2_n2)
8907 {
8908         struct drm_device *dev = crtc->base.dev;
8909         struct drm_i915_private *dev_priv = dev->dev_private;
8910         enum pipe pipe = crtc->pipe;
8911
8912         if (INTEL_INFO(dev)->gen >= 5) {
8913                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8914                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8915                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8916                         & ~TU_SIZE_MASK;
8917                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8918                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8919                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8920                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8921                  * gen < 8) and if DRRS is supported (to make sure the
8922                  * registers are not unnecessarily read).
8923                  */
8924                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8925                         crtc->config->has_drrs) {
8926                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8927                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8928                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8929                                         & ~TU_SIZE_MASK;
8930                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8931                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8932                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8933                 }
8934         } else {
8935                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8936                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8937                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8938                         & ~TU_SIZE_MASK;
8939                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8940                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8941                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8942         }
8943 }
8944
8945 void intel_dp_get_m_n(struct intel_crtc *crtc,
8946                       struct intel_crtc_state *pipe_config)
8947 {
8948         if (pipe_config->has_pch_encoder)
8949                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8950         else
8951                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8952                                              &pipe_config->dp_m_n,
8953                                              &pipe_config->dp_m2_n2);
8954 }
8955
8956 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8957                                         struct intel_crtc_state *pipe_config)
8958 {
8959         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8960                                      &pipe_config->fdi_m_n, NULL);
8961 }
8962
8963 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8964                                     struct intel_crtc_state *pipe_config)
8965 {
8966         struct drm_device *dev = crtc->base.dev;
8967         struct drm_i915_private *dev_priv = dev->dev_private;
8968         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8969         uint32_t ps_ctrl = 0;
8970         int id = -1;
8971         int i;
8972
8973         /* find scaler attached to this pipe */
8974         for (i = 0; i < crtc->num_scalers; i++) {
8975                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8976                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8977                         id = i;
8978                         pipe_config->pch_pfit.enabled = true;
8979                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8980                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8981                         break;
8982                 }
8983         }
8984
8985         scaler_state->scaler_id = id;
8986         if (id >= 0) {
8987                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8988         } else {
8989                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8990         }
8991 }
8992
8993 static void
8994 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8995                                  struct intel_initial_plane_config *plane_config)
8996 {
8997         struct drm_device *dev = crtc->base.dev;
8998         struct drm_i915_private *dev_priv = dev->dev_private;
8999         u32 val, base, offset, stride_mult, tiling;
9000         int pipe = crtc->pipe;
9001         int fourcc, pixel_format;
9002         unsigned int aligned_height;
9003         struct drm_framebuffer *fb;
9004         struct intel_framebuffer *intel_fb;
9005
9006         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9007         if (!intel_fb) {
9008                 DRM_DEBUG_KMS("failed to alloc fb\n");
9009                 return;
9010         }
9011
9012         fb = &intel_fb->base;
9013
9014         val = I915_READ(PLANE_CTL(pipe, 0));
9015         if (!(val & PLANE_CTL_ENABLE))
9016                 goto error;
9017
9018         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9019         fourcc = skl_format_to_fourcc(pixel_format,
9020                                       val & PLANE_CTL_ORDER_RGBX,
9021                                       val & PLANE_CTL_ALPHA_MASK);
9022         fb->pixel_format = fourcc;
9023         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9024
9025         tiling = val & PLANE_CTL_TILED_MASK;
9026         switch (tiling) {
9027         case PLANE_CTL_TILED_LINEAR:
9028                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9029                 break;
9030         case PLANE_CTL_TILED_X:
9031                 plane_config->tiling = I915_TILING_X;
9032                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9033                 break;
9034         case PLANE_CTL_TILED_Y:
9035                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9036                 break;
9037         case PLANE_CTL_TILED_YF:
9038                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9039                 break;
9040         default:
9041                 MISSING_CASE(tiling);
9042                 goto error;
9043         }
9044
9045         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9046         plane_config->base = base;
9047
9048         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9049
9050         val = I915_READ(PLANE_SIZE(pipe, 0));
9051         fb->height = ((val >> 16) & 0xfff) + 1;
9052         fb->width = ((val >> 0) & 0x1fff) + 1;
9053
9054         val = I915_READ(PLANE_STRIDE(pipe, 0));
9055         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9056                                                 fb->pixel_format);
9057         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9058
9059         aligned_height = intel_fb_align_height(dev, fb->height,
9060                                                fb->pixel_format,
9061                                                fb->modifier[0]);
9062
9063         plane_config->size = fb->pitches[0] * aligned_height;
9064
9065         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9066                       pipe_name(pipe), fb->width, fb->height,
9067                       fb->bits_per_pixel, base, fb->pitches[0],
9068                       plane_config->size);
9069
9070         plane_config->fb = intel_fb;
9071         return;
9072
9073 error:
9074         kfree(fb);
9075 }
9076
9077 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9078                                      struct intel_crtc_state *pipe_config)
9079 {
9080         struct drm_device *dev = crtc->base.dev;
9081         struct drm_i915_private *dev_priv = dev->dev_private;
9082         uint32_t tmp;
9083
9084         tmp = I915_READ(PF_CTL(crtc->pipe));
9085
9086         if (tmp & PF_ENABLE) {
9087                 pipe_config->pch_pfit.enabled = true;
9088                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9089                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9090
9091                 /* We currently do not free assignements of panel fitters on
9092                  * ivb/hsw (since we don't use the higher upscaling modes which
9093                  * differentiates them) so just WARN about this case for now. */
9094                 if (IS_GEN7(dev)) {
9095                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9096                                 PF_PIPE_SEL_IVB(crtc->pipe));
9097                 }
9098         }
9099 }
9100
9101 static void
9102 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9103                                   struct intel_initial_plane_config *plane_config)
9104 {
9105         struct drm_device *dev = crtc->base.dev;
9106         struct drm_i915_private *dev_priv = dev->dev_private;
9107         u32 val, base, offset;
9108         int pipe = crtc->pipe;
9109         int fourcc, pixel_format;
9110         unsigned int aligned_height;
9111         struct drm_framebuffer *fb;
9112         struct intel_framebuffer *intel_fb;
9113
9114         val = I915_READ(DSPCNTR(pipe));
9115         if (!(val & DISPLAY_PLANE_ENABLE))
9116                 return;
9117
9118         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9119         if (!intel_fb) {
9120                 DRM_DEBUG_KMS("failed to alloc fb\n");
9121                 return;
9122         }
9123
9124         fb = &intel_fb->base;
9125
9126         if (INTEL_INFO(dev)->gen >= 4) {
9127                 if (val & DISPPLANE_TILED) {
9128                         plane_config->tiling = I915_TILING_X;
9129                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9130                 }
9131         }
9132
9133         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9134         fourcc = i9xx_format_to_fourcc(pixel_format);
9135         fb->pixel_format = fourcc;
9136         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9137
9138         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9139         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9140                 offset = I915_READ(DSPOFFSET(pipe));
9141         } else {
9142                 if (plane_config->tiling)
9143                         offset = I915_READ(DSPTILEOFF(pipe));
9144                 else
9145                         offset = I915_READ(DSPLINOFF(pipe));
9146         }
9147         plane_config->base = base;
9148
9149         val = I915_READ(PIPESRC(pipe));
9150         fb->width = ((val >> 16) & 0xfff) + 1;
9151         fb->height = ((val >> 0) & 0xfff) + 1;
9152
9153         val = I915_READ(DSPSTRIDE(pipe));
9154         fb->pitches[0] = val & 0xffffffc0;
9155
9156         aligned_height = intel_fb_align_height(dev, fb->height,
9157                                                fb->pixel_format,
9158                                                fb->modifier[0]);
9159
9160         plane_config->size = fb->pitches[0] * aligned_height;
9161
9162         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9163                       pipe_name(pipe), fb->width, fb->height,
9164                       fb->bits_per_pixel, base, fb->pitches[0],
9165                       plane_config->size);
9166
9167         plane_config->fb = intel_fb;
9168 }
9169
9170 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9171                                      struct intel_crtc_state *pipe_config)
9172 {
9173         struct drm_device *dev = crtc->base.dev;
9174         struct drm_i915_private *dev_priv = dev->dev_private;
9175         uint32_t tmp;
9176
9177         if (!intel_display_power_is_enabled(dev_priv,
9178                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9179                 return false;
9180
9181         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9182         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9183
9184         tmp = I915_READ(PIPECONF(crtc->pipe));
9185         if (!(tmp & PIPECONF_ENABLE))
9186                 return false;
9187
9188         switch (tmp & PIPECONF_BPC_MASK) {
9189         case PIPECONF_6BPC:
9190                 pipe_config->pipe_bpp = 18;
9191                 break;
9192         case PIPECONF_8BPC:
9193                 pipe_config->pipe_bpp = 24;
9194                 break;
9195         case PIPECONF_10BPC:
9196                 pipe_config->pipe_bpp = 30;
9197                 break;
9198         case PIPECONF_12BPC:
9199                 pipe_config->pipe_bpp = 36;
9200                 break;
9201         default:
9202                 break;
9203         }
9204
9205         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9206                 pipe_config->limited_color_range = true;
9207
9208         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9209                 struct intel_shared_dpll *pll;
9210
9211                 pipe_config->has_pch_encoder = true;
9212
9213                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9214                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9215                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9216
9217                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9218
9219                 if (HAS_PCH_IBX(dev_priv->dev)) {
9220                         pipe_config->shared_dpll =
9221                                 (enum intel_dpll_id) crtc->pipe;
9222                 } else {
9223                         tmp = I915_READ(PCH_DPLL_SEL);
9224                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9225                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9226                         else
9227                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9228                 }
9229
9230                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9231
9232                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9233                                            &pipe_config->dpll_hw_state));
9234
9235                 tmp = pipe_config->dpll_hw_state.dpll;
9236                 pipe_config->pixel_multiplier =
9237                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9238                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9239
9240                 ironlake_pch_clock_get(crtc, pipe_config);
9241         } else {
9242                 pipe_config->pixel_multiplier = 1;
9243         }
9244
9245         intel_get_pipe_timings(crtc, pipe_config);
9246
9247         ironlake_get_pfit_config(crtc, pipe_config);
9248
9249         return true;
9250 }
9251
9252 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9253 {
9254         struct drm_device *dev = dev_priv->dev;
9255         struct intel_crtc *crtc;
9256
9257         for_each_intel_crtc(dev, crtc)
9258                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9259                      pipe_name(crtc->pipe));
9260
9261         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9262         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9263         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9264         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9265         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9266         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9267              "CPU PWM1 enabled\n");
9268         if (IS_HASWELL(dev))
9269                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9270                      "CPU PWM2 enabled\n");
9271         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9272              "PCH PWM1 enabled\n");
9273         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9274              "Utility pin enabled\n");
9275         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9276
9277         /*
9278          * In theory we can still leave IRQs enabled, as long as only the HPD
9279          * interrupts remain enabled. We used to check for that, but since it's
9280          * gen-specific and since we only disable LCPLL after we fully disable
9281          * the interrupts, the check below should be enough.
9282          */
9283         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9284 }
9285
9286 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9287 {
9288         struct drm_device *dev = dev_priv->dev;
9289
9290         if (IS_HASWELL(dev))
9291                 return I915_READ(D_COMP_HSW);
9292         else
9293                 return I915_READ(D_COMP_BDW);
9294 }
9295
9296 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9297 {
9298         struct drm_device *dev = dev_priv->dev;
9299
9300         if (IS_HASWELL(dev)) {
9301                 mutex_lock(&dev_priv->rps.hw_lock);
9302                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9303                                             val))
9304                         DRM_ERROR("Failed to write to D_COMP\n");
9305                 mutex_unlock(&dev_priv->rps.hw_lock);
9306         } else {
9307                 I915_WRITE(D_COMP_BDW, val);
9308                 POSTING_READ(D_COMP_BDW);
9309         }
9310 }
9311
9312 /*
9313  * This function implements pieces of two sequences from BSpec:
9314  * - Sequence for display software to disable LCPLL
9315  * - Sequence for display software to allow package C8+
9316  * The steps implemented here are just the steps that actually touch the LCPLL
9317  * register. Callers should take care of disabling all the display engine
9318  * functions, doing the mode unset, fixing interrupts, etc.
9319  */
9320 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9321                               bool switch_to_fclk, bool allow_power_down)
9322 {
9323         uint32_t val;
9324
9325         assert_can_disable_lcpll(dev_priv);
9326
9327         val = I915_READ(LCPLL_CTL);
9328
9329         if (switch_to_fclk) {
9330                 val |= LCPLL_CD_SOURCE_FCLK;
9331                 I915_WRITE(LCPLL_CTL, val);
9332
9333                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9334                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9335                         DRM_ERROR("Switching to FCLK failed\n");
9336
9337                 val = I915_READ(LCPLL_CTL);
9338         }
9339
9340         val |= LCPLL_PLL_DISABLE;
9341         I915_WRITE(LCPLL_CTL, val);
9342         POSTING_READ(LCPLL_CTL);
9343
9344         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9345                 DRM_ERROR("LCPLL still locked\n");
9346
9347         val = hsw_read_dcomp(dev_priv);
9348         val |= D_COMP_COMP_DISABLE;
9349         hsw_write_dcomp(dev_priv, val);
9350         ndelay(100);
9351
9352         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9353                      1))
9354                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9355
9356         if (allow_power_down) {
9357                 val = I915_READ(LCPLL_CTL);
9358                 val |= LCPLL_POWER_DOWN_ALLOW;
9359                 I915_WRITE(LCPLL_CTL, val);
9360                 POSTING_READ(LCPLL_CTL);
9361         }
9362 }
9363
9364 /*
9365  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9366  * source.
9367  */
9368 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9369 {
9370         uint32_t val;
9371
9372         val = I915_READ(LCPLL_CTL);
9373
9374         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9375                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9376                 return;
9377
9378         /*
9379          * Make sure we're not on PC8 state before disabling PC8, otherwise
9380          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9381          */
9382         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9383
9384         if (val & LCPLL_POWER_DOWN_ALLOW) {
9385                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9386                 I915_WRITE(LCPLL_CTL, val);
9387                 POSTING_READ(LCPLL_CTL);
9388         }
9389
9390         val = hsw_read_dcomp(dev_priv);
9391         val |= D_COMP_COMP_FORCE;
9392         val &= ~D_COMP_COMP_DISABLE;
9393         hsw_write_dcomp(dev_priv, val);
9394
9395         val = I915_READ(LCPLL_CTL);
9396         val &= ~LCPLL_PLL_DISABLE;
9397         I915_WRITE(LCPLL_CTL, val);
9398
9399         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9400                 DRM_ERROR("LCPLL not locked yet\n");
9401
9402         if (val & LCPLL_CD_SOURCE_FCLK) {
9403                 val = I915_READ(LCPLL_CTL);
9404                 val &= ~LCPLL_CD_SOURCE_FCLK;
9405                 I915_WRITE(LCPLL_CTL, val);
9406
9407                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9408                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9409                         DRM_ERROR("Switching back to LCPLL failed\n");
9410         }
9411
9412         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9413         intel_update_cdclk(dev_priv->dev);
9414 }
9415
9416 /*
9417  * Package states C8 and deeper are really deep PC states that can only be
9418  * reached when all the devices on the system allow it, so even if the graphics
9419  * device allows PC8+, it doesn't mean the system will actually get to these
9420  * states. Our driver only allows PC8+ when going into runtime PM.
9421  *
9422  * The requirements for PC8+ are that all the outputs are disabled, the power
9423  * well is disabled and most interrupts are disabled, and these are also
9424  * requirements for runtime PM. When these conditions are met, we manually do
9425  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9426  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9427  * hang the machine.
9428  *
9429  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9430  * the state of some registers, so when we come back from PC8+ we need to
9431  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9432  * need to take care of the registers kept by RC6. Notice that this happens even
9433  * if we don't put the device in PCI D3 state (which is what currently happens
9434  * because of the runtime PM support).
9435  *
9436  * For more, read "Display Sequences for Package C8" on the hardware
9437  * documentation.
9438  */
9439 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9440 {
9441         struct drm_device *dev = dev_priv->dev;
9442         uint32_t val;
9443
9444         DRM_DEBUG_KMS("Enabling package C8+\n");
9445
9446         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9447                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9448                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9449                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9450         }
9451
9452         lpt_disable_clkout_dp(dev);
9453         hsw_disable_lcpll(dev_priv, true, true);
9454 }
9455
9456 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9457 {
9458         struct drm_device *dev = dev_priv->dev;
9459         uint32_t val;
9460
9461         DRM_DEBUG_KMS("Disabling package C8+\n");
9462
9463         hsw_restore_lcpll(dev_priv);
9464         lpt_init_pch_refclk(dev);
9465
9466         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9467                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9468                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9469                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9470         }
9471
9472         intel_prepare_ddi(dev);
9473 }
9474
9475 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9476 {
9477         struct drm_device *dev = old_state->dev;
9478         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9479
9480         broxton_set_cdclk(dev, req_cdclk);
9481 }
9482
9483 /* compute the max rate for new configuration */
9484 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9485 {
9486         struct intel_crtc *intel_crtc;
9487         struct intel_crtc_state *crtc_state;
9488         int max_pixel_rate = 0;
9489
9490         for_each_intel_crtc(state->dev, intel_crtc) {
9491                 int pixel_rate;
9492
9493                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9494                 if (IS_ERR(crtc_state))
9495                         return PTR_ERR(crtc_state);
9496
9497                 if (!crtc_state->base.enable)
9498                         continue;
9499
9500                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9501
9502                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9503                 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9504                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9505
9506                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9507         }
9508
9509         return max_pixel_rate;
9510 }
9511
9512 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9513 {
9514         struct drm_i915_private *dev_priv = dev->dev_private;
9515         uint32_t val, data;
9516         int ret;
9517
9518         if (WARN((I915_READ(LCPLL_CTL) &
9519                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9520                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9521                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9522                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9523                  "trying to change cdclk frequency with cdclk not enabled\n"))
9524                 return;
9525
9526         mutex_lock(&dev_priv->rps.hw_lock);
9527         ret = sandybridge_pcode_write(dev_priv,
9528                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9529         mutex_unlock(&dev_priv->rps.hw_lock);
9530         if (ret) {
9531                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9532                 return;
9533         }
9534
9535         val = I915_READ(LCPLL_CTL);
9536         val |= LCPLL_CD_SOURCE_FCLK;
9537         I915_WRITE(LCPLL_CTL, val);
9538
9539         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9540                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9541                 DRM_ERROR("Switching to FCLK failed\n");
9542
9543         val = I915_READ(LCPLL_CTL);
9544         val &= ~LCPLL_CLK_FREQ_MASK;
9545
9546         switch (cdclk) {
9547         case 450000:
9548                 val |= LCPLL_CLK_FREQ_450;
9549                 data = 0;
9550                 break;
9551         case 540000:
9552                 val |= LCPLL_CLK_FREQ_54O_BDW;
9553                 data = 1;
9554                 break;
9555         case 337500:
9556                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9557                 data = 2;
9558                 break;
9559         case 675000:
9560                 val |= LCPLL_CLK_FREQ_675_BDW;
9561                 data = 3;
9562                 break;
9563         default:
9564                 WARN(1, "invalid cdclk frequency\n");
9565                 return;
9566         }
9567
9568         I915_WRITE(LCPLL_CTL, val);
9569
9570         val = I915_READ(LCPLL_CTL);
9571         val &= ~LCPLL_CD_SOURCE_FCLK;
9572         I915_WRITE(LCPLL_CTL, val);
9573
9574         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9575                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9576                 DRM_ERROR("Switching back to LCPLL failed\n");
9577
9578         mutex_lock(&dev_priv->rps.hw_lock);
9579         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9580         mutex_unlock(&dev_priv->rps.hw_lock);
9581
9582         intel_update_cdclk(dev);
9583
9584         WARN(cdclk != dev_priv->cdclk_freq,
9585              "cdclk requested %d kHz but got %d kHz\n",
9586              cdclk, dev_priv->cdclk_freq);
9587 }
9588
9589 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9590 {
9591         struct drm_i915_private *dev_priv = to_i915(state->dev);
9592         int max_pixclk = ilk_max_pixel_rate(state);
9593         int cdclk;
9594
9595         /*
9596          * FIXME should also account for plane ratio
9597          * once 64bpp pixel formats are supported.
9598          */
9599         if (max_pixclk > 540000)
9600                 cdclk = 675000;
9601         else if (max_pixclk > 450000)
9602                 cdclk = 540000;
9603         else if (max_pixclk > 337500)
9604                 cdclk = 450000;
9605         else
9606                 cdclk = 337500;
9607
9608         /*
9609          * FIXME move the cdclk caclulation to
9610          * compute_config() so we can fail gracegully.
9611          */
9612         if (cdclk > dev_priv->max_cdclk_freq) {
9613                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9614                           cdclk, dev_priv->max_cdclk_freq);
9615                 cdclk = dev_priv->max_cdclk_freq;
9616         }
9617
9618         to_intel_atomic_state(state)->cdclk = cdclk;
9619
9620         return 0;
9621 }
9622
9623 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9624 {
9625         struct drm_device *dev = old_state->dev;
9626         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9627
9628         broadwell_set_cdclk(dev, req_cdclk);
9629 }
9630
9631 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9632                                       struct intel_crtc_state *crtc_state)
9633 {
9634         if (!intel_ddi_pll_select(crtc, crtc_state))
9635                 return -EINVAL;
9636
9637         crtc->lowfreq_avail = false;
9638
9639         return 0;
9640 }
9641
9642 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9643                                 enum port port,
9644                                 struct intel_crtc_state *pipe_config)
9645 {
9646         switch (port) {
9647         case PORT_A:
9648                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9649                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9650                 break;
9651         case PORT_B:
9652                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9653                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9654                 break;
9655         case PORT_C:
9656                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9657                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9658                 break;
9659         default:
9660                 DRM_ERROR("Incorrect port type\n");
9661         }
9662 }
9663
9664 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9665                                 enum port port,
9666                                 struct intel_crtc_state *pipe_config)
9667 {
9668         u32 temp, dpll_ctl1;
9669
9670         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9671         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9672
9673         switch (pipe_config->ddi_pll_sel) {
9674         case SKL_DPLL0:
9675                 /*
9676                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9677                  * of the shared DPLL framework and thus needs to be read out
9678                  * separately
9679                  */
9680                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9681                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9682                 break;
9683         case SKL_DPLL1:
9684                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9685                 break;
9686         case SKL_DPLL2:
9687                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9688                 break;
9689         case SKL_DPLL3:
9690                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9691                 break;
9692         }
9693 }
9694
9695 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9696                                 enum port port,
9697                                 struct intel_crtc_state *pipe_config)
9698 {
9699         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9700
9701         switch (pipe_config->ddi_pll_sel) {
9702         case PORT_CLK_SEL_WRPLL1:
9703                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9704                 break;
9705         case PORT_CLK_SEL_WRPLL2:
9706                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9707                 break;
9708         }
9709 }
9710
9711 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9712                                        struct intel_crtc_state *pipe_config)
9713 {
9714         struct drm_device *dev = crtc->base.dev;
9715         struct drm_i915_private *dev_priv = dev->dev_private;
9716         struct intel_shared_dpll *pll;
9717         enum port port;
9718         uint32_t tmp;
9719
9720         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9721
9722         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9723
9724         if (IS_SKYLAKE(dev))
9725                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9726         else if (IS_BROXTON(dev))
9727                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9728         else
9729                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9730
9731         if (pipe_config->shared_dpll >= 0) {
9732                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9733
9734                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9735                                            &pipe_config->dpll_hw_state));
9736         }
9737
9738         /*
9739          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9740          * DDI E. So just check whether this pipe is wired to DDI E and whether
9741          * the PCH transcoder is on.
9742          */
9743         if (INTEL_INFO(dev)->gen < 9 &&
9744             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9745                 pipe_config->has_pch_encoder = true;
9746
9747                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9748                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9749                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9750
9751                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9752         }
9753 }
9754
9755 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9756                                     struct intel_crtc_state *pipe_config)
9757 {
9758         struct drm_device *dev = crtc->base.dev;
9759         struct drm_i915_private *dev_priv = dev->dev_private;
9760         enum intel_display_power_domain pfit_domain;
9761         uint32_t tmp;
9762
9763         if (!intel_display_power_is_enabled(dev_priv,
9764                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9765                 return false;
9766
9767         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9768         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9769
9770         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9771         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9772                 enum pipe trans_edp_pipe;
9773                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9774                 default:
9775                         WARN(1, "unknown pipe linked to edp transcoder\n");
9776                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9777                 case TRANS_DDI_EDP_INPUT_A_ON:
9778                         trans_edp_pipe = PIPE_A;
9779                         break;
9780                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9781                         trans_edp_pipe = PIPE_B;
9782                         break;
9783                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9784                         trans_edp_pipe = PIPE_C;
9785                         break;
9786                 }
9787
9788                 if (trans_edp_pipe == crtc->pipe)
9789                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9790         }
9791
9792         if (!intel_display_power_is_enabled(dev_priv,
9793                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9794                 return false;
9795
9796         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9797         if (!(tmp & PIPECONF_ENABLE))
9798                 return false;
9799
9800         haswell_get_ddi_port_state(crtc, pipe_config);
9801
9802         intel_get_pipe_timings(crtc, pipe_config);
9803
9804         if (INTEL_INFO(dev)->gen >= 9) {
9805                 skl_init_scalers(dev, crtc, pipe_config);
9806         }
9807
9808         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9809
9810         if (INTEL_INFO(dev)->gen >= 9) {
9811                 pipe_config->scaler_state.scaler_id = -1;
9812                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9813         }
9814
9815         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9816                 if (INTEL_INFO(dev)->gen == 9)
9817                         skylake_get_pfit_config(crtc, pipe_config);
9818                 else if (INTEL_INFO(dev)->gen < 9)
9819                         ironlake_get_pfit_config(crtc, pipe_config);
9820                 else
9821                         MISSING_CASE(INTEL_INFO(dev)->gen);
9822         }
9823
9824         if (IS_HASWELL(dev))
9825                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9826                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9827
9828         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9829                 pipe_config->pixel_multiplier =
9830                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9831         } else {
9832                 pipe_config->pixel_multiplier = 1;
9833         }
9834
9835         return true;
9836 }
9837
9838 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9839 {
9840         struct drm_device *dev = crtc->dev;
9841         struct drm_i915_private *dev_priv = dev->dev_private;
9842         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9843         uint32_t cntl = 0, size = 0;
9844
9845         if (base) {
9846                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9847                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9848                 unsigned int stride = roundup_pow_of_two(width) * 4;
9849
9850                 switch (stride) {
9851                 default:
9852                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9853                                   width, stride);
9854                         stride = 256;
9855                         /* fallthrough */
9856                 case 256:
9857                 case 512:
9858                 case 1024:
9859                 case 2048:
9860                         break;
9861                 }
9862
9863                 cntl |= CURSOR_ENABLE |
9864                         CURSOR_GAMMA_ENABLE |
9865                         CURSOR_FORMAT_ARGB |
9866                         CURSOR_STRIDE(stride);
9867
9868                 size = (height << 12) | width;
9869         }
9870
9871         if (intel_crtc->cursor_cntl != 0 &&
9872             (intel_crtc->cursor_base != base ||
9873              intel_crtc->cursor_size != size ||
9874              intel_crtc->cursor_cntl != cntl)) {
9875                 /* On these chipsets we can only modify the base/size/stride
9876                  * whilst the cursor is disabled.
9877                  */
9878                 I915_WRITE(_CURACNTR, 0);
9879                 POSTING_READ(_CURACNTR);
9880                 intel_crtc->cursor_cntl = 0;
9881         }
9882
9883         if (intel_crtc->cursor_base != base) {
9884                 I915_WRITE(_CURABASE, base);
9885                 intel_crtc->cursor_base = base;
9886         }
9887
9888         if (intel_crtc->cursor_size != size) {
9889                 I915_WRITE(CURSIZE, size);
9890                 intel_crtc->cursor_size = size;
9891         }
9892
9893         if (intel_crtc->cursor_cntl != cntl) {
9894                 I915_WRITE(_CURACNTR, cntl);
9895                 POSTING_READ(_CURACNTR);
9896                 intel_crtc->cursor_cntl = cntl;
9897         }
9898 }
9899
9900 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9901 {
9902         struct drm_device *dev = crtc->dev;
9903         struct drm_i915_private *dev_priv = dev->dev_private;
9904         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9905         int pipe = intel_crtc->pipe;
9906         uint32_t cntl;
9907
9908         cntl = 0;
9909         if (base) {
9910                 cntl = MCURSOR_GAMMA_ENABLE;
9911                 switch (intel_crtc->base.cursor->state->crtc_w) {
9912                         case 64:
9913                                 cntl |= CURSOR_MODE_64_ARGB_AX;
9914                                 break;
9915                         case 128:
9916                                 cntl |= CURSOR_MODE_128_ARGB_AX;
9917                                 break;
9918                         case 256:
9919                                 cntl |= CURSOR_MODE_256_ARGB_AX;
9920                                 break;
9921                         default:
9922                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9923                                 return;
9924                 }
9925                 cntl |= pipe << 28; /* Connect to correct pipe */
9926
9927                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9928                         cntl |= CURSOR_PIPE_CSC_ENABLE;
9929         }
9930
9931         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9932                 cntl |= CURSOR_ROTATE_180;
9933
9934         if (intel_crtc->cursor_cntl != cntl) {
9935                 I915_WRITE(CURCNTR(pipe), cntl);
9936                 POSTING_READ(CURCNTR(pipe));
9937                 intel_crtc->cursor_cntl = cntl;
9938         }
9939
9940         /* and commit changes on next vblank */
9941         I915_WRITE(CURBASE(pipe), base);
9942         POSTING_READ(CURBASE(pipe));
9943
9944         intel_crtc->cursor_base = base;
9945 }
9946
9947 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9948 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9949                                      bool on)
9950 {
9951         struct drm_device *dev = crtc->dev;
9952         struct drm_i915_private *dev_priv = dev->dev_private;
9953         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9954         int pipe = intel_crtc->pipe;
9955         int x = crtc->cursor_x;
9956         int y = crtc->cursor_y;
9957         u32 base = 0, pos = 0;
9958
9959         if (on)
9960                 base = intel_crtc->cursor_addr;
9961
9962         if (x >= intel_crtc->config->pipe_src_w)
9963                 base = 0;
9964
9965         if (y >= intel_crtc->config->pipe_src_h)
9966                 base = 0;
9967
9968         if (x < 0) {
9969                 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9970                         base = 0;
9971
9972                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9973                 x = -x;
9974         }
9975         pos |= x << CURSOR_X_SHIFT;
9976
9977         if (y < 0) {
9978                 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9979                         base = 0;
9980
9981                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9982                 y = -y;
9983         }
9984         pos |= y << CURSOR_Y_SHIFT;
9985
9986         if (base == 0 && intel_crtc->cursor_base == 0)
9987                 return;
9988
9989         I915_WRITE(CURPOS(pipe), pos);
9990
9991         /* ILK+ do this automagically */
9992         if (HAS_GMCH_DISPLAY(dev) &&
9993             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9994                 base += (intel_crtc->base.cursor->state->crtc_h *
9995                         intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9996         }
9997
9998         if (IS_845G(dev) || IS_I865G(dev))
9999                 i845_update_cursor(crtc, base);
10000         else
10001                 i9xx_update_cursor(crtc, base);
10002 }
10003
10004 static bool cursor_size_ok(struct drm_device *dev,
10005                            uint32_t width, uint32_t height)
10006 {
10007         if (width == 0 || height == 0)
10008                 return false;
10009
10010         /*
10011          * 845g/865g are special in that they are only limited by
10012          * the width of their cursors, the height is arbitrary up to
10013          * the precision of the register. Everything else requires
10014          * square cursors, limited to a few power-of-two sizes.
10015          */
10016         if (IS_845G(dev) || IS_I865G(dev)) {
10017                 if ((width & 63) != 0)
10018                         return false;
10019
10020                 if (width > (IS_845G(dev) ? 64 : 512))
10021                         return false;
10022
10023                 if (height > 1023)
10024                         return false;
10025         } else {
10026                 switch (width | height) {
10027                 case 256:
10028                 case 128:
10029                         if (IS_GEN2(dev))
10030                                 return false;
10031                 case 64:
10032                         break;
10033                 default:
10034                         return false;
10035                 }
10036         }
10037
10038         return true;
10039 }
10040
10041 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10042                                  u16 *blue, uint32_t start, uint32_t size)
10043 {
10044         int end = (start + size > 256) ? 256 : start + size, i;
10045         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10046
10047         for (i = start; i < end; i++) {
10048                 intel_crtc->lut_r[i] = red[i] >> 8;
10049                 intel_crtc->lut_g[i] = green[i] >> 8;
10050                 intel_crtc->lut_b[i] = blue[i] >> 8;
10051         }
10052
10053         intel_crtc_load_lut(crtc);
10054 }
10055
10056 /* VESA 640x480x72Hz mode to set on the pipe */
10057 static struct drm_display_mode load_detect_mode = {
10058         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10059                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10060 };
10061
10062 struct drm_framebuffer *
10063 __intel_framebuffer_create(struct drm_device *dev,
10064                            struct drm_mode_fb_cmd2 *mode_cmd,
10065                            struct drm_i915_gem_object *obj)
10066 {
10067         struct intel_framebuffer *intel_fb;
10068         int ret;
10069
10070         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10071         if (!intel_fb) {
10072                 drm_gem_object_unreference(&obj->base);
10073                 return ERR_PTR(-ENOMEM);
10074         }
10075
10076         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10077         if (ret)
10078                 goto err;
10079
10080         return &intel_fb->base;
10081 err:
10082         drm_gem_object_unreference(&obj->base);
10083         kfree(intel_fb);
10084
10085         return ERR_PTR(ret);
10086 }
10087
10088 static struct drm_framebuffer *
10089 intel_framebuffer_create(struct drm_device *dev,
10090                          struct drm_mode_fb_cmd2 *mode_cmd,
10091                          struct drm_i915_gem_object *obj)
10092 {
10093         struct drm_framebuffer *fb;
10094         int ret;
10095
10096         ret = i915_mutex_lock_interruptible(dev);
10097         if (ret)
10098                 return ERR_PTR(ret);
10099         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10100         mutex_unlock(&dev->struct_mutex);
10101
10102         return fb;
10103 }
10104
10105 static u32
10106 intel_framebuffer_pitch_for_width(int width, int bpp)
10107 {
10108         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10109         return ALIGN(pitch, 64);
10110 }
10111
10112 static u32
10113 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10114 {
10115         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10116         return PAGE_ALIGN(pitch * mode->vdisplay);
10117 }
10118
10119 static struct drm_framebuffer *
10120 intel_framebuffer_create_for_mode(struct drm_device *dev,
10121                                   struct drm_display_mode *mode,
10122                                   int depth, int bpp)
10123 {
10124         struct drm_i915_gem_object *obj;
10125         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10126
10127         obj = i915_gem_alloc_object(dev,
10128                                     intel_framebuffer_size_for_mode(mode, bpp));
10129         if (obj == NULL)
10130                 return ERR_PTR(-ENOMEM);
10131
10132         mode_cmd.width = mode->hdisplay;
10133         mode_cmd.height = mode->vdisplay;
10134         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10135                                                                 bpp);
10136         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10137
10138         return intel_framebuffer_create(dev, &mode_cmd, obj);
10139 }
10140
10141 static struct drm_framebuffer *
10142 mode_fits_in_fbdev(struct drm_device *dev,
10143                    struct drm_display_mode *mode)
10144 {
10145 #ifdef CONFIG_DRM_FBDEV_EMULATION
10146         struct drm_i915_private *dev_priv = dev->dev_private;
10147         struct drm_i915_gem_object *obj;
10148         struct drm_framebuffer *fb;
10149
10150         if (!dev_priv->fbdev)
10151                 return NULL;
10152
10153         if (!dev_priv->fbdev->fb)
10154                 return NULL;
10155
10156         obj = dev_priv->fbdev->fb->obj;
10157         BUG_ON(!obj);
10158
10159         fb = &dev_priv->fbdev->fb->base;
10160         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10161                                                                fb->bits_per_pixel))
10162                 return NULL;
10163
10164         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10165                 return NULL;
10166
10167         return fb;
10168 #else
10169         return NULL;
10170 #endif
10171 }
10172
10173 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10174                                            struct drm_crtc *crtc,
10175                                            struct drm_display_mode *mode,
10176                                            struct drm_framebuffer *fb,
10177                                            int x, int y)
10178 {
10179         struct drm_plane_state *plane_state;
10180         int hdisplay, vdisplay;
10181         int ret;
10182
10183         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10184         if (IS_ERR(plane_state))
10185                 return PTR_ERR(plane_state);
10186
10187         if (mode)
10188                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10189         else
10190                 hdisplay = vdisplay = 0;
10191
10192         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10193         if (ret)
10194                 return ret;
10195         drm_atomic_set_fb_for_plane(plane_state, fb);
10196         plane_state->crtc_x = 0;
10197         plane_state->crtc_y = 0;
10198         plane_state->crtc_w = hdisplay;
10199         plane_state->crtc_h = vdisplay;
10200         plane_state->src_x = x << 16;
10201         plane_state->src_y = y << 16;
10202         plane_state->src_w = hdisplay << 16;
10203         plane_state->src_h = vdisplay << 16;
10204
10205         return 0;
10206 }
10207
10208 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10209                                 struct drm_display_mode *mode,
10210                                 struct intel_load_detect_pipe *old,
10211                                 struct drm_modeset_acquire_ctx *ctx)
10212 {
10213         struct intel_crtc *intel_crtc;
10214         struct intel_encoder *intel_encoder =
10215                 intel_attached_encoder(connector);
10216         struct drm_crtc *possible_crtc;
10217         struct drm_encoder *encoder = &intel_encoder->base;
10218         struct drm_crtc *crtc = NULL;
10219         struct drm_device *dev = encoder->dev;
10220         struct drm_framebuffer *fb;
10221         struct drm_mode_config *config = &dev->mode_config;
10222         struct drm_atomic_state *state = NULL;
10223         struct drm_connector_state *connector_state;
10224         struct intel_crtc_state *crtc_state;
10225         int ret, i = -1;
10226
10227         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10228                       connector->base.id, connector->name,
10229                       encoder->base.id, encoder->name);
10230
10231 retry:
10232         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10233         if (ret)
10234                 goto fail;
10235
10236         /*
10237          * Algorithm gets a little messy:
10238          *
10239          *   - if the connector already has an assigned crtc, use it (but make
10240          *     sure it's on first)
10241          *
10242          *   - try to find the first unused crtc that can drive this connector,
10243          *     and use that if we find one
10244          */
10245
10246         /* See if we already have a CRTC for this connector */
10247         if (encoder->crtc) {
10248                 crtc = encoder->crtc;
10249
10250                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10251                 if (ret)
10252                         goto fail;
10253                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10254                 if (ret)
10255                         goto fail;
10256
10257                 old->dpms_mode = connector->dpms;
10258                 old->load_detect_temp = false;
10259
10260                 /* Make sure the crtc and connector are running */
10261                 if (connector->dpms != DRM_MODE_DPMS_ON)
10262                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10263
10264                 return true;
10265         }
10266
10267         /* Find an unused one (if possible) */
10268         for_each_crtc(dev, possible_crtc) {
10269                 i++;
10270                 if (!(encoder->possible_crtcs & (1 << i)))
10271                         continue;
10272                 if (possible_crtc->state->enable)
10273                         continue;
10274
10275                 crtc = possible_crtc;
10276                 break;
10277         }
10278
10279         /*
10280          * If we didn't find an unused CRTC, don't use any.
10281          */
10282         if (!crtc) {
10283                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10284                 goto fail;
10285         }
10286
10287         ret = drm_modeset_lock(&crtc->mutex, ctx);
10288         if (ret)
10289                 goto fail;
10290         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10291         if (ret)
10292                 goto fail;
10293
10294         intel_crtc = to_intel_crtc(crtc);
10295         old->dpms_mode = connector->dpms;
10296         old->load_detect_temp = true;
10297         old->release_fb = NULL;
10298
10299         state = drm_atomic_state_alloc(dev);
10300         if (!state)
10301                 return false;
10302
10303         state->acquire_ctx = ctx;
10304
10305         connector_state = drm_atomic_get_connector_state(state, connector);
10306         if (IS_ERR(connector_state)) {
10307                 ret = PTR_ERR(connector_state);
10308                 goto fail;
10309         }
10310
10311         connector_state->crtc = crtc;
10312         connector_state->best_encoder = &intel_encoder->base;
10313
10314         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10315         if (IS_ERR(crtc_state)) {
10316                 ret = PTR_ERR(crtc_state);
10317                 goto fail;
10318         }
10319
10320         crtc_state->base.active = crtc_state->base.enable = true;
10321
10322         if (!mode)
10323                 mode = &load_detect_mode;
10324
10325         /* We need a framebuffer large enough to accommodate all accesses
10326          * that the plane may generate whilst we perform load detection.
10327          * We can not rely on the fbcon either being present (we get called
10328          * during its initialisation to detect all boot displays, or it may
10329          * not even exist) or that it is large enough to satisfy the
10330          * requested mode.
10331          */
10332         fb = mode_fits_in_fbdev(dev, mode);
10333         if (fb == NULL) {
10334                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10335                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10336                 old->release_fb = fb;
10337         } else
10338                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10339         if (IS_ERR(fb)) {
10340                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10341                 goto fail;
10342         }
10343
10344         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10345         if (ret)
10346                 goto fail;
10347
10348         drm_mode_copy(&crtc_state->base.mode, mode);
10349
10350         if (drm_atomic_commit(state)) {
10351                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10352                 if (old->release_fb)
10353                         old->release_fb->funcs->destroy(old->release_fb);
10354                 goto fail;
10355         }
10356         crtc->primary->crtc = crtc;
10357
10358         /* let the connector get through one full cycle before testing */
10359         intel_wait_for_vblank(dev, intel_crtc->pipe);
10360         return true;
10361
10362 fail:
10363         drm_atomic_state_free(state);
10364         state = NULL;
10365
10366         if (ret == -EDEADLK) {
10367                 drm_modeset_backoff(ctx);
10368                 goto retry;
10369         }
10370
10371         return false;
10372 }
10373
10374 void intel_release_load_detect_pipe(struct drm_connector *connector,
10375                                     struct intel_load_detect_pipe *old,
10376                                     struct drm_modeset_acquire_ctx *ctx)
10377 {
10378         struct drm_device *dev = connector->dev;
10379         struct intel_encoder *intel_encoder =
10380                 intel_attached_encoder(connector);
10381         struct drm_encoder *encoder = &intel_encoder->base;
10382         struct drm_crtc *crtc = encoder->crtc;
10383         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10384         struct drm_atomic_state *state;
10385         struct drm_connector_state *connector_state;
10386         struct intel_crtc_state *crtc_state;
10387         int ret;
10388
10389         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10390                       connector->base.id, connector->name,
10391                       encoder->base.id, encoder->name);
10392
10393         if (old->load_detect_temp) {
10394                 state = drm_atomic_state_alloc(dev);
10395                 if (!state)
10396                         goto fail;
10397
10398                 state->acquire_ctx = ctx;
10399
10400                 connector_state = drm_atomic_get_connector_state(state, connector);
10401                 if (IS_ERR(connector_state))
10402                         goto fail;
10403
10404                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10405                 if (IS_ERR(crtc_state))
10406                         goto fail;
10407
10408                 connector_state->best_encoder = NULL;
10409                 connector_state->crtc = NULL;
10410
10411                 crtc_state->base.enable = crtc_state->base.active = false;
10412
10413                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10414                                                       0, 0);
10415                 if (ret)
10416                         goto fail;
10417
10418                 ret = drm_atomic_commit(state);
10419                 if (ret)
10420                         goto fail;
10421
10422                 if (old->release_fb) {
10423                         drm_framebuffer_unregister_private(old->release_fb);
10424                         drm_framebuffer_unreference(old->release_fb);
10425                 }
10426
10427                 return;
10428         }
10429
10430         /* Switch crtc and encoder back off if necessary */
10431         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10432                 connector->funcs->dpms(connector, old->dpms_mode);
10433
10434         return;
10435 fail:
10436         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10437         drm_atomic_state_free(state);
10438 }
10439
10440 static int i9xx_pll_refclk(struct drm_device *dev,
10441                            const struct intel_crtc_state *pipe_config)
10442 {
10443         struct drm_i915_private *dev_priv = dev->dev_private;
10444         u32 dpll = pipe_config->dpll_hw_state.dpll;
10445
10446         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10447                 return dev_priv->vbt.lvds_ssc_freq;
10448         else if (HAS_PCH_SPLIT(dev))
10449                 return 120000;
10450         else if (!IS_GEN2(dev))
10451                 return 96000;
10452         else
10453                 return 48000;
10454 }
10455
10456 /* Returns the clock of the currently programmed mode of the given pipe. */
10457 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10458                                 struct intel_crtc_state *pipe_config)
10459 {
10460         struct drm_device *dev = crtc->base.dev;
10461         struct drm_i915_private *dev_priv = dev->dev_private;
10462         int pipe = pipe_config->cpu_transcoder;
10463         u32 dpll = pipe_config->dpll_hw_state.dpll;
10464         u32 fp;
10465         intel_clock_t clock;
10466         int port_clock;
10467         int refclk = i9xx_pll_refclk(dev, pipe_config);
10468
10469         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10470                 fp = pipe_config->dpll_hw_state.fp0;
10471         else
10472                 fp = pipe_config->dpll_hw_state.fp1;
10473
10474         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10475         if (IS_PINEVIEW(dev)) {
10476                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10477                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10478         } else {
10479                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10480                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10481         }
10482
10483         if (!IS_GEN2(dev)) {
10484                 if (IS_PINEVIEW(dev))
10485                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10486                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10487                 else
10488                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10489                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10490
10491                 switch (dpll & DPLL_MODE_MASK) {
10492                 case DPLLB_MODE_DAC_SERIAL:
10493                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10494                                 5 : 10;
10495                         break;
10496                 case DPLLB_MODE_LVDS:
10497                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10498                                 7 : 14;
10499                         break;
10500                 default:
10501                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10502                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10503                         return;
10504                 }
10505
10506                 if (IS_PINEVIEW(dev))
10507                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10508                 else
10509                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10510         } else {
10511                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10512                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10513
10514                 if (is_lvds) {
10515                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10516                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10517
10518                         if (lvds & LVDS_CLKB_POWER_UP)
10519                                 clock.p2 = 7;
10520                         else
10521                                 clock.p2 = 14;
10522                 } else {
10523                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10524                                 clock.p1 = 2;
10525                         else {
10526                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10527                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10528                         }
10529                         if (dpll & PLL_P2_DIVIDE_BY_4)
10530                                 clock.p2 = 4;
10531                         else
10532                                 clock.p2 = 2;
10533                 }
10534
10535                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10536         }
10537
10538         /*
10539          * This value includes pixel_multiplier. We will use
10540          * port_clock to compute adjusted_mode.crtc_clock in the
10541          * encoder's get_config() function.
10542          */
10543         pipe_config->port_clock = port_clock;
10544 }
10545
10546 int intel_dotclock_calculate(int link_freq,
10547                              const struct intel_link_m_n *m_n)
10548 {
10549         /*
10550          * The calculation for the data clock is:
10551          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10552          * But we want to avoid losing precison if possible, so:
10553          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10554          *
10555          * and the link clock is simpler:
10556          * link_clock = (m * link_clock) / n
10557          */
10558
10559         if (!m_n->link_n)
10560                 return 0;
10561
10562         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10563 }
10564
10565 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10566                                    struct intel_crtc_state *pipe_config)
10567 {
10568         struct drm_device *dev = crtc->base.dev;
10569
10570         /* read out port_clock from the DPLL */
10571         i9xx_crtc_clock_get(crtc, pipe_config);
10572
10573         /*
10574          * This value does not include pixel_multiplier.
10575          * We will check that port_clock and adjusted_mode.crtc_clock
10576          * agree once we know their relationship in the encoder's
10577          * get_config() function.
10578          */
10579         pipe_config->base.adjusted_mode.crtc_clock =
10580                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10581                                          &pipe_config->fdi_m_n);
10582 }
10583
10584 /** Returns the currently programmed mode of the given pipe. */
10585 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10586                                              struct drm_crtc *crtc)
10587 {
10588         struct drm_i915_private *dev_priv = dev->dev_private;
10589         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10590         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10591         struct drm_display_mode *mode;
10592         struct intel_crtc_state pipe_config;
10593         int htot = I915_READ(HTOTAL(cpu_transcoder));
10594         int hsync = I915_READ(HSYNC(cpu_transcoder));
10595         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10596         int vsync = I915_READ(VSYNC(cpu_transcoder));
10597         enum pipe pipe = intel_crtc->pipe;
10598
10599         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10600         if (!mode)
10601                 return NULL;
10602
10603         /*
10604          * Construct a pipe_config sufficient for getting the clock info
10605          * back out of crtc_clock_get.
10606          *
10607          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10608          * to use a real value here instead.
10609          */
10610         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10611         pipe_config.pixel_multiplier = 1;
10612         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10613         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10614         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10615         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10616
10617         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10618         mode->hdisplay = (htot & 0xffff) + 1;
10619         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10620         mode->hsync_start = (hsync & 0xffff) + 1;
10621         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10622         mode->vdisplay = (vtot & 0xffff) + 1;
10623         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10624         mode->vsync_start = (vsync & 0xffff) + 1;
10625         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10626
10627         drm_mode_set_name(mode);
10628
10629         return mode;
10630 }
10631
10632 void intel_mark_busy(struct drm_device *dev)
10633 {
10634         struct drm_i915_private *dev_priv = dev->dev_private;
10635
10636         if (dev_priv->mm.busy)
10637                 return;
10638
10639         intel_runtime_pm_get(dev_priv);
10640         i915_update_gfx_val(dev_priv);
10641         if (INTEL_INFO(dev)->gen >= 6)
10642                 gen6_rps_busy(dev_priv);
10643         dev_priv->mm.busy = true;
10644 }
10645
10646 void intel_mark_idle(struct drm_device *dev)
10647 {
10648         struct drm_i915_private *dev_priv = dev->dev_private;
10649
10650         if (!dev_priv->mm.busy)
10651                 return;
10652
10653         dev_priv->mm.busy = false;
10654
10655         if (INTEL_INFO(dev)->gen >= 6)
10656                 gen6_rps_idle(dev->dev_private);
10657
10658         intel_runtime_pm_put(dev_priv);
10659 }
10660
10661 static void intel_crtc_destroy(struct drm_crtc *crtc)
10662 {
10663         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10664         struct drm_device *dev = crtc->dev;
10665         struct intel_unpin_work *work;
10666
10667         spin_lock_irq(&dev->event_lock);
10668         work = intel_crtc->unpin_work;
10669         intel_crtc->unpin_work = NULL;
10670         spin_unlock_irq(&dev->event_lock);
10671
10672         if (work) {
10673                 cancel_work_sync(&work->work);
10674                 kfree(work);
10675         }
10676
10677         drm_crtc_cleanup(crtc);
10678
10679         kfree(intel_crtc);
10680 }
10681
10682 static void intel_unpin_work_fn(struct work_struct *__work)
10683 {
10684         struct intel_unpin_work *work =
10685                 container_of(__work, struct intel_unpin_work, work);
10686         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10687         struct drm_device *dev = crtc->base.dev;
10688         struct drm_plane *primary = crtc->base.primary;
10689
10690         mutex_lock(&dev->struct_mutex);
10691         intel_unpin_fb_obj(work->old_fb, primary->state);
10692         drm_gem_object_unreference(&work->pending_flip_obj->base);
10693
10694         if (work->flip_queued_req)
10695                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10696         mutex_unlock(&dev->struct_mutex);
10697
10698         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10699         drm_framebuffer_unreference(work->old_fb);
10700
10701         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10702         atomic_dec(&crtc->unpin_work_count);
10703
10704         kfree(work);
10705 }
10706
10707 static void do_intel_finish_page_flip(struct drm_device *dev,
10708                                       struct drm_crtc *crtc)
10709 {
10710         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10711         struct intel_unpin_work *work;
10712         unsigned long flags;
10713
10714         /* Ignore early vblank irqs */
10715         if (intel_crtc == NULL)
10716                 return;
10717
10718         /*
10719          * This is called both by irq handlers and the reset code (to complete
10720          * lost pageflips) so needs the full irqsave spinlocks.
10721          */
10722         spin_lock_irqsave(&dev->event_lock, flags);
10723         work = intel_crtc->unpin_work;
10724
10725         /* Ensure we don't miss a work->pending update ... */
10726         smp_rmb();
10727
10728         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10729                 spin_unlock_irqrestore(&dev->event_lock, flags);
10730                 return;
10731         }
10732
10733         page_flip_completed(intel_crtc);
10734
10735         spin_unlock_irqrestore(&dev->event_lock, flags);
10736 }
10737
10738 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10739 {
10740         struct drm_i915_private *dev_priv = dev->dev_private;
10741         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10742
10743         do_intel_finish_page_flip(dev, crtc);
10744 }
10745
10746 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10747 {
10748         struct drm_i915_private *dev_priv = dev->dev_private;
10749         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10750
10751         do_intel_finish_page_flip(dev, crtc);
10752 }
10753
10754 /* Is 'a' after or equal to 'b'? */
10755 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10756 {
10757         return !((a - b) & 0x80000000);
10758 }
10759
10760 static bool page_flip_finished(struct intel_crtc *crtc)
10761 {
10762         struct drm_device *dev = crtc->base.dev;
10763         struct drm_i915_private *dev_priv = dev->dev_private;
10764
10765         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10766             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10767                 return true;
10768
10769         /*
10770          * The relevant registers doen't exist on pre-ctg.
10771          * As the flip done interrupt doesn't trigger for mmio
10772          * flips on gmch platforms, a flip count check isn't
10773          * really needed there. But since ctg has the registers,
10774          * include it in the check anyway.
10775          */
10776         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10777                 return true;
10778
10779         /*
10780          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10781          * used the same base address. In that case the mmio flip might
10782          * have completed, but the CS hasn't even executed the flip yet.
10783          *
10784          * A flip count check isn't enough as the CS might have updated
10785          * the base address just after start of vblank, but before we
10786          * managed to process the interrupt. This means we'd complete the
10787          * CS flip too soon.
10788          *
10789          * Combining both checks should get us a good enough result. It may
10790          * still happen that the CS flip has been executed, but has not
10791          * yet actually completed. But in case the base address is the same
10792          * anyway, we don't really care.
10793          */
10794         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10795                 crtc->unpin_work->gtt_offset &&
10796                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10797                                     crtc->unpin_work->flip_count);
10798 }
10799
10800 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10801 {
10802         struct drm_i915_private *dev_priv = dev->dev_private;
10803         struct intel_crtc *intel_crtc =
10804                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10805         unsigned long flags;
10806
10807
10808         /*
10809          * This is called both by irq handlers and the reset code (to complete
10810          * lost pageflips) so needs the full irqsave spinlocks.
10811          *
10812          * NB: An MMIO update of the plane base pointer will also
10813          * generate a page-flip completion irq, i.e. every modeset
10814          * is also accompanied by a spurious intel_prepare_page_flip().
10815          */
10816         spin_lock_irqsave(&dev->event_lock, flags);
10817         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10818                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10819         spin_unlock_irqrestore(&dev->event_lock, flags);
10820 }
10821
10822 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10823 {
10824         /* Ensure that the work item is consistent when activating it ... */
10825         smp_wmb();
10826         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10827         /* and that it is marked active as soon as the irq could fire. */
10828         smp_wmb();
10829 }
10830
10831 static int intel_gen2_queue_flip(struct drm_device *dev,
10832                                  struct drm_crtc *crtc,
10833                                  struct drm_framebuffer *fb,
10834                                  struct drm_i915_gem_object *obj,
10835                                  struct drm_i915_gem_request *req,
10836                                  uint32_t flags)
10837 {
10838         struct intel_engine_cs *ring = req->ring;
10839         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10840         u32 flip_mask;
10841         int ret;
10842
10843         ret = intel_ring_begin(req, 6);
10844         if (ret)
10845                 return ret;
10846
10847         /* Can't queue multiple flips, so wait for the previous
10848          * one to finish before executing the next.
10849          */
10850         if (intel_crtc->plane)
10851                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10852         else
10853                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10854         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10855         intel_ring_emit(ring, MI_NOOP);
10856         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10857                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10858         intel_ring_emit(ring, fb->pitches[0]);
10859         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10860         intel_ring_emit(ring, 0); /* aux display base address, unused */
10861
10862         intel_mark_page_flip_active(intel_crtc);
10863         return 0;
10864 }
10865
10866 static int intel_gen3_queue_flip(struct drm_device *dev,
10867                                  struct drm_crtc *crtc,
10868                                  struct drm_framebuffer *fb,
10869                                  struct drm_i915_gem_object *obj,
10870                                  struct drm_i915_gem_request *req,
10871                                  uint32_t flags)
10872 {
10873         struct intel_engine_cs *ring = req->ring;
10874         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10875         u32 flip_mask;
10876         int ret;
10877
10878         ret = intel_ring_begin(req, 6);
10879         if (ret)
10880                 return ret;
10881
10882         if (intel_crtc->plane)
10883                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10884         else
10885                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10886         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10887         intel_ring_emit(ring, MI_NOOP);
10888         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10889                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10890         intel_ring_emit(ring, fb->pitches[0]);
10891         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10892         intel_ring_emit(ring, MI_NOOP);
10893
10894         intel_mark_page_flip_active(intel_crtc);
10895         return 0;
10896 }
10897
10898 static int intel_gen4_queue_flip(struct drm_device *dev,
10899                                  struct drm_crtc *crtc,
10900                                  struct drm_framebuffer *fb,
10901                                  struct drm_i915_gem_object *obj,
10902                                  struct drm_i915_gem_request *req,
10903                                  uint32_t flags)
10904 {
10905         struct intel_engine_cs *ring = req->ring;
10906         struct drm_i915_private *dev_priv = dev->dev_private;
10907         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10908         uint32_t pf, pipesrc;
10909         int ret;
10910
10911         ret = intel_ring_begin(req, 4);
10912         if (ret)
10913                 return ret;
10914
10915         /* i965+ uses the linear or tiled offsets from the
10916          * Display Registers (which do not change across a page-flip)
10917          * so we need only reprogram the base address.
10918          */
10919         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10920                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10921         intel_ring_emit(ring, fb->pitches[0]);
10922         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10923                         obj->tiling_mode);
10924
10925         /* XXX Enabling the panel-fitter across page-flip is so far
10926          * untested on non-native modes, so ignore it for now.
10927          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10928          */
10929         pf = 0;
10930         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10931         intel_ring_emit(ring, pf | pipesrc);
10932
10933         intel_mark_page_flip_active(intel_crtc);
10934         return 0;
10935 }
10936
10937 static int intel_gen6_queue_flip(struct drm_device *dev,
10938                                  struct drm_crtc *crtc,
10939                                  struct drm_framebuffer *fb,
10940                                  struct drm_i915_gem_object *obj,
10941                                  struct drm_i915_gem_request *req,
10942                                  uint32_t flags)
10943 {
10944         struct intel_engine_cs *ring = req->ring;
10945         struct drm_i915_private *dev_priv = dev->dev_private;
10946         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10947         uint32_t pf, pipesrc;
10948         int ret;
10949
10950         ret = intel_ring_begin(req, 4);
10951         if (ret)
10952                 return ret;
10953
10954         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10955                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10956         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10957         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10958
10959         /* Contrary to the suggestions in the documentation,
10960          * "Enable Panel Fitter" does not seem to be required when page
10961          * flipping with a non-native mode, and worse causes a normal
10962          * modeset to fail.
10963          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10964          */
10965         pf = 0;
10966         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10967         intel_ring_emit(ring, pf | pipesrc);
10968
10969         intel_mark_page_flip_active(intel_crtc);
10970         return 0;
10971 }
10972
10973 static int intel_gen7_queue_flip(struct drm_device *dev,
10974                                  struct drm_crtc *crtc,
10975                                  struct drm_framebuffer *fb,
10976                                  struct drm_i915_gem_object *obj,
10977                                  struct drm_i915_gem_request *req,
10978                                  uint32_t flags)
10979 {
10980         struct intel_engine_cs *ring = req->ring;
10981         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10982         uint32_t plane_bit = 0;
10983         int len, ret;
10984
10985         switch (intel_crtc->plane) {
10986         case PLANE_A:
10987                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10988                 break;
10989         case PLANE_B:
10990                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10991                 break;
10992         case PLANE_C:
10993                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10994                 break;
10995         default:
10996                 WARN_ONCE(1, "unknown plane in flip command\n");
10997                 return -ENODEV;
10998         }
10999
11000         len = 4;
11001         if (ring->id == RCS) {
11002                 len += 6;
11003                 /*
11004                  * On Gen 8, SRM is now taking an extra dword to accommodate
11005                  * 48bits addresses, and we need a NOOP for the batch size to
11006                  * stay even.
11007                  */
11008                 if (IS_GEN8(dev))
11009                         len += 2;
11010         }
11011
11012         /*
11013          * BSpec MI_DISPLAY_FLIP for IVB:
11014          * "The full packet must be contained within the same cache line."
11015          *
11016          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11017          * cacheline, if we ever start emitting more commands before
11018          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11019          * then do the cacheline alignment, and finally emit the
11020          * MI_DISPLAY_FLIP.
11021          */
11022         ret = intel_ring_cacheline_align(req);
11023         if (ret)
11024                 return ret;
11025
11026         ret = intel_ring_begin(req, len);
11027         if (ret)
11028                 return ret;
11029
11030         /* Unmask the flip-done completion message. Note that the bspec says that
11031          * we should do this for both the BCS and RCS, and that we must not unmask
11032          * more than one flip event at any time (or ensure that one flip message
11033          * can be sent by waiting for flip-done prior to queueing new flips).
11034          * Experimentation says that BCS works despite DERRMR masking all
11035          * flip-done completion events and that unmasking all planes at once
11036          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11037          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11038          */
11039         if (ring->id == RCS) {
11040                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11041                 intel_ring_emit(ring, DERRMR);
11042                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11043                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11044                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11045                 if (IS_GEN8(dev))
11046                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11047                                               MI_SRM_LRM_GLOBAL_GTT);
11048                 else
11049                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11050                                               MI_SRM_LRM_GLOBAL_GTT);
11051                 intel_ring_emit(ring, DERRMR);
11052                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11053                 if (IS_GEN8(dev)) {
11054                         intel_ring_emit(ring, 0);
11055                         intel_ring_emit(ring, MI_NOOP);
11056                 }
11057         }
11058
11059         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11060         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11061         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11062         intel_ring_emit(ring, (MI_NOOP));
11063
11064         intel_mark_page_flip_active(intel_crtc);
11065         return 0;
11066 }
11067
11068 static bool use_mmio_flip(struct intel_engine_cs *ring,
11069                           struct drm_i915_gem_object *obj)
11070 {
11071         /*
11072          * This is not being used for older platforms, because
11073          * non-availability of flip done interrupt forces us to use
11074          * CS flips. Older platforms derive flip done using some clever
11075          * tricks involving the flip_pending status bits and vblank irqs.
11076          * So using MMIO flips there would disrupt this mechanism.
11077          */
11078
11079         if (ring == NULL)
11080                 return true;
11081
11082         if (INTEL_INFO(ring->dev)->gen < 5)
11083                 return false;
11084
11085         if (i915.use_mmio_flip < 0)
11086                 return false;
11087         else if (i915.use_mmio_flip > 0)
11088                 return true;
11089         else if (i915.enable_execlists)
11090                 return true;
11091         else
11092                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11093 }
11094
11095 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11096 {
11097         struct drm_device *dev = intel_crtc->base.dev;
11098         struct drm_i915_private *dev_priv = dev->dev_private;
11099         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11100         const enum pipe pipe = intel_crtc->pipe;
11101         u32 ctl, stride;
11102
11103         ctl = I915_READ(PLANE_CTL(pipe, 0));
11104         ctl &= ~PLANE_CTL_TILED_MASK;
11105         switch (fb->modifier[0]) {
11106         case DRM_FORMAT_MOD_NONE:
11107                 break;
11108         case I915_FORMAT_MOD_X_TILED:
11109                 ctl |= PLANE_CTL_TILED_X;
11110                 break;
11111         case I915_FORMAT_MOD_Y_TILED:
11112                 ctl |= PLANE_CTL_TILED_Y;
11113                 break;
11114         case I915_FORMAT_MOD_Yf_TILED:
11115                 ctl |= PLANE_CTL_TILED_YF;
11116                 break;
11117         default:
11118                 MISSING_CASE(fb->modifier[0]);
11119         }
11120
11121         /*
11122          * The stride is either expressed as a multiple of 64 bytes chunks for
11123          * linear buffers or in number of tiles for tiled buffers.
11124          */
11125         stride = fb->pitches[0] /
11126                  intel_fb_stride_alignment(dev, fb->modifier[0],
11127                                            fb->pixel_format);
11128
11129         /*
11130          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11131          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11132          */
11133         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11134         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11135
11136         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11137         POSTING_READ(PLANE_SURF(pipe, 0));
11138 }
11139
11140 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11141 {
11142         struct drm_device *dev = intel_crtc->base.dev;
11143         struct drm_i915_private *dev_priv = dev->dev_private;
11144         struct intel_framebuffer *intel_fb =
11145                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11146         struct drm_i915_gem_object *obj = intel_fb->obj;
11147         u32 dspcntr;
11148         u32 reg;
11149
11150         reg = DSPCNTR(intel_crtc->plane);
11151         dspcntr = I915_READ(reg);
11152
11153         if (obj->tiling_mode != I915_TILING_NONE)
11154                 dspcntr |= DISPPLANE_TILED;
11155         else
11156                 dspcntr &= ~DISPPLANE_TILED;
11157
11158         I915_WRITE(reg, dspcntr);
11159
11160         I915_WRITE(DSPSURF(intel_crtc->plane),
11161                    intel_crtc->unpin_work->gtt_offset);
11162         POSTING_READ(DSPSURF(intel_crtc->plane));
11163
11164 }
11165
11166 /*
11167  * XXX: This is the temporary way to update the plane registers until we get
11168  * around to using the usual plane update functions for MMIO flips
11169  */
11170 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11171 {
11172         struct drm_device *dev = intel_crtc->base.dev;
11173         u32 start_vbl_count;
11174
11175         intel_mark_page_flip_active(intel_crtc);
11176
11177         intel_pipe_update_start(intel_crtc, &start_vbl_count);
11178
11179         if (INTEL_INFO(dev)->gen >= 9)
11180                 skl_do_mmio_flip(intel_crtc);
11181         else
11182                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11183                 ilk_do_mmio_flip(intel_crtc);
11184
11185         intel_pipe_update_end(intel_crtc, start_vbl_count);
11186 }
11187
11188 static void intel_mmio_flip_work_func(struct work_struct *work)
11189 {
11190         struct intel_mmio_flip *mmio_flip =
11191                 container_of(work, struct intel_mmio_flip, work);
11192
11193         if (mmio_flip->req)
11194                 WARN_ON(__i915_wait_request(mmio_flip->req,
11195                                             mmio_flip->crtc->reset_counter,
11196                                             false, NULL,
11197                                             &mmio_flip->i915->rps.mmioflips));
11198
11199         intel_do_mmio_flip(mmio_flip->crtc);
11200
11201         i915_gem_request_unreference__unlocked(mmio_flip->req);
11202         kfree(mmio_flip);
11203 }
11204
11205 static int intel_queue_mmio_flip(struct drm_device *dev,
11206                                  struct drm_crtc *crtc,
11207                                  struct drm_framebuffer *fb,
11208                                  struct drm_i915_gem_object *obj,
11209                                  struct intel_engine_cs *ring,
11210                                  uint32_t flags)
11211 {
11212         struct intel_mmio_flip *mmio_flip;
11213
11214         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11215         if (mmio_flip == NULL)
11216                 return -ENOMEM;
11217
11218         mmio_flip->i915 = to_i915(dev);
11219         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11220         mmio_flip->crtc = to_intel_crtc(crtc);
11221
11222         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11223         schedule_work(&mmio_flip->work);
11224
11225         return 0;
11226 }
11227
11228 static int intel_default_queue_flip(struct drm_device *dev,
11229                                     struct drm_crtc *crtc,
11230                                     struct drm_framebuffer *fb,
11231                                     struct drm_i915_gem_object *obj,
11232                                     struct drm_i915_gem_request *req,
11233                                     uint32_t flags)
11234 {
11235         return -ENODEV;
11236 }
11237
11238 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11239                                          struct drm_crtc *crtc)
11240 {
11241         struct drm_i915_private *dev_priv = dev->dev_private;
11242         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11243         struct intel_unpin_work *work = intel_crtc->unpin_work;
11244         u32 addr;
11245
11246         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11247                 return true;
11248
11249         if (!work->enable_stall_check)
11250                 return false;
11251
11252         if (work->flip_ready_vblank == 0) {
11253                 if (work->flip_queued_req &&
11254                     !i915_gem_request_completed(work->flip_queued_req, true))
11255                         return false;
11256
11257                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11258         }
11259
11260         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11261                 return false;
11262
11263         /* Potential stall - if we see that the flip has happened,
11264          * assume a missed interrupt. */
11265         if (INTEL_INFO(dev)->gen >= 4)
11266                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11267         else
11268                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11269
11270         /* There is a potential issue here with a false positive after a flip
11271          * to the same address. We could address this by checking for a
11272          * non-incrementing frame counter.
11273          */
11274         return addr == work->gtt_offset;
11275 }
11276
11277 void intel_check_page_flip(struct drm_device *dev, int pipe)
11278 {
11279         struct drm_i915_private *dev_priv = dev->dev_private;
11280         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11281         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11282         struct intel_unpin_work *work;
11283
11284         WARN_ON(!in_interrupt());
11285
11286         if (crtc == NULL)
11287                 return;
11288
11289         spin_lock(&dev->event_lock);
11290         work = intel_crtc->unpin_work;
11291         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11292                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11293                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11294                 page_flip_completed(intel_crtc);
11295                 work = NULL;
11296         }
11297         if (work != NULL &&
11298             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11299                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11300         spin_unlock(&dev->event_lock);
11301 }
11302
11303 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11304                                 struct drm_framebuffer *fb,
11305                                 struct drm_pending_vblank_event *event,
11306                                 uint32_t page_flip_flags)
11307 {
11308         struct drm_device *dev = crtc->dev;
11309         struct drm_i915_private *dev_priv = dev->dev_private;
11310         struct drm_framebuffer *old_fb = crtc->primary->fb;
11311         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11312         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11313         struct drm_plane *primary = crtc->primary;
11314         enum pipe pipe = intel_crtc->pipe;
11315         struct intel_unpin_work *work;
11316         struct intel_engine_cs *ring;
11317         bool mmio_flip;
11318         struct drm_i915_gem_request *request = NULL;
11319         int ret;
11320
11321         /*
11322          * drm_mode_page_flip_ioctl() should already catch this, but double
11323          * check to be safe.  In the future we may enable pageflipping from
11324          * a disabled primary plane.
11325          */
11326         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11327                 return -EBUSY;
11328
11329         /* Can't change pixel format via MI display flips. */
11330         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11331                 return -EINVAL;
11332
11333         /*
11334          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11335          * Note that pitch changes could also affect these register.
11336          */
11337         if (INTEL_INFO(dev)->gen > 3 &&
11338             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11339              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11340                 return -EINVAL;
11341
11342         if (i915_terminally_wedged(&dev_priv->gpu_error))
11343                 goto out_hang;
11344
11345         work = kzalloc(sizeof(*work), GFP_KERNEL);
11346         if (work == NULL)
11347                 return -ENOMEM;
11348
11349         work->event = event;
11350         work->crtc = crtc;
11351         work->old_fb = old_fb;
11352         INIT_WORK(&work->work, intel_unpin_work_fn);
11353
11354         ret = drm_crtc_vblank_get(crtc);
11355         if (ret)
11356                 goto free_work;
11357
11358         /* We borrow the event spin lock for protecting unpin_work */
11359         spin_lock_irq(&dev->event_lock);
11360         if (intel_crtc->unpin_work) {
11361                 /* Before declaring the flip queue wedged, check if
11362                  * the hardware completed the operation behind our backs.
11363                  */
11364                 if (__intel_pageflip_stall_check(dev, crtc)) {
11365                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11366                         page_flip_completed(intel_crtc);
11367                 } else {
11368                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11369                         spin_unlock_irq(&dev->event_lock);
11370
11371                         drm_crtc_vblank_put(crtc);
11372                         kfree(work);
11373                         return -EBUSY;
11374                 }
11375         }
11376         intel_crtc->unpin_work = work;
11377         spin_unlock_irq(&dev->event_lock);
11378
11379         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11380                 flush_workqueue(dev_priv->wq);
11381
11382         /* Reference the objects for the scheduled work. */
11383         drm_framebuffer_reference(work->old_fb);
11384         drm_gem_object_reference(&obj->base);
11385
11386         crtc->primary->fb = fb;
11387         update_state_fb(crtc->primary);
11388
11389         work->pending_flip_obj = obj;
11390
11391         ret = i915_mutex_lock_interruptible(dev);
11392         if (ret)
11393                 goto cleanup;
11394
11395         atomic_inc(&intel_crtc->unpin_work_count);
11396         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11397
11398         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11399                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11400
11401         if (IS_VALLEYVIEW(dev)) {
11402                 ring = &dev_priv->ring[BCS];
11403                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11404                         /* vlv: DISPLAY_FLIP fails to change tiling */
11405                         ring = NULL;
11406         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11407                 ring = &dev_priv->ring[BCS];
11408         } else if (INTEL_INFO(dev)->gen >= 7) {
11409                 ring = i915_gem_request_get_ring(obj->last_write_req);
11410                 if (ring == NULL || ring->id != RCS)
11411                         ring = &dev_priv->ring[BCS];
11412         } else {
11413                 ring = &dev_priv->ring[RCS];
11414         }
11415
11416         mmio_flip = use_mmio_flip(ring, obj);
11417
11418         /* When using CS flips, we want to emit semaphores between rings.
11419          * However, when using mmio flips we will create a task to do the
11420          * synchronisation, so all we want here is to pin the framebuffer
11421          * into the display plane and skip any waits.
11422          */
11423         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11424                                          crtc->primary->state,
11425                                          mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11426         if (ret)
11427                 goto cleanup_pending;
11428
11429         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11430                                                   + intel_crtc->dspaddr_offset;
11431
11432         if (mmio_flip) {
11433                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11434                                             page_flip_flags);
11435                 if (ret)
11436                         goto cleanup_unpin;
11437
11438                 i915_gem_request_assign(&work->flip_queued_req,
11439                                         obj->last_write_req);
11440         } else {
11441                 if (!request) {
11442                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11443                         if (ret)
11444                                 goto cleanup_unpin;
11445                 }
11446
11447                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11448                                                    page_flip_flags);
11449                 if (ret)
11450                         goto cleanup_unpin;
11451
11452                 i915_gem_request_assign(&work->flip_queued_req, request);
11453         }
11454
11455         if (request)
11456                 i915_add_request_no_flush(request);
11457
11458         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11459         work->enable_stall_check = true;
11460
11461         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11462                           to_intel_plane(primary)->frontbuffer_bit);
11463         mutex_unlock(&dev->struct_mutex);
11464
11465         intel_fbc_disable_crtc(intel_crtc);
11466         intel_frontbuffer_flip_prepare(dev,
11467                                        to_intel_plane(primary)->frontbuffer_bit);
11468
11469         trace_i915_flip_request(intel_crtc->plane, obj);
11470
11471         return 0;
11472
11473 cleanup_unpin:
11474         intel_unpin_fb_obj(fb, crtc->primary->state);
11475 cleanup_pending:
11476         if (request)
11477                 i915_gem_request_cancel(request);
11478         atomic_dec(&intel_crtc->unpin_work_count);
11479         mutex_unlock(&dev->struct_mutex);
11480 cleanup:
11481         crtc->primary->fb = old_fb;
11482         update_state_fb(crtc->primary);
11483
11484         drm_gem_object_unreference_unlocked(&obj->base);
11485         drm_framebuffer_unreference(work->old_fb);
11486
11487         spin_lock_irq(&dev->event_lock);
11488         intel_crtc->unpin_work = NULL;
11489         spin_unlock_irq(&dev->event_lock);
11490
11491         drm_crtc_vblank_put(crtc);
11492 free_work:
11493         kfree(work);
11494
11495         if (ret == -EIO) {
11496                 struct drm_atomic_state *state;
11497                 struct drm_plane_state *plane_state;
11498
11499 out_hang:
11500                 state = drm_atomic_state_alloc(dev);
11501                 if (!state)
11502                         return -ENOMEM;
11503                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11504
11505 retry:
11506                 plane_state = drm_atomic_get_plane_state(state, primary);
11507                 ret = PTR_ERR_OR_ZERO(plane_state);
11508                 if (!ret) {
11509                         drm_atomic_set_fb_for_plane(plane_state, fb);
11510
11511                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11512                         if (!ret)
11513                                 ret = drm_atomic_commit(state);
11514                 }
11515
11516                 if (ret == -EDEADLK) {
11517                         drm_modeset_backoff(state->acquire_ctx);
11518                         drm_atomic_state_clear(state);
11519                         goto retry;
11520                 }
11521
11522                 if (ret)
11523                         drm_atomic_state_free(state);
11524
11525                 if (ret == 0 && event) {
11526                         spin_lock_irq(&dev->event_lock);
11527                         drm_send_vblank_event(dev, pipe, event);
11528                         spin_unlock_irq(&dev->event_lock);
11529                 }
11530         }
11531         return ret;
11532 }
11533
11534
11535 /**
11536  * intel_wm_need_update - Check whether watermarks need updating
11537  * @plane: drm plane
11538  * @state: new plane state
11539  *
11540  * Check current plane state versus the new one to determine whether
11541  * watermarks need to be recalculated.
11542  *
11543  * Returns true or false.
11544  */
11545 static bool intel_wm_need_update(struct drm_plane *plane,
11546                                  struct drm_plane_state *state)
11547 {
11548         /* Update watermarks on tiling changes. */
11549         if (!plane->state->fb || !state->fb ||
11550             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11551             plane->state->rotation != state->rotation)
11552                 return true;
11553
11554         if (plane->state->crtc_w != state->crtc_w)
11555                 return true;
11556
11557         return false;
11558 }
11559
11560 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11561                                     struct drm_plane_state *plane_state)
11562 {
11563         struct drm_crtc *crtc = crtc_state->crtc;
11564         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11565         struct drm_plane *plane = plane_state->plane;
11566         struct drm_device *dev = crtc->dev;
11567         struct drm_i915_private *dev_priv = dev->dev_private;
11568         struct intel_plane_state *old_plane_state =
11569                 to_intel_plane_state(plane->state);
11570         int idx = intel_crtc->base.base.id, ret;
11571         int i = drm_plane_index(plane);
11572         bool mode_changed = needs_modeset(crtc_state);
11573         bool was_crtc_enabled = crtc->state->active;
11574         bool is_crtc_enabled = crtc_state->active;
11575
11576         bool turn_off, turn_on, visible, was_visible;
11577         struct drm_framebuffer *fb = plane_state->fb;
11578
11579         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11580             plane->type != DRM_PLANE_TYPE_CURSOR) {
11581                 ret = skl_update_scaler_plane(
11582                         to_intel_crtc_state(crtc_state),
11583                         to_intel_plane_state(plane_state));
11584                 if (ret)
11585                         return ret;
11586         }
11587
11588         /*
11589          * Disabling a plane is always okay; we just need to update
11590          * fb tracking in a special way since cleanup_fb() won't
11591          * get called by the plane helpers.
11592          */
11593         if (old_plane_state->base.fb && !fb)
11594                 intel_crtc->atomic.disabled_planes |= 1 << i;
11595
11596         was_visible = old_plane_state->visible;
11597         visible = to_intel_plane_state(plane_state)->visible;
11598
11599         if (!was_crtc_enabled && WARN_ON(was_visible))
11600                 was_visible = false;
11601
11602         if (!is_crtc_enabled && WARN_ON(visible))
11603                 visible = false;
11604
11605         if (!was_visible && !visible)
11606                 return 0;
11607
11608         turn_off = was_visible && (!visible || mode_changed);
11609         turn_on = visible && (!was_visible || mode_changed);
11610
11611         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11612                          plane->base.id, fb ? fb->base.id : -1);
11613
11614         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11615                          plane->base.id, was_visible, visible,
11616                          turn_off, turn_on, mode_changed);
11617
11618         if (turn_on) {
11619                 intel_crtc->atomic.update_wm_pre = true;
11620                 /* must disable cxsr around plane enable/disable */
11621                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11622                         intel_crtc->atomic.disable_cxsr = true;
11623                         /* to potentially re-enable cxsr */
11624                         intel_crtc->atomic.wait_vblank = true;
11625                         intel_crtc->atomic.update_wm_post = true;
11626                 }
11627         } else if (turn_off) {
11628                 intel_crtc->atomic.update_wm_post = true;
11629                 /* must disable cxsr around plane enable/disable */
11630                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11631                         if (is_crtc_enabled)
11632                                 intel_crtc->atomic.wait_vblank = true;
11633                         intel_crtc->atomic.disable_cxsr = true;
11634                 }
11635         } else if (intel_wm_need_update(plane, plane_state)) {
11636                 intel_crtc->atomic.update_wm_pre = true;
11637         }
11638
11639         if (visible)
11640                 intel_crtc->atomic.fb_bits |=
11641                         to_intel_plane(plane)->frontbuffer_bit;
11642
11643         switch (plane->type) {
11644         case DRM_PLANE_TYPE_PRIMARY:
11645                 intel_crtc->atomic.wait_for_flips = true;
11646                 intel_crtc->atomic.pre_disable_primary = turn_off;
11647                 intel_crtc->atomic.post_enable_primary = turn_on;
11648
11649                 if (turn_off) {
11650                         /*
11651                          * FIXME: Actually if we will still have any other
11652                          * plane enabled on the pipe we could let IPS enabled
11653                          * still, but for now lets consider that when we make
11654                          * primary invisible by setting DSPCNTR to 0 on
11655                          * update_primary_plane function IPS needs to be
11656                          * disable.
11657                          */
11658                         intel_crtc->atomic.disable_ips = true;
11659
11660                         intel_crtc->atomic.disable_fbc = true;
11661                 }
11662
11663                 /*
11664                  * FBC does not work on some platforms for rotated
11665                  * planes, so disable it when rotation is not 0 and
11666                  * update it when rotation is set back to 0.
11667                  *
11668                  * FIXME: This is redundant with the fbc update done in
11669                  * the primary plane enable function except that that
11670                  * one is done too late. We eventually need to unify
11671                  * this.
11672                  */
11673
11674                 if (visible &&
11675                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11676                     dev_priv->fbc.crtc == intel_crtc &&
11677                     plane_state->rotation != BIT(DRM_ROTATE_0))
11678                         intel_crtc->atomic.disable_fbc = true;
11679
11680                 /*
11681                  * BDW signals flip done immediately if the plane
11682                  * is disabled, even if the plane enable is already
11683                  * armed to occur at the next vblank :(
11684                  */
11685                 if (turn_on && IS_BROADWELL(dev))
11686                         intel_crtc->atomic.wait_vblank = true;
11687
11688                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11689                 break;
11690         case DRM_PLANE_TYPE_CURSOR:
11691                 break;
11692         case DRM_PLANE_TYPE_OVERLAY:
11693                 if (turn_off && !mode_changed) {
11694                         intel_crtc->atomic.wait_vblank = true;
11695                         intel_crtc->atomic.update_sprite_watermarks |=
11696                                 1 << i;
11697                 }
11698         }
11699         return 0;
11700 }
11701
11702 static bool encoders_cloneable(const struct intel_encoder *a,
11703                                const struct intel_encoder *b)
11704 {
11705         /* masks could be asymmetric, so check both ways */
11706         return a == b || (a->cloneable & (1 << b->type) &&
11707                           b->cloneable & (1 << a->type));
11708 }
11709
11710 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11711                                          struct intel_crtc *crtc,
11712                                          struct intel_encoder *encoder)
11713 {
11714         struct intel_encoder *source_encoder;
11715         struct drm_connector *connector;
11716         struct drm_connector_state *connector_state;
11717         int i;
11718
11719         for_each_connector_in_state(state, connector, connector_state, i) {
11720                 if (connector_state->crtc != &crtc->base)
11721                         continue;
11722
11723                 source_encoder =
11724                         to_intel_encoder(connector_state->best_encoder);
11725                 if (!encoders_cloneable(encoder, source_encoder))
11726                         return false;
11727         }
11728
11729         return true;
11730 }
11731
11732 static bool check_encoder_cloning(struct drm_atomic_state *state,
11733                                   struct intel_crtc *crtc)
11734 {
11735         struct intel_encoder *encoder;
11736         struct drm_connector *connector;
11737         struct drm_connector_state *connector_state;
11738         int i;
11739
11740         for_each_connector_in_state(state, connector, connector_state, i) {
11741                 if (connector_state->crtc != &crtc->base)
11742                         continue;
11743
11744                 encoder = to_intel_encoder(connector_state->best_encoder);
11745                 if (!check_single_encoder_cloning(state, crtc, encoder))
11746                         return false;
11747         }
11748
11749         return true;
11750 }
11751
11752 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11753                                    struct drm_crtc_state *crtc_state)
11754 {
11755         struct drm_device *dev = crtc->dev;
11756         struct drm_i915_private *dev_priv = dev->dev_private;
11757         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11758         struct intel_crtc_state *pipe_config =
11759                 to_intel_crtc_state(crtc_state);
11760         struct drm_atomic_state *state = crtc_state->state;
11761         int ret;
11762         bool mode_changed = needs_modeset(crtc_state);
11763
11764         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11765                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11766                 return -EINVAL;
11767         }
11768
11769         if (mode_changed && !crtc_state->active)
11770                 intel_crtc->atomic.update_wm_post = true;
11771
11772         if (mode_changed && crtc_state->enable &&
11773             dev_priv->display.crtc_compute_clock &&
11774             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11775                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11776                                                            pipe_config);
11777                 if (ret)
11778                         return ret;
11779         }
11780
11781         ret = 0;
11782         if (INTEL_INFO(dev)->gen >= 9) {
11783                 if (mode_changed)
11784                         ret = skl_update_scaler_crtc(pipe_config);
11785
11786                 if (!ret)
11787                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11788                                                          pipe_config);
11789         }
11790
11791         return ret;
11792 }
11793
11794 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11795         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11796         .load_lut = intel_crtc_load_lut,
11797         .atomic_begin = intel_begin_crtc_commit,
11798         .atomic_flush = intel_finish_crtc_commit,
11799         .atomic_check = intel_crtc_atomic_check,
11800 };
11801
11802 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11803 {
11804         struct intel_connector *connector;
11805
11806         for_each_intel_connector(dev, connector) {
11807                 if (connector->base.encoder) {
11808                         connector->base.state->best_encoder =
11809                                 connector->base.encoder;
11810                         connector->base.state->crtc =
11811                                 connector->base.encoder->crtc;
11812                 } else {
11813                         connector->base.state->best_encoder = NULL;
11814                         connector->base.state->crtc = NULL;
11815                 }
11816         }
11817 }
11818
11819 static void
11820 connected_sink_compute_bpp(struct intel_connector *connector,
11821                            struct intel_crtc_state *pipe_config)
11822 {
11823         int bpp = pipe_config->pipe_bpp;
11824
11825         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11826                 connector->base.base.id,
11827                 connector->base.name);
11828
11829         /* Don't use an invalid EDID bpc value */
11830         if (connector->base.display_info.bpc &&
11831             connector->base.display_info.bpc * 3 < bpp) {
11832                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11833                               bpp, connector->base.display_info.bpc*3);
11834                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11835         }
11836
11837         /* Clamp bpp to 8 on screens without EDID 1.4 */
11838         if (connector->base.display_info.bpc == 0 && bpp > 24) {
11839                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11840                               bpp);
11841                 pipe_config->pipe_bpp = 24;
11842         }
11843 }
11844
11845 static int
11846 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11847                           struct intel_crtc_state *pipe_config)
11848 {
11849         struct drm_device *dev = crtc->base.dev;
11850         struct drm_atomic_state *state;
11851         struct drm_connector *connector;
11852         struct drm_connector_state *connector_state;
11853         int bpp, i;
11854
11855         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11856                 bpp = 10*3;
11857         else if (INTEL_INFO(dev)->gen >= 5)
11858                 bpp = 12*3;
11859         else
11860                 bpp = 8*3;
11861
11862
11863         pipe_config->pipe_bpp = bpp;
11864
11865         state = pipe_config->base.state;
11866
11867         /* Clamp display bpp to EDID value */
11868         for_each_connector_in_state(state, connector, connector_state, i) {
11869                 if (connector_state->crtc != &crtc->base)
11870                         continue;
11871
11872                 connected_sink_compute_bpp(to_intel_connector(connector),
11873                                            pipe_config);
11874         }
11875
11876         return bpp;
11877 }
11878
11879 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11880 {
11881         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11882                         "type: 0x%x flags: 0x%x\n",
11883                 mode->crtc_clock,
11884                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11885                 mode->crtc_hsync_end, mode->crtc_htotal,
11886                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11887                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11888 }
11889
11890 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11891                                    struct intel_crtc_state *pipe_config,
11892                                    const char *context)
11893 {
11894         struct drm_device *dev = crtc->base.dev;
11895         struct drm_plane *plane;
11896         struct intel_plane *intel_plane;
11897         struct intel_plane_state *state;
11898         struct drm_framebuffer *fb;
11899
11900         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11901                       context, pipe_config, pipe_name(crtc->pipe));
11902
11903         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11904         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11905                       pipe_config->pipe_bpp, pipe_config->dither);
11906         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11907                       pipe_config->has_pch_encoder,
11908                       pipe_config->fdi_lanes,
11909                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11910                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11911                       pipe_config->fdi_m_n.tu);
11912         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11913                       pipe_config->has_dp_encoder,
11914                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11915                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11916                       pipe_config->dp_m_n.tu);
11917
11918         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11919                       pipe_config->has_dp_encoder,
11920                       pipe_config->dp_m2_n2.gmch_m,
11921                       pipe_config->dp_m2_n2.gmch_n,
11922                       pipe_config->dp_m2_n2.link_m,
11923                       pipe_config->dp_m2_n2.link_n,
11924                       pipe_config->dp_m2_n2.tu);
11925
11926         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11927                       pipe_config->has_audio,
11928                       pipe_config->has_infoframe);
11929
11930         DRM_DEBUG_KMS("requested mode:\n");
11931         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11932         DRM_DEBUG_KMS("adjusted mode:\n");
11933         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11934         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11935         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11936         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11937                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11938         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11939                       crtc->num_scalers,
11940                       pipe_config->scaler_state.scaler_users,
11941                       pipe_config->scaler_state.scaler_id);
11942         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11943                       pipe_config->gmch_pfit.control,
11944                       pipe_config->gmch_pfit.pgm_ratios,
11945                       pipe_config->gmch_pfit.lvds_border_bits);
11946         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11947                       pipe_config->pch_pfit.pos,
11948                       pipe_config->pch_pfit.size,
11949                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11950         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11951         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11952
11953         if (IS_BROXTON(dev)) {
11954                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11955                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11956                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11957                               pipe_config->ddi_pll_sel,
11958                               pipe_config->dpll_hw_state.ebb0,
11959                               pipe_config->dpll_hw_state.ebb4,
11960                               pipe_config->dpll_hw_state.pll0,
11961                               pipe_config->dpll_hw_state.pll1,
11962                               pipe_config->dpll_hw_state.pll2,
11963                               pipe_config->dpll_hw_state.pll3,
11964                               pipe_config->dpll_hw_state.pll6,
11965                               pipe_config->dpll_hw_state.pll8,
11966                               pipe_config->dpll_hw_state.pll9,
11967                               pipe_config->dpll_hw_state.pll10,
11968                               pipe_config->dpll_hw_state.pcsdw12);
11969         } else if (IS_SKYLAKE(dev)) {
11970                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11971                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11972                               pipe_config->ddi_pll_sel,
11973                               pipe_config->dpll_hw_state.ctrl1,
11974                               pipe_config->dpll_hw_state.cfgcr1,
11975                               pipe_config->dpll_hw_state.cfgcr2);
11976         } else if (HAS_DDI(dev)) {
11977                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11978                               pipe_config->ddi_pll_sel,
11979                               pipe_config->dpll_hw_state.wrpll);
11980         } else {
11981                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11982                               "fp0: 0x%x, fp1: 0x%x\n",
11983                               pipe_config->dpll_hw_state.dpll,
11984                               pipe_config->dpll_hw_state.dpll_md,
11985                               pipe_config->dpll_hw_state.fp0,
11986                               pipe_config->dpll_hw_state.fp1);
11987         }
11988
11989         DRM_DEBUG_KMS("planes on this crtc\n");
11990         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11991                 intel_plane = to_intel_plane(plane);
11992                 if (intel_plane->pipe != crtc->pipe)
11993                         continue;
11994
11995                 state = to_intel_plane_state(plane->state);
11996                 fb = state->base.fb;
11997                 if (!fb) {
11998                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11999                                 "disabled, scaler_id = %d\n",
12000                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12001                                 plane->base.id, intel_plane->pipe,
12002                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12003                                 drm_plane_index(plane), state->scaler_id);
12004                         continue;
12005                 }
12006
12007                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12008                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12009                         plane->base.id, intel_plane->pipe,
12010                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12011                         drm_plane_index(plane));
12012                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12013                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12014                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12015                         state->scaler_id,
12016                         state->src.x1 >> 16, state->src.y1 >> 16,
12017                         drm_rect_width(&state->src) >> 16,
12018                         drm_rect_height(&state->src) >> 16,
12019                         state->dst.x1, state->dst.y1,
12020                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12021         }
12022 }
12023
12024 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12025 {
12026         struct drm_device *dev = state->dev;
12027         struct intel_encoder *encoder;
12028         struct drm_connector *connector;
12029         struct drm_connector_state *connector_state;
12030         unsigned int used_ports = 0;
12031         int i;
12032
12033         /*
12034          * Walk the connector list instead of the encoder
12035          * list to detect the problem on ddi platforms
12036          * where there's just one encoder per digital port.
12037          */
12038         for_each_connector_in_state(state, connector, connector_state, i) {
12039                 if (!connector_state->best_encoder)
12040                         continue;
12041
12042                 encoder = to_intel_encoder(connector_state->best_encoder);
12043
12044                 WARN_ON(!connector_state->crtc);
12045
12046                 switch (encoder->type) {
12047                         unsigned int port_mask;
12048                 case INTEL_OUTPUT_UNKNOWN:
12049                         if (WARN_ON(!HAS_DDI(dev)))
12050                                 break;
12051                 case INTEL_OUTPUT_DISPLAYPORT:
12052                 case INTEL_OUTPUT_HDMI:
12053                 case INTEL_OUTPUT_EDP:
12054                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12055
12056                         /* the same port mustn't appear more than once */
12057                         if (used_ports & port_mask)
12058                                 return false;
12059
12060                         used_ports |= port_mask;
12061                 default:
12062                         break;
12063                 }
12064         }
12065
12066         return true;
12067 }
12068
12069 static void
12070 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12071 {
12072         struct drm_crtc_state tmp_state;
12073         struct intel_crtc_scaler_state scaler_state;
12074         struct intel_dpll_hw_state dpll_hw_state;
12075         enum intel_dpll_id shared_dpll;
12076         uint32_t ddi_pll_sel;
12077         bool force_thru;
12078
12079         /* FIXME: before the switch to atomic started, a new pipe_config was
12080          * kzalloc'd. Code that depends on any field being zero should be
12081          * fixed, so that the crtc_state can be safely duplicated. For now,
12082          * only fields that are know to not cause problems are preserved. */
12083
12084         tmp_state = crtc_state->base;
12085         scaler_state = crtc_state->scaler_state;
12086         shared_dpll = crtc_state->shared_dpll;
12087         dpll_hw_state = crtc_state->dpll_hw_state;
12088         ddi_pll_sel = crtc_state->ddi_pll_sel;
12089         force_thru = crtc_state->pch_pfit.force_thru;
12090
12091         memset(crtc_state, 0, sizeof *crtc_state);
12092
12093         crtc_state->base = tmp_state;
12094         crtc_state->scaler_state = scaler_state;
12095         crtc_state->shared_dpll = shared_dpll;
12096         crtc_state->dpll_hw_state = dpll_hw_state;
12097         crtc_state->ddi_pll_sel = ddi_pll_sel;
12098         crtc_state->pch_pfit.force_thru = force_thru;
12099 }
12100
12101 static int
12102 intel_modeset_pipe_config(struct drm_crtc *crtc,
12103                           struct intel_crtc_state *pipe_config)
12104 {
12105         struct drm_atomic_state *state = pipe_config->base.state;
12106         struct intel_encoder *encoder;
12107         struct drm_connector *connector;
12108         struct drm_connector_state *connector_state;
12109         int base_bpp, ret = -EINVAL;
12110         int i;
12111         bool retry = true;
12112
12113         clear_intel_crtc_state(pipe_config);
12114
12115         pipe_config->cpu_transcoder =
12116                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12117
12118         /*
12119          * Sanitize sync polarity flags based on requested ones. If neither
12120          * positive or negative polarity is requested, treat this as meaning
12121          * negative polarity.
12122          */
12123         if (!(pipe_config->base.adjusted_mode.flags &
12124               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12125                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12126
12127         if (!(pipe_config->base.adjusted_mode.flags &
12128               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12129                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12130
12131         /* Compute a starting value for pipe_config->pipe_bpp taking the source
12132          * plane pixel format and any sink constraints into account. Returns the
12133          * source plane bpp so that dithering can be selected on mismatches
12134          * after encoders and crtc also have had their say. */
12135         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12136                                              pipe_config);
12137         if (base_bpp < 0)
12138                 goto fail;
12139
12140         /*
12141          * Determine the real pipe dimensions. Note that stereo modes can
12142          * increase the actual pipe size due to the frame doubling and
12143          * insertion of additional space for blanks between the frame. This
12144          * is stored in the crtc timings. We use the requested mode to do this
12145          * computation to clearly distinguish it from the adjusted mode, which
12146          * can be changed by the connectors in the below retry loop.
12147          */
12148         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12149                                &pipe_config->pipe_src_w,
12150                                &pipe_config->pipe_src_h);
12151
12152 encoder_retry:
12153         /* Ensure the port clock defaults are reset when retrying. */
12154         pipe_config->port_clock = 0;
12155         pipe_config->pixel_multiplier = 1;
12156
12157         /* Fill in default crtc timings, allow encoders to overwrite them. */
12158         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12159                               CRTC_STEREO_DOUBLE);
12160
12161         /* Pass our mode to the connectors and the CRTC to give them a chance to
12162          * adjust it according to limitations or connector properties, and also
12163          * a chance to reject the mode entirely.
12164          */
12165         for_each_connector_in_state(state, connector, connector_state, i) {
12166                 if (connector_state->crtc != crtc)
12167                         continue;
12168
12169                 encoder = to_intel_encoder(connector_state->best_encoder);
12170
12171                 if (!(encoder->compute_config(encoder, pipe_config))) {
12172                         DRM_DEBUG_KMS("Encoder config failure\n");
12173                         goto fail;
12174                 }
12175         }
12176
12177         /* Set default port clock if not overwritten by the encoder. Needs to be
12178          * done afterwards in case the encoder adjusts the mode. */
12179         if (!pipe_config->port_clock)
12180                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12181                         * pipe_config->pixel_multiplier;
12182
12183         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12184         if (ret < 0) {
12185                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12186                 goto fail;
12187         }
12188
12189         if (ret == RETRY) {
12190                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12191                         ret = -EINVAL;
12192                         goto fail;
12193                 }
12194
12195                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12196                 retry = false;
12197                 goto encoder_retry;
12198         }
12199
12200         /* Dithering seems to not pass-through bits correctly when it should, so
12201          * only enable it on 6bpc panels. */
12202         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12203         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12204                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12205
12206 fail:
12207         return ret;
12208 }
12209
12210 static void
12211 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12212 {
12213         struct drm_crtc *crtc;
12214         struct drm_crtc_state *crtc_state;
12215         int i;
12216
12217         /* Double check state. */
12218         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12219                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12220
12221                 /* Update hwmode for vblank functions */
12222                 if (crtc->state->active)
12223                         crtc->hwmode = crtc->state->adjusted_mode;
12224                 else
12225                         crtc->hwmode.crtc_clock = 0;
12226         }
12227 }
12228
12229 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12230 {
12231         int diff;
12232
12233         if (clock1 == clock2)
12234                 return true;
12235
12236         if (!clock1 || !clock2)
12237                 return false;
12238
12239         diff = abs(clock1 - clock2);
12240
12241         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12242                 return true;
12243
12244         return false;
12245 }
12246
12247 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12248         list_for_each_entry((intel_crtc), \
12249                             &(dev)->mode_config.crtc_list, \
12250                             base.head) \
12251                 if (mask & (1 <<(intel_crtc)->pipe))
12252
12253
12254 static bool
12255 intel_compare_m_n(unsigned int m, unsigned int n,
12256                   unsigned int m2, unsigned int n2,
12257                   bool exact)
12258 {
12259         if (m == m2 && n == n2)
12260                 return true;
12261
12262         if (exact || !m || !n || !m2 || !n2)
12263                 return false;
12264
12265         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12266
12267         if (m > m2) {
12268                 while (m > m2) {
12269                         m2 <<= 1;
12270                         n2 <<= 1;
12271                 }
12272         } else if (m < m2) {
12273                 while (m < m2) {
12274                         m <<= 1;
12275                         n <<= 1;
12276                 }
12277         }
12278
12279         return m == m2 && n == n2;
12280 }
12281
12282 static bool
12283 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12284                        struct intel_link_m_n *m2_n2,
12285                        bool adjust)
12286 {
12287         if (m_n->tu == m2_n2->tu &&
12288             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12289                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12290             intel_compare_m_n(m_n->link_m, m_n->link_n,
12291                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12292                 if (adjust)
12293                         *m2_n2 = *m_n;
12294
12295                 return true;
12296         }
12297
12298         return false;
12299 }
12300
12301 static bool
12302 intel_pipe_config_compare(struct drm_device *dev,
12303                           struct intel_crtc_state *current_config,
12304                           struct intel_crtc_state *pipe_config,
12305                           bool adjust)
12306 {
12307         bool ret = true;
12308
12309 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12310         do { \
12311                 if (!adjust) \
12312                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12313                 else \
12314                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12315         } while (0)
12316
12317 #define PIPE_CONF_CHECK_X(name) \
12318         if (current_config->name != pipe_config->name) { \
12319                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12320                           "(expected 0x%08x, found 0x%08x)\n", \
12321                           current_config->name, \
12322                           pipe_config->name); \
12323                 ret = false; \
12324         }
12325
12326 #define PIPE_CONF_CHECK_I(name) \
12327         if (current_config->name != pipe_config->name) { \
12328                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12329                           "(expected %i, found %i)\n", \
12330                           current_config->name, \
12331                           pipe_config->name); \
12332                 ret = false; \
12333         }
12334
12335 #define PIPE_CONF_CHECK_M_N(name) \
12336         if (!intel_compare_link_m_n(&current_config->name, \
12337                                     &pipe_config->name,\
12338                                     adjust)) { \
12339                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12340                           "(expected tu %i gmch %i/%i link %i/%i, " \
12341                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12342                           current_config->name.tu, \
12343                           current_config->name.gmch_m, \
12344                           current_config->name.gmch_n, \
12345                           current_config->name.link_m, \
12346                           current_config->name.link_n, \
12347                           pipe_config->name.tu, \
12348                           pipe_config->name.gmch_m, \
12349                           pipe_config->name.gmch_n, \
12350                           pipe_config->name.link_m, \
12351                           pipe_config->name.link_n); \
12352                 ret = false; \
12353         }
12354
12355 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12356         if (!intel_compare_link_m_n(&current_config->name, \
12357                                     &pipe_config->name, adjust) && \
12358             !intel_compare_link_m_n(&current_config->alt_name, \
12359                                     &pipe_config->name, adjust)) { \
12360                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12361                           "(expected tu %i gmch %i/%i link %i/%i, " \
12362                           "or tu %i gmch %i/%i link %i/%i, " \
12363                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12364                           current_config->name.tu, \
12365                           current_config->name.gmch_m, \
12366                           current_config->name.gmch_n, \
12367                           current_config->name.link_m, \
12368                           current_config->name.link_n, \
12369                           current_config->alt_name.tu, \
12370                           current_config->alt_name.gmch_m, \
12371                           current_config->alt_name.gmch_n, \
12372                           current_config->alt_name.link_m, \
12373                           current_config->alt_name.link_n, \
12374                           pipe_config->name.tu, \
12375                           pipe_config->name.gmch_m, \
12376                           pipe_config->name.gmch_n, \
12377                           pipe_config->name.link_m, \
12378                           pipe_config->name.link_n); \
12379                 ret = false; \
12380         }
12381
12382 /* This is required for BDW+ where there is only one set of registers for
12383  * switching between high and low RR.
12384  * This macro can be used whenever a comparison has to be made between one
12385  * hw state and multiple sw state variables.
12386  */
12387 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12388         if ((current_config->name != pipe_config->name) && \
12389                 (current_config->alt_name != pipe_config->name)) { \
12390                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12391                                   "(expected %i or %i, found %i)\n", \
12392                                   current_config->name, \
12393                                   current_config->alt_name, \
12394                                   pipe_config->name); \
12395                         ret = false; \
12396         }
12397
12398 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12399         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12400                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12401                           "(expected %i, found %i)\n", \
12402                           current_config->name & (mask), \
12403                           pipe_config->name & (mask)); \
12404                 ret = false; \
12405         }
12406
12407 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12408         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12409                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12410                           "(expected %i, found %i)\n", \
12411                           current_config->name, \
12412                           pipe_config->name); \
12413                 ret = false; \
12414         }
12415
12416 #define PIPE_CONF_QUIRK(quirk)  \
12417         ((current_config->quirks | pipe_config->quirks) & (quirk))
12418
12419         PIPE_CONF_CHECK_I(cpu_transcoder);
12420
12421         PIPE_CONF_CHECK_I(has_pch_encoder);
12422         PIPE_CONF_CHECK_I(fdi_lanes);
12423         PIPE_CONF_CHECK_M_N(fdi_m_n);
12424
12425         PIPE_CONF_CHECK_I(has_dp_encoder);
12426
12427         if (INTEL_INFO(dev)->gen < 8) {
12428                 PIPE_CONF_CHECK_M_N(dp_m_n);
12429
12430                 PIPE_CONF_CHECK_I(has_drrs);
12431                 if (current_config->has_drrs)
12432                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12433         } else
12434                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12435
12436         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12437         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12438         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12439         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12440         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12441         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12442
12443         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12444         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12445         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12446         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12447         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12448         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12449
12450         PIPE_CONF_CHECK_I(pixel_multiplier);
12451         PIPE_CONF_CHECK_I(has_hdmi_sink);
12452         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12453             IS_VALLEYVIEW(dev))
12454                 PIPE_CONF_CHECK_I(limited_color_range);
12455         PIPE_CONF_CHECK_I(has_infoframe);
12456
12457         PIPE_CONF_CHECK_I(has_audio);
12458
12459         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12460                               DRM_MODE_FLAG_INTERLACE);
12461
12462         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12463                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12464                                       DRM_MODE_FLAG_PHSYNC);
12465                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12466                                       DRM_MODE_FLAG_NHSYNC);
12467                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12468                                       DRM_MODE_FLAG_PVSYNC);
12469                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12470                                       DRM_MODE_FLAG_NVSYNC);
12471         }
12472
12473         PIPE_CONF_CHECK_I(pipe_src_w);
12474         PIPE_CONF_CHECK_I(pipe_src_h);
12475
12476         PIPE_CONF_CHECK_I(gmch_pfit.control);
12477         /* pfit ratios are autocomputed by the hw on gen4+ */
12478         if (INTEL_INFO(dev)->gen < 4)
12479                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12480         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12481
12482         PIPE_CONF_CHECK_I(pch_pfit.enabled);
12483         if (current_config->pch_pfit.enabled) {
12484                 PIPE_CONF_CHECK_I(pch_pfit.pos);
12485                 PIPE_CONF_CHECK_I(pch_pfit.size);
12486         }
12487
12488         PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12489
12490         /* BDW+ don't expose a synchronous way to read the state */
12491         if (IS_HASWELL(dev))
12492                 PIPE_CONF_CHECK_I(ips_enabled);
12493
12494         PIPE_CONF_CHECK_I(double_wide);
12495
12496         PIPE_CONF_CHECK_X(ddi_pll_sel);
12497
12498         PIPE_CONF_CHECK_I(shared_dpll);
12499         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12500         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12501         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12502         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12503         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12504         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12505         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12506         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12507
12508         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12509                 PIPE_CONF_CHECK_I(pipe_bpp);
12510
12511         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12512         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12513
12514 #undef PIPE_CONF_CHECK_X
12515 #undef PIPE_CONF_CHECK_I
12516 #undef PIPE_CONF_CHECK_I_ALT
12517 #undef PIPE_CONF_CHECK_FLAGS
12518 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12519 #undef PIPE_CONF_QUIRK
12520 #undef INTEL_ERR_OR_DBG_KMS
12521
12522         return ret;
12523 }
12524
12525 static void check_wm_state(struct drm_device *dev)
12526 {
12527         struct drm_i915_private *dev_priv = dev->dev_private;
12528         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12529         struct intel_crtc *intel_crtc;
12530         int plane;
12531
12532         if (INTEL_INFO(dev)->gen < 9)
12533                 return;
12534
12535         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12536         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12537
12538         for_each_intel_crtc(dev, intel_crtc) {
12539                 struct skl_ddb_entry *hw_entry, *sw_entry;
12540                 const enum pipe pipe = intel_crtc->pipe;
12541
12542                 if (!intel_crtc->active)
12543                         continue;
12544
12545                 /* planes */
12546                 for_each_plane(dev_priv, pipe, plane) {
12547                         hw_entry = &hw_ddb.plane[pipe][plane];
12548                         sw_entry = &sw_ddb->plane[pipe][plane];
12549
12550                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12551                                 continue;
12552
12553                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12554                                   "(expected (%u,%u), found (%u,%u))\n",
12555                                   pipe_name(pipe), plane + 1,
12556                                   sw_entry->start, sw_entry->end,
12557                                   hw_entry->start, hw_entry->end);
12558                 }
12559
12560                 /* cursor */
12561                 hw_entry = &hw_ddb.cursor[pipe];
12562                 sw_entry = &sw_ddb->cursor[pipe];
12563
12564                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12565                         continue;
12566
12567                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12568                           "(expected (%u,%u), found (%u,%u))\n",
12569                           pipe_name(pipe),
12570                           sw_entry->start, sw_entry->end,
12571                           hw_entry->start, hw_entry->end);
12572         }
12573 }
12574
12575 static void
12576 check_connector_state(struct drm_device *dev,
12577                       struct drm_atomic_state *old_state)
12578 {
12579         struct drm_connector_state *old_conn_state;
12580         struct drm_connector *connector;
12581         int i;
12582
12583         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12584                 struct drm_encoder *encoder = connector->encoder;
12585                 struct drm_connector_state *state = connector->state;
12586
12587                 /* This also checks the encoder/connector hw state with the
12588                  * ->get_hw_state callbacks. */
12589                 intel_connector_check_state(to_intel_connector(connector));
12590
12591                 I915_STATE_WARN(state->best_encoder != encoder,
12592                      "connector's atomic encoder doesn't match legacy encoder\n");
12593         }
12594 }
12595
12596 static void
12597 check_encoder_state(struct drm_device *dev)
12598 {
12599         struct intel_encoder *encoder;
12600         struct intel_connector *connector;
12601
12602         for_each_intel_encoder(dev, encoder) {
12603                 bool enabled = false;
12604                 enum pipe pipe;
12605
12606                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12607                               encoder->base.base.id,
12608                               encoder->base.name);
12609
12610                 for_each_intel_connector(dev, connector) {
12611                         if (connector->base.state->best_encoder != &encoder->base)
12612                                 continue;
12613                         enabled = true;
12614
12615                         I915_STATE_WARN(connector->base.state->crtc !=
12616                                         encoder->base.crtc,
12617                              "connector's crtc doesn't match encoder crtc\n");
12618                 }
12619
12620                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12621                      "encoder's enabled state mismatch "
12622                      "(expected %i, found %i)\n",
12623                      !!encoder->base.crtc, enabled);
12624
12625                 if (!encoder->base.crtc) {
12626                         bool active;
12627
12628                         active = encoder->get_hw_state(encoder, &pipe);
12629                         I915_STATE_WARN(active,
12630                              "encoder detached but still enabled on pipe %c.\n",
12631                              pipe_name(pipe));
12632                 }
12633         }
12634 }
12635
12636 static void
12637 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12638 {
12639         struct drm_i915_private *dev_priv = dev->dev_private;
12640         struct intel_encoder *encoder;
12641         struct drm_crtc_state *old_crtc_state;
12642         struct drm_crtc *crtc;
12643         int i;
12644
12645         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12646                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12647                 struct intel_crtc_state *pipe_config, *sw_config;
12648                 bool active;
12649
12650                 if (!needs_modeset(crtc->state))
12651                         continue;
12652
12653                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12654                 pipe_config = to_intel_crtc_state(old_crtc_state);
12655                 memset(pipe_config, 0, sizeof(*pipe_config));
12656                 pipe_config->base.crtc = crtc;
12657                 pipe_config->base.state = old_state;
12658
12659                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12660                               crtc->base.id);
12661
12662                 active = dev_priv->display.get_pipe_config(intel_crtc,
12663                                                            pipe_config);
12664
12665                 /* hw state is inconsistent with the pipe quirk */
12666                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12667                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12668                         active = crtc->state->active;
12669
12670                 I915_STATE_WARN(crtc->state->active != active,
12671                      "crtc active state doesn't match with hw state "
12672                      "(expected %i, found %i)\n", crtc->state->active, active);
12673
12674                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12675                      "transitional active state does not match atomic hw state "
12676                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12677
12678                 for_each_encoder_on_crtc(dev, crtc, encoder) {
12679                         enum pipe pipe;
12680
12681                         active = encoder->get_hw_state(encoder, &pipe);
12682                         I915_STATE_WARN(active != crtc->state->active,
12683                                 "[ENCODER:%i] active %i with crtc active %i\n",
12684                                 encoder->base.base.id, active, crtc->state->active);
12685
12686                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12687                                         "Encoder connected to wrong pipe %c\n",
12688                                         pipe_name(pipe));
12689
12690                         if (active)
12691                                 encoder->get_config(encoder, pipe_config);
12692                 }
12693
12694                 if (!crtc->state->active)
12695                         continue;
12696
12697                 sw_config = to_intel_crtc_state(crtc->state);
12698                 if (!intel_pipe_config_compare(dev, sw_config,
12699                                                pipe_config, false)) {
12700                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12701                         intel_dump_pipe_config(intel_crtc, pipe_config,
12702                                                "[hw state]");
12703                         intel_dump_pipe_config(intel_crtc, sw_config,
12704                                                "[sw state]");
12705                 }
12706         }
12707 }
12708
12709 static void
12710 check_shared_dpll_state(struct drm_device *dev)
12711 {
12712         struct drm_i915_private *dev_priv = dev->dev_private;
12713         struct intel_crtc *crtc;
12714         struct intel_dpll_hw_state dpll_hw_state;
12715         int i;
12716
12717         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12718                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12719                 int enabled_crtcs = 0, active_crtcs = 0;
12720                 bool active;
12721
12722                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12723
12724                 DRM_DEBUG_KMS("%s\n", pll->name);
12725
12726                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12727
12728                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12729                      "more active pll users than references: %i vs %i\n",
12730                      pll->active, hweight32(pll->config.crtc_mask));
12731                 I915_STATE_WARN(pll->active && !pll->on,
12732                      "pll in active use but not on in sw tracking\n");
12733                 I915_STATE_WARN(pll->on && !pll->active,
12734                      "pll in on but not on in use in sw tracking\n");
12735                 I915_STATE_WARN(pll->on != active,
12736                      "pll on state mismatch (expected %i, found %i)\n",
12737                      pll->on, active);
12738
12739                 for_each_intel_crtc(dev, crtc) {
12740                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12741                                 enabled_crtcs++;
12742                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12743                                 active_crtcs++;
12744                 }
12745                 I915_STATE_WARN(pll->active != active_crtcs,
12746                      "pll active crtcs mismatch (expected %i, found %i)\n",
12747                      pll->active, active_crtcs);
12748                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12749                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12750                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12751
12752                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12753                                        sizeof(dpll_hw_state)),
12754                      "pll hw state mismatch\n");
12755         }
12756 }
12757
12758 static void
12759 intel_modeset_check_state(struct drm_device *dev,
12760                           struct drm_atomic_state *old_state)
12761 {
12762         check_wm_state(dev);
12763         check_connector_state(dev, old_state);
12764         check_encoder_state(dev);
12765         check_crtc_state(dev, old_state);
12766         check_shared_dpll_state(dev);
12767 }
12768
12769 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12770                                      int dotclock)
12771 {
12772         /*
12773          * FDI already provided one idea for the dotclock.
12774          * Yell if the encoder disagrees.
12775          */
12776         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12777              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12778              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12779 }
12780
12781 static void update_scanline_offset(struct intel_crtc *crtc)
12782 {
12783         struct drm_device *dev = crtc->base.dev;
12784
12785         /*
12786          * The scanline counter increments at the leading edge of hsync.
12787          *
12788          * On most platforms it starts counting from vtotal-1 on the
12789          * first active line. That means the scanline counter value is
12790          * always one less than what we would expect. Ie. just after
12791          * start of vblank, which also occurs at start of hsync (on the
12792          * last active line), the scanline counter will read vblank_start-1.
12793          *
12794          * On gen2 the scanline counter starts counting from 1 instead
12795          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12796          * to keep the value positive), instead of adding one.
12797          *
12798          * On HSW+ the behaviour of the scanline counter depends on the output
12799          * type. For DP ports it behaves like most other platforms, but on HDMI
12800          * there's an extra 1 line difference. So we need to add two instead of
12801          * one to the value.
12802          */
12803         if (IS_GEN2(dev)) {
12804                 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12805                 int vtotal;
12806
12807                 vtotal = mode->crtc_vtotal;
12808                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12809                         vtotal /= 2;
12810
12811                 crtc->scanline_offset = vtotal - 1;
12812         } else if (HAS_DDI(dev) &&
12813                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12814                 crtc->scanline_offset = 2;
12815         } else
12816                 crtc->scanline_offset = 1;
12817 }
12818
12819 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12820 {
12821         struct drm_device *dev = state->dev;
12822         struct drm_i915_private *dev_priv = to_i915(dev);
12823         struct intel_shared_dpll_config *shared_dpll = NULL;
12824         struct intel_crtc *intel_crtc;
12825         struct intel_crtc_state *intel_crtc_state;
12826         struct drm_crtc *crtc;
12827         struct drm_crtc_state *crtc_state;
12828         int i;
12829
12830         if (!dev_priv->display.crtc_compute_clock)
12831                 return;
12832
12833         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12834                 int dpll;
12835
12836                 intel_crtc = to_intel_crtc(crtc);
12837                 intel_crtc_state = to_intel_crtc_state(crtc_state);
12838                 dpll = intel_crtc_state->shared_dpll;
12839
12840                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12841                         continue;
12842
12843                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12844
12845                 if (!shared_dpll)
12846                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
12847
12848                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12849         }
12850 }
12851
12852 /*
12853  * This implements the workaround described in the "notes" section of the mode
12854  * set sequence documentation. When going from no pipes or single pipe to
12855  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12856  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12857  */
12858 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12859 {
12860         struct drm_crtc_state *crtc_state;
12861         struct intel_crtc *intel_crtc;
12862         struct drm_crtc *crtc;
12863         struct intel_crtc_state *first_crtc_state = NULL;
12864         struct intel_crtc_state *other_crtc_state = NULL;
12865         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12866         int i;
12867
12868         /* look at all crtc's that are going to be enabled in during modeset */
12869         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12870                 intel_crtc = to_intel_crtc(crtc);
12871
12872                 if (!crtc_state->active || !needs_modeset(crtc_state))
12873                         continue;
12874
12875                 if (first_crtc_state) {
12876                         other_crtc_state = to_intel_crtc_state(crtc_state);
12877                         break;
12878                 } else {
12879                         first_crtc_state = to_intel_crtc_state(crtc_state);
12880                         first_pipe = intel_crtc->pipe;
12881                 }
12882         }
12883
12884         /* No workaround needed? */
12885         if (!first_crtc_state)
12886                 return 0;
12887
12888         /* w/a possibly needed, check how many crtc's are already enabled. */
12889         for_each_intel_crtc(state->dev, intel_crtc) {
12890                 struct intel_crtc_state *pipe_config;
12891
12892                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12893                 if (IS_ERR(pipe_config))
12894                         return PTR_ERR(pipe_config);
12895
12896                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12897
12898                 if (!pipe_config->base.active ||
12899                     needs_modeset(&pipe_config->base))
12900                         continue;
12901
12902                 /* 2 or more enabled crtcs means no need for w/a */
12903                 if (enabled_pipe != INVALID_PIPE)
12904                         return 0;
12905
12906                 enabled_pipe = intel_crtc->pipe;
12907         }
12908
12909         if (enabled_pipe != INVALID_PIPE)
12910                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12911         else if (other_crtc_state)
12912                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12913
12914         return 0;
12915 }
12916
12917 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12918 {
12919         struct drm_crtc *crtc;
12920         struct drm_crtc_state *crtc_state;
12921         int ret = 0;
12922
12923         /* add all active pipes to the state */
12924         for_each_crtc(state->dev, crtc) {
12925                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12926                 if (IS_ERR(crtc_state))
12927                         return PTR_ERR(crtc_state);
12928
12929                 if (!crtc_state->active || needs_modeset(crtc_state))
12930                         continue;
12931
12932                 crtc_state->mode_changed = true;
12933
12934                 ret = drm_atomic_add_affected_connectors(state, crtc);
12935                 if (ret)
12936                         break;
12937
12938                 ret = drm_atomic_add_affected_planes(state, crtc);
12939                 if (ret)
12940                         break;
12941         }
12942
12943         return ret;
12944 }
12945
12946
12947 static int intel_modeset_checks(struct drm_atomic_state *state)
12948 {
12949         struct drm_device *dev = state->dev;
12950         struct drm_i915_private *dev_priv = dev->dev_private;
12951         int ret;
12952
12953         if (!check_digital_port_conflicts(state)) {
12954                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12955                 return -EINVAL;
12956         }
12957
12958         /*
12959          * See if the config requires any additional preparation, e.g.
12960          * to adjust global state with pipes off.  We need to do this
12961          * here so we can get the modeset_pipe updated config for the new
12962          * mode set on this crtc.  For other crtcs we need to use the
12963          * adjusted_mode bits in the crtc directly.
12964          */
12965         if (dev_priv->display.modeset_calc_cdclk) {
12966                 unsigned int cdclk;
12967
12968                 ret = dev_priv->display.modeset_calc_cdclk(state);
12969
12970                 cdclk = to_intel_atomic_state(state)->cdclk;
12971                 if (!ret && cdclk != dev_priv->cdclk_freq)
12972                         ret = intel_modeset_all_pipes(state);
12973
12974                 if (ret < 0)
12975                         return ret;
12976         } else
12977                 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
12978
12979         intel_modeset_clear_plls(state);
12980
12981         if (IS_HASWELL(dev))
12982                 return haswell_mode_set_planes_workaround(state);
12983
12984         return 0;
12985 }
12986
12987 /**
12988  * intel_atomic_check - validate state object
12989  * @dev: drm device
12990  * @state: state to validate
12991  */
12992 static int intel_atomic_check(struct drm_device *dev,
12993                               struct drm_atomic_state *state)
12994 {
12995         struct drm_crtc *crtc;
12996         struct drm_crtc_state *crtc_state;
12997         int ret, i;
12998         bool any_ms = false;
12999
13000         ret = drm_atomic_helper_check_modeset(dev, state);
13001         if (ret)
13002                 return ret;
13003
13004         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13005                 struct intel_crtc_state *pipe_config =
13006                         to_intel_crtc_state(crtc_state);
13007
13008                 /* Catch I915_MODE_FLAG_INHERITED */
13009                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13010                         crtc_state->mode_changed = true;
13011
13012                 if (!crtc_state->enable) {
13013                         if (needs_modeset(crtc_state))
13014                                 any_ms = true;
13015                         continue;
13016                 }
13017
13018                 if (!needs_modeset(crtc_state))
13019                         continue;
13020
13021                 /* FIXME: For only active_changed we shouldn't need to do any
13022                  * state recomputation at all. */
13023
13024                 ret = drm_atomic_add_affected_connectors(state, crtc);
13025                 if (ret)
13026                         return ret;
13027
13028                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13029                 if (ret)
13030                         return ret;
13031
13032                 if (i915.fastboot &&
13033                     intel_pipe_config_compare(state->dev,
13034                                         to_intel_crtc_state(crtc->state),
13035                                         pipe_config, true)) {
13036                         crtc_state->mode_changed = false;
13037                 }
13038
13039                 if (needs_modeset(crtc_state)) {
13040                         any_ms = true;
13041
13042                         ret = drm_atomic_add_affected_planes(state, crtc);
13043                         if (ret)
13044                                 return ret;
13045                 }
13046
13047                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13048                                        needs_modeset(crtc_state) ?
13049                                        "[modeset]" : "[fastset]");
13050         }
13051
13052         if (any_ms) {
13053                 ret = intel_modeset_checks(state);
13054
13055                 if (ret)
13056                         return ret;
13057         } else
13058                 to_intel_atomic_state(state)->cdclk =
13059                         to_i915(state->dev)->cdclk_freq;
13060
13061         return drm_atomic_helper_check_planes(state->dev, state);
13062 }
13063
13064 /**
13065  * intel_atomic_commit - commit validated state object
13066  * @dev: DRM device
13067  * @state: the top-level driver state object
13068  * @async: asynchronous commit
13069  *
13070  * This function commits a top-level state object that has been validated
13071  * with drm_atomic_helper_check().
13072  *
13073  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13074  * we can only handle plane-related operations and do not yet support
13075  * asynchronous commit.
13076  *
13077  * RETURNS
13078  * Zero for success or -errno.
13079  */
13080 static int intel_atomic_commit(struct drm_device *dev,
13081                                struct drm_atomic_state *state,
13082                                bool async)
13083 {
13084         struct drm_i915_private *dev_priv = dev->dev_private;
13085         struct drm_crtc *crtc;
13086         struct drm_crtc_state *crtc_state;
13087         int ret = 0;
13088         int i;
13089         bool any_ms = false;
13090
13091         if (async) {
13092                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13093                 return -EINVAL;
13094         }
13095
13096         ret = drm_atomic_helper_prepare_planes(dev, state);
13097         if (ret)
13098                 return ret;
13099
13100         drm_atomic_helper_swap_state(dev, state);
13101
13102         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13103                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13104
13105                 if (!needs_modeset(crtc->state))
13106                         continue;
13107
13108                 any_ms = true;
13109                 intel_pre_plane_update(intel_crtc);
13110
13111                 if (crtc_state->active) {
13112                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13113                         dev_priv->display.crtc_disable(crtc);
13114                         intel_crtc->active = false;
13115                         intel_disable_shared_dpll(intel_crtc);
13116                 }
13117         }
13118
13119         /* Only after disabling all output pipelines that will be changed can we
13120          * update the the output configuration. */
13121         intel_modeset_update_crtc_state(state);
13122
13123         if (any_ms) {
13124                 intel_shared_dpll_commit(state);
13125
13126                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13127                 modeset_update_crtc_power_domains(state);
13128         }
13129
13130         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13131         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13132                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13133                 bool modeset = needs_modeset(crtc->state);
13134
13135                 if (modeset && crtc->state->active) {
13136                         update_scanline_offset(to_intel_crtc(crtc));
13137                         dev_priv->display.crtc_enable(crtc);
13138                 }
13139
13140                 if (!modeset)
13141                         intel_pre_plane_update(intel_crtc);
13142
13143                 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13144                 intel_post_plane_update(intel_crtc);
13145         }
13146
13147         /* FIXME: add subpixel order */
13148
13149         drm_atomic_helper_wait_for_vblanks(dev, state);
13150         drm_atomic_helper_cleanup_planes(dev, state);
13151
13152         if (any_ms)
13153                 intel_modeset_check_state(dev, state);
13154
13155         drm_atomic_state_free(state);
13156
13157         return 0;
13158 }
13159
13160 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13161 {
13162         struct drm_device *dev = crtc->dev;
13163         struct drm_atomic_state *state;
13164         struct drm_crtc_state *crtc_state;
13165         int ret;
13166
13167         state = drm_atomic_state_alloc(dev);
13168         if (!state) {
13169                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13170                               crtc->base.id);
13171                 return;
13172         }
13173
13174         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13175
13176 retry:
13177         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13178         ret = PTR_ERR_OR_ZERO(crtc_state);
13179         if (!ret) {
13180                 if (!crtc_state->active)
13181                         goto out;
13182
13183                 crtc_state->mode_changed = true;
13184                 ret = drm_atomic_commit(state);
13185         }
13186
13187         if (ret == -EDEADLK) {
13188                 drm_atomic_state_clear(state);
13189                 drm_modeset_backoff(state->acquire_ctx);
13190                 goto retry;
13191         }
13192
13193         if (ret)
13194 out:
13195                 drm_atomic_state_free(state);
13196 }
13197
13198 #undef for_each_intel_crtc_masked
13199
13200 static const struct drm_crtc_funcs intel_crtc_funcs = {
13201         .gamma_set = intel_crtc_gamma_set,
13202         .set_config = drm_atomic_helper_set_config,
13203         .destroy = intel_crtc_destroy,
13204         .page_flip = intel_crtc_page_flip,
13205         .atomic_duplicate_state = intel_crtc_duplicate_state,
13206         .atomic_destroy_state = intel_crtc_destroy_state,
13207 };
13208
13209 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13210                                       struct intel_shared_dpll *pll,
13211                                       struct intel_dpll_hw_state *hw_state)
13212 {
13213         uint32_t val;
13214
13215         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13216                 return false;
13217
13218         val = I915_READ(PCH_DPLL(pll->id));
13219         hw_state->dpll = val;
13220         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13221         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13222
13223         return val & DPLL_VCO_ENABLE;
13224 }
13225
13226 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13227                                   struct intel_shared_dpll *pll)
13228 {
13229         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13230         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13231 }
13232
13233 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13234                                 struct intel_shared_dpll *pll)
13235 {
13236         /* PCH refclock must be enabled first */
13237         ibx_assert_pch_refclk_enabled(dev_priv);
13238
13239         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13240
13241         /* Wait for the clocks to stabilize. */
13242         POSTING_READ(PCH_DPLL(pll->id));
13243         udelay(150);
13244
13245         /* The pixel multiplier can only be updated once the
13246          * DPLL is enabled and the clocks are stable.
13247          *
13248          * So write it again.
13249          */
13250         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13251         POSTING_READ(PCH_DPLL(pll->id));
13252         udelay(200);
13253 }
13254
13255 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13256                                  struct intel_shared_dpll *pll)
13257 {
13258         struct drm_device *dev = dev_priv->dev;
13259         struct intel_crtc *crtc;
13260
13261         /* Make sure no transcoder isn't still depending on us. */
13262         for_each_intel_crtc(dev, crtc) {
13263                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13264                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13265         }
13266
13267         I915_WRITE(PCH_DPLL(pll->id), 0);
13268         POSTING_READ(PCH_DPLL(pll->id));
13269         udelay(200);
13270 }
13271
13272 static char *ibx_pch_dpll_names[] = {
13273         "PCH DPLL A",
13274         "PCH DPLL B",
13275 };
13276
13277 static void ibx_pch_dpll_init(struct drm_device *dev)
13278 {
13279         struct drm_i915_private *dev_priv = dev->dev_private;
13280         int i;
13281
13282         dev_priv->num_shared_dpll = 2;
13283
13284         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13285                 dev_priv->shared_dplls[i].id = i;
13286                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13287                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13288                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13289                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13290                 dev_priv->shared_dplls[i].get_hw_state =
13291                         ibx_pch_dpll_get_hw_state;
13292         }
13293 }
13294
13295 static void intel_shared_dpll_init(struct drm_device *dev)
13296 {
13297         struct drm_i915_private *dev_priv = dev->dev_private;
13298
13299         intel_update_cdclk(dev);
13300
13301         if (HAS_DDI(dev))
13302                 intel_ddi_pll_init(dev);
13303         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13304                 ibx_pch_dpll_init(dev);
13305         else
13306                 dev_priv->num_shared_dpll = 0;
13307
13308         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13309 }
13310
13311 /**
13312  * intel_prepare_plane_fb - Prepare fb for usage on plane
13313  * @plane: drm plane to prepare for
13314  * @fb: framebuffer to prepare for presentation
13315  *
13316  * Prepares a framebuffer for usage on a display plane.  Generally this
13317  * involves pinning the underlying object and updating the frontbuffer tracking
13318  * bits.  Some older platforms need special physical address handling for
13319  * cursor planes.
13320  *
13321  * Returns 0 on success, negative error code on failure.
13322  */
13323 int
13324 intel_prepare_plane_fb(struct drm_plane *plane,
13325                        struct drm_framebuffer *fb,
13326                        const struct drm_plane_state *new_state)
13327 {
13328         struct drm_device *dev = plane->dev;
13329         struct intel_plane *intel_plane = to_intel_plane(plane);
13330         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13331         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13332         int ret = 0;
13333
13334         if (!obj)
13335                 return 0;
13336
13337         mutex_lock(&dev->struct_mutex);
13338
13339         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13340             INTEL_INFO(dev)->cursor_needs_physical) {
13341                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13342                 ret = i915_gem_object_attach_phys(obj, align);
13343                 if (ret)
13344                         DRM_DEBUG_KMS("failed to attach phys object\n");
13345         } else {
13346                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13347         }
13348
13349         if (ret == 0)
13350                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13351
13352         mutex_unlock(&dev->struct_mutex);
13353
13354         return ret;
13355 }
13356
13357 /**
13358  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13359  * @plane: drm plane to clean up for
13360  * @fb: old framebuffer that was on plane
13361  *
13362  * Cleans up a framebuffer that has just been removed from a plane.
13363  */
13364 void
13365 intel_cleanup_plane_fb(struct drm_plane *plane,
13366                        struct drm_framebuffer *fb,
13367                        const struct drm_plane_state *old_state)
13368 {
13369         struct drm_device *dev = plane->dev;
13370         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13371
13372         if (WARN_ON(!obj))
13373                 return;
13374
13375         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13376             !INTEL_INFO(dev)->cursor_needs_physical) {
13377                 mutex_lock(&dev->struct_mutex);
13378                 intel_unpin_fb_obj(fb, old_state);
13379                 mutex_unlock(&dev->struct_mutex);
13380         }
13381 }
13382
13383 int
13384 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13385 {
13386         int max_scale;
13387         struct drm_device *dev;
13388         struct drm_i915_private *dev_priv;
13389         int crtc_clock, cdclk;
13390
13391         if (!intel_crtc || !crtc_state)
13392                 return DRM_PLANE_HELPER_NO_SCALING;
13393
13394         dev = intel_crtc->base.dev;
13395         dev_priv = dev->dev_private;
13396         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13397         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13398
13399         if (!crtc_clock || !cdclk)
13400                 return DRM_PLANE_HELPER_NO_SCALING;
13401
13402         /*
13403          * skl max scale is lower of:
13404          *    close to 3 but not 3, -1 is for that purpose
13405          *            or
13406          *    cdclk/crtc_clock
13407          */
13408         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13409
13410         return max_scale;
13411 }
13412
13413 static int
13414 intel_check_primary_plane(struct drm_plane *plane,
13415                           struct intel_crtc_state *crtc_state,
13416                           struct intel_plane_state *state)
13417 {
13418         struct drm_crtc *crtc = state->base.crtc;
13419         struct drm_framebuffer *fb = state->base.fb;
13420         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13421         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13422         bool can_position = false;
13423
13424         /* use scaler when colorkey is not required */
13425         if (INTEL_INFO(plane->dev)->gen >= 9 &&
13426             state->ckey.flags == I915_SET_COLORKEY_NONE) {
13427                 min_scale = 1;
13428                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13429                 can_position = true;
13430         }
13431
13432         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13433                                              &state->dst, &state->clip,
13434                                              min_scale, max_scale,
13435                                              can_position, true,
13436                                              &state->visible);
13437 }
13438
13439 static void
13440 intel_commit_primary_plane(struct drm_plane *plane,
13441                            struct intel_plane_state *state)
13442 {
13443         struct drm_crtc *crtc = state->base.crtc;
13444         struct drm_framebuffer *fb = state->base.fb;
13445         struct drm_device *dev = plane->dev;
13446         struct drm_i915_private *dev_priv = dev->dev_private;
13447         struct intel_crtc *intel_crtc;
13448         struct drm_rect *src = &state->src;
13449
13450         crtc = crtc ? crtc : plane->crtc;
13451         intel_crtc = to_intel_crtc(crtc);
13452
13453         plane->fb = fb;
13454         crtc->x = src->x1 >> 16;
13455         crtc->y = src->y1 >> 16;
13456
13457         if (!crtc->state->active)
13458                 return;
13459
13460         if (state->visible)
13461                 /* FIXME: kill this fastboot hack */
13462                 intel_update_pipe_size(intel_crtc);
13463
13464         dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
13465 }
13466
13467 static void
13468 intel_disable_primary_plane(struct drm_plane *plane,
13469                             struct drm_crtc *crtc)
13470 {
13471         struct drm_device *dev = plane->dev;
13472         struct drm_i915_private *dev_priv = dev->dev_private;
13473
13474         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13475 }
13476
13477 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13478                                     struct drm_crtc_state *old_crtc_state)
13479 {
13480         struct drm_device *dev = crtc->dev;
13481         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13482
13483         if (intel_crtc->atomic.update_wm_pre)
13484                 intel_update_watermarks(crtc);
13485
13486         /* Perform vblank evasion around commit operation */
13487         if (crtc->state->active)
13488                 intel_pipe_update_start(intel_crtc, &intel_crtc->start_vbl_count);
13489
13490         if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13491                 skl_detach_scalers(intel_crtc);
13492 }
13493
13494 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13495                                      struct drm_crtc_state *old_crtc_state)
13496 {
13497         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13498
13499         if (crtc->state->active)
13500                 intel_pipe_update_end(intel_crtc, intel_crtc->start_vbl_count);
13501 }
13502
13503 /**
13504  * intel_plane_destroy - destroy a plane
13505  * @plane: plane to destroy
13506  *
13507  * Common destruction function for all types of planes (primary, cursor,
13508  * sprite).
13509  */
13510 void intel_plane_destroy(struct drm_plane *plane)
13511 {
13512         struct intel_plane *intel_plane = to_intel_plane(plane);
13513         drm_plane_cleanup(plane);
13514         kfree(intel_plane);
13515 }
13516
13517 const struct drm_plane_funcs intel_plane_funcs = {
13518         .update_plane = drm_atomic_helper_update_plane,
13519         .disable_plane = drm_atomic_helper_disable_plane,
13520         .destroy = intel_plane_destroy,
13521         .set_property = drm_atomic_helper_plane_set_property,
13522         .atomic_get_property = intel_plane_atomic_get_property,
13523         .atomic_set_property = intel_plane_atomic_set_property,
13524         .atomic_duplicate_state = intel_plane_duplicate_state,
13525         .atomic_destroy_state = intel_plane_destroy_state,
13526
13527 };
13528
13529 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13530                                                     int pipe)
13531 {
13532         struct intel_plane *primary;
13533         struct intel_plane_state *state;
13534         const uint32_t *intel_primary_formats;
13535         unsigned int num_formats;
13536
13537         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13538         if (primary == NULL)
13539                 return NULL;
13540
13541         state = intel_create_plane_state(&primary->base);
13542         if (!state) {
13543                 kfree(primary);
13544                 return NULL;
13545         }
13546         primary->base.state = &state->base;
13547
13548         primary->can_scale = false;
13549         primary->max_downscale = 1;
13550         if (INTEL_INFO(dev)->gen >= 9) {
13551                 primary->can_scale = true;
13552                 state->scaler_id = -1;
13553         }
13554         primary->pipe = pipe;
13555         primary->plane = pipe;
13556         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13557         primary->check_plane = intel_check_primary_plane;
13558         primary->commit_plane = intel_commit_primary_plane;
13559         primary->disable_plane = intel_disable_primary_plane;
13560         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13561                 primary->plane = !pipe;
13562
13563         if (INTEL_INFO(dev)->gen >= 9) {
13564                 intel_primary_formats = skl_primary_formats;
13565                 num_formats = ARRAY_SIZE(skl_primary_formats);
13566         } else if (INTEL_INFO(dev)->gen >= 4) {
13567                 intel_primary_formats = i965_primary_formats;
13568                 num_formats = ARRAY_SIZE(i965_primary_formats);
13569         } else {
13570                 intel_primary_formats = i8xx_primary_formats;
13571                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13572         }
13573
13574         drm_universal_plane_init(dev, &primary->base, 0,
13575                                  &intel_plane_funcs,
13576                                  intel_primary_formats, num_formats,
13577                                  DRM_PLANE_TYPE_PRIMARY);
13578
13579         if (INTEL_INFO(dev)->gen >= 4)
13580                 intel_create_rotation_property(dev, primary);
13581
13582         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13583
13584         return &primary->base;
13585 }
13586
13587 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13588 {
13589         if (!dev->mode_config.rotation_property) {
13590                 unsigned long flags = BIT(DRM_ROTATE_0) |
13591                         BIT(DRM_ROTATE_180);
13592
13593                 if (INTEL_INFO(dev)->gen >= 9)
13594                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13595
13596                 dev->mode_config.rotation_property =
13597                         drm_mode_create_rotation_property(dev, flags);
13598         }
13599         if (dev->mode_config.rotation_property)
13600                 drm_object_attach_property(&plane->base.base,
13601                                 dev->mode_config.rotation_property,
13602                                 plane->base.state->rotation);
13603 }
13604
13605 static int
13606 intel_check_cursor_plane(struct drm_plane *plane,
13607                          struct intel_crtc_state *crtc_state,
13608                          struct intel_plane_state *state)
13609 {
13610         struct drm_crtc *crtc = crtc_state->base.crtc;
13611         struct drm_framebuffer *fb = state->base.fb;
13612         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13613         unsigned stride;
13614         int ret;
13615
13616         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13617                                             &state->dst, &state->clip,
13618                                             DRM_PLANE_HELPER_NO_SCALING,
13619                                             DRM_PLANE_HELPER_NO_SCALING,
13620                                             true, true, &state->visible);
13621         if (ret)
13622                 return ret;
13623
13624         /* if we want to turn off the cursor ignore width and height */
13625         if (!obj)
13626                 return 0;
13627
13628         /* Check for which cursor types we support */
13629         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13630                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13631                           state->base.crtc_w, state->base.crtc_h);
13632                 return -EINVAL;
13633         }
13634
13635         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13636         if (obj->base.size < stride * state->base.crtc_h) {
13637                 DRM_DEBUG_KMS("buffer is too small\n");
13638                 return -ENOMEM;
13639         }
13640
13641         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13642                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13643                 return -EINVAL;
13644         }
13645
13646         return 0;
13647 }
13648
13649 static void
13650 intel_disable_cursor_plane(struct drm_plane *plane,
13651                            struct drm_crtc *crtc)
13652 {
13653         intel_crtc_update_cursor(crtc, false);
13654 }
13655
13656 static void
13657 intel_commit_cursor_plane(struct drm_plane *plane,
13658                           struct intel_plane_state *state)
13659 {
13660         struct drm_crtc *crtc = state->base.crtc;
13661         struct drm_device *dev = plane->dev;
13662         struct intel_crtc *intel_crtc;
13663         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13664         uint32_t addr;
13665
13666         crtc = crtc ? crtc : plane->crtc;
13667         intel_crtc = to_intel_crtc(crtc);
13668
13669         plane->fb = state->base.fb;
13670         crtc->cursor_x = state->base.crtc_x;
13671         crtc->cursor_y = state->base.crtc_y;
13672
13673         if (intel_crtc->cursor_bo == obj)
13674                 goto update;
13675
13676         if (!obj)
13677                 addr = 0;
13678         else if (!INTEL_INFO(dev)->cursor_needs_physical)
13679                 addr = i915_gem_obj_ggtt_offset(obj);
13680         else
13681                 addr = obj->phys_handle->busaddr;
13682
13683         intel_crtc->cursor_addr = addr;
13684         intel_crtc->cursor_bo = obj;
13685
13686 update:
13687         if (crtc->state->active)
13688                 intel_crtc_update_cursor(crtc, state->visible);
13689 }
13690
13691 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13692                                                    int pipe)
13693 {
13694         struct intel_plane *cursor;
13695         struct intel_plane_state *state;
13696
13697         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13698         if (cursor == NULL)
13699                 return NULL;
13700
13701         state = intel_create_plane_state(&cursor->base);
13702         if (!state) {
13703                 kfree(cursor);
13704                 return NULL;
13705         }
13706         cursor->base.state = &state->base;
13707
13708         cursor->can_scale = false;
13709         cursor->max_downscale = 1;
13710         cursor->pipe = pipe;
13711         cursor->plane = pipe;
13712         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13713         cursor->check_plane = intel_check_cursor_plane;
13714         cursor->commit_plane = intel_commit_cursor_plane;
13715         cursor->disable_plane = intel_disable_cursor_plane;
13716
13717         drm_universal_plane_init(dev, &cursor->base, 0,
13718                                  &intel_plane_funcs,
13719                                  intel_cursor_formats,
13720                                  ARRAY_SIZE(intel_cursor_formats),
13721                                  DRM_PLANE_TYPE_CURSOR);
13722
13723         if (INTEL_INFO(dev)->gen >= 4) {
13724                 if (!dev->mode_config.rotation_property)
13725                         dev->mode_config.rotation_property =
13726                                 drm_mode_create_rotation_property(dev,
13727                                                         BIT(DRM_ROTATE_0) |
13728                                                         BIT(DRM_ROTATE_180));
13729                 if (dev->mode_config.rotation_property)
13730                         drm_object_attach_property(&cursor->base.base,
13731                                 dev->mode_config.rotation_property,
13732                                 state->base.rotation);
13733         }
13734
13735         if (INTEL_INFO(dev)->gen >=9)
13736                 state->scaler_id = -1;
13737
13738         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13739
13740         return &cursor->base;
13741 }
13742
13743 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13744         struct intel_crtc_state *crtc_state)
13745 {
13746         int i;
13747         struct intel_scaler *intel_scaler;
13748         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13749
13750         for (i = 0; i < intel_crtc->num_scalers; i++) {
13751                 intel_scaler = &scaler_state->scalers[i];
13752                 intel_scaler->in_use = 0;
13753                 intel_scaler->mode = PS_SCALER_MODE_DYN;
13754         }
13755
13756         scaler_state->scaler_id = -1;
13757 }
13758
13759 static void intel_crtc_init(struct drm_device *dev, int pipe)
13760 {
13761         struct drm_i915_private *dev_priv = dev->dev_private;
13762         struct intel_crtc *intel_crtc;
13763         struct intel_crtc_state *crtc_state = NULL;
13764         struct drm_plane *primary = NULL;
13765         struct drm_plane *cursor = NULL;
13766         int i, ret;
13767
13768         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13769         if (intel_crtc == NULL)
13770                 return;
13771
13772         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13773         if (!crtc_state)
13774                 goto fail;
13775         intel_crtc->config = crtc_state;
13776         intel_crtc->base.state = &crtc_state->base;
13777         crtc_state->base.crtc = &intel_crtc->base;
13778
13779         /* initialize shared scalers */
13780         if (INTEL_INFO(dev)->gen >= 9) {
13781                 if (pipe == PIPE_C)
13782                         intel_crtc->num_scalers = 1;
13783                 else
13784                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
13785
13786                 skl_init_scalers(dev, intel_crtc, crtc_state);
13787         }
13788
13789         primary = intel_primary_plane_create(dev, pipe);
13790         if (!primary)
13791                 goto fail;
13792
13793         cursor = intel_cursor_plane_create(dev, pipe);
13794         if (!cursor)
13795                 goto fail;
13796
13797         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13798                                         cursor, &intel_crtc_funcs);
13799         if (ret)
13800                 goto fail;
13801
13802         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13803         for (i = 0; i < 256; i++) {
13804                 intel_crtc->lut_r[i] = i;
13805                 intel_crtc->lut_g[i] = i;
13806                 intel_crtc->lut_b[i] = i;
13807         }
13808
13809         /*
13810          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13811          * is hooked to pipe B. Hence we want plane A feeding pipe B.
13812          */
13813         intel_crtc->pipe = pipe;
13814         intel_crtc->plane = pipe;
13815         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13816                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13817                 intel_crtc->plane = !pipe;
13818         }
13819
13820         intel_crtc->cursor_base = ~0;
13821         intel_crtc->cursor_cntl = ~0;
13822         intel_crtc->cursor_size = ~0;
13823
13824         intel_crtc->wm.cxsr_allowed = true;
13825
13826         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13827                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13828         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13829         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13830
13831         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13832
13833         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13834         return;
13835
13836 fail:
13837         if (primary)
13838                 drm_plane_cleanup(primary);
13839         if (cursor)
13840                 drm_plane_cleanup(cursor);
13841         kfree(crtc_state);
13842         kfree(intel_crtc);
13843 }
13844
13845 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13846 {
13847         struct drm_encoder *encoder = connector->base.encoder;
13848         struct drm_device *dev = connector->base.dev;
13849
13850         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13851
13852         if (!encoder || WARN_ON(!encoder->crtc))
13853                 return INVALID_PIPE;
13854
13855         return to_intel_crtc(encoder->crtc)->pipe;
13856 }
13857
13858 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13859                                 struct drm_file *file)
13860 {
13861         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13862         struct drm_crtc *drmmode_crtc;
13863         struct intel_crtc *crtc;
13864
13865         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13866
13867         if (!drmmode_crtc) {
13868                 DRM_ERROR("no such CRTC id\n");
13869                 return -ENOENT;
13870         }
13871
13872         crtc = to_intel_crtc(drmmode_crtc);
13873         pipe_from_crtc_id->pipe = crtc->pipe;
13874
13875         return 0;
13876 }
13877
13878 static int intel_encoder_clones(struct intel_encoder *encoder)
13879 {
13880         struct drm_device *dev = encoder->base.dev;
13881         struct intel_encoder *source_encoder;
13882         int index_mask = 0;
13883         int entry = 0;
13884
13885         for_each_intel_encoder(dev, source_encoder) {
13886                 if (encoders_cloneable(encoder, source_encoder))
13887                         index_mask |= (1 << entry);
13888
13889                 entry++;
13890         }
13891
13892         return index_mask;
13893 }
13894
13895 static bool has_edp_a(struct drm_device *dev)
13896 {
13897         struct drm_i915_private *dev_priv = dev->dev_private;
13898
13899         if (!IS_MOBILE(dev))
13900                 return false;
13901
13902         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13903                 return false;
13904
13905         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13906                 return false;
13907
13908         return true;
13909 }
13910
13911 static bool intel_crt_present(struct drm_device *dev)
13912 {
13913         struct drm_i915_private *dev_priv = dev->dev_private;
13914
13915         if (INTEL_INFO(dev)->gen >= 9)
13916                 return false;
13917
13918         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13919                 return false;
13920
13921         if (IS_CHERRYVIEW(dev))
13922                 return false;
13923
13924         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13925                 return false;
13926
13927         return true;
13928 }
13929
13930 static void intel_setup_outputs(struct drm_device *dev)
13931 {
13932         struct drm_i915_private *dev_priv = dev->dev_private;
13933         struct intel_encoder *encoder;
13934         bool dpd_is_edp = false;
13935
13936         intel_lvds_init(dev);
13937
13938         if (intel_crt_present(dev))
13939                 intel_crt_init(dev);
13940
13941         if (IS_BROXTON(dev)) {
13942                 /*
13943                  * FIXME: Broxton doesn't support port detection via the
13944                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13945                  * detect the ports.
13946                  */
13947                 intel_ddi_init(dev, PORT_A);
13948                 intel_ddi_init(dev, PORT_B);
13949                 intel_ddi_init(dev, PORT_C);
13950         } else if (HAS_DDI(dev)) {
13951                 int found;
13952
13953                 /*
13954                  * Haswell uses DDI functions to detect digital outputs.
13955                  * On SKL pre-D0 the strap isn't connected, so we assume
13956                  * it's there.
13957                  */
13958                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13959                 /* WaIgnoreDDIAStrap: skl */
13960                 if (found || IS_SKYLAKE(dev))
13961                         intel_ddi_init(dev, PORT_A);
13962
13963                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13964                  * register */
13965                 found = I915_READ(SFUSE_STRAP);
13966
13967                 if (found & SFUSE_STRAP_DDIB_DETECTED)
13968                         intel_ddi_init(dev, PORT_B);
13969                 if (found & SFUSE_STRAP_DDIC_DETECTED)
13970                         intel_ddi_init(dev, PORT_C);
13971                 if (found & SFUSE_STRAP_DDID_DETECTED)
13972                         intel_ddi_init(dev, PORT_D);
13973                 /*
13974                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13975                  */
13976                 if (IS_SKYLAKE(dev) &&
13977                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13978                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13979                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13980                         intel_ddi_init(dev, PORT_E);
13981
13982         } else if (HAS_PCH_SPLIT(dev)) {
13983                 int found;
13984                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13985
13986                 if (has_edp_a(dev))
13987                         intel_dp_init(dev, DP_A, PORT_A);
13988
13989                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13990                         /* PCH SDVOB multiplex with HDMIB */
13991                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
13992                         if (!found)
13993                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
13994                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13995                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
13996                 }
13997
13998                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13999                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14000
14001                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14002                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14003
14004                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14005                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14006
14007                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14008                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14009         } else if (IS_VALLEYVIEW(dev)) {
14010                 /*
14011                  * The DP_DETECTED bit is the latched state of the DDC
14012                  * SDA pin at boot. However since eDP doesn't require DDC
14013                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14014                  * eDP ports may have been muxed to an alternate function.
14015                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14016                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14017                  * detect eDP ports.
14018                  */
14019                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14020                     !intel_dp_is_edp(dev, PORT_B))
14021                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14022                                         PORT_B);
14023                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14024                     intel_dp_is_edp(dev, PORT_B))
14025                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14026
14027                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14028                     !intel_dp_is_edp(dev, PORT_C))
14029                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14030                                         PORT_C);
14031                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14032                     intel_dp_is_edp(dev, PORT_C))
14033                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14034
14035                 if (IS_CHERRYVIEW(dev)) {
14036                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14037                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14038                                                 PORT_D);
14039                         /* eDP not supported on port D, so don't check VBT */
14040                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14041                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14042                 }
14043
14044                 intel_dsi_init(dev);
14045         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14046                 bool found = false;
14047
14048                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14049                         DRM_DEBUG_KMS("probing SDVOB\n");
14050                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14051                         if (!found && IS_G4X(dev)) {
14052                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14053                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14054                         }
14055
14056                         if (!found && IS_G4X(dev))
14057                                 intel_dp_init(dev, DP_B, PORT_B);
14058                 }
14059
14060                 /* Before G4X SDVOC doesn't have its own detect register */
14061
14062                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14063                         DRM_DEBUG_KMS("probing SDVOC\n");
14064                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14065                 }
14066
14067                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14068
14069                         if (IS_G4X(dev)) {
14070                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14071                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14072                         }
14073                         if (IS_G4X(dev))
14074                                 intel_dp_init(dev, DP_C, PORT_C);
14075                 }
14076
14077                 if (IS_G4X(dev) &&
14078                     (I915_READ(DP_D) & DP_DETECTED))
14079                         intel_dp_init(dev, DP_D, PORT_D);
14080         } else if (IS_GEN2(dev))
14081                 intel_dvo_init(dev);
14082
14083         if (SUPPORTS_TV(dev))
14084                 intel_tv_init(dev);
14085
14086         intel_psr_init(dev);
14087
14088         for_each_intel_encoder(dev, encoder) {
14089                 encoder->base.possible_crtcs = encoder->crtc_mask;
14090                 encoder->base.possible_clones =
14091                         intel_encoder_clones(encoder);
14092         }
14093
14094         intel_init_pch_refclk(dev);
14095
14096         drm_helper_move_panel_connectors_to_head(dev);
14097 }
14098
14099 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14100 {
14101         struct drm_device *dev = fb->dev;
14102         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14103
14104         drm_framebuffer_cleanup(fb);
14105         mutex_lock(&dev->struct_mutex);
14106         WARN_ON(!intel_fb->obj->framebuffer_references--);
14107         drm_gem_object_unreference(&intel_fb->obj->base);
14108         mutex_unlock(&dev->struct_mutex);
14109         kfree(intel_fb);
14110 }
14111
14112 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14113                                                 struct drm_file *file,
14114                                                 unsigned int *handle)
14115 {
14116         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14117         struct drm_i915_gem_object *obj = intel_fb->obj;
14118
14119         if (obj->userptr.mm) {
14120                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14121                 return -EINVAL;
14122         }
14123
14124         return drm_gem_handle_create(file, &obj->base, handle);
14125 }
14126
14127 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14128                                         struct drm_file *file,
14129                                         unsigned flags, unsigned color,
14130                                         struct drm_clip_rect *clips,
14131                                         unsigned num_clips)
14132 {
14133         struct drm_device *dev = fb->dev;
14134         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14135         struct drm_i915_gem_object *obj = intel_fb->obj;
14136
14137         mutex_lock(&dev->struct_mutex);
14138         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14139         mutex_unlock(&dev->struct_mutex);
14140
14141         return 0;
14142 }
14143
14144 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14145         .destroy = intel_user_framebuffer_destroy,
14146         .create_handle = intel_user_framebuffer_create_handle,
14147         .dirty = intel_user_framebuffer_dirty,
14148 };
14149
14150 static
14151 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14152                          uint32_t pixel_format)
14153 {
14154         u32 gen = INTEL_INFO(dev)->gen;
14155
14156         if (gen >= 9) {
14157                 /* "The stride in bytes must not exceed the of the size of 8K
14158                  *  pixels and 32K bytes."
14159                  */
14160                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14161         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14162                 return 32*1024;
14163         } else if (gen >= 4) {
14164                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14165                         return 16*1024;
14166                 else
14167                         return 32*1024;
14168         } else if (gen >= 3) {
14169                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14170                         return 8*1024;
14171                 else
14172                         return 16*1024;
14173         } else {
14174                 /* XXX DSPC is limited to 4k tiled */
14175                 return 8*1024;
14176         }
14177 }
14178
14179 static int intel_framebuffer_init(struct drm_device *dev,
14180                                   struct intel_framebuffer *intel_fb,
14181                                   struct drm_mode_fb_cmd2 *mode_cmd,
14182                                   struct drm_i915_gem_object *obj)
14183 {
14184         unsigned int aligned_height;
14185         int ret;
14186         u32 pitch_limit, stride_alignment;
14187
14188         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14189
14190         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14191                 /* Enforce that fb modifier and tiling mode match, but only for
14192                  * X-tiled. This is needed for FBC. */
14193                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14194                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14195                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14196                         return -EINVAL;
14197                 }
14198         } else {
14199                 if (obj->tiling_mode == I915_TILING_X)
14200                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14201                 else if (obj->tiling_mode == I915_TILING_Y) {
14202                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14203                         return -EINVAL;
14204                 }
14205         }
14206
14207         /* Passed in modifier sanity checking. */
14208         switch (mode_cmd->modifier[0]) {
14209         case I915_FORMAT_MOD_Y_TILED:
14210         case I915_FORMAT_MOD_Yf_TILED:
14211                 if (INTEL_INFO(dev)->gen < 9) {
14212                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14213                                   mode_cmd->modifier[0]);
14214                         return -EINVAL;
14215                 }
14216         case DRM_FORMAT_MOD_NONE:
14217         case I915_FORMAT_MOD_X_TILED:
14218                 break;
14219         default:
14220                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14221                           mode_cmd->modifier[0]);
14222                 return -EINVAL;
14223         }
14224
14225         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14226                                                      mode_cmd->pixel_format);
14227         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14228                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14229                           mode_cmd->pitches[0], stride_alignment);
14230                 return -EINVAL;
14231         }
14232
14233         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14234                                            mode_cmd->pixel_format);
14235         if (mode_cmd->pitches[0] > pitch_limit) {
14236                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14237                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14238                           "tiled" : "linear",
14239                           mode_cmd->pitches[0], pitch_limit);
14240                 return -EINVAL;
14241         }
14242
14243         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14244             mode_cmd->pitches[0] != obj->stride) {
14245                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14246                           mode_cmd->pitches[0], obj->stride);
14247                 return -EINVAL;
14248         }
14249
14250         /* Reject formats not supported by any plane early. */
14251         switch (mode_cmd->pixel_format) {
14252         case DRM_FORMAT_C8:
14253         case DRM_FORMAT_RGB565:
14254         case DRM_FORMAT_XRGB8888:
14255         case DRM_FORMAT_ARGB8888:
14256                 break;
14257         case DRM_FORMAT_XRGB1555:
14258                 if (INTEL_INFO(dev)->gen > 3) {
14259                         DRM_DEBUG("unsupported pixel format: %s\n",
14260                                   drm_get_format_name(mode_cmd->pixel_format));
14261                         return -EINVAL;
14262                 }
14263                 break;
14264         case DRM_FORMAT_ABGR8888:
14265                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14266                         DRM_DEBUG("unsupported pixel format: %s\n",
14267                                   drm_get_format_name(mode_cmd->pixel_format));
14268                         return -EINVAL;
14269                 }
14270                 break;
14271         case DRM_FORMAT_XBGR8888:
14272         case DRM_FORMAT_XRGB2101010:
14273         case DRM_FORMAT_XBGR2101010:
14274                 if (INTEL_INFO(dev)->gen < 4) {
14275                         DRM_DEBUG("unsupported pixel format: %s\n",
14276                                   drm_get_format_name(mode_cmd->pixel_format));
14277                         return -EINVAL;
14278                 }
14279                 break;
14280         case DRM_FORMAT_ABGR2101010:
14281                 if (!IS_VALLEYVIEW(dev)) {
14282                         DRM_DEBUG("unsupported pixel format: %s\n",
14283                                   drm_get_format_name(mode_cmd->pixel_format));
14284                         return -EINVAL;
14285                 }
14286                 break;
14287         case DRM_FORMAT_YUYV:
14288         case DRM_FORMAT_UYVY:
14289         case DRM_FORMAT_YVYU:
14290         case DRM_FORMAT_VYUY:
14291                 if (INTEL_INFO(dev)->gen < 5) {
14292                         DRM_DEBUG("unsupported pixel format: %s\n",
14293                                   drm_get_format_name(mode_cmd->pixel_format));
14294                         return -EINVAL;
14295                 }
14296                 break;
14297         default:
14298                 DRM_DEBUG("unsupported pixel format: %s\n",
14299                           drm_get_format_name(mode_cmd->pixel_format));
14300                 return -EINVAL;
14301         }
14302
14303         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14304         if (mode_cmd->offsets[0] != 0)
14305                 return -EINVAL;
14306
14307         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14308                                                mode_cmd->pixel_format,
14309                                                mode_cmd->modifier[0]);
14310         /* FIXME drm helper for size checks (especially planar formats)? */
14311         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14312                 return -EINVAL;
14313
14314         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14315         intel_fb->obj = obj;
14316         intel_fb->obj->framebuffer_references++;
14317
14318         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14319         if (ret) {
14320                 DRM_ERROR("framebuffer init failed %d\n", ret);
14321                 return ret;
14322         }
14323
14324         return 0;
14325 }
14326
14327 static struct drm_framebuffer *
14328 intel_user_framebuffer_create(struct drm_device *dev,
14329                               struct drm_file *filp,
14330                               struct drm_mode_fb_cmd2 *mode_cmd)
14331 {
14332         struct drm_i915_gem_object *obj;
14333
14334         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14335                                                 mode_cmd->handles[0]));
14336         if (&obj->base == NULL)
14337                 return ERR_PTR(-ENOENT);
14338
14339         return intel_framebuffer_create(dev, mode_cmd, obj);
14340 }
14341
14342 #ifndef CONFIG_DRM_FBDEV_EMULATION
14343 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14344 {
14345 }
14346 #endif
14347
14348 static const struct drm_mode_config_funcs intel_mode_funcs = {
14349         .fb_create = intel_user_framebuffer_create,
14350         .output_poll_changed = intel_fbdev_output_poll_changed,
14351         .atomic_check = intel_atomic_check,
14352         .atomic_commit = intel_atomic_commit,
14353         .atomic_state_alloc = intel_atomic_state_alloc,
14354         .atomic_state_clear = intel_atomic_state_clear,
14355 };
14356
14357 /* Set up chip specific display functions */
14358 static void intel_init_display(struct drm_device *dev)
14359 {
14360         struct drm_i915_private *dev_priv = dev->dev_private;
14361
14362         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14363                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14364         else if (IS_CHERRYVIEW(dev))
14365                 dev_priv->display.find_dpll = chv_find_best_dpll;
14366         else if (IS_VALLEYVIEW(dev))
14367                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14368         else if (IS_PINEVIEW(dev))
14369                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14370         else
14371                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14372
14373         if (INTEL_INFO(dev)->gen >= 9) {
14374                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14375                 dev_priv->display.get_initial_plane_config =
14376                         skylake_get_initial_plane_config;
14377                 dev_priv->display.crtc_compute_clock =
14378                         haswell_crtc_compute_clock;
14379                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14380                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14381                 dev_priv->display.update_primary_plane =
14382                         skylake_update_primary_plane;
14383         } else if (HAS_DDI(dev)) {
14384                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14385                 dev_priv->display.get_initial_plane_config =
14386                         ironlake_get_initial_plane_config;
14387                 dev_priv->display.crtc_compute_clock =
14388                         haswell_crtc_compute_clock;
14389                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14390                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14391                 dev_priv->display.update_primary_plane =
14392                         ironlake_update_primary_plane;
14393         } else if (HAS_PCH_SPLIT(dev)) {
14394                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14395                 dev_priv->display.get_initial_plane_config =
14396                         ironlake_get_initial_plane_config;
14397                 dev_priv->display.crtc_compute_clock =
14398                         ironlake_crtc_compute_clock;
14399                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14400                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14401                 dev_priv->display.update_primary_plane =
14402                         ironlake_update_primary_plane;
14403         } else if (IS_VALLEYVIEW(dev)) {
14404                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14405                 dev_priv->display.get_initial_plane_config =
14406                         i9xx_get_initial_plane_config;
14407                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14408                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14409                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14410                 dev_priv->display.update_primary_plane =
14411                         i9xx_update_primary_plane;
14412         } else {
14413                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14414                 dev_priv->display.get_initial_plane_config =
14415                         i9xx_get_initial_plane_config;
14416                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14417                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14418                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14419                 dev_priv->display.update_primary_plane =
14420                         i9xx_update_primary_plane;
14421         }
14422
14423         /* Returns the core display clock speed */
14424         if (IS_SKYLAKE(dev))
14425                 dev_priv->display.get_display_clock_speed =
14426                         skylake_get_display_clock_speed;
14427         else if (IS_BROXTON(dev))
14428                 dev_priv->display.get_display_clock_speed =
14429                         broxton_get_display_clock_speed;
14430         else if (IS_BROADWELL(dev))
14431                 dev_priv->display.get_display_clock_speed =
14432                         broadwell_get_display_clock_speed;
14433         else if (IS_HASWELL(dev))
14434                 dev_priv->display.get_display_clock_speed =
14435                         haswell_get_display_clock_speed;
14436         else if (IS_VALLEYVIEW(dev))
14437                 dev_priv->display.get_display_clock_speed =
14438                         valleyview_get_display_clock_speed;
14439         else if (IS_GEN5(dev))
14440                 dev_priv->display.get_display_clock_speed =
14441                         ilk_get_display_clock_speed;
14442         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14443                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14444                 dev_priv->display.get_display_clock_speed =
14445                         i945_get_display_clock_speed;
14446         else if (IS_GM45(dev))
14447                 dev_priv->display.get_display_clock_speed =
14448                         gm45_get_display_clock_speed;
14449         else if (IS_CRESTLINE(dev))
14450                 dev_priv->display.get_display_clock_speed =
14451                         i965gm_get_display_clock_speed;
14452         else if (IS_PINEVIEW(dev))
14453                 dev_priv->display.get_display_clock_speed =
14454                         pnv_get_display_clock_speed;
14455         else if (IS_G33(dev) || IS_G4X(dev))
14456                 dev_priv->display.get_display_clock_speed =
14457                         g33_get_display_clock_speed;
14458         else if (IS_I915G(dev))
14459                 dev_priv->display.get_display_clock_speed =
14460                         i915_get_display_clock_speed;
14461         else if (IS_I945GM(dev) || IS_845G(dev))
14462                 dev_priv->display.get_display_clock_speed =
14463                         i9xx_misc_get_display_clock_speed;
14464         else if (IS_PINEVIEW(dev))
14465                 dev_priv->display.get_display_clock_speed =
14466                         pnv_get_display_clock_speed;
14467         else if (IS_I915GM(dev))
14468                 dev_priv->display.get_display_clock_speed =
14469                         i915gm_get_display_clock_speed;
14470         else if (IS_I865G(dev))
14471                 dev_priv->display.get_display_clock_speed =
14472                         i865_get_display_clock_speed;
14473         else if (IS_I85X(dev))
14474                 dev_priv->display.get_display_clock_speed =
14475                         i85x_get_display_clock_speed;
14476         else { /* 830 */
14477                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14478                 dev_priv->display.get_display_clock_speed =
14479                         i830_get_display_clock_speed;
14480         }
14481
14482         if (IS_GEN5(dev)) {
14483                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14484         } else if (IS_GEN6(dev)) {
14485                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14486         } else if (IS_IVYBRIDGE(dev)) {
14487                 /* FIXME: detect B0+ stepping and use auto training */
14488                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14489         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14490                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14491                 if (IS_BROADWELL(dev)) {
14492                         dev_priv->display.modeset_commit_cdclk =
14493                                 broadwell_modeset_commit_cdclk;
14494                         dev_priv->display.modeset_calc_cdclk =
14495                                 broadwell_modeset_calc_cdclk;
14496                 }
14497         } else if (IS_VALLEYVIEW(dev)) {
14498                 dev_priv->display.modeset_commit_cdclk =
14499                         valleyview_modeset_commit_cdclk;
14500                 dev_priv->display.modeset_calc_cdclk =
14501                         valleyview_modeset_calc_cdclk;
14502         } else if (IS_BROXTON(dev)) {
14503                 dev_priv->display.modeset_commit_cdclk =
14504                         broxton_modeset_commit_cdclk;
14505                 dev_priv->display.modeset_calc_cdclk =
14506                         broxton_modeset_calc_cdclk;
14507         }
14508
14509         switch (INTEL_INFO(dev)->gen) {
14510         case 2:
14511                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14512                 break;
14513
14514         case 3:
14515                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14516                 break;
14517
14518         case 4:
14519         case 5:
14520                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14521                 break;
14522
14523         case 6:
14524                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14525                 break;
14526         case 7:
14527         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14528                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14529                 break;
14530         case 9:
14531                 /* Drop through - unsupported since execlist only. */
14532         default:
14533                 /* Default just returns -ENODEV to indicate unsupported */
14534                 dev_priv->display.queue_flip = intel_default_queue_flip;
14535         }
14536
14537         intel_panel_init_backlight_funcs(dev);
14538
14539         mutex_init(&dev_priv->pps_mutex);
14540 }
14541
14542 /*
14543  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14544  * resume, or other times.  This quirk makes sure that's the case for
14545  * affected systems.
14546  */
14547 static void quirk_pipea_force(struct drm_device *dev)
14548 {
14549         struct drm_i915_private *dev_priv = dev->dev_private;
14550
14551         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14552         DRM_INFO("applying pipe a force quirk\n");
14553 }
14554
14555 static void quirk_pipeb_force(struct drm_device *dev)
14556 {
14557         struct drm_i915_private *dev_priv = dev->dev_private;
14558
14559         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14560         DRM_INFO("applying pipe b force quirk\n");
14561 }
14562
14563 /*
14564  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14565  */
14566 static void quirk_ssc_force_disable(struct drm_device *dev)
14567 {
14568         struct drm_i915_private *dev_priv = dev->dev_private;
14569         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14570         DRM_INFO("applying lvds SSC disable quirk\n");
14571 }
14572
14573 /*
14574  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14575  * brightness value
14576  */
14577 static void quirk_invert_brightness(struct drm_device *dev)
14578 {
14579         struct drm_i915_private *dev_priv = dev->dev_private;
14580         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14581         DRM_INFO("applying inverted panel brightness quirk\n");
14582 }
14583
14584 /* Some VBT's incorrectly indicate no backlight is present */
14585 static void quirk_backlight_present(struct drm_device *dev)
14586 {
14587         struct drm_i915_private *dev_priv = dev->dev_private;
14588         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14589         DRM_INFO("applying backlight present quirk\n");
14590 }
14591
14592 struct intel_quirk {
14593         int device;
14594         int subsystem_vendor;
14595         int subsystem_device;
14596         void (*hook)(struct drm_device *dev);
14597 };
14598
14599 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14600 struct intel_dmi_quirk {
14601         void (*hook)(struct drm_device *dev);
14602         const struct dmi_system_id (*dmi_id_list)[];
14603 };
14604
14605 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14606 {
14607         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14608         return 1;
14609 }
14610
14611 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14612         {
14613                 .dmi_id_list = &(const struct dmi_system_id[]) {
14614                         {
14615                                 .callback = intel_dmi_reverse_brightness,
14616                                 .ident = "NCR Corporation",
14617                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14618                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14619                                 },
14620                         },
14621                         { }  /* terminating entry */
14622                 },
14623                 .hook = quirk_invert_brightness,
14624         },
14625 };
14626
14627 static struct intel_quirk intel_quirks[] = {
14628         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14629         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14630
14631         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14632         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14633
14634         /* 830 needs to leave pipe A & dpll A up */
14635         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14636
14637         /* 830 needs to leave pipe B & dpll B up */
14638         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14639
14640         /* Lenovo U160 cannot use SSC on LVDS */
14641         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14642
14643         /* Sony Vaio Y cannot use SSC on LVDS */
14644         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14645
14646         /* Acer Aspire 5734Z must invert backlight brightness */
14647         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14648
14649         /* Acer/eMachines G725 */
14650         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14651
14652         /* Acer/eMachines e725 */
14653         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14654
14655         /* Acer/Packard Bell NCL20 */
14656         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14657
14658         /* Acer Aspire 4736Z */
14659         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14660
14661         /* Acer Aspire 5336 */
14662         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14663
14664         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14665         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14666
14667         /* Acer C720 Chromebook (Core i3 4005U) */
14668         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14669
14670         /* Apple Macbook 2,1 (Core 2 T7400) */
14671         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14672
14673         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14674         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14675
14676         /* HP Chromebook 14 (Celeron 2955U) */
14677         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14678
14679         /* Dell Chromebook 11 */
14680         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14681 };
14682
14683 static void intel_init_quirks(struct drm_device *dev)
14684 {
14685         struct pci_dev *d = dev->pdev;
14686         int i;
14687
14688         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14689                 struct intel_quirk *q = &intel_quirks[i];
14690
14691                 if (d->device == q->device &&
14692                     (d->subsystem_vendor == q->subsystem_vendor ||
14693                      q->subsystem_vendor == PCI_ANY_ID) &&
14694                     (d->subsystem_device == q->subsystem_device ||
14695                      q->subsystem_device == PCI_ANY_ID))
14696                         q->hook(dev);
14697         }
14698         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14699                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14700                         intel_dmi_quirks[i].hook(dev);
14701         }
14702 }
14703
14704 /* Disable the VGA plane that we never use */
14705 static void i915_disable_vga(struct drm_device *dev)
14706 {
14707         struct drm_i915_private *dev_priv = dev->dev_private;
14708         u8 sr1;
14709         u32 vga_reg = i915_vgacntrl_reg(dev);
14710
14711         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14712         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14713         outb(SR01, VGA_SR_INDEX);
14714         sr1 = inb(VGA_SR_DATA);
14715         outb(sr1 | 1<<5, VGA_SR_DATA);
14716         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14717         udelay(300);
14718
14719         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14720         POSTING_READ(vga_reg);
14721 }
14722
14723 void intel_modeset_init_hw(struct drm_device *dev)
14724 {
14725         intel_update_cdclk(dev);
14726         intel_prepare_ddi(dev);
14727         intel_init_clock_gating(dev);
14728         intel_enable_gt_powersave(dev);
14729 }
14730
14731 void intel_modeset_init(struct drm_device *dev)
14732 {
14733         struct drm_i915_private *dev_priv = dev->dev_private;
14734         int sprite, ret;
14735         enum pipe pipe;
14736         struct intel_crtc *crtc;
14737
14738         drm_mode_config_init(dev);
14739
14740         dev->mode_config.min_width = 0;
14741         dev->mode_config.min_height = 0;
14742
14743         dev->mode_config.preferred_depth = 24;
14744         dev->mode_config.prefer_shadow = 1;
14745
14746         dev->mode_config.allow_fb_modifiers = true;
14747
14748         dev->mode_config.funcs = &intel_mode_funcs;
14749
14750         intel_init_quirks(dev);
14751
14752         intel_init_pm(dev);
14753
14754         if (INTEL_INFO(dev)->num_pipes == 0)
14755                 return;
14756
14757         /*
14758          * There may be no VBT; and if the BIOS enabled SSC we can
14759          * just keep using it to avoid unnecessary flicker.  Whereas if the
14760          * BIOS isn't using it, don't assume it will work even if the VBT
14761          * indicates as much.
14762          */
14763         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14764                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14765                                             DREF_SSC1_ENABLE);
14766
14767                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14768                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14769                                      bios_lvds_use_ssc ? "en" : "dis",
14770                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14771                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14772                 }
14773         }
14774
14775         intel_init_display(dev);
14776         intel_init_audio(dev);
14777
14778         if (IS_GEN2(dev)) {
14779                 dev->mode_config.max_width = 2048;
14780                 dev->mode_config.max_height = 2048;
14781         } else if (IS_GEN3(dev)) {
14782                 dev->mode_config.max_width = 4096;
14783                 dev->mode_config.max_height = 4096;
14784         } else {
14785                 dev->mode_config.max_width = 8192;
14786                 dev->mode_config.max_height = 8192;
14787         }
14788
14789         if (IS_845G(dev) || IS_I865G(dev)) {
14790                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14791                 dev->mode_config.cursor_height = 1023;
14792         } else if (IS_GEN2(dev)) {
14793                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14794                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14795         } else {
14796                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14797                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14798         }
14799
14800         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14801
14802         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14803                       INTEL_INFO(dev)->num_pipes,
14804                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14805
14806         for_each_pipe(dev_priv, pipe) {
14807                 intel_crtc_init(dev, pipe);
14808                 for_each_sprite(dev_priv, pipe, sprite) {
14809                         ret = intel_plane_init(dev, pipe, sprite);
14810                         if (ret)
14811                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14812                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
14813                 }
14814         }
14815
14816         intel_init_dpio(dev);
14817
14818         intel_shared_dpll_init(dev);
14819
14820         /* Just disable it once at startup */
14821         i915_disable_vga(dev);
14822         intel_setup_outputs(dev);
14823
14824         /* Just in case the BIOS is doing something questionable. */
14825         intel_fbc_disable(dev_priv);
14826
14827         drm_modeset_lock_all(dev);
14828         intel_modeset_setup_hw_state(dev);
14829         drm_modeset_unlock_all(dev);
14830
14831         for_each_intel_crtc(dev, crtc) {
14832                 struct intel_initial_plane_config plane_config = {};
14833
14834                 if (!crtc->active)
14835                         continue;
14836
14837                 /*
14838                  * Note that reserving the BIOS fb up front prevents us
14839                  * from stuffing other stolen allocations like the ring
14840                  * on top.  This prevents some ugliness at boot time, and
14841                  * can even allow for smooth boot transitions if the BIOS
14842                  * fb is large enough for the active pipe configuration.
14843                  */
14844                 dev_priv->display.get_initial_plane_config(crtc,
14845                                                            &plane_config);
14846
14847                 /*
14848                  * If the fb is shared between multiple heads, we'll
14849                  * just get the first one.
14850                  */
14851                 intel_find_initial_plane_obj(crtc, &plane_config);
14852         }
14853 }
14854
14855 static void intel_enable_pipe_a(struct drm_device *dev)
14856 {
14857         struct intel_connector *connector;
14858         struct drm_connector *crt = NULL;
14859         struct intel_load_detect_pipe load_detect_temp;
14860         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14861
14862         /* We can't just switch on the pipe A, we need to set things up with a
14863          * proper mode and output configuration. As a gross hack, enable pipe A
14864          * by enabling the load detect pipe once. */
14865         for_each_intel_connector(dev, connector) {
14866                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14867                         crt = &connector->base;
14868                         break;
14869                 }
14870         }
14871
14872         if (!crt)
14873                 return;
14874
14875         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14876                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14877 }
14878
14879 static bool
14880 intel_check_plane_mapping(struct intel_crtc *crtc)
14881 {
14882         struct drm_device *dev = crtc->base.dev;
14883         struct drm_i915_private *dev_priv = dev->dev_private;
14884         u32 reg, val;
14885
14886         if (INTEL_INFO(dev)->num_pipes == 1)
14887                 return true;
14888
14889         reg = DSPCNTR(!crtc->plane);
14890         val = I915_READ(reg);
14891
14892         if ((val & DISPLAY_PLANE_ENABLE) &&
14893             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14894                 return false;
14895
14896         return true;
14897 }
14898
14899 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14900 {
14901         struct drm_device *dev = crtc->base.dev;
14902         struct drm_i915_private *dev_priv = dev->dev_private;
14903         struct intel_encoder *encoder;
14904         u32 reg;
14905         bool enable;
14906
14907         /* Clear any frame start delays used for debugging left by the BIOS */
14908         reg = PIPECONF(crtc->config->cpu_transcoder);
14909         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14910
14911         /* restore vblank interrupts to correct state */
14912         drm_crtc_vblank_reset(&crtc->base);
14913         if (crtc->active) {
14914                 struct intel_plane *plane;
14915
14916                 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
14917                 update_scanline_offset(crtc);
14918                 drm_crtc_vblank_on(&crtc->base);
14919
14920                 /* Disable everything but the primary plane */
14921                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14922                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14923                                 continue;
14924
14925                         plane->disable_plane(&plane->base, &crtc->base);
14926                 }
14927         }
14928
14929         /* We need to sanitize the plane -> pipe mapping first because this will
14930          * disable the crtc (and hence change the state) if it is wrong. Note
14931          * that gen4+ has a fixed plane -> pipe mapping.  */
14932         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14933                 bool plane;
14934
14935                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14936                               crtc->base.base.id);
14937
14938                 /* Pipe has the wrong plane attached and the plane is active.
14939                  * Temporarily change the plane mapping and disable everything
14940                  * ...  */
14941                 plane = crtc->plane;
14942                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14943                 crtc->plane = !plane;
14944                 intel_crtc_disable_noatomic(&crtc->base);
14945                 crtc->plane = plane;
14946         }
14947
14948         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14949             crtc->pipe == PIPE_A && !crtc->active) {
14950                 /* BIOS forgot to enable pipe A, this mostly happens after
14951                  * resume. Force-enable the pipe to fix this, the update_dpms
14952                  * call below we restore the pipe to the right state, but leave
14953                  * the required bits on. */
14954                 intel_enable_pipe_a(dev);
14955         }
14956
14957         /* Adjust the state of the output pipe according to whether we
14958          * have active connectors/encoders. */
14959         enable = false;
14960         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14961                 enable = true;
14962                 break;
14963         }
14964
14965         if (!enable)
14966                 intel_crtc_disable_noatomic(&crtc->base);
14967
14968         if (crtc->active != crtc->base.state->active) {
14969
14970                 /* This can happen either due to bugs in the get_hw_state
14971                  * functions or because of calls to intel_crtc_disable_noatomic,
14972                  * or because the pipe is force-enabled due to the
14973                  * pipe A quirk. */
14974                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14975                               crtc->base.base.id,
14976                               crtc->base.state->enable ? "enabled" : "disabled",
14977                               crtc->active ? "enabled" : "disabled");
14978
14979                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
14980                 crtc->base.state->active = crtc->active;
14981                 crtc->base.enabled = crtc->active;
14982
14983                 /* Because we only establish the connector -> encoder ->
14984                  * crtc links if something is active, this means the
14985                  * crtc is now deactivated. Break the links. connector
14986                  * -> encoder links are only establish when things are
14987                  *  actually up, hence no need to break them. */
14988                 WARN_ON(crtc->active);
14989
14990                 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14991                         encoder->base.crtc = NULL;
14992         }
14993
14994         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14995                 /*
14996                  * We start out with underrun reporting disabled to avoid races.
14997                  * For correct bookkeeping mark this on active crtcs.
14998                  *
14999                  * Also on gmch platforms we dont have any hardware bits to
15000                  * disable the underrun reporting. Which means we need to start
15001                  * out with underrun reporting disabled also on inactive pipes,
15002                  * since otherwise we'll complain about the garbage we read when
15003                  * e.g. coming up after runtime pm.
15004                  *
15005                  * No protection against concurrent access is required - at
15006                  * worst a fifo underrun happens which also sets this to false.
15007                  */
15008                 crtc->cpu_fifo_underrun_disabled = true;
15009                 crtc->pch_fifo_underrun_disabled = true;
15010         }
15011 }
15012
15013 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15014 {
15015         struct intel_connector *connector;
15016         struct drm_device *dev = encoder->base.dev;
15017         bool active = false;
15018
15019         /* We need to check both for a crtc link (meaning that the
15020          * encoder is active and trying to read from a pipe) and the
15021          * pipe itself being active. */
15022         bool has_active_crtc = encoder->base.crtc &&
15023                 to_intel_crtc(encoder->base.crtc)->active;
15024
15025         for_each_intel_connector(dev, connector) {
15026                 if (connector->base.encoder != &encoder->base)
15027                         continue;
15028
15029                 active = true;
15030                 break;
15031         }
15032
15033         if (active && !has_active_crtc) {
15034                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15035                               encoder->base.base.id,
15036                               encoder->base.name);
15037
15038                 /* Connector is active, but has no active pipe. This is
15039                  * fallout from our resume register restoring. Disable
15040                  * the encoder manually again. */
15041                 if (encoder->base.crtc) {
15042                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15043                                       encoder->base.base.id,
15044                                       encoder->base.name);
15045                         encoder->disable(encoder);
15046                         if (encoder->post_disable)
15047                                 encoder->post_disable(encoder);
15048                 }
15049                 encoder->base.crtc = NULL;
15050
15051                 /* Inconsistent output/port/pipe state happens presumably due to
15052                  * a bug in one of the get_hw_state functions. Or someplace else
15053                  * in our code, like the register restore mess on resume. Clamp
15054                  * things to off as a safer default. */
15055                 for_each_intel_connector(dev, connector) {
15056                         if (connector->encoder != encoder)
15057                                 continue;
15058                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15059                         connector->base.encoder = NULL;
15060                 }
15061         }
15062         /* Enabled encoders without active connectors will be fixed in
15063          * the crtc fixup. */
15064 }
15065
15066 void i915_redisable_vga_power_on(struct drm_device *dev)
15067 {
15068         struct drm_i915_private *dev_priv = dev->dev_private;
15069         u32 vga_reg = i915_vgacntrl_reg(dev);
15070
15071         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15072                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15073                 i915_disable_vga(dev);
15074         }
15075 }
15076
15077 void i915_redisable_vga(struct drm_device *dev)
15078 {
15079         struct drm_i915_private *dev_priv = dev->dev_private;
15080
15081         /* This function can be called both from intel_modeset_setup_hw_state or
15082          * at a very early point in our resume sequence, where the power well
15083          * structures are not yet restored. Since this function is at a very
15084          * paranoid "someone might have enabled VGA while we were not looking"
15085          * level, just check if the power well is enabled instead of trying to
15086          * follow the "don't touch the power well if we don't need it" policy
15087          * the rest of the driver uses. */
15088         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15089                 return;
15090
15091         i915_redisable_vga_power_on(dev);
15092 }
15093
15094 static bool primary_get_hw_state(struct intel_plane *plane)
15095 {
15096         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15097
15098         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15099 }
15100
15101 /* FIXME read out full plane state for all planes */
15102 static void readout_plane_state(struct intel_crtc *crtc)
15103 {
15104         struct drm_plane *primary = crtc->base.primary;
15105         struct intel_plane_state *plane_state =
15106                 to_intel_plane_state(primary->state);
15107
15108         plane_state->visible =
15109                 primary_get_hw_state(to_intel_plane(primary));
15110
15111         if (plane_state->visible)
15112                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15113 }
15114
15115 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15116 {
15117         struct drm_i915_private *dev_priv = dev->dev_private;
15118         enum pipe pipe;
15119         struct intel_crtc *crtc;
15120         struct intel_encoder *encoder;
15121         struct intel_connector *connector;
15122         int i;
15123
15124         for_each_intel_crtc(dev, crtc) {
15125                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15126                 memset(crtc->config, 0, sizeof(*crtc->config));
15127                 crtc->config->base.crtc = &crtc->base;
15128
15129                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15130                                                                  crtc->config);
15131
15132                 crtc->base.state->active = crtc->active;
15133                 crtc->base.enabled = crtc->active;
15134
15135                 readout_plane_state(crtc);
15136
15137                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15138                               crtc->base.base.id,
15139                               crtc->active ? "enabled" : "disabled");
15140         }
15141
15142         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15143                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15144
15145                 pll->on = pll->get_hw_state(dev_priv, pll,
15146                                             &pll->config.hw_state);
15147                 pll->active = 0;
15148                 pll->config.crtc_mask = 0;
15149                 for_each_intel_crtc(dev, crtc) {
15150                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15151                                 pll->active++;
15152                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15153                         }
15154                 }
15155
15156                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15157                               pll->name, pll->config.crtc_mask, pll->on);
15158
15159                 if (pll->config.crtc_mask)
15160                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15161         }
15162
15163         for_each_intel_encoder(dev, encoder) {
15164                 pipe = 0;
15165
15166                 if (encoder->get_hw_state(encoder, &pipe)) {
15167                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15168                         encoder->base.crtc = &crtc->base;
15169                         encoder->get_config(encoder, crtc->config);
15170                 } else {
15171                         encoder->base.crtc = NULL;
15172                 }
15173
15174                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15175                               encoder->base.base.id,
15176                               encoder->base.name,
15177                               encoder->base.crtc ? "enabled" : "disabled",
15178                               pipe_name(pipe));
15179         }
15180
15181         for_each_intel_connector(dev, connector) {
15182                 if (connector->get_hw_state(connector)) {
15183                         connector->base.dpms = DRM_MODE_DPMS_ON;
15184                         connector->base.encoder = &connector->encoder->base;
15185                 } else {
15186                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15187                         connector->base.encoder = NULL;
15188                 }
15189                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15190                               connector->base.base.id,
15191                               connector->base.name,
15192                               connector->base.encoder ? "enabled" : "disabled");
15193         }
15194
15195         for_each_intel_crtc(dev, crtc) {
15196                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15197
15198                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15199                 if (crtc->base.state->active) {
15200                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15201                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15202                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15203
15204                         /*
15205                          * The initial mode needs to be set in order to keep
15206                          * the atomic core happy. It wants a valid mode if the
15207                          * crtc's enabled, so we do the above call.
15208                          *
15209                          * At this point some state updated by the connectors
15210                          * in their ->detect() callback has not run yet, so
15211                          * no recalculation can be done yet.
15212                          *
15213                          * Even if we could do a recalculation and modeset
15214                          * right now it would cause a double modeset if
15215                          * fbdev or userspace chooses a different initial mode.
15216                          *
15217                          * If that happens, someone indicated they wanted a
15218                          * mode change, which means it's safe to do a full
15219                          * recalculation.
15220                          */
15221                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15222                 }
15223         }
15224 }
15225
15226 /* Scan out the current hw modeset state,
15227  * and sanitizes it to the current state
15228  */
15229 static void
15230 intel_modeset_setup_hw_state(struct drm_device *dev)
15231 {
15232         struct drm_i915_private *dev_priv = dev->dev_private;
15233         enum pipe pipe;
15234         struct intel_crtc *crtc;
15235         struct intel_encoder *encoder;
15236         int i;
15237
15238         intel_modeset_readout_hw_state(dev);
15239
15240         /* HW state is read out, now we need to sanitize this mess. */
15241         for_each_intel_encoder(dev, encoder) {
15242                 intel_sanitize_encoder(encoder);
15243         }
15244
15245         for_each_pipe(dev_priv, pipe) {
15246                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15247                 intel_sanitize_crtc(crtc);
15248                 intel_dump_pipe_config(crtc, crtc->config,
15249                                        "[setup_hw_state]");
15250         }
15251
15252         intel_modeset_update_connector_atomic_state(dev);
15253
15254         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15255                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15256
15257                 if (!pll->on || pll->active)
15258                         continue;
15259
15260                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15261
15262                 pll->disable(dev_priv, pll);
15263                 pll->on = false;
15264         }
15265
15266         if (IS_VALLEYVIEW(dev))
15267                 vlv_wm_get_hw_state(dev);
15268         else if (IS_GEN9(dev))
15269                 skl_wm_get_hw_state(dev);
15270         else if (HAS_PCH_SPLIT(dev))
15271                 ilk_wm_get_hw_state(dev);
15272
15273         for_each_intel_crtc(dev, crtc) {
15274                 unsigned long put_domains;
15275
15276                 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15277                 if (WARN_ON(put_domains))
15278                         modeset_put_power_domains(dev_priv, put_domains);
15279         }
15280         intel_display_set_init_power(dev_priv, false);
15281 }
15282
15283 void intel_display_resume(struct drm_device *dev)
15284 {
15285         struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15286         struct intel_connector *conn;
15287         struct intel_plane *plane;
15288         struct drm_crtc *crtc;
15289         int ret;
15290
15291         if (!state)
15292                 return;
15293
15294         state->acquire_ctx = dev->mode_config.acquire_ctx;
15295
15296         /* preserve complete old state, including dpll */
15297         intel_atomic_get_shared_dpll_state(state);
15298
15299         for_each_crtc(dev, crtc) {
15300                 struct drm_crtc_state *crtc_state =
15301                         drm_atomic_get_crtc_state(state, crtc);
15302
15303                 ret = PTR_ERR_OR_ZERO(crtc_state);
15304                 if (ret)
15305                         goto err;
15306
15307                 /* force a restore */
15308                 crtc_state->mode_changed = true;
15309         }
15310
15311         for_each_intel_plane(dev, plane) {
15312                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15313                 if (ret)
15314                         goto err;
15315         }
15316
15317         for_each_intel_connector(dev, conn) {
15318                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15319                 if (ret)
15320                         goto err;
15321         }
15322
15323         intel_modeset_setup_hw_state(dev);
15324
15325         i915_redisable_vga(dev);
15326         ret = drm_atomic_commit(state);
15327         if (!ret)
15328                 return;
15329
15330 err:
15331         DRM_ERROR("Restoring old state failed with %i\n", ret);
15332         drm_atomic_state_free(state);
15333 }
15334
15335 void intel_modeset_gem_init(struct drm_device *dev)
15336 {
15337         struct drm_crtc *c;
15338         struct drm_i915_gem_object *obj;
15339         int ret;
15340
15341         mutex_lock(&dev->struct_mutex);
15342         intel_init_gt_powersave(dev);
15343         mutex_unlock(&dev->struct_mutex);
15344
15345         intel_modeset_init_hw(dev);
15346
15347         intel_setup_overlay(dev);
15348
15349         /*
15350          * Make sure any fbs we allocated at startup are properly
15351          * pinned & fenced.  When we do the allocation it's too early
15352          * for this.
15353          */
15354         for_each_crtc(dev, c) {
15355                 obj = intel_fb_obj(c->primary->fb);
15356                 if (obj == NULL)
15357                         continue;
15358
15359                 mutex_lock(&dev->struct_mutex);
15360                 ret = intel_pin_and_fence_fb_obj(c->primary,
15361                                                  c->primary->fb,
15362                                                  c->primary->state,
15363                                                  NULL, NULL);
15364                 mutex_unlock(&dev->struct_mutex);
15365                 if (ret) {
15366                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15367                                   to_intel_crtc(c)->pipe);
15368                         drm_framebuffer_unreference(c->primary->fb);
15369                         c->primary->fb = NULL;
15370                         c->primary->crtc = c->primary->state->crtc = NULL;
15371                         update_state_fb(c->primary);
15372                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15373                 }
15374         }
15375
15376         intel_backlight_register(dev);
15377 }
15378
15379 void intel_connector_unregister(struct intel_connector *intel_connector)
15380 {
15381         struct drm_connector *connector = &intel_connector->base;
15382
15383         intel_panel_destroy_backlight(connector);
15384         drm_connector_unregister(connector);
15385 }
15386
15387 void intel_modeset_cleanup(struct drm_device *dev)
15388 {
15389         struct drm_i915_private *dev_priv = dev->dev_private;
15390         struct drm_connector *connector;
15391
15392         intel_disable_gt_powersave(dev);
15393
15394         intel_backlight_unregister(dev);
15395
15396         /*
15397          * Interrupts and polling as the first thing to avoid creating havoc.
15398          * Too much stuff here (turning of connectors, ...) would
15399          * experience fancy races otherwise.
15400          */
15401         intel_irq_uninstall(dev_priv);
15402
15403         /*
15404          * Due to the hpd irq storm handling the hotplug work can re-arm the
15405          * poll handlers. Hence disable polling after hpd handling is shut down.
15406          */
15407         drm_kms_helper_poll_fini(dev);
15408
15409         intel_unregister_dsm_handler();
15410
15411         intel_fbc_disable(dev_priv);
15412
15413         /* flush any delayed tasks or pending work */
15414         flush_scheduled_work();
15415
15416         /* destroy the backlight and sysfs files before encoders/connectors */
15417         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15418                 struct intel_connector *intel_connector;
15419
15420                 intel_connector = to_intel_connector(connector);
15421                 intel_connector->unregister(intel_connector);
15422         }
15423
15424         drm_mode_config_cleanup(dev);
15425
15426         intel_cleanup_overlay(dev);
15427
15428         mutex_lock(&dev->struct_mutex);
15429         intel_cleanup_gt_powersave(dev);
15430         mutex_unlock(&dev->struct_mutex);
15431 }
15432
15433 /*
15434  * Return which encoder is currently attached for connector.
15435  */
15436 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15437 {
15438         return &intel_attached_encoder(connector)->base;
15439 }
15440
15441 void intel_connector_attach_encoder(struct intel_connector *connector,
15442                                     struct intel_encoder *encoder)
15443 {
15444         connector->encoder = encoder;
15445         drm_mode_connector_attach_encoder(&connector->base,
15446                                           &encoder->base);
15447 }
15448
15449 /*
15450  * set vga decode state - true == enable VGA decode
15451  */
15452 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15453 {
15454         struct drm_i915_private *dev_priv = dev->dev_private;
15455         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15456         u16 gmch_ctrl;
15457
15458         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15459                 DRM_ERROR("failed to read control word\n");
15460                 return -EIO;
15461         }
15462
15463         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15464                 return 0;
15465
15466         if (state)
15467                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15468         else
15469                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15470
15471         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15472                 DRM_ERROR("failed to write control word\n");
15473                 return -EIO;
15474         }
15475
15476         return 0;
15477 }
15478
15479 struct intel_display_error_state {
15480
15481         u32 power_well_driver;
15482
15483         int num_transcoders;
15484
15485         struct intel_cursor_error_state {
15486                 u32 control;
15487                 u32 position;
15488                 u32 base;
15489                 u32 size;
15490         } cursor[I915_MAX_PIPES];
15491
15492         struct intel_pipe_error_state {
15493                 bool power_domain_on;
15494                 u32 source;
15495                 u32 stat;
15496         } pipe[I915_MAX_PIPES];
15497
15498         struct intel_plane_error_state {
15499                 u32 control;
15500                 u32 stride;
15501                 u32 size;
15502                 u32 pos;
15503                 u32 addr;
15504                 u32 surface;
15505                 u32 tile_offset;
15506         } plane[I915_MAX_PIPES];
15507
15508         struct intel_transcoder_error_state {
15509                 bool power_domain_on;
15510                 enum transcoder cpu_transcoder;
15511
15512                 u32 conf;
15513
15514                 u32 htotal;
15515                 u32 hblank;
15516                 u32 hsync;
15517                 u32 vtotal;
15518                 u32 vblank;
15519                 u32 vsync;
15520         } transcoder[4];
15521 };
15522
15523 struct intel_display_error_state *
15524 intel_display_capture_error_state(struct drm_device *dev)
15525 {
15526         struct drm_i915_private *dev_priv = dev->dev_private;
15527         struct intel_display_error_state *error;
15528         int transcoders[] = {
15529                 TRANSCODER_A,
15530                 TRANSCODER_B,
15531                 TRANSCODER_C,
15532                 TRANSCODER_EDP,
15533         };
15534         int i;
15535
15536         if (INTEL_INFO(dev)->num_pipes == 0)
15537                 return NULL;
15538
15539         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15540         if (error == NULL)
15541                 return NULL;
15542
15543         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15544                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15545
15546         for_each_pipe(dev_priv, i) {
15547                 error->pipe[i].power_domain_on =
15548                         __intel_display_power_is_enabled(dev_priv,
15549                                                          POWER_DOMAIN_PIPE(i));
15550                 if (!error->pipe[i].power_domain_on)
15551                         continue;
15552
15553                 error->cursor[i].control = I915_READ(CURCNTR(i));
15554                 error->cursor[i].position = I915_READ(CURPOS(i));
15555                 error->cursor[i].base = I915_READ(CURBASE(i));
15556
15557                 error->plane[i].control = I915_READ(DSPCNTR(i));
15558                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15559                 if (INTEL_INFO(dev)->gen <= 3) {
15560                         error->plane[i].size = I915_READ(DSPSIZE(i));
15561                         error->plane[i].pos = I915_READ(DSPPOS(i));
15562                 }
15563                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15564                         error->plane[i].addr = I915_READ(DSPADDR(i));
15565                 if (INTEL_INFO(dev)->gen >= 4) {
15566                         error->plane[i].surface = I915_READ(DSPSURF(i));
15567                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15568                 }
15569
15570                 error->pipe[i].source = I915_READ(PIPESRC(i));
15571
15572                 if (HAS_GMCH_DISPLAY(dev))
15573                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15574         }
15575
15576         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15577         if (HAS_DDI(dev_priv->dev))
15578                 error->num_transcoders++; /* Account for eDP. */
15579
15580         for (i = 0; i < error->num_transcoders; i++) {
15581                 enum transcoder cpu_transcoder = transcoders[i];
15582
15583                 error->transcoder[i].power_domain_on =
15584                         __intel_display_power_is_enabled(dev_priv,
15585                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15586                 if (!error->transcoder[i].power_domain_on)
15587                         continue;
15588
15589                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15590
15591                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15592                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15593                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15594                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15595                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15596                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15597                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15598         }
15599
15600         return error;
15601 }
15602
15603 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15604
15605 void
15606 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15607                                 struct drm_device *dev,
15608                                 struct intel_display_error_state *error)
15609 {
15610         struct drm_i915_private *dev_priv = dev->dev_private;
15611         int i;
15612
15613         if (!error)
15614                 return;
15615
15616         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15617         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15618                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15619                            error->power_well_driver);
15620         for_each_pipe(dev_priv, i) {
15621                 err_printf(m, "Pipe [%d]:\n", i);
15622                 err_printf(m, "  Power: %s\n",
15623                            error->pipe[i].power_domain_on ? "on" : "off");
15624                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15625                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15626
15627                 err_printf(m, "Plane [%d]:\n", i);
15628                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15629                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15630                 if (INTEL_INFO(dev)->gen <= 3) {
15631                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15632                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15633                 }
15634                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15635                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15636                 if (INTEL_INFO(dev)->gen >= 4) {
15637                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15638                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15639                 }
15640
15641                 err_printf(m, "Cursor [%d]:\n", i);
15642                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15643                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15644                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15645         }
15646
15647         for (i = 0; i < error->num_transcoders; i++) {
15648                 err_printf(m, "CPU transcoder: %c\n",
15649                            transcoder_name(error->transcoder[i].cpu_transcoder));
15650                 err_printf(m, "  Power: %s\n",
15651                            error->transcoder[i].power_domain_on ? "on" : "off");
15652                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15653                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15654                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15655                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15656                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15657                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15658                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15659         }
15660 }
15661
15662 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15663 {
15664         struct intel_crtc *crtc;
15665
15666         for_each_intel_crtc(dev, crtc) {
15667                 struct intel_unpin_work *work;
15668
15669                 spin_lock_irq(&dev->event_lock);
15670
15671                 work = crtc->unpin_work;
15672
15673                 if (work && work->event &&
15674                     work->event->base.file_priv == file) {
15675                         kfree(work->event);
15676                         work->event = NULL;
15677                 }
15678
15679                 spin_unlock_irq(&dev->event_lock);
15680         }
15681 }