drivers/gpu/drm/radeon/atombios_encoders.c

   1 /*
   2  * Copyright 2007-11 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon.h"
  30 #include "radeon_audio.h"
  31 #include "atom.h"
  32 #include <linux/backlight.h>
  33
  34 extern int atom_debug;
  35
  36 static u8
  37 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
  38 {
  39         u8 backlight_level;
  40         u32 bios_2_scratch;
  41
  42         if (rdev->family >= CHIP_R600)
  43                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  44         else
  45                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  46
  47         backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
  48                            ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
  49
  50         return backlight_level;
  51 }
  52
  53 static void
  54 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
  55                                        u8 backlight_level)
  56 {
  57         u32 bios_2_scratch;
  58
  59         if (rdev->family >= CHIP_R600)
  60                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  61         else
  62                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  63
  64         bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
  65         bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
  66                            ATOM_S2_CURRENT_BL_LEVEL_MASK);
  67
  68         if (rdev->family >= CHIP_R600)
  69                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
  70         else
  71                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
  72 }
  73
  74 u8
  75 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
  76 {
  77         struct drm_device *dev = radeon_encoder->base.dev;
  78         struct radeon_device *rdev = dev->dev_private;
  79
  80         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  81                 return 0;
  82
  83         return radeon_atom_get_backlight_level_from_reg(rdev);
  84 }
  85
  86 void
  87 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
  88 {
  89         struct drm_encoder *encoder = &radeon_encoder->base;
  90         struct drm_device *dev = radeon_encoder->base.dev;
  91         struct radeon_device *rdev = dev->dev_private;
  92         struct radeon_encoder_atom_dig *dig;
  93         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
  94         int index;
  95
  96         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  97                 return;
  98
  99         if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
 100             radeon_encoder->enc_priv) {
 101                 dig = radeon_encoder->enc_priv;
 102                 dig->backlight_level = level;
 103                 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
 104
 105                 switch (radeon_encoder->encoder_id) {
 106                 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 107                 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 108                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 109                         if (dig->backlight_level == 0) {
 110                                 args.ucAction = ATOM_LCD_BLOFF;
 111                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 112                         } else {
 113                                 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
 114                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 115                                 args.ucAction = ATOM_LCD_BLON;
 116                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 117                         }
 118                         break;
 119                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 120                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 121                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 122                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 123                         if (dig->backlight_level == 0)
 124                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
 125                         else {
 126                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
 127                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
 128                         }
 129                         break;
 130                 default:
 131                         break;
 132                 }
 133         }
 134 }
 135
 136 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 137
 138 static u8 radeon_atom_bl_level(struct backlight_device *bd)
 139 {
 140         u8 level;
 141
 142         /* Convert brightness to hardware level */
 143         if (bd->props.brightness < 0)
 144                 level = 0;
 145         else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
 146                 level = RADEON_MAX_BL_LEVEL;
 147         else
 148                 level = bd->props.brightness;
 149
 150         return level;
 151 }
 152
 153 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
 154 {
 155         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 156         struct radeon_encoder *radeon_encoder = pdata->encoder;
 157
 158         atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
 159
 160         return 0;
 161 }
 162
 163 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
 164 {
 165         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 166         struct radeon_encoder *radeon_encoder = pdata->encoder;
 167         struct drm_device *dev = radeon_encoder->base.dev;
 168         struct radeon_device *rdev = dev->dev_private;
 169
 170         return radeon_atom_get_backlight_level_from_reg(rdev);
 171 }
 172
 173 static const struct backlight_ops radeon_atom_backlight_ops = {
 174         .get_brightness = radeon_atom_backlight_get_brightness,
 175         .update_status  = radeon_atom_backlight_update_status,
 176 };
 177
 178 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
 179                                 struct drm_connector *drm_connector)
 180 {
 181         struct drm_device *dev = radeon_encoder->base.dev;
 182         struct radeon_device *rdev = dev->dev_private;
 183         struct backlight_device *bd;
 184         struct backlight_properties props;
 185         struct radeon_backlight_privdata *pdata;
 186         struct radeon_encoder_atom_dig *dig;
 187         char bl_name[16];
 188
 189         /* Mac laptops with multiple GPUs use the gmux driver for backlight
 190          * so don't register a backlight device
 191          */
 192         if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
 193             (rdev->pdev->device == 0x6741))
 194                 return;
 195
 196         if (!radeon_encoder->enc_priv)
 197                 return;
 198
 199         if (!rdev->is_atom_bios)
 200                 return;
 201
 202         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 203                 return;
 204
 205         pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
 206         if (!pdata) {
 207                 DRM_ERROR("Memory allocation failed\n");
 208                 goto error;
 209         }
 210
 211         memset(&props, 0, sizeof(props));
 212         props.max_brightness = RADEON_MAX_BL_LEVEL;
 213         props.type = BACKLIGHT_RAW;
 214         snprintf(bl_name, sizeof(bl_name),
 215                  "radeon_bl%d", dev->primary->index);
 216         bd = backlight_device_register(bl_name, drm_connector->kdev,
 217                                        pdata, &radeon_atom_backlight_ops, &props);
 218         if (IS_ERR(bd)) {
 219                 DRM_ERROR("Backlight registration failed\n");
 220                 goto error;
 221         }
 222
 223         pdata->encoder = radeon_encoder;
 224
 225         dig = radeon_encoder->enc_priv;
 226         dig->bl_dev = bd;
 227
 228         bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
 229         /* Set a reasonable default here if the level is 0 otherwise
 230          * fbdev will attempt to turn the backlight on after console
 231          * unblanking and it will try and restore 0 which turns the backlight
 232          * off again.
 233          */
 234         if (bd->props.brightness == 0)
 235                 bd->props.brightness = RADEON_MAX_BL_LEVEL;
 236         bd->props.power = FB_BLANK_UNBLANK;
 237         backlight_update_status(bd);
 238
 239         DRM_INFO("radeon atom DIG backlight initialized\n");
 240         rdev->mode_info.bl_encoder = radeon_encoder;
 241
 242         return;
 243
 244 error:
 245         kfree(pdata);
 246         return;
 247 }
 248
 249 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
 250 {
 251         struct drm_device *dev = radeon_encoder->base.dev;
 252         struct radeon_device *rdev = dev->dev_private;
 253         struct backlight_device *bd = NULL;
 254         struct radeon_encoder_atom_dig *dig;
 255
 256         if (!radeon_encoder->enc_priv)
 257                 return;
 258
 259         if (!rdev->is_atom_bios)
 260                 return;
 261
 262         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 263                 return;
 264
 265         dig = radeon_encoder->enc_priv;
 266         bd = dig->bl_dev;
 267         dig->bl_dev = NULL;
 268
 269         if (bd) {
 270                 struct radeon_legacy_backlight_privdata *pdata;
 271
 272                 pdata = bl_get_data(bd);
 273                 backlight_device_unregister(bd);
 274                 kfree(pdata);
 275
 276                 DRM_INFO("radeon atom LVDS backlight unloaded\n");
 277         }
 278 }
 279
 280 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
 281
 282 void radeon_atom_backlight_init(struct radeon_encoder *encoder)
 283 {
 284 }
 285
 286 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
 287 {
 288 }
 289
 290 #endif
 291
 292 /* evil but including atombios.h is much worse */
 293 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
 294                                 struct drm_display_mode *mode);
 295
 296 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 297                                    const struct drm_display_mode *mode,
 298                                    struct drm_display_mode *adjusted_mode)
 299 {
 300         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 301         struct drm_device *dev = encoder->dev;
 302         struct radeon_device *rdev = dev->dev_private;
 303
 304         /* set the active encoder to connector routing */
 305         radeon_encoder_set_active_device(encoder);
 306         drm_mode_set_crtcinfo(adjusted_mode, 0);
 307
 308         /* hw bug */
 309         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 310             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 311                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 312
 313         /* get the native mode for scaling */
 314         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
 315                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 316         } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 317                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 318                 if (tv_dac) {
 319                         if (tv_dac->tv_std == TV_STD_NTSC ||
 320                             tv_dac->tv_std == TV_STD_NTSC_J ||
 321                             tv_dac->tv_std == TV_STD_PAL_M)
 322                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 323                         else
 324                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 325                 }
 326         } else if (radeon_encoder->rmx_type != RMX_OFF) {
 327                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 328         }
 329
 330         if (ASIC_IS_DCE3(rdev) &&
 331             ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
 332              (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
 333                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 334                 radeon_dp_set_link_config(connector, adjusted_mode);
 335         }
 336
 337         return true;
 338 }
 339
 340 static void
 341 atombios_dac_setup(struct drm_encoder *encoder, int action)
 342 {
 343         struct drm_device *dev = encoder->dev;
 344         struct radeon_device *rdev = dev->dev_private;
 345         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 346         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 347         int index = 0;
 348         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 349
 350         memset(&args, 0, sizeof(args));
 351
 352         switch (radeon_encoder->encoder_id) {
 353         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 354         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 355                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 356                 break;
 357         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 358         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 359                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 360                 break;
 361         }
 362
 363         args.ucAction = action;
 364
 365         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 366                 args.ucDacStandard = ATOM_DAC1_PS2;
 367         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 368                 args.ucDacStandard = ATOM_DAC1_CV;
 369         else {
 370                 switch (dac_info->tv_std) {
 371                 case TV_STD_PAL:
 372                 case TV_STD_PAL_M:
 373                 case TV_STD_SCART_PAL:
 374                 case TV_STD_SECAM:
 375                 case TV_STD_PAL_CN:
 376                         args.ucDacStandard = ATOM_DAC1_PAL;
 377                         break;
 378                 case TV_STD_NTSC:
 379                 case TV_STD_NTSC_J:
 380                 case TV_STD_PAL_60:
 381                 default:
 382                         args.ucDacStandard = ATOM_DAC1_NTSC;
 383                         break;
 384                 }
 385         }
 386         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 387
 388         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 389
 390 }
 391
 392 static void
 393 atombios_tv_setup(struct drm_encoder *encoder, int action)
 394 {
 395         struct drm_device *dev = encoder->dev;
 396         struct radeon_device *rdev = dev->dev_private;
 397         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 398         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 399         int index = 0;
 400         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 401
 402         memset(&args, 0, sizeof(args));
 403
 404         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 405
 406         args.sTVEncoder.ucAction = action;
 407
 408         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 409                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 410         else {
 411                 switch (dac_info->tv_std) {
 412                 case TV_STD_NTSC:
 413                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 414                         break;
 415                 case TV_STD_PAL:
 416                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 417                         break;
 418                 case TV_STD_PAL_M:
 419                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 420                         break;
 421                 case TV_STD_PAL_60:
 422                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 423                         break;
 424                 case TV_STD_NTSC_J:
 425                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 426                         break;
 427                 case TV_STD_SCART_PAL:
 428                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 429                         break;
 430                 case TV_STD_SECAM:
 431                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 432                         break;
 433                 case TV_STD_PAL_CN:
 434                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 435                         break;
 436                 default:
 437                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 438                         break;
 439                 }
 440         }
 441
 442         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 443
 444         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 445
 446 }
 447
 448 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
 449 {
 450         int bpc = 8;
 451
 452         if (encoder->crtc) {
 453                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 454                 bpc = radeon_crtc->bpc;
 455         }
 456
 457         switch (bpc) {
 458         case 0:
 459                 return PANEL_BPC_UNDEFINE;
 460         case 6:
 461                 return PANEL_6BIT_PER_COLOR;
 462         case 8:
 463         default:
 464                 return PANEL_8BIT_PER_COLOR;
 465         case 10:
 466                 return PANEL_10BIT_PER_COLOR;
 467         case 12:
 468                 return PANEL_12BIT_PER_COLOR;
 469         case 16:
 470                 return PANEL_16BIT_PER_COLOR;
 471         }
 472 }
 473
 474 union dvo_encoder_control {
 475         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
 476         DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
 477         DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
 478         DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
 479 };
 480
 481 void
 482 atombios_dvo_setup(struct drm_encoder *encoder, int action)
 483 {
 484         struct drm_device *dev = encoder->dev;
 485         struct radeon_device *rdev = dev->dev_private;
 486         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 487         union dvo_encoder_control args;
 488         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 489         uint8_t frev, crev;
 490
 491         memset(&args, 0, sizeof(args));
 492
 493         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 494                 return;
 495
 496         /* some R4xx chips have the wrong frev */
 497         if (rdev->family <= CHIP_RV410)
 498                 frev = 1;
 499
 500         switch (frev) {
 501         case 1:
 502                 switch (crev) {
 503                 case 1:
 504                         /* R4xx, R5xx */
 505                         args.ext_tmds.sXTmdsEncoder.ucEnable = action;
 506
 507                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 508                                 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 509
 510                         args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
 511                         break;
 512                 case 2:
 513                         /* RS600/690/740 */
 514                         args.dvo.sDVOEncoder.ucAction = action;
 515                         args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 516                         /* DFP1, CRT1, TV1 depending on the type of port */
 517                         args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
 518
 519                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 520                                 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
 521                         break;
 522                 case 3:
 523                         /* R6xx */
 524                         args.dvo_v3.ucAction = action;
 525                         args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 526                         args.dvo_v3.ucDVOConfig = 0; /* XXX */
 527                         break;
 528                 case 4:
 529                         /* DCE8 */
 530                         args.dvo_v4.ucAction = action;
 531                         args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 532                         args.dvo_v4.ucDVOConfig = 0; /* XXX */
 533                         args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 534                         break;
 535                 default:
 536                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 537                         break;
 538                 }
 539                 break;
 540         default:
 541                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 542                 break;
 543         }
 544
 545         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 546 }
 547
 548 union lvds_encoder_control {
 549         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 550         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 551 };
 552
 553 void
 554 atombios_digital_setup(struct drm_encoder *encoder, int action)
 555 {
 556         struct drm_device *dev = encoder->dev;
 557         struct radeon_device *rdev = dev->dev_private;
 558         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 559         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 560         union lvds_encoder_control args;
 561         int index = 0;
 562         int hdmi_detected = 0;
 563         uint8_t frev, crev;
 564
 565         if (!dig)
 566                 return;
 567
 568         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 569                 hdmi_detected = 1;
 570
 571         memset(&args, 0, sizeof(args));
 572
 573         switch (radeon_encoder->encoder_id) {
 574         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 575                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 576                 break;
 577         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 578         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 579                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 580                 break;
 581         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 582                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 583                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 584                 else
 585                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 586                 break;
 587         }
 588
 589         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 590                 return;
 591
 592         switch (frev) {
 593         case 1:
 594         case 2:
 595                 switch (crev) {
 596                 case 1:
 597                         args.v1.ucMisc = 0;
 598                         args.v1.ucAction = action;
 599                         if (hdmi_detected)
 600                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 601                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 602                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 603                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 604                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 605                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 606                                         args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 607                         } else {
 608                                 if (dig->linkb)
 609                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 610                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 611                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 612                                 /*if (pScrn->rgbBits == 8) */
 613                                 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 614                         }
 615                         break;
 616                 case 2:
 617                 case 3:
 618                         args.v2.ucMisc = 0;
 619                         args.v2.ucAction = action;
 620                         if (crev == 3) {
 621                                 if (dig->coherent_mode)
 622                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 623                         }
 624                         if (hdmi_detected)
 625                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 626                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 627                         args.v2.ucTruncate = 0;
 628                         args.v2.ucSpatial = 0;
 629                         args.v2.ucTemporal = 0;
 630                         args.v2.ucFRC = 0;
 631                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 632                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 633                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 634                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
 635                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 636                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 637                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 638                                 }
 639                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
 640                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 641                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 642                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 643                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 644                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 645                                 }
 646                         } else {
 647                                 if (dig->linkb)
 648                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 649                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 650                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 651                         }
 652                         break;
 653                 default:
 654                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 655                         break;
 656                 }
 657                 break;
 658         default:
 659                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 660                 break;
 661         }
 662
 663         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 664 }
 665
 666 int
 667 atombios_get_encoder_mode(struct drm_encoder *encoder)
 668 {
 669         struct drm_device *dev = encoder->dev;
 670         struct radeon_device *rdev = dev->dev_private;
 671         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 672         struct drm_connector *connector;
 673         struct radeon_connector *radeon_connector;
 674         struct radeon_connector_atom_dig *dig_connector;
 675         struct radeon_encoder_atom_dig *dig_enc;
 676
 677         if (radeon_encoder_is_digital(encoder)) {
 678                 dig_enc = radeon_encoder->enc_priv;
 679                 if (dig_enc->active_mst_links)
 680                         return ATOM_ENCODER_MODE_DP_MST;
 681         }
 682         if (radeon_encoder->is_mst_encoder || radeon_encoder->offset)
 683                 return ATOM_ENCODER_MODE_DP_MST;
 684         /* dp bridges are always DP */
 685         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
 686                 return ATOM_ENCODER_MODE_DP;
 687
 688         /* DVO is always DVO */
 689         if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
 690             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
 691                 return ATOM_ENCODER_MODE_DVO;
 692
 693         connector = radeon_get_connector_for_encoder(encoder);
 694         /* if we don't have an active device yet, just use one of
 695          * the connectors tied to the encoder.
 696          */
 697         if (!connector)
 698                 connector = radeon_get_connector_for_encoder_init(encoder);
 699         radeon_connector = to_radeon_connector(connector);
 700
 701         switch (connector->connector_type) {
 702         case DRM_MODE_CONNECTOR_DVII:
 703         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 704                 if (radeon_audio != 0) {
 705                         if (radeon_connector->use_digital &&
 706                             (radeon_connector->audio == RADEON_AUDIO_ENABLE))
 707                                 return ATOM_ENCODER_MODE_HDMI;
 708                         else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 709                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 710                                 return ATOM_ENCODER_MODE_HDMI;
 711                         else if (radeon_connector->use_digital)
 712                                 return ATOM_ENCODER_MODE_DVI;
 713                         else
 714                                 return ATOM_ENCODER_MODE_CRT;
 715                 } else if (radeon_connector->use_digital) {
 716                         return ATOM_ENCODER_MODE_DVI;
 717                 } else {
 718                         return ATOM_ENCODER_MODE_CRT;
 719                 }
 720                 break;
 721         case DRM_MODE_CONNECTOR_DVID:
 722         case DRM_MODE_CONNECTOR_HDMIA:
 723         default:
 724                 if (radeon_audio != 0) {
 725                         if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
 726                                 return ATOM_ENCODER_MODE_HDMI;
 727                         else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 728                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 729                                 return ATOM_ENCODER_MODE_HDMI;
 730                         else
 731                                 return ATOM_ENCODER_MODE_DVI;
 732                 } else {
 733                         return ATOM_ENCODER_MODE_DVI;
 734                 }
 735                 break;
 736         case DRM_MODE_CONNECTOR_LVDS:
 737                 return ATOM_ENCODER_MODE_LVDS;
 738                 break;
 739         case DRM_MODE_CONNECTOR_DisplayPort:
 740                 dig_connector = radeon_connector->con_priv;
 741                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 742                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 743                         if (radeon_audio != 0 &&
 744                             drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
 745                             ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
 746                                 return ATOM_ENCODER_MODE_DP_AUDIO;
 747                         return ATOM_ENCODER_MODE_DP;
 748                 } else if (radeon_audio != 0) {
 749                         if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
 750                                 return ATOM_ENCODER_MODE_HDMI;
 751                         else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 752                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 753                                 return ATOM_ENCODER_MODE_HDMI;
 754                         else
 755                                 return ATOM_ENCODER_MODE_DVI;
 756                 } else {
 757                         return ATOM_ENCODER_MODE_DVI;
 758                 }
 759                 break;
 760         case DRM_MODE_CONNECTOR_eDP:
 761                 if (radeon_audio != 0 &&
 762                     drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
 763                     ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
 764                         return ATOM_ENCODER_MODE_DP_AUDIO;
 765                 return ATOM_ENCODER_MODE_DP;
 766         case DRM_MODE_CONNECTOR_DVIA:
 767         case DRM_MODE_CONNECTOR_VGA:
 768                 return ATOM_ENCODER_MODE_CRT;
 769                 break;
 770         case DRM_MODE_CONNECTOR_Composite:
 771         case DRM_MODE_CONNECTOR_SVIDEO:
 772         case DRM_MODE_CONNECTOR_9PinDIN:
 773                 /* fix me */
 774                 return ATOM_ENCODER_MODE_TV;
 775                 /*return ATOM_ENCODER_MODE_CV;*/
 776                 break;
 777         }
 778 }
 779
 780 /*
 781  * DIG Encoder/Transmitter Setup
 782  *
 783  * DCE 3.0/3.1
 784  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 785  * Supports up to 3 digital outputs
 786  * - 2 DIG encoder blocks.
 787  * DIG1 can drive UNIPHY link A or link B
 788  * DIG2 can drive UNIPHY link B or LVTMA
 789  *
 790  * DCE 3.2
 791  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 792  * Supports up to 5 digital outputs
 793  * - 2 DIG encoder blocks.
 794  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 795  *
 796  * DCE 4.0/5.0/6.0
 797  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 798  * Supports up to 6 digital outputs
 799  * - 6 DIG encoder blocks.
 800  * - DIG to PHY mapping is hardcoded
 801  * DIG1 drives UNIPHY0 link A, A+B
 802  * DIG2 drives UNIPHY0 link B
 803  * DIG3 drives UNIPHY1 link A, A+B
 804  * DIG4 drives UNIPHY1 link B
 805  * DIG5 drives UNIPHY2 link A, A+B
 806  * DIG6 drives UNIPHY2 link B
 807  *
 808  * DCE 4.1
 809  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 810  * Supports up to 6 digital outputs
 811  * - 2 DIG encoder blocks.
 812  * llano
 813  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 814  * ontario
 815  * DIG1 drives UNIPHY0/1/2 link A
 816  * DIG2 drives UNIPHY0/1/2 link B
 817  *
 818  * Routing
 819  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 820  * Examples:
 821  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 822  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 823  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 824  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 825  */
 826
 827 union dig_encoder_control {
 828         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 829         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 830         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 831         DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
 832 };
 833
 834 void
 835 atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override)
 836 {
 837         struct drm_device *dev = encoder->dev;
 838         struct radeon_device *rdev = dev->dev_private;
 839         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 840         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 841         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 842         union dig_encoder_control args;
 843         int index = 0;
 844         uint8_t frev, crev;
 845         int dp_clock = 0;
 846         int dp_lane_count = 0;
 847         int hpd_id = RADEON_HPD_NONE;
 848
 849         if (connector) {
 850                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 851                 struct radeon_connector_atom_dig *dig_connector =
 852                         radeon_connector->con_priv;
 853
 854                 dp_clock = dig_connector->dp_clock;
 855                 dp_lane_count = dig_connector->dp_lane_count;
 856                 hpd_id = radeon_connector->hpd.hpd;
 857         }
 858
 859         /* no dig encoder assigned */
 860         if (dig->dig_encoder == -1)
 861                 return;
 862
 863         memset(&args, 0, sizeof(args));
 864
 865         if (ASIC_IS_DCE4(rdev))
 866                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 867         else {
 868                 if (dig->dig_encoder)
 869                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 870                 else
 871                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 872         }
 873
 874         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 875                 return;
 876
 877         switch (frev) {
 878         case 1:
 879                 switch (crev) {
 880                 case 1:
 881                         args.v1.ucAction = action;
 882                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 883                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 884                                 args.v3.ucPanelMode = panel_mode;
 885                         else
 886                                 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 887
 888                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 889                                 args.v1.ucLaneNum = dp_lane_count;
 890                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 891                                 args.v1.ucLaneNum = 8;
 892                         else
 893                                 args.v1.ucLaneNum = 4;
 894
 895                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
 896                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 897                         switch (radeon_encoder->encoder_id) {
 898                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 899                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 900                                 break;
 901                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 902                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 903                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 904                                 break;
 905                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 906                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 907                                 break;
 908                         }
 909                         if (dig->linkb)
 910                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 911                         else
 912                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 913                         break;
 914                 case 2:
 915                 case 3:
 916                         args.v3.ucAction = action;
 917                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 918                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 919                                 args.v3.ucPanelMode = panel_mode;
 920                         else
 921                                 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
 922
 923                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
 924                                 args.v3.ucLaneNum = dp_lane_count;
 925                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 926                                 args.v3.ucLaneNum = 8;
 927                         else
 928                                 args.v3.ucLaneNum = 4;
 929
 930                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
 931                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
 932                         if (enc_override != -1)
 933                                 args.v3.acConfig.ucDigSel = enc_override;
 934                         else
 935                                 args.v3.acConfig.ucDigSel = dig->dig_encoder;
 936                         args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
 937                         break;
 938                 case 4:
 939                         args.v4.ucAction = action;
 940                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 941                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 942                                 args.v4.ucPanelMode = panel_mode;
 943                         else
 944                                 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
 945
 946                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
 947                                 args.v4.ucLaneNum = dp_lane_count;
 948                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 949                                 args.v4.ucLaneNum = 8;
 950                         else
 951                                 args.v4.ucLaneNum = 4;
 952
 953                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
 954                                 if (dp_clock == 540000)
 955                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
 956                                 else if (dp_clock == 324000)
 957                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
 958                                 else if (dp_clock == 270000)
 959                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
 960                                 else
 961                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
 962                         }
 963
 964                         if (enc_override != -1)
 965                                 args.v4.acConfig.ucDigSel = enc_override;
 966                         else
 967                                 args.v4.acConfig.ucDigSel = dig->dig_encoder;
 968                         args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 969                         if (hpd_id == RADEON_HPD_NONE)
 970                                 args.v4.ucHPD_ID = 0;
 971                         else
 972                                 args.v4.ucHPD_ID = hpd_id + 1;
 973                         break;
 974                 default:
 975                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 976                         break;
 977                 }
 978                 break;
 979         default:
 980                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 981                 break;
 982         }
 983
 984         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 985
 986 }
 987
 988 void
 989 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
 990 {
 991         atombios_dig_encoder_setup2(encoder, action, panel_mode, -1);
 992 }
 993
 994 union dig_transmitter_control {
 995         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 996         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 997         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
 998         DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
 999         DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
1000 };
1001
1002 void
1003 atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe)
1004 {
1005         struct drm_device *dev = encoder->dev;
1006         struct radeon_device *rdev = dev->dev_private;
1007         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1008         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1009         struct drm_connector *connector;
1010         union dig_transmitter_control args;
1011         int index = 0;
1012         uint8_t frev, crev;
1013         bool is_dp = false;
1014         int pll_id = 0;
1015         int dp_clock = 0;
1016         int dp_lane_count = 0;
1017         int connector_object_id = 0;
1018         int igp_lane_info = 0;
1019         int dig_encoder = dig->dig_encoder;
1020         int hpd_id = RADEON_HPD_NONE;
1021
1022         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1023                 connector = radeon_get_connector_for_encoder_init(encoder);
1024                 /* just needed to avoid bailing in the encoder check.  the encoder
1025                  * isn't used for init
1026                  */
1027                 dig_encoder = 0;
1028         } else
1029                 connector = radeon_get_connector_for_encoder(encoder);
1030
1031         if (connector) {
1032                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1033                 struct radeon_connector_atom_dig *dig_connector =
1034                         radeon_connector->con_priv;
1035
1036                 hpd_id = radeon_connector->hpd.hpd;
1037                 dp_clock = dig_connector->dp_clock;
1038                 dp_lane_count = dig_connector->dp_lane_count;
1039                 connector_object_id =
1040                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1041                 igp_lane_info = dig_connector->igp_lane_info;
1042         }
1043
1044         if (encoder->crtc) {
1045                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1046                 pll_id = radeon_crtc->pll_id;
1047         }
1048
1049         /* no dig encoder assigned */
1050         if (dig_encoder == -1)
1051                 return;
1052
1053         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1054                 is_dp = true;
1055
1056         memset(&args, 0, sizeof(args));
1057
1058         switch (radeon_encoder->encoder_id) {
1059         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1060                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1061                 break;
1062         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1063         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1064         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1065         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1066                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1067                 break;
1068         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1069                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1070                 break;
1071         }
1072
1073         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1074                 return;
1075
1076         switch (frev) {
1077         case 1:
1078                 switch (crev) {
1079                 case 1:
1080                         args.v1.ucAction = action;
1081                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1082                                 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1083                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1084                                 args.v1.asMode.ucLaneSel = lane_num;
1085                                 args.v1.asMode.ucLaneSet = lane_set;
1086                         } else {
1087                                 if (is_dp)
1088                                         args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1089                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1090                                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1091                                 else
1092                                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1093                         }
1094
1095                         args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1096
1097                         if (dig_encoder)
1098                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1099                         else
1100                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1101
1102                         if ((rdev->flags & RADEON_IS_IGP) &&
1103                             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1104                                 if (is_dp ||
1105                                     !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1106                                         if (igp_lane_info & 0x1)
1107                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1108                                         else if (igp_lane_info & 0x2)
1109                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1110                                         else if (igp_lane_info & 0x4)
1111                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1112                                         else if (igp_lane_info & 0x8)
1113                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1114                                 } else {
1115                                         if (igp_lane_info & 0x3)
1116                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1117                                         else if (igp_lane_info & 0xc)
1118                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1119                                 }
1120                         }
1121
1122                         if (dig->linkb)
1123                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1124                         else
1125                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1126
1127                         if (is_dp)
1128                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1129                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1130                                 if (dig->coherent_mode)
1131                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1132                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1133                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1134                         }
1135                         break;
1136                 case 2:
1137                         args.v2.ucAction = action;
1138                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1139                                 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1140                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1141                                 args.v2.asMode.ucLaneSel = lane_num;
1142                                 args.v2.asMode.ucLaneSet = lane_set;
1143                         } else {
1144                                 if (is_dp)
1145                                         args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1146                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1147                                         args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1148                                 else
1149                                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1150                         }
1151
1152                         args.v2.acConfig.ucEncoderSel = dig_encoder;
1153                         if (dig->linkb)
1154                                 args.v2.acConfig.ucLinkSel = 1;
1155
1156                         switch (radeon_encoder->encoder_id) {
1157                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1158                                 args.v2.acConfig.ucTransmitterSel = 0;
1159                                 break;
1160                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1161                                 args.v2.acConfig.ucTransmitterSel = 1;
1162                                 break;
1163                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1164                                 args.v2.acConfig.ucTransmitterSel = 2;
1165                                 break;
1166                         }
1167
1168                         if (is_dp) {
1169                                 args.v2.acConfig.fCoherentMode = 1;
1170                                 args.v2.acConfig.fDPConnector = 1;
1171                         } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1172                                 if (dig->coherent_mode)
1173                                         args.v2.acConfig.fCoherentMode = 1;
1174                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1175                                         args.v2.acConfig.fDualLinkConnector = 1;
1176                         }
1177                         break;
1178                 case 3:
1179                         args.v3.ucAction = action;
1180                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1181                                 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1182                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1183                                 args.v3.asMode.ucLaneSel = lane_num;
1184                                 args.v3.asMode.ucLaneSet = lane_set;
1185                         } else {
1186                                 if (is_dp)
1187                                         args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1188                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1189                                         args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1190                                 else
1191                                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1192                         }
1193
1194                         if (is_dp)
1195                                 args.v3.ucLaneNum = dp_lane_count;
1196                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1197                                 args.v3.ucLaneNum = 8;
1198                         else
1199                                 args.v3.ucLaneNum = 4;
1200
1201                         if (dig->linkb)
1202                                 args.v3.acConfig.ucLinkSel = 1;
1203                         if (dig_encoder & 1)
1204                                 args.v3.acConfig.ucEncoderSel = 1;
1205
1206                         /* Select the PLL for the PHY
1207                          * DP PHY should be clocked from external src if there is
1208                          * one.
1209                          */
1210                         /* On DCE4, if there is an external clock, it generates the DP ref clock */
1211                         if (is_dp && rdev->clock.dp_extclk)
1212                                 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1213                         else
1214                                 args.v3.acConfig.ucRefClkSource = pll_id;
1215
1216                         switch (radeon_encoder->encoder_id) {
1217                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1218                                 args.v3.acConfig.ucTransmitterSel = 0;
1219                                 break;
1220                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1221                                 args.v3.acConfig.ucTransmitterSel = 1;
1222                                 break;
1223                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1224                                 args.v3.acConfig.ucTransmitterSel = 2;
1225                                 break;
1226                         }
1227
1228                         if (is_dp)
1229                                 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1230                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1231                                 if (dig->coherent_mode)
1232                                         args.v3.acConfig.fCoherentMode = 1;
1233                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1234                                         args.v3.acConfig.fDualLinkConnector = 1;
1235                         }
1236                         break;
1237                 case 4:
1238                         args.v4.ucAction = action;
1239                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1240                                 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1241                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1242                                 args.v4.asMode.ucLaneSel = lane_num;
1243                                 args.v4.asMode.ucLaneSet = lane_set;
1244                         } else {
1245                                 if (is_dp)
1246                                         args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1247                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1248                                         args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1249                                 else
1250                                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1251                         }
1252
1253                         if (is_dp)
1254                                 args.v4.ucLaneNum = dp_lane_count;
1255                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1256                                 args.v4.ucLaneNum = 8;
1257                         else
1258                                 args.v4.ucLaneNum = 4;
1259
1260                         if (dig->linkb)
1261                                 args.v4.acConfig.ucLinkSel = 1;
1262                         if (dig_encoder & 1)
1263                                 args.v4.acConfig.ucEncoderSel = 1;
1264
1265                         /* Select the PLL for the PHY
1266                          * DP PHY should be clocked from external src if there is
1267                          * one.
1268                          */
1269                         /* On DCE5 DCPLL usually generates the DP ref clock */
1270                         if (is_dp) {
1271                                 if (rdev->clock.dp_extclk)
1272                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1273                                 else
1274                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1275                         } else
1276                                 args.v4.acConfig.ucRefClkSource = pll_id;
1277
1278                         switch (radeon_encoder->encoder_id) {
1279                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1280                                 args.v4.acConfig.ucTransmitterSel = 0;
1281                                 break;
1282                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1283                                 args.v4.acConfig.ucTransmitterSel = 1;
1284                                 break;
1285                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1286                                 args.v4.acConfig.ucTransmitterSel = 2;
1287                                 break;
1288                         }
1289
1290                         if (is_dp)
1291                                 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1292                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1293                                 if (dig->coherent_mode)
1294                                         args.v4.acConfig.fCoherentMode = 1;
1295                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1296                                         args.v4.acConfig.fDualLinkConnector = 1;
1297                         }
1298                         break;
1299                 case 5:
1300                         args.v5.ucAction = action;
1301                         if (is_dp)
1302                                 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1303                         else
1304                                 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1305
1306                         switch (radeon_encoder->encoder_id) {
1307                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1308                                 if (dig->linkb)
1309                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1310                                 else
1311                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1312                                 break;
1313                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1314                                 if (dig->linkb)
1315                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1316                                 else
1317                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1318                                 break;
1319                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1320                                 if (dig->linkb)
1321                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1322                                 else
1323                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1324                                 break;
1325                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1326                                 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1327                                 break;
1328                         }
1329                         if (is_dp)
1330                                 args.v5.ucLaneNum = dp_lane_count;
1331                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1332                                 args.v5.ucLaneNum = 8;
1333                         else
1334                                 args.v5.ucLaneNum = 4;
1335                         args.v5.ucConnObjId = connector_object_id;
1336                         args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1337
1338                         if (is_dp && rdev->clock.dp_extclk)
1339                                 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1340                         else
1341                                 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1342
1343                         if (is_dp)
1344                                 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1345                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1346                                 if (dig->coherent_mode)
1347                                         args.v5.asConfig.ucCoherentMode = 1;
1348                         }
1349                         if (hpd_id == RADEON_HPD_NONE)
1350                                 args.v5.asConfig.ucHPDSel = 0;
1351                         else
1352                                 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1353                         args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder);
1354                         args.v5.ucDPLaneSet = lane_set;
1355                         break;
1356                 default:
1357                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1358                         break;
1359                 }
1360                 break;
1361         default:
1362                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1363                 break;
1364         }
1365
1366         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1367 }
1368
1369 void
1370 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
1371 {
1372         atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1);
1373 }
1374
1375 bool
1376 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1377 {
1378         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1379         struct drm_device *dev = radeon_connector->base.dev;
1380         struct radeon_device *rdev = dev->dev_private;
1381         union dig_transmitter_control args;
1382         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1383         uint8_t frev, crev;
1384
1385         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1386                 goto done;
1387
1388         if (!ASIC_IS_DCE4(rdev))
1389                 goto done;
1390
1391         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1392             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1393                 goto done;
1394
1395         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1396                 goto done;
1397
1398         memset(&args, 0, sizeof(args));
1399
1400         args.v1.ucAction = action;
1401
1402         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1403
1404         /* wait for the panel to power up */
1405         if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1406                 int i;
1407
1408                 for (i = 0; i < 300; i++) {
1409                         if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1410                                 return true;
1411                         mdelay(1);
1412                 }
1413                 return false;
1414         }
1415 done:
1416         return true;
1417 }
1418
1419 union external_encoder_control {
1420         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1421         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1422 };
1423
1424 static void
1425 atombios_external_encoder_setup(struct drm_encoder *encoder,
1426                                 struct drm_encoder *ext_encoder,
1427                                 int action)
1428 {
1429         struct drm_device *dev = encoder->dev;
1430         struct radeon_device *rdev = dev->dev_private;
1431         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1432         struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1433         union external_encoder_control args;
1434         struct drm_connector *connector;
1435         int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1436         u8 frev, crev;
1437         int dp_clock = 0;
1438         int dp_lane_count = 0;
1439         int connector_object_id = 0;
1440         u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1441
1442         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1443                 connector = radeon_get_connector_for_encoder_init(encoder);
1444         else
1445                 connector = radeon_get_connector_for_encoder(encoder);
1446
1447         if (connector) {
1448                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1449                 struct radeon_connector_atom_dig *dig_connector =
1450                         radeon_connector->con_priv;
1451
1452                 dp_clock = dig_connector->dp_clock;
1453                 dp_lane_count = dig_connector->dp_lane_count;
1454                 connector_object_id =
1455                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1456         }
1457
1458         memset(&args, 0, sizeof(args));
1459
1460         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1461                 return;
1462
1463         switch (frev) {
1464         case 1:
1465                 /* no params on frev 1 */
1466                 break;
1467         case 2:
1468                 switch (crev) {
1469                 case 1:
1470                 case 2:
1471                         args.v1.sDigEncoder.ucAction = action;
1472                         args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1473                         args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1474
1475                         if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1476                                 if (dp_clock == 270000)
1477                                         args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1478                                 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1479                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1480                                 args.v1.sDigEncoder.ucLaneNum = 8;
1481                         else
1482                                 args.v1.sDigEncoder.ucLaneNum = 4;
1483                         break;
1484                 case 3:
1485                         args.v3.sExtEncoder.ucAction = action;
1486                         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1487                                 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1488                         else
1489                                 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1490                         args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1491
1492                         if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1493                                 if (dp_clock == 270000)
1494                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1495                                 else if (dp_clock == 540000)
1496                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1497                                 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1498                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1499                                 args.v3.sExtEncoder.ucLaneNum = 8;
1500                         else
1501                                 args.v3.sExtEncoder.ucLaneNum = 4;
1502                         switch (ext_enum) {
1503                         case GRAPH_OBJECT_ENUM_ID1:
1504                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1505                                 break;
1506                         case GRAPH_OBJECT_ENUM_ID2:
1507                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1508                                 break;
1509                         case GRAPH_OBJECT_ENUM_ID3:
1510                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1511                                 break;
1512                         }
1513                         args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1514                         break;
1515                 default:
1516                         DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1517                         return;
1518                 }
1519                 break;
1520         default:
1521                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1522                 return;
1523         }
1524         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1525 }
1526
1527 static void
1528 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1529 {
1530         struct drm_device *dev = encoder->dev;
1531         struct radeon_device *rdev = dev->dev_private;
1532         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1533         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1534         ENABLE_YUV_PS_ALLOCATION args;
1535         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1536         uint32_t temp, reg;
1537
1538         memset(&args, 0, sizeof(args));
1539
1540         if (rdev->family >= CHIP_R600)
1541                 reg = R600_BIOS_3_SCRATCH;
1542         else
1543                 reg = RADEON_BIOS_3_SCRATCH;
1544
1545         /* XXX: fix up scratch reg handling */
1546         temp = RREG32(reg);
1547         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1548                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1549                              (radeon_crtc->crtc_id << 18)));
1550         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1551                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1552         else
1553                 WREG32(reg, 0);
1554
1555         if (enable)
1556                 args.ucEnable = ATOM_ENABLE;
1557         args.ucCRTC = radeon_crtc->crtc_id;
1558
1559         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1560
1561         WREG32(reg, temp);
1562 }
1563
1564 static void
1565 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1566 {
1567         struct drm_device *dev = encoder->dev;
1568         struct radeon_device *rdev = dev->dev_private;
1569         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1570         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1571         int index = 0;
1572
1573         memset(&args, 0, sizeof(args));
1574
1575         switch (radeon_encoder->encoder_id) {
1576         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1577         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1578                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1579                 break;
1580         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1581         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1582         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1583                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1584                 break;
1585         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1586                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1587                 break;
1588         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1589                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1590                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1591                 else
1592                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1593                 break;
1594         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1595         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1596                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1597                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1598                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1599                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1600                 else
1601                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1602                 break;
1603         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1604         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1605                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1606                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1607                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1608                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1609                 else
1610                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1611                 break;
1612         default:
1613                 return;
1614         }
1615
1616         switch (mode) {
1617         case DRM_MODE_DPMS_ON:
1618                 args.ucAction = ATOM_ENABLE;
1619                 /* workaround for DVOOutputControl on some RS690 systems */
1620                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1621                         u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1622                         WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1623                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1624                         WREG32(RADEON_BIOS_3_SCRATCH, reg);
1625                 } else
1626                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1627                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1628                         if (rdev->mode_info.bl_encoder) {
1629                                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1630
1631                                 atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1632                         } else {
1633                                 args.ucAction = ATOM_LCD_BLON;
1634                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1635                         }
1636                 }
1637                 break;
1638         case DRM_MODE_DPMS_STANDBY:
1639         case DRM_MODE_DPMS_SUSPEND:
1640         case DRM_MODE_DPMS_OFF:
1641                 args.ucAction = ATOM_DISABLE;
1642                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1643                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1644                         args.ucAction = ATOM_LCD_BLOFF;
1645                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1646                 }
1647                 break;
1648         }
1649 }
1650
1651 static void
1652 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1653 {
1654         struct drm_device *dev = encoder->dev;
1655         struct radeon_device *rdev = dev->dev_private;
1656         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1657         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1658         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1659         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1660         struct radeon_connector *radeon_connector = NULL;
1661         struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1662         bool travis_quirk = false;
1663
1664         if (connector) {
1665                 radeon_connector = to_radeon_connector(connector);
1666                 radeon_dig_connector = radeon_connector->con_priv;
1667                 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
1668                      ENCODER_OBJECT_ID_TRAVIS) &&
1669                     (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
1670                     !ASIC_IS_DCE5(rdev))
1671                         travis_quirk = true;
1672         }
1673
1674         switch (mode) {
1675         case DRM_MODE_DPMS_ON:
1676                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1677                         if (!connector)
1678                                 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1679                         else
1680                                 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1681
1682                         /* setup and enable the encoder */
1683                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1684                         atombios_dig_encoder_setup(encoder,
1685                                                    ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1686                                                    dig->panel_mode);
1687                         if (ext_encoder) {
1688                                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1689                                         atombios_external_encoder_setup(encoder, ext_encoder,
1690                                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1691                         }
1692                 } else if (ASIC_IS_DCE4(rdev)) {
1693                         /* setup and enable the encoder */
1694                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1695                 } else {
1696                         /* setup and enable the encoder and transmitter */
1697                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1698                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1699                 }
1700                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1701                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1702                                 atombios_set_edp_panel_power(connector,
1703                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1704                                 radeon_dig_connector->edp_on = true;
1705                         }
1706                 }
1707                 /* enable the transmitter */
1708                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1709                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1710                         /* DP_SET_POWER_D0 is set in radeon_dp_link_train */
1711                         radeon_dp_link_train(encoder, connector);
1712                         if (ASIC_IS_DCE4(rdev))
1713                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1714                 }
1715                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1716                         if (rdev->mode_info.bl_encoder)
1717                                 atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1718                         else
1719                                 atombios_dig_transmitter_setup(encoder,
1720                                                                ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1721                 }
1722                 if (ext_encoder)
1723                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1724                 break;
1725         case DRM_MODE_DPMS_STANDBY:
1726         case DRM_MODE_DPMS_SUSPEND:
1727         case DRM_MODE_DPMS_OFF:
1728
1729                 /* don't power off encoders with active MST links */
1730                 if (dig->active_mst_links)
1731                         return;
1732
1733                 if (ASIC_IS_DCE4(rdev)) {
1734                         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector)
1735                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1736                 }
1737                 if (ext_encoder)
1738                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1739                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1740                         atombios_dig_transmitter_setup(encoder,
1741                                                        ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1742
1743                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) &&
1744                     connector && !travis_quirk)
1745                         radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1746                 if (ASIC_IS_DCE4(rdev)) {
1747                         /* disable the transmitter */
1748                         atombios_dig_transmitter_setup(encoder,
1749                                                        ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1750                 } else {
1751                         /* disable the encoder and transmitter */
1752                         atombios_dig_transmitter_setup(encoder,
1753                                                        ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1754                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1755                 }
1756                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1757                         if (travis_quirk)
1758                                 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1759                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1760                                 atombios_set_edp_panel_power(connector,
1761                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1762                                 radeon_dig_connector->edp_on = false;
1763                         }
1764                 }
1765                 break;
1766         }
1767 }
1768
1769 static void
1770 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1771 {
1772         struct drm_device *dev = encoder->dev;
1773         struct radeon_device *rdev = dev->dev_private;
1774         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1775         int encoder_mode = atombios_get_encoder_mode(encoder);
1776
1777         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1778                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1779                   radeon_encoder->active_device);
1780
1781         if ((radeon_audio != 0) &&
1782             ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
1783              ENCODER_MODE_IS_DP(encoder_mode)))
1784                 radeon_audio_dpms(encoder, mode);
1785
1786         switch (radeon_encoder->encoder_id) {
1787         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1788         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1789         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1790         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1791         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1792         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1793         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1794         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1795                 radeon_atom_encoder_dpms_avivo(encoder, mode);
1796                 break;
1797         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1798         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1799         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1800         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1801         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1802                 radeon_atom_encoder_dpms_dig(encoder, mode);
1803                 break;
1804         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1805                 if (ASIC_IS_DCE5(rdev)) {
1806                         switch (mode) {
1807                         case DRM_MODE_DPMS_ON:
1808                                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1809                                 break;
1810                         case DRM_MODE_DPMS_STANDBY:
1811                         case DRM_MODE_DPMS_SUSPEND:
1812                         case DRM_MODE_DPMS_OFF:
1813                                 atombios_dvo_setup(encoder, ATOM_DISABLE);
1814                                 break;
1815                         }
1816                 } else if (ASIC_IS_DCE3(rdev))
1817                         radeon_atom_encoder_dpms_dig(encoder, mode);
1818                 else
1819                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1820                 break;
1821         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1822         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1823                 if (ASIC_IS_DCE5(rdev)) {
1824                         switch (mode) {
1825                         case DRM_MODE_DPMS_ON:
1826                                 atombios_dac_setup(encoder, ATOM_ENABLE);
1827                                 break;
1828                         case DRM_MODE_DPMS_STANDBY:
1829                         case DRM_MODE_DPMS_SUSPEND:
1830                         case DRM_MODE_DPMS_OFF:
1831                                 atombios_dac_setup(encoder, ATOM_DISABLE);
1832                                 break;
1833                         }
1834                 } else
1835                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1836                 break;
1837         default:
1838                 return;
1839         }
1840
1841         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1842
1843 }
1844
1845 union crtc_source_param {
1846         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1847         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1848 };
1849
1850 static void
1851 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1852 {
1853         struct drm_device *dev = encoder->dev;
1854         struct radeon_device *rdev = dev->dev_private;
1855         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1856         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1857         union crtc_source_param args;
1858         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1859         uint8_t frev, crev;
1860         struct radeon_encoder_atom_dig *dig;
1861
1862         memset(&args, 0, sizeof(args));
1863
1864         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1865                 return;
1866
1867         switch (frev) {
1868         case 1:
1869                 switch (crev) {
1870                 case 1:
1871                 default:
1872                         if (ASIC_IS_AVIVO(rdev))
1873                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1874                         else {
1875                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1876                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1877                                 } else {
1878                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1879                                 }
1880                         }
1881                         switch (radeon_encoder->encoder_id) {
1882                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1883                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1884                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1885                                 break;
1886                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1887                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1888                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1889                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1890                                 else
1891                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1892                                 break;
1893                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1894                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1895                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1896                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1897                                 break;
1898                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1899                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1900                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1901                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1902                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1903                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1904                                 else
1905                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1906                                 break;
1907                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1908                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1909                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1910                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1911                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1912                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1913                                 else
1914                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1915                                 break;
1916                         }
1917                         break;
1918                 case 2:
1919                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1920                         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1921                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1922
1923                                 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1924                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1925                                 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1926                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1927                                 else
1928                                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1929                         } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1930                                 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1931                         } else {
1932                                 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1933                         }
1934                         switch (radeon_encoder->encoder_id) {
1935                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1936                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1937                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1938                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1939                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1940                                 dig = radeon_encoder->enc_priv;
1941                                 switch (dig->dig_encoder) {
1942                                 case 0:
1943                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1944                                         break;
1945                                 case 1:
1946                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1947                                         break;
1948                                 case 2:
1949                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1950                                         break;
1951                                 case 3:
1952                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1953                                         break;
1954                                 case 4:
1955                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1956                                         break;
1957                                 case 5:
1958                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1959                                         break;
1960                                 case 6:
1961                                         args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1962                                         break;
1963                                 }
1964                                 break;
1965                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1966                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1967                                 break;
1968                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1969                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1970                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1971                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1972                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1973                                 else
1974                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1975                                 break;
1976                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1977                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1978                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1979                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1980                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1981                                 else
1982                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1983                                 break;
1984                         }
1985                         break;
1986                 }
1987                 break;
1988         default:
1989                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1990                 return;
1991         }
1992
1993         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1994
1995         /* update scratch regs with new routing */
1996         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1997 }
1998
1999 void
2000 atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, int fe)
2001 {
2002         struct drm_device *dev = encoder->dev;
2003         struct radeon_device *rdev = dev->dev_private;
2004         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2005         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
2006         uint8_t frev, crev;
2007         union crtc_source_param args;
2008
2009         memset(&args, 0, sizeof(args));
2010
2011         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2012                 return;
2013
2014         if (frev != 1 && crev != 2)
2015                 DRM_ERROR("Unknown table for MST %d, %d\n", frev, crev);
2016
2017         args.v2.ucCRTC = radeon_crtc->crtc_id;
2018         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_DP_MST;
2019
2020         switch (fe) {
2021         case 0:
2022                 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
2023                 break;
2024         case 1:
2025                 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
2026                 break;
2027         case 2:
2028                 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
2029                 break;
2030         case 3:
2031                 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
2032                 break;
2033         case 4:
2034                 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
2035                 break;
2036         case 5:
2037                 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
2038                 break;
2039         case 6:
2040                 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
2041                 break;
2042         }
2043         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2044 }
2045
2046 static void
2047 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
2048                               struct drm_display_mode *mode)
2049 {
2050         struct drm_device *dev = encoder->dev;
2051         struct radeon_device *rdev = dev->dev_private;
2052         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2053         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2054
2055         /* Funky macbooks */
2056         if ((dev->pdev->device == 0x71C5) &&
2057             (dev->pdev->subsystem_vendor == 0x106b) &&
2058             (dev->pdev->subsystem_device == 0x0080)) {
2059                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2060                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
2061
2062                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
2063                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
2064
2065                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
2066                 }
2067         }
2068
2069         /* set scaler clears this on some chips */
2070         if (ASIC_IS_AVIVO(rdev) &&
2071             (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
2072                 if (ASIC_IS_DCE8(rdev)) {
2073                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2074                                 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
2075                                        CIK_INTERLEAVE_EN);
2076                         else
2077                                 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2078                 } else if (ASIC_IS_DCE4(rdev)) {
2079                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2080                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
2081                                        EVERGREEN_INTERLEAVE_EN);
2082                         else
2083                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2084                 } else {
2085                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2086                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
2087                                        AVIVO_D1MODE_INTERLEAVE_EN);
2088                         else
2089                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2090                 }
2091         }
2092 }
2093
2094 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx)
2095 {
2096         if (enc_idx < 0)
2097                 return;
2098         rdev->mode_info.active_encoders &= ~(1 << enc_idx);
2099 }
2100
2101 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx)
2102 {
2103         struct drm_device *dev = encoder->dev;
2104         struct radeon_device *rdev = dev->dev_private;
2105         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2106         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2107         struct drm_encoder *test_encoder;
2108         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2109         uint32_t dig_enc_in_use = 0;
2110         int enc_idx = -1;
2111
2112         if (fe_idx >= 0) {
2113                 enc_idx = fe_idx;
2114                 goto assigned;
2115         }
2116         if (ASIC_IS_DCE6(rdev)) {
2117                 /* DCE6 */
2118                 switch (radeon_encoder->encoder_id) {
2119                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2120                         if (dig->linkb)
2121                                 enc_idx = 1;
2122                         else
2123                                 enc_idx = 0;
2124                         break;
2125                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2126                         if (dig->linkb)
2127                                 enc_idx = 3;
2128                         else
2129                                 enc_idx = 2;
2130                         break;
2131                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2132                         if (dig->linkb)
2133                                 enc_idx = 5;
2134                         else
2135                                 enc_idx = 4;
2136                         break;
2137                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2138                         enc_idx = 6;
2139                         break;
2140                 }
2141                 goto assigned;
2142         } else if (ASIC_IS_DCE4(rdev)) {
2143                 /* DCE4/5 */
2144                 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2145                         /* ontario follows DCE4 */
2146                         if (rdev->family == CHIP_PALM) {
2147                                 if (dig->linkb)
2148                                         enc_idx = 1;
2149                                 else
2150                                         enc_idx = 0;
2151                         } else
2152                                 /* llano follows DCE3.2 */
2153                                 enc_idx = radeon_crtc->crtc_id;
2154                 } else {
2155                         switch (radeon_encoder->encoder_id) {
2156                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2157                                 if (dig->linkb)
2158                                         enc_idx = 1;
2159                                 else
2160                                         enc_idx = 0;
2161                                 break;
2162                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2163                                 if (dig->linkb)
2164                                         enc_idx = 3;
2165                                 else
2166                                         enc_idx = 2;
2167                                 break;
2168                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2169                                 if (dig->linkb)
2170                                         enc_idx = 5;
2171                                 else
2172                                         enc_idx = 4;
2173                                 break;
2174                         }
2175                 }
2176                 goto assigned;
2177         }
2178
2179         /* on DCE32 and encoder can driver any block so just crtc id */
2180         if (ASIC_IS_DCE32(rdev)) {
2181                 enc_idx = radeon_crtc->crtc_id;
2182                 goto assigned;
2183         }
2184
2185         /* on DCE3 - LVTMA can only be driven by DIGB */
2186         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2187                 struct radeon_encoder *radeon_test_encoder;
2188
2189                 if (encoder == test_encoder)
2190                         continue;
2191
2192                 if (!radeon_encoder_is_digital(test_encoder))
2193                         continue;
2194
2195                 radeon_test_encoder = to_radeon_encoder(test_encoder);
2196                 dig = radeon_test_encoder->enc_priv;
2197
2198                 if (dig->dig_encoder >= 0)
2199                         dig_enc_in_use |= (1 << dig->dig_encoder);
2200         }
2201
2202         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2203                 if (dig_enc_in_use & 0x2)
2204                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2205                 return 1;
2206         }
2207         if (!(dig_enc_in_use & 1))
2208                 return 0;
2209         return 1;
2210
2211 assigned:
2212         if (enc_idx == -1) {
2213                 DRM_ERROR("Got encoder index incorrect - returning 0\n");
2214                 return 0;
2215         }
2216         if (rdev->mode_info.active_encoders & (1 << enc_idx)) {
2217                 DRM_ERROR("chosen encoder in use %d\n", enc_idx);
2218         }
2219         rdev->mode_info.active_encoders |= (1 << enc_idx);
2220         return enc_idx;
2221 }
2222
2223 /* This only needs to be called once at startup */
2224 void
2225 radeon_atom_encoder_init(struct radeon_device *rdev)
2226 {
2227         struct drm_device *dev = rdev->ddev;
2228         struct drm_encoder *encoder;
2229
2230         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2231                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2232                 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2233
2234                 switch (radeon_encoder->encoder_id) {
2235                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2236                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2237                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2238                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2239                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2240                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2241                         break;
2242                 default:
2243                         break;
2244                 }
2245
2246                 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2247                         atombios_external_encoder_setup(encoder, ext_encoder,
2248                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2249         }
2250 }
2251
2252 static void
2253 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2254                              struct drm_display_mode *mode,
2255                              struct drm_display_mode *adjusted_mode)
2256 {
2257         struct drm_device *dev = encoder->dev;
2258         struct radeon_device *rdev = dev->dev_private;
2259         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2260         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2261         int encoder_mode;
2262
2263         radeon_encoder->pixel_clock = adjusted_mode->clock;
2264
2265         /* need to call this here rather than in prepare() since we need some crtc info */
2266         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2267
2268         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2269                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2270                         atombios_yuv_setup(encoder, true);
2271                 else
2272                         atombios_yuv_setup(encoder, false);
2273         }
2274
2275         switch (radeon_encoder->encoder_id) {
2276         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2277         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2278         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2279         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2280                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2281                 break;
2282         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2283         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2284         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2285         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2286         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2287                 /* handled in dpms */
2288                 break;
2289         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2290         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2291         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2292                 atombios_dvo_setup(encoder, ATOM_ENABLE);
2293                 break;
2294         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2295         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2296         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2297         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2298                 atombios_dac_setup(encoder, ATOM_ENABLE);
2299                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2300                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2301                                 atombios_tv_setup(encoder, ATOM_ENABLE);
2302                         else
2303                                 atombios_tv_setup(encoder, ATOM_DISABLE);
2304                 }
2305                 break;
2306         }
2307
2308         atombios_apply_encoder_quirks(encoder, adjusted_mode);
2309
2310         encoder_mode = atombios_get_encoder_mode(encoder);
2311         if (connector && (radeon_audio != 0) &&
2312             ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
2313              ENCODER_MODE_IS_DP(encoder_mode)))
2314                 radeon_audio_mode_set(encoder, adjusted_mode);
2315 }
2316
2317 static bool
2318 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2319 {
2320         struct drm_device *dev = encoder->dev;
2321         struct radeon_device *rdev = dev->dev_private;
2322         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2323         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2324
2325         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2326                                        ATOM_DEVICE_CV_SUPPORT |
2327                                        ATOM_DEVICE_CRT_SUPPORT)) {
2328                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2329                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2330                 uint8_t frev, crev;
2331
2332                 memset(&args, 0, sizeof(args));
2333
2334                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2335                         return false;
2336
2337                 args.sDacload.ucMisc = 0;
2338
2339                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2340                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2341                         args.sDacload.ucDacType = ATOM_DAC_A;
2342                 else
2343                         args.sDacload.ucDacType = ATOM_DAC_B;
2344
2345                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2346                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2347                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2348                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2349                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2350                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2351                         if (crev >= 3)
2352                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2353                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2354                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2355                         if (crev >= 3)
2356                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2357                 }
2358
2359                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2360
2361                 return true;
2362         } else
2363                 return false;
2364 }
2365
2366 static enum drm_connector_status
2367 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2368 {
2369         struct drm_device *dev = encoder->dev;
2370         struct radeon_device *rdev = dev->dev_private;
2371         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2372         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2373         uint32_t bios_0_scratch;
2374
2375         if (!atombios_dac_load_detect(encoder, connector)) {
2376                 DRM_DEBUG_KMS("detect returned false \n");
2377                 return connector_status_unknown;
2378         }
2379
2380         if (rdev->family >= CHIP_R600)
2381                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2382         else
2383                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2384
2385         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2386         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2387                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2388                         return connector_status_connected;
2389         }
2390         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2391                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2392                         return connector_status_connected;
2393         }
2394         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2395                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2396                         return connector_status_connected;
2397         }
2398         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2399                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2400                         return connector_status_connected; /* CTV */
2401                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2402                         return connector_status_connected; /* STV */
2403         }
2404         return connector_status_disconnected;
2405 }
2406
2407 static enum drm_connector_status
2408 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2409 {
2410         struct drm_device *dev = encoder->dev;
2411         struct radeon_device *rdev = dev->dev_private;
2412         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2413         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2414         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2415         u32 bios_0_scratch;
2416
2417         if (!ASIC_IS_DCE4(rdev))
2418                 return connector_status_unknown;
2419
2420         if (!ext_encoder)
2421                 return connector_status_unknown;
2422
2423         if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2424                 return connector_status_unknown;
2425
2426         /* load detect on the dp bridge */
2427         atombios_external_encoder_setup(encoder, ext_encoder,
2428                                         EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2429
2430         bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2431
2432         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2433         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2434                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2435                         return connector_status_connected;
2436         }
2437         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2438                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2439                         return connector_status_connected;
2440         }
2441         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2442                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2443                         return connector_status_connected;
2444         }
2445         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2446                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2447                         return connector_status_connected; /* CTV */
2448                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2449                         return connector_status_connected; /* STV */
2450         }
2451         return connector_status_disconnected;
2452 }
2453
2454 void
2455 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2456 {
2457         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2458
2459         if (ext_encoder)
2460                 /* ddc_setup on the dp bridge */
2461                 atombios_external_encoder_setup(encoder, ext_encoder,
2462                                                 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2463
2464 }
2465
2466 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2467 {
2468         struct radeon_device *rdev = encoder->dev->dev_private;
2469         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2470         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2471
2472         if ((radeon_encoder->active_device &
2473              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2474             (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2475              ENCODER_OBJECT_ID_NONE)) {
2476                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2477                 if (dig) {
2478                         if (dig->dig_encoder >= 0)
2479                                 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2480                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1);
2481                         if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2482                                 if (rdev->family >= CHIP_R600)
2483                                         dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2484                                 else
2485                                         /* RS600/690/740 have only 1 afmt block */
2486                                         dig->afmt = rdev->mode_info.afmt[0];
2487                         }
2488                 }
2489         }
2490
2491         radeon_atom_output_lock(encoder, true);
2492
2493         if (connector) {
2494                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2495
2496                 /* select the clock/data port if it uses a router */
2497                 if (radeon_connector->router.cd_valid)
2498                         radeon_router_select_cd_port(radeon_connector);
2499
2500                 /* turn eDP panel on for mode set */
2501                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2502                         atombios_set_edp_panel_power(connector,
2503                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
2504         }
2505
2506         /* this is needed for the pll/ss setup to work correctly in some cases */
2507         atombios_set_encoder_crtc_source(encoder);
2508         /* set up the FMT blocks */
2509         if (ASIC_IS_DCE8(rdev))
2510                 dce8_program_fmt(encoder);
2511         else if (ASIC_IS_DCE4(rdev))
2512                 dce4_program_fmt(encoder);
2513         else if (ASIC_IS_DCE3(rdev))
2514                 dce3_program_fmt(encoder);
2515         else if (ASIC_IS_AVIVO(rdev))
2516                 avivo_program_fmt(encoder);
2517 }
2518
2519 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2520 {
2521         /* need to call this here as we need the crtc set up */
2522         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2523         radeon_atom_output_lock(encoder, false);
2524 }
2525
2526 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2527 {
2528         struct drm_device *dev = encoder->dev;
2529         struct radeon_device *rdev = dev->dev_private;
2530         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2531         struct radeon_encoder_atom_dig *dig;
2532
2533         /* check for pre-DCE3 cards with shared encoders;
2534          * can't really use the links individually, so don't disable
2535          * the encoder if it's in use by another connector
2536          */
2537         if (!ASIC_IS_DCE3(rdev)) {
2538                 struct drm_encoder *other_encoder;
2539                 struct radeon_encoder *other_radeon_encoder;
2540
2541                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2542                         other_radeon_encoder = to_radeon_encoder(other_encoder);
2543                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2544                             drm_helper_encoder_in_use(other_encoder))
2545                                 goto disable_done;
2546                 }
2547         }
2548
2549         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2550
2551         switch (radeon_encoder->encoder_id) {
2552         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2553         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2554         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2555         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2556                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2557                 break;
2558         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2559         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2560         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2561         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2562         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2563                 /* handled in dpms */
2564                 break;
2565         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2566         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2567         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2568                 atombios_dvo_setup(encoder, ATOM_DISABLE);
2569                 break;
2570         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2571         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2572         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2573         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2574                 atombios_dac_setup(encoder, ATOM_DISABLE);
2575                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2576                         atombios_tv_setup(encoder, ATOM_DISABLE);
2577                 break;
2578         }
2579
2580 disable_done:
2581         if (radeon_encoder_is_digital(encoder)) {
2582                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2583                         if (rdev->asic->display.hdmi_enable)
2584                                 radeon_hdmi_enable(rdev, encoder, false);
2585                 }
2586                 if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST) {
2587                         dig = radeon_encoder->enc_priv;
2588                         radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2589                         dig->dig_encoder = -1;
2590                         radeon_encoder->active_device = 0;
2591                 }
2592         } else
2593                 radeon_encoder->active_device = 0;
2594 }
2595
2596 /* these are handled by the primary encoders */
2597 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2598 {
2599
2600 }
2601
2602 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2603 {
2604
2605 }
2606
2607 static void
2608 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2609                          struct drm_display_mode *mode,
2610                          struct drm_display_mode *adjusted_mode)
2611 {
2612
2613 }
2614
2615 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2616 {
2617
2618 }
2619
2620 static void
2621 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2622 {
2623
2624 }
2625
2626 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2627                                        const struct drm_display_mode *mode,
2628                                        struct drm_display_mode *adjusted_mode)
2629 {
2630         return true;
2631 }
2632
2633 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2634         .dpms = radeon_atom_ext_dpms,
2635         .mode_fixup = radeon_atom_ext_mode_fixup,
2636         .prepare = radeon_atom_ext_prepare,
2637         .mode_set = radeon_atom_ext_mode_set,
2638         .commit = radeon_atom_ext_commit,
2639         .disable = radeon_atom_ext_disable,
2640         /* no detect for TMDS/LVDS yet */
2641 };
2642
2643 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2644         .dpms = radeon_atom_encoder_dpms,
2645         .mode_fixup = radeon_atom_mode_fixup,
2646         .prepare = radeon_atom_encoder_prepare,
2647         .mode_set = radeon_atom_encoder_mode_set,
2648         .commit = radeon_atom_encoder_commit,
2649         .disable = radeon_atom_encoder_disable,
2650         .detect = radeon_atom_dig_detect,
2651 };
2652
2653 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2654         .dpms = radeon_atom_encoder_dpms,
2655         .mode_fixup = radeon_atom_mode_fixup,
2656         .prepare = radeon_atom_encoder_prepare,
2657         .mode_set = radeon_atom_encoder_mode_set,
2658         .commit = radeon_atom_encoder_commit,
2659         .detect = radeon_atom_dac_detect,
2660 };
2661
2662 void radeon_enc_destroy(struct drm_encoder *encoder)
2663 {
2664         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2665         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2666                 radeon_atom_backlight_exit(radeon_encoder);
2667         kfree(radeon_encoder->enc_priv);
2668         drm_encoder_cleanup(encoder);
2669         kfree(radeon_encoder);
2670 }
2671
2672 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2673         .destroy = radeon_enc_destroy,
2674 };
2675
2676 static struct radeon_encoder_atom_dac *
2677 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2678 {
2679         struct drm_device *dev = radeon_encoder->base.dev;
2680         struct radeon_device *rdev = dev->dev_private;
2681         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2682
2683         if (!dac)
2684                 return NULL;
2685
2686         dac->tv_std = radeon_atombios_get_tv_info(rdev);
2687         return dac;
2688 }
2689
2690 static struct radeon_encoder_atom_dig *
2691 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2692 {
2693         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2694         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2695
2696         if (!dig)
2697                 return NULL;
2698
2699         /* coherent mode by default */
2700         dig->coherent_mode = true;
2701         dig->dig_encoder = -1;
2702
2703         if (encoder_enum == 2)
2704                 dig->linkb = true;
2705         else
2706                 dig->linkb = false;
2707
2708         return dig;
2709 }
2710
2711 void
2712 radeon_add_atom_encoder(struct drm_device *dev,
2713                         uint32_t encoder_enum,
2714                         uint32_t supported_device,
2715                         u16 caps)
2716 {
2717         struct radeon_device *rdev = dev->dev_private;
2718         struct drm_encoder *encoder;
2719         struct radeon_encoder *radeon_encoder;
2720
2721         /* see if we already added it */
2722         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2723                 radeon_encoder = to_radeon_encoder(encoder);
2724                 if (radeon_encoder->encoder_enum == encoder_enum) {
2725                         radeon_encoder->devices |= supported_device;
2726                         return;
2727                 }
2728
2729         }
2730
2731         /* add a new one */
2732         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2733         if (!radeon_encoder)
2734                 return;
2735
2736         encoder = &radeon_encoder->base;
2737         switch (rdev->num_crtc) {
2738         case 1:
2739                 encoder->possible_crtcs = 0x1;
2740                 break;
2741         case 2:
2742         default:
2743                 encoder->possible_crtcs = 0x3;
2744                 break;
2745         case 4:
2746                 encoder->possible_crtcs = 0xf;
2747                 break;
2748         case 6:
2749                 encoder->possible_crtcs = 0x3f;
2750                 break;
2751         }
2752
2753         radeon_encoder->enc_priv = NULL;
2754
2755         radeon_encoder->encoder_enum = encoder_enum;
2756         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2757         radeon_encoder->devices = supported_device;
2758         radeon_encoder->rmx_type = RMX_OFF;
2759         radeon_encoder->underscan_type = UNDERSCAN_OFF;
2760         radeon_encoder->is_ext_encoder = false;
2761         radeon_encoder->caps = caps;
2762
2763         switch (radeon_encoder->encoder_id) {
2764         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2765         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2766         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2767         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2768                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2769                         radeon_encoder->rmx_type = RMX_FULL;
2770                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2771                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2772                 } else {
2773                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2774                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2775                 }
2776                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2777                 break;
2778         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2779                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2780                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2781                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2782                 break;
2783         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2784         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2785         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2786                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2787                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2788                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2789                 break;
2790         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2791         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2792         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2793         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2794         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2795         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2796         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2797         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2798                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2799                         radeon_encoder->rmx_type = RMX_FULL;
2800                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2801                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2802                 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2803                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2804                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2805                 } else {
2806                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2807                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2808                 }
2809                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2810                 break;
2811         case ENCODER_OBJECT_ID_SI170B:
2812         case ENCODER_OBJECT_ID_CH7303:
2813         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2814         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2815         case ENCODER_OBJECT_ID_TITFP513:
2816         case ENCODER_OBJECT_ID_VT1623:
2817         case ENCODER_OBJECT_ID_HDMI_SI1930:
2818         case ENCODER_OBJECT_ID_TRAVIS:
2819         case ENCODER_OBJECT_ID_NUTMEG:
2820                 /* these are handled by the primary encoders */
2821                 radeon_encoder->is_ext_encoder = true;
2822                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2823                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2824                 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2825                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2826                 else
2827                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2828                 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2829                 break;
2830         }
2831 }