drivers/gpu/drm/tegra/dc.c

   1 /*
   2  * Copyright (C) 2012 Avionic Design GmbH
   3  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/debugfs.h>
  12 #include <linux/iommu.h>
  13 #include <linux/reset.h>
  14
  15 #include <soc/tegra/pmc.h>
  16
  17 #include "dc.h"
  18 #include "drm.h"
  19 #include "gem.h"
  20
  21 #include <drm/drm_atomic.h>
  22 #include <drm/drm_atomic_helper.h>
  23 #include <drm/drm_plane_helper.h>
  24
  25 struct tegra_dc_soc_info {
  26         bool supports_border_color;
  27         bool supports_interlacing;
  28         bool supports_cursor;
  29         bool supports_block_linear;
  30         unsigned int pitch_align;
  31         bool has_powergate;
  32 };
  33
  34 struct tegra_plane {
  35         struct drm_plane base;
  36         unsigned int index;
  37 };
  38
  39 static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
  40 {
  41         return container_of(plane, struct tegra_plane, base);
  42 }
  43
  44 struct tegra_dc_state {
  45         struct drm_crtc_state base;
  46
  47         struct clk *clk;
  48         unsigned long pclk;
  49         unsigned int div;
  50
  51         u32 planes;
  52 };
  53
  54 static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state)
  55 {
  56         if (state)
  57                 return container_of(state, struct tegra_dc_state, base);
  58
  59         return NULL;
  60 }
  61
  62 struct tegra_plane_state {
  63         struct drm_plane_state base;
  64
  65         struct tegra_bo_tiling tiling;
  66         u32 format;
  67         u32 swap;
  68 };
  69
  70 static inline struct tegra_plane_state *
  71 to_tegra_plane_state(struct drm_plane_state *state)
  72 {
  73         if (state)
  74                 return container_of(state, struct tegra_plane_state, base);
  75
  76         return NULL;
  77 }
  78
  79 static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
  80 {
  81         stats->frames = 0;
  82         stats->vblank = 0;
  83         stats->underflow = 0;
  84         stats->overflow = 0;
  85 }
  86
  87 /*
  88  * Reads the active copy of a register. This takes the dc->lock spinlock to
  89  * prevent races with the VBLANK processing which also needs access to the
  90  * active copy of some registers.
  91  */
  92 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
  93 {
  94         unsigned long flags;
  95         u32 value;
  96
  97         spin_lock_irqsave(&dc->lock, flags);
  98
  99         tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
 100         value = tegra_dc_readl(dc, offset);
 101         tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
 102
 103         spin_unlock_irqrestore(&dc->lock, flags);
 104         return value;
 105 }
 106
 107 /*
 108  * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
 109  * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
 110  * Latching happens mmediately if the display controller is in STOP mode or
 111  * on the next frame boundary otherwise.
 112  *
 113  * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
 114  * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
 115  * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
 116  * into the ACTIVE copy, either immediately if the display controller is in
 117  * STOP mode, or at the next frame boundary otherwise.
 118  */
 119 void tegra_dc_commit(struct tegra_dc *dc)
 120 {
 121         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
 122         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
 123 }
 124
 125 static int tegra_dc_format(u32 fourcc, u32 *format, u32 *swap)
 126 {
 127         /* assume no swapping of fetched data */
 128         if (swap)
 129                 *swap = BYTE_SWAP_NOSWAP;
 130
 131         switch (fourcc) {
 132         case DRM_FORMAT_XBGR8888:
 133                 *format = WIN_COLOR_DEPTH_R8G8B8A8;
 134                 break;
 135
 136         case DRM_FORMAT_XRGB8888:
 137                 *format = WIN_COLOR_DEPTH_B8G8R8A8;
 138                 break;
 139
 140         case DRM_FORMAT_RGB565:
 141                 *format = WIN_COLOR_DEPTH_B5G6R5;
 142                 break;
 143
 144         case DRM_FORMAT_UYVY:
 145                 *format = WIN_COLOR_DEPTH_YCbCr422;
 146                 break;
 147
 148         case DRM_FORMAT_YUYV:
 149                 if (swap)
 150                         *swap = BYTE_SWAP_SWAP2;
 151
 152                 *format = WIN_COLOR_DEPTH_YCbCr422;
 153                 break;
 154
 155         case DRM_FORMAT_YUV420:
 156                 *format = WIN_COLOR_DEPTH_YCbCr420P;
 157                 break;
 158
 159         case DRM_FORMAT_YUV422:
 160                 *format = WIN_COLOR_DEPTH_YCbCr422P;
 161                 break;
 162
 163         default:
 164                 return -EINVAL;
 165         }
 166
 167         return 0;
 168 }
 169
 170 static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
 171 {
 172         switch (format) {
 173         case WIN_COLOR_DEPTH_YCbCr422:
 174         case WIN_COLOR_DEPTH_YUV422:
 175                 if (planar)
 176                         *planar = false;
 177
 178                 return true;
 179
 180         case WIN_COLOR_DEPTH_YCbCr420P:
 181         case WIN_COLOR_DEPTH_YUV420P:
 182         case WIN_COLOR_DEPTH_YCbCr422P:
 183         case WIN_COLOR_DEPTH_YUV422P:
 184         case WIN_COLOR_DEPTH_YCbCr422R:
 185         case WIN_COLOR_DEPTH_YUV422R:
 186         case WIN_COLOR_DEPTH_YCbCr422RA:
 187         case WIN_COLOR_DEPTH_YUV422RA:
 188                 if (planar)
 189                         *planar = true;
 190
 191                 return true;
 192         }
 193
 194         if (planar)
 195                 *planar = false;
 196
 197         return false;
 198 }
 199
 200 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
 201                                   unsigned int bpp)
 202 {
 203         fixed20_12 outf = dfixed_init(out);
 204         fixed20_12 inf = dfixed_init(in);
 205         u32 dda_inc;
 206         int max;
 207
 208         if (v)
 209                 max = 15;
 210         else {
 211                 switch (bpp) {
 212                 case 2:
 213                         max = 8;
 214                         break;
 215
 216                 default:
 217                         WARN_ON_ONCE(1);
 218                         /* fallthrough */
 219                 case 4:
 220                         max = 4;
 221                         break;
 222                 }
 223         }
 224
 225         outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
 226         inf.full -= dfixed_const(1);
 227
 228         dda_inc = dfixed_div(inf, outf);
 229         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
 230
 231         return dda_inc;
 232 }
 233
 234 static inline u32 compute_initial_dda(unsigned int in)
 235 {
 236         fixed20_12 inf = dfixed_init(in);
 237         return dfixed_frac(inf);
 238 }
 239
 240 static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
 241                                   const struct tegra_dc_window *window)
 242 {
 243         unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
 244         unsigned long value, flags;
 245         bool yuv, planar;
 246
 247         /*
 248          * For YUV planar modes, the number of bytes per pixel takes into
 249          * account only the luma component and therefore is 1.
 250          */
 251         yuv = tegra_dc_format_is_yuv(window->format, &planar);
 252         if (!yuv)
 253                 bpp = window->bits_per_pixel / 8;
 254         else
 255                 bpp = planar ? 1 : 2;
 256
 257         spin_lock_irqsave(&dc->lock, flags);
 258
 259         value = WINDOW_A_SELECT << index;
 260         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
 261
 262         tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
 263         tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
 264
 265         value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
 266         tegra_dc_writel(dc, value, DC_WIN_POSITION);
 267
 268         value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
 269         tegra_dc_writel(dc, value, DC_WIN_SIZE);
 270
 271         h_offset = window->src.x * bpp;
 272         v_offset = window->src.y;
 273         h_size = window->src.w * bpp;
 274         v_size = window->src.h;
 275
 276         value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
 277         tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
 278
 279         /*
 280          * For DDA computations the number of bytes per pixel for YUV planar
 281          * modes needs to take into account all Y, U and V components.
 282          */
 283         if (yuv && planar)
 284                 bpp = 2;
 285
 286         h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
 287         v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
 288
 289         value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
 290         tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
 291
 292         h_dda = compute_initial_dda(window->src.x);
 293         v_dda = compute_initial_dda(window->src.y);
 294
 295         tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
 296         tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
 297
 298         tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
 299         tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
 300
 301         tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
 302
 303         if (yuv && planar) {
 304                 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
 305                 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
 306                 value = window->stride[1] << 16 | window->stride[0];
 307                 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
 308         } else {
 309                 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
 310         }
 311
 312         if (window->bottom_up)
 313                 v_offset += window->src.h - 1;
 314
 315         tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
 316         tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
 317
 318         if (dc->soc->supports_block_linear) {
 319                 unsigned long height = window->tiling.value;
 320
 321                 switch (window->tiling.mode) {
 322                 case TEGRA_BO_TILING_MODE_PITCH:
 323                         value = DC_WINBUF_SURFACE_KIND_PITCH;
 324                         break;
 325
 326                 case TEGRA_BO_TILING_MODE_TILED:
 327                         value = DC_WINBUF_SURFACE_KIND_TILED;
 328                         break;
 329
 330                 case TEGRA_BO_TILING_MODE_BLOCK:
 331                         value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
 332                                 DC_WINBUF_SURFACE_KIND_BLOCK;
 333                         break;
 334                 }
 335
 336                 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
 337         } else {
 338                 switch (window->tiling.mode) {
 339                 case TEGRA_BO_TILING_MODE_PITCH:
 340                         value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
 341                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
 342                         break;
 343
 344                 case TEGRA_BO_TILING_MODE_TILED:
 345                         value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
 346                                 DC_WIN_BUFFER_ADDR_MODE_TILE;
 347                         break;
 348
 349                 case TEGRA_BO_TILING_MODE_BLOCK:
 350                         /*
 351                          * No need to handle this here because ->atomic_check
 352                          * will already have filtered it out.
 353                          */
 354                         break;
 355                 }
 356
 357                 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
 358         }
 359
 360         value = WIN_ENABLE;
 361
 362         if (yuv) {
 363                 /* setup default colorspace conversion coefficients */
 364                 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
 365                 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
 366                 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
 367                 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
 368                 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
 369                 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
 370                 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
 371                 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
 372
 373                 value |= CSC_ENABLE;
 374         } else if (window->bits_per_pixel < 24) {
 375                 value |= COLOR_EXPAND;
 376         }
 377
 378         if (window->bottom_up)
 379                 value |= V_DIRECTION;
 380
 381         tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
 382
 383         /*
 384          * Disable blending and assume Window A is the bottom-most window,
 385          * Window C is the top-most window and Window B is in the middle.
 386          */
 387         tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
 388         tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
 389
 390         switch (index) {
 391         case 0:
 392                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
 393                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
 394                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
 395                 break;
 396
 397         case 1:
 398                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
 399                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
 400                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
 401                 break;
 402
 403         case 2:
 404                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
 405                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
 406                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
 407                 break;
 408         }
 409
 410         spin_unlock_irqrestore(&dc->lock, flags);
 411 }
 412
 413 static void tegra_plane_destroy(struct drm_plane *plane)
 414 {
 415         struct tegra_plane *p = to_tegra_plane(plane);
 416
 417         drm_plane_cleanup(plane);
 418         kfree(p);
 419 }
 420
 421 static const u32 tegra_primary_plane_formats[] = {
 422         DRM_FORMAT_XBGR8888,
 423         DRM_FORMAT_XRGB8888,
 424         DRM_FORMAT_RGB565,
 425 };
 426
 427 static void tegra_primary_plane_destroy(struct drm_plane *plane)
 428 {
 429         tegra_plane_destroy(plane);
 430 }
 431
 432 static void tegra_plane_reset(struct drm_plane *plane)
 433 {
 434         struct tegra_plane_state *state;
 435
 436         if (plane->state)
 437                 __drm_atomic_helper_plane_destroy_state(plane, plane->state);
 438
 439         kfree(plane->state);
 440         plane->state = NULL;
 441
 442         state = kzalloc(sizeof(*state), GFP_KERNEL);
 443         if (state) {
 444                 plane->state = &state->base;
 445                 plane->state->plane = plane;
 446         }
 447 }
 448
 449 static struct drm_plane_state *tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
 450 {
 451         struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
 452         struct tegra_plane_state *copy;
 453
 454         copy = kmalloc(sizeof(*copy), GFP_KERNEL);
 455         if (!copy)
 456                 return NULL;
 457
 458         __drm_atomic_helper_plane_duplicate_state(plane, &copy->base);
 459         copy->tiling = state->tiling;
 460         copy->format = state->format;
 461         copy->swap = state->swap;
 462
 463         return &copy->base;
 464 }
 465
 466 static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
 467                                              struct drm_plane_state *state)
 468 {
 469         __drm_atomic_helper_plane_destroy_state(plane, state);
 470         kfree(state);
 471 }
 472
 473 static const struct drm_plane_funcs tegra_primary_plane_funcs = {
 474         .update_plane = drm_atomic_helper_update_plane,
 475         .disable_plane = drm_atomic_helper_disable_plane,
 476         .destroy = tegra_primary_plane_destroy,
 477         .reset = tegra_plane_reset,
 478         .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
 479         .atomic_destroy_state = tegra_plane_atomic_destroy_state,
 480 };
 481
 482 static int tegra_plane_prepare_fb(struct drm_plane *plane,
 483                                   const struct drm_plane_state *new_state)
 484 {
 485         return 0;
 486 }
 487
 488 static void tegra_plane_cleanup_fb(struct drm_plane *plane,
 489                                    const struct drm_plane_state *old_fb)
 490 {
 491 }
 492
 493 static int tegra_plane_state_add(struct tegra_plane *plane,
 494                                  struct drm_plane_state *state)
 495 {
 496         struct drm_crtc_state *crtc_state;
 497         struct tegra_dc_state *tegra;
 498
 499         /* Propagate errors from allocation or locking failures. */
 500         crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
 501         if (IS_ERR(crtc_state))
 502                 return PTR_ERR(crtc_state);
 503
 504         tegra = to_dc_state(crtc_state);
 505
 506         tegra->planes |= WIN_A_ACT_REQ << plane->index;
 507
 508         return 0;
 509 }
 510
 511 static int tegra_plane_atomic_check(struct drm_plane *plane,
 512                                     struct drm_plane_state *state)
 513 {
 514         struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
 515         struct tegra_bo_tiling *tiling = &plane_state->tiling;
 516         struct tegra_plane *tegra = to_tegra_plane(plane);
 517         struct tegra_dc *dc = to_tegra_dc(state->crtc);
 518         int err;
 519
 520         /* no need for further checks if the plane is being disabled */
 521         if (!state->crtc)
 522                 return 0;
 523
 524         err = tegra_dc_format(state->fb->pixel_format, &plane_state->format,
 525                               &plane_state->swap);
 526         if (err < 0)
 527                 return err;
 528
 529         err = tegra_fb_get_tiling(state->fb, tiling);
 530         if (err < 0)
 531                 return err;
 532
 533         if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
 534             !dc->soc->supports_block_linear) {
 535                 DRM_ERROR("hardware doesn't support block linear mode\n");
 536                 return -EINVAL;
 537         }
 538
 539         /*
 540          * Tegra doesn't support different strides for U and V planes so we
 541          * error out if the user tries to display a framebuffer with such a
 542          * configuration.
 543          */
 544         if (drm_format_num_planes(state->fb->pixel_format) > 2) {
 545                 if (state->fb->pitches[2] != state->fb->pitches[1]) {
 546                         DRM_ERROR("unsupported UV-plane configuration\n");
 547                         return -EINVAL;
 548                 }
 549         }
 550
 551         err = tegra_plane_state_add(tegra, state);
 552         if (err < 0)
 553                 return err;
 554
 555         return 0;
 556 }
 557
 558 static void tegra_plane_atomic_update(struct drm_plane *plane,
 559                                       struct drm_plane_state *old_state)
 560 {
 561         struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
 562         struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
 563         struct drm_framebuffer *fb = plane->state->fb;
 564         struct tegra_plane *p = to_tegra_plane(plane);
 565         struct tegra_dc_window window;
 566         unsigned int i;
 567
 568         /* rien ne va plus */
 569         if (!plane->state->crtc || !plane->state->fb)
 570                 return;
 571
 572         memset(&window, 0, sizeof(window));
 573         window.src.x = plane->state->src_x >> 16;
 574         window.src.y = plane->state->src_y >> 16;
 575         window.src.w = plane->state->src_w >> 16;
 576         window.src.h = plane->state->src_h >> 16;
 577         window.dst.x = plane->state->crtc_x;
 578         window.dst.y = plane->state->crtc_y;
 579         window.dst.w = plane->state->crtc_w;
 580         window.dst.h = plane->state->crtc_h;
 581         window.bits_per_pixel = fb->bits_per_pixel;
 582         window.bottom_up = tegra_fb_is_bottom_up(fb);
 583
 584         /* copy from state */
 585         window.tiling = state->tiling;
 586         window.format = state->format;
 587         window.swap = state->swap;
 588
 589         for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
 590                 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
 591
 592                 window.base[i] = bo->paddr + fb->offsets[i];
 593                 window.stride[i] = fb->pitches[i];
 594         }
 595
 596         tegra_dc_setup_window(dc, p->index, &window);
 597 }
 598
 599 static void tegra_plane_atomic_disable(struct drm_plane *plane,
 600                                        struct drm_plane_state *old_state)
 601 {
 602         struct tegra_plane *p = to_tegra_plane(plane);
 603         struct tegra_dc *dc;
 604         unsigned long flags;
 605         u32 value;
 606
 607         /* rien ne va plus */
 608         if (!old_state || !old_state->crtc)
 609                 return;
 610
 611         dc = to_tegra_dc(old_state->crtc);
 612
 613         spin_lock_irqsave(&dc->lock, flags);
 614
 615         value = WINDOW_A_SELECT << p->index;
 616         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
 617
 618         value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
 619         value &= ~WIN_ENABLE;
 620         tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
 621
 622         spin_unlock_irqrestore(&dc->lock, flags);
 623 }
 624
 625 static const struct drm_plane_helper_funcs tegra_primary_plane_helper_funcs = {
 626         .prepare_fb = tegra_plane_prepare_fb,
 627         .cleanup_fb = tegra_plane_cleanup_fb,
 628         .atomic_check = tegra_plane_atomic_check,
 629         .atomic_update = tegra_plane_atomic_update,
 630         .atomic_disable = tegra_plane_atomic_disable,
 631 };
 632
 633 static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
 634                                                        struct tegra_dc *dc)
 635 {
 636         /*
 637          * Ideally this would use drm_crtc_mask(), but that would require the
 638          * CRTC to already be in the mode_config's list of CRTCs. However, it
 639          * will only be added to that list in the drm_crtc_init_with_planes()
 640          * (in tegra_dc_init()), which in turn requires registration of these
 641          * planes. So we have ourselves a nice little chicken and egg problem
 642          * here.
 643          *
 644          * We work around this by manually creating the mask from the number
 645          * of CRTCs that have been registered, and should therefore always be
 646          * the same as drm_crtc_index() after registration.
 647          */
 648         unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc;
 649         struct tegra_plane *plane;
 650         unsigned int num_formats;
 651         const u32 *formats;
 652         int err;
 653
 654         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 655         if (!plane)
 656                 return ERR_PTR(-ENOMEM);
 657
 658         num_formats = ARRAY_SIZE(tegra_primary_plane_formats);
 659         formats = tegra_primary_plane_formats;
 660
 661         err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
 662                                        &tegra_primary_plane_funcs, formats,
 663                                        num_formats, DRM_PLANE_TYPE_PRIMARY);
 664         if (err < 0) {
 665                 kfree(plane);
 666                 return ERR_PTR(err);
 667         }
 668
 669         drm_plane_helper_add(&plane->base, &tegra_primary_plane_helper_funcs);
 670
 671         return &plane->base;
 672 }
 673
 674 static const u32 tegra_cursor_plane_formats[] = {
 675         DRM_FORMAT_RGBA8888,
 676 };
 677
 678 static int tegra_cursor_atomic_check(struct drm_plane *plane,
 679                                      struct drm_plane_state *state)
 680 {
 681         struct tegra_plane *tegra = to_tegra_plane(plane);
 682         int err;
 683
 684         /* no need for further checks if the plane is being disabled */
 685         if (!state->crtc)
 686                 return 0;
 687
 688         /* scaling not supported for cursor */
 689         if ((state->src_w >> 16 != state->crtc_w) ||
 690             (state->src_h >> 16 != state->crtc_h))
 691                 return -EINVAL;
 692
 693         /* only square cursors supported */
 694         if (state->src_w != state->src_h)
 695                 return -EINVAL;
 696
 697         if (state->crtc_w != 32 && state->crtc_w != 64 &&
 698             state->crtc_w != 128 && state->crtc_w != 256)
 699                 return -EINVAL;
 700
 701         err = tegra_plane_state_add(tegra, state);
 702         if (err < 0)
 703                 return err;
 704
 705         return 0;
 706 }
 707
 708 static void tegra_cursor_atomic_update(struct drm_plane *plane,
 709                                        struct drm_plane_state *old_state)
 710 {
 711         struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
 712         struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
 713         struct drm_plane_state *state = plane->state;
 714         u32 value = CURSOR_CLIP_DISPLAY;
 715
 716         /* rien ne va plus */
 717         if (!plane->state->crtc || !plane->state->fb)
 718                 return;
 719
 720         switch (state->crtc_w) {
 721         case 32:
 722                 value |= CURSOR_SIZE_32x32;
 723                 break;
 724
 725         case 64:
 726                 value |= CURSOR_SIZE_64x64;
 727                 break;
 728
 729         case 128:
 730                 value |= CURSOR_SIZE_128x128;
 731                 break;
 732
 733         case 256:
 734                 value |= CURSOR_SIZE_256x256;
 735                 break;
 736
 737         default:
 738                 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
 739                      state->crtc_h);
 740                 return;
 741         }
 742
 743         value |= (bo->paddr >> 10) & 0x3fffff;
 744         tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
 745
 746 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
 747         value = (bo->paddr >> 32) & 0x3;
 748         tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
 749 #endif
 750
 751         /* enable cursor and set blend mode */
 752         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
 753         value |= CURSOR_ENABLE;
 754         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 755
 756         value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
 757         value &= ~CURSOR_DST_BLEND_MASK;
 758         value &= ~CURSOR_SRC_BLEND_MASK;
 759         value |= CURSOR_MODE_NORMAL;
 760         value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
 761         value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
 762         value |= CURSOR_ALPHA;
 763         tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
 764
 765         /* position the cursor */
 766         value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
 767         tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
 768 }
 769
 770 static void tegra_cursor_atomic_disable(struct drm_plane *plane,
 771                                         struct drm_plane_state *old_state)
 772 {
 773         struct tegra_dc *dc;
 774         u32 value;
 775
 776         /* rien ne va plus */
 777         if (!old_state || !old_state->crtc)
 778                 return;
 779
 780         dc = to_tegra_dc(old_state->crtc);
 781
 782         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
 783         value &= ~CURSOR_ENABLE;
 784         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 785 }
 786
 787 static const struct drm_plane_funcs tegra_cursor_plane_funcs = {
 788         .update_plane = drm_atomic_helper_update_plane,
 789         .disable_plane = drm_atomic_helper_disable_plane,
 790         .destroy = tegra_plane_destroy,
 791         .reset = tegra_plane_reset,
 792         .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
 793         .atomic_destroy_state = tegra_plane_atomic_destroy_state,
 794 };
 795
 796 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
 797         .prepare_fb = tegra_plane_prepare_fb,
 798         .cleanup_fb = tegra_plane_cleanup_fb,
 799         .atomic_check = tegra_cursor_atomic_check,
 800         .atomic_update = tegra_cursor_atomic_update,
 801         .atomic_disable = tegra_cursor_atomic_disable,
 802 };
 803
 804 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
 805                                                       struct tegra_dc *dc)
 806 {
 807         struct tegra_plane *plane;
 808         unsigned int num_formats;
 809         const u32 *formats;
 810         int err;
 811
 812         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 813         if (!plane)
 814                 return ERR_PTR(-ENOMEM);
 815
 816         /*
 817          * This index is kind of fake. The cursor isn't a regular plane, but
 818          * its update and activation request bits in DC_CMD_STATE_CONTROL do
 819          * use the same programming. Setting this fake index here allows the
 820          * code in tegra_add_plane_state() to do the right thing without the
 821          * need to special-casing the cursor plane.
 822          */
 823         plane->index = 6;
 824
 825         num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
 826         formats = tegra_cursor_plane_formats;
 827
 828         err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
 829                                        &tegra_cursor_plane_funcs, formats,
 830                                        num_formats, DRM_PLANE_TYPE_CURSOR);
 831         if (err < 0) {
 832                 kfree(plane);
 833                 return ERR_PTR(err);
 834         }
 835
 836         drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
 837
 838         return &plane->base;
 839 }
 840
 841 static void tegra_overlay_plane_destroy(struct drm_plane *plane)
 842 {
 843         tegra_plane_destroy(plane);
 844 }
 845
 846 static const struct drm_plane_funcs tegra_overlay_plane_funcs = {
 847         .update_plane = drm_atomic_helper_update_plane,
 848         .disable_plane = drm_atomic_helper_disable_plane,
 849         .destroy = tegra_overlay_plane_destroy,
 850         .reset = tegra_plane_reset,
 851         .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
 852         .atomic_destroy_state = tegra_plane_atomic_destroy_state,
 853 };
 854
 855 static const uint32_t tegra_overlay_plane_formats[] = {
 856         DRM_FORMAT_XBGR8888,
 857         DRM_FORMAT_XRGB8888,
 858         DRM_FORMAT_RGB565,
 859         DRM_FORMAT_UYVY,
 860         DRM_FORMAT_YUYV,
 861         DRM_FORMAT_YUV420,
 862         DRM_FORMAT_YUV422,
 863 };
 864
 865 static const struct drm_plane_helper_funcs tegra_overlay_plane_helper_funcs = {
 866         .prepare_fb = tegra_plane_prepare_fb,
 867         .cleanup_fb = tegra_plane_cleanup_fb,
 868         .atomic_check = tegra_plane_atomic_check,
 869         .atomic_update = tegra_plane_atomic_update,
 870         .atomic_disable = tegra_plane_atomic_disable,
 871 };
 872
 873 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
 874                                                        struct tegra_dc *dc,
 875                                                        unsigned int index)
 876 {
 877         struct tegra_plane *plane;
 878         unsigned int num_formats;
 879         const u32 *formats;
 880         int err;
 881
 882         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 883         if (!plane)
 884                 return ERR_PTR(-ENOMEM);
 885
 886         plane->index = index;
 887
 888         num_formats = ARRAY_SIZE(tegra_overlay_plane_formats);
 889         formats = tegra_overlay_plane_formats;
 890
 891         err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
 892                                        &tegra_overlay_plane_funcs, formats,
 893                                        num_formats, DRM_PLANE_TYPE_OVERLAY);
 894         if (err < 0) {
 895                 kfree(plane);
 896                 return ERR_PTR(err);
 897         }
 898
 899         drm_plane_helper_add(&plane->base, &tegra_overlay_plane_helper_funcs);
 900
 901         return &plane->base;
 902 }
 903
 904 static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
 905 {
 906         struct drm_plane *plane;
 907         unsigned int i;
 908
 909         for (i = 0; i < 2; i++) {
 910                 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
 911                 if (IS_ERR(plane))
 912                         return PTR_ERR(plane);
 913         }
 914
 915         return 0;
 916 }
 917
 918 u32 tegra_dc_get_vblank_counter(struct tegra_dc *dc)
 919 {
 920         if (dc->syncpt)
 921                 return host1x_syncpt_read(dc->syncpt);
 922
 923         /* fallback to software emulated VBLANK counter */
 924         return drm_crtc_vblank_count(&dc->base);
 925 }
 926
 927 void tegra_dc_enable_vblank(struct tegra_dc *dc)
 928 {
 929         unsigned long value, flags;
 930
 931         spin_lock_irqsave(&dc->lock, flags);
 932
 933         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
 934         value |= VBLANK_INT;
 935         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
 936
 937         spin_unlock_irqrestore(&dc->lock, flags);
 938 }
 939
 940 void tegra_dc_disable_vblank(struct tegra_dc *dc)
 941 {
 942         unsigned long value, flags;
 943
 944         spin_lock_irqsave(&dc->lock, flags);
 945
 946         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
 947         value &= ~VBLANK_INT;
 948         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
 949
 950         spin_unlock_irqrestore(&dc->lock, flags);
 951 }
 952
 953 static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
 954 {
 955         struct drm_device *drm = dc->base.dev;
 956         struct drm_crtc *crtc = &dc->base;
 957         unsigned long flags, base;
 958         struct tegra_bo *bo;
 959
 960         spin_lock_irqsave(&drm->event_lock, flags);
 961
 962         if (!dc->event) {
 963                 spin_unlock_irqrestore(&drm->event_lock, flags);
 964                 return;
 965         }
 966
 967         bo = tegra_fb_get_plane(crtc->primary->fb, 0);
 968
 969         spin_lock(&dc->lock);
 970
 971         /* check if new start address has been latched */
 972         tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
 973         tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
 974         base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
 975         tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
 976
 977         spin_unlock(&dc->lock);
 978
 979         if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
 980                 drm_crtc_send_vblank_event(crtc, dc->event);
 981                 drm_crtc_vblank_put(crtc);
 982                 dc->event = NULL;
 983         }
 984
 985         spin_unlock_irqrestore(&drm->event_lock, flags);
 986 }
 987
 988 void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
 989 {
 990         struct tegra_dc *dc = to_tegra_dc(crtc);
 991         struct drm_device *drm = crtc->dev;
 992         unsigned long flags;
 993
 994         spin_lock_irqsave(&drm->event_lock, flags);
 995
 996         if (dc->event && dc->event->base.file_priv == file) {
 997                 dc->event->base.destroy(&dc->event->base);
 998                 drm_crtc_vblank_put(crtc);
 999                 dc->event = NULL;
1000         }
1001
1002         spin_unlock_irqrestore(&drm->event_lock, flags);
1003 }
1004
1005 static void tegra_dc_destroy(struct drm_crtc *crtc)
1006 {
1007         drm_crtc_cleanup(crtc);
1008 }
1009
1010 static void tegra_crtc_reset(struct drm_crtc *crtc)
1011 {
1012         struct tegra_dc_state *state;
1013
1014         if (crtc->state)
1015                 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
1016
1017         kfree(crtc->state);
1018         crtc->state = NULL;
1019
1020         state = kzalloc(sizeof(*state), GFP_KERNEL);
1021         if (state) {
1022                 crtc->state = &state->base;
1023                 crtc->state->crtc = crtc;
1024         }
1025
1026         drm_crtc_vblank_reset(crtc);
1027 }
1028
1029 static struct drm_crtc_state *
1030 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1031 {
1032         struct tegra_dc_state *state = to_dc_state(crtc->state);
1033         struct tegra_dc_state *copy;
1034
1035         copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1036         if (!copy)
1037                 return NULL;
1038
1039         __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->base);
1040         copy->clk = state->clk;
1041         copy->pclk = state->pclk;
1042         copy->div = state->div;
1043         copy->planes = state->planes;
1044
1045         return &copy->base;
1046 }
1047
1048 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1049                                             struct drm_crtc_state *state)
1050 {
1051         __drm_atomic_helper_crtc_destroy_state(crtc, state);
1052         kfree(state);
1053 }
1054
1055 static const struct drm_crtc_funcs tegra_crtc_funcs = {
1056         .page_flip = drm_atomic_helper_page_flip,
1057         .set_config = drm_atomic_helper_set_config,
1058         .destroy = tegra_dc_destroy,
1059         .reset = tegra_crtc_reset,
1060         .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1061         .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1062 };
1063
1064 static int tegra_dc_set_timings(struct tegra_dc *dc,
1065                                 struct drm_display_mode *mode)
1066 {
1067         unsigned int h_ref_to_sync = 1;
1068         unsigned int v_ref_to_sync = 1;
1069         unsigned long value;
1070
1071         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1072
1073         value = (v_ref_to_sync << 16) | h_ref_to_sync;
1074         tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1075
1076         value = ((mode->vsync_end - mode->vsync_start) << 16) |
1077                 ((mode->hsync_end - mode->hsync_start) <<  0);
1078         tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1079
1080         value = ((mode->vtotal - mode->vsync_end) << 16) |
1081                 ((mode->htotal - mode->hsync_end) <<  0);
1082         tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1083
1084         value = ((mode->vsync_start - mode->vdisplay) << 16) |
1085                 ((mode->hsync_start - mode->hdisplay) <<  0);
1086         tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1087
1088         value = (mode->vdisplay << 16) | mode->hdisplay;
1089         tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1090
1091         return 0;
1092 }
1093
1094 /**
1095  * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1096  *     state
1097  * @dc: display controller
1098  * @crtc_state: CRTC atomic state
1099  * @clk: parent clock for display controller
1100  * @pclk: pixel clock
1101  * @div: shift clock divider
1102  *
1103  * Returns:
1104  * 0 on success or a negative error-code on failure.
1105  */
1106 int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1107                                struct drm_crtc_state *crtc_state,
1108                                struct clk *clk, unsigned long pclk,
1109                                unsigned int div)
1110 {
1111         struct tegra_dc_state *state = to_dc_state(crtc_state);
1112
1113         if (!clk_has_parent(dc->clk, clk))
1114                 return -EINVAL;
1115
1116         state->clk = clk;
1117         state->pclk = pclk;
1118         state->div = div;
1119
1120         return 0;
1121 }
1122
1123 static void tegra_dc_commit_state(struct tegra_dc *dc,
1124                                   struct tegra_dc_state *state)
1125 {
1126         u32 value;
1127         int err;
1128
1129         err = clk_set_parent(dc->clk, state->clk);
1130         if (err < 0)
1131                 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1132
1133         /*
1134          * Outputs may not want to change the parent clock rate. This is only
1135          * relevant to Tegra20 where only a single display PLL is available.
1136          * Since that PLL would typically be used for HDMI, an internal LVDS
1137          * panel would need to be driven by some other clock such as PLL_P
1138          * which is shared with other peripherals. Changing the clock rate
1139          * should therefore be avoided.
1140          */
1141         if (state->pclk > 0) {
1142                 err = clk_set_rate(state->clk, state->pclk);
1143                 if (err < 0)
1144                         dev_err(dc->dev,
1145                                 "failed to set clock rate to %lu Hz\n",
1146                                 state->pclk);
1147         }
1148
1149         DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1150                       state->div);
1151         DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1152
1153         value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1154         tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1155 }
1156
1157 static void tegra_dc_stop(struct tegra_dc *dc)
1158 {
1159         u32 value;
1160
1161         /* stop the display controller */
1162         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1163         value &= ~DISP_CTRL_MODE_MASK;
1164         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1165
1166         tegra_dc_commit(dc);
1167 }
1168
1169 static bool tegra_dc_idle(struct tegra_dc *dc)
1170 {
1171         u32 value;
1172
1173         value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1174
1175         return (value & DISP_CTRL_MODE_MASK) == 0;
1176 }
1177
1178 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1179 {
1180         timeout = jiffies + msecs_to_jiffies(timeout);
1181
1182         while (time_before(jiffies, timeout)) {
1183                 if (tegra_dc_idle(dc))
1184                         return 0;
1185
1186                 usleep_range(1000, 2000);
1187         }
1188
1189         dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1190         return -ETIMEDOUT;
1191 }
1192
1193 static void tegra_crtc_disable(struct drm_crtc *crtc)
1194 {
1195         struct tegra_dc *dc = to_tegra_dc(crtc);
1196         u32 value;
1197
1198         if (!tegra_dc_idle(dc)) {
1199                 tegra_dc_stop(dc);
1200
1201                 /*
1202                  * Ignore the return value, there isn't anything useful to do
1203                  * in case this fails.
1204                  */
1205                 tegra_dc_wait_idle(dc, 100);
1206         }
1207
1208         /*
1209          * This should really be part of the RGB encoder driver, but clearing
1210          * these bits has the side-effect of stopping the display controller.
1211          * When that happens no VBLANK interrupts will be raised. At the same
1212          * time the encoder is disabled before the display controller, so the
1213          * above code is always going to timeout waiting for the controller
1214          * to go idle.
1215          *
1216          * Given the close coupling between the RGB encoder and the display
1217          * controller doing it here is still kind of okay. None of the other
1218          * encoder drivers require these bits to be cleared.
1219          *
1220          * XXX: Perhaps given that the display controller is switched off at
1221          * this point anyway maybe clearing these bits isn't even useful for
1222          * the RGB encoder?
1223          */
1224         if (dc->rgb) {
1225                 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1226                 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1227                            PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1228                 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1229         }
1230
1231         tegra_dc_stats_reset(&dc->stats);
1232         drm_crtc_vblank_off(crtc);
1233 }
1234
1235 static void tegra_crtc_enable(struct drm_crtc *crtc)
1236 {
1237         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1238         struct tegra_dc_state *state = to_dc_state(crtc->state);
1239         struct tegra_dc *dc = to_tegra_dc(crtc);
1240         u32 value;
1241
1242         tegra_dc_commit_state(dc, state);
1243
1244         /* program display mode */
1245         tegra_dc_set_timings(dc, mode);
1246
1247         /* interlacing isn't supported yet, so disable it */
1248         if (dc->soc->supports_interlacing) {
1249                 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1250                 value &= ~INTERLACE_ENABLE;
1251                 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1252         }
1253
1254         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1255         value &= ~DISP_CTRL_MODE_MASK;
1256         value |= DISP_CTRL_MODE_C_DISPLAY;
1257         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1258
1259         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1260         value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1261                  PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1262         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1263
1264         tegra_dc_commit(dc);
1265
1266         drm_crtc_vblank_on(crtc);
1267 }
1268
1269 static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
1270                                    struct drm_crtc_state *state)
1271 {
1272         return 0;
1273 }
1274
1275 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1276                                     struct drm_crtc_state *old_crtc_state)
1277 {
1278         struct tegra_dc *dc = to_tegra_dc(crtc);
1279
1280         if (crtc->state->event) {
1281                 crtc->state->event->pipe = drm_crtc_index(crtc);
1282
1283                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1284
1285                 dc->event = crtc->state->event;
1286                 crtc->state->event = NULL;
1287         }
1288 }
1289
1290 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1291                                     struct drm_crtc_state *old_crtc_state)
1292 {
1293         struct tegra_dc_state *state = to_dc_state(crtc->state);
1294         struct tegra_dc *dc = to_tegra_dc(crtc);
1295
1296         tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL);
1297         tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL);
1298 }
1299
1300 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1301         .disable = tegra_crtc_disable,
1302         .enable = tegra_crtc_enable,
1303         .atomic_check = tegra_crtc_atomic_check,
1304         .atomic_begin = tegra_crtc_atomic_begin,
1305         .atomic_flush = tegra_crtc_atomic_flush,
1306 };
1307
1308 static irqreturn_t tegra_dc_irq(int irq, void *data)
1309 {
1310         struct tegra_dc *dc = data;
1311         unsigned long status;
1312
1313         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1314         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1315
1316         if (status & FRAME_END_INT) {
1317                 /*
1318                 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1319                 */
1320                 dc->stats.frames++;
1321         }
1322
1323         if (status & VBLANK_INT) {
1324                 /*
1325                 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1326                 */
1327                 drm_crtc_handle_vblank(&dc->base);
1328                 tegra_dc_finish_page_flip(dc);
1329                 dc->stats.vblank++;
1330         }
1331
1332         if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1333                 /*
1334                 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1335                 */
1336                 dc->stats.underflow++;
1337         }
1338
1339         if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1340                 /*
1341                 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1342                 */
1343                 dc->stats.overflow++;
1344         }
1345
1346         return IRQ_HANDLED;
1347 }
1348
1349 static int tegra_dc_show_regs(struct seq_file *s, void *data)
1350 {
1351         struct drm_info_node *node = s->private;
1352         struct tegra_dc *dc = node->info_ent->data;
1353         int err = 0;
1354
1355         drm_modeset_lock_crtc(&dc->base, NULL);
1356
1357         if (!dc->base.state->active) {
1358                 err = -EBUSY;
1359                 goto unlock;
1360         }
1361
1362 #define DUMP_REG(name)                                          \
1363         seq_printf(s, "%-40s %#05x %08x\n", #name, name,        \
1364                    tegra_dc_readl(dc, name))
1365
1366         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
1367         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1368         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
1369         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
1370         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
1371         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
1372         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
1373         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
1374         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
1375         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
1376         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
1377         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
1378         DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
1379         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
1380         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
1381         DUMP_REG(DC_CMD_SIGNAL_RAISE);
1382         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
1383         DUMP_REG(DC_CMD_INT_STATUS);
1384         DUMP_REG(DC_CMD_INT_MASK);
1385         DUMP_REG(DC_CMD_INT_ENABLE);
1386         DUMP_REG(DC_CMD_INT_TYPE);
1387         DUMP_REG(DC_CMD_INT_POLARITY);
1388         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
1389         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
1390         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
1391         DUMP_REG(DC_CMD_STATE_ACCESS);
1392         DUMP_REG(DC_CMD_STATE_CONTROL);
1393         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
1394         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
1395         DUMP_REG(DC_COM_CRC_CONTROL);
1396         DUMP_REG(DC_COM_CRC_CHECKSUM);
1397         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1398         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1399         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1400         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1401         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1402         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1403         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1404         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1405         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1406         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1407         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1408         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1409         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1410         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1411         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1412         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1413         DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1414         DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1415         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1416         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1417         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1418         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1419         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1420         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1421         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1422         DUMP_REG(DC_COM_PIN_MISC_CONTROL);
1423         DUMP_REG(DC_COM_PIN_PM0_CONTROL);
1424         DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
1425         DUMP_REG(DC_COM_PIN_PM1_CONTROL);
1426         DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
1427         DUMP_REG(DC_COM_SPI_CONTROL);
1428         DUMP_REG(DC_COM_SPI_START_BYTE);
1429         DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
1430         DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
1431         DUMP_REG(DC_COM_HSPI_CS_DC);
1432         DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
1433         DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
1434         DUMP_REG(DC_COM_GPIO_CTRL);
1435         DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
1436         DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
1437         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
1438         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
1439         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
1440         DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
1441         DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1442         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
1443         DUMP_REG(DC_DISP_REF_TO_SYNC);
1444         DUMP_REG(DC_DISP_SYNC_WIDTH);
1445         DUMP_REG(DC_DISP_BACK_PORCH);
1446         DUMP_REG(DC_DISP_ACTIVE);
1447         DUMP_REG(DC_DISP_FRONT_PORCH);
1448         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
1449         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
1450         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
1451         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
1452         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
1453         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
1454         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
1455         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
1456         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
1457         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
1458         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
1459         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
1460         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
1461         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
1462         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
1463         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
1464         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
1465         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
1466         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
1467         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
1468         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
1469         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
1470         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
1471         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
1472         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
1473         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
1474         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
1475         DUMP_REG(DC_DISP_M0_CONTROL);
1476         DUMP_REG(DC_DISP_M1_CONTROL);
1477         DUMP_REG(DC_DISP_DI_CONTROL);
1478         DUMP_REG(DC_DISP_PP_CONTROL);
1479         DUMP_REG(DC_DISP_PP_SELECT_A);
1480         DUMP_REG(DC_DISP_PP_SELECT_B);
1481         DUMP_REG(DC_DISP_PP_SELECT_C);
1482         DUMP_REG(DC_DISP_PP_SELECT_D);
1483         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
1484         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
1485         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
1486         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
1487         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
1488         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
1489         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
1490         DUMP_REG(DC_DISP_BORDER_COLOR);
1491         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
1492         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
1493         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
1494         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
1495         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
1496         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
1497         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
1498         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
1499         DUMP_REG(DC_DISP_CURSOR_POSITION);
1500         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
1501         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
1502         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
1503         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
1504         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
1505         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
1506         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
1507         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
1508         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
1509         DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
1510         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
1511         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
1512         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
1513         DUMP_REG(DC_DISP_SD_CONTROL);
1514         DUMP_REG(DC_DISP_SD_CSC_COEFF);
1515         DUMP_REG(DC_DISP_SD_LUT(0));
1516         DUMP_REG(DC_DISP_SD_LUT(1));
1517         DUMP_REG(DC_DISP_SD_LUT(2));
1518         DUMP_REG(DC_DISP_SD_LUT(3));
1519         DUMP_REG(DC_DISP_SD_LUT(4));
1520         DUMP_REG(DC_DISP_SD_LUT(5));
1521         DUMP_REG(DC_DISP_SD_LUT(6));
1522         DUMP_REG(DC_DISP_SD_LUT(7));
1523         DUMP_REG(DC_DISP_SD_LUT(8));
1524         DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
1525         DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
1526         DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1527         DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1528         DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1529         DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1530         DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1531         DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1532         DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1533         DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1534         DUMP_REG(DC_DISP_SD_BL_TF(0));
1535         DUMP_REG(DC_DISP_SD_BL_TF(1));
1536         DUMP_REG(DC_DISP_SD_BL_TF(2));
1537         DUMP_REG(DC_DISP_SD_BL_TF(3));
1538         DUMP_REG(DC_DISP_SD_BL_CONTROL);
1539         DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1540         DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
1541         DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1542         DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
1543         DUMP_REG(DC_WIN_WIN_OPTIONS);
1544         DUMP_REG(DC_WIN_BYTE_SWAP);
1545         DUMP_REG(DC_WIN_BUFFER_CONTROL);
1546         DUMP_REG(DC_WIN_COLOR_DEPTH);
1547         DUMP_REG(DC_WIN_POSITION);
1548         DUMP_REG(DC_WIN_SIZE);
1549         DUMP_REG(DC_WIN_PRESCALED_SIZE);
1550         DUMP_REG(DC_WIN_H_INITIAL_DDA);
1551         DUMP_REG(DC_WIN_V_INITIAL_DDA);
1552         DUMP_REG(DC_WIN_DDA_INC);
1553         DUMP_REG(DC_WIN_LINE_STRIDE);
1554         DUMP_REG(DC_WIN_BUF_STRIDE);
1555         DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1556         DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1557         DUMP_REG(DC_WIN_DV_CONTROL);
1558         DUMP_REG(DC_WIN_BLEND_NOKEY);
1559         DUMP_REG(DC_WIN_BLEND_1WIN);
1560         DUMP_REG(DC_WIN_BLEND_2WIN_X);
1561         DUMP_REG(DC_WIN_BLEND_2WIN_Y);
1562         DUMP_REG(DC_WIN_BLEND_3WIN_XY);
1563         DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1564         DUMP_REG(DC_WINBUF_START_ADDR);
1565         DUMP_REG(DC_WINBUF_START_ADDR_NS);
1566         DUMP_REG(DC_WINBUF_START_ADDR_U);
1567         DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1568         DUMP_REG(DC_WINBUF_START_ADDR_V);
1569         DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1570         DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1571         DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1572         DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1573         DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1574         DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1575         DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1576         DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1577         DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1578
1579 #undef DUMP_REG
1580
1581 unlock:
1582         drm_modeset_unlock_crtc(&dc->base);
1583         return err;
1584 }
1585
1586 static int tegra_dc_show_crc(struct seq_file *s, void *data)
1587 {
1588         struct drm_info_node *node = s->private;
1589         struct tegra_dc *dc = node->info_ent->data;
1590         int err = 0;
1591         u32 value;
1592
1593         drm_modeset_lock_crtc(&dc->base, NULL);
1594
1595         if (!dc->base.state->active) {
1596                 err = -EBUSY;
1597                 goto unlock;
1598         }
1599
1600         value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1601         tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1602         tegra_dc_commit(dc);
1603
1604         drm_crtc_wait_one_vblank(&dc->base);
1605         drm_crtc_wait_one_vblank(&dc->base);
1606
1607         value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1608         seq_printf(s, "%08x\n", value);
1609
1610         tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1611
1612 unlock:
1613         drm_modeset_unlock_crtc(&dc->base);
1614         return err;
1615 }
1616
1617 static int tegra_dc_show_stats(struct seq_file *s, void *data)
1618 {
1619         struct drm_info_node *node = s->private;
1620         struct tegra_dc *dc = node->info_ent->data;
1621
1622         seq_printf(s, "frames: %lu\n", dc->stats.frames);
1623         seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1624         seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1625         seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1626
1627         return 0;
1628 }
1629
1630 static struct drm_info_list debugfs_files[] = {
1631         { "regs", tegra_dc_show_regs, 0, NULL },
1632         { "crc", tegra_dc_show_crc, 0, NULL },
1633         { "stats", tegra_dc_show_stats, 0, NULL },
1634 };
1635
1636 static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1637 {
1638         unsigned int i;
1639         char *name;
1640         int err;
1641
1642         name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1643         dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1644         kfree(name);
1645
1646         if (!dc->debugfs)
1647                 return -ENOMEM;
1648
1649         dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1650                                     GFP_KERNEL);
1651         if (!dc->debugfs_files) {
1652                 err = -ENOMEM;
1653                 goto remove;
1654         }
1655
1656         for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1657                 dc->debugfs_files[i].data = dc;
1658
1659         err = drm_debugfs_create_files(dc->debugfs_files,
1660                                        ARRAY_SIZE(debugfs_files),
1661                                        dc->debugfs, minor);
1662         if (err < 0)
1663                 goto free;
1664
1665         dc->minor = minor;
1666
1667         return 0;
1668
1669 free:
1670         kfree(dc->debugfs_files);
1671         dc->debugfs_files = NULL;
1672 remove:
1673         debugfs_remove(dc->debugfs);
1674         dc->debugfs = NULL;
1675
1676         return err;
1677 }
1678
1679 static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1680 {
1681         drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1682                                  dc->minor);
1683         dc->minor = NULL;
1684
1685         kfree(dc->debugfs_files);
1686         dc->debugfs_files = NULL;
1687
1688         debugfs_remove(dc->debugfs);
1689         dc->debugfs = NULL;
1690
1691         return 0;
1692 }
1693
1694 static int tegra_dc_init(struct host1x_client *client)
1695 {
1696         struct drm_device *drm = dev_get_drvdata(client->parent);
1697         unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
1698         struct tegra_dc *dc = host1x_client_to_dc(client);
1699         struct tegra_drm *tegra = drm->dev_private;
1700         struct drm_plane *primary = NULL;
1701         struct drm_plane *cursor = NULL;
1702         u32 value;
1703         int err;
1704
1705         dc->syncpt = host1x_syncpt_request(dc->dev, flags);
1706         if (!dc->syncpt)
1707                 dev_warn(dc->dev, "failed to allocate syncpoint\n");
1708
1709         if (tegra->domain) {
1710                 err = iommu_attach_device(tegra->domain, dc->dev);
1711                 if (err < 0) {
1712                         dev_err(dc->dev, "failed to attach to domain: %d\n",
1713                                 err);
1714                         return err;
1715                 }
1716
1717                 dc->domain = tegra->domain;
1718         }
1719
1720         primary = tegra_dc_primary_plane_create(drm, dc);
1721         if (IS_ERR(primary)) {
1722                 err = PTR_ERR(primary);
1723                 goto cleanup;
1724         }
1725
1726         if (dc->soc->supports_cursor) {
1727                 cursor = tegra_dc_cursor_plane_create(drm, dc);
1728                 if (IS_ERR(cursor)) {
1729                         err = PTR_ERR(cursor);
1730                         goto cleanup;
1731                 }
1732         }
1733
1734         err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
1735                                         &tegra_crtc_funcs);
1736         if (err < 0)
1737                 goto cleanup;
1738
1739         drm_mode_crtc_set_gamma_size(&dc->base, 256);
1740         drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1741
1742         /*
1743          * Keep track of the minimum pitch alignment across all display
1744          * controllers.
1745          */
1746         if (dc->soc->pitch_align > tegra->pitch_align)
1747                 tegra->pitch_align = dc->soc->pitch_align;
1748
1749         err = tegra_dc_rgb_init(drm, dc);
1750         if (err < 0 && err != -ENODEV) {
1751                 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1752                 goto cleanup;
1753         }
1754
1755         err = tegra_dc_add_planes(drm, dc);
1756         if (err < 0)
1757                 goto cleanup;
1758
1759         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1760                 err = tegra_dc_debugfs_init(dc, drm->primary);
1761                 if (err < 0)
1762                         dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1763         }
1764
1765         err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
1766                                dev_name(dc->dev), dc);
1767         if (err < 0) {
1768                 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1769                         err);
1770                 goto cleanup;
1771         }
1772
1773         /* initialize display controller */
1774         if (dc->syncpt) {
1775                 u32 syncpt = host1x_syncpt_id(dc->syncpt);
1776
1777                 value = SYNCPT_CNTRL_NO_STALL;
1778                 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1779
1780                 value = SYNCPT_VSYNC_ENABLE | syncpt;
1781                 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1782         }
1783
1784         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1785                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1786         tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1787
1788         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1789                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1790         tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1791
1792         /* initialize timer */
1793         value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1794                 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1795         tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1796
1797         value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1798                 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1799         tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1800
1801         value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1802                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1803         tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1804
1805         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1806                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1807         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1808
1809         if (dc->soc->supports_border_color)
1810                 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1811
1812         tegra_dc_stats_reset(&dc->stats);
1813
1814         return 0;
1815
1816 cleanup:
1817         if (cursor)
1818                 drm_plane_cleanup(cursor);
1819
1820         if (primary)
1821                 drm_plane_cleanup(primary);
1822
1823         if (tegra->domain) {
1824                 iommu_detach_device(tegra->domain, dc->dev);
1825                 dc->domain = NULL;
1826         }
1827
1828         return err;
1829 }
1830
1831 static int tegra_dc_exit(struct host1x_client *client)
1832 {
1833         struct tegra_dc *dc = host1x_client_to_dc(client);
1834         int err;
1835
1836         devm_free_irq(dc->dev, dc->irq, dc);
1837
1838         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1839                 err = tegra_dc_debugfs_exit(dc);
1840                 if (err < 0)
1841                         dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1842         }
1843
1844         err = tegra_dc_rgb_exit(dc);
1845         if (err) {
1846                 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1847                 return err;
1848         }
1849
1850         if (dc->domain) {
1851                 iommu_detach_device(dc->domain, dc->dev);
1852                 dc->domain = NULL;
1853         }
1854
1855         host1x_syncpt_free(dc->syncpt);
1856
1857         return 0;
1858 }
1859
1860 static const struct host1x_client_ops dc_client_ops = {
1861         .init = tegra_dc_init,
1862         .exit = tegra_dc_exit,
1863 };
1864
1865 static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
1866         .supports_border_color = true,
1867         .supports_interlacing = false,
1868         .supports_cursor = false,
1869         .supports_block_linear = false,
1870         .pitch_align = 8,
1871         .has_powergate = false,
1872 };
1873
1874 static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
1875         .supports_border_color = true,
1876         .supports_interlacing = false,
1877         .supports_cursor = false,
1878         .supports_block_linear = false,
1879         .pitch_align = 8,
1880         .has_powergate = false,
1881 };
1882
1883 static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
1884         .supports_border_color = true,
1885         .supports_interlacing = false,
1886         .supports_cursor = false,
1887         .supports_block_linear = false,
1888         .pitch_align = 64,
1889         .has_powergate = true,
1890 };
1891
1892 static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
1893         .supports_border_color = false,
1894         .supports_interlacing = true,
1895         .supports_cursor = true,
1896         .supports_block_linear = true,
1897         .pitch_align = 64,
1898         .has_powergate = true,
1899 };
1900
1901 static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
1902         .supports_border_color = false,
1903         .supports_interlacing = true,
1904         .supports_cursor = true,
1905         .supports_block_linear = true,
1906         .pitch_align = 64,
1907         .has_powergate = true,
1908 };
1909
1910 static const struct of_device_id tegra_dc_of_match[] = {
1911         {
1912                 .compatible = "nvidia,tegra210-dc",
1913                 .data = &tegra210_dc_soc_info,
1914         }, {
1915                 .compatible = "nvidia,tegra124-dc",
1916                 .data = &tegra124_dc_soc_info,
1917         }, {
1918                 .compatible = "nvidia,tegra114-dc",
1919                 .data = &tegra114_dc_soc_info,
1920         }, {
1921                 .compatible = "nvidia,tegra30-dc",
1922                 .data = &tegra30_dc_soc_info,
1923         }, {
1924                 .compatible = "nvidia,tegra20-dc",
1925                 .data = &tegra20_dc_soc_info,
1926         }, {
1927                 /* sentinel */
1928         }
1929 };
1930 MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
1931
1932 static int tegra_dc_parse_dt(struct tegra_dc *dc)
1933 {
1934         struct device_node *np;
1935         u32 value = 0;
1936         int err;
1937
1938         err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1939         if (err < 0) {
1940                 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1941
1942                 /*
1943                  * If the nvidia,head property isn't present, try to find the
1944                  * correct head number by looking up the position of this
1945                  * display controller's node within the device tree. Assuming
1946                  * that the nodes are ordered properly in the DTS file and
1947                  * that the translation into a flattened device tree blob
1948                  * preserves that ordering this will actually yield the right
1949                  * head number.
1950                  *
1951                  * If those assumptions don't hold, this will still work for
1952                  * cases where only a single display controller is used.
1953                  */
1954                 for_each_matching_node(np, tegra_dc_of_match) {
1955                         if (np == dc->dev->of_node)
1956                                 break;
1957
1958                         value++;
1959                 }
1960         }
1961
1962         dc->pipe = value;
1963
1964         return 0;
1965 }
1966
1967 static int tegra_dc_probe(struct platform_device *pdev)
1968 {
1969         const struct of_device_id *id;
1970         struct resource *regs;
1971         struct tegra_dc *dc;
1972         int err;
1973
1974         dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1975         if (!dc)
1976                 return -ENOMEM;
1977
1978         id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1979         if (!id)
1980                 return -ENODEV;
1981
1982         spin_lock_init(&dc->lock);
1983         INIT_LIST_HEAD(&dc->list);
1984         dc->dev = &pdev->dev;
1985         dc->soc = id->data;
1986
1987         err = tegra_dc_parse_dt(dc);
1988         if (err < 0)
1989                 return err;
1990
1991         dc->clk = devm_clk_get(&pdev->dev, NULL);
1992         if (IS_ERR(dc->clk)) {
1993                 dev_err(&pdev->dev, "failed to get clock\n");
1994                 return PTR_ERR(dc->clk);
1995         }
1996
1997         dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1998         if (IS_ERR(dc->rst)) {
1999                 dev_err(&pdev->dev, "failed to get reset\n");
2000                 return PTR_ERR(dc->rst);
2001         }
2002
2003         if (dc->soc->has_powergate) {
2004                 if (dc->pipe == 0)
2005                         dc->powergate = TEGRA_POWERGATE_DIS;
2006                 else
2007                         dc->powergate = TEGRA_POWERGATE_DISB;
2008
2009                 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2010                                                         dc->rst);
2011                 if (err < 0) {
2012                         dev_err(&pdev->dev, "failed to power partition: %d\n",
2013                                 err);
2014                         return err;
2015                 }
2016         } else {
2017                 err = clk_prepare_enable(dc->clk);
2018                 if (err < 0) {
2019                         dev_err(&pdev->dev, "failed to enable clock: %d\n",
2020                                 err);
2021                         return err;
2022                 }
2023
2024                 err = reset_control_deassert(dc->rst);
2025                 if (err < 0) {
2026                         dev_err(&pdev->dev, "failed to deassert reset: %d\n",
2027                                 err);
2028                         return err;
2029                 }
2030         }
2031
2032         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2033         dc->regs = devm_ioremap_resource(&pdev->dev, regs);
2034         if (IS_ERR(dc->regs))
2035                 return PTR_ERR(dc->regs);
2036
2037         dc->irq = platform_get_irq(pdev, 0);
2038         if (dc->irq < 0) {
2039                 dev_err(&pdev->dev, "failed to get IRQ\n");
2040                 return -ENXIO;
2041         }
2042
2043         INIT_LIST_HEAD(&dc->client.list);
2044         dc->client.ops = &dc_client_ops;
2045         dc->client.dev = &pdev->dev;
2046
2047         err = tegra_dc_rgb_probe(dc);
2048         if (err < 0 && err != -ENODEV) {
2049                 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
2050                 return err;
2051         }
2052
2053         err = host1x_client_register(&dc->client);
2054         if (err < 0) {
2055                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2056                         err);
2057                 return err;
2058         }
2059
2060         platform_set_drvdata(pdev, dc);
2061
2062         return 0;
2063 }
2064
2065 static int tegra_dc_remove(struct platform_device *pdev)
2066 {
2067         struct tegra_dc *dc = platform_get_drvdata(pdev);
2068         int err;
2069
2070         err = host1x_client_unregister(&dc->client);
2071         if (err < 0) {
2072                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2073                         err);
2074                 return err;
2075         }
2076
2077         err = tegra_dc_rgb_remove(dc);
2078         if (err < 0) {
2079                 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2080                 return err;
2081         }
2082
2083         reset_control_assert(dc->rst);
2084
2085         if (dc->soc->has_powergate)
2086                 tegra_powergate_power_off(dc->powergate);
2087
2088         clk_disable_unprepare(dc->clk);
2089
2090         return 0;
2091 }
2092
2093 struct platform_driver tegra_dc_driver = {
2094         .driver = {
2095                 .name = "tegra-dc",
2096                 .of_match_table = tegra_dc_of_match,
2097         },
2098         .probe = tegra_dc_probe,
2099         .remove = tegra_dc_remove,
2100 };