drivers/i2c/busses/i2c-pxa.c

   1 /*
   2  *  i2c_adap_pxa.c
   3  *
   4  *  I2C adapter for the PXA I2C bus access.
   5  *
   6  *  Copyright (C) 2002 Intrinsyc Software Inc.
   7  *  Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
   8  *
   9  *  This program is free software; you can redistribute it and/or modify
  10  *  it under the terms of the GNU General Public License version 2 as
  11  *  published by the Free Software Foundation.
  12  *
  13  *  History:
  14  *    Apr 2002: Initial version [CS]
  15  *    Jun 2002: Properly separated algo/adap [FB]
  16  *    Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
  17  *    Jan 2003: added limited signal handling [Kai-Uwe Bloem]
  18  *    Sep 2004: Major rework to ensure efficient bus handling [RMK]
  19  *    Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
  20  *    Feb 2005: Rework slave mode handling [RMK]
  21  */
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/i2c.h>
  25 #include <linux/init.h>
  26 #include <linux/time.h>
  27 #include <linux/sched.h>
  28 #include <linux/delay.h>
  29 #include <linux/errno.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/i2c-pxa.h>
  32 #include <linux/of.h>
  33 #include <linux/of_device.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/err.h>
  36 #include <linux/clk.h>
  37 #include <linux/slab.h>
  38 #include <linux/io.h>
  39 #include <linux/i2c/pxa-i2c.h>
  40
  41 #include <asm/irq.h>
  42
  43 struct pxa_reg_layout {
  44         u32 ibmr;
  45         u32 idbr;
  46         u32 icr;
  47         u32 isr;
  48         u32 isar;
  49 };
  50
  51 enum pxa_i2c_types {
  52         REGS_PXA2XX,
  53         REGS_PXA3XX,
  54         REGS_CE4100,
  55 };
  56
  57 /*
  58  * I2C registers definitions
  59  */
  60 static struct pxa_reg_layout pxa_reg_layout[] = {
  61         [REGS_PXA2XX] = {
  62                 .ibmr = 0x00,
  63                 .idbr = 0x08,
  64                 .icr =  0x10,
  65                 .isr =  0x18,
  66                 .isar = 0x20,
  67         },
  68         [REGS_PXA3XX] = {
  69                 .ibmr = 0x00,
  70                 .idbr = 0x04,
  71                 .icr =  0x08,
  72                 .isr =  0x0c,
  73                 .isar = 0x10,
  74         },
  75         [REGS_CE4100] = {
  76                 .ibmr = 0x14,
  77                 .idbr = 0x0c,
  78                 .icr =  0x00,
  79                 .isr =  0x04,
  80                 /* no isar register */
  81         },
  82 };
  83
  84 static const struct platform_device_id i2c_pxa_id_table[] = {
  85         { "pxa2xx-i2c",         REGS_PXA2XX },
  86         { "pxa3xx-pwri2c",      REGS_PXA3XX },
  87         { "ce4100-i2c",         REGS_CE4100 },
  88         { },
  89 };
  90 MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
  91
  92 /*
  93  * I2C bit definitions
  94  */
  95
  96 #define ICR_START       (1 << 0)           /* start bit */
  97 #define ICR_STOP        (1 << 1)           /* stop bit */
  98 #define ICR_ACKNAK      (1 << 2)           /* send ACK(0) or NAK(1) */
  99 #define ICR_TB          (1 << 3)           /* transfer byte bit */
 100 #define ICR_MA          (1 << 4)           /* master abort */
 101 #define ICR_SCLE        (1 << 5)           /* master clock enable */
 102 #define ICR_IUE         (1 << 6)           /* unit enable */
 103 #define ICR_GCD         (1 << 7)           /* general call disable */
 104 #define ICR_ITEIE       (1 << 8)           /* enable tx interrupts */
 105 #define ICR_IRFIE       (1 << 9)           /* enable rx interrupts */
 106 #define ICR_BEIE        (1 << 10)          /* enable bus error ints */
 107 #define ICR_SSDIE       (1 << 11)          /* slave STOP detected int enable */
 108 #define ICR_ALDIE       (1 << 12)          /* enable arbitration interrupt */
 109 #define ICR_SADIE       (1 << 13)          /* slave address detected int enable */
 110 #define ICR_UR          (1 << 14)          /* unit reset */
 111 #define ICR_FM          (1 << 15)          /* fast mode */
 112 #define ICR_HS          (1 << 16)          /* High Speed mode */
 113 #define ICR_GPIOEN      (1 << 19)          /* enable GPIO mode for SCL in HS */
 114
 115 #define ISR_RWM         (1 << 0)           /* read/write mode */
 116 #define ISR_ACKNAK      (1 << 1)           /* ack/nak status */
 117 #define ISR_UB          (1 << 2)           /* unit busy */
 118 #define ISR_IBB         (1 << 3)           /* bus busy */
 119 #define ISR_SSD         (1 << 4)           /* slave stop detected */
 120 #define ISR_ALD         (1 << 5)           /* arbitration loss detected */
 121 #define ISR_ITE         (1 << 6)           /* tx buffer empty */
 122 #define ISR_IRF         (1 << 7)           /* rx buffer full */
 123 #define ISR_GCAD        (1 << 8)           /* general call address detected */
 124 #define ISR_SAD         (1 << 9)           /* slave address detected */
 125 #define ISR_BED         (1 << 10)          /* bus error no ACK/NAK */
 126
 127 struct pxa_i2c {
 128         spinlock_t              lock;
 129         wait_queue_head_t       wait;
 130         struct i2c_msg          *msg;
 131         unsigned int            msg_num;
 132         unsigned int            msg_idx;
 133         unsigned int            msg_ptr;
 134         unsigned int            slave_addr;
 135         unsigned int            req_slave_addr;
 136
 137         struct i2c_adapter      adap;
 138         struct clk              *clk;
 139 #ifdef CONFIG_I2C_PXA_SLAVE
 140         struct i2c_slave_client *slave;
 141 #endif
 142
 143         unsigned int            irqlogidx;
 144         u32                     isrlog[32];
 145         u32                     icrlog[32];
 146
 147         void __iomem            *reg_base;
 148         void __iomem            *reg_ibmr;
 149         void __iomem            *reg_idbr;
 150         void __iomem            *reg_icr;
 151         void __iomem            *reg_isr;
 152         void __iomem            *reg_isar;
 153
 154         unsigned long           iobase;
 155         unsigned long           iosize;
 156
 157         int                     irq;
 158         unsigned int            use_pio :1;
 159         unsigned int            fast_mode :1;
 160         unsigned int            high_mode:1;
 161         unsigned char           master_code;
 162         unsigned long           rate;
 163         bool                    highmode_enter;
 164 };
 165
 166 #define _IBMR(i2c)      ((i2c)->reg_ibmr)
 167 #define _IDBR(i2c)      ((i2c)->reg_idbr)
 168 #define _ICR(i2c)       ((i2c)->reg_icr)
 169 #define _ISR(i2c)       ((i2c)->reg_isr)
 170 #define _ISAR(i2c)      ((i2c)->reg_isar)
 171
 172 /*
 173  * I2C Slave mode address
 174  */
 175 #define I2C_PXA_SLAVE_ADDR      0x1
 176
 177 #ifdef DEBUG
 178
 179 struct bits {
 180         u32     mask;
 181         const char *set;
 182         const char *unset;
 183 };
 184 #define PXA_BIT(m, s, u)        { .mask = m, .set = s, .unset = u }
 185
 186 static inline void
 187 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
 188 {
 189         printk("%s %08x: ", prefix, val);
 190         while (num--) {
 191                 const char *str = val & bits->mask ? bits->set : bits->unset;
 192                 if (str)
 193                         printk("%s ", str);
 194                 bits++;
 195         }
 196 }
 197
 198 static const struct bits isr_bits[] = {
 199         PXA_BIT(ISR_RWM,        "RX",           "TX"),
 200         PXA_BIT(ISR_ACKNAK,     "NAK",          "ACK"),
 201         PXA_BIT(ISR_UB,         "Bsy",          "Rdy"),
 202         PXA_BIT(ISR_IBB,        "BusBsy",       "BusRdy"),
 203         PXA_BIT(ISR_SSD,        "SlaveStop",    NULL),
 204         PXA_BIT(ISR_ALD,        "ALD",          NULL),
 205         PXA_BIT(ISR_ITE,        "TxEmpty",      NULL),
 206         PXA_BIT(ISR_IRF,        "RxFull",       NULL),
 207         PXA_BIT(ISR_GCAD,       "GenCall",      NULL),
 208         PXA_BIT(ISR_SAD,        "SlaveAddr",    NULL),
 209         PXA_BIT(ISR_BED,        "BusErr",       NULL),
 210 };
 211
 212 static void decode_ISR(unsigned int val)
 213 {
 214         decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
 215         printk("\n");
 216 }
 217
 218 static const struct bits icr_bits[] = {
 219         PXA_BIT(ICR_START,  "START",    NULL),
 220         PXA_BIT(ICR_STOP,   "STOP",     NULL),
 221         PXA_BIT(ICR_ACKNAK, "ACKNAK",   NULL),
 222         PXA_BIT(ICR_TB,     "TB",       NULL),
 223         PXA_BIT(ICR_MA,     "MA",       NULL),
 224         PXA_BIT(ICR_SCLE,   "SCLE",     "scle"),
 225         PXA_BIT(ICR_IUE,    "IUE",      "iue"),
 226         PXA_BIT(ICR_GCD,    "GCD",      NULL),
 227         PXA_BIT(ICR_ITEIE,  "ITEIE",    NULL),
 228         PXA_BIT(ICR_IRFIE,  "IRFIE",    NULL),
 229         PXA_BIT(ICR_BEIE,   "BEIE",     NULL),
 230         PXA_BIT(ICR_SSDIE,  "SSDIE",    NULL),
 231         PXA_BIT(ICR_ALDIE,  "ALDIE",    NULL),
 232         PXA_BIT(ICR_SADIE,  "SADIE",    NULL),
 233         PXA_BIT(ICR_UR,     "UR",               "ur"),
 234 };
 235
 236 #ifdef CONFIG_I2C_PXA_SLAVE
 237 static void decode_ICR(unsigned int val)
 238 {
 239         decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
 240         printk("\n");
 241 }
 242 #endif
 243
 244 static unsigned int i2c_debug = DEBUG;
 245
 246 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
 247 {
 248         dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
 249                 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 250 }
 251
 252 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
 253
 254 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
 255 {
 256         unsigned int i;
 257         struct device *dev = &i2c->adap.dev;
 258
 259         dev_err(dev, "slave_0x%x error: %s\n",
 260                 i2c->req_slave_addr >> 1, why);
 261         dev_err(dev, "msg_num: %d msg_idx: %d msg_ptr: %d\n",
 262                 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
 263         dev_err(dev, "IBMR: %08x IDBR: %08x ICR: %08x ISR: %08x\n",
 264                 readl(_IBMR(i2c)), readl(_IDBR(i2c)), readl(_ICR(i2c)),
 265                 readl(_ISR(i2c)));
 266         dev_dbg(dev, "log: ");
 267         for (i = 0; i < i2c->irqlogidx; i++)
 268                 pr_debug("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
 269
 270         pr_debug("\n");
 271 }
 272
 273 #else /* ifdef DEBUG */
 274
 275 #define i2c_debug       0
 276
 277 #define show_state(i2c) do { } while (0)
 278 #define decode_ISR(val) do { } while (0)
 279 #define decode_ICR(val) do { } while (0)
 280 #define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0)
 281
 282 #endif /* ifdef DEBUG / else */
 283
 284 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
 285 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id);
 286
 287 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
 288 {
 289         return !(readl(_ICR(i2c)) & ICR_SCLE);
 290 }
 291
 292 static void i2c_pxa_abort(struct pxa_i2c *i2c)
 293 {
 294         int i = 250;
 295
 296         if (i2c_pxa_is_slavemode(i2c)) {
 297                 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
 298                 return;
 299         }
 300
 301         while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) {
 302                 unsigned long icr = readl(_ICR(i2c));
 303
 304                 icr &= ~ICR_START;
 305                 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
 306
 307                 writel(icr, _ICR(i2c));
 308
 309                 show_state(i2c);
 310
 311                 mdelay(1);
 312                 i --;
 313         }
 314
 315         writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
 316                _ICR(i2c));
 317 }
 318
 319 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
 320 {
 321         int timeout = DEF_TIMEOUT;
 322
 323         while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
 324                 if ((readl(_ISR(i2c)) & ISR_SAD) != 0)
 325                         timeout += 4;
 326
 327                 msleep(2);
 328                 show_state(i2c);
 329         }
 330
 331         if (timeout < 0)
 332                 show_state(i2c);
 333
 334         return timeout < 0 ? I2C_RETRY : 0;
 335 }
 336
 337 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
 338 {
 339         unsigned long timeout = jiffies + HZ*4;
 340
 341         while (time_before(jiffies, timeout)) {
 342                 if (i2c_debug > 1)
 343                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 344                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 345
 346                 if (readl(_ISR(i2c)) & ISR_SAD) {
 347                         if (i2c_debug > 0)
 348                                 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
 349                         goto out;
 350                 }
 351
 352                 /* wait for unit and bus being not busy, and we also do a
 353                  * quick check of the i2c lines themselves to ensure they've
 354                  * gone high...
 355                  */
 356                 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) {
 357                         if (i2c_debug > 0)
 358                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
 359                         return 1;
 360                 }
 361
 362                 msleep(1);
 363         }
 364
 365         if (i2c_debug > 0)
 366                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
 367  out:
 368         return 0;
 369 }
 370
 371 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
 372 {
 373         if (i2c_debug)
 374                 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
 375
 376         if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
 377                 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
 378                 if (!i2c_pxa_wait_master(i2c)) {
 379                         dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
 380                         return I2C_RETRY;
 381                 }
 382         }
 383
 384         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
 385         return 0;
 386 }
 387
 388 #ifdef CONFIG_I2C_PXA_SLAVE
 389 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
 390 {
 391         unsigned long timeout = jiffies + HZ*1;
 392
 393         /* wait for stop */
 394
 395         show_state(i2c);
 396
 397         while (time_before(jiffies, timeout)) {
 398                 if (i2c_debug > 1)
 399                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 400                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 401
 402                 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
 403                     (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
 404                     (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
 405                         if (i2c_debug > 1)
 406                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
 407                         return 1;
 408                 }
 409
 410                 msleep(1);
 411         }
 412
 413         if (i2c_debug > 0)
 414                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
 415         return 0;
 416 }
 417
 418 /*
 419  * clear the hold on the bus, and take of anything else
 420  * that has been configured
 421  */
 422 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
 423 {
 424         show_state(i2c);
 425
 426         if (errcode < 0) {
 427                 udelay(100);   /* simple delay */
 428         } else {
 429                 /* we need to wait for the stop condition to end */
 430
 431                 /* if we where in stop, then clear... */
 432                 if (readl(_ICR(i2c)) & ICR_STOP) {
 433                         udelay(100);
 434                         writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
 435                 }
 436
 437                 if (!i2c_pxa_wait_slave(i2c)) {
 438                         dev_err(&i2c->adap.dev, "%s: wait timedout\n",
 439                                 __func__);
 440                         return;
 441                 }
 442         }
 443
 444         writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
 445         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 446
 447         if (i2c_debug) {
 448                 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
 449                 decode_ICR(readl(_ICR(i2c)));
 450         }
 451 }
 452 #else
 453 #define i2c_pxa_set_slave(i2c, err)     do { } while (0)
 454 #endif
 455
 456 static void i2c_pxa_reset(struct pxa_i2c *i2c)
 457 {
 458         pr_debug("Resetting I2C Controller Unit\n");
 459
 460         /* abort any transfer currently under way */
 461         i2c_pxa_abort(i2c);
 462
 463         /* reset according to 9.8 */
 464         writel(ICR_UR, _ICR(i2c));
 465         writel(I2C_ISR_INIT, _ISR(i2c));
 466         writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
 467
 468         if (i2c->reg_isar && IS_ENABLED(CONFIG_I2C_PXA_SLAVE))
 469                 writel(i2c->slave_addr, _ISAR(i2c));
 470
 471         /* set control register values */
 472         writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c));
 473         writel(readl(_ICR(i2c)) | (i2c->high_mode ? ICR_HS : 0), _ICR(i2c));
 474
 475 #ifdef CONFIG_I2C_PXA_SLAVE
 476         dev_info(&i2c->adap.dev, "Enabling slave mode\n");
 477         writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
 478 #endif
 479
 480         i2c_pxa_set_slave(i2c, 0);
 481
 482         /* enable unit */
 483         writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
 484         udelay(100);
 485 }
 486
 487
 488 #ifdef CONFIG_I2C_PXA_SLAVE
 489 /*
 490  * PXA I2C Slave mode
 491  */
 492
 493 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
 494 {
 495         if (isr & ISR_BED) {
 496                 /* what should we do here? */
 497         } else {
 498                 int ret = 0;
 499
 500                 if (i2c->slave != NULL)
 501                         ret = i2c->slave->read(i2c->slave->data);
 502
 503                 writel(ret, _IDBR(i2c));
 504                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));   /* allow next byte */
 505         }
 506 }
 507
 508 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
 509 {
 510         unsigned int byte = readl(_IDBR(i2c));
 511
 512         if (i2c->slave != NULL)
 513                 i2c->slave->write(i2c->slave->data, byte);
 514
 515         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 516 }
 517
 518 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
 519 {
 520         int timeout;
 521
 522         if (i2c_debug > 0)
 523                 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
 524                        (isr & ISR_RWM) ? 'r' : 't');
 525
 526         if (i2c->slave != NULL)
 527                 i2c->slave->event(i2c->slave->data,
 528                                  (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
 529
 530         /*
 531          * slave could interrupt in the middle of us generating a
 532          * start condition... if this happens, we'd better back off
 533          * and stop holding the poor thing up
 534          */
 535         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
 536         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 537
 538         timeout = 0x10000;
 539
 540         while (1) {
 541                 if ((readl(_IBMR(i2c)) & 2) == 2)
 542                         break;
 543
 544                 timeout--;
 545
 546                 if (timeout <= 0) {
 547                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
 548                         break;
 549                 }
 550         }
 551
 552         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 553 }
 554
 555 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
 556 {
 557         if (i2c_debug > 2)
 558                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
 559
 560         if (i2c->slave != NULL)
 561                 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
 562
 563         if (i2c_debug > 2)
 564                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
 565
 566         /*
 567          * If we have a master-mode message waiting,
 568          * kick it off now that the slave has completed.
 569          */
 570         if (i2c->msg)
 571                 i2c_pxa_master_complete(i2c, I2C_RETRY);
 572 }
 573 #else
 574 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
 575 {
 576         if (isr & ISR_BED) {
 577                 /* what should we do here? */
 578         } else {
 579                 writel(0, _IDBR(i2c));
 580                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 581         }
 582 }
 583
 584 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
 585 {
 586         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
 587 }
 588
 589 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
 590 {
 591         int timeout;
 592
 593         /*
 594          * slave could interrupt in the middle of us generating a
 595          * start condition... if this happens, we'd better back off
 596          * and stop holding the poor thing up
 597          */
 598         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
 599         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
 600
 601         timeout = 0x10000;
 602
 603         while (1) {
 604                 if ((readl(_IBMR(i2c)) & 2) == 2)
 605                         break;
 606
 607                 timeout--;
 608
 609                 if (timeout <= 0) {
 610                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
 611                         break;
 612                 }
 613         }
 614
 615         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 616 }
 617
 618 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
 619 {
 620         if (i2c->msg)
 621                 i2c_pxa_master_complete(i2c, I2C_RETRY);
 622 }
 623 #endif
 624
 625 /*
 626  * PXA I2C Master mode
 627  */
 628
 629 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
 630 {
 631         unsigned int addr = (msg->addr & 0x7f) << 1;
 632
 633         if (msg->flags & I2C_M_RD)
 634                 addr |= 1;
 635
 636         return addr;
 637 }
 638
 639 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
 640 {
 641         u32 icr;
 642
 643         /*
 644          * Step 1: target slave address into IDBR
 645          */
 646         writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
 647         i2c->req_slave_addr = i2c_pxa_addr_byte(i2c->msg);
 648
 649         /*
 650          * Step 2: initiate the write.
 651          */
 652         icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
 653         writel(icr | ICR_START | ICR_TB, _ICR(i2c));
 654 }
 655
 656 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
 657 {
 658         u32 icr;
 659
 660         /*
 661          * Clear the STOP and ACK flags
 662          */
 663         icr = readl(_ICR(i2c));
 664         icr &= ~(ICR_STOP | ICR_ACKNAK);
 665         writel(icr, _ICR(i2c));
 666 }
 667
 668 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
 669 {
 670         /* make timeout the same as for interrupt based functions */
 671         long timeout = 2 * DEF_TIMEOUT;
 672
 673         /*
 674          * Wait for the bus to become free.
 675          */
 676         while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
 677                 udelay(1000);
 678                 show_state(i2c);
 679         }
 680
 681         if (timeout < 0) {
 682                 show_state(i2c);
 683                 dev_err(&i2c->adap.dev,
 684                         "i2c_pxa: timeout waiting for bus free\n");
 685                 return I2C_RETRY;
 686         }
 687
 688         /*
 689          * Set master mode.
 690          */
 691         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
 692
 693         return 0;
 694 }
 695
 696 /*
 697  * PXA I2C send master code
 698  * 1. Load master code to IDBR and send it.
 699  *    Note for HS mode, set ICR [GPIOEN].
 700  * 2. Wait until win arbitration.
 701  */
 702 static int i2c_pxa_send_mastercode(struct pxa_i2c *i2c)
 703 {
 704         u32 icr;
 705         long timeout;
 706
 707         spin_lock_irq(&i2c->lock);
 708         i2c->highmode_enter = true;
 709         writel(i2c->master_code, _IDBR(i2c));
 710
 711         icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
 712         icr |= ICR_GPIOEN | ICR_START | ICR_TB | ICR_ITEIE;
 713         writel(icr, _ICR(i2c));
 714
 715         spin_unlock_irq(&i2c->lock);
 716         timeout = wait_event_timeout(i2c->wait,
 717                         i2c->highmode_enter == false, HZ * 1);
 718
 719         i2c->highmode_enter = false;
 720
 721         return (timeout == 0) ? I2C_RETRY : 0;
 722 }
 723
 724 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
 725                                struct i2c_msg *msg, int num)
 726 {
 727         unsigned long timeout = 500000; /* 5 seconds */
 728         int ret = 0;
 729
 730         ret = i2c_pxa_pio_set_master(i2c);
 731         if (ret)
 732                 goto out;
 733
 734         i2c->msg = msg;
 735         i2c->msg_num = num;
 736         i2c->msg_idx = 0;
 737         i2c->msg_ptr = 0;
 738         i2c->irqlogidx = 0;
 739
 740         i2c_pxa_start_message(i2c);
 741
 742         while (i2c->msg_num > 0 && --timeout) {
 743                 i2c_pxa_handler(0, i2c);
 744                 udelay(10);
 745         }
 746
 747         i2c_pxa_stop_message(i2c);
 748
 749         /*
 750          * We place the return code in i2c->msg_idx.
 751          */
 752         ret = i2c->msg_idx;
 753
 754 out:
 755         if (timeout == 0) {
 756                 i2c_pxa_scream_blue_murder(i2c, "timeout");
 757                 ret = I2C_RETRY;
 758         }
 759
 760         return ret;
 761 }
 762
 763 /*
 764  * We are protected by the adapter bus mutex.
 765  */
 766 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
 767 {
 768         long timeout;
 769         int ret;
 770
 771         /*
 772          * Wait for the bus to become free.
 773          */
 774         ret = i2c_pxa_wait_bus_not_busy(i2c);
 775         if (ret) {
 776                 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
 777                 goto out;
 778         }
 779
 780         /*
 781          * Set master mode.
 782          */
 783         ret = i2c_pxa_set_master(i2c);
 784         if (ret) {
 785                 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
 786                 goto out;
 787         }
 788
 789         if (i2c->high_mode) {
 790                 ret = i2c_pxa_send_mastercode(i2c);
 791                 if (ret) {
 792                         dev_err(&i2c->adap.dev, "i2c_pxa_send_mastercode timeout\n");
 793                         goto out;
 794                         }
 795         }
 796
 797         spin_lock_irq(&i2c->lock);
 798
 799         i2c->msg = msg;
 800         i2c->msg_num = num;
 801         i2c->msg_idx = 0;
 802         i2c->msg_ptr = 0;
 803         i2c->irqlogidx = 0;
 804
 805         i2c_pxa_start_message(i2c);
 806
 807         spin_unlock_irq(&i2c->lock);
 808
 809         /*
 810          * The rest of the processing occurs in the interrupt handler.
 811          */
 812         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
 813         i2c_pxa_stop_message(i2c);
 814
 815         /*
 816          * We place the return code in i2c->msg_idx.
 817          */
 818         ret = i2c->msg_idx;
 819
 820         if (!timeout && i2c->msg_num) {
 821                 i2c_pxa_scream_blue_murder(i2c, "timeout");
 822                 ret = I2C_RETRY;
 823         }
 824
 825  out:
 826         return ret;
 827 }
 828
 829 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
 830                             struct i2c_msg msgs[], int num)
 831 {
 832         struct pxa_i2c *i2c = adap->algo_data;
 833         int ret, i;
 834
 835         /* If the I2C controller is disabled we need to reset it
 836           (probably due to a suspend/resume destroying state). We do
 837           this here as we can then avoid worrying about resuming the
 838           controller before its users. */
 839         if (!(readl(_ICR(i2c)) & ICR_IUE))
 840                 i2c_pxa_reset(i2c);
 841
 842         for (i = adap->retries; i >= 0; i--) {
 843                 ret = i2c_pxa_do_pio_xfer(i2c, msgs, num);
 844                 if (ret != I2C_RETRY)
 845                         goto out;
 846
 847                 if (i2c_debug)
 848                         dev_dbg(&adap->dev, "Retrying transmission\n");
 849                 udelay(100);
 850         }
 851         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
 852         ret = -EREMOTEIO;
 853  out:
 854         i2c_pxa_set_slave(i2c, ret);
 855         return ret;
 856 }
 857
 858 /*
 859  * i2c_pxa_master_complete - complete the message and wake up.
 860  */
 861 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
 862 {
 863         i2c->msg_ptr = 0;
 864         i2c->msg = NULL;
 865         i2c->msg_idx ++;
 866         i2c->msg_num = 0;
 867         if (ret)
 868                 i2c->msg_idx = ret;
 869         if (!i2c->use_pio)
 870                 wake_up(&i2c->wait);
 871 }
 872
 873 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
 874 {
 875         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
 876
 877  again:
 878         /*
 879          * If ISR_ALD is set, we lost arbitration.
 880          */
 881         if (isr & ISR_ALD) {
 882                 /*
 883                  * Do we need to do anything here?  The PXA docs
 884                  * are vague about what happens.
 885                  */
 886                 i2c_pxa_scream_blue_murder(i2c, "ALD set");
 887
 888                 /*
 889                  * We ignore this error.  We seem to see spurious ALDs
 890                  * for seemingly no reason.  If we handle them as I think
 891                  * they should, we end up causing an I2C error, which
 892                  * is painful for some systems.
 893                  */
 894                 return; /* ignore */
 895         }
 896
 897         if ((isr & ISR_BED) &&
 898                 (!((i2c->msg->flags & I2C_M_IGNORE_NAK) &&
 899                         (isr & ISR_ACKNAK)))) {
 900                 int ret = BUS_ERROR;
 901
 902                 /*
 903                  * I2C bus error - either the device NAK'd us, or
 904                  * something more serious happened.  If we were NAK'd
 905                  * on the initial address phase, we can retry.
 906                  */
 907                 if (isr & ISR_ACKNAK) {
 908                         if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
 909                                 ret = I2C_RETRY;
 910                         else
 911                                 ret = XFER_NAKED;
 912                 }
 913                 i2c_pxa_master_complete(i2c, ret);
 914         } else if (isr & ISR_RWM) {
 915                 /*
 916                  * Read mode.  We have just sent the address byte, and
 917                  * now we must initiate the transfer.
 918                  */
 919                 if (i2c->msg_ptr == i2c->msg->len - 1 &&
 920                     i2c->msg_idx == i2c->msg_num - 1)
 921                         icr |= ICR_STOP | ICR_ACKNAK;
 922
 923                 icr |= ICR_ALDIE | ICR_TB;
 924         } else if (i2c->msg_ptr < i2c->msg->len) {
 925                 /*
 926                  * Write mode.  Write the next data byte.
 927                  */
 928                 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
 929
 930                 icr |= ICR_ALDIE | ICR_TB;
 931
 932                 /*
 933                  * If this is the last byte of the last message or last byte
 934                  * of any message with I2C_M_STOP (e.g. SCCB), send a STOP.
 935                  */
 936                 if ((i2c->msg_ptr == i2c->msg->len) &&
 937                         ((i2c->msg->flags & I2C_M_STOP) ||
 938                         (i2c->msg_idx == i2c->msg_num - 1)))
 939                                 icr |= ICR_STOP;
 940
 941         } else if (i2c->msg_idx < i2c->msg_num - 1) {
 942                 /*
 943                  * Next segment of the message.
 944                  */
 945                 i2c->msg_ptr = 0;
 946                 i2c->msg_idx ++;
 947                 i2c->msg++;
 948
 949                 /*
 950                  * If we aren't doing a repeated start and address,
 951                  * go back and try to send the next byte.  Note that
 952                  * we do not support switching the R/W direction here.
 953                  */
 954                 if (i2c->msg->flags & I2C_M_NOSTART)
 955                         goto again;
 956
 957                 /*
 958                  * Write the next address.
 959                  */
 960                 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
 961                 i2c->req_slave_addr = i2c_pxa_addr_byte(i2c->msg);
 962
 963                 /*
 964                  * And trigger a repeated start, and send the byte.
 965                  */
 966                 icr &= ~ICR_ALDIE;
 967                 icr |= ICR_START | ICR_TB;
 968         } else {
 969                 if (i2c->msg->len == 0) {
 970                         /*
 971                          * Device probes have a message length of zero
 972                          * and need the bus to be reset before it can
 973                          * be used again.
 974                          */
 975                         i2c_pxa_reset(i2c);
 976                 }
 977                 i2c_pxa_master_complete(i2c, 0);
 978         }
 979
 980         i2c->icrlog[i2c->irqlogidx-1] = icr;
 981
 982         writel(icr, _ICR(i2c));
 983         show_state(i2c);
 984 }
 985
 986 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
 987 {
 988         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
 989
 990         /*
 991          * Read the byte.
 992          */
 993         i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
 994
 995         if (i2c->msg_ptr < i2c->msg->len) {
 996                 /*
 997                  * If this is the last byte of the last
 998                  * message, send a STOP.
 999                  */
1000                 if (i2c->msg_ptr == i2c->msg->len - 1)
1001                         icr |= ICR_STOP | ICR_ACKNAK;
1002
1003                 icr |= ICR_ALDIE | ICR_TB;
1004         } else {
1005                 i2c_pxa_master_complete(i2c, 0);
1006         }
1007
1008         i2c->icrlog[i2c->irqlogidx-1] = icr;
1009
1010         writel(icr, _ICR(i2c));
1011 }
1012
1013 #define VALID_INT_SOURCE        (ISR_SSD | ISR_ALD | ISR_ITE | ISR_IRF | \
1014                                 ISR_SAD | ISR_BED)
1015 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
1016 {
1017         struct pxa_i2c *i2c = dev_id;
1018         u32 isr = readl(_ISR(i2c));
1019
1020         if (!(isr & VALID_INT_SOURCE))
1021                 return IRQ_NONE;
1022
1023         if (i2c_debug > 2 && 0) {
1024                 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
1025                         __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
1026                 decode_ISR(isr);
1027         }
1028
1029         if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
1030                 i2c->isrlog[i2c->irqlogidx++] = isr;
1031
1032         show_state(i2c);
1033
1034         /*
1035          * Always clear all pending IRQs.
1036          */
1037         writel(isr & VALID_INT_SOURCE, _ISR(i2c));
1038
1039         if (isr & ISR_SAD)
1040                 i2c_pxa_slave_start(i2c, isr);
1041         if (isr & ISR_SSD)
1042                 i2c_pxa_slave_stop(i2c);
1043
1044         if (i2c_pxa_is_slavemode(i2c)) {
1045                 if (isr & ISR_ITE)
1046                         i2c_pxa_slave_txempty(i2c, isr);
1047                 if (isr & ISR_IRF)
1048                         i2c_pxa_slave_rxfull(i2c, isr);
1049         } else if (i2c->msg && (!i2c->highmode_enter)) {
1050                 if (isr & ISR_ITE)
1051                         i2c_pxa_irq_txempty(i2c, isr);
1052                 if (isr & ISR_IRF)
1053                         i2c_pxa_irq_rxfull(i2c, isr);
1054         } else if ((isr & ISR_ITE) && i2c->highmode_enter) {
1055                 i2c->highmode_enter = false;
1056                 wake_up(&i2c->wait);
1057         } else {
1058                 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
1059         }
1060
1061         return IRQ_HANDLED;
1062 }
1063
1064
1065 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
1066 {
1067         struct pxa_i2c *i2c = adap->algo_data;
1068         int ret, i;
1069
1070         for (i = adap->retries; i >= 0; i--) {
1071                 ret = i2c_pxa_do_xfer(i2c, msgs, num);
1072                 if (ret != I2C_RETRY)
1073                         goto out;
1074
1075                 if (i2c_debug)
1076                         dev_dbg(&adap->dev, "Retrying transmission\n");
1077                 udelay(100);
1078         }
1079         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
1080         ret = -EREMOTEIO;
1081  out:
1082         i2c_pxa_set_slave(i2c, ret);
1083         return ret;
1084 }
1085
1086 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
1087 {
1088         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
1089                 I2C_FUNC_PROTOCOL_MANGLING | I2C_FUNC_NOSTART;
1090 }
1091
1092 static const struct i2c_algorithm i2c_pxa_algorithm = {
1093         .master_xfer    = i2c_pxa_xfer,
1094         .functionality  = i2c_pxa_functionality,
1095 };
1096
1097 static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
1098         .master_xfer    = i2c_pxa_pio_xfer,
1099         .functionality  = i2c_pxa_functionality,
1100 };
1101
1102 static const struct of_device_id i2c_pxa_dt_ids[] = {
1103         { .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
1104         { .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
1105         { .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA2XX },
1106         {}
1107 };
1108 MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
1109
1110 static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
1111                             enum pxa_i2c_types *i2c_types)
1112 {
1113         struct device_node *np = pdev->dev.of_node;
1114         const struct of_device_id *of_id =
1115                         of_match_device(i2c_pxa_dt_ids, &pdev->dev);
1116
1117         if (!of_id)
1118                 return 1;
1119
1120         /* For device tree we always use the dynamic or alias-assigned ID */
1121         i2c->adap.nr = -1;
1122
1123         if (of_get_property(np, "mrvl,i2c-polling", NULL))
1124                 i2c->use_pio = 1;
1125         if (of_get_property(np, "mrvl,i2c-fast-mode", NULL))
1126                 i2c->fast_mode = 1;
1127
1128         *i2c_types = (enum pxa_i2c_types)(of_id->data);
1129
1130         return 0;
1131 }
1132
1133 static int i2c_pxa_probe_pdata(struct platform_device *pdev,
1134                                struct pxa_i2c *i2c,
1135                                enum pxa_i2c_types *i2c_types)
1136 {
1137         struct i2c_pxa_platform_data *plat = dev_get_platdata(&pdev->dev);
1138         const struct platform_device_id *id = platform_get_device_id(pdev);
1139
1140         *i2c_types = id->driver_data;
1141         if (plat) {
1142                 i2c->use_pio = plat->use_pio;
1143                 i2c->fast_mode = plat->fast_mode;
1144                 i2c->high_mode = plat->high_mode;
1145                 i2c->master_code = plat->master_code;
1146                 if (!i2c->master_code)
1147                         i2c->master_code = 0xe;
1148                 i2c->rate = plat->rate;
1149         }
1150         return 0;
1151 }
1152
1153 static int i2c_pxa_probe(struct platform_device *dev)
1154 {
1155         struct i2c_pxa_platform_data *plat = dev_get_platdata(&dev->dev);
1156         enum pxa_i2c_types i2c_type;
1157         struct pxa_i2c *i2c;
1158         struct resource *res = NULL;
1159         int ret, irq;
1160
1161         i2c = devm_kzalloc(&dev->dev, sizeof(struct pxa_i2c), GFP_KERNEL);
1162         if (!i2c)
1163                 return -ENOMEM;
1164
1165         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1166         i2c->reg_base = devm_ioremap_resource(&dev->dev, res);
1167         if (IS_ERR(i2c->reg_base))
1168                 return PTR_ERR(i2c->reg_base);
1169
1170         irq = platform_get_irq(dev, 0);
1171         if (irq < 0) {
1172                 dev_err(&dev->dev, "no irq resource: %d\n", irq);
1173                 return irq;
1174         }
1175
1176         /* Default adapter num to device id; i2c_pxa_probe_dt can override. */
1177         i2c->adap.nr = dev->id;
1178
1179         ret = i2c_pxa_probe_dt(dev, i2c, &i2c_type);
1180         if (ret > 0)
1181                 ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type);
1182         if (ret < 0)
1183                 return ret;
1184
1185         i2c->adap.owner   = THIS_MODULE;
1186         i2c->adap.retries = 5;
1187
1188         spin_lock_init(&i2c->lock);
1189         init_waitqueue_head(&i2c->wait);
1190
1191         strlcpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name));
1192
1193         i2c->clk = devm_clk_get(&dev->dev, NULL);
1194         if (IS_ERR(i2c->clk)) {
1195                 dev_err(&dev->dev, "failed to get the clk: %ld\n", PTR_ERR(i2c->clk));
1196                 return PTR_ERR(i2c->clk);
1197         }
1198
1199         i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr;
1200         i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr;
1201         i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr;
1202         i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr;
1203         if (i2c_type != REGS_CE4100)
1204                 i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar;
1205
1206         i2c->iobase = res->start;
1207         i2c->iosize = resource_size(res);
1208
1209         i2c->irq = irq;
1210
1211         i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1212         i2c->highmode_enter = false;
1213
1214         if (plat) {
1215 #ifdef CONFIG_I2C_PXA_SLAVE
1216                 i2c->slave_addr = plat->slave_addr;
1217                 i2c->slave = plat->slave;
1218 #endif
1219                 i2c->adap.class = plat->class;
1220         }
1221
1222         if (i2c->high_mode) {
1223                 if (i2c->rate) {
1224                         clk_set_rate(i2c->clk, i2c->rate);
1225                         pr_info("i2c: <%s> set rate to %ld\n",
1226                                 i2c->adap.name, clk_get_rate(i2c->clk));
1227                 } else
1228                         pr_warn("i2c: <%s> clock rate not set\n",
1229                                 i2c->adap.name);
1230         }
1231
1232         clk_prepare_enable(i2c->clk);
1233
1234         if (i2c->use_pio) {
1235                 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1236         } else {
1237                 i2c->adap.algo = &i2c_pxa_algorithm;
1238                 ret = devm_request_irq(&dev->dev, irq, i2c_pxa_handler,
1239                                 IRQF_SHARED | IRQF_NO_SUSPEND,
1240                                 dev_name(&dev->dev), i2c);
1241                 if (ret) {
1242                         dev_err(&dev->dev, "failed to request irq: %d\n", ret);
1243                         goto ereqirq;
1244                 }
1245         }
1246
1247         i2c_pxa_reset(i2c);
1248
1249         i2c->adap.algo_data = i2c;
1250         i2c->adap.dev.parent = &dev->dev;
1251 #ifdef CONFIG_OF
1252         i2c->adap.dev.of_node = dev->dev.of_node;
1253 #endif
1254
1255         ret = i2c_add_numbered_adapter(&i2c->adap);
1256         if (ret < 0) {
1257                 dev_err(&dev->dev, "failed to add bus: %d\n", ret);
1258                 goto ereqirq;
1259         }
1260
1261         platform_set_drvdata(dev, i2c);
1262
1263 #ifdef CONFIG_I2C_PXA_SLAVE
1264         dev_info(&i2c->adap.dev, " PXA I2C adapter, slave address %d\n",
1265                 i2c->slave_addr);
1266 #else
1267         dev_info(&i2c->adap.dev, " PXA I2C adapter\n");
1268 #endif
1269         return 0;
1270
1271 ereqirq:
1272         clk_disable_unprepare(i2c->clk);
1273         return ret;
1274 }
1275
1276 static int i2c_pxa_remove(struct platform_device *dev)
1277 {
1278         struct pxa_i2c *i2c = platform_get_drvdata(dev);
1279
1280         i2c_del_adapter(&i2c->adap);
1281
1282         clk_disable_unprepare(i2c->clk);
1283
1284         return 0;
1285 }
1286
1287 #ifdef CONFIG_PM
1288 static int i2c_pxa_suspend_noirq(struct device *dev)
1289 {
1290         struct platform_device *pdev = to_platform_device(dev);
1291         struct pxa_i2c *i2c = platform_get_drvdata(pdev);
1292
1293         clk_disable(i2c->clk);
1294
1295         return 0;
1296 }
1297
1298 static int i2c_pxa_resume_noirq(struct device *dev)
1299 {
1300         struct platform_device *pdev = to_platform_device(dev);
1301         struct pxa_i2c *i2c = platform_get_drvdata(pdev);
1302
1303         clk_enable(i2c->clk);
1304         i2c_pxa_reset(i2c);
1305
1306         return 0;
1307 }
1308
1309 static const struct dev_pm_ops i2c_pxa_dev_pm_ops = {
1310         .suspend_noirq = i2c_pxa_suspend_noirq,
1311         .resume_noirq = i2c_pxa_resume_noirq,
1312 };
1313
1314 #define I2C_PXA_DEV_PM_OPS (&i2c_pxa_dev_pm_ops)
1315 #else
1316 #define I2C_PXA_DEV_PM_OPS NULL
1317 #endif
1318
1319 static struct platform_driver i2c_pxa_driver = {
1320         .probe          = i2c_pxa_probe,
1321         .remove         = i2c_pxa_remove,
1322         .driver         = {
1323                 .name   = "pxa2xx-i2c",
1324                 .pm     = I2C_PXA_DEV_PM_OPS,
1325                 .of_match_table = i2c_pxa_dt_ids,
1326         },
1327         .id_table       = i2c_pxa_id_table,
1328 };
1329
1330 static int __init i2c_adap_pxa_init(void)
1331 {
1332         return platform_driver_register(&i2c_pxa_driver);
1333 }
1334
1335 static void __exit i2c_adap_pxa_exit(void)
1336 {
1337         platform_driver_unregister(&i2c_pxa_driver);
1338 }
1339
1340 MODULE_LICENSE("GPL");
1341 MODULE_ALIAS("platform:pxa2xx-i2c");
1342
1343 subsys_initcall(i2c_adap_pxa_init);
1344 module_exit(i2c_adap_pxa_exit);