drivers/irqchip/irq-gic-v3-its.c

   1 /*
   2  * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/bitmap.h>
  19 #include <linux/cpu.h>
  20 #include <linux/delay.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/log2.h>
  23 #include <linux/mm.h>
  24 #include <linux/msi.h>
  25 #include <linux/of.h>
  26 #include <linux/of_address.h>
  27 #include <linux/of_irq.h>
  28 #include <linux/of_pci.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/percpu.h>
  31 #include <linux/slab.h>
  32
  33 #include <linux/irqchip.h>
  34 #include <linux/irqchip/arm-gic-v3.h>
  35
  36 #include <asm/cacheflush.h>
  37 #include <asm/cputype.h>
  38 #include <asm/exception.h>
  39
  40 #include "irq-gic-common.h"
  41
  42 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING           (1ULL << 0)
  43 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375       (1ULL << 1)
  44
  45 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING     (1 << 0)
  46
  47 /*
  48  * Collection structure - just an ID, and a redistributor address to
  49  * ping. We use one per CPU as a bag of interrupts assigned to this
  50  * CPU.
  51  */
  52 struct its_collection {
  53         u64                     target_address;
  54         u16                     col_id;
  55 };
  56
  57 /*
  58  * The ITS structure - contains most of the infrastructure, with the
  59  * top-level MSI domain, the command queue, the collections, and the
  60  * list of devices writing to it.
  61  */
  62 struct its_node {
  63         raw_spinlock_t          lock;
  64         struct list_head        entry;
  65         void __iomem            *base;
  66         unsigned long           phys_base;
  67         struct its_cmd_block    *cmd_base;
  68         struct its_cmd_block    *cmd_write;
  69         void                    *tables[GITS_BASER_NR_REGS];
  70         struct its_collection   *collections;
  71         struct list_head        its_device_list;
  72         u64                     flags;
  73         u32                     ite_size;
  74 };
  75
  76 #define ITS_ITT_ALIGN           SZ_256
  77
  78 struct event_lpi_map {
  79         unsigned long           *lpi_map;
  80         u16                     *col_map;
  81         irq_hw_number_t         lpi_base;
  82         int                     nr_lpis;
  83 };
  84
  85 /*
  86  * The ITS view of a device - belongs to an ITS, a collection, owns an
  87  * interrupt translation table, and a list of interrupts.
  88  */
  89 struct its_device {
  90         struct list_head        entry;
  91         struct its_node         *its;
  92         struct event_lpi_map    event_map;
  93         void                    *itt;
  94         u32                     nr_ites;
  95         u32                     device_id;
  96 };
  97
  98 static LIST_HEAD(its_nodes);
  99 static DEFINE_SPINLOCK(its_lock);
 100 static struct device_node *gic_root_node;
 101 static struct rdists *gic_rdists;
 102
 103 #define gic_data_rdist()                (raw_cpu_ptr(gic_rdists->rdist))
 104 #define gic_data_rdist_rd_base()        (gic_data_rdist()->rd_base)
 105
 106 static struct its_collection *dev_event_to_col(struct its_device *its_dev,
 107                                                u32 event)
 108 {
 109         struct its_node *its = its_dev->its;
 110
 111         return its->collections + its_dev->event_map.col_map[event];
 112 }
 113
 114 /*
 115  * ITS command descriptors - parameters to be encoded in a command
 116  * block.
 117  */
 118 struct its_cmd_desc {
 119         union {
 120                 struct {
 121                         struct its_device *dev;
 122                         u32 event_id;
 123                 } its_inv_cmd;
 124
 125                 struct {
 126                         struct its_device *dev;
 127                         u32 event_id;
 128                 } its_int_cmd;
 129
 130                 struct {
 131                         struct its_device *dev;
 132                         int valid;
 133                 } its_mapd_cmd;
 134
 135                 struct {
 136                         struct its_collection *col;
 137                         int valid;
 138                 } its_mapc_cmd;
 139
 140                 struct {
 141                         struct its_device *dev;
 142                         u32 phys_id;
 143                         u32 event_id;
 144                 } its_mapvi_cmd;
 145
 146                 struct {
 147                         struct its_device *dev;
 148                         struct its_collection *col;
 149                         u32 event_id;
 150                 } its_movi_cmd;
 151
 152                 struct {
 153                         struct its_device *dev;
 154                         u32 event_id;
 155                 } its_discard_cmd;
 156
 157                 struct {
 158                         struct its_collection *col;
 159                 } its_invall_cmd;
 160         };
 161 };
 162
 163 /*
 164  * The ITS command block, which is what the ITS actually parses.
 165  */
 166 struct its_cmd_block {
 167         u64     raw_cmd[4];
 168 };
 169
 170 #define ITS_CMD_QUEUE_SZ                SZ_64K
 171 #define ITS_CMD_QUEUE_NR_ENTRIES        (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
 172
 173 typedef struct its_collection *(*its_cmd_builder_t)(struct its_cmd_block *,
 174                                                     struct its_cmd_desc *);
 175
 176 static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
 177 {
 178         cmd->raw_cmd[0] &= ~0xffUL;
 179         cmd->raw_cmd[0] |= cmd_nr;
 180 }
 181
 182 static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
 183 {
 184         cmd->raw_cmd[0] &= BIT_ULL(32) - 1;
 185         cmd->raw_cmd[0] |= ((u64)devid) << 32;
 186 }
 187
 188 static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
 189 {
 190         cmd->raw_cmd[1] &= ~0xffffffffUL;
 191         cmd->raw_cmd[1] |= id;
 192 }
 193
 194 static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
 195 {
 196         cmd->raw_cmd[1] &= 0xffffffffUL;
 197         cmd->raw_cmd[1] |= ((u64)phys_id) << 32;
 198 }
 199
 200 static void its_encode_size(struct its_cmd_block *cmd, u8 size)
 201 {
 202         cmd->raw_cmd[1] &= ~0x1fUL;
 203         cmd->raw_cmd[1] |= size & 0x1f;
 204 }
 205
 206 static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
 207 {
 208         cmd->raw_cmd[2] &= ~0xffffffffffffUL;
 209         cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00UL;
 210 }
 211
 212 static void its_encode_valid(struct its_cmd_block *cmd, int valid)
 213 {
 214         cmd->raw_cmd[2] &= ~(1UL << 63);
 215         cmd->raw_cmd[2] |= ((u64)!!valid) << 63;
 216 }
 217
 218 static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
 219 {
 220         cmd->raw_cmd[2] &= ~(0xffffffffUL << 16);
 221         cmd->raw_cmd[2] |= (target_addr & (0xffffffffUL << 16));
 222 }
 223
 224 static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
 225 {
 226         cmd->raw_cmd[2] &= ~0xffffUL;
 227         cmd->raw_cmd[2] |= col;
 228 }
 229
 230 static inline void its_fixup_cmd(struct its_cmd_block *cmd)
 231 {
 232         /* Let's fixup BE commands */
 233         cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]);
 234         cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]);
 235         cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]);
 236         cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]);
 237 }
 238
 239 static struct its_collection *its_build_mapd_cmd(struct its_cmd_block *cmd,
 240                                                  struct its_cmd_desc *desc)
 241 {
 242         unsigned long itt_addr;
 243         u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
 244
 245         itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
 246         itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
 247
 248         its_encode_cmd(cmd, GITS_CMD_MAPD);
 249         its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
 250         its_encode_size(cmd, size - 1);
 251         its_encode_itt(cmd, itt_addr);
 252         its_encode_valid(cmd, desc->its_mapd_cmd.valid);
 253
 254         its_fixup_cmd(cmd);
 255
 256         return NULL;
 257 }
 258
 259 static struct its_collection *its_build_mapc_cmd(struct its_cmd_block *cmd,
 260                                                  struct its_cmd_desc *desc)
 261 {
 262         its_encode_cmd(cmd, GITS_CMD_MAPC);
 263         its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
 264         its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
 265         its_encode_valid(cmd, desc->its_mapc_cmd.valid);
 266
 267         its_fixup_cmd(cmd);
 268
 269         return desc->its_mapc_cmd.col;
 270 }
 271
 272 static struct its_collection *its_build_mapvi_cmd(struct its_cmd_block *cmd,
 273                                                   struct its_cmd_desc *desc)
 274 {
 275         struct its_collection *col;
 276
 277         col = dev_event_to_col(desc->its_mapvi_cmd.dev,
 278                                desc->its_mapvi_cmd.event_id);
 279
 280         its_encode_cmd(cmd, GITS_CMD_MAPVI);
 281         its_encode_devid(cmd, desc->its_mapvi_cmd.dev->device_id);
 282         its_encode_event_id(cmd, desc->its_mapvi_cmd.event_id);
 283         its_encode_phys_id(cmd, desc->its_mapvi_cmd.phys_id);
 284         its_encode_collection(cmd, col->col_id);
 285
 286         its_fixup_cmd(cmd);
 287
 288         return col;
 289 }
 290
 291 static struct its_collection *its_build_movi_cmd(struct its_cmd_block *cmd,
 292                                                  struct its_cmd_desc *desc)
 293 {
 294         struct its_collection *col;
 295
 296         col = dev_event_to_col(desc->its_movi_cmd.dev,
 297                                desc->its_movi_cmd.event_id);
 298
 299         its_encode_cmd(cmd, GITS_CMD_MOVI);
 300         its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
 301         its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
 302         its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
 303
 304         its_fixup_cmd(cmd);
 305
 306         return col;
 307 }
 308
 309 static struct its_collection *its_build_discard_cmd(struct its_cmd_block *cmd,
 310                                                     struct its_cmd_desc *desc)
 311 {
 312         struct its_collection *col;
 313
 314         col = dev_event_to_col(desc->its_discard_cmd.dev,
 315                                desc->its_discard_cmd.event_id);
 316
 317         its_encode_cmd(cmd, GITS_CMD_DISCARD);
 318         its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
 319         its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
 320
 321         its_fixup_cmd(cmd);
 322
 323         return col;
 324 }
 325
 326 static struct its_collection *its_build_inv_cmd(struct its_cmd_block *cmd,
 327                                                 struct its_cmd_desc *desc)
 328 {
 329         struct its_collection *col;
 330
 331         col = dev_event_to_col(desc->its_inv_cmd.dev,
 332                                desc->its_inv_cmd.event_id);
 333
 334         its_encode_cmd(cmd, GITS_CMD_INV);
 335         its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
 336         its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
 337
 338         its_fixup_cmd(cmd);
 339
 340         return col;
 341 }
 342
 343 static struct its_collection *its_build_invall_cmd(struct its_cmd_block *cmd,
 344                                                    struct its_cmd_desc *desc)
 345 {
 346         its_encode_cmd(cmd, GITS_CMD_INVALL);
 347         its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
 348
 349         its_fixup_cmd(cmd);
 350
 351         return NULL;
 352 }
 353
 354 static u64 its_cmd_ptr_to_offset(struct its_node *its,
 355                                  struct its_cmd_block *ptr)
 356 {
 357         return (ptr - its->cmd_base) * sizeof(*ptr);
 358 }
 359
 360 static int its_queue_full(struct its_node *its)
 361 {
 362         int widx;
 363         int ridx;
 364
 365         widx = its->cmd_write - its->cmd_base;
 366         ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
 367
 368         /* This is incredibly unlikely to happen, unless the ITS locks up. */
 369         if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
 370                 return 1;
 371
 372         return 0;
 373 }
 374
 375 static struct its_cmd_block *its_allocate_entry(struct its_node *its)
 376 {
 377         struct its_cmd_block *cmd;
 378         u32 count = 1000000;    /* 1s! */
 379
 380         while (its_queue_full(its)) {
 381                 count--;
 382                 if (!count) {
 383                         pr_err_ratelimited("ITS queue not draining\n");
 384                         return NULL;
 385                 }
 386                 cpu_relax();
 387                 udelay(1);
 388         }
 389
 390         cmd = its->cmd_write++;
 391
 392         /* Handle queue wrapping */
 393         if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
 394                 its->cmd_write = its->cmd_base;
 395
 396         return cmd;
 397 }
 398
 399 static struct its_cmd_block *its_post_commands(struct its_node *its)
 400 {
 401         u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
 402
 403         writel_relaxed(wr, its->base + GITS_CWRITER);
 404
 405         return its->cmd_write;
 406 }
 407
 408 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
 409 {
 410         /*
 411          * Make sure the commands written to memory are observable by
 412          * the ITS.
 413          */
 414         if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
 415                 __flush_dcache_area(cmd, sizeof(*cmd));
 416         else
 417                 dsb(ishst);
 418 }
 419
 420 static void its_wait_for_range_completion(struct its_node *its,
 421                                           struct its_cmd_block *from,
 422                                           struct its_cmd_block *to)
 423 {
 424         u64 rd_idx, from_idx, to_idx;
 425         u32 count = 1000000;    /* 1s! */
 426
 427         from_idx = its_cmd_ptr_to_offset(its, from);
 428         to_idx = its_cmd_ptr_to_offset(its, to);
 429
 430         while (1) {
 431                 rd_idx = readl_relaxed(its->base + GITS_CREADR);
 432                 if (rd_idx >= to_idx || rd_idx < from_idx)
 433                         break;
 434
 435                 count--;
 436                 if (!count) {
 437                         pr_err_ratelimited("ITS queue timeout\n");
 438                         return;
 439                 }
 440                 cpu_relax();
 441                 udelay(1);
 442         }
 443 }
 444
 445 static void its_send_single_command(struct its_node *its,
 446                                     its_cmd_builder_t builder,
 447                                     struct its_cmd_desc *desc)
 448 {
 449         struct its_cmd_block *cmd, *sync_cmd, *next_cmd;
 450         struct its_collection *sync_col;
 451         unsigned long flags;
 452
 453         raw_spin_lock_irqsave(&its->lock, flags);
 454
 455         cmd = its_allocate_entry(its);
 456         if (!cmd) {             /* We're soooooo screewed... */
 457                 pr_err_ratelimited("ITS can't allocate, dropping command\n");
 458                 raw_spin_unlock_irqrestore(&its->lock, flags);
 459                 return;
 460         }
 461         sync_col = builder(cmd, desc);
 462         its_flush_cmd(its, cmd);
 463
 464         if (sync_col) {
 465                 sync_cmd = its_allocate_entry(its);
 466                 if (!sync_cmd) {
 467                         pr_err_ratelimited("ITS can't SYNC, skipping\n");
 468                         goto post;
 469                 }
 470                 its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
 471                 its_encode_target(sync_cmd, sync_col->target_address);
 472                 its_fixup_cmd(sync_cmd);
 473                 its_flush_cmd(its, sync_cmd);
 474         }
 475
 476 post:
 477         next_cmd = its_post_commands(its);
 478         raw_spin_unlock_irqrestore(&its->lock, flags);
 479
 480         its_wait_for_range_completion(its, cmd, next_cmd);
 481 }
 482
 483 static void its_send_inv(struct its_device *dev, u32 event_id)
 484 {
 485         struct its_cmd_desc desc;
 486
 487         desc.its_inv_cmd.dev = dev;
 488         desc.its_inv_cmd.event_id = event_id;
 489
 490         its_send_single_command(dev->its, its_build_inv_cmd, &desc);
 491 }
 492
 493 static void its_send_mapd(struct its_device *dev, int valid)
 494 {
 495         struct its_cmd_desc desc;
 496
 497         desc.its_mapd_cmd.dev = dev;
 498         desc.its_mapd_cmd.valid = !!valid;
 499
 500         its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
 501 }
 502
 503 static void its_send_mapc(struct its_node *its, struct its_collection *col,
 504                           int valid)
 505 {
 506         struct its_cmd_desc desc;
 507
 508         desc.its_mapc_cmd.col = col;
 509         desc.its_mapc_cmd.valid = !!valid;
 510
 511         its_send_single_command(its, its_build_mapc_cmd, &desc);
 512 }
 513
 514 static void its_send_mapvi(struct its_device *dev, u32 irq_id, u32 id)
 515 {
 516         struct its_cmd_desc desc;
 517
 518         desc.its_mapvi_cmd.dev = dev;
 519         desc.its_mapvi_cmd.phys_id = irq_id;
 520         desc.its_mapvi_cmd.event_id = id;
 521
 522         its_send_single_command(dev->its, its_build_mapvi_cmd, &desc);
 523 }
 524
 525 static void its_send_movi(struct its_device *dev,
 526                           struct its_collection *col, u32 id)
 527 {
 528         struct its_cmd_desc desc;
 529
 530         desc.its_movi_cmd.dev = dev;
 531         desc.its_movi_cmd.col = col;
 532         desc.its_movi_cmd.event_id = id;
 533
 534         its_send_single_command(dev->its, its_build_movi_cmd, &desc);
 535 }
 536
 537 static void its_send_discard(struct its_device *dev, u32 id)
 538 {
 539         struct its_cmd_desc desc;
 540
 541         desc.its_discard_cmd.dev = dev;
 542         desc.its_discard_cmd.event_id = id;
 543
 544         its_send_single_command(dev->its, its_build_discard_cmd, &desc);
 545 }
 546
 547 static void its_send_invall(struct its_node *its, struct its_collection *col)
 548 {
 549         struct its_cmd_desc desc;
 550
 551         desc.its_invall_cmd.col = col;
 552
 553         its_send_single_command(its, its_build_invall_cmd, &desc);
 554 }
 555
 556 /*
 557  * irqchip functions - assumes MSI, mostly.
 558  */
 559
 560 static inline u32 its_get_event_id(struct irq_data *d)
 561 {
 562         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
 563         return d->hwirq - its_dev->event_map.lpi_base;
 564 }
 565
 566 static void lpi_set_config(struct irq_data *d, bool enable)
 567 {
 568         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
 569         irq_hw_number_t hwirq = d->hwirq;
 570         u32 id = its_get_event_id(d);
 571         u8 *cfg = page_address(gic_rdists->prop_page) + hwirq - 8192;
 572
 573         if (enable)
 574                 *cfg |= LPI_PROP_ENABLED;
 575         else
 576                 *cfg &= ~LPI_PROP_ENABLED;
 577
 578         /*
 579          * Make the above write visible to the redistributors.
 580          * And yes, we're flushing exactly: One. Single. Byte.
 581          * Humpf...
 582          */
 583         if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
 584                 __flush_dcache_area(cfg, sizeof(*cfg));
 585         else
 586                 dsb(ishst);
 587         its_send_inv(its_dev, id);
 588 }
 589
 590 static void its_mask_irq(struct irq_data *d)
 591 {
 592         lpi_set_config(d, false);
 593 }
 594
 595 static void its_unmask_irq(struct irq_data *d)
 596 {
 597         lpi_set_config(d, true);
 598 }
 599
 600 static void its_eoi_irq(struct irq_data *d)
 601 {
 602         gic_write_eoir(d->hwirq);
 603 }
 604
 605 static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 606                             bool force)
 607 {
 608         unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
 609         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
 610         struct its_collection *target_col;
 611         u32 id = its_get_event_id(d);
 612
 613         if (cpu >= nr_cpu_ids)
 614                 return -EINVAL;
 615
 616         target_col = &its_dev->its->collections[cpu];
 617         its_send_movi(its_dev, target_col, id);
 618         its_dev->event_map.col_map[id] = cpu;
 619
 620         return IRQ_SET_MASK_OK_DONE;
 621 }
 622
 623 static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
 624 {
 625         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
 626         struct its_node *its;
 627         u64 addr;
 628
 629         its = its_dev->its;
 630         addr = its->phys_base + GITS_TRANSLATER;
 631
 632         msg->address_lo         = addr & ((1UL << 32) - 1);
 633         msg->address_hi         = addr >> 32;
 634         msg->data               = its_get_event_id(d);
 635 }
 636
 637 static struct irq_chip its_irq_chip = {
 638         .name                   = "ITS",
 639         .irq_mask               = its_mask_irq,
 640         .irq_unmask             = its_unmask_irq,
 641         .irq_eoi                = its_eoi_irq,
 642         .irq_set_affinity       = its_set_affinity,
 643         .irq_compose_msi_msg    = its_irq_compose_msi_msg,
 644 };
 645
 646 /*
 647  * How we allocate LPIs:
 648  *
 649  * The GIC has id_bits bits for interrupt identifiers. From there, we
 650  * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as
 651  * we allocate LPIs by chunks of 32, we can shift the whole thing by 5
 652  * bits to the right.
 653  *
 654  * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations.
 655  */
 656 #define IRQS_PER_CHUNK_SHIFT    5
 657 #define IRQS_PER_CHUNK          (1 << IRQS_PER_CHUNK_SHIFT)
 658
 659 static unsigned long *lpi_bitmap;
 660 static u32 lpi_chunks;
 661 static DEFINE_SPINLOCK(lpi_lock);
 662
 663 static int its_lpi_to_chunk(int lpi)
 664 {
 665         return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT;
 666 }
 667
 668 static int its_chunk_to_lpi(int chunk)
 669 {
 670         return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192;
 671 }
 672
 673 static int its_lpi_init(u32 id_bits)
 674 {
 675         lpi_chunks = its_lpi_to_chunk(1UL << id_bits);
 676
 677         lpi_bitmap = kzalloc(BITS_TO_LONGS(lpi_chunks) * sizeof(long),
 678                              GFP_KERNEL);
 679         if (!lpi_bitmap) {
 680                 lpi_chunks = 0;
 681                 return -ENOMEM;
 682         }
 683
 684         pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks);
 685         return 0;
 686 }
 687
 688 static unsigned long *its_lpi_alloc_chunks(int nr_irqs, int *base, int *nr_ids)
 689 {
 690         unsigned long *bitmap = NULL;
 691         int chunk_id;
 692         int nr_chunks;
 693         int i;
 694
 695         nr_chunks = DIV_ROUND_UP(nr_irqs, IRQS_PER_CHUNK);
 696
 697         spin_lock(&lpi_lock);
 698
 699         do {
 700                 chunk_id = bitmap_find_next_zero_area(lpi_bitmap, lpi_chunks,
 701                                                       0, nr_chunks, 0);
 702                 if (chunk_id < lpi_chunks)
 703                         break;
 704
 705                 nr_chunks--;
 706         } while (nr_chunks > 0);
 707
 708         if (!nr_chunks)
 709                 goto out;
 710
 711         bitmap = kzalloc(BITS_TO_LONGS(nr_chunks * IRQS_PER_CHUNK) * sizeof (long),
 712                          GFP_ATOMIC);
 713         if (!bitmap)
 714                 goto out;
 715
 716         for (i = 0; i < nr_chunks; i++)
 717                 set_bit(chunk_id + i, lpi_bitmap);
 718
 719         *base = its_chunk_to_lpi(chunk_id);
 720         *nr_ids = nr_chunks * IRQS_PER_CHUNK;
 721
 722 out:
 723         spin_unlock(&lpi_lock);
 724
 725         if (!bitmap)
 726                 *base = *nr_ids = 0;
 727
 728         return bitmap;
 729 }
 730
 731 static void its_lpi_free(struct event_lpi_map *map)
 732 {
 733         int base = map->lpi_base;
 734         int nr_ids = map->nr_lpis;
 735         int lpi;
 736
 737         spin_lock(&lpi_lock);
 738
 739         for (lpi = base; lpi < (base + nr_ids); lpi += IRQS_PER_CHUNK) {
 740                 int chunk = its_lpi_to_chunk(lpi);
 741                 BUG_ON(chunk > lpi_chunks);
 742                 if (test_bit(chunk, lpi_bitmap)) {
 743                         clear_bit(chunk, lpi_bitmap);
 744                 } else {
 745                         pr_err("Bad LPI chunk %d\n", chunk);
 746                 }
 747         }
 748
 749         spin_unlock(&lpi_lock);
 750
 751         kfree(map->lpi_map);
 752         kfree(map->col_map);
 753 }
 754
 755 /*
 756  * We allocate 64kB for PROPBASE. That gives us at most 64K LPIs to
 757  * deal with (one configuration byte per interrupt). PENDBASE has to
 758  * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
 759  */
 760 #define LPI_PROPBASE_SZ         SZ_64K
 761 #define LPI_PENDBASE_SZ         (LPI_PROPBASE_SZ / 8 + SZ_1K)
 762
 763 /*
 764  * This is how many bits of ID we need, including the useless ones.
 765  */
 766 #define LPI_NRBITS              ilog2(LPI_PROPBASE_SZ + SZ_8K)
 767
 768 #define LPI_PROP_DEFAULT_PRIO   0xa0
 769
 770 static int __init its_alloc_lpi_tables(void)
 771 {
 772         phys_addr_t paddr;
 773
 774         gic_rdists->prop_page = alloc_pages(GFP_NOWAIT,
 775                                            get_order(LPI_PROPBASE_SZ));
 776         if (!gic_rdists->prop_page) {
 777                 pr_err("Failed to allocate PROPBASE\n");
 778                 return -ENOMEM;
 779         }
 780
 781         paddr = page_to_phys(gic_rdists->prop_page);
 782         pr_info("GIC: using LPI property table @%pa\n", &paddr);
 783
 784         /* Priority 0xa0, Group-1, disabled */
 785         memset(page_address(gic_rdists->prop_page),
 786                LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1,
 787                LPI_PROPBASE_SZ);
 788
 789         /* Make sure the GIC will observe the written configuration */
 790         __flush_dcache_area(page_address(gic_rdists->prop_page), LPI_PROPBASE_SZ);
 791
 792         return 0;
 793 }
 794
 795 static const char *its_base_type_string[] = {
 796         [GITS_BASER_TYPE_DEVICE]        = "Devices",
 797         [GITS_BASER_TYPE_VCPU]          = "Virtual CPUs",
 798         [GITS_BASER_TYPE_CPU]           = "Physical CPUs",
 799         [GITS_BASER_TYPE_COLLECTION]    = "Interrupt Collections",
 800         [GITS_BASER_TYPE_RESERVED5]     = "Reserved (5)",
 801         [GITS_BASER_TYPE_RESERVED6]     = "Reserved (6)",
 802         [GITS_BASER_TYPE_RESERVED7]     = "Reserved (7)",
 803 };
 804
 805 static void its_free_tables(struct its_node *its)
 806 {
 807         int i;
 808
 809         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
 810                 if (its->tables[i]) {
 811                         free_page((unsigned long)its->tables[i]);
 812                         its->tables[i] = NULL;
 813                 }
 814         }
 815 }
 816
 817 static int its_alloc_tables(const char *node_name, struct its_node *its)
 818 {
 819         int err;
 820         int i;
 821         int psz = SZ_64K;
 822         u64 shr = GITS_BASER_InnerShareable;
 823         u64 cache;
 824         u64 typer;
 825         u32 ids;
 826
 827         if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) {
 828                 /*
 829                  * erratum 22375: only alloc 8MB table size
 830                  * erratum 24313: ignore memory access type
 831                  */
 832                 cache   = 0;
 833                 ids     = 0x14;                 /* 20 bits, 8MB */
 834         } else {
 835                 cache   = GITS_BASER_WaWb;
 836                 typer   = readq_relaxed(its->base + GITS_TYPER);
 837                 ids     = GITS_TYPER_DEVBITS(typer);
 838         }
 839
 840         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
 841                 u64 val = readq_relaxed(its->base + GITS_BASER + i * 8);
 842                 u64 type = GITS_BASER_TYPE(val);
 843                 u64 entry_size = GITS_BASER_ENTRY_SIZE(val);
 844                 int order = get_order(psz);
 845                 int alloc_size;
 846                 int alloc_pages;
 847                 u64 tmp;
 848                 void *base;
 849
 850                 if (type == GITS_BASER_TYPE_NONE)
 851                         continue;
 852
 853                 /*
 854                  * Allocate as many entries as required to fit the
 855                  * range of device IDs that the ITS can grok... The ID
 856                  * space being incredibly sparse, this results in a
 857                  * massive waste of memory.
 858                  *
 859                  * For other tables, only allocate a single page.
 860                  */
 861                 if (type == GITS_BASER_TYPE_DEVICE) {
 862                         /*
 863                          * 'order' was initialized earlier to the default page
 864                          * granule of the the ITS.  We can't have an allocation
 865                          * smaller than that.  If the requested allocation
 866                          * is smaller, round up to the default page granule.
 867                          */
 868                         order = max(get_order((1UL << ids) * entry_size),
 869                                     order);
 870                         if (order >= MAX_ORDER) {
 871                                 order = MAX_ORDER - 1;
 872                                 pr_warn("%s: Device Table too large, reduce its page order to %u\n",
 873                                         node_name, order);
 874                         }
 875                 }
 876
 877                 alloc_size = (1 << order) * PAGE_SIZE;
 878                 alloc_pages = (alloc_size / psz);
 879                 if (alloc_pages > GITS_BASER_PAGES_MAX) {
 880                         alloc_pages = GITS_BASER_PAGES_MAX;
 881                         order = get_order(GITS_BASER_PAGES_MAX * psz);
 882                         pr_warn("%s: Device Table too large, reduce its page order to %u (%u pages)\n",
 883                                 node_name, order, alloc_pages);
 884                 }
 885
 886                 base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
 887                 if (!base) {
 888                         err = -ENOMEM;
 889                         goto out_free;
 890                 }
 891
 892                 its->tables[i] = base;
 893
 894 retry_baser:
 895                 val = (virt_to_phys(base)                                |
 896                        (type << GITS_BASER_TYPE_SHIFT)                   |
 897                        ((entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
 898                        cache                                             |
 899                        shr                                               |
 900                        GITS_BASER_VALID);
 901
 902                 switch (psz) {
 903                 case SZ_4K:
 904                         val |= GITS_BASER_PAGE_SIZE_4K;
 905                         break;
 906                 case SZ_16K:
 907                         val |= GITS_BASER_PAGE_SIZE_16K;
 908                         break;
 909                 case SZ_64K:
 910                         val |= GITS_BASER_PAGE_SIZE_64K;
 911                         break;
 912                 }
 913
 914                 val |= alloc_pages - 1;
 915
 916                 writeq_relaxed(val, its->base + GITS_BASER + i * 8);
 917                 tmp = readq_relaxed(its->base + GITS_BASER + i * 8);
 918
 919                 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
 920                         /*
 921                          * Shareability didn't stick. Just use
 922                          * whatever the read reported, which is likely
 923                          * to be the only thing this redistributor
 924                          * supports. If that's zero, make it
 925                          * non-cacheable as well.
 926                          */
 927                         shr = tmp & GITS_BASER_SHAREABILITY_MASK;
 928                         if (!shr) {
 929                                 cache = GITS_BASER_nC;
 930                                 __flush_dcache_area(base, alloc_size);
 931                         }
 932                         goto retry_baser;
 933                 }
 934
 935                 if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
 936                         /*
 937                          * Page size didn't stick. Let's try a smaller
 938                          * size and retry. If we reach 4K, then
 939                          * something is horribly wrong...
 940                          */
 941                         switch (psz) {
 942                         case SZ_16K:
 943                                 psz = SZ_4K;
 944                                 goto retry_baser;
 945                         case SZ_64K:
 946                                 psz = SZ_16K;
 947                                 goto retry_baser;
 948                         }
 949                 }
 950
 951                 if (val != tmp) {
 952                         pr_err("ITS: %s: GITS_BASER%d doesn't stick: %lx %lx\n",
 953                                node_name, i,
 954                                (unsigned long) val, (unsigned long) tmp);
 955                         err = -ENXIO;
 956                         goto out_free;
 957                 }
 958
 959                 pr_info("ITS: allocated %d %s @%lx (psz %dK, shr %d)\n",
 960                         (int)(alloc_size / entry_size),
 961                         its_base_type_string[type],
 962                         (unsigned long)virt_to_phys(base),
 963                         psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
 964         }
 965
 966         return 0;
 967
 968 out_free:
 969         its_free_tables(its);
 970
 971         return err;
 972 }
 973
 974 static int its_alloc_collections(struct its_node *its)
 975 {
 976         its->collections = kzalloc(nr_cpu_ids * sizeof(*its->collections),
 977                                    GFP_KERNEL);
 978         if (!its->collections)
 979                 return -ENOMEM;
 980
 981         return 0;
 982 }
 983
 984 static void its_cpu_init_lpis(void)
 985 {
 986         void __iomem *rbase = gic_data_rdist_rd_base();
 987         struct page *pend_page;
 988         u64 val, tmp;
 989
 990         /* If we didn't allocate the pending table yet, do it now */
 991         pend_page = gic_data_rdist()->pend_page;
 992         if (!pend_page) {
 993                 phys_addr_t paddr;
 994                 /*
 995                  * The pending pages have to be at least 64kB aligned,
 996                  * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below.
 997                  */
 998                 pend_page = alloc_pages(GFP_NOWAIT | __GFP_ZERO,
 999                                         get_order(max(LPI_PENDBASE_SZ, SZ_64K)));
1000                 if (!pend_page) {
1001                         pr_err("Failed to allocate PENDBASE for CPU%d\n",
1002                                smp_processor_id());
1003                         return;
1004                 }
1005
1006                 /* Make sure the GIC will observe the zero-ed page */
1007                 __flush_dcache_area(page_address(pend_page), LPI_PENDBASE_SZ);
1008
1009                 paddr = page_to_phys(pend_page);
1010                 pr_info("CPU%d: using LPI pending table @%pa\n",
1011                         smp_processor_id(), &paddr);
1012                 gic_data_rdist()->pend_page = pend_page;
1013         }
1014
1015         /* Disable LPIs */
1016         val = readl_relaxed(rbase + GICR_CTLR);
1017         val &= ~GICR_CTLR_ENABLE_LPIS;
1018         writel_relaxed(val, rbase + GICR_CTLR);
1019
1020         /*
1021          * Make sure any change to the table is observable by the GIC.
1022          */
1023         dsb(sy);
1024
1025         /* set PROPBASE */
1026         val = (page_to_phys(gic_rdists->prop_page) |
1027                GICR_PROPBASER_InnerShareable |
1028                GICR_PROPBASER_WaWb |
1029                ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
1030
1031         writeq_relaxed(val, rbase + GICR_PROPBASER);
1032         tmp = readq_relaxed(rbase + GICR_PROPBASER);
1033
1034         if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
1035                 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
1036                         /*
1037                          * The HW reports non-shareable, we must
1038                          * remove the cacheability attributes as
1039                          * well.
1040                          */
1041                         val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
1042                                  GICR_PROPBASER_CACHEABILITY_MASK);
1043                         val |= GICR_PROPBASER_nC;
1044                         writeq_relaxed(val, rbase + GICR_PROPBASER);
1045                 }
1046                 pr_info_once("GIC: using cache flushing for LPI property table\n");
1047                 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
1048         }
1049
1050         /* set PENDBASE */
1051         val = (page_to_phys(pend_page) |
1052                GICR_PENDBASER_InnerShareable |
1053                GICR_PENDBASER_WaWb);
1054
1055         writeq_relaxed(val, rbase + GICR_PENDBASER);
1056         tmp = readq_relaxed(rbase + GICR_PENDBASER);
1057
1058         if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
1059                 /*
1060                  * The HW reports non-shareable, we must remove the
1061                  * cacheability attributes as well.
1062                  */
1063                 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
1064                          GICR_PENDBASER_CACHEABILITY_MASK);
1065                 val |= GICR_PENDBASER_nC;
1066                 writeq_relaxed(val, rbase + GICR_PENDBASER);
1067         }
1068
1069         /* Enable LPIs */
1070         val = readl_relaxed(rbase + GICR_CTLR);
1071         val |= GICR_CTLR_ENABLE_LPIS;
1072         writel_relaxed(val, rbase + GICR_CTLR);
1073
1074         /* Make sure the GIC has seen the above */
1075         dsb(sy);
1076 }
1077
1078 static void its_cpu_init_collection(void)
1079 {
1080         struct its_node *its;
1081         int cpu;
1082
1083         spin_lock(&its_lock);
1084         cpu = smp_processor_id();
1085
1086         list_for_each_entry(its, &its_nodes, entry) {
1087                 u64 target;
1088
1089                 /*
1090                  * We now have to bind each collection to its target
1091                  * redistributor.
1092                  */
1093                 if (readq_relaxed(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
1094                         /*
1095                          * This ITS wants the physical address of the
1096                          * redistributor.
1097                          */
1098                         target = gic_data_rdist()->phys_base;
1099                 } else {
1100                         /*
1101                          * This ITS wants a linear CPU number.
1102                          */
1103                         target = readq_relaxed(gic_data_rdist_rd_base() + GICR_TYPER);
1104                         target = GICR_TYPER_CPU_NUMBER(target) << 16;
1105                 }
1106
1107                 /* Perform collection mapping */
1108                 its->collections[cpu].target_address = target;
1109                 its->collections[cpu].col_id = cpu;
1110
1111                 its_send_mapc(its, &its->collections[cpu], 1);
1112                 its_send_invall(its, &its->collections[cpu]);
1113         }
1114
1115         spin_unlock(&its_lock);
1116 }
1117
1118 static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
1119 {
1120         struct its_device *its_dev = NULL, *tmp;
1121         unsigned long flags;
1122
1123         raw_spin_lock_irqsave(&its->lock, flags);
1124
1125         list_for_each_entry(tmp, &its->its_device_list, entry) {
1126                 if (tmp->device_id == dev_id) {
1127                         its_dev = tmp;
1128                         break;
1129                 }
1130         }
1131
1132         raw_spin_unlock_irqrestore(&its->lock, flags);
1133
1134         return its_dev;
1135 }
1136
1137 static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
1138                                             int nvecs)
1139 {
1140         struct its_device *dev;
1141         unsigned long *lpi_map;
1142         unsigned long flags;
1143         u16 *col_map = NULL;
1144         void *itt;
1145         int lpi_base;
1146         int nr_lpis;
1147         int nr_ites;
1148         int sz;
1149
1150         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1151         /*
1152          * At least one bit of EventID is being used, hence a minimum
1153          * of two entries. No, the architecture doesn't let you
1154          * express an ITT with a single entry.
1155          */
1156         nr_ites = max(2UL, roundup_pow_of_two(nvecs));
1157         sz = nr_ites * its->ite_size;
1158         sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
1159         itt = kzalloc(sz, GFP_KERNEL);
1160         lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis);
1161         if (lpi_map)
1162                 col_map = kzalloc(sizeof(*col_map) * nr_lpis, GFP_KERNEL);
1163
1164         if (!dev || !itt || !lpi_map || !col_map) {
1165                 kfree(dev);
1166                 kfree(itt);
1167                 kfree(lpi_map);
1168                 kfree(col_map);
1169                 return NULL;
1170         }
1171
1172         __flush_dcache_area(itt, sz);
1173
1174         dev->its = its;
1175         dev->itt = itt;
1176         dev->nr_ites = nr_ites;
1177         dev->event_map.lpi_map = lpi_map;
1178         dev->event_map.col_map = col_map;
1179         dev->event_map.lpi_base = lpi_base;
1180         dev->event_map.nr_lpis = nr_lpis;
1181         dev->device_id = dev_id;
1182         INIT_LIST_HEAD(&dev->entry);
1183
1184         raw_spin_lock_irqsave(&its->lock, flags);
1185         list_add(&dev->entry, &its->its_device_list);
1186         raw_spin_unlock_irqrestore(&its->lock, flags);
1187
1188         /* Map device to its ITT */
1189         its_send_mapd(dev, 1);
1190
1191         return dev;
1192 }
1193
1194 static void its_free_device(struct its_device *its_dev)
1195 {
1196         unsigned long flags;
1197
1198         raw_spin_lock_irqsave(&its_dev->its->lock, flags);
1199         list_del(&its_dev->entry);
1200         raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
1201         kfree(its_dev->itt);
1202         kfree(its_dev);
1203 }
1204
1205 static int its_alloc_device_irq(struct its_device *dev, irq_hw_number_t *hwirq)
1206 {
1207         int idx;
1208
1209         idx = find_first_zero_bit(dev->event_map.lpi_map,
1210                                   dev->event_map.nr_lpis);
1211         if (idx == dev->event_map.nr_lpis)
1212                 return -ENOSPC;
1213
1214         *hwirq = dev->event_map.lpi_base + idx;
1215         set_bit(idx, dev->event_map.lpi_map);
1216
1217         return 0;
1218 }
1219
1220 static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
1221                            int nvec, msi_alloc_info_t *info)
1222 {
1223         struct its_node *its;
1224         struct its_device *its_dev;
1225         struct msi_domain_info *msi_info;
1226         u32 dev_id;
1227
1228         /*
1229          * We ignore "dev" entierely, and rely on the dev_id that has
1230          * been passed via the scratchpad. This limits this domain's
1231          * usefulness to upper layers that definitely know that they
1232          * are built on top of the ITS.
1233          */
1234         dev_id = info->scratchpad[0].ul;
1235
1236         msi_info = msi_get_domain_info(domain);
1237         its = msi_info->data;
1238
1239         its_dev = its_find_device(its, dev_id);
1240         if (its_dev) {
1241                 /*
1242                  * We already have seen this ID, probably through
1243                  * another alias (PCI bridge of some sort). No need to
1244                  * create the device.
1245                  */
1246                 pr_debug("Reusing ITT for devID %x\n", dev_id);
1247                 goto out;
1248         }
1249
1250         its_dev = its_create_device(its, dev_id, nvec);
1251         if (!its_dev)
1252                 return -ENOMEM;
1253
1254         pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
1255 out:
1256         info->scratchpad[0].ptr = its_dev;
1257         return 0;
1258 }
1259
1260 static struct msi_domain_ops its_msi_domain_ops = {
1261         .msi_prepare    = its_msi_prepare,
1262 };
1263
1264 static int its_irq_gic_domain_alloc(struct irq_domain *domain,
1265                                     unsigned int virq,
1266                                     irq_hw_number_t hwirq)
1267 {
1268         struct irq_fwspec fwspec;
1269
1270         if (irq_domain_get_of_node(domain->parent)) {
1271                 fwspec.fwnode = domain->parent->fwnode;
1272                 fwspec.param_count = 3;
1273                 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
1274                 fwspec.param[1] = hwirq;
1275                 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
1276         } else {
1277                 return -EINVAL;
1278         }
1279
1280         return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
1281 }
1282
1283 static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1284                                 unsigned int nr_irqs, void *args)
1285 {
1286         msi_alloc_info_t *info = args;
1287         struct its_device *its_dev = info->scratchpad[0].ptr;
1288         irq_hw_number_t hwirq;
1289         int err;
1290         int i;
1291
1292         for (i = 0; i < nr_irqs; i++) {
1293                 err = its_alloc_device_irq(its_dev, &hwirq);
1294                 if (err)
1295                         return err;
1296
1297                 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq);
1298                 if (err)
1299                         return err;
1300
1301                 irq_domain_set_hwirq_and_chip(domain, virq + i,
1302                                               hwirq, &its_irq_chip, its_dev);
1303                 pr_debug("ID:%d pID:%d vID:%d\n",
1304                          (int)(hwirq - its_dev->event_map.lpi_base),
1305                          (int) hwirq, virq + i);
1306         }
1307
1308         return 0;
1309 }
1310
1311 static void its_irq_domain_activate(struct irq_domain *domain,
1312                                     struct irq_data *d)
1313 {
1314         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1315         u32 event = its_get_event_id(d);
1316
1317         /* Bind the LPI to the first possible CPU */
1318         its_dev->event_map.col_map[event] = cpumask_first(cpu_online_mask);
1319
1320         /* Map the GIC IRQ and event to the device */
1321         its_send_mapvi(its_dev, d->hwirq, event);
1322 }
1323
1324 static void its_irq_domain_deactivate(struct irq_domain *domain,
1325                                       struct irq_data *d)
1326 {
1327         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1328         u32 event = its_get_event_id(d);
1329
1330         /* Stop the delivery of interrupts */
1331         its_send_discard(its_dev, event);
1332 }
1333
1334 static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
1335                                 unsigned int nr_irqs)
1336 {
1337         struct irq_data *d = irq_domain_get_irq_data(domain, virq);
1338         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1339         int i;
1340
1341         for (i = 0; i < nr_irqs; i++) {
1342                 struct irq_data *data = irq_domain_get_irq_data(domain,
1343                                                                 virq + i);
1344                 u32 event = its_get_event_id(data);
1345
1346                 /* Mark interrupt index as unused */
1347                 clear_bit(event, its_dev->event_map.lpi_map);
1348
1349                 /* Nuke the entry in the domain */
1350                 irq_domain_reset_irq_data(data);
1351         }
1352
1353         /* If all interrupts have been freed, start mopping the floor */
1354         if (bitmap_empty(its_dev->event_map.lpi_map,
1355                          its_dev->event_map.nr_lpis)) {
1356                 its_lpi_free(&its_dev->event_map);
1357
1358                 /* Unmap device/itt */
1359                 its_send_mapd(its_dev, 0);
1360                 its_free_device(its_dev);
1361         }
1362
1363         irq_domain_free_irqs_parent(domain, virq, nr_irqs);
1364 }
1365
1366 static const struct irq_domain_ops its_domain_ops = {
1367         .alloc                  = its_irq_domain_alloc,
1368         .free                   = its_irq_domain_free,
1369         .activate               = its_irq_domain_activate,
1370         .deactivate             = its_irq_domain_deactivate,
1371 };
1372
1373 static int its_force_quiescent(void __iomem *base)
1374 {
1375         u32 count = 1000000;    /* 1s */
1376         u32 val;
1377
1378         val = readl_relaxed(base + GITS_CTLR);
1379         if (val & GITS_CTLR_QUIESCENT)
1380                 return 0;
1381
1382         /* Disable the generation of all interrupts to this ITS */
1383         val &= ~GITS_CTLR_ENABLE;
1384         writel_relaxed(val, base + GITS_CTLR);
1385
1386         /* Poll GITS_CTLR and wait until ITS becomes quiescent */
1387         while (1) {
1388                 val = readl_relaxed(base + GITS_CTLR);
1389                 if (val & GITS_CTLR_QUIESCENT)
1390                         return 0;
1391
1392                 count--;
1393                 if (!count)
1394                         return -EBUSY;
1395
1396                 cpu_relax();
1397                 udelay(1);
1398         }
1399 }
1400
1401 static void __maybe_unused its_enable_quirk_cavium_22375(void *data)
1402 {
1403         struct its_node *its = data;
1404
1405         its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
1406 }
1407
1408 static const struct gic_quirk its_quirks[] = {
1409 #ifdef CONFIG_CAVIUM_ERRATUM_22375
1410         {
1411                 .desc   = "ITS: Cavium errata 22375, 24313",
1412                 .iidr   = 0xa100034c,   /* ThunderX pass 1.x */
1413                 .mask   = 0xffff0fff,
1414                 .init   = its_enable_quirk_cavium_22375,
1415         },
1416 #endif
1417         {
1418         }
1419 };
1420
1421 static void its_enable_quirks(struct its_node *its)
1422 {
1423         u32 iidr = readl_relaxed(its->base + GITS_IIDR);
1424
1425         gic_enable_quirks(iidr, its_quirks, its);
1426 }
1427
1428 static int its_probe(struct device_node *node, struct irq_domain *parent)
1429 {
1430         struct resource res;
1431         struct its_node *its;
1432         void __iomem *its_base;
1433         struct irq_domain *inner_domain;
1434         u32 val;
1435         u64 baser, tmp;
1436         int err;
1437
1438         err = of_address_to_resource(node, 0, &res);
1439         if (err) {
1440                 pr_warn("%s: no regs?\n", node->full_name);
1441                 return -ENXIO;
1442         }
1443
1444         its_base = ioremap(res.start, resource_size(&res));
1445         if (!its_base) {
1446                 pr_warn("%s: unable to map registers\n", node->full_name);
1447                 return -ENOMEM;
1448         }
1449
1450         val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
1451         if (val != 0x30 && val != 0x40) {
1452                 pr_warn("%s: no ITS detected, giving up\n", node->full_name);
1453                 err = -ENODEV;
1454                 goto out_unmap;
1455         }
1456
1457         err = its_force_quiescent(its_base);
1458         if (err) {
1459                 pr_warn("%s: failed to quiesce, giving up\n",
1460                         node->full_name);
1461                 goto out_unmap;
1462         }
1463
1464         pr_info("ITS: %s\n", node->full_name);
1465
1466         its = kzalloc(sizeof(*its), GFP_KERNEL);
1467         if (!its) {
1468                 err = -ENOMEM;
1469                 goto out_unmap;
1470         }
1471
1472         raw_spin_lock_init(&its->lock);
1473         INIT_LIST_HEAD(&its->entry);
1474         INIT_LIST_HEAD(&its->its_device_list);
1475         its->base = its_base;
1476         its->phys_base = res.start;
1477         its->ite_size = ((readl_relaxed(its_base + GITS_TYPER) >> 4) & 0xf) + 1;
1478
1479         its->cmd_base = kzalloc(ITS_CMD_QUEUE_SZ, GFP_KERNEL);
1480         if (!its->cmd_base) {
1481                 err = -ENOMEM;
1482                 goto out_free_its;
1483         }
1484         its->cmd_write = its->cmd_base;
1485
1486         its_enable_quirks(its);
1487
1488         err = its_alloc_tables(node->full_name, its);
1489         if (err)
1490                 goto out_free_cmd;
1491
1492         err = its_alloc_collections(its);
1493         if (err)
1494                 goto out_free_tables;
1495
1496         baser = (virt_to_phys(its->cmd_base)    |
1497                  GITS_CBASER_WaWb               |
1498                  GITS_CBASER_InnerShareable     |
1499                  (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
1500                  GITS_CBASER_VALID);
1501
1502         writeq_relaxed(baser, its->base + GITS_CBASER);
1503         tmp = readq_relaxed(its->base + GITS_CBASER);
1504
1505         if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
1506                 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
1507                         /*
1508                          * The HW reports non-shareable, we must
1509                          * remove the cacheability attributes as
1510                          * well.
1511                          */
1512                         baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
1513                                    GITS_CBASER_CACHEABILITY_MASK);
1514                         baser |= GITS_CBASER_nC;
1515                         writeq_relaxed(baser, its->base + GITS_CBASER);
1516                 }
1517                 pr_info("ITS: using cache flushing for cmd queue\n");
1518                 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
1519         }
1520
1521         writeq_relaxed(0, its->base + GITS_CWRITER);
1522         writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR);
1523
1524         if (of_property_read_bool(node, "msi-controller")) {
1525                 struct msi_domain_info *info;
1526
1527                 info = kzalloc(sizeof(*info), GFP_KERNEL);
1528                 if (!info) {
1529                         err = -ENOMEM;
1530                         goto out_free_tables;
1531                 }
1532
1533                 inner_domain = irq_domain_add_tree(node, &its_domain_ops, its);
1534                 if (!inner_domain) {
1535                         err = -ENOMEM;
1536                         kfree(info);
1537                         goto out_free_tables;
1538                 }
1539
1540                 inner_domain->parent = parent;
1541                 inner_domain->bus_token = DOMAIN_BUS_NEXUS;
1542                 info->ops = &its_msi_domain_ops;
1543                 info->data = its;
1544                 inner_domain->host_data = info;
1545         }
1546
1547         spin_lock(&its_lock);
1548         list_add(&its->entry, &its_nodes);
1549         spin_unlock(&its_lock);
1550
1551         return 0;
1552
1553 out_free_tables:
1554         its_free_tables(its);
1555 out_free_cmd:
1556         kfree(its->cmd_base);
1557 out_free_its:
1558         kfree(its);
1559 out_unmap:
1560         iounmap(its_base);
1561         pr_err("ITS: failed probing %s (%d)\n", node->full_name, err);
1562         return err;
1563 }
1564
1565 static bool gic_rdists_supports_plpis(void)
1566 {
1567         return !!(readl_relaxed(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
1568 }
1569
1570 int its_cpu_init(void)
1571 {
1572         if (!list_empty(&its_nodes)) {
1573                 if (!gic_rdists_supports_plpis()) {
1574                         pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
1575                         return -ENXIO;
1576                 }
1577                 its_cpu_init_lpis();
1578                 its_cpu_init_collection();
1579         }
1580
1581         return 0;
1582 }
1583
1584 static struct of_device_id its_device_id[] = {
1585         {       .compatible     = "arm,gic-v3-its",     },
1586         {},
1587 };
1588
1589 int its_init(struct device_node *node, struct rdists *rdists,
1590              struct irq_domain *parent_domain)
1591 {
1592         struct device_node *np;
1593
1594         for (np = of_find_matching_node(node, its_device_id); np;
1595              np = of_find_matching_node(np, its_device_id)) {
1596                 its_probe(np, parent_domain);
1597         }
1598
1599         if (list_empty(&its_nodes)) {
1600                 pr_warn("ITS: No ITS available, not enabling LPIs\n");
1601                 return -ENXIO;
1602         }
1603
1604         gic_rdists = rdists;
1605         gic_root_node = node;
1606
1607         its_alloc_lpi_tables();
1608         its_lpi_init(rdists->id_bits);
1609
1610         return 0;
1611 }