drivers/memory/omap-gpmc.c

   1 /*
   2  * GPMC support functions
   3  *
   4  * Copyright (C) 2005-2006 Nokia Corporation
   5  *
   6  * Author: Juha Yrjola
   7  *
   8  * Copyright (C) 2009 Texas Instruments
   9  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15 #include <linux/irq.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/ioport.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/io.h>
  23 #include <linux/module.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/of.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_mtd.h>
  29 #include <linux/of_device.h>
  30 #include <linux/of_platform.h>
  31 #include <linux/omap-gpmc.h>
  32 #include <linux/mtd/nand.h>
  33 #include <linux/pm_runtime.h>
  34
  35 #include <linux/platform_data/mtd-nand-omap2.h>
  36 #include <linux/platform_data/mtd-onenand-omap2.h>
  37
  38 #include <asm/mach-types.h>
  39
  40 #define DEVICE_NAME             "omap-gpmc"
  41
  42 /* GPMC register offsets */
  43 #define GPMC_REVISION           0x00
  44 #define GPMC_SYSCONFIG          0x10
  45 #define GPMC_SYSSTATUS          0x14
  46 #define GPMC_IRQSTATUS          0x18
  47 #define GPMC_IRQENABLE          0x1c
  48 #define GPMC_TIMEOUT_CONTROL    0x40
  49 #define GPMC_ERR_ADDRESS        0x44
  50 #define GPMC_ERR_TYPE           0x48
  51 #define GPMC_CONFIG             0x50
  52 #define GPMC_STATUS             0x54
  53 #define GPMC_PREFETCH_CONFIG1   0x1e0
  54 #define GPMC_PREFETCH_CONFIG2   0x1e4
  55 #define GPMC_PREFETCH_CONTROL   0x1ec
  56 #define GPMC_PREFETCH_STATUS    0x1f0
  57 #define GPMC_ECC_CONFIG         0x1f4
  58 #define GPMC_ECC_CONTROL        0x1f8
  59 #define GPMC_ECC_SIZE_CONFIG    0x1fc
  60 #define GPMC_ECC1_RESULT        0x200
  61 #define GPMC_ECC_BCH_RESULT_0   0x240   /* not available on OMAP2 */
  62 #define GPMC_ECC_BCH_RESULT_1   0x244   /* not available on OMAP2 */
  63 #define GPMC_ECC_BCH_RESULT_2   0x248   /* not available on OMAP2 */
  64 #define GPMC_ECC_BCH_RESULT_3   0x24c   /* not available on OMAP2 */
  65 #define GPMC_ECC_BCH_RESULT_4   0x300   /* not available on OMAP2 */
  66 #define GPMC_ECC_BCH_RESULT_5   0x304   /* not available on OMAP2 */
  67 #define GPMC_ECC_BCH_RESULT_6   0x308   /* not available on OMAP2 */
  68
  69 /* GPMC ECC control settings */
  70 #define GPMC_ECC_CTRL_ECCCLEAR          0x100
  71 #define GPMC_ECC_CTRL_ECCDISABLE        0x000
  72 #define GPMC_ECC_CTRL_ECCREG1           0x001
  73 #define GPMC_ECC_CTRL_ECCREG2           0x002
  74 #define GPMC_ECC_CTRL_ECCREG3           0x003
  75 #define GPMC_ECC_CTRL_ECCREG4           0x004
  76 #define GPMC_ECC_CTRL_ECCREG5           0x005
  77 #define GPMC_ECC_CTRL_ECCREG6           0x006
  78 #define GPMC_ECC_CTRL_ECCREG7           0x007
  79 #define GPMC_ECC_CTRL_ECCREG8           0x008
  80 #define GPMC_ECC_CTRL_ECCREG9           0x009
  81
  82 #define GPMC_CONFIG_LIMITEDADDRESS              BIT(1)
  83
  84 #define GPMC_CONFIG2_CSEXTRADELAY               BIT(7)
  85 #define GPMC_CONFIG3_ADVEXTRADELAY              BIT(7)
  86 #define GPMC_CONFIG4_OEEXTRADELAY               BIT(7)
  87 #define GPMC_CONFIG4_WEEXTRADELAY               BIT(23)
  88 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN        BIT(6)
  89 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN        BIT(7)
  90
  91 #define GPMC_CS0_OFFSET         0x60
  92 #define GPMC_CS_SIZE            0x30
  93 #define GPMC_BCH_SIZE           0x10
  94
  95 #define GPMC_MEM_END            0x3FFFFFFF
  96
  97 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
  98 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
  99
 100 #define CS_NUM_SHIFT            24
 101 #define ENABLE_PREFETCH         (0x1 << 7)
 102 #define DMA_MPU_MODE            2
 103
 104 #define GPMC_REVISION_MAJOR(l)          ((l >> 4) & 0xf)
 105 #define GPMC_REVISION_MINOR(l)          (l & 0xf)
 106
 107 #define GPMC_HAS_WR_ACCESS              0x1
 108 #define GPMC_HAS_WR_DATA_MUX_BUS        0x2
 109 #define GPMC_HAS_MUX_AAD                0x4
 110
 111 #define GPMC_NR_WAITPINS                4
 112
 113 #define GPMC_CS_CONFIG1         0x00
 114 #define GPMC_CS_CONFIG2         0x04
 115 #define GPMC_CS_CONFIG3         0x08
 116 #define GPMC_CS_CONFIG4         0x0c
 117 #define GPMC_CS_CONFIG5         0x10
 118 #define GPMC_CS_CONFIG6         0x14
 119 #define GPMC_CS_CONFIG7         0x18
 120 #define GPMC_CS_NAND_COMMAND    0x1c
 121 #define GPMC_CS_NAND_ADDRESS    0x20
 122 #define GPMC_CS_NAND_DATA       0x24
 123
 124 /* Control Commands */
 125 #define GPMC_CONFIG_RDY_BSY     0x00000001
 126 #define GPMC_CONFIG_DEV_SIZE    0x00000002
 127 #define GPMC_CONFIG_DEV_TYPE    0x00000003
 128 #define GPMC_SET_IRQ_STATUS     0x00000004
 129
 130 #define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
 131 #define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)
 132 #define GPMC_CONFIG1_READTYPE_ASYNC     (0 << 29)
 133 #define GPMC_CONFIG1_READTYPE_SYNC      (1 << 29)
 134 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
 135 #define GPMC_CONFIG1_WRITETYPE_ASYNC    (0 << 27)
 136 #define GPMC_CONFIG1_WRITETYPE_SYNC     (1 << 27)
 137 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
 138 /** CLKACTIVATIONTIME Max Ticks */
 139 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
 140 #define GPMC_CONFIG1_PAGE_LEN(val)      ((val & 3) << 23)
 141 /** ATTACHEDDEVICEPAGELENGTH Max Value */
 142 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
 143 #define GPMC_CONFIG1_WAIT_READ_MON      (1 << 22)
 144 #define GPMC_CONFIG1_WAIT_WRITE_MON     (1 << 21)
 145 #define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18)
 146 /** WAITMONITORINGTIME Max Ticks */
 147 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX  2
 148 #define GPMC_CONFIG1_WAIT_PIN_SEL(val)  ((val & 3) << 16)
 149 #define GPMC_CONFIG1_DEVICESIZE(val)    ((val & 3) << 12)
 150 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 151 /** DEVICESIZE Max Value */
 152 #define GPMC_CONFIG1_DEVICESIZE_MAX     1
 153 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 154 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
 155 #define GPMC_CONFIG1_MUXTYPE(val)       ((val & 3) << 8)
 156 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 157 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
 158 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
 159 #define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
 160 #define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
 161 #define GPMC_CONFIG7_CSVALID            (1 << 6)
 162
 163 #define GPMC_CONFIG7_BASEADDRESS_MASK   0x3f
 164 #define GPMC_CONFIG7_CSVALID_MASK       BIT(6)
 165 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
 166 #define GPMC_CONFIG7_MASKADDRESS_MASK   (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
 167 /* All CONFIG7 bits except reserved bits */
 168 #define GPMC_CONFIG7_MASK               (GPMC_CONFIG7_BASEADDRESS_MASK | \
 169                                          GPMC_CONFIG7_CSVALID_MASK |     \
 170                                          GPMC_CONFIG7_MASKADDRESS_MASK)
 171
 172 #define GPMC_DEVICETYPE_NOR             0
 173 #define GPMC_DEVICETYPE_NAND            2
 174 #define GPMC_CONFIG_WRITEPROTECT        0x00000010
 175 #define WR_RD_PIN_MONITORING            0x00600000
 176
 177 #define GPMC_ENABLE_IRQ         0x0000000d
 178
 179 /* ECC commands */
 180 #define GPMC_ECC_READ           0 /* Reset Hardware ECC for read */
 181 #define GPMC_ECC_WRITE          1 /* Reset Hardware ECC for write */
 182 #define GPMC_ECC_READSYN        2 /* Reset before syndrom is read back */
 183
 184 /* XXX: Only NAND irq has been considered,currently these are the only ones used
 185  */
 186 #define GPMC_NR_IRQ             2
 187
 188 enum gpmc_clk_domain {
 189         GPMC_CD_FCLK,
 190         GPMC_CD_CLK
 191 };
 192
 193 struct gpmc_cs_data {
 194         const char *name;
 195
 196 #define GPMC_CS_RESERVED        (1 << 0)
 197         u32 flags;
 198
 199         struct resource mem;
 200 };
 201
 202 struct gpmc_client_irq  {
 203         unsigned                irq;
 204         u32                     bitmask;
 205 };
 206
 207 /* Structure to save gpmc cs context */
 208 struct gpmc_cs_config {
 209         u32 config1;
 210         u32 config2;
 211         u32 config3;
 212         u32 config4;
 213         u32 config5;
 214         u32 config6;
 215         u32 config7;
 216         int is_valid;
 217 };
 218
 219 /*
 220  * Structure to save/restore gpmc context
 221  * to support core off on OMAP3
 222  */
 223 struct omap3_gpmc_regs {
 224         u32 sysconfig;
 225         u32 irqenable;
 226         u32 timeout_ctrl;
 227         u32 config;
 228         u32 prefetch_config1;
 229         u32 prefetch_config2;
 230         u32 prefetch_control;
 231         struct gpmc_cs_config cs_context[GPMC_CS_NUM];
 232 };
 233
 234 static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
 235 static struct irq_chip gpmc_irq_chip;
 236 static int gpmc_irq_start;
 237
 238 static struct resource  gpmc_mem_root;
 239 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
 240 static DEFINE_SPINLOCK(gpmc_mem_lock);
 241 /* Define chip-selects as reserved by default until probe completes */
 242 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
 243 static unsigned int gpmc_nr_waitpins;
 244 static struct device *gpmc_dev;
 245 static int gpmc_irq;
 246 static resource_size_t phys_base, mem_size;
 247 static unsigned gpmc_capability;
 248 static void __iomem *gpmc_base;
 249
 250 static struct clk *gpmc_l3_clk;
 251
 252 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
 253
 254 static void gpmc_write_reg(int idx, u32 val)
 255 {
 256         writel_relaxed(val, gpmc_base + idx);
 257 }
 258
 259 static u32 gpmc_read_reg(int idx)
 260 {
 261         return readl_relaxed(gpmc_base + idx);
 262 }
 263
 264 void gpmc_cs_write_reg(int cs, int idx, u32 val)
 265 {
 266         void __iomem *reg_addr;
 267
 268         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 269         writel_relaxed(val, reg_addr);
 270 }
 271
 272 static u32 gpmc_cs_read_reg(int cs, int idx)
 273 {
 274         void __iomem *reg_addr;
 275
 276         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 277         return readl_relaxed(reg_addr);
 278 }
 279
 280 /* TODO: Add support for gpmc_fck to clock framework and use it */
 281 static unsigned long gpmc_get_fclk_period(void)
 282 {
 283         unsigned long rate = clk_get_rate(gpmc_l3_clk);
 284
 285         rate /= 1000;
 286         rate = 1000000000 / rate;       /* In picoseconds */
 287
 288         return rate;
 289 }
 290
 291 /**
 292  * gpmc_get_clk_period - get period of selected clock domain in ps
 293  * @cs Chip Select Region.
 294  * @cd Clock Domain.
 295  *
 296  * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
 297  * prior to calling this function with GPMC_CD_CLK.
 298  */
 299 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
 300 {
 301
 302         unsigned long tick_ps = gpmc_get_fclk_period();
 303         u32 l;
 304         int div;
 305
 306         switch (cd) {
 307         case GPMC_CD_CLK:
 308                 /* get current clk divider */
 309                 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 310                 div = (l & 0x03) + 1;
 311                 /* get GPMC_CLK period */
 312                 tick_ps *= div;
 313                 break;
 314         case GPMC_CD_FCLK:
 315                 /* FALL-THROUGH */
 316         default:
 317                 break;
 318         }
 319
 320         return tick_ps;
 321
 322 }
 323
 324 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
 325                                          enum gpmc_clk_domain cd)
 326 {
 327         unsigned long tick_ps;
 328
 329         /* Calculate in picosecs to yield more exact results */
 330         tick_ps = gpmc_get_clk_period(cs, cd);
 331
 332         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 333 }
 334
 335 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 336 {
 337         return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
 338 }
 339
 340 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 341 {
 342         unsigned long tick_ps;
 343
 344         /* Calculate in picosecs to yield more exact results */
 345         tick_ps = gpmc_get_fclk_period();
 346
 347         return (time_ps + tick_ps - 1) / tick_ps;
 348 }
 349
 350 unsigned int gpmc_clk_ticks_to_ns(unsigned ticks, int cs,
 351                                   enum gpmc_clk_domain cd)
 352 {
 353         return ticks * gpmc_get_clk_period(cs, cd) / 1000;
 354 }
 355
 356 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
 357 {
 358         return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
 359 }
 360
 361 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
 362 {
 363         return ticks * gpmc_get_fclk_period();
 364 }
 365
 366 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
 367 {
 368         unsigned long ticks = gpmc_ps_to_ticks(time_ps);
 369
 370         return ticks * gpmc_get_fclk_period();
 371 }
 372
 373 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
 374 {
 375         u32 l;
 376
 377         l = gpmc_cs_read_reg(cs, reg);
 378         if (value)
 379                 l |= mask;
 380         else
 381                 l &= ~mask;
 382         gpmc_cs_write_reg(cs, reg, l);
 383 }
 384
 385 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
 386 {
 387         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
 388                            GPMC_CONFIG1_TIME_PARA_GRAN,
 389                            p->time_para_granularity);
 390         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
 391                            GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
 392         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
 393                            GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
 394         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 395                            GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
 396         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 397                            GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
 398         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 399                            GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
 400                            p->cycle2cyclesamecsen);
 401         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 402                            GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
 403                            p->cycle2cyclediffcsen);
 404 }
 405
 406 #ifdef CONFIG_OMAP_GPMC_DEBUG
 407 /**
 408  * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
 409  * @cs:      Chip Select Region
 410  * @reg:     GPMC_CS_CONFIGn register offset.
 411  * @st_bit:  Start Bit
 412  * @end_bit: End Bit. Must be >= @st_bit.
 413  * @ma:x     Maximum parameter value (before optional @shift).
 414  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 415  * @name:    DTS node name, w/o "gpmc,"
 416  * @cd:      Clock Domain of timing parameter.
 417  * @shift:   Parameter value left shifts @shift, which is then printed instead of value.
 418  * @raw:     Raw Format Option.
 419  *           raw format:  gpmc,name = <value>
 420  *           tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/
 421  *           Where x ns -- y ns result in the same tick value.
 422  *           When @max is exceeded, "invalid" is printed inside comment.
 423  * @noval:   Parameter values equal to 0 are not printed.
 424  * @return:  Specified timing parameter (after optional @shift).
 425  *
 426  */
 427 static int get_gpmc_timing_reg(
 428         /* timing specifiers */
 429         int cs, int reg, int st_bit, int end_bit, int max,
 430         const char *name, const enum gpmc_clk_domain cd,
 431         /* value transform */
 432         int shift,
 433         /* format specifiers */
 434         bool raw, bool noval)
 435 {
 436         u32 l;
 437         int nr_bits;
 438         int mask;
 439         bool invalid;
 440
 441         l = gpmc_cs_read_reg(cs, reg);
 442         nr_bits = end_bit - st_bit + 1;
 443         mask = (1 << nr_bits) - 1;
 444         l = (l >> st_bit) & mask;
 445         if (!max)
 446                 max = mask;
 447         invalid = l > max;
 448         if (shift)
 449                 l = (shift << l);
 450         if (noval && (l == 0))
 451                 return 0;
 452         if (!raw) {
 453                 /* DTS tick format for timings in ns */
 454                 unsigned int time_ns;
 455                 unsigned int time_ns_min = 0;
 456
 457                 if (l)
 458                         time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
 459                 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
 460                 pr_info("gpmc,%s = <%u> /* %u ns - %u ns; %i ticks%s*/\n",
 461                         name, time_ns, time_ns_min, time_ns, l,
 462                         invalid ? "; invalid " : " ");
 463         } else {
 464                 /* raw format */
 465                 pr_info("gpmc,%s = <%u>%s\n", name, l,
 466                         invalid ? " /* invalid */" : "");
 467         }
 468
 469         return l;
 470 }
 471
 472 #define GPMC_PRINT_CONFIG(cs, config) \
 473         pr_info("cs%i %s: 0x%08x\n", cs, #config, \
 474                 gpmc_cs_read_reg(cs, config))
 475 #define GPMC_GET_RAW(reg, st, end, field) \
 476         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
 477 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
 478         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
 479 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
 480         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
 481 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
 482         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
 483 #define GPMC_GET_TICKS(reg, st, end, field) \
 484         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
 485 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
 486         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
 487 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
 488         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
 489
 490 static void gpmc_show_regs(int cs, const char *desc)
 491 {
 492         pr_info("gpmc cs%i %s:\n", cs, desc);
 493         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
 494         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
 495         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
 496         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
 497         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
 498         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
 499 }
 500
 501 /*
 502  * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
 503  * see commit c9fb809.
 504  */
 505 static void gpmc_cs_show_timings(int cs, const char *desc)
 506 {
 507         gpmc_show_regs(cs, desc);
 508
 509         pr_info("gpmc cs%i access configuration:\n", cs);
 510         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
 511         GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
 512         GPMC_GET_RAW_MAX(GPMC_CS_CONFIG1, 12, 13,
 513                          GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
 514         GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
 515         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
 516         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
 517         GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
 518                                GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
 519                                "burst-length");
 520         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
 521         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
 522         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
 523         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
 524         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
 525
 526         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2,  7,  7, "cs-extra-delay");
 527
 528         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3,  7,  7, "adv-extra-delay");
 529
 530         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
 531         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4,  7,  7, "oe-extra-delay");
 532
 533         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  7,  7, "cycle2cycle-samecsen");
 534         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  6,  6, "cycle2cycle-diffcsen");
 535
 536         pr_info("gpmc cs%i timings configuration:\n", cs);
 537         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  0,  3, "cs-on-ns");
 538         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  8, 12, "cs-rd-off-ns");
 539         GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
 540
 541         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  0,  3, "adv-on-ns");
 542         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  8, 12, "adv-rd-off-ns");
 543         GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
 544
 545         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  0,  3, "oe-on-ns");
 546         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  8, 12, "oe-off-ns");
 547         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
 548         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
 549
 550         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  0,  4, "rd-cycle-ns");
 551         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  8, 12, "wr-cycle-ns");
 552         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
 553
 554         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
 555
 556         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
 557         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
 558
 559         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 560                               GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 561                               "wait-monitoring-ns", GPMC_CD_CLK);
 562         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 563                               GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 564                               "clk-activation-ns", GPMC_CD_FCLK);
 565
 566         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
 567         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
 568 }
 569 #else
 570 static inline void gpmc_cs_show_timings(int cs, const char *desc)
 571 {
 572 }
 573 #endif
 574
 575 /**
 576  * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
 577  * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
 578  * prior to calling this function with @cd equal to GPMC_CD_CLK.
 579  *
 580  * @cs:      Chip Select Region.
 581  * @reg:     GPMC_CS_CONFIGn register offset.
 582  * @st_bit:  Start Bit
 583  * @end_bit: End Bit. Must be >= @st_bit.
 584  * @max:     Maximum parameter value.
 585  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 586  * @time:    Timing parameter in ns.
 587  * @cd:      Timing parameter clock domain.
 588  * @name:    Timing parameter name.
 589  * @return:  0 on success, -1 on error.
 590  */
 591 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
 592                                int time, enum gpmc_clk_domain cd, const char *name)
 593 {
 594         u32 l;
 595         int ticks, mask, nr_bits;
 596
 597         if (time == 0)
 598                 ticks = 0;
 599         else
 600                 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
 601         nr_bits = end_bit - st_bit + 1;
 602         mask = (1 << nr_bits) - 1;
 603
 604         if (!max)
 605                 max = mask;
 606
 607         if (ticks > max) {
 608                 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
 609                        __func__, cs, name, time, ticks, max);
 610
 611                 return -1;
 612         }
 613
 614         l = gpmc_cs_read_reg(cs, reg);
 615 #ifdef CONFIG_OMAP_GPMC_DEBUG
 616         pr_info(
 617                 "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
 618                cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
 619                         (l >> st_bit) & mask, time);
 620 #endif
 621         l &= ~(mask << st_bit);
 622         l |= ticks << st_bit;
 623         gpmc_cs_write_reg(cs, reg, l);
 624
 625         return 0;
 626 }
 627
 628 #define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd)  \
 629         if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \
 630             t->field, (cd), #field) < 0)                       \
 631                 return -1
 632
 633 #define GPMC_SET_ONE(reg, st, end, field) \
 634         GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK)
 635
 636 /**
 637  * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
 638  * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
 639  * read  --> don't sample bus too early
 640  * write --> data is longer on bus
 641  *
 642  * Formula:
 643  * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
 644  *                    / waitmonitoring_ticks)
 645  * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
 646  * div <= 0 check.
 647  *
 648  * @wait_monitoring: WAITMONITORINGTIME in ns.
 649  * @return:          -1 on failure to scale, else proper divider > 0.
 650  */
 651 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
 652 {
 653
 654         int div = gpmc_ns_to_ticks(wait_monitoring);
 655
 656         div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
 657         div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
 658
 659         if (div > 4)
 660                 return -1;
 661         if (div <= 0)
 662                 div = 1;
 663
 664         return div;
 665
 666 }
 667
 668 /**
 669  * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
 670  * @sync_clk: GPMC_CLK period in ps.
 671  * @return:   Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
 672  *            Else, returns -1.
 673  */
 674 int gpmc_calc_divider(unsigned int sync_clk)
 675 {
 676         int div = gpmc_ps_to_ticks(sync_clk);
 677
 678         if (div > 4)
 679                 return -1;
 680         if (div <= 0)
 681                 div = 1;
 682
 683         return div;
 684 }
 685
 686 /**
 687  * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
 688  * @cs:     Chip Select Region.
 689  * @t:      GPMC timing parameters.
 690  * @s:      GPMC timing settings.
 691  * @return: 0 on success, -1 on error.
 692  */
 693 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
 694                         const struct gpmc_settings *s)
 695 {
 696         int div;
 697         u32 l;
 698
 699         div = gpmc_calc_divider(t->sync_clk);
 700         if (div < 0)
 701                 return div;
 702
 703         /*
 704          * See if we need to change the divider for waitmonitoringtime.
 705          *
 706          * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
 707          * pure asynchronous accesses, i.e. both read and write asynchronous.
 708          * However, only do so if WAITMONITORINGTIME is actually used, i.e.
 709          * either WAITREADMONITORING or WAITWRITEMONITORING is set.
 710          *
 711          * This statement must not change div to scale async WAITMONITORINGTIME
 712          * to protect mixed synchronous and asynchronous accesses.
 713          *
 714          * We raise an error later if WAITMONITORINGTIME does not fit.
 715          */
 716         if (!s->sync_read && !s->sync_write &&
 717             (s->wait_on_read || s->wait_on_write)
 718            ) {
 719
 720                 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
 721                 if (div < 0) {
 722                         pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
 723                                __func__,
 724                                t->wait_monitoring
 725                                );
 726                         return -1;
 727                 }
 728         }
 729
 730         GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
 731         GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
 732         GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
 733
 734         GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
 735         GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
 736         GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
 737
 738         GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
 739         GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
 740         GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
 741         GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
 742
 743         GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
 744         GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
 745         GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
 746
 747         GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
 748
 749         GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
 750         GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
 751
 752         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
 753                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
 754         if (gpmc_capability & GPMC_HAS_WR_ACCESS)
 755                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
 756
 757         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 758         l &= ~0x03;
 759         l |= (div - 1);
 760         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
 761
 762         GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 763                             GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 764                             wait_monitoring, GPMC_CD_CLK);
 765         GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 766                             GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 767                             clk_activation, GPMC_CD_FCLK);
 768
 769 #ifdef CONFIG_OMAP_GPMC_DEBUG
 770         pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
 771                         cs, (div * gpmc_get_fclk_period()) / 1000, div);
 772 #endif
 773
 774         gpmc_cs_bool_timings(cs, &t->bool_timings);
 775         gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
 776
 777         return 0;
 778 }
 779
 780 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
 781 {
 782         u32 l;
 783         u32 mask;
 784
 785         /*
 786          * Ensure that base address is aligned on a
 787          * boundary equal to or greater than size.
 788          */
 789         if (base & (size - 1))
 790                 return -EINVAL;
 791
 792         base >>= GPMC_CHUNK_SHIFT;
 793         mask = (1 << GPMC_SECTION_SHIFT) - size;
 794         mask >>= GPMC_CHUNK_SHIFT;
 795         mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
 796
 797         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 798         l &= ~GPMC_CONFIG7_MASK;
 799         l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
 800         l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
 801         l |= GPMC_CONFIG7_CSVALID;
 802         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 803
 804         return 0;
 805 }
 806
 807 static void gpmc_cs_enable_mem(int cs)
 808 {
 809         u32 l;
 810
 811         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 812         l |= GPMC_CONFIG7_CSVALID;
 813         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 814 }
 815
 816 static void gpmc_cs_disable_mem(int cs)
 817 {
 818         u32 l;
 819
 820         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 821         l &= ~GPMC_CONFIG7_CSVALID;
 822         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 823 }
 824
 825 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
 826 {
 827         u32 l;
 828         u32 mask;
 829
 830         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 831         *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
 832         mask = (l >> 8) & 0x0f;
 833         *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
 834 }
 835
 836 static int gpmc_cs_mem_enabled(int cs)
 837 {
 838         u32 l;
 839
 840         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 841         return l & GPMC_CONFIG7_CSVALID;
 842 }
 843
 844 static void gpmc_cs_set_reserved(int cs, int reserved)
 845 {
 846         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 847
 848         gpmc->flags |= GPMC_CS_RESERVED;
 849 }
 850
 851 static bool gpmc_cs_reserved(int cs)
 852 {
 853         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 854
 855         return gpmc->flags & GPMC_CS_RESERVED;
 856 }
 857
 858 static void gpmc_cs_set_name(int cs, const char *name)
 859 {
 860         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 861
 862         gpmc->name = name;
 863 }
 864
 865 static const char *gpmc_cs_get_name(int cs)
 866 {
 867         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 868
 869         return gpmc->name;
 870 }
 871
 872 static unsigned long gpmc_mem_align(unsigned long size)
 873 {
 874         int order;
 875
 876         size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
 877         order = GPMC_CHUNK_SHIFT - 1;
 878         do {
 879                 size >>= 1;
 880                 order++;
 881         } while (size);
 882         size = 1 << order;
 883         return size;
 884 }
 885
 886 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
 887 {
 888         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 889         struct resource *res = &gpmc->mem;
 890         int r;
 891
 892         size = gpmc_mem_align(size);
 893         spin_lock(&gpmc_mem_lock);
 894         res->start = base;
 895         res->end = base + size - 1;
 896         r = request_resource(&gpmc_mem_root, res);
 897         spin_unlock(&gpmc_mem_lock);
 898
 899         return r;
 900 }
 901
 902 static int gpmc_cs_delete_mem(int cs)
 903 {
 904         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 905         struct resource *res = &gpmc->mem;
 906         int r;
 907
 908         spin_lock(&gpmc_mem_lock);
 909         r = release_resource(res);
 910         res->start = 0;
 911         res->end = 0;
 912         spin_unlock(&gpmc_mem_lock);
 913
 914         return r;
 915 }
 916
 917 /**
 918  * gpmc_cs_remap - remaps a chip-select physical base address
 919  * @cs:         chip-select to remap
 920  * @base:       physical base address to re-map chip-select to
 921  *
 922  * Re-maps a chip-select to a new physical base address specified by
 923  * "base". Returns 0 on success and appropriate negative error code
 924  * on failure.
 925  */
 926 static int gpmc_cs_remap(int cs, u32 base)
 927 {
 928         int ret;
 929         u32 old_base, size;
 930
 931         if (cs > gpmc_cs_num) {
 932                 pr_err("%s: requested chip-select is disabled\n", __func__);
 933                 return -ENODEV;
 934         }
 935
 936         /*
 937          * Make sure we ignore any device offsets from the GPMC partition
 938          * allocated for the chip select and that the new base confirms
 939          * to the GPMC 16MB minimum granularity.
 940          */
 941         base &= ~(SZ_16M - 1);
 942
 943         gpmc_cs_get_memconf(cs, &old_base, &size);
 944         if (base == old_base)
 945                 return 0;
 946
 947         ret = gpmc_cs_delete_mem(cs);
 948         if (ret < 0)
 949                 return ret;
 950
 951         ret = gpmc_cs_insert_mem(cs, base, size);
 952         if (ret < 0)
 953                 return ret;
 954
 955         ret = gpmc_cs_set_memconf(cs, base, size);
 956
 957         return ret;
 958 }
 959
 960 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 961 {
 962         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 963         struct resource *res = &gpmc->mem;
 964         int r = -1;
 965
 966         if (cs > gpmc_cs_num) {
 967                 pr_err("%s: requested chip-select is disabled\n", __func__);
 968                 return -ENODEV;
 969         }
 970         size = gpmc_mem_align(size);
 971         if (size > (1 << GPMC_SECTION_SHIFT))
 972                 return -ENOMEM;
 973
 974         spin_lock(&gpmc_mem_lock);
 975         if (gpmc_cs_reserved(cs)) {
 976                 r = -EBUSY;
 977                 goto out;
 978         }
 979         if (gpmc_cs_mem_enabled(cs))
 980                 r = adjust_resource(res, res->start & ~(size - 1), size);
 981         if (r < 0)
 982                 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
 983                                       size, NULL, NULL);
 984         if (r < 0)
 985                 goto out;
 986
 987         /* Disable CS while changing base address and size mask */
 988         gpmc_cs_disable_mem(cs);
 989
 990         r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
 991         if (r < 0) {
 992                 release_resource(res);
 993                 goto out;
 994         }
 995
 996         /* Enable CS */
 997         gpmc_cs_enable_mem(cs);
 998         *base = res->start;
 999         gpmc_cs_set_reserved(cs, 1);
1000 out:
1001         spin_unlock(&gpmc_mem_lock);
1002         return r;
1003 }
1004 EXPORT_SYMBOL(gpmc_cs_request);
1005
1006 void gpmc_cs_free(int cs)
1007 {
1008         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1009         struct resource *res = &gpmc->mem;
1010
1011         spin_lock(&gpmc_mem_lock);
1012         if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
1013                 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
1014                 BUG();
1015                 spin_unlock(&gpmc_mem_lock);
1016                 return;
1017         }
1018         gpmc_cs_disable_mem(cs);
1019         if (res->flags)
1020                 release_resource(res);
1021         gpmc_cs_set_reserved(cs, 0);
1022         spin_unlock(&gpmc_mem_lock);
1023 }
1024 EXPORT_SYMBOL(gpmc_cs_free);
1025
1026 /**
1027  * gpmc_configure - write request to configure gpmc
1028  * @cmd: command type
1029  * @wval: value to write
1030  * @return status of the operation
1031  */
1032 int gpmc_configure(int cmd, int wval)
1033 {
1034         u32 regval;
1035
1036         switch (cmd) {
1037         case GPMC_ENABLE_IRQ:
1038                 gpmc_write_reg(GPMC_IRQENABLE, wval);
1039                 break;
1040
1041         case GPMC_SET_IRQ_STATUS:
1042                 gpmc_write_reg(GPMC_IRQSTATUS, wval);
1043                 break;
1044
1045         case GPMC_CONFIG_WP:
1046                 regval = gpmc_read_reg(GPMC_CONFIG);
1047                 if (wval)
1048                         regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1049                 else
1050                         regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
1051                 gpmc_write_reg(GPMC_CONFIG, regval);
1052                 break;
1053
1054         default:
1055                 pr_err("%s: command not supported\n", __func__);
1056                 return -EINVAL;
1057         }
1058
1059         return 0;
1060 }
1061 EXPORT_SYMBOL(gpmc_configure);
1062
1063 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
1064 {
1065         int i;
1066
1067         reg->gpmc_status = gpmc_base + GPMC_STATUS;
1068         reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1069                                 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1070         reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1071                                 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1072         reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1073                                 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1074         reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1075         reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1076         reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1077         reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1078         reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1079         reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1080         reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1081         reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
1082
1083         for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1084                 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1085                                            GPMC_BCH_SIZE * i;
1086                 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1087                                            GPMC_BCH_SIZE * i;
1088                 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1089                                            GPMC_BCH_SIZE * i;
1090                 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1091                                            GPMC_BCH_SIZE * i;
1092                 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1093                                            i * GPMC_BCH_SIZE;
1094                 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1095                                            i * GPMC_BCH_SIZE;
1096                 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1097                                            i * GPMC_BCH_SIZE;
1098         }
1099 }
1100
1101 int gpmc_get_client_irq(unsigned irq_config)
1102 {
1103         int i;
1104
1105         if (hweight32(irq_config) > 1)
1106                 return 0;
1107
1108         for (i = 0; i < GPMC_NR_IRQ; i++)
1109                 if (gpmc_client_irq[i].bitmask & irq_config)
1110                         return gpmc_client_irq[i].irq;
1111
1112         return 0;
1113 }
1114
1115 static int gpmc_irq_endis(unsigned irq, bool endis)
1116 {
1117         int i;
1118         u32 regval;
1119
1120         for (i = 0; i < GPMC_NR_IRQ; i++)
1121                 if (irq == gpmc_client_irq[i].irq) {
1122                         regval = gpmc_read_reg(GPMC_IRQENABLE);
1123                         if (endis)
1124                                 regval |= gpmc_client_irq[i].bitmask;
1125                         else
1126                                 regval &= ~gpmc_client_irq[i].bitmask;
1127                         gpmc_write_reg(GPMC_IRQENABLE, regval);
1128                         break;
1129                 }
1130
1131         return 0;
1132 }
1133
1134 static void gpmc_irq_disable(struct irq_data *p)
1135 {
1136         gpmc_irq_endis(p->irq, false);
1137 }
1138
1139 static void gpmc_irq_enable(struct irq_data *p)
1140 {
1141         gpmc_irq_endis(p->irq, true);
1142 }
1143
1144 static void gpmc_irq_noop(struct irq_data *data) { }
1145
1146 static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
1147
1148 static int gpmc_setup_irq(void)
1149 {
1150         int i;
1151         u32 regval;
1152
1153         if (!gpmc_irq)
1154                 return -EINVAL;
1155
1156         gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
1157         if (gpmc_irq_start < 0) {
1158                 pr_err("irq_alloc_descs failed\n");
1159                 return gpmc_irq_start;
1160         }
1161
1162         gpmc_irq_chip.name = "gpmc";
1163         gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
1164         gpmc_irq_chip.irq_enable = gpmc_irq_enable;
1165         gpmc_irq_chip.irq_disable = gpmc_irq_disable;
1166         gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
1167         gpmc_irq_chip.irq_ack = gpmc_irq_noop;
1168         gpmc_irq_chip.irq_mask = gpmc_irq_noop;
1169         gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
1170
1171         gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
1172         gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
1173
1174         for (i = 0; i < GPMC_NR_IRQ; i++) {
1175                 gpmc_client_irq[i].irq = gpmc_irq_start + i;
1176                 irq_set_chip_and_handler(gpmc_client_irq[i].irq,
1177                                         &gpmc_irq_chip, handle_simple_irq);
1178                 irq_modify_status(gpmc_client_irq[i].irq, IRQ_NOREQUEST,
1179                                   IRQ_NOAUTOEN);
1180         }
1181
1182         /* Disable interrupts */
1183         gpmc_write_reg(GPMC_IRQENABLE, 0);
1184
1185         /* clear interrupts */
1186         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1187         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1188
1189         return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
1190 }
1191
1192 static int gpmc_free_irq(void)
1193 {
1194         int i;
1195
1196         if (gpmc_irq)
1197                 free_irq(gpmc_irq, NULL);
1198
1199         for (i = 0; i < GPMC_NR_IRQ; i++) {
1200                 irq_set_handler(gpmc_client_irq[i].irq, NULL);
1201                 irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
1202         }
1203
1204         irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
1205
1206         return 0;
1207 }
1208
1209 static void gpmc_mem_exit(void)
1210 {
1211         int cs;
1212
1213         for (cs = 0; cs < gpmc_cs_num; cs++) {
1214                 if (!gpmc_cs_mem_enabled(cs))
1215                         continue;
1216                 gpmc_cs_delete_mem(cs);
1217         }
1218
1219 }
1220
1221 static void gpmc_mem_init(void)
1222 {
1223         int cs;
1224
1225         /*
1226          * The first 1MB of GPMC address space is typically mapped to
1227          * the internal ROM. Never allocate the first page, to
1228          * facilitate bug detection; even if we didn't boot from ROM.
1229          */
1230         gpmc_mem_root.start = SZ_1M;
1231         gpmc_mem_root.end = GPMC_MEM_END;
1232
1233         /* Reserve all regions that has been set up by bootloader */
1234         for (cs = 0; cs < gpmc_cs_num; cs++) {
1235                 u32 base, size;
1236
1237                 if (!gpmc_cs_mem_enabled(cs))
1238                         continue;
1239                 gpmc_cs_get_memconf(cs, &base, &size);
1240                 if (gpmc_cs_insert_mem(cs, base, size)) {
1241                         pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1242                                 __func__, cs, base, base + size);
1243                         gpmc_cs_disable_mem(cs);
1244                 }
1245         }
1246 }
1247
1248 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1249 {
1250         u32 temp;
1251         int div;
1252
1253         div = gpmc_calc_divider(sync_clk);
1254         temp = gpmc_ps_to_ticks(time_ps);
1255         temp = (temp + div - 1) / div;
1256         return gpmc_ticks_to_ps(temp * div);
1257 }
1258
1259 /* XXX: can the cycles be avoided ? */
1260 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1261                                        struct gpmc_device_timings *dev_t,
1262                                        bool mux)
1263 {
1264         u32 temp;
1265
1266         /* adv_rd_off */
1267         temp = dev_t->t_avdp_r;
1268         /* XXX: mux check required ? */
1269         if (mux) {
1270                 /* XXX: t_avdp not to be required for sync, only added for tusb
1271                  * this indirectly necessitates requirement of t_avdp_r and
1272                  * t_avdp_w instead of having a single t_avdp
1273                  */
1274                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1275                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1276         }
1277         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1278
1279         /* oe_on */
1280         temp = dev_t->t_oeasu; /* XXX: remove this ? */
1281         if (mux) {
1282                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1283                 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1284                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1285         }
1286         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1287
1288         /* access */
1289         /* XXX: any scope for improvement ?, by combining oe_on
1290          * and clk_activation, need to check whether
1291          * access = clk_activation + round to sync clk ?
1292          */
1293         temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1294         temp += gpmc_t->clk_activation;
1295         if (dev_t->cyc_oe)
1296                 temp = max_t(u32, temp, gpmc_t->oe_on +
1297                                 gpmc_ticks_to_ps(dev_t->cyc_oe));
1298         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1299
1300         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1301         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1302
1303         /* rd_cycle */
1304         temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1305         temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1306                                                         gpmc_t->access;
1307         /* XXX: barter t_ce_rdyz with t_cez_r ? */
1308         if (dev_t->t_ce_rdyz)
1309                 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1310         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1311
1312         return 0;
1313 }
1314
1315 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1316                                         struct gpmc_device_timings *dev_t,
1317                                         bool mux)
1318 {
1319         u32 temp;
1320
1321         /* adv_wr_off */
1322         temp = dev_t->t_avdp_w;
1323         if (mux) {
1324                 temp = max_t(u32, temp,
1325                         gpmc_t->clk_activation + dev_t->t_avdh);
1326                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1327         }
1328         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1329
1330         /* wr_data_mux_bus */
1331         temp = max_t(u32, dev_t->t_weasu,
1332                         gpmc_t->clk_activation + dev_t->t_rdyo);
1333         /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1334          * and in that case remember to handle we_on properly
1335          */
1336         if (mux) {
1337                 temp = max_t(u32, temp,
1338                         gpmc_t->adv_wr_off + dev_t->t_aavdh);
1339                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1340                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1341         }
1342         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1343
1344         /* we_on */
1345         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1346                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1347         else
1348                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1349
1350         /* wr_access */
1351         /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1352         gpmc_t->wr_access = gpmc_t->access;
1353
1354         /* we_off */
1355         temp = gpmc_t->we_on + dev_t->t_wpl;
1356         temp = max_t(u32, temp,
1357                         gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1358         temp = max_t(u32, temp,
1359                 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1360         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1361
1362         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1363                                                         dev_t->t_wph);
1364
1365         /* wr_cycle */
1366         temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1367         temp += gpmc_t->wr_access;
1368         /* XXX: barter t_ce_rdyz with t_cez_w ? */
1369         if (dev_t->t_ce_rdyz)
1370                 temp = max_t(u32, temp,
1371                                  gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1372         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1373
1374         return 0;
1375 }
1376
1377 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1378                                         struct gpmc_device_timings *dev_t,
1379                                         bool mux)
1380 {
1381         u32 temp;
1382
1383         /* adv_rd_off */
1384         temp = dev_t->t_avdp_r;
1385         if (mux)
1386                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1387         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1388
1389         /* oe_on */
1390         temp = dev_t->t_oeasu;
1391         if (mux)
1392                 temp = max_t(u32, temp,
1393                         gpmc_t->adv_rd_off + dev_t->t_aavdh);
1394         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1395
1396         /* access */
1397         temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1398                                 gpmc_t->oe_on + dev_t->t_oe);
1399         temp = max_t(u32, temp,
1400                                 gpmc_t->cs_on + dev_t->t_ce);
1401         temp = max_t(u32, temp,
1402                                 gpmc_t->adv_on + dev_t->t_aa);
1403         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1404
1405         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1406         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1407
1408         /* rd_cycle */
1409         temp = max_t(u32, dev_t->t_rd_cycle,
1410                         gpmc_t->cs_rd_off + dev_t->t_cez_r);
1411         temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1412         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1413
1414         return 0;
1415 }
1416
1417 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1418                                          struct gpmc_device_timings *dev_t,
1419                                          bool mux)
1420 {
1421         u32 temp;
1422
1423         /* adv_wr_off */
1424         temp = dev_t->t_avdp_w;
1425         if (mux)
1426                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1427         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1428
1429         /* wr_data_mux_bus */
1430         temp = dev_t->t_weasu;
1431         if (mux) {
1432                 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1433                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1434                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1435         }
1436         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1437
1438         /* we_on */
1439         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1440                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1441         else
1442                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1443
1444         /* we_off */
1445         temp = gpmc_t->we_on + dev_t->t_wpl;
1446         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1447
1448         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1449                                                         dev_t->t_wph);
1450
1451         /* wr_cycle */
1452         temp = max_t(u32, dev_t->t_wr_cycle,
1453                                 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1454         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1455
1456         return 0;
1457 }
1458
1459 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1460                         struct gpmc_device_timings *dev_t)
1461 {
1462         u32 temp;
1463
1464         gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1465                                                 gpmc_get_fclk_period();
1466
1467         gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1468                                         dev_t->t_bacc,
1469                                         gpmc_t->sync_clk);
1470
1471         temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1472         gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1473
1474         if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1475                 return 0;
1476
1477         if (dev_t->ce_xdelay)
1478                 gpmc_t->bool_timings.cs_extra_delay = true;
1479         if (dev_t->avd_xdelay)
1480                 gpmc_t->bool_timings.adv_extra_delay = true;
1481         if (dev_t->oe_xdelay)
1482                 gpmc_t->bool_timings.oe_extra_delay = true;
1483         if (dev_t->we_xdelay)
1484                 gpmc_t->bool_timings.we_extra_delay = true;
1485
1486         return 0;
1487 }
1488
1489 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1490                                     struct gpmc_device_timings *dev_t,
1491                                     bool sync)
1492 {
1493         u32 temp;
1494
1495         /* cs_on */
1496         gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1497
1498         /* adv_on */
1499         temp = dev_t->t_avdasu;
1500         if (dev_t->t_ce_avd)
1501                 temp = max_t(u32, temp,
1502                                 gpmc_t->cs_on + dev_t->t_ce_avd);
1503         gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1504
1505         if (sync)
1506                 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1507
1508         return 0;
1509 }
1510
1511 /* TODO: remove this function once all peripherals are confirmed to
1512  * work with generic timing. Simultaneously gpmc_cs_set_timings()
1513  * has to be modified to handle timings in ps instead of ns
1514 */
1515 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1516 {
1517         t->cs_on /= 1000;
1518         t->cs_rd_off /= 1000;
1519         t->cs_wr_off /= 1000;
1520         t->adv_on /= 1000;
1521         t->adv_rd_off /= 1000;
1522         t->adv_wr_off /= 1000;
1523         t->we_on /= 1000;
1524         t->we_off /= 1000;
1525         t->oe_on /= 1000;
1526         t->oe_off /= 1000;
1527         t->page_burst_access /= 1000;
1528         t->access /= 1000;
1529         t->rd_cycle /= 1000;
1530         t->wr_cycle /= 1000;
1531         t->bus_turnaround /= 1000;
1532         t->cycle2cycle_delay /= 1000;
1533         t->wait_monitoring /= 1000;
1534         t->clk_activation /= 1000;
1535         t->wr_access /= 1000;
1536         t->wr_data_mux_bus /= 1000;
1537 }
1538
1539 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1540                       struct gpmc_settings *gpmc_s,
1541                       struct gpmc_device_timings *dev_t)
1542 {
1543         bool mux = false, sync = false;
1544
1545         if (gpmc_s) {
1546                 mux = gpmc_s->mux_add_data ? true : false;
1547                 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1548         }
1549
1550         memset(gpmc_t, 0, sizeof(*gpmc_t));
1551
1552         gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1553
1554         if (gpmc_s && gpmc_s->sync_read)
1555                 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1556         else
1557                 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1558
1559         if (gpmc_s && gpmc_s->sync_write)
1560                 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1561         else
1562                 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1563
1564         /* TODO: remove, see function definition */
1565         gpmc_convert_ps_to_ns(gpmc_t);
1566
1567         return 0;
1568 }
1569
1570 /**
1571  * gpmc_cs_program_settings - programs non-timing related settings
1572  * @cs:         GPMC chip-select to program
1573  * @p:          pointer to GPMC settings structure
1574  *
1575  * Programs non-timing related settings for a GPMC chip-select, such as
1576  * bus-width, burst configuration, etc. Function should be called once
1577  * for each chip-select that is being used and must be called before
1578  * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1579  * register will be initialised to zero by this function. Returns 0 on
1580  * success and appropriate negative error code on failure.
1581  */
1582 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1583 {
1584         u32 config1;
1585
1586         if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1587                 pr_err("%s: invalid width %d!", __func__, p->device_width);
1588                 return -EINVAL;
1589         }
1590
1591         /* Address-data multiplexing not supported for NAND devices */
1592         if (p->device_nand && p->mux_add_data) {
1593                 pr_err("%s: invalid configuration!\n", __func__);
1594                 return -EINVAL;
1595         }
1596
1597         if ((p->mux_add_data > GPMC_MUX_AD) ||
1598             ((p->mux_add_data == GPMC_MUX_AAD) &&
1599              !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1600                 pr_err("%s: invalid multiplex configuration!\n", __func__);
1601                 return -EINVAL;
1602         }
1603
1604         /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1605         if (p->burst_read || p->burst_write) {
1606                 switch (p->burst_len) {
1607                 case GPMC_BURST_4:
1608                 case GPMC_BURST_8:
1609                 case GPMC_BURST_16:
1610                         break;
1611                 default:
1612                         pr_err("%s: invalid page/burst-length (%d)\n",
1613                                __func__, p->burst_len);
1614                         return -EINVAL;
1615                 }
1616         }
1617
1618         if (p->wait_pin > gpmc_nr_waitpins) {
1619                 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1620                 return -EINVAL;
1621         }
1622
1623         config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1624
1625         if (p->sync_read)
1626                 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1627         if (p->sync_write)
1628                 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1629         if (p->wait_on_read)
1630                 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1631         if (p->wait_on_write)
1632                 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1633         if (p->wait_on_read || p->wait_on_write)
1634                 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1635         if (p->device_nand)
1636                 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1637         if (p->mux_add_data)
1638                 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1639         if (p->burst_read)
1640                 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1641         if (p->burst_write)
1642                 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1643         if (p->burst_read || p->burst_write) {
1644                 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1645                 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1646         }
1647
1648         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1649
1650         return 0;
1651 }
1652
1653 #ifdef CONFIG_OF
1654 static const struct of_device_id gpmc_dt_ids[] = {
1655         { .compatible = "ti,omap2420-gpmc" },
1656         { .compatible = "ti,omap2430-gpmc" },
1657         { .compatible = "ti,omap3430-gpmc" },   /* omap3430 & omap3630 */
1658         { .compatible = "ti,omap4430-gpmc" },   /* omap4430 & omap4460 & omap543x */
1659         { .compatible = "ti,am3352-gpmc" },     /* am335x devices */
1660         { }
1661 };
1662 MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
1663
1664 /**
1665  * gpmc_read_settings_dt - read gpmc settings from device-tree
1666  * @np:         pointer to device-tree node for a gpmc child device
1667  * @p:          pointer to gpmc settings structure
1668  *
1669  * Reads the GPMC settings for a GPMC child device from device-tree and
1670  * stores them in the GPMC settings structure passed. The GPMC settings
1671  * structure is initialised to zero by this function and so any
1672  * previously stored settings will be cleared.
1673  */
1674 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1675 {
1676         memset(p, 0, sizeof(struct gpmc_settings));
1677
1678         p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1679         p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1680         of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1681         of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1682
1683         if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1684                 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1685                 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1686                 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1687                 if (!p->burst_read && !p->burst_write)
1688                         pr_warn("%s: page/burst-length set but not used!\n",
1689                                 __func__);
1690         }
1691
1692         if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1693                 p->wait_on_read = of_property_read_bool(np,
1694                                                         "gpmc,wait-on-read");
1695                 p->wait_on_write = of_property_read_bool(np,
1696                                                          "gpmc,wait-on-write");
1697                 if (!p->wait_on_read && !p->wait_on_write)
1698                         pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1699                                  __func__);
1700         }
1701 }
1702
1703 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1704                                                 struct gpmc_timings *gpmc_t)
1705 {
1706         struct gpmc_bool_timings *p;
1707
1708         if (!np || !gpmc_t)
1709                 return;
1710
1711         memset(gpmc_t, 0, sizeof(*gpmc_t));
1712
1713         /* minimum clock period for syncronous mode */
1714         of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
1715
1716         /* chip select timtings */
1717         of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1718         of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1719         of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
1720
1721         /* ADV signal timings */
1722         of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1723         of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1724         of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
1725
1726         /* WE signal timings */
1727         of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1728         of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
1729
1730         /* OE signal timings */
1731         of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1732         of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
1733
1734         /* access and cycle timings */
1735         of_property_read_u32(np, "gpmc,page-burst-access-ns",
1736                              &gpmc_t->page_burst_access);
1737         of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1738         of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1739         of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1740         of_property_read_u32(np, "gpmc,bus-turnaround-ns",
1741                              &gpmc_t->bus_turnaround);
1742         of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
1743                              &gpmc_t->cycle2cycle_delay);
1744         of_property_read_u32(np, "gpmc,wait-monitoring-ns",
1745                              &gpmc_t->wait_monitoring);
1746         of_property_read_u32(np, "gpmc,clk-activation-ns",
1747                              &gpmc_t->clk_activation);
1748
1749         /* only applicable to OMAP3+ */
1750         of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
1751         of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
1752                              &gpmc_t->wr_data_mux_bus);
1753
1754         /* bool timing parameters */
1755         p = &gpmc_t->bool_timings;
1756
1757         p->cycle2cyclediffcsen =
1758                 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
1759         p->cycle2cyclesamecsen =
1760                 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
1761         p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
1762         p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
1763         p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
1764         p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
1765         p->time_para_granularity =
1766                 of_property_read_bool(np, "gpmc,time-para-granularity");
1767 }
1768
1769 #if IS_ENABLED(CONFIG_MTD_NAND)
1770
1771 static const char * const nand_xfer_types[] = {
1772         [NAND_OMAP_PREFETCH_POLLED]             = "prefetch-polled",
1773         [NAND_OMAP_POLLED]                      = "polled",
1774         [NAND_OMAP_PREFETCH_DMA]                = "prefetch-dma",
1775         [NAND_OMAP_PREFETCH_IRQ]                = "prefetch-irq",
1776 };
1777
1778 static int gpmc_probe_nand_child(struct platform_device *pdev,
1779                                  struct device_node *child)
1780 {
1781         u32 val;
1782         const char *s;
1783         struct gpmc_timings gpmc_t;
1784         struct omap_nand_platform_data *gpmc_nand_data;
1785
1786         if (of_property_read_u32(child, "reg", &val) < 0) {
1787                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1788                         child->full_name);
1789                 return -ENODEV;
1790         }
1791
1792         gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
1793                                       GFP_KERNEL);
1794         if (!gpmc_nand_data)
1795                 return -ENOMEM;
1796
1797         gpmc_nand_data->cs = val;
1798         gpmc_nand_data->of_node = child;
1799
1800         /* Detect availability of ELM module */
1801         gpmc_nand_data->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0);
1802         if (gpmc_nand_data->elm_of_node == NULL)
1803                 gpmc_nand_data->elm_of_node =
1804                                         of_parse_phandle(child, "elm_id", 0);
1805
1806         /* select ecc-scheme for NAND */
1807         if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) {
1808                 pr_err("%s: ti,nand-ecc-opt not found\n", __func__);
1809                 return -ENODEV;
1810         }
1811
1812         if (!strcmp(s, "sw"))
1813                 gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
1814         else if (!strcmp(s, "ham1") ||
1815                  !strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
1816                 gpmc_nand_data->ecc_opt =
1817                                 OMAP_ECC_HAM1_CODE_HW;
1818         else if (!strcmp(s, "bch4"))
1819                 if (gpmc_nand_data->elm_of_node)
1820                         gpmc_nand_data->ecc_opt =
1821                                 OMAP_ECC_BCH4_CODE_HW;
1822                 else
1823                         gpmc_nand_data->ecc_opt =
1824                                 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;
1825         else if (!strcmp(s, "bch8"))
1826                 if (gpmc_nand_data->elm_of_node)
1827                         gpmc_nand_data->ecc_opt =
1828                                 OMAP_ECC_BCH8_CODE_HW;
1829                 else
1830                         gpmc_nand_data->ecc_opt =
1831                                 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
1832         else if (!strcmp(s, "bch16"))
1833                 if (gpmc_nand_data->elm_of_node)
1834                         gpmc_nand_data->ecc_opt =
1835                                 OMAP_ECC_BCH16_CODE_HW;
1836                 else
1837                         pr_err("%s: BCH16 requires ELM support\n", __func__);
1838         else
1839                 pr_err("%s: ti,nand-ecc-opt invalid value\n", __func__);
1840
1841         /* select data transfer mode for NAND controller */
1842         if (!of_property_read_string(child, "ti,nand-xfer-type", &s))
1843                 for (val = 0; val < ARRAY_SIZE(nand_xfer_types); val++)
1844                         if (!strcasecmp(s, nand_xfer_types[val])) {
1845                                 gpmc_nand_data->xfer_type = val;
1846                                 break;
1847                         }
1848
1849         gpmc_nand_data->flash_bbt = of_get_nand_on_flash_bbt(child);
1850
1851         val = of_get_nand_bus_width(child);
1852         if (val == 16)
1853                 gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
1854
1855         gpmc_read_timings_dt(child, &gpmc_t);
1856         gpmc_nand_init(gpmc_nand_data, &gpmc_t);
1857
1858         return 0;
1859 }
1860 #else
1861 static int gpmc_probe_nand_child(struct platform_device *pdev,
1862                                  struct device_node *child)
1863 {
1864         return 0;
1865 }
1866 #endif
1867
1868 #if IS_ENABLED(CONFIG_MTD_ONENAND)
1869 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1870                                  struct device_node *child)
1871 {
1872         u32 val;
1873         struct omap_onenand_platform_data *gpmc_onenand_data;
1874
1875         if (of_property_read_u32(child, "reg", &val) < 0) {
1876                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1877                         child->full_name);
1878                 return -ENODEV;
1879         }
1880
1881         gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
1882                                          GFP_KERNEL);
1883         if (!gpmc_onenand_data)
1884                 return -ENOMEM;
1885
1886         gpmc_onenand_data->cs = val;
1887         gpmc_onenand_data->of_node = child;
1888         gpmc_onenand_data->dma_channel = -1;
1889
1890         if (!of_property_read_u32(child, "dma-channel", &val))
1891                 gpmc_onenand_data->dma_channel = val;
1892
1893         gpmc_onenand_init(gpmc_onenand_data);
1894
1895         return 0;
1896 }
1897 #else
1898 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1899                                     struct device_node *child)
1900 {
1901         return 0;
1902 }
1903 #endif
1904
1905 /**
1906  * gpmc_probe_generic_child - configures the gpmc for a child device
1907  * @pdev:       pointer to gpmc platform device
1908  * @child:      pointer to device-tree node for child device
1909  *
1910  * Allocates and configures a GPMC chip-select for a child device.
1911  * Returns 0 on success and appropriate negative error code on failure.
1912  */
1913 static int gpmc_probe_generic_child(struct platform_device *pdev,
1914                                 struct device_node *child)
1915 {
1916         struct gpmc_settings gpmc_s;
1917         struct gpmc_timings gpmc_t;
1918         struct resource res;
1919         unsigned long base;
1920         const char *name;
1921         int ret, cs;
1922         u32 val;
1923
1924         if (of_property_read_u32(child, "reg", &cs) < 0) {
1925                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1926                         child->full_name);
1927                 return -ENODEV;
1928         }
1929
1930         if (of_address_to_resource(child, 0, &res) < 0) {
1931                 dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
1932                         child->full_name);
1933                 return -ENODEV;
1934         }
1935
1936         /*
1937          * Check if we have multiple instances of the same device
1938          * on a single chip select. If so, use the already initialized
1939          * timings.
1940          */
1941         name = gpmc_cs_get_name(cs);
1942         if (name && child->name && of_node_cmp(child->name, name) == 0)
1943                         goto no_timings;
1944
1945         ret = gpmc_cs_request(cs, resource_size(&res), &base);
1946         if (ret < 0) {
1947                 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
1948                 return ret;
1949         }
1950         gpmc_cs_set_name(cs, child->name);
1951
1952         gpmc_read_settings_dt(child, &gpmc_s);
1953         gpmc_read_timings_dt(child, &gpmc_t);
1954
1955         /*
1956          * For some GPMC devices we still need to rely on the bootloader
1957          * timings because the devices can be connected via FPGA.
1958          * REVISIT: Add timing support from slls644g.pdf.
1959          */
1960         if (!gpmc_t.cs_rd_off) {
1961                 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
1962                         cs);
1963                 gpmc_cs_show_timings(cs,
1964                                      "please add GPMC bootloader timings to .dts");
1965                 goto no_timings;
1966         }
1967
1968         /* CS must be disabled while making changes to gpmc configuration */
1969         gpmc_cs_disable_mem(cs);
1970
1971         /*
1972          * FIXME: gpmc_cs_request() will map the CS to an arbitary
1973          * location in the gpmc address space. When booting with
1974          * device-tree we want the NOR flash to be mapped to the
1975          * location specified in the device-tree blob. So remap the
1976          * CS to this location. Once DT migration is complete should
1977          * just make gpmc_cs_request() map a specific address.
1978          */
1979         ret = gpmc_cs_remap(cs, res.start);
1980         if (ret < 0) {
1981                 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
1982                         cs, &res.start);
1983                 goto err;
1984         }
1985
1986         ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width);
1987         if (ret < 0)
1988                 goto err;
1989
1990         gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
1991         ret = gpmc_cs_program_settings(cs, &gpmc_s);
1992         if (ret < 0)
1993                 goto err;
1994
1995         ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
1996         if (ret) {
1997                 dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n",
1998                         child->name);
1999                 goto err;
2000         }
2001
2002         /* Clear limited address i.e. enable A26-A11 */
2003         val = gpmc_read_reg(GPMC_CONFIG);
2004         val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2005         gpmc_write_reg(GPMC_CONFIG, val);
2006
2007         /* Enable CS region */
2008         gpmc_cs_enable_mem(cs);
2009
2010 no_timings:
2011
2012         /* create platform device, NULL on error or when disabled */
2013         if (!of_platform_device_create(child, NULL, &pdev->dev))
2014                 goto err_child_fail;
2015
2016         /* is child a common bus? */
2017         if (of_match_node(of_default_bus_match_table, child))
2018                 /* create children and other common bus children */
2019                 if (of_platform_populate(child, of_default_bus_match_table,
2020                                          NULL, &pdev->dev))
2021                         goto err_child_fail;
2022
2023         return 0;
2024
2025 err_child_fail:
2026
2027         dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
2028         ret = -ENODEV;
2029
2030 err:
2031         gpmc_cs_free(cs);
2032
2033         return ret;
2034 }
2035
2036 static int gpmc_probe_dt(struct platform_device *pdev)
2037 {
2038         int ret;
2039         struct device_node *child;
2040         const struct of_device_id *of_id =
2041                 of_match_device(gpmc_dt_ids, &pdev->dev);
2042
2043         if (!of_id)
2044                 return 0;
2045
2046         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2047                                    &gpmc_cs_num);
2048         if (ret < 0) {
2049                 pr_err("%s: number of chip-selects not defined\n", __func__);
2050                 return ret;
2051         } else if (gpmc_cs_num < 1) {
2052                 pr_err("%s: all chip-selects are disabled\n", __func__);
2053                 return -EINVAL;
2054         } else if (gpmc_cs_num > GPMC_CS_NUM) {
2055                 pr_err("%s: number of supported chip-selects cannot be > %d\n",
2056                                          __func__, GPMC_CS_NUM);
2057                 return -EINVAL;
2058         }
2059
2060         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2061                                    &gpmc_nr_waitpins);
2062         if (ret < 0) {
2063                 pr_err("%s: number of wait pins not found!\n", __func__);
2064                 return ret;
2065         }
2066
2067         for_each_available_child_of_node(pdev->dev.of_node, child) {
2068
2069                 if (!child->name)
2070                         continue;
2071
2072                 if (of_node_cmp(child->name, "nand") == 0)
2073                         ret = gpmc_probe_nand_child(pdev, child);
2074                 else if (of_node_cmp(child->name, "onenand") == 0)
2075                         ret = gpmc_probe_onenand_child(pdev, child);
2076                 else
2077                         ret = gpmc_probe_generic_child(pdev, child);
2078         }
2079
2080         return 0;
2081 }
2082 #else
2083 static int gpmc_probe_dt(struct platform_device *pdev)
2084 {
2085         return 0;
2086 }
2087 #endif
2088
2089 static int gpmc_probe(struct platform_device *pdev)
2090 {
2091         int rc;
2092         u32 l;
2093         struct resource *res;
2094
2095         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2096         if (res == NULL)
2097                 return -ENOENT;
2098
2099         phys_base = res->start;
2100         mem_size = resource_size(res);
2101
2102         gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2103         if (IS_ERR(gpmc_base))
2104                 return PTR_ERR(gpmc_base);
2105
2106         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2107         if (res == NULL)
2108                 dev_warn(&pdev->dev, "Failed to get resource: irq\n");
2109         else
2110                 gpmc_irq = res->start;
2111
2112         gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
2113         if (IS_ERR(gpmc_l3_clk)) {
2114                 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
2115                 gpmc_irq = 0;
2116                 return PTR_ERR(gpmc_l3_clk);
2117         }
2118
2119         if (!clk_get_rate(gpmc_l3_clk)) {
2120                 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2121                 return -EINVAL;
2122         }
2123
2124         pm_runtime_enable(&pdev->dev);
2125         pm_runtime_get_sync(&pdev->dev);
2126
2127         gpmc_dev = &pdev->dev;
2128
2129         l = gpmc_read_reg(GPMC_REVISION);
2130
2131         /*
2132          * FIXME: Once device-tree migration is complete the below flags
2133          * should be populated based upon the device-tree compatible
2134          * string. For now just use the IP revision. OMAP3+ devices have
2135          * the wr_access and wr_data_mux_bus register fields. OMAP4+
2136          * devices support the addr-addr-data multiplex protocol.
2137          *
2138          * GPMC IP revisions:
2139          * - OMAP24xx                   = 2.0
2140          * - OMAP3xxx                   = 5.0
2141          * - OMAP44xx/54xx/AM335x       = 6.0
2142          */
2143         if (GPMC_REVISION_MAJOR(l) > 0x4)
2144                 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
2145         if (GPMC_REVISION_MAJOR(l) > 0x5)
2146                 gpmc_capability |= GPMC_HAS_MUX_AAD;
2147         dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
2148                  GPMC_REVISION_MINOR(l));
2149
2150         gpmc_mem_init();
2151
2152         if (gpmc_setup_irq() < 0)
2153                 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
2154
2155         if (!pdev->dev.of_node) {
2156                 gpmc_cs_num      = GPMC_CS_NUM;
2157                 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2158         }
2159
2160         rc = gpmc_probe_dt(pdev);
2161         if (rc < 0) {
2162                 pm_runtime_put_sync(&pdev->dev);
2163                 dev_err(gpmc_dev, "failed to probe DT parameters\n");
2164                 return rc;
2165         }
2166
2167         return 0;
2168 }
2169
2170 static int gpmc_remove(struct platform_device *pdev)
2171 {
2172         gpmc_free_irq();
2173         gpmc_mem_exit();
2174         pm_runtime_put_sync(&pdev->dev);
2175         pm_runtime_disable(&pdev->dev);
2176         gpmc_dev = NULL;
2177         return 0;
2178 }
2179
2180 #ifdef CONFIG_PM_SLEEP
2181 static int gpmc_suspend(struct device *dev)
2182 {
2183         omap3_gpmc_save_context();
2184         pm_runtime_put_sync(dev);
2185         return 0;
2186 }
2187
2188 static int gpmc_resume(struct device *dev)
2189 {
2190         pm_runtime_get_sync(dev);
2191         omap3_gpmc_restore_context();
2192         return 0;
2193 }
2194 #endif
2195
2196 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2197
2198 static struct platform_driver gpmc_driver = {
2199         .probe          = gpmc_probe,
2200         .remove         = gpmc_remove,
2201         .driver         = {
2202                 .name   = DEVICE_NAME,
2203                 .of_match_table = of_match_ptr(gpmc_dt_ids),
2204                 .pm     = &gpmc_pm_ops,
2205         },
2206 };
2207
2208 static __init int gpmc_init(void)
2209 {
2210         return platform_driver_register(&gpmc_driver);
2211 }
2212
2213 static __exit void gpmc_exit(void)
2214 {
2215         platform_driver_unregister(&gpmc_driver);
2216
2217 }
2218
2219 postcore_initcall(gpmc_init);
2220 module_exit(gpmc_exit);
2221
2222 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
2223 {
2224         int i;
2225         u32 regval;
2226
2227         regval = gpmc_read_reg(GPMC_IRQSTATUS);
2228
2229         if (!regval)
2230                 return IRQ_NONE;
2231
2232         for (i = 0; i < GPMC_NR_IRQ; i++)
2233                 if (regval & gpmc_client_irq[i].bitmask)
2234                         generic_handle_irq(gpmc_client_irq[i].irq);
2235
2236         gpmc_write_reg(GPMC_IRQSTATUS, regval);
2237
2238         return IRQ_HANDLED;
2239 }
2240
2241 static struct omap3_gpmc_regs gpmc_context;
2242
2243 void omap3_gpmc_save_context(void)
2244 {
2245         int i;
2246
2247         if (!gpmc_base)
2248                 return;
2249
2250         gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2251         gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2252         gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2253         gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2254         gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2255         gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2256         gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2257         for (i = 0; i < gpmc_cs_num; i++) {
2258                 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2259                 if (gpmc_context.cs_context[i].is_valid) {
2260                         gpmc_context.cs_context[i].config1 =
2261                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2262                         gpmc_context.cs_context[i].config2 =
2263                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2264                         gpmc_context.cs_context[i].config3 =
2265                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2266                         gpmc_context.cs_context[i].config4 =
2267                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2268                         gpmc_context.cs_context[i].config5 =
2269                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2270                         gpmc_context.cs_context[i].config6 =
2271                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2272                         gpmc_context.cs_context[i].config7 =
2273                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2274                 }
2275         }
2276 }
2277
2278 void omap3_gpmc_restore_context(void)
2279 {
2280         int i;
2281
2282         if (!gpmc_base)
2283                 return;
2284
2285         gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2286         gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2287         gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2288         gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2289         gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2290         gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2291         gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
2292         for (i = 0; i < gpmc_cs_num; i++) {
2293                 if (gpmc_context.cs_context[i].is_valid) {
2294                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2295                                 gpmc_context.cs_context[i].config1);
2296                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2297                                 gpmc_context.cs_context[i].config2);
2298                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2299                                 gpmc_context.cs_context[i].config3);
2300                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2301                                 gpmc_context.cs_context[i].config4);
2302                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2303                                 gpmc_context.cs_context[i].config5);
2304                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2305                                 gpmc_context.cs_context[i].config6);
2306                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2307                                 gpmc_context.cs_context[i].config7);
2308                 }
2309         }
2310 }