drivers/mfd/intel-lpss.c

   1 /*
   2  * Intel Sunrisepoint LPSS core support.
   3  *
   4  * Copyright (C) 2015, Intel Corporation
   5  *
   6  * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
   7  *          Mika Westerberg <mika.westerberg@linux.intel.com>
   8  *          Heikki Krogerus <heikki.krogerus@linux.intel.com>
   9  *          Jarkko Nikula <jarkko.nikula@linux.intel.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/clkdev.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/debugfs.h>
  20 #include <linux/idr.h>
  21 #include <linux/ioport.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/mfd/core.h>
  25 #include <linux/pm_qos.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/seq_file.h>
  28
  29 #include <asm-generic/io-64-nonatomic-lo-hi.h>
  30
  31 #include "intel-lpss.h"
  32
  33 #define LPSS_DEV_OFFSET         0x000
  34 #define LPSS_DEV_SIZE           0x200
  35 #define LPSS_PRIV_OFFSET        0x200
  36 #define LPSS_PRIV_SIZE          0x100
  37 #define LPSS_IDMA64_OFFSET      0x800
  38 #define LPSS_IDMA64_SIZE        0x800
  39
  40 /* Offsets from lpss->priv */
  41 #define LPSS_PRIV_RESETS                0x04
  42 #define LPSS_PRIV_RESETS_FUNC           BIT(2)
  43 #define LPSS_PRIV_RESETS_IDMA           0x3
  44
  45 #define LPSS_PRIV_ACTIVELTR             0x10
  46 #define LPSS_PRIV_IDLELTR               0x14
  47
  48 #define LPSS_PRIV_LTR_REQ               BIT(15)
  49 #define LPSS_PRIV_LTR_SCALE_MASK        0xc00
  50 #define LPSS_PRIV_LTR_SCALE_1US         0x800
  51 #define LPSS_PRIV_LTR_SCALE_32US        0xc00
  52 #define LPSS_PRIV_LTR_VALUE_MASK        0x3ff
  53
  54 #define LPSS_PRIV_SSP_REG               0x20
  55 #define LPSS_PRIV_SSP_REG_DIS_DMA_FIN   BIT(0)
  56
  57 #define LPSS_PRIV_REMAP_ADDR            0x40
  58
  59 #define LPSS_PRIV_CAPS                  0xfc
  60 #define LPSS_PRIV_CAPS_NO_IDMA          BIT(8)
  61 #define LPSS_PRIV_CAPS_TYPE_SHIFT       4
  62 #define LPSS_PRIV_CAPS_TYPE_MASK        (0xf << LPSS_PRIV_CAPS_TYPE_SHIFT)
  63
  64 /* This matches the type field in CAPS register */
  65 enum intel_lpss_dev_type {
  66         LPSS_DEV_I2C = 0,
  67         LPSS_DEV_UART,
  68         LPSS_DEV_SPI,
  69 };
  70
  71 struct intel_lpss {
  72         const struct intel_lpss_platform_info *info;
  73         enum intel_lpss_dev_type type;
  74         struct clk *clk;
  75         struct clk_lookup *clock;
  76         const struct mfd_cell *cell;
  77         struct device *dev;
  78         void __iomem *priv;
  79         int devid;
  80         u32 caps;
  81         u32 active_ltr;
  82         u32 idle_ltr;
  83         struct dentry *debugfs;
  84 };
  85
  86 static const struct resource intel_lpss_dev_resources[] = {
  87         DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET, LPSS_DEV_SIZE, "lpss_dev"),
  88         DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET, LPSS_PRIV_SIZE, "lpss_priv"),
  89         DEFINE_RES_IRQ(0),
  90 };
  91
  92 static const struct resource intel_lpss_idma64_resources[] = {
  93         DEFINE_RES_MEM(LPSS_IDMA64_OFFSET, LPSS_IDMA64_SIZE),
  94         DEFINE_RES_IRQ(0),
  95 };
  96
  97 #define LPSS_IDMA64_DRIVER_NAME         "idma64"
  98
  99 /*
 100  * Cells needs to be ordered so that the iDMA is created first. This is
 101  * because we need to be sure the DMA is available when the host controller
 102  * driver is probed.
 103  */
 104 static const struct mfd_cell intel_lpss_idma64_cell = {
 105         .name = LPSS_IDMA64_DRIVER_NAME,
 106         .num_resources = ARRAY_SIZE(intel_lpss_idma64_resources),
 107         .resources = intel_lpss_idma64_resources,
 108 };
 109
 110 static const struct mfd_cell intel_lpss_i2c_cell = {
 111         .name = "i2c_designware",
 112         .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
 113         .resources = intel_lpss_dev_resources,
 114 };
 115
 116 static const struct mfd_cell intel_lpss_uart_cell = {
 117         .name = "dw-apb-uart",
 118         .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
 119         .resources = intel_lpss_dev_resources,
 120 };
 121
 122 static const struct mfd_cell intel_lpss_spi_cell = {
 123         .name = "pxa2xx-spi",
 124         .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
 125         .resources = intel_lpss_dev_resources,
 126 };
 127
 128 static DEFINE_IDA(intel_lpss_devid_ida);
 129 static struct dentry *intel_lpss_debugfs;
 130
 131 static int intel_lpss_request_dma_module(const char *name)
 132 {
 133         static bool intel_lpss_dma_requested;
 134
 135         if (intel_lpss_dma_requested)
 136                 return 0;
 137
 138         intel_lpss_dma_requested = true;
 139         return request_module("%s", name);
 140 }
 141
 142 static void intel_lpss_cache_ltr(struct intel_lpss *lpss)
 143 {
 144         lpss->active_ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
 145         lpss->idle_ltr = readl(lpss->priv + LPSS_PRIV_IDLELTR);
 146 }
 147
 148 static int intel_lpss_debugfs_add(struct intel_lpss *lpss)
 149 {
 150         struct dentry *dir;
 151
 152         dir = debugfs_create_dir(dev_name(lpss->dev), intel_lpss_debugfs);
 153         if (IS_ERR(dir))
 154                 return PTR_ERR(dir);
 155
 156         /* Cache the values into lpss structure */
 157         intel_lpss_cache_ltr(lpss);
 158
 159         debugfs_create_x32("capabilities", S_IRUGO, dir, &lpss->caps);
 160         debugfs_create_x32("active_ltr", S_IRUGO, dir, &lpss->active_ltr);
 161         debugfs_create_x32("idle_ltr", S_IRUGO, dir, &lpss->idle_ltr);
 162
 163         lpss->debugfs = dir;
 164         return 0;
 165 }
 166
 167 static void intel_lpss_debugfs_remove(struct intel_lpss *lpss)
 168 {
 169         debugfs_remove_recursive(lpss->debugfs);
 170 }
 171
 172 static void intel_lpss_ltr_set(struct device *dev, s32 val)
 173 {
 174         struct intel_lpss *lpss = dev_get_drvdata(dev);
 175         u32 ltr;
 176
 177         /*
 178          * Program latency tolerance (LTR) accordingly what has been asked
 179          * by the PM QoS layer or disable it in case we were passed
 180          * negative value or PM_QOS_LATENCY_ANY.
 181          */
 182         ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
 183
 184         if (val == PM_QOS_LATENCY_ANY || val < 0) {
 185                 ltr &= ~LPSS_PRIV_LTR_REQ;
 186         } else {
 187                 ltr |= LPSS_PRIV_LTR_REQ;
 188                 ltr &= ~LPSS_PRIV_LTR_SCALE_MASK;
 189                 ltr &= ~LPSS_PRIV_LTR_VALUE_MASK;
 190
 191                 if (val > LPSS_PRIV_LTR_VALUE_MASK)
 192                         ltr |= LPSS_PRIV_LTR_SCALE_32US | val >> 5;
 193                 else
 194                         ltr |= LPSS_PRIV_LTR_SCALE_1US | val;
 195         }
 196
 197         if (ltr == lpss->active_ltr)
 198                 return;
 199
 200         writel(ltr, lpss->priv + LPSS_PRIV_ACTIVELTR);
 201         writel(ltr, lpss->priv + LPSS_PRIV_IDLELTR);
 202
 203         /* Cache the values into lpss structure */
 204         intel_lpss_cache_ltr(lpss);
 205 }
 206
 207 static void intel_lpss_ltr_expose(struct intel_lpss *lpss)
 208 {
 209         lpss->dev->power.set_latency_tolerance = intel_lpss_ltr_set;
 210         dev_pm_qos_expose_latency_tolerance(lpss->dev);
 211 }
 212
 213 static void intel_lpss_ltr_hide(struct intel_lpss *lpss)
 214 {
 215         dev_pm_qos_hide_latency_tolerance(lpss->dev);
 216         lpss->dev->power.set_latency_tolerance = NULL;
 217 }
 218
 219 static int intel_lpss_assign_devs(struct intel_lpss *lpss)
 220 {
 221         unsigned int type;
 222
 223         type = lpss->caps & LPSS_PRIV_CAPS_TYPE_MASK;
 224         type >>= LPSS_PRIV_CAPS_TYPE_SHIFT;
 225
 226         switch (type) {
 227         case LPSS_DEV_I2C:
 228                 lpss->cell = &intel_lpss_i2c_cell;
 229                 break;
 230         case LPSS_DEV_UART:
 231                 lpss->cell = &intel_lpss_uart_cell;
 232                 break;
 233         case LPSS_DEV_SPI:
 234                 lpss->cell = &intel_lpss_spi_cell;
 235                 break;
 236         default:
 237                 return -ENODEV;
 238         }
 239
 240         lpss->type = type;
 241
 242         return 0;
 243 }
 244
 245 static bool intel_lpss_has_idma(const struct intel_lpss *lpss)
 246 {
 247         return (lpss->caps & LPSS_PRIV_CAPS_NO_IDMA) == 0;
 248 }
 249
 250 static void intel_lpss_set_remap_addr(const struct intel_lpss *lpss)
 251 {
 252         resource_size_t addr = lpss->info->mem->start;
 253
 254         lo_hi_writeq(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR);
 255 }
 256
 257 static void intel_lpss_deassert_reset(const struct intel_lpss *lpss)
 258 {
 259         u32 value = LPSS_PRIV_RESETS_FUNC | LPSS_PRIV_RESETS_IDMA;
 260
 261         /* Bring out the device from reset */
 262         writel(value, lpss->priv + LPSS_PRIV_RESETS);
 263 }
 264
 265 static void intel_lpss_init_dev(const struct intel_lpss *lpss)
 266 {
 267         u32 value = LPSS_PRIV_SSP_REG_DIS_DMA_FIN;
 268
 269         intel_lpss_deassert_reset(lpss);
 270
 271         if (!intel_lpss_has_idma(lpss))
 272                 return;
 273
 274         intel_lpss_set_remap_addr(lpss);
 275
 276         /* Make sure that SPI multiblock DMA transfers are re-enabled */
 277         if (lpss->type == LPSS_DEV_SPI)
 278                 writel(value, lpss->priv + LPSS_PRIV_SSP_REG);
 279 }
 280
 281 static void intel_lpss_unregister_clock_tree(struct clk *clk)
 282 {
 283         struct clk *parent;
 284
 285         while (clk) {
 286                 parent = clk_get_parent(clk);
 287                 clk_unregister(clk);
 288                 clk = parent;
 289         }
 290 }
 291
 292 static int intel_lpss_register_clock_divider(struct intel_lpss *lpss,
 293                                              const char *devname,
 294                                              struct clk **clk)
 295 {
 296         char name[32];
 297         struct clk *tmp = *clk;
 298
 299         snprintf(name, sizeof(name), "%s-enable", devname);
 300         tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0,
 301                                 lpss->priv, 0, 0, NULL);
 302         if (IS_ERR(tmp))
 303                 return PTR_ERR(tmp);
 304
 305         snprintf(name, sizeof(name), "%s-div", devname);
 306         tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp),
 307                                               0, lpss->priv, 1, 15, 16, 15, 0,
 308                                               NULL);
 309         if (IS_ERR(tmp))
 310                 return PTR_ERR(tmp);
 311         *clk = tmp;
 312
 313         snprintf(name, sizeof(name), "%s-update", devname);
 314         tmp = clk_register_gate(NULL, name, __clk_get_name(tmp),
 315                                 CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL);
 316         if (IS_ERR(tmp))
 317                 return PTR_ERR(tmp);
 318         *clk = tmp;
 319
 320         return 0;
 321 }
 322
 323 static int intel_lpss_register_clock(struct intel_lpss *lpss)
 324 {
 325         const struct mfd_cell *cell = lpss->cell;
 326         struct clk *clk;
 327         char devname[24];
 328         int ret;
 329
 330         if (!lpss->info->clk_rate)
 331                 return 0;
 332
 333         /* Root clock */
 334         clk = clk_register_fixed_rate(NULL, dev_name(lpss->dev), NULL,
 335                                       CLK_IS_ROOT, lpss->info->clk_rate);
 336         if (IS_ERR(clk))
 337                 return PTR_ERR(clk);
 338
 339         snprintf(devname, sizeof(devname), "%s.%d", cell->name, lpss->devid);
 340
 341         /*
 342          * Support for clock divider only if it has some preset value.
 343          * Otherwise we assume that the divider is not used.
 344          */
 345         if (lpss->type != LPSS_DEV_I2C) {
 346                 ret = intel_lpss_register_clock_divider(lpss, devname, &clk);
 347                 if (ret)
 348                         goto err_clk_register;
 349         }
 350
 351         ret = -ENOMEM;
 352
 353         /* Clock for the host controller */
 354         lpss->clock = clkdev_create(clk, lpss->info->clk_con_id, "%s", devname);
 355         if (!lpss->clock)
 356                 goto err_clk_register;
 357
 358         lpss->clk = clk;
 359
 360         return 0;
 361
 362 err_clk_register:
 363         intel_lpss_unregister_clock_tree(clk);
 364
 365         return ret;
 366 }
 367
 368 static void intel_lpss_unregister_clock(struct intel_lpss *lpss)
 369 {
 370         if (IS_ERR_OR_NULL(lpss->clk))
 371                 return;
 372
 373         clkdev_drop(lpss->clock);
 374         intel_lpss_unregister_clock_tree(lpss->clk);
 375 }
 376
 377 int intel_lpss_probe(struct device *dev,
 378                      const struct intel_lpss_platform_info *info)
 379 {
 380         struct intel_lpss *lpss;
 381         int ret;
 382
 383         if (!info || !info->mem || info->irq <= 0)
 384                 return -EINVAL;
 385
 386         lpss = devm_kzalloc(dev, sizeof(*lpss), GFP_KERNEL);
 387         if (!lpss)
 388                 return -ENOMEM;
 389
 390         lpss->priv = devm_ioremap(dev, info->mem->start + LPSS_PRIV_OFFSET,
 391                                   LPSS_PRIV_SIZE);
 392         if (!lpss->priv)
 393                 return -ENOMEM;
 394
 395         lpss->info = info;
 396         lpss->dev = dev;
 397         lpss->caps = readl(lpss->priv + LPSS_PRIV_CAPS);
 398
 399         dev_set_drvdata(dev, lpss);
 400
 401         ret = intel_lpss_assign_devs(lpss);
 402         if (ret)
 403                 return ret;
 404
 405         intel_lpss_init_dev(lpss);
 406
 407         lpss->devid = ida_simple_get(&intel_lpss_devid_ida, 0, 0, GFP_KERNEL);
 408         if (lpss->devid < 0)
 409                 return lpss->devid;
 410
 411         ret = intel_lpss_register_clock(lpss);
 412         if (ret)
 413                 goto err_clk_register;
 414
 415         intel_lpss_ltr_expose(lpss);
 416
 417         ret = intel_lpss_debugfs_add(lpss);
 418         if (ret)
 419                 dev_warn(dev, "Failed to create debugfs entries\n");
 420
 421         if (intel_lpss_has_idma(lpss)) {
 422                 /*
 423                  * Ensure the DMA driver is loaded before the host
 424                  * controller device appears, so that the host controller
 425                  * driver can request its DMA channels as early as
 426                  * possible.
 427                  *
 428                  * If the DMA module is not there that's OK as well.
 429                  */
 430                 intel_lpss_request_dma_module(LPSS_IDMA64_DRIVER_NAME);
 431
 432                 ret = mfd_add_devices(dev, lpss->devid, &intel_lpss_idma64_cell,
 433                                       1, info->mem, info->irq, NULL);
 434                 if (ret)
 435                         dev_warn(dev, "Failed to add %s, fallback to PIO\n",
 436                                  LPSS_IDMA64_DRIVER_NAME);
 437         }
 438
 439         ret = mfd_add_devices(dev, lpss->devid, lpss->cell,
 440                               1, info->mem, info->irq, NULL);
 441         if (ret)
 442                 goto err_remove_ltr;
 443
 444         return 0;
 445
 446 err_remove_ltr:
 447         intel_lpss_debugfs_remove(lpss);
 448         intel_lpss_ltr_hide(lpss);
 449
 450 err_clk_register:
 451         ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
 452
 453         return ret;
 454 }
 455 EXPORT_SYMBOL_GPL(intel_lpss_probe);
 456
 457 void intel_lpss_remove(struct device *dev)
 458 {
 459         struct intel_lpss *lpss = dev_get_drvdata(dev);
 460
 461         mfd_remove_devices(dev);
 462         intel_lpss_debugfs_remove(lpss);
 463         intel_lpss_ltr_hide(lpss);
 464         intel_lpss_unregister_clock(lpss);
 465         ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
 466 }
 467 EXPORT_SYMBOL_GPL(intel_lpss_remove);
 468
 469 static int resume_lpss_device(struct device *dev, void *data)
 470 {
 471         pm_runtime_resume(dev);
 472         return 0;
 473 }
 474
 475 int intel_lpss_prepare(struct device *dev)
 476 {
 477         /*
 478          * Resume both child devices before entering system sleep. This
 479          * ensures that they are in proper state before they get suspended.
 480          */
 481         device_for_each_child_reverse(dev, NULL, resume_lpss_device);
 482         return 0;
 483 }
 484 EXPORT_SYMBOL_GPL(intel_lpss_prepare);
 485
 486 int intel_lpss_suspend(struct device *dev)
 487 {
 488         return 0;
 489 }
 490 EXPORT_SYMBOL_GPL(intel_lpss_suspend);
 491
 492 int intel_lpss_resume(struct device *dev)
 493 {
 494         struct intel_lpss *lpss = dev_get_drvdata(dev);
 495
 496         intel_lpss_init_dev(lpss);
 497
 498         return 0;
 499 }
 500 EXPORT_SYMBOL_GPL(intel_lpss_resume);
 501
 502 static int __init intel_lpss_init(void)
 503 {
 504         intel_lpss_debugfs = debugfs_create_dir("intel_lpss", NULL);
 505         return 0;
 506 }
 507 module_init(intel_lpss_init);
 508
 509 static void __exit intel_lpss_exit(void)
 510 {
 511         debugfs_remove(intel_lpss_debugfs);
 512 }
 513 module_exit(intel_lpss_exit);
 514
 515 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
 516 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
 517 MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>");
 518 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
 519 MODULE_DESCRIPTION("Intel LPSS core driver");
 520 MODULE_LICENSE("GPL v2");