drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  36
  37 #include <linux/bitmap.h>
  38 #include <linux/crc32.h>
  39 #include <linux/ctype.h>
  40 #include <linux/debugfs.h>
  41 #include <linux/err.h>
  42 #include <linux/etherdevice.h>
  43 #include <linux/firmware.h>
  44 #include <linux/if.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/init.h>
  47 #include <linux/log2.h>
  48 #include <linux/mdio.h>
  49 #include <linux/module.h>
  50 #include <linux/moduleparam.h>
  51 #include <linux/mutex.h>
  52 #include <linux/netdevice.h>
  53 #include <linux/pci.h>
  54 #include <linux/aer.h>
  55 #include <linux/rtnetlink.h>
  56 #include <linux/sched.h>
  57 #include <linux/seq_file.h>
  58 #include <linux/sockios.h>
  59 #include <linux/vmalloc.h>
  60 #include <linux/workqueue.h>
  61 #include <net/neighbour.h>
  62 #include <net/netevent.h>
  63 #include <net/addrconf.h>
  64 #include <net/bonding.h>
  65 #include <asm/uaccess.h>
  66
  67 #include "cxgb4.h"
  68 #include "t4_regs.h"
  69 #include "t4_msg.h"
  70 #include "t4fw_api.h"
  71 #include "cxgb4_dcb.h"
  72 #include "cxgb4_debugfs.h"
  73 #include "l2t.h"
  74
  75 #ifdef DRV_VERSION
  76 #undef DRV_VERSION
  77 #endif
  78 #define DRV_VERSION "2.0.0-ko"
  79 #define DRV_DESC "Chelsio T4/T5 Network Driver"
  80
  81 /*
  82  * Max interrupt hold-off timer value in us.  Queues fall back to this value
  83  * under extreme memory pressure so it's largish to give the system time to
  84  * recover.
  85  */
  86 #define MAX_SGE_TIMERVAL 200U
  87
  88 enum {
  89         /*
  90          * Physical Function provisioning constants.
  91          */
  92         PFRES_NVI = 4,                  /* # of Virtual Interfaces */
  93         PFRES_NETHCTRL = 128,           /* # of EQs used for ETH or CTRL Qs */
  94         PFRES_NIQFLINT = 128,           /* # of ingress Qs/w Free List(s)/intr
  95                                          */
  96         PFRES_NEQ = 256,                /* # of egress queues */
  97         PFRES_NIQ = 0,                  /* # of ingress queues */
  98         PFRES_TC = 0,                   /* PCI-E traffic class */
  99         PFRES_NEXACTF = 128,            /* # of exact MPS filters */
 100
 101         PFRES_R_CAPS = FW_CMD_CAP_PF,
 102         PFRES_WX_CAPS = FW_CMD_CAP_PF,
 103
 104 #ifdef CONFIG_PCI_IOV
 105         /*
 106          * Virtual Function provisioning constants.  We need two extra Ingress
 107          * Queues with Interrupt capability to serve as the VF's Firmware
 108          * Event Queue and Forwarded Interrupt Queue (when using MSI mode) --
 109          * neither will have Free Lists associated with them).  For each
 110          * Ethernet/Control Egress Queue and for each Free List, we need an
 111          * Egress Context.
 112          */
 113         VFRES_NPORTS = 1,               /* # of "ports" per VF */
 114         VFRES_NQSETS = 2,               /* # of "Queue Sets" per VF */
 115
 116         VFRES_NVI = VFRES_NPORTS,       /* # of Virtual Interfaces */
 117         VFRES_NETHCTRL = VFRES_NQSETS,  /* # of EQs used for ETH or CTRL Qs */
 118         VFRES_NIQFLINT = VFRES_NQSETS+2,/* # of ingress Qs/w Free List(s)/intr */
 119         VFRES_NEQ = VFRES_NQSETS*2,     /* # of egress queues */
 120         VFRES_NIQ = 0,                  /* # of non-fl/int ingress queues */
 121         VFRES_TC = 0,                   /* PCI-E traffic class */
 122         VFRES_NEXACTF = 16,             /* # of exact MPS filters */
 123
 124         VFRES_R_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF|FW_CMD_CAP_PORT,
 125         VFRES_WX_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF,
 126 #endif
 127 };
 128
 129 /*
 130  * Provide a Port Access Rights Mask for the specified PF/VF.  This is very
 131  * static and likely not to be useful in the long run.  We really need to
 132  * implement some form of persistent configuration which the firmware
 133  * controls.
 134  */
 135 static unsigned int pfvfres_pmask(struct adapter *adapter,
 136                                   unsigned int pf, unsigned int vf)
 137 {
 138         unsigned int portn, portvec;
 139
 140         /*
 141          * Give PF's access to all of the ports.
 142          */
 143         if (vf == 0)
 144                 return FW_PFVF_CMD_PMASK_M;
 145
 146         /*
 147          * For VFs, we'll assign them access to the ports based purely on the
 148          * PF.  We assign active ports in order, wrapping around if there are
 149          * fewer active ports than PFs: e.g. active port[pf % nports].
 150          * Unfortunately the adapter's port_info structs haven't been
 151          * initialized yet so we have to compute this.
 152          */
 153         if (adapter->params.nports == 0)
 154                 return 0;
 155
 156         portn = pf % adapter->params.nports;
 157         portvec = adapter->params.portvec;
 158         for (;;) {
 159                 /*
 160                  * Isolate the lowest set bit in the port vector.  If we're at
 161                  * the port number that we want, return that as the pmask.
 162                  * otherwise mask that bit out of the port vector and
 163                  * decrement our port number ...
 164                  */
 165                 unsigned int pmask = portvec ^ (portvec & (portvec-1));
 166                 if (portn == 0)
 167                         return pmask;
 168                 portn--;
 169                 portvec &= ~pmask;
 170         }
 171         /*NOTREACHED*/
 172 }
 173
 174 enum {
 175         MAX_TXQ_ENTRIES      = 16384,
 176         MAX_CTRL_TXQ_ENTRIES = 1024,
 177         MAX_RSPQ_ENTRIES     = 16384,
 178         MAX_RX_BUFFERS       = 16384,
 179         MIN_TXQ_ENTRIES      = 32,
 180         MIN_CTRL_TXQ_ENTRIES = 32,
 181         MIN_RSPQ_ENTRIES     = 128,
 182         MIN_FL_ENTRIES       = 16
 183 };
 184
 185 /* Host shadow copy of ingress filter entry.  This is in host native format
 186  * and doesn't match the ordering or bit order, etc. of the hardware of the
 187  * firmware command.  The use of bit-field structure elements is purely to
 188  * remind ourselves of the field size limitations and save memory in the case
 189  * where the filter table is large.
 190  */
 191 struct filter_entry {
 192         /* Administrative fields for filter.
 193          */
 194         u32 valid:1;            /* filter allocated and valid */
 195         u32 locked:1;           /* filter is administratively locked */
 196
 197         u32 pending:1;          /* filter action is pending firmware reply */
 198         u32 smtidx:8;           /* Source MAC Table index for smac */
 199         struct l2t_entry *l2t;  /* Layer Two Table entry for dmac */
 200
 201         /* The filter itself.  Most of this is a straight copy of information
 202          * provided by the extended ioctl().  Some fields are translated to
 203          * internal forms -- for instance the Ingress Queue ID passed in from
 204          * the ioctl() is translated into the Absolute Ingress Queue ID.
 205          */
 206         struct ch_filter_specification fs;
 207 };
 208
 209 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
 210                          NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
 211                          NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
 212
 213 /* Macros needed to support the PCI Device ID Table ...
 214  */
 215 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
 216         static struct pci_device_id cxgb4_pci_tbl[] = {
 217 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
 218
 219 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
 220  * called for both.
 221  */
 222 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0
 223
 224 #define CH_PCI_ID_TABLE_ENTRY(devid) \
 225                 {PCI_VDEVICE(CHELSIO, (devid)), 4}
 226
 227 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
 228                 { 0, } \
 229         }
 230
 231 #include "t4_pci_id_tbl.h"
 232
 233 #define FW4_FNAME "cxgb4/t4fw.bin"
 234 #define FW5_FNAME "cxgb4/t5fw.bin"
 235 #define FW4_CFNAME "cxgb4/t4-config.txt"
 236 #define FW5_CFNAME "cxgb4/t5-config.txt"
 237
 238 MODULE_DESCRIPTION(DRV_DESC);
 239 MODULE_AUTHOR("Chelsio Communications");
 240 MODULE_LICENSE("Dual BSD/GPL");
 241 MODULE_VERSION(DRV_VERSION);
 242 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
 243 MODULE_FIRMWARE(FW4_FNAME);
 244 MODULE_FIRMWARE(FW5_FNAME);
 245
 246 /*
 247  * Normally we're willing to become the firmware's Master PF but will be happy
 248  * if another PF has already become the Master and initialized the adapter.
 249  * Setting "force_init" will cause this driver to forcibly establish itself as
 250  * the Master PF and initialize the adapter.
 251  */
 252 static uint force_init;
 253
 254 module_param(force_init, uint, 0644);
 255 MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter");
 256
 257 /*
 258  * Normally if the firmware we connect to has Configuration File support, we
 259  * use that and only fall back to the old Driver-based initialization if the
 260  * Configuration File fails for some reason.  If force_old_init is set, then
 261  * we'll always use the old Driver-based initialization sequence.
 262  */
 263 static uint force_old_init;
 264
 265 module_param(force_old_init, uint, 0644);
 266 MODULE_PARM_DESC(force_old_init, "Force old initialization sequence");
 267
 268 static int dflt_msg_enable = DFLT_MSG_ENABLE;
 269
 270 module_param(dflt_msg_enable, int, 0644);
 271 MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap");
 272
 273 /*
 274  * The driver uses the best interrupt scheme available on a platform in the
 275  * order MSI-X, MSI, legacy INTx interrupts.  This parameter determines which
 276  * of these schemes the driver may consider as follows:
 277  *
 278  * msi = 2: choose from among all three options
 279  * msi = 1: only consider MSI and INTx interrupts
 280  * msi = 0: force INTx interrupts
 281  */
 282 static int msi = 2;
 283
 284 module_param(msi, int, 0644);
 285 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
 286
 287 /*
 288  * Queue interrupt hold-off timer values.  Queues default to the first of these
 289  * upon creation.
 290  */
 291 static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 };
 292
 293 module_param_array(intr_holdoff, uint, NULL, 0644);
 294 MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers "
 295                  "0..4 in microseconds");
 296
 297 static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 };
 298
 299 module_param_array(intr_cnt, uint, NULL, 0644);
 300 MODULE_PARM_DESC(intr_cnt,
 301                  "thresholds 1..3 for queue interrupt packet counters");
 302
 303 /*
 304  * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
 305  * offset by 2 bytes in order to have the IP headers line up on 4-byte
 306  * boundaries.  This is a requirement for many architectures which will throw
 307  * a machine check fault if an attempt is made to access one of the 4-byte IP
 308  * header fields on a non-4-byte boundary.  And it's a major performance issue
 309  * even on some architectures which allow it like some implementations of the
 310  * x86 ISA.  However, some architectures don't mind this and for some very
 311  * edge-case performance sensitive applications (like forwarding large volumes
 312  * of small packets), setting this DMA offset to 0 will decrease the number of
 313  * PCI-E Bus transfers enough to measurably affect performance.
 314  */
 315 static int rx_dma_offset = 2;
 316
 317 static bool vf_acls;
 318
 319 #ifdef CONFIG_PCI_IOV
 320 module_param(vf_acls, bool, 0644);
 321 MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement");
 322
 323 /* Configure the number of PCI-E Virtual Function which are to be instantiated
 324  * on SR-IOV Capable Physical Functions.
 325  */
 326 static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV];
 327
 328 module_param_array(num_vf, uint, NULL, 0644);
 329 MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
 330 #endif
 331
 332 /* TX Queue select used to determine what algorithm to use for selecting TX
 333  * queue. Select between the kernel provided function (select_queue=0) or user
 334  * cxgb_select_queue function (select_queue=1)
 335  *
 336  * Default: select_queue=0
 337  */
 338 static int select_queue;
 339 module_param(select_queue, int, 0644);
 340 MODULE_PARM_DESC(select_queue,
 341                  "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
 342
 343 /*
 344  * The filter TCAM has a fixed portion and a variable portion.  The fixed
 345  * portion can match on source/destination IP IPv4/IPv6 addresses and TCP/UDP
 346  * ports.  The variable portion is 36 bits which can include things like Exact
 347  * Match MAC Index (9 bits), Ether Type (16 bits), IP Protocol (8 bits),
 348  * [Inner] VLAN Tag (17 bits), etc. which, if all were somehow selected, would
 349  * far exceed the 36-bit budget for this "compressed" header portion of the
 350  * filter.  Thus, we have a scarce resource which must be carefully managed.
 351  *
 352  * By default we set this up to mostly match the set of filter matching
 353  * capabilities of T3 but with accommodations for some of T4's more
 354  * interesting features:
 355  *
 356  *   { IP Fragment (1), MPS Match Type (3), IP Protocol (8),
 357  *     [Inner] VLAN (17), Port (3), FCoE (1) }
 358  */
 359 enum {
 360         TP_VLAN_PRI_MAP_DEFAULT = HW_TPL_FR_MT_PR_IV_P_FC,
 361         TP_VLAN_PRI_MAP_FIRST = FCOE_SHIFT,
 362         TP_VLAN_PRI_MAP_LAST = FRAGMENTATION_SHIFT,
 363 };
 364
 365 static unsigned int tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
 366
 367 module_param(tp_vlan_pri_map, uint, 0644);
 368 MODULE_PARM_DESC(tp_vlan_pri_map, "global compressed filter configuration");
 369
 370 static struct dentry *cxgb4_debugfs_root;
 371
 372 static LIST_HEAD(adapter_list);
 373 static DEFINE_MUTEX(uld_mutex);
 374 /* Adapter list to be accessed from atomic context */
 375 static LIST_HEAD(adap_rcu_list);
 376 static DEFINE_SPINLOCK(adap_rcu_lock);
 377 static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
 378 static const char *uld_str[] = { "RDMA", "iSCSI" };
 379
 380 static void link_report(struct net_device *dev)
 381 {
 382         if (!netif_carrier_ok(dev))
 383                 netdev_info(dev, "link down\n");
 384         else {
 385                 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
 386
 387                 const char *s = "10Mbps";
 388                 const struct port_info *p = netdev_priv(dev);
 389
 390                 switch (p->link_cfg.speed) {
 391                 case 10000:
 392                         s = "10Gbps";
 393                         break;
 394                 case 1000:
 395                         s = "1000Mbps";
 396                         break;
 397                 case 100:
 398                         s = "100Mbps";
 399                         break;
 400                 case 40000:
 401                         s = "40Gbps";
 402                         break;
 403                 }
 404
 405                 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
 406                             fc[p->link_cfg.fc]);
 407         }
 408 }
 409
 410 #ifdef CONFIG_CHELSIO_T4_DCB
 411 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
 412 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
 413 {
 414         struct port_info *pi = netdev_priv(dev);
 415         struct adapter *adap = pi->adapter;
 416         struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
 417         int i;
 418
 419         /* We use a simple mapping of Port TX Queue Index to DCB
 420          * Priority when we're enabling DCB.
 421          */
 422         for (i = 0; i < pi->nqsets; i++, txq++) {
 423                 u32 name, value;
 424                 int err;
 425
 426                 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
 427                         FW_PARAMS_PARAM_X_V(
 428                                 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
 429                         FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
 430                 value = enable ? i : 0xffffffff;
 431
 432                 /* Since we can be called while atomic (from "interrupt
 433                  * level") we need to issue the Set Parameters Commannd
 434                  * without sleeping (timeout < 0).
 435                  */
 436                 err = t4_set_params_nosleep(adap, adap->mbox, adap->fn, 0, 1,
 437                                             &name, &value);
 438
 439                 if (err)
 440                         dev_err(adap->pdev_dev,
 441                                 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
 442                                 enable ? "set" : "unset", pi->port_id, i, -err);
 443                 else
 444                         txq->dcb_prio = value;
 445         }
 446 }
 447 #endif /* CONFIG_CHELSIO_T4_DCB */
 448
 449 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
 450 {
 451         struct net_device *dev = adapter->port[port_id];
 452
 453         /* Skip changes from disabled ports. */
 454         if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
 455                 if (link_stat)
 456                         netif_carrier_on(dev);
 457                 else {
 458 #ifdef CONFIG_CHELSIO_T4_DCB
 459                         cxgb4_dcb_state_init(dev);
 460                         dcb_tx_queue_prio_enable(dev, false);
 461 #endif /* CONFIG_CHELSIO_T4_DCB */
 462                         netif_carrier_off(dev);
 463                 }
 464
 465                 link_report(dev);
 466         }
 467 }
 468
 469 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
 470 {
 471         static const char *mod_str[] = {
 472                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
 473         };
 474
 475         const struct net_device *dev = adap->port[port_id];
 476         const struct port_info *pi = netdev_priv(dev);
 477
 478         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
 479                 netdev_info(dev, "port module unplugged\n");
 480         else if (pi->mod_type < ARRAY_SIZE(mod_str))
 481                 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
 482 }
 483
 484 /*
 485  * Configure the exact and hash address filters to handle a port's multicast
 486  * and secondary unicast MAC addresses.
 487  */
 488 static int set_addr_filters(const struct net_device *dev, bool sleep)
 489 {
 490         u64 mhash = 0;
 491         u64 uhash = 0;
 492         bool free = true;
 493         u16 filt_idx[7];
 494         const u8 *addr[7];
 495         int ret, naddr = 0;
 496         const struct netdev_hw_addr *ha;
 497         int uc_cnt = netdev_uc_count(dev);
 498         int mc_cnt = netdev_mc_count(dev);
 499         const struct port_info *pi = netdev_priv(dev);
 500         unsigned int mb = pi->adapter->fn;
 501
 502         /* first do the secondary unicast addresses */
 503         netdev_for_each_uc_addr(ha, dev) {
 504                 addr[naddr++] = ha->addr;
 505                 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
 506                         ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
 507                                         naddr, addr, filt_idx, &uhash, sleep);
 508                         if (ret < 0)
 509                                 return ret;
 510
 511                         free = false;
 512                         naddr = 0;
 513                 }
 514         }
 515
 516         /* next set up the multicast addresses */
 517         netdev_for_each_mc_addr(ha, dev) {
 518                 addr[naddr++] = ha->addr;
 519                 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
 520                         ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
 521                                         naddr, addr, filt_idx, &mhash, sleep);
 522                         if (ret < 0)
 523                                 return ret;
 524
 525                         free = false;
 526                         naddr = 0;
 527                 }
 528         }
 529
 530         return t4_set_addr_hash(pi->adapter, mb, pi->viid, uhash != 0,
 531                                 uhash | mhash, sleep);
 532 }
 533
 534 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
 535 module_param(dbfifo_int_thresh, int, 0644);
 536 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
 537
 538 /*
 539  * usecs to sleep while draining the dbfifo
 540  */
 541 static int dbfifo_drain_delay = 1000;
 542 module_param(dbfifo_drain_delay, int, 0644);
 543 MODULE_PARM_DESC(dbfifo_drain_delay,
 544                  "usecs to sleep while draining the dbfifo");
 545
 546 /*
 547  * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
 548  * If @mtu is -1 it is left unchanged.
 549  */
 550 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
 551 {
 552         int ret;
 553         struct port_info *pi = netdev_priv(dev);
 554
 555         ret = set_addr_filters(dev, sleep_ok);
 556         if (ret == 0)
 557                 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, mtu,
 558                                     (dev->flags & IFF_PROMISC) ? 1 : 0,
 559                                     (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
 560                                     sleep_ok);
 561         return ret;
 562 }
 563
 564 /**
 565  *      link_start - enable a port
 566  *      @dev: the port to enable
 567  *
 568  *      Performs the MAC and PHY actions needed to enable a port.
 569  */
 570 static int link_start(struct net_device *dev)
 571 {
 572         int ret;
 573         struct port_info *pi = netdev_priv(dev);
 574         unsigned int mb = pi->adapter->fn;
 575
 576         /*
 577          * We do not set address filters and promiscuity here, the stack does
 578          * that step explicitly.
 579          */
 580         ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
 581                             !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
 582         if (ret == 0) {
 583                 ret = t4_change_mac(pi->adapter, mb, pi->viid,
 584                                     pi->xact_addr_filt, dev->dev_addr, true,
 585                                     true);
 586                 if (ret >= 0) {
 587                         pi->xact_addr_filt = ret;
 588                         ret = 0;
 589                 }
 590         }
 591         if (ret == 0)
 592                 ret = t4_link_start(pi->adapter, mb, pi->tx_chan,
 593                                     &pi->link_cfg);
 594         if (ret == 0) {
 595                 local_bh_disable();
 596                 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
 597                                           true, CXGB4_DCB_ENABLED);
 598                 local_bh_enable();
 599         }
 600
 601         return ret;
 602 }
 603
 604 int cxgb4_dcb_enabled(const struct net_device *dev)
 605 {
 606 #ifdef CONFIG_CHELSIO_T4_DCB
 607         struct port_info *pi = netdev_priv(dev);
 608
 609         if (!pi->dcb.enabled)
 610                 return 0;
 611
 612         return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
 613                 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
 614 #else
 615         return 0;
 616 #endif
 617 }
 618 EXPORT_SYMBOL(cxgb4_dcb_enabled);
 619
 620 #ifdef CONFIG_CHELSIO_T4_DCB
 621 /* Handle a Data Center Bridging update message from the firmware. */
 622 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
 623 {
 624         int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
 625         struct net_device *dev = adap->port[port];
 626         int old_dcb_enabled = cxgb4_dcb_enabled(dev);
 627         int new_dcb_enabled;
 628
 629         cxgb4_dcb_handle_fw_update(adap, pcmd);
 630         new_dcb_enabled = cxgb4_dcb_enabled(dev);
 631
 632         /* If the DCB has become enabled or disabled on the port then we're
 633          * going to need to set up/tear down DCB Priority parameters for the
 634          * TX Queues associated with the port.
 635          */
 636         if (new_dcb_enabled != old_dcb_enabled)
 637                 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
 638 }
 639 #endif /* CONFIG_CHELSIO_T4_DCB */
 640
 641 /* Clear a filter and release any of its resources that we own.  This also
 642  * clears the filter's "pending" status.
 643  */
 644 static void clear_filter(struct adapter *adap, struct filter_entry *f)
 645 {
 646         /* If the new or old filter have loopback rewriteing rules then we'll
 647          * need to free any existing Layer Two Table (L2T) entries of the old
 648          * filter rule.  The firmware will handle freeing up any Source MAC
 649          * Table (SMT) entries used for rewriting Source MAC Addresses in
 650          * loopback rules.
 651          */
 652         if (f->l2t)
 653                 cxgb4_l2t_release(f->l2t);
 654
 655         /* The zeroing of the filter rule below clears the filter valid,
 656          * pending, locked flags, l2t pointer, etc. so it's all we need for
 657          * this operation.
 658          */
 659         memset(f, 0, sizeof(*f));
 660 }
 661
 662 /* Handle a filter write/deletion reply.
 663  */
 664 static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
 665 {
 666         unsigned int idx = GET_TID(rpl);
 667         unsigned int nidx = idx - adap->tids.ftid_base;
 668         unsigned int ret;
 669         struct filter_entry *f;
 670
 671         if (idx >= adap->tids.ftid_base && nidx <
 672            (adap->tids.nftids + adap->tids.nsftids)) {
 673                 idx = nidx;
 674                 ret = GET_TCB_COOKIE(rpl->cookie);
 675                 f = &adap->tids.ftid_tab[idx];
 676
 677                 if (ret == FW_FILTER_WR_FLT_DELETED) {
 678                         /* Clear the filter when we get confirmation from the
 679                          * hardware that the filter has been deleted.
 680                          */
 681                         clear_filter(adap, f);
 682                 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) {
 683                         dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n",
 684                                 idx);
 685                         clear_filter(adap, f);
 686                 } else if (ret == FW_FILTER_WR_FLT_ADDED) {
 687                         f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff;
 688                         f->pending = 0;  /* asynchronous setup completed */
 689                         f->valid = 1;
 690                 } else {
 691                         /* Something went wrong.  Issue a warning about the
 692                          * problem and clear everything out.
 693                          */
 694                         dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n",
 695                                 idx, ret);
 696                         clear_filter(adap, f);
 697                 }
 698         }
 699 }
 700
 701 /* Response queue handler for the FW event queue.
 702  */
 703 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
 704                           const struct pkt_gl *gl)
 705 {
 706         u8 opcode = ((const struct rss_header *)rsp)->opcode;
 707
 708         rsp++;                                          /* skip RSS header */
 709
 710         /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
 711          */
 712         if (unlikely(opcode == CPL_FW4_MSG &&
 713            ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
 714                 rsp++;
 715                 opcode = ((const struct rss_header *)rsp)->opcode;
 716                 rsp++;
 717                 if (opcode != CPL_SGE_EGR_UPDATE) {
 718                         dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
 719                                 , opcode);
 720                         goto out;
 721                 }
 722         }
 723
 724         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
 725                 const struct cpl_sge_egr_update *p = (void *)rsp;
 726                 unsigned int qid = EGR_QID(ntohl(p->opcode_qid));
 727                 struct sge_txq *txq;
 728
 729                 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
 730                 txq->restarts++;
 731                 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) {
 732                         struct sge_eth_txq *eq;
 733
 734                         eq = container_of(txq, struct sge_eth_txq, q);
 735                         netif_tx_wake_queue(eq->txq);
 736                 } else {
 737                         struct sge_ofld_txq *oq;
 738
 739                         oq = container_of(txq, struct sge_ofld_txq, q);
 740                         tasklet_schedule(&oq->qresume_tsk);
 741                 }
 742         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
 743                 const struct cpl_fw6_msg *p = (void *)rsp;
 744
 745 #ifdef CONFIG_CHELSIO_T4_DCB
 746                 const struct fw_port_cmd *pcmd = (const void *)p->data;
 747                 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
 748                 unsigned int action =
 749                         FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
 750
 751                 if (cmd == FW_PORT_CMD &&
 752                     action == FW_PORT_ACTION_GET_PORT_INFO) {
 753                         int port = FW_PORT_CMD_PORTID_G(
 754                                         be32_to_cpu(pcmd->op_to_portid));
 755                         struct net_device *dev = q->adap->port[port];
 756                         int state_input = ((pcmd->u.info.dcbxdis_pkd &
 757                                             FW_PORT_CMD_DCBXDIS_F)
 758                                            ? CXGB4_DCB_INPUT_FW_DISABLED
 759                                            : CXGB4_DCB_INPUT_FW_ENABLED);
 760
 761                         cxgb4_dcb_state_fsm(dev, state_input);
 762                 }
 763
 764                 if (cmd == FW_PORT_CMD &&
 765                     action == FW_PORT_ACTION_L2_DCB_CFG)
 766                         dcb_rpl(q->adap, pcmd);
 767                 else
 768 #endif
 769                         if (p->type == 0)
 770                                 t4_handle_fw_rpl(q->adap, p->data);
 771         } else if (opcode == CPL_L2T_WRITE_RPL) {
 772                 const struct cpl_l2t_write_rpl *p = (void *)rsp;
 773
 774                 do_l2t_write_rpl(q->adap, p);
 775         } else if (opcode == CPL_SET_TCB_RPL) {
 776                 const struct cpl_set_tcb_rpl *p = (void *)rsp;
 777
 778                 filter_rpl(q->adap, p);
 779         } else
 780                 dev_err(q->adap->pdev_dev,
 781                         "unexpected CPL %#x on FW event queue\n", opcode);
 782 out:
 783         return 0;
 784 }
 785
 786 /**
 787  *      uldrx_handler - response queue handler for ULD queues
 788  *      @q: the response queue that received the packet
 789  *      @rsp: the response queue descriptor holding the offload message
 790  *      @gl: the gather list of packet fragments
 791  *
 792  *      Deliver an ingress offload packet to a ULD.  All processing is done by
 793  *      the ULD, we just maintain statistics.
 794  */
 795 static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
 796                          const struct pkt_gl *gl)
 797 {
 798         struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
 799
 800         /* FW can send CPLs encapsulated in a CPL_FW4_MSG.
 801          */
 802         if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG &&
 803             ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL)
 804                 rsp += 2;
 805
 806         if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) {
 807                 rxq->stats.nomem++;
 808                 return -1;
 809         }
 810         if (gl == NULL)
 811                 rxq->stats.imm++;
 812         else if (gl == CXGB4_MSG_AN)
 813                 rxq->stats.an++;
 814         else
 815                 rxq->stats.pkts++;
 816         return 0;
 817 }
 818
 819 static void disable_msi(struct adapter *adapter)
 820 {
 821         if (adapter->flags & USING_MSIX) {
 822                 pci_disable_msix(adapter->pdev);
 823                 adapter->flags &= ~USING_MSIX;
 824         } else if (adapter->flags & USING_MSI) {
 825                 pci_disable_msi(adapter->pdev);
 826                 adapter->flags &= ~USING_MSI;
 827         }
 828 }
 829
 830 /*
 831  * Interrupt handler for non-data events used with MSI-X.
 832  */
 833 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
 834 {
 835         struct adapter *adap = cookie;
 836
 837         u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE));
 838         if (v & PFSW) {
 839                 adap->swintr = 1;
 840                 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE), v);
 841         }
 842         t4_slow_intr_handler(adap);
 843         return IRQ_HANDLED;
 844 }
 845
 846 /*
 847  * Name the MSI-X interrupts.
 848  */
 849 static void name_msix_vecs(struct adapter *adap)
 850 {
 851         int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
 852
 853         /* non-data interrupts */
 854         snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
 855
 856         /* FW events */
 857         snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
 858                  adap->port[0]->name);
 859
 860         /* Ethernet queues */
 861         for_each_port(adap, j) {
 862                 struct net_device *d = adap->port[j];
 863                 const struct port_info *pi = netdev_priv(d);
 864
 865                 for (i = 0; i < pi->nqsets; i++, msi_idx++)
 866                         snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
 867                                  d->name, i);
 868         }
 869
 870         /* offload queues */
 871         for_each_ofldrxq(&adap->sge, i)
 872                 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-ofld%d",
 873                          adap->port[0]->name, i);
 874
 875         for_each_rdmarxq(&adap->sge, i)
 876                 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d",
 877                          adap->port[0]->name, i);
 878
 879         for_each_rdmaciq(&adap->sge, i)
 880                 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d",
 881                          adap->port[0]->name, i);
 882 }
 883
 884 static int request_msix_queue_irqs(struct adapter *adap)
 885 {
 886         struct sge *s = &adap->sge;
 887         int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0;
 888         int msi_index = 2;
 889
 890         err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
 891                           adap->msix_info[1].desc, &s->fw_evtq);
 892         if (err)
 893                 return err;
 894
 895         for_each_ethrxq(s, ethqidx) {
 896                 err = request_irq(adap->msix_info[msi_index].vec,
 897                                   t4_sge_intr_msix, 0,
 898                                   adap->msix_info[msi_index].desc,
 899                                   &s->ethrxq[ethqidx].rspq);
 900                 if (err)
 901                         goto unwind;
 902                 msi_index++;
 903         }
 904         for_each_ofldrxq(s, ofldqidx) {
 905                 err = request_irq(adap->msix_info[msi_index].vec,
 906                                   t4_sge_intr_msix, 0,
 907                                   adap->msix_info[msi_index].desc,
 908                                   &s->ofldrxq[ofldqidx].rspq);
 909                 if (err)
 910                         goto unwind;
 911                 msi_index++;
 912         }
 913         for_each_rdmarxq(s, rdmaqidx) {
 914                 err = request_irq(adap->msix_info[msi_index].vec,
 915                                   t4_sge_intr_msix, 0,
 916                                   adap->msix_info[msi_index].desc,
 917                                   &s->rdmarxq[rdmaqidx].rspq);
 918                 if (err)
 919                         goto unwind;
 920                 msi_index++;
 921         }
 922         for_each_rdmaciq(s, rdmaciqqidx) {
 923                 err = request_irq(adap->msix_info[msi_index].vec,
 924                                   t4_sge_intr_msix, 0,
 925                                   adap->msix_info[msi_index].desc,
 926                                   &s->rdmaciq[rdmaciqqidx].rspq);
 927                 if (err)
 928                         goto unwind;
 929                 msi_index++;
 930         }
 931         return 0;
 932
 933 unwind:
 934         while (--rdmaciqqidx >= 0)
 935                 free_irq(adap->msix_info[--msi_index].vec,
 936                          &s->rdmaciq[rdmaciqqidx].rspq);
 937         while (--rdmaqidx >= 0)
 938                 free_irq(adap->msix_info[--msi_index].vec,
 939                          &s->rdmarxq[rdmaqidx].rspq);
 940         while (--ofldqidx >= 0)
 941                 free_irq(adap->msix_info[--msi_index].vec,
 942                          &s->ofldrxq[ofldqidx].rspq);
 943         while (--ethqidx >= 0)
 944                 free_irq(adap->msix_info[--msi_index].vec,
 945                          &s->ethrxq[ethqidx].rspq);
 946         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
 947         return err;
 948 }
 949
 950 static void free_msix_queue_irqs(struct adapter *adap)
 951 {
 952         int i, msi_index = 2;
 953         struct sge *s = &adap->sge;
 954
 955         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
 956         for_each_ethrxq(s, i)
 957                 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
 958         for_each_ofldrxq(s, i)
 959                 free_irq(adap->msix_info[msi_index++].vec, &s->ofldrxq[i].rspq);
 960         for_each_rdmarxq(s, i)
 961                 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq);
 962         for_each_rdmaciq(s, i)
 963                 free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq);
 964 }
 965
 966 /**
 967  *      write_rss - write the RSS table for a given port
 968  *      @pi: the port
 969  *      @queues: array of queue indices for RSS
 970  *
 971  *      Sets up the portion of the HW RSS table for the port's VI to distribute
 972  *      packets to the Rx queues in @queues.
 973  */
 974 static int write_rss(const struct port_info *pi, const u16 *queues)
 975 {
 976         u16 *rss;
 977         int i, err;
 978         const struct sge_eth_rxq *q = &pi->adapter->sge.ethrxq[pi->first_qset];
 979
 980         rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
 981         if (!rss)
 982                 return -ENOMEM;
 983
 984         /* map the queue indices to queue ids */
 985         for (i = 0; i < pi->rss_size; i++, queues++)
 986                 rss[i] = q[*queues].rspq.abs_id;
 987
 988         err = t4_config_rss_range(pi->adapter, pi->adapter->fn, pi->viid, 0,
 989                                   pi->rss_size, rss, pi->rss_size);
 990         kfree(rss);
 991         return err;
 992 }
 993
 994 /**
 995  *      setup_rss - configure RSS
 996  *      @adap: the adapter
 997  *
 998  *      Sets up RSS for each port.
 999  */
1000 static int setup_rss(struct adapter *adap)
1001 {
1002         int i, err;
1003
1004         for_each_port(adap, i) {
1005                 const struct port_info *pi = adap2pinfo(adap, i);
1006
1007                 err = write_rss(pi, pi->rss);
1008                 if (err)
1009                         return err;
1010         }
1011         return 0;
1012 }
1013
1014 /*
1015  * Return the channel of the ingress queue with the given qid.
1016  */
1017 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
1018 {
1019         qid -= p->ingr_start;
1020         return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
1021 }
1022
1023 /*
1024  * Wait until all NAPI handlers are descheduled.
1025  */
1026 static void quiesce_rx(struct adapter *adap)
1027 {
1028         int i;
1029
1030         for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
1031                 struct sge_rspq *q = adap->sge.ingr_map[i];
1032
1033                 if (q && q->handler)
1034                         napi_disable(&q->napi);
1035         }
1036 }
1037
1038 /*
1039  * Enable NAPI scheduling and interrupt generation for all Rx queues.
1040  */
1041 static void enable_rx(struct adapter *adap)
1042 {
1043         int i;
1044
1045         for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
1046                 struct sge_rspq *q = adap->sge.ingr_map[i];
1047
1048                 if (!q)
1049                         continue;
1050                 if (q->handler)
1051                         napi_enable(&q->napi);
1052                 /* 0-increment GTS to start the timer and enable interrupts */
1053                 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS),
1054                              SEINTARM(q->intr_params) |
1055                              INGRESSQID(q->cntxt_id));
1056         }
1057 }
1058
1059 /**
1060  *      setup_sge_queues - configure SGE Tx/Rx/response queues
1061  *      @adap: the adapter
1062  *
1063  *      Determines how many sets of SGE queues to use and initializes them.
1064  *      We support multiple queue sets per port if we have MSI-X, otherwise
1065  *      just one queue set per port.
1066  */
1067 static int setup_sge_queues(struct adapter *adap)
1068 {
1069         int err, msi_idx, i, j;
1070         struct sge *s = &adap->sge;
1071
1072         bitmap_zero(s->starving_fl, MAX_EGRQ);
1073         bitmap_zero(s->txq_maperr, MAX_EGRQ);
1074
1075         if (adap->flags & USING_MSIX)
1076                 msi_idx = 1;         /* vector 0 is for non-queue interrupts */
1077         else {
1078                 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
1079                                        NULL, NULL);
1080                 if (err)
1081                         return err;
1082                 msi_idx = -((int)s->intrq.abs_id + 1);
1083         }
1084
1085         err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
1086                                msi_idx, NULL, fwevtq_handler);
1087         if (err) {
1088 freeout:        t4_free_sge_resources(adap);
1089                 return err;
1090         }
1091
1092         for_each_port(adap, i) {
1093                 struct net_device *dev = adap->port[i];
1094                 struct port_info *pi = netdev_priv(dev);
1095                 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1096                 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1097
1098                 for (j = 0; j < pi->nqsets; j++, q++) {
1099                         if (msi_idx > 0)
1100                                 msi_idx++;
1101                         err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1102                                                msi_idx, &q->fl,
1103                                                t4_ethrx_handler);
1104                         if (err)
1105                                 goto freeout;
1106                         q->rspq.idx = j;
1107                         memset(&q->stats, 0, sizeof(q->stats));
1108                 }
1109                 for (j = 0; j < pi->nqsets; j++, t++) {
1110                         err = t4_sge_alloc_eth_txq(adap, t, dev,
1111                                         netdev_get_tx_queue(dev, j),
1112                                         s->fw_evtq.cntxt_id);
1113                         if (err)
1114                                 goto freeout;
1115                 }
1116         }
1117
1118         j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */
1119         for_each_ofldrxq(s, i) {
1120                 struct sge_ofld_rxq *q = &s->ofldrxq[i];
1121                 struct net_device *dev = adap->port[i / j];
1122
1123                 if (msi_idx > 0)
1124                         msi_idx++;
1125                 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, msi_idx,
1126                                        q->fl.size ? &q->fl : NULL,
1127                                        uldrx_handler);
1128                 if (err)
1129                         goto freeout;
1130                 memset(&q->stats, 0, sizeof(q->stats));
1131                 s->ofld_rxq[i] = q->rspq.abs_id;
1132                 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i], dev,
1133                                             s->fw_evtq.cntxt_id);
1134                 if (err)
1135                         goto freeout;
1136         }
1137
1138         for_each_rdmarxq(s, i) {
1139                 struct sge_ofld_rxq *q = &s->rdmarxq[i];
1140
1141                 if (msi_idx > 0)
1142                         msi_idx++;
1143                 err = t4_sge_alloc_rxq(adap, &q->rspq, false, adap->port[i],
1144                                        msi_idx, q->fl.size ? &q->fl : NULL,
1145                                        uldrx_handler);
1146                 if (err)
1147                         goto freeout;
1148                 memset(&q->stats, 0, sizeof(q->stats));
1149                 s->rdma_rxq[i] = q->rspq.abs_id;
1150         }
1151
1152         for_each_rdmaciq(s, i) {
1153                 struct sge_ofld_rxq *q = &s->rdmaciq[i];
1154
1155                 if (msi_idx > 0)
1156                         msi_idx++;
1157                 err = t4_sge_alloc_rxq(adap, &q->rspq, false, adap->port[i],
1158                                        msi_idx, q->fl.size ? &q->fl : NULL,
1159                                        uldrx_handler);
1160                 if (err)
1161                         goto freeout;
1162                 memset(&q->stats, 0, sizeof(q->stats));
1163                 s->rdma_ciq[i] = q->rspq.abs_id;
1164         }
1165
1166         for_each_port(adap, i) {
1167                 /*
1168                  * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
1169                  * have RDMA queues, and that's the right value.
1170                  */
1171                 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1172                                             s->fw_evtq.cntxt_id,
1173                                             s->rdmarxq[i].rspq.cntxt_id);
1174                 if (err)
1175                         goto freeout;
1176         }
1177
1178         t4_write_reg(adap, is_t4(adap->params.chip) ?
1179                                 MPS_TRC_RSS_CONTROL :
1180                                 MPS_T5_TRC_RSS_CONTROL,
1181                      RSSCONTROL(netdev2pinfo(adap->port[0])->tx_chan) |
1182                      QUEUENUMBER(s->ethrxq[0].rspq.abs_id));
1183         return 0;
1184 }
1185
1186 /*
1187  * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
1188  * The allocated memory is cleared.
1189  */
1190 void *t4_alloc_mem(size_t size)
1191 {
1192         void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
1193
1194         if (!p)
1195                 p = vzalloc(size);
1196         return p;
1197 }
1198
1199 /*
1200  * Free memory allocated through alloc_mem().
1201  */
1202 void t4_free_mem(void *addr)
1203 {
1204         if (is_vmalloc_addr(addr))
1205                 vfree(addr);
1206         else
1207                 kfree(addr);
1208 }
1209
1210 /* Send a Work Request to write the filter at a specified index.  We construct
1211  * a Firmware Filter Work Request to have the work done and put the indicated
1212  * filter into "pending" mode which will prevent any further actions against
1213  * it till we get a reply from the firmware on the completion status of the
1214  * request.
1215  */
1216 static int set_filter_wr(struct adapter *adapter, int fidx)
1217 {
1218         struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1219         struct sk_buff *skb;
1220         struct fw_filter_wr *fwr;
1221         unsigned int ftid;
1222
1223         /* If the new filter requires loopback Destination MAC and/or VLAN
1224          * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
1225          * the filter.
1226          */
1227         if (f->fs.newdmac || f->fs.newvlan) {
1228                 /* allocate L2T entry for new filter */
1229                 f->l2t = t4_l2t_alloc_switching(adapter->l2t);
1230                 if (f->l2t == NULL)
1231                         return -EAGAIN;
1232                 if (t4_l2t_set_switching(adapter, f->l2t, f->fs.vlan,
1233                                         f->fs.eport, f->fs.dmac)) {
1234                         cxgb4_l2t_release(f->l2t);
1235                         f->l2t = NULL;
1236                         return -ENOMEM;
1237                 }
1238         }
1239
1240         ftid = adapter->tids.ftid_base + fidx;
1241
1242         skb = alloc_skb(sizeof(*fwr), GFP_KERNEL | __GFP_NOFAIL);
1243         fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr));
1244         memset(fwr, 0, sizeof(*fwr));
1245
1246         /* It would be nice to put most of the following in t4_hw.c but most
1247          * of the work is translating the cxgbtool ch_filter_specification
1248          * into the Work Request and the definition of that structure is
1249          * currently in cxgbtool.h which isn't appropriate to pull into the
1250          * common code.  We may eventually try to come up with a more neutral
1251          * filter specification structure but for now it's easiest to simply
1252          * put this fairly direct code in line ...
1253          */
1254         fwr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR));
1255         fwr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*fwr)/16));
1256         fwr->tid_to_iq =
1257                 htonl(FW_FILTER_WR_TID_V(ftid) |
1258                       FW_FILTER_WR_RQTYPE_V(f->fs.type) |
1259                       FW_FILTER_WR_NOREPLY_V(0) |
1260                       FW_FILTER_WR_IQ_V(f->fs.iq));
1261         fwr->del_filter_to_l2tix =
1262                 htonl(FW_FILTER_WR_RPTTID_V(f->fs.rpttid) |
1263                       FW_FILTER_WR_DROP_V(f->fs.action == FILTER_DROP) |
1264                       FW_FILTER_WR_DIRSTEER_V(f->fs.dirsteer) |
1265                       FW_FILTER_WR_MASKHASH_V(f->fs.maskhash) |
1266                       FW_FILTER_WR_DIRSTEERHASH_V(f->fs.dirsteerhash) |
1267                       FW_FILTER_WR_LPBK_V(f->fs.action == FILTER_SWITCH) |
1268                       FW_FILTER_WR_DMAC_V(f->fs.newdmac) |
1269                       FW_FILTER_WR_SMAC_V(f->fs.newsmac) |
1270                       FW_FILTER_WR_INSVLAN_V(f->fs.newvlan == VLAN_INSERT ||
1271                                              f->fs.newvlan == VLAN_REWRITE) |
1272                       FW_FILTER_WR_RMVLAN_V(f->fs.newvlan == VLAN_REMOVE ||
1273                                             f->fs.newvlan == VLAN_REWRITE) |
1274                       FW_FILTER_WR_HITCNTS_V(f->fs.hitcnts) |
1275                       FW_FILTER_WR_TXCHAN_V(f->fs.eport) |
1276                       FW_FILTER_WR_PRIO_V(f->fs.prio) |
1277                       FW_FILTER_WR_L2TIX_V(f->l2t ? f->l2t->idx : 0));
1278         fwr->ethtype = htons(f->fs.val.ethtype);
1279         fwr->ethtypem = htons(f->fs.mask.ethtype);
1280         fwr->frag_to_ovlan_vldm =
1281                 (FW_FILTER_WR_FRAG_V(f->fs.val.frag) |
1282                  FW_FILTER_WR_FRAGM_V(f->fs.mask.frag) |
1283                  FW_FILTER_WR_IVLAN_VLD_V(f->fs.val.ivlan_vld) |
1284                  FW_FILTER_WR_OVLAN_VLD_V(f->fs.val.ovlan_vld) |
1285                  FW_FILTER_WR_IVLAN_VLDM_V(f->fs.mask.ivlan_vld) |
1286                  FW_FILTER_WR_OVLAN_VLDM_V(f->fs.mask.ovlan_vld));
1287         fwr->smac_sel = 0;
1288         fwr->rx_chan_rx_rpl_iq =
1289                 htons(FW_FILTER_WR_RX_CHAN_V(0) |
1290                       FW_FILTER_WR_RX_RPL_IQ_V(adapter->sge.fw_evtq.abs_id));
1291         fwr->maci_to_matchtypem =
1292                 htonl(FW_FILTER_WR_MACI_V(f->fs.val.macidx) |
1293                       FW_FILTER_WR_MACIM_V(f->fs.mask.macidx) |
1294                       FW_FILTER_WR_FCOE_V(f->fs.val.fcoe) |
1295                       FW_FILTER_WR_FCOEM_V(f->fs.mask.fcoe) |
1296                       FW_FILTER_WR_PORT_V(f->fs.val.iport) |
1297                       FW_FILTER_WR_PORTM_V(f->fs.mask.iport) |
1298                       FW_FILTER_WR_MATCHTYPE_V(f->fs.val.matchtype) |
1299                       FW_FILTER_WR_MATCHTYPEM_V(f->fs.mask.matchtype));
1300         fwr->ptcl = f->fs.val.proto;
1301         fwr->ptclm = f->fs.mask.proto;
1302         fwr->ttyp = f->fs.val.tos;
1303         fwr->ttypm = f->fs.mask.tos;
1304         fwr->ivlan = htons(f->fs.val.ivlan);
1305         fwr->ivlanm = htons(f->fs.mask.ivlan);
1306         fwr->ovlan = htons(f->fs.val.ovlan);
1307         fwr->ovlanm = htons(f->fs.mask.ovlan);
1308         memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
1309         memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
1310         memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
1311         memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
1312         fwr->lp = htons(f->fs.val.lport);
1313         fwr->lpm = htons(f->fs.mask.lport);
1314         fwr->fp = htons(f->fs.val.fport);
1315         fwr->fpm = htons(f->fs.mask.fport);
1316         if (f->fs.newsmac)
1317                 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma));
1318
1319         /* Mark the filter as "pending" and ship off the Filter Work Request.
1320          * When we get the Work Request Reply we'll clear the pending status.
1321          */
1322         f->pending = 1;
1323         set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3);
1324         t4_ofld_send(adapter, skb);
1325         return 0;
1326 }
1327
1328 /* Delete the filter at a specified index.
1329  */
1330 static int del_filter_wr(struct adapter *adapter, int fidx)
1331 {
1332         struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1333         struct sk_buff *skb;
1334         struct fw_filter_wr *fwr;
1335         unsigned int len, ftid;
1336
1337         len = sizeof(*fwr);
1338         ftid = adapter->tids.ftid_base + fidx;
1339
1340         skb = alloc_skb(len, GFP_KERNEL | __GFP_NOFAIL);
1341         fwr = (struct fw_filter_wr *)__skb_put(skb, len);
1342         t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id);
1343
1344         /* Mark the filter as "pending" and ship off the Filter Work Request.
1345          * When we get the Work Request Reply we'll clear the pending status.
1346          */
1347         f->pending = 1;
1348         t4_mgmt_tx(adapter, skb);
1349         return 0;
1350 }
1351
1352 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1353                              void *accel_priv, select_queue_fallback_t fallback)
1354 {
1355         int txq;
1356
1357 #ifdef CONFIG_CHELSIO_T4_DCB
1358         /* If a Data Center Bridging has been successfully negotiated on this
1359          * link then we'll use the skb's priority to map it to a TX Queue.
1360          * The skb's priority is determined via the VLAN Tag Priority Code
1361          * Point field.
1362          */
1363         if (cxgb4_dcb_enabled(dev)) {
1364                 u16 vlan_tci;
1365                 int err;
1366
1367                 err = vlan_get_tag(skb, &vlan_tci);
1368                 if (unlikely(err)) {
1369                         if (net_ratelimit())
1370                                 netdev_warn(dev,
1371                                             "TX Packet without VLAN Tag on DCB Link\n");
1372                         txq = 0;
1373                 } else {
1374                         txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1375                 }
1376                 return txq;
1377         }
1378 #endif /* CONFIG_CHELSIO_T4_DCB */
1379
1380         if (select_queue) {
1381                 txq = (skb_rx_queue_recorded(skb)
1382                         ? skb_get_rx_queue(skb)
1383                         : smp_processor_id());
1384
1385                 while (unlikely(txq >= dev->real_num_tx_queues))
1386                         txq -= dev->real_num_tx_queues;
1387
1388                 return txq;
1389         }
1390
1391         return fallback(dev, skb) % dev->real_num_tx_queues;
1392 }
1393
1394 static inline int is_offload(const struct adapter *adap)
1395 {
1396         return adap->params.offload;
1397 }
1398
1399 /*
1400  * Implementation of ethtool operations.
1401  */
1402
1403 static u32 get_msglevel(struct net_device *dev)
1404 {
1405         return netdev2adap(dev)->msg_enable;
1406 }
1407
1408 static void set_msglevel(struct net_device *dev, u32 val)
1409 {
1410         netdev2adap(dev)->msg_enable = val;
1411 }
1412
1413 static char stats_strings[][ETH_GSTRING_LEN] = {
1414         "TxOctetsOK         ",
1415         "TxFramesOK         ",
1416         "TxBroadcastFrames  ",
1417         "TxMulticastFrames  ",
1418         "TxUnicastFrames    ",
1419         "TxErrorFrames      ",
1420
1421         "TxFrames64         ",
1422         "TxFrames65To127    ",
1423         "TxFrames128To255   ",
1424         "TxFrames256To511   ",
1425         "TxFrames512To1023  ",
1426         "TxFrames1024To1518 ",
1427         "TxFrames1519ToMax  ",
1428
1429         "TxFramesDropped    ",
1430         "TxPauseFrames      ",
1431         "TxPPP0Frames       ",
1432         "TxPPP1Frames       ",
1433         "TxPPP2Frames       ",
1434         "TxPPP3Frames       ",
1435         "TxPPP4Frames       ",
1436         "TxPPP5Frames       ",
1437         "TxPPP6Frames       ",
1438         "TxPPP7Frames       ",
1439
1440         "RxOctetsOK         ",
1441         "RxFramesOK         ",
1442         "RxBroadcastFrames  ",
1443         "RxMulticastFrames  ",
1444         "RxUnicastFrames    ",
1445
1446         "RxFramesTooLong    ",
1447         "RxJabberErrors     ",
1448         "RxFCSErrors        ",
1449         "RxLengthErrors     ",
1450         "RxSymbolErrors     ",
1451         "RxRuntFrames       ",
1452
1453         "RxFrames64         ",
1454         "RxFrames65To127    ",
1455         "RxFrames128To255   ",
1456         "RxFrames256To511   ",
1457         "RxFrames512To1023  ",
1458         "RxFrames1024To1518 ",
1459         "RxFrames1519ToMax  ",
1460
1461         "RxPauseFrames      ",
1462         "RxPPP0Frames       ",
1463         "RxPPP1Frames       ",
1464         "RxPPP2Frames       ",
1465         "RxPPP3Frames       ",
1466         "RxPPP4Frames       ",
1467         "RxPPP5Frames       ",
1468         "RxPPP6Frames       ",
1469         "RxPPP7Frames       ",
1470
1471         "RxBG0FramesDropped ",
1472         "RxBG1FramesDropped ",
1473         "RxBG2FramesDropped ",
1474         "RxBG3FramesDropped ",
1475         "RxBG0FramesTrunc   ",
1476         "RxBG1FramesTrunc   ",
1477         "RxBG2FramesTrunc   ",
1478         "RxBG3FramesTrunc   ",
1479
1480         "TSO                ",
1481         "TxCsumOffload      ",
1482         "RxCsumGood         ",
1483         "VLANextractions    ",
1484         "VLANinsertions     ",
1485         "GROpackets         ",
1486         "GROmerged          ",
1487         "WriteCoalSuccess   ",
1488         "WriteCoalFail      ",
1489 };
1490
1491 static int get_sset_count(struct net_device *dev, int sset)
1492 {
1493         switch (sset) {
1494         case ETH_SS_STATS:
1495                 return ARRAY_SIZE(stats_strings);
1496         default:
1497                 return -EOPNOTSUPP;
1498         }
1499 }
1500
1501 #define T4_REGMAP_SIZE (160 * 1024)
1502 #define T5_REGMAP_SIZE (332 * 1024)
1503
1504 static int get_regs_len(struct net_device *dev)
1505 {
1506         struct adapter *adap = netdev2adap(dev);
1507         if (is_t4(adap->params.chip))
1508                 return T4_REGMAP_SIZE;
1509         else
1510                 return T5_REGMAP_SIZE;
1511 }
1512
1513 static int get_eeprom_len(struct net_device *dev)
1514 {
1515         return EEPROMSIZE;
1516 }
1517
1518 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1519 {
1520         struct adapter *adapter = netdev2adap(dev);
1521
1522         strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1523         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1524         strlcpy(info->bus_info, pci_name(adapter->pdev),
1525                 sizeof(info->bus_info));
1526
1527         if (adapter->params.fw_vers)
1528                 snprintf(info->fw_version, sizeof(info->fw_version),
1529                         "%u.%u.%u.%u, TP %u.%u.%u.%u",
1530                         FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
1531                         FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
1532                         FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
1533                         FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers),
1534                         FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
1535                         FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
1536                         FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
1537                         FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
1538 }
1539
1540 static void get_strings(struct net_device *dev, u32 stringset, u8 *data)
1541 {
1542         if (stringset == ETH_SS_STATS)
1543                 memcpy(data, stats_strings, sizeof(stats_strings));
1544 }
1545
1546 /*
1547  * port stats maintained per queue of the port.  They should be in the same
1548  * order as in stats_strings above.
1549  */
1550 struct queue_port_stats {
1551         u64 tso;
1552         u64 tx_csum;
1553         u64 rx_csum;
1554         u64 vlan_ex;
1555         u64 vlan_ins;
1556         u64 gro_pkts;
1557         u64 gro_merged;
1558 };
1559
1560 static void collect_sge_port_stats(const struct adapter *adap,
1561                 const struct port_info *p, struct queue_port_stats *s)
1562 {
1563         int i;
1564         const struct sge_eth_txq *tx = &adap->sge.ethtxq[p->first_qset];
1565         const struct sge_eth_rxq *rx = &adap->sge.ethrxq[p->first_qset];
1566
1567         memset(s, 0, sizeof(*s));
1568         for (i = 0; i < p->nqsets; i++, rx++, tx++) {
1569                 s->tso += tx->tso;
1570                 s->tx_csum += tx->tx_cso;
1571                 s->rx_csum += rx->stats.rx_cso;
1572                 s->vlan_ex += rx->stats.vlan_ex;
1573                 s->vlan_ins += tx->vlan_ins;
1574                 s->gro_pkts += rx->stats.lro_pkts;
1575                 s->gro_merged += rx->stats.lro_merged;
1576         }
1577 }
1578
1579 static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1580                       u64 *data)
1581 {
1582         struct port_info *pi = netdev_priv(dev);
1583         struct adapter *adapter = pi->adapter;
1584         u32 val1, val2;
1585
1586         t4_get_port_stats(adapter, pi->tx_chan, (struct port_stats *)data);
1587
1588         data += sizeof(struct port_stats) / sizeof(u64);
1589         collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data);
1590         data += sizeof(struct queue_port_stats) / sizeof(u64);
1591         if (!is_t4(adapter->params.chip)) {
1592                 t4_write_reg(adapter, SGE_STAT_CFG, STATSOURCE_T5(7));
1593                 val1 = t4_read_reg(adapter, SGE_STAT_TOTAL);
1594                 val2 = t4_read_reg(adapter, SGE_STAT_MATCH);
1595                 *data = val1 - val2;
1596                 data++;
1597                 *data = val2;
1598                 data++;
1599         } else {
1600                 memset(data, 0, 2 * sizeof(u64));
1601                 *data += 2;
1602         }
1603 }
1604
1605 /*
1606  * Return a version number to identify the type of adapter.  The scheme is:
1607  * - bits 0..9: chip version
1608  * - bits 10..15: chip revision
1609  * - bits 16..23: register dump version
1610  */
1611 static inline unsigned int mk_adap_vers(const struct adapter *ap)
1612 {
1613         return CHELSIO_CHIP_VERSION(ap->params.chip) |
1614                 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1615 }
1616
1617 static void reg_block_dump(struct adapter *ap, void *buf, unsigned int start,
1618                            unsigned int end)
1619 {
1620         u32 *p = buf + start;
1621
1622         for ( ; start <= end; start += sizeof(u32))
1623                 *p++ = t4_read_reg(ap, start);
1624 }
1625
1626 static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
1627                      void *buf)
1628 {
1629         static const unsigned int t4_reg_ranges[] = {
1630                 0x1008, 0x1108,
1631                 0x1180, 0x11b4,
1632                 0x11fc, 0x123c,
1633                 0x1300, 0x173c,
1634                 0x1800, 0x18fc,
1635                 0x3000, 0x30d8,
1636                 0x30e0, 0x5924,
1637                 0x5960, 0x59d4,
1638                 0x5a00, 0x5af8,
1639                 0x6000, 0x6098,
1640                 0x6100, 0x6150,
1641                 0x6200, 0x6208,
1642                 0x6240, 0x6248,
1643                 0x6280, 0x6338,
1644                 0x6370, 0x638c,
1645                 0x6400, 0x643c,
1646                 0x6500, 0x6524,
1647                 0x6a00, 0x6a38,
1648                 0x6a60, 0x6a78,
1649                 0x6b00, 0x6b84,
1650                 0x6bf0, 0x6c84,
1651                 0x6cf0, 0x6d84,
1652                 0x6df0, 0x6e84,
1653                 0x6ef0, 0x6f84,
1654                 0x6ff0, 0x7084,
1655                 0x70f0, 0x7184,
1656                 0x71f0, 0x7284,
1657                 0x72f0, 0x7384,
1658                 0x73f0, 0x7450,
1659                 0x7500, 0x7530,
1660                 0x7600, 0x761c,
1661                 0x7680, 0x76cc,
1662                 0x7700, 0x7798,
1663                 0x77c0, 0x77fc,
1664                 0x7900, 0x79fc,
1665                 0x7b00, 0x7c38,
1666                 0x7d00, 0x7efc,
1667                 0x8dc0, 0x8e1c,
1668                 0x8e30, 0x8e78,
1669                 0x8ea0, 0x8f6c,
1670                 0x8fc0, 0x9074,
1671                 0x90fc, 0x90fc,
1672                 0x9400, 0x9458,
1673                 0x9600, 0x96bc,
1674                 0x9800, 0x9808,
1675                 0x9820, 0x983c,
1676                 0x9850, 0x9864,
1677                 0x9c00, 0x9c6c,
1678                 0x9c80, 0x9cec,
1679                 0x9d00, 0x9d6c,
1680                 0x9d80, 0x9dec,
1681                 0x9e00, 0x9e6c,
1682                 0x9e80, 0x9eec,
1683                 0x9f00, 0x9f6c,
1684                 0x9f80, 0x9fec,
1685                 0xd004, 0xd03c,
1686                 0xdfc0, 0xdfe0,
1687                 0xe000, 0xea7c,
1688                 0xf000, 0x11110,
1689                 0x11118, 0x11190,
1690                 0x19040, 0x1906c,
1691                 0x19078, 0x19080,
1692                 0x1908c, 0x19124,
1693                 0x19150, 0x191b0,
1694                 0x191d0, 0x191e8,
1695                 0x19238, 0x1924c,
1696                 0x193f8, 0x19474,
1697                 0x19490, 0x194f8,
1698                 0x19800, 0x19f30,
1699                 0x1a000, 0x1a06c,
1700                 0x1a0b0, 0x1a120,
1701                 0x1a128, 0x1a138,
1702                 0x1a190, 0x1a1c4,
1703                 0x1a1fc, 0x1a1fc,
1704                 0x1e040, 0x1e04c,
1705                 0x1e284, 0x1e28c,
1706                 0x1e2c0, 0x1e2c0,
1707                 0x1e2e0, 0x1e2e0,
1708                 0x1e300, 0x1e384,
1709                 0x1e3c0, 0x1e3c8,
1710                 0x1e440, 0x1e44c,
1711                 0x1e684, 0x1e68c,
1712                 0x1e6c0, 0x1e6c0,
1713                 0x1e6e0, 0x1e6e0,
1714                 0x1e700, 0x1e784,
1715                 0x1e7c0, 0x1e7c8,
1716                 0x1e840, 0x1e84c,
1717                 0x1ea84, 0x1ea8c,
1718                 0x1eac0, 0x1eac0,
1719                 0x1eae0, 0x1eae0,
1720                 0x1eb00, 0x1eb84,
1721                 0x1ebc0, 0x1ebc8,
1722                 0x1ec40, 0x1ec4c,
1723                 0x1ee84, 0x1ee8c,
1724                 0x1eec0, 0x1eec0,
1725                 0x1eee0, 0x1eee0,
1726                 0x1ef00, 0x1ef84,
1727                 0x1efc0, 0x1efc8,
1728                 0x1f040, 0x1f04c,
1729                 0x1f284, 0x1f28c,
1730                 0x1f2c0, 0x1f2c0,
1731                 0x1f2e0, 0x1f2e0,
1732                 0x1f300, 0x1f384,
1733                 0x1f3c0, 0x1f3c8,
1734                 0x1f440, 0x1f44c,
1735                 0x1f684, 0x1f68c,
1736                 0x1f6c0, 0x1f6c0,
1737                 0x1f6e0, 0x1f6e0,
1738                 0x1f700, 0x1f784,
1739                 0x1f7c0, 0x1f7c8,
1740                 0x1f840, 0x1f84c,
1741                 0x1fa84, 0x1fa8c,
1742                 0x1fac0, 0x1fac0,
1743                 0x1fae0, 0x1fae0,
1744                 0x1fb00, 0x1fb84,
1745                 0x1fbc0, 0x1fbc8,
1746                 0x1fc40, 0x1fc4c,
1747                 0x1fe84, 0x1fe8c,
1748                 0x1fec0, 0x1fec0,
1749                 0x1fee0, 0x1fee0,
1750                 0x1ff00, 0x1ff84,
1751                 0x1ffc0, 0x1ffc8,
1752                 0x20000, 0x2002c,
1753                 0x20100, 0x2013c,
1754                 0x20190, 0x201c8,
1755                 0x20200, 0x20318,
1756                 0x20400, 0x20528,
1757                 0x20540, 0x20614,
1758                 0x21000, 0x21040,
1759                 0x2104c, 0x21060,
1760                 0x210c0, 0x210ec,
1761                 0x21200, 0x21268,
1762                 0x21270, 0x21284,
1763                 0x212fc, 0x21388,
1764                 0x21400, 0x21404,
1765                 0x21500, 0x21518,
1766                 0x2152c, 0x2153c,
1767                 0x21550, 0x21554,
1768                 0x21600, 0x21600,
1769                 0x21608, 0x21628,
1770                 0x21630, 0x2163c,
1771                 0x21700, 0x2171c,
1772                 0x21780, 0x2178c,
1773                 0x21800, 0x21c38,
1774                 0x21c80, 0x21d7c,
1775                 0x21e00, 0x21e04,
1776                 0x22000, 0x2202c,
1777                 0x22100, 0x2213c,
1778                 0x22190, 0x221c8,
1779                 0x22200, 0x22318,
1780                 0x22400, 0x22528,
1781                 0x22540, 0x22614,
1782                 0x23000, 0x23040,
1783                 0x2304c, 0x23060,
1784                 0x230c0, 0x230ec,
1785                 0x23200, 0x23268,
1786                 0x23270, 0x23284,
1787                 0x232fc, 0x23388,
1788                 0x23400, 0x23404,
1789                 0x23500, 0x23518,
1790                 0x2352c, 0x2353c,
1791                 0x23550, 0x23554,
1792                 0x23600, 0x23600,
1793                 0x23608, 0x23628,
1794                 0x23630, 0x2363c,
1795                 0x23700, 0x2371c,
1796                 0x23780, 0x2378c,
1797                 0x23800, 0x23c38,
1798                 0x23c80, 0x23d7c,
1799                 0x23e00, 0x23e04,
1800                 0x24000, 0x2402c,
1801                 0x24100, 0x2413c,
1802                 0x24190, 0x241c8,
1803                 0x24200, 0x24318,
1804                 0x24400, 0x24528,
1805                 0x24540, 0x24614,
1806                 0x25000, 0x25040,
1807                 0x2504c, 0x25060,
1808                 0x250c0, 0x250ec,
1809                 0x25200, 0x25268,
1810                 0x25270, 0x25284,
1811                 0x252fc, 0x25388,
1812                 0x25400, 0x25404,
1813                 0x25500, 0x25518,
1814                 0x2552c, 0x2553c,
1815                 0x25550, 0x25554,
1816                 0x25600, 0x25600,
1817                 0x25608, 0x25628,
1818                 0x25630, 0x2563c,
1819                 0x25700, 0x2571c,
1820                 0x25780, 0x2578c,
1821                 0x25800, 0x25c38,
1822                 0x25c80, 0x25d7c,
1823                 0x25e00, 0x25e04,
1824                 0x26000, 0x2602c,
1825                 0x26100, 0x2613c,
1826                 0x26190, 0x261c8,
1827                 0x26200, 0x26318,
1828                 0x26400, 0x26528,
1829                 0x26540, 0x26614,
1830                 0x27000, 0x27040,
1831                 0x2704c, 0x27060,
1832                 0x270c0, 0x270ec,
1833                 0x27200, 0x27268,
1834                 0x27270, 0x27284,
1835                 0x272fc, 0x27388,
1836                 0x27400, 0x27404,
1837                 0x27500, 0x27518,
1838                 0x2752c, 0x2753c,
1839                 0x27550, 0x27554,
1840                 0x27600, 0x27600,
1841                 0x27608, 0x27628,
1842                 0x27630, 0x2763c,
1843                 0x27700, 0x2771c,
1844                 0x27780, 0x2778c,
1845                 0x27800, 0x27c38,
1846                 0x27c80, 0x27d7c,
1847                 0x27e00, 0x27e04
1848         };
1849
1850         static const unsigned int t5_reg_ranges[] = {
1851                 0x1008, 0x1148,
1852                 0x1180, 0x11b4,
1853                 0x11fc, 0x123c,
1854                 0x1280, 0x173c,
1855                 0x1800, 0x18fc,
1856                 0x3000, 0x3028,
1857                 0x3060, 0x30d8,
1858                 0x30e0, 0x30fc,
1859                 0x3140, 0x357c,
1860                 0x35a8, 0x35cc,
1861                 0x35ec, 0x35ec,
1862                 0x3600, 0x5624,
1863                 0x56cc, 0x575c,
1864                 0x580c, 0x5814,
1865                 0x5890, 0x58bc,
1866                 0x5940, 0x59dc,
1867                 0x59fc, 0x5a18,
1868                 0x5a60, 0x5a9c,
1869                 0x5b9c, 0x5bfc,
1870                 0x6000, 0x6040,
1871                 0x6058, 0x614c,
1872                 0x7700, 0x7798,
1873                 0x77c0, 0x78fc,
1874                 0x7b00, 0x7c54,
1875                 0x7d00, 0x7efc,
1876                 0x8dc0, 0x8de0,
1877                 0x8df8, 0x8e84,
1878                 0x8ea0, 0x8f84,
1879                 0x8fc0, 0x90f8,
1880                 0x9400, 0x9470,
1881                 0x9600, 0x96f4,
1882                 0x9800, 0x9808,
1883                 0x9820, 0x983c,
1884                 0x9850, 0x9864,
1885                 0x9c00, 0x9c6c,
1886                 0x9c80, 0x9cec,
1887                 0x9d00, 0x9d6c,
1888                 0x9d80, 0x9dec,
1889                 0x9e00, 0x9e6c,
1890                 0x9e80, 0x9eec,
1891                 0x9f00, 0x9f6c,
1892                 0x9f80, 0xa020,
1893                 0xd004, 0xd03c,
1894                 0xdfc0, 0xdfe0,
1895                 0xe000, 0x11088,
1896                 0x1109c, 0x11110,
1897                 0x11118, 0x1117c,
1898                 0x11190, 0x11204,
1899                 0x19040, 0x1906c,
1900                 0x19078, 0x19080,
1901                 0x1908c, 0x19124,
1902                 0x19150, 0x191b0,
1903                 0x191d0, 0x191e8,
1904                 0x19238, 0x19290,
1905                 0x193f8, 0x19474,
1906                 0x19490, 0x194cc,
1907                 0x194f0, 0x194f8,
1908                 0x19c00, 0x19c60,
1909                 0x19c94, 0x19e10,
1910                 0x19e50, 0x19f34,
1911                 0x19f40, 0x19f50,
1912                 0x19f90, 0x19fe4,
1913                 0x1a000, 0x1a06c,
1914                 0x1a0b0, 0x1a120,
1915                 0x1a128, 0x1a138,
1916                 0x1a190, 0x1a1c4,
1917                 0x1a1fc, 0x1a1fc,
1918                 0x1e008, 0x1e00c,
1919                 0x1e040, 0x1e04c,
1920                 0x1e284, 0x1e290,
1921                 0x1e2c0, 0x1e2c0,
1922                 0x1e2e0, 0x1e2e0,
1923                 0x1e300, 0x1e384,
1924                 0x1e3c0, 0x1e3c8,
1925                 0x1e408, 0x1e40c,
1926                 0x1e440, 0x1e44c,
1927                 0x1e684, 0x1e690,
1928                 0x1e6c0, 0x1e6c0,
1929                 0x1e6e0, 0x1e6e0,
1930                 0x1e700, 0x1e784,
1931                 0x1e7c0, 0x1e7c8,
1932                 0x1e808, 0x1e80c,
1933                 0x1e840, 0x1e84c,
1934                 0x1ea84, 0x1ea90,
1935                 0x1eac0, 0x1eac0,
1936                 0x1eae0, 0x1eae0,
1937                 0x1eb00, 0x1eb84,
1938                 0x1ebc0, 0x1ebc8,
1939                 0x1ec08, 0x1ec0c,
1940                 0x1ec40, 0x1ec4c,
1941                 0x1ee84, 0x1ee90,
1942                 0x1eec0, 0x1eec0,
1943                 0x1eee0, 0x1eee0,
1944                 0x1ef00, 0x1ef84,
1945                 0x1efc0, 0x1efc8,
1946                 0x1f008, 0x1f00c,
1947                 0x1f040, 0x1f04c,
1948                 0x1f284, 0x1f290,
1949                 0x1f2c0, 0x1f2c0,
1950                 0x1f2e0, 0x1f2e0,
1951                 0x1f300, 0x1f384,
1952                 0x1f3c0, 0x1f3c8,
1953                 0x1f408, 0x1f40c,
1954                 0x1f440, 0x1f44c,
1955                 0x1f684, 0x1f690,
1956                 0x1f6c0, 0x1f6c0,
1957                 0x1f6e0, 0x1f6e0,
1958                 0x1f700, 0x1f784,
1959                 0x1f7c0, 0x1f7c8,
1960                 0x1f808, 0x1f80c,
1961                 0x1f840, 0x1f84c,
1962                 0x1fa84, 0x1fa90,
1963                 0x1fac0, 0x1fac0,
1964                 0x1fae0, 0x1fae0,
1965                 0x1fb00, 0x1fb84,
1966                 0x1fbc0, 0x1fbc8,
1967                 0x1fc08, 0x1fc0c,
1968                 0x1fc40, 0x1fc4c,
1969                 0x1fe84, 0x1fe90,
1970                 0x1fec0, 0x1fec0,
1971                 0x1fee0, 0x1fee0,
1972                 0x1ff00, 0x1ff84,
1973                 0x1ffc0, 0x1ffc8,
1974                 0x30000, 0x30030,
1975                 0x30100, 0x30144,
1976                 0x30190, 0x301d0,
1977                 0x30200, 0x30318,
1978                 0x30400, 0x3052c,
1979                 0x30540, 0x3061c,
1980                 0x30800, 0x30834,
1981                 0x308c0, 0x30908,
1982                 0x30910, 0x309ac,
1983                 0x30a00, 0x30a04,
1984                 0x30a0c, 0x30a2c,
1985                 0x30a44, 0x30a50,
1986                 0x30a74, 0x30c24,
1987                 0x30d08, 0x30d14,
1988                 0x30d1c, 0x30d20,
1989                 0x30d3c, 0x30d50,
1990                 0x31200, 0x3120c,
1991                 0x31220, 0x31220,
1992                 0x31240, 0x31240,
1993                 0x31600, 0x31600,
1994                 0x31608, 0x3160c,
1995                 0x31a00, 0x31a1c,
1996                 0x31e04, 0x31e20,
1997                 0x31e38, 0x31e3c,
1998                 0x31e80, 0x31e80,
1999                 0x31e88, 0x31ea8,
2000                 0x31eb0, 0x31eb4,
2001                 0x31ec8, 0x31ed4,
2002                 0x31fb8, 0x32004,
2003                 0x32208, 0x3223c,
2004                 0x32600, 0x32630,
2005                 0x32a00, 0x32abc,
2006                 0x32b00, 0x32b70,
2007                 0x33000, 0x33048,
2008                 0x33060, 0x3309c,
2009                 0x330f0, 0x33148,
2010                 0x33160, 0x3319c,
2011                 0x331f0, 0x332e4,
2012                 0x332f8, 0x333e4,
2013                 0x333f8, 0x33448,
2014                 0x33460, 0x3349c,
2015                 0x334f0, 0x33548,
2016                 0x33560, 0x3359c,
2017                 0x335f0, 0x336e4,
2018                 0x336f8, 0x337e4,
2019                 0x337f8, 0x337fc,
2020                 0x33814, 0x33814,
2021                 0x3382c, 0x3382c,
2022                 0x33880, 0x3388c,
2023                 0x338e8, 0x338ec,
2024                 0x33900, 0x33948,
2025                 0x33960, 0x3399c,
2026                 0x339f0, 0x33ae4,
2027                 0x33af8, 0x33b10,
2028                 0x33b28, 0x33b28,
2029                 0x33b3c, 0x33b50,
2030                 0x33bf0, 0x33c10,
2031                 0x33c28, 0x33c28,
2032                 0x33c3c, 0x33c50,
2033                 0x33cf0, 0x33cfc,
2034                 0x34000, 0x34030,
2035                 0x34100, 0x34144,
2036                 0x34190, 0x341d0,
2037                 0x34200, 0x34318,
2038                 0x34400, 0x3452c,
2039                 0x34540, 0x3461c,
2040                 0x34800, 0x34834,
2041                 0x348c0, 0x34908,
2042                 0x34910, 0x349ac,
2043                 0x34a00, 0x34a04,
2044                 0x34a0c, 0x34a2c,
2045                 0x34a44, 0x34a50,
2046                 0x34a74, 0x34c24,
2047                 0x34d08, 0x34d14,
2048                 0x34d1c, 0x34d20,
2049                 0x34d3c, 0x34d50,
2050                 0x35200, 0x3520c,
2051                 0x35220, 0x35220,
2052                 0x35240, 0x35240,
2053                 0x35600, 0x35600,
2054                 0x35608, 0x3560c,
2055                 0x35a00, 0x35a1c,
2056                 0x35e04, 0x35e20,
2057                 0x35e38, 0x35e3c,
2058                 0x35e80, 0x35e80,
2059                 0x35e88, 0x35ea8,
2060                 0x35eb0, 0x35eb4,
2061                 0x35ec8, 0x35ed4,
2062                 0x35fb8, 0x36004,
2063                 0x36208, 0x3623c,
2064                 0x36600, 0x36630,
2065                 0x36a00, 0x36abc,
2066                 0x36b00, 0x36b70,
2067                 0x37000, 0x37048,
2068                 0x37060, 0x3709c,
2069                 0x370f0, 0x37148,
2070                 0x37160, 0x3719c,
2071                 0x371f0, 0x372e4,
2072                 0x372f8, 0x373e4,
2073                 0x373f8, 0x37448,
2074                 0x37460, 0x3749c,
2075                 0x374f0, 0x37548,
2076                 0x37560, 0x3759c,
2077                 0x375f0, 0x376e4,
2078                 0x376f8, 0x377e4,
2079                 0x377f8, 0x377fc,
2080                 0x37814, 0x37814,
2081                 0x3782c, 0x3782c,
2082                 0x37880, 0x3788c,
2083                 0x378e8, 0x378ec,
2084                 0x37900, 0x37948,
2085                 0x37960, 0x3799c,
2086                 0x379f0, 0x37ae4,
2087                 0x37af8, 0x37b10,
2088                 0x37b28, 0x37b28,
2089                 0x37b3c, 0x37b50,
2090                 0x37bf0, 0x37c10,
2091                 0x37c28, 0x37c28,
2092                 0x37c3c, 0x37c50,
2093                 0x37cf0, 0x37cfc,
2094                 0x38000, 0x38030,
2095                 0x38100, 0x38144,
2096                 0x38190, 0x381d0,
2097                 0x38200, 0x38318,
2098                 0x38400, 0x3852c,
2099                 0x38540, 0x3861c,
2100                 0x38800, 0x38834,
2101                 0x388c0, 0x38908,
2102                 0x38910, 0x389ac,
2103                 0x38a00, 0x38a04,
2104                 0x38a0c, 0x38a2c,
2105                 0x38a44, 0x38a50,
2106                 0x38a74, 0x38c24,
2107                 0x38d08, 0x38d14,
2108                 0x38d1c, 0x38d20,
2109                 0x38d3c, 0x38d50,
2110                 0x39200, 0x3920c,
2111                 0x39220, 0x39220,
2112                 0x39240, 0x39240,
2113                 0x39600, 0x39600,
2114                 0x39608, 0x3960c,
2115                 0x39a00, 0x39a1c,
2116                 0x39e04, 0x39e20,
2117                 0x39e38, 0x39e3c,
2118                 0x39e80, 0x39e80,
2119                 0x39e88, 0x39ea8,
2120                 0x39eb0, 0x39eb4,
2121                 0x39ec8, 0x39ed4,
2122                 0x39fb8, 0x3a004,
2123                 0x3a208, 0x3a23c,
2124                 0x3a600, 0x3a630,
2125                 0x3aa00, 0x3aabc,
2126                 0x3ab00, 0x3ab70,
2127                 0x3b000, 0x3b048,
2128                 0x3b060, 0x3b09c,
2129                 0x3b0f0, 0x3b148,
2130                 0x3b160, 0x3b19c,
2131                 0x3b1f0, 0x3b2e4,
2132                 0x3b2f8, 0x3b3e4,
2133                 0x3b3f8, 0x3b448,
2134                 0x3b460, 0x3b49c,
2135                 0x3b4f0, 0x3b548,
2136                 0x3b560, 0x3b59c,
2137                 0x3b5f0, 0x3b6e4,
2138                 0x3b6f8, 0x3b7e4,
2139                 0x3b7f8, 0x3b7fc,
2140                 0x3b814, 0x3b814,
2141                 0x3b82c, 0x3b82c,
2142                 0x3b880, 0x3b88c,
2143                 0x3b8e8, 0x3b8ec,
2144                 0x3b900, 0x3b948,
2145                 0x3b960, 0x3b99c,
2146                 0x3b9f0, 0x3bae4,
2147                 0x3baf8, 0x3bb10,
2148                 0x3bb28, 0x3bb28,
2149                 0x3bb3c, 0x3bb50,
2150                 0x3bbf0, 0x3bc10,
2151                 0x3bc28, 0x3bc28,
2152                 0x3bc3c, 0x3bc50,
2153                 0x3bcf0, 0x3bcfc,
2154                 0x3c000, 0x3c030,
2155                 0x3c100, 0x3c144,
2156                 0x3c190, 0x3c1d0,
2157                 0x3c200, 0x3c318,
2158                 0x3c400, 0x3c52c,
2159                 0x3c540, 0x3c61c,
2160                 0x3c800, 0x3c834,
2161                 0x3c8c0, 0x3c908,
2162                 0x3c910, 0x3c9ac,
2163                 0x3ca00, 0x3ca04,
2164                 0x3ca0c, 0x3ca2c,
2165                 0x3ca44, 0x3ca50,
2166                 0x3ca74, 0x3cc24,
2167                 0x3cd08, 0x3cd14,
2168                 0x3cd1c, 0x3cd20,
2169                 0x3cd3c, 0x3cd50,
2170                 0x3d200, 0x3d20c,
2171                 0x3d220, 0x3d220,
2172                 0x3d240, 0x3d240,
2173                 0x3d600, 0x3d600,
2174                 0x3d608, 0x3d60c,
2175                 0x3da00, 0x3da1c,
2176                 0x3de04, 0x3de20,
2177                 0x3de38, 0x3de3c,
2178                 0x3de80, 0x3de80,
2179                 0x3de88, 0x3dea8,
2180                 0x3deb0, 0x3deb4,
2181                 0x3dec8, 0x3ded4,
2182                 0x3dfb8, 0x3e004,
2183                 0x3e208, 0x3e23c,
2184                 0x3e600, 0x3e630,
2185                 0x3ea00, 0x3eabc,
2186                 0x3eb00, 0x3eb70,
2187                 0x3f000, 0x3f048,
2188                 0x3f060, 0x3f09c,
2189                 0x3f0f0, 0x3f148,
2190                 0x3f160, 0x3f19c,
2191                 0x3f1f0, 0x3f2e4,
2192                 0x3f2f8, 0x3f3e4,
2193                 0x3f3f8, 0x3f448,
2194                 0x3f460, 0x3f49c,
2195                 0x3f4f0, 0x3f548,
2196                 0x3f560, 0x3f59c,
2197                 0x3f5f0, 0x3f6e4,
2198                 0x3f6f8, 0x3f7e4,
2199                 0x3f7f8, 0x3f7fc,
2200                 0x3f814, 0x3f814,
2201                 0x3f82c, 0x3f82c,
2202                 0x3f880, 0x3f88c,
2203                 0x3f8e8, 0x3f8ec,
2204                 0x3f900, 0x3f948,
2205                 0x3f960, 0x3f99c,
2206                 0x3f9f0, 0x3fae4,
2207                 0x3faf8, 0x3fb10,
2208                 0x3fb28, 0x3fb28,
2209                 0x3fb3c, 0x3fb50,
2210                 0x3fbf0, 0x3fc10,
2211                 0x3fc28, 0x3fc28,
2212                 0x3fc3c, 0x3fc50,
2213                 0x3fcf0, 0x3fcfc,
2214                 0x40000, 0x4000c,
2215                 0x40040, 0x40068,
2216                 0x40080, 0x40144,
2217                 0x40180, 0x4018c,
2218                 0x40200, 0x40298,
2219                 0x402ac, 0x4033c,
2220                 0x403f8, 0x403fc,
2221                 0x41304, 0x413c4,
2222                 0x41400, 0x4141c,
2223                 0x41480, 0x414d0,
2224                 0x44000, 0x44078,
2225                 0x440c0, 0x44278,
2226                 0x442c0, 0x44478,
2227                 0x444c0, 0x44678,
2228                 0x446c0, 0x44878,
2229                 0x448c0, 0x449fc,
2230                 0x45000, 0x45068,
2231                 0x45080, 0x45084,
2232                 0x450a0, 0x450b0,
2233                 0x45200, 0x45268,
2234                 0x45280, 0x45284,
2235                 0x452a0, 0x452b0,
2236                 0x460c0, 0x460e4,
2237                 0x47000, 0x4708c,
2238                 0x47200, 0x47250,
2239                 0x47400, 0x47420,
2240                 0x47600, 0x47618,
2241                 0x47800, 0x47814,
2242                 0x48000, 0x4800c,
2243                 0x48040, 0x48068,
2244                 0x48080, 0x48144,
2245                 0x48180, 0x4818c,
2246                 0x48200, 0x48298,
2247                 0x482ac, 0x4833c,
2248                 0x483f8, 0x483fc,
2249                 0x49304, 0x493c4,
2250                 0x49400, 0x4941c,
2251                 0x49480, 0x494d0,
2252                 0x4c000, 0x4c078,
2253                 0x4c0c0, 0x4c278,
2254                 0x4c2c0, 0x4c478,
2255                 0x4c4c0, 0x4c678,
2256                 0x4c6c0, 0x4c878,
2257                 0x4c8c0, 0x4c9fc,
2258                 0x4d000, 0x4d068,
2259                 0x4d080, 0x4d084,
2260                 0x4d0a0, 0x4d0b0,
2261                 0x4d200, 0x4d268,
2262                 0x4d280, 0x4d284,
2263                 0x4d2a0, 0x4d2b0,
2264                 0x4e0c0, 0x4e0e4,
2265                 0x4f000, 0x4f08c,
2266                 0x4f200, 0x4f250,
2267                 0x4f400, 0x4f420,
2268                 0x4f600, 0x4f618,
2269                 0x4f800, 0x4f814,
2270                 0x50000, 0x500cc,
2271                 0x50400, 0x50400,
2272                 0x50800, 0x508cc,
2273                 0x50c00, 0x50c00,
2274                 0x51000, 0x5101c,
2275                 0x51300, 0x51308,
2276         };
2277
2278         int i;
2279         struct adapter *ap = netdev2adap(dev);
2280         static const unsigned int *reg_ranges;
2281         int arr_size = 0, buf_size = 0;
2282
2283         if (is_t4(ap->params.chip)) {
2284                 reg_ranges = &t4_reg_ranges[0];
2285                 arr_size = ARRAY_SIZE(t4_reg_ranges);
2286                 buf_size = T4_REGMAP_SIZE;
2287         } else {
2288                 reg_ranges = &t5_reg_ranges[0];
2289                 arr_size = ARRAY_SIZE(t5_reg_ranges);
2290                 buf_size = T5_REGMAP_SIZE;
2291         }
2292
2293         regs->version = mk_adap_vers(ap);
2294
2295         memset(buf, 0, buf_size);
2296         for (i = 0; i < arr_size; i += 2)
2297                 reg_block_dump(ap, buf, reg_ranges[i], reg_ranges[i + 1]);
2298 }
2299
2300 static int restart_autoneg(struct net_device *dev)
2301 {
2302         struct port_info *p = netdev_priv(dev);
2303
2304         if (!netif_running(dev))
2305                 return -EAGAIN;
2306         if (p->link_cfg.autoneg != AUTONEG_ENABLE)
2307                 return -EINVAL;
2308         t4_restart_aneg(p->adapter, p->adapter->fn, p->tx_chan);
2309         return 0;
2310 }
2311
2312 static int identify_port(struct net_device *dev,
2313                          enum ethtool_phys_id_state state)
2314 {
2315         unsigned int val;
2316         struct adapter *adap = netdev2adap(dev);
2317
2318         if (state == ETHTOOL_ID_ACTIVE)
2319                 val = 0xffff;
2320         else if (state == ETHTOOL_ID_INACTIVE)
2321                 val = 0;
2322         else
2323                 return -EINVAL;
2324
2325         return t4_identify_port(adap, adap->fn, netdev2pinfo(dev)->viid, val);
2326 }
2327
2328 static unsigned int from_fw_linkcaps(unsigned int type, unsigned int caps)
2329 {
2330         unsigned int v = 0;
2331
2332         if (type == FW_PORT_TYPE_BT_SGMII || type == FW_PORT_TYPE_BT_XFI ||
2333             type == FW_PORT_TYPE_BT_XAUI) {
2334                 v |= SUPPORTED_TP;
2335                 if (caps & FW_PORT_CAP_SPEED_100M)
2336                         v |= SUPPORTED_100baseT_Full;
2337                 if (caps & FW_PORT_CAP_SPEED_1G)
2338                         v |= SUPPORTED_1000baseT_Full;
2339                 if (caps & FW_PORT_CAP_SPEED_10G)
2340                         v |= SUPPORTED_10000baseT_Full;
2341         } else if (type == FW_PORT_TYPE_KX4 || type == FW_PORT_TYPE_KX) {
2342                 v |= SUPPORTED_Backplane;
2343                 if (caps & FW_PORT_CAP_SPEED_1G)
2344                         v |= SUPPORTED_1000baseKX_Full;
2345                 if (caps & FW_PORT_CAP_SPEED_10G)
2346                         v |= SUPPORTED_10000baseKX4_Full;
2347         } else if (type == FW_PORT_TYPE_KR)
2348                 v |= SUPPORTED_Backplane | SUPPORTED_10000baseKR_Full;
2349         else if (type == FW_PORT_TYPE_BP_AP)
2350                 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
2351                      SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full;
2352         else if (type == FW_PORT_TYPE_BP4_AP)
2353                 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
2354                      SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full |
2355                      SUPPORTED_10000baseKX4_Full;
2356         else if (type == FW_PORT_TYPE_FIBER_XFI ||
2357                  type == FW_PORT_TYPE_FIBER_XAUI || type == FW_PORT_TYPE_SFP)
2358                 v |= SUPPORTED_FIBRE;
2359         else if (type == FW_PORT_TYPE_BP40_BA)
2360                 v |= SUPPORTED_40000baseSR4_Full;
2361
2362         if (caps & FW_PORT_CAP_ANEG)
2363                 v |= SUPPORTED_Autoneg;
2364         return v;
2365 }
2366
2367 static unsigned int to_fw_linkcaps(unsigned int caps)
2368 {
2369         unsigned int v = 0;
2370
2371         if (caps & ADVERTISED_100baseT_Full)
2372                 v |= FW_PORT_CAP_SPEED_100M;
2373         if (caps & ADVERTISED_1000baseT_Full)
2374                 v |= FW_PORT_CAP_SPEED_1G;
2375         if (caps & ADVERTISED_10000baseT_Full)
2376                 v |= FW_PORT_CAP_SPEED_10G;
2377         if (caps & ADVERTISED_40000baseSR4_Full)
2378                 v |= FW_PORT_CAP_SPEED_40G;
2379         return v;
2380 }
2381
2382 static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2383 {
2384         const struct port_info *p = netdev_priv(dev);
2385
2386         if (p->port_type == FW_PORT_TYPE_BT_SGMII ||
2387             p->port_type == FW_PORT_TYPE_BT_XFI ||
2388             p->port_type == FW_PORT_TYPE_BT_XAUI)
2389                 cmd->port = PORT_TP;
2390         else if (p->port_type == FW_PORT_TYPE_FIBER_XFI ||
2391                  p->port_type == FW_PORT_TYPE_FIBER_XAUI)
2392                 cmd->port = PORT_FIBRE;
2393         else if (p->port_type == FW_PORT_TYPE_SFP ||
2394                  p->port_type == FW_PORT_TYPE_QSFP_10G ||
2395                  p->port_type == FW_PORT_TYPE_QSFP) {
2396                 if (p->mod_type == FW_PORT_MOD_TYPE_LR ||
2397                     p->mod_type == FW_PORT_MOD_TYPE_SR ||
2398                     p->mod_type == FW_PORT_MOD_TYPE_ER ||
2399                     p->mod_type == FW_PORT_MOD_TYPE_LRM)
2400                         cmd->port = PORT_FIBRE;
2401                 else if (p->mod_type == FW_PORT_MOD_TYPE_TWINAX_PASSIVE ||
2402                          p->mod_type == FW_PORT_MOD_TYPE_TWINAX_ACTIVE)
2403                         cmd->port = PORT_DA;
2404                 else
2405                         cmd->port = PORT_OTHER;
2406         } else
2407                 cmd->port = PORT_OTHER;
2408
2409         if (p->mdio_addr >= 0) {
2410                 cmd->phy_address = p->mdio_addr;
2411                 cmd->transceiver = XCVR_EXTERNAL;
2412                 cmd->mdio_support = p->port_type == FW_PORT_TYPE_BT_SGMII ?
2413                         MDIO_SUPPORTS_C22 : MDIO_SUPPORTS_C45;
2414         } else {
2415                 cmd->phy_address = 0;  /* not really, but no better option */
2416                 cmd->transceiver = XCVR_INTERNAL;
2417                 cmd->mdio_support = 0;
2418         }
2419
2420         cmd->supported = from_fw_linkcaps(p->port_type, p->link_cfg.supported);
2421         cmd->advertising = from_fw_linkcaps(p->port_type,
2422                                             p->link_cfg.advertising);
2423         ethtool_cmd_speed_set(cmd,
2424                               netif_carrier_ok(dev) ? p->link_cfg.speed : 0);
2425         cmd->duplex = DUPLEX_FULL;
2426         cmd->autoneg = p->link_cfg.autoneg;
2427         cmd->maxtxpkt = 0;
2428         cmd->maxrxpkt = 0;
2429         return 0;
2430 }
2431
2432 static unsigned int speed_to_caps(int speed)
2433 {
2434         if (speed == 100)
2435                 return FW_PORT_CAP_SPEED_100M;
2436         if (speed == 1000)
2437                 return FW_PORT_CAP_SPEED_1G;
2438         if (speed == 10000)
2439                 return FW_PORT_CAP_SPEED_10G;
2440         if (speed == 40000)
2441                 return FW_PORT_CAP_SPEED_40G;
2442         return 0;
2443 }
2444
2445 static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2446 {
2447         unsigned int cap;
2448         struct port_info *p = netdev_priv(dev);
2449         struct link_config *lc = &p->link_cfg;
2450         u32 speed = ethtool_cmd_speed(cmd);
2451
2452         if (cmd->duplex != DUPLEX_FULL)     /* only full-duplex supported */
2453                 return -EINVAL;
2454
2455         if (!(lc->supported & FW_PORT_CAP_ANEG)) {
2456                 /*
2457                  * PHY offers a single speed.  See if that's what's
2458                  * being requested.
2459                  */
2460                 if (cmd->autoneg == AUTONEG_DISABLE &&
2461                     (lc->supported & speed_to_caps(speed)))
2462                         return 0;
2463                 return -EINVAL;
2464         }
2465
2466         if (cmd->autoneg == AUTONEG_DISABLE) {
2467                 cap = speed_to_caps(speed);
2468
2469                 if (!(lc->supported & cap) ||
2470                     (speed == 1000) ||
2471                     (speed == 10000) ||
2472                     (speed == 40000))
2473                         return -EINVAL;
2474                 lc->requested_speed = cap;
2475                 lc->advertising = 0;
2476         } else {
2477                 cap = to_fw_linkcaps(cmd->advertising);
2478                 if (!(lc->supported & cap))
2479                         return -EINVAL;
2480                 lc->requested_speed = 0;
2481                 lc->advertising = cap | FW_PORT_CAP_ANEG;
2482         }
2483         lc->autoneg = cmd->autoneg;
2484
2485         if (netif_running(dev))
2486                 return t4_link_start(p->adapter, p->adapter->fn, p->tx_chan,
2487                                      lc);
2488         return 0;
2489 }
2490
2491 static void get_pauseparam(struct net_device *dev,
2492                            struct ethtool_pauseparam *epause)
2493 {
2494         struct port_info *p = netdev_priv(dev);
2495
2496         epause->autoneg = (p->link_cfg.requested_fc & PAUSE_AUTONEG) != 0;
2497         epause->rx_pause = (p->link_cfg.fc & PAUSE_RX) != 0;
2498         epause->tx_pause = (p->link_cfg.fc & PAUSE_TX) != 0;
2499 }
2500
2501 static int set_pauseparam(struct net_device *dev,
2502                           struct ethtool_pauseparam *epause)
2503 {
2504         struct port_info *p = netdev_priv(dev);
2505         struct link_config *lc = &p->link_cfg;
2506
2507         if (epause->autoneg == AUTONEG_DISABLE)
2508                 lc->requested_fc = 0;
2509         else if (lc->supported & FW_PORT_CAP_ANEG)
2510                 lc->requested_fc = PAUSE_AUTONEG;
2511         else
2512                 return -EINVAL;
2513
2514         if (epause->rx_pause)
2515                 lc->requested_fc |= PAUSE_RX;
2516         if (epause->tx_pause)
2517                 lc->requested_fc |= PAUSE_TX;
2518         if (netif_running(dev))
2519                 return t4_link_start(p->adapter, p->adapter->fn, p->tx_chan,
2520                                      lc);
2521         return 0;
2522 }
2523
2524 static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
2525 {
2526         const struct port_info *pi = netdev_priv(dev);
2527         const struct sge *s = &pi->adapter->sge;
2528
2529         e->rx_max_pending = MAX_RX_BUFFERS;
2530         e->rx_mini_max_pending = MAX_RSPQ_ENTRIES;
2531         e->rx_jumbo_max_pending = 0;
2532         e->tx_max_pending = MAX_TXQ_ENTRIES;
2533
2534         e->rx_pending = s->ethrxq[pi->first_qset].fl.size - 8;
2535         e->rx_mini_pending = s->ethrxq[pi->first_qset].rspq.size;
2536         e->rx_jumbo_pending = 0;
2537         e->tx_pending = s->ethtxq[pi->first_qset].q.size;
2538 }
2539
2540 static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
2541 {
2542         int i;
2543         const struct port_info *pi = netdev_priv(dev);
2544         struct adapter *adapter = pi->adapter;
2545         struct sge *s = &adapter->sge;
2546
2547         if (e->rx_pending > MAX_RX_BUFFERS || e->rx_jumbo_pending ||
2548             e->tx_pending > MAX_TXQ_ENTRIES ||
2549             e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
2550             e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
2551             e->rx_pending < MIN_FL_ENTRIES || e->tx_pending < MIN_TXQ_ENTRIES)
2552                 return -EINVAL;
2553
2554         if (adapter->flags & FULL_INIT_DONE)
2555                 return -EBUSY;
2556
2557         for (i = 0; i < pi->nqsets; ++i) {
2558                 s->ethtxq[pi->first_qset + i].q.size = e->tx_pending;
2559                 s->ethrxq[pi->first_qset + i].fl.size = e->rx_pending + 8;
2560                 s->ethrxq[pi->first_qset + i].rspq.size = e->rx_mini_pending;
2561         }
2562         return 0;
2563 }
2564
2565 static int closest_timer(const struct sge *s, int time)
2566 {
2567         int i, delta, match = 0, min_delta = INT_MAX;
2568
2569         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
2570                 delta = time - s->timer_val[i];
2571                 if (delta < 0)
2572                         delta = -delta;
2573                 if (delta < min_delta) {
2574                         min_delta = delta;
2575                         match = i;
2576                 }
2577         }
2578         return match;
2579 }
2580
2581 static int closest_thres(const struct sge *s, int thres)
2582 {
2583         int i, delta, match = 0, min_delta = INT_MAX;
2584
2585         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
2586                 delta = thres - s->counter_val[i];
2587                 if (delta < 0)
2588                         delta = -delta;
2589                 if (delta < min_delta) {
2590                         min_delta = delta;
2591                         match = i;
2592                 }
2593         }
2594         return match;
2595 }
2596
2597 /*
2598  * Return a queue's interrupt hold-off time in us.  0 means no timer.
2599  */
2600 static unsigned int qtimer_val(const struct adapter *adap,
2601                                const struct sge_rspq *q)
2602 {
2603         unsigned int idx = q->intr_params >> 1;
2604
2605         return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
2606 }
2607
2608 /**
2609  *      set_rspq_intr_params - set a queue's interrupt holdoff parameters
2610  *      @q: the Rx queue
2611  *      @us: the hold-off time in us, or 0 to disable timer
2612  *      @cnt: the hold-off packet count, or 0 to disable counter
2613  *
2614  *      Sets an Rx queue's interrupt hold-off time and packet count.  At least
2615  *      one of the two needs to be enabled for the queue to generate interrupts.
2616  */
2617 static int set_rspq_intr_params(struct sge_rspq *q,
2618                                 unsigned int us, unsigned int cnt)
2619 {
2620         struct adapter *adap = q->adap;
2621
2622         if ((us | cnt) == 0)
2623                 cnt = 1;
2624
2625         if (cnt) {
2626                 int err;
2627                 u32 v, new_idx;
2628
2629                 new_idx = closest_thres(&adap->sge, cnt);
2630                 if (q->desc && q->pktcnt_idx != new_idx) {
2631                         /* the queue has already been created, update it */
2632                         v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
2633                             FW_PARAMS_PARAM_X_V(
2634                                         FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
2635                             FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
2636                         err = t4_set_params(adap, adap->fn, adap->fn, 0, 1, &v,
2637                                             &new_idx);
2638                         if (err)
2639                                 return err;
2640                 }
2641                 q->pktcnt_idx = new_idx;
2642         }
2643
2644         us = us == 0 ? 6 : closest_timer(&adap->sge, us);
2645         q->intr_params = QINTR_TIMER_IDX(us) | (cnt > 0 ? QINTR_CNT_EN : 0);
2646         return 0;
2647 }
2648
2649 /**
2650  * set_rx_intr_params - set a net devices's RX interrupt holdoff paramete!
2651  * @dev: the network device
2652  * @us: the hold-off time in us, or 0 to disable timer
2653  * @cnt: the hold-off packet count, or 0 to disable counter
2654  *
2655  * Set the RX interrupt hold-off parameters for a network device.
2656  */
2657 static int set_rx_intr_params(struct net_device *dev,
2658                               unsigned int us, unsigned int cnt)
2659 {
2660         int i, err;
2661         struct port_info *pi = netdev_priv(dev);
2662         struct adapter *adap = pi->adapter;
2663         struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
2664
2665         for (i = 0; i < pi->nqsets; i++, q++) {
2666                 err = set_rspq_intr_params(&q->rspq, us, cnt);
2667                 if (err)
2668                         return err;
2669         }
2670         return 0;
2671 }
2672
2673 static int set_adaptive_rx_setting(struct net_device *dev, int adaptive_rx)
2674 {
2675         int i;
2676         struct port_info *pi = netdev_priv(dev);
2677         struct adapter *adap = pi->adapter;
2678         struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
2679
2680         for (i = 0; i < pi->nqsets; i++, q++)
2681                 q->rspq.adaptive_rx = adaptive_rx;
2682
2683         return 0;
2684 }
2685
2686 static int get_adaptive_rx_setting(struct net_device *dev)
2687 {
2688         struct port_info *pi = netdev_priv(dev);
2689         struct adapter *adap = pi->adapter;
2690         struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
2691
2692         return q->rspq.adaptive_rx;
2693 }
2694
2695 static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2696 {
2697         set_adaptive_rx_setting(dev, c->use_adaptive_rx_coalesce);
2698         return set_rx_intr_params(dev, c->rx_coalesce_usecs,
2699                                   c->rx_max_coalesced_frames);
2700 }
2701
2702 static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2703 {
2704         const struct port_info *pi = netdev_priv(dev);
2705         const struct adapter *adap = pi->adapter;
2706         const struct sge_rspq *rq = &adap->sge.ethrxq[pi->first_qset].rspq;
2707
2708         c->rx_coalesce_usecs = qtimer_val(adap, rq);
2709         c->rx_max_coalesced_frames = (rq->intr_params & QINTR_CNT_EN) ?
2710                 adap->sge.counter_val[rq->pktcnt_idx] : 0;
2711         c->use_adaptive_rx_coalesce = get_adaptive_rx_setting(dev);
2712         return 0;
2713 }
2714
2715 /**
2716  *      eeprom_ptov - translate a physical EEPROM address to virtual
2717  *      @phys_addr: the physical EEPROM address
2718  *      @fn: the PCI function number
2719  *      @sz: size of function-specific area
2720  *
2721  *      Translate a physical EEPROM address to virtual.  The first 1K is
2722  *      accessed through virtual addresses starting at 31K, the rest is
2723  *      accessed through virtual addresses starting at 0.
2724  *
2725  *      The mapping is as follows:
2726  *      [0..1K) -> [31K..32K)
2727  *      [1K..1K+A) -> [31K-A..31K)
2728  *      [1K+A..ES) -> [0..ES-A-1K)
2729  *
2730  *      where A = @fn * @sz, and ES = EEPROM size.
2731  */
2732 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2733 {
2734         fn *= sz;
2735         if (phys_addr < 1024)
2736                 return phys_addr + (31 << 10);
2737         if (phys_addr < 1024 + fn)
2738                 return 31744 - fn + phys_addr - 1024;
2739         if (phys_addr < EEPROMSIZE)
2740                 return phys_addr - 1024 - fn;
2741         return -EINVAL;
2742 }
2743
2744 /*
2745  * The next two routines implement eeprom read/write from physical addresses.
2746  */
2747 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
2748 {
2749         int vaddr = eeprom_ptov(phys_addr, adap->fn, EEPROMPFSIZE);
2750
2751         if (vaddr >= 0)
2752                 vaddr = pci_read_vpd(adap->pdev, vaddr, sizeof(u32), v);
2753         return vaddr < 0 ? vaddr : 0;
2754 }
2755
2756 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
2757 {
2758         int vaddr = eeprom_ptov(phys_addr, adap->fn, EEPROMPFSIZE);
2759
2760         if (vaddr >= 0)
2761                 vaddr = pci_write_vpd(adap->pdev, vaddr, sizeof(u32), &v);
2762         return vaddr < 0 ? vaddr : 0;
2763 }
2764
2765 #define EEPROM_MAGIC 0x38E2F10C
2766
2767 static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
2768                       u8 *data)
2769 {
2770         int i, err = 0;
2771         struct adapter *adapter = netdev2adap(dev);
2772
2773         u8 *buf = kmalloc(EEPROMSIZE, GFP_KERNEL);
2774         if (!buf)
2775                 return -ENOMEM;
2776
2777         e->magic = EEPROM_MAGIC;
2778         for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
2779                 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
2780
2781         if (!err)
2782                 memcpy(data, buf + e->offset, e->len);
2783         kfree(buf);
2784         return err;
2785 }
2786
2787 static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
2788                       u8 *data)
2789 {
2790         u8 *buf;
2791         int err = 0;
2792         u32 aligned_offset, aligned_len, *p;
2793         struct adapter *adapter = netdev2adap(dev);
2794
2795         if (eeprom->magic != EEPROM_MAGIC)
2796                 return -EINVAL;
2797
2798         aligned_offset = eeprom->offset & ~3;
2799         aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
2800
2801         if (adapter->fn > 0) {
2802                 u32 start = 1024 + adapter->fn * EEPROMPFSIZE;
2803
2804                 if (aligned_offset < start ||
2805                     aligned_offset + aligned_len > start + EEPROMPFSIZE)
2806                         return -EPERM;
2807         }
2808
2809         if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
2810                 /*
2811                  * RMW possibly needed for first or last words.
2812                  */
2813                 buf = kmalloc(aligned_len, GFP_KERNEL);
2814                 if (!buf)
2815                         return -ENOMEM;
2816                 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
2817                 if (!err && aligned_len > 4)
2818                         err = eeprom_rd_phys(adapter,
2819                                              aligned_offset + aligned_len - 4,
2820                                              (u32 *)&buf[aligned_len - 4]);
2821                 if (err)
2822                         goto out;
2823                 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
2824         } else
2825                 buf = data;
2826
2827         err = t4_seeprom_wp(adapter, false);
2828         if (err)
2829                 goto out;
2830
2831         for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
2832                 err = eeprom_wr_phys(adapter, aligned_offset, *p);
2833                 aligned_offset += 4;
2834         }
2835
2836         if (!err)
2837                 err = t4_seeprom_wp(adapter, true);
2838 out:
2839         if (buf != data)
2840                 kfree(buf);
2841         return err;
2842 }
2843
2844 static int set_flash(struct net_device *netdev, struct ethtool_flash *ef)
2845 {
2846         int ret;
2847         const struct firmware *fw;
2848         struct adapter *adap = netdev2adap(netdev);
2849         unsigned int mbox = PCIE_FW_MASTER_M + 1;
2850
2851         ef->data[sizeof(ef->data) - 1] = '\0';
2852         ret = request_firmware(&fw, ef->data, adap->pdev_dev);
2853         if (ret < 0)
2854                 return ret;
2855
2856         /* If the adapter has been fully initialized then we'll go ahead and
2857          * try to get the firmware's cooperation in upgrading to the new
2858          * firmware image otherwise we'll try to do the entire job from the
2859          * host ... and we always "force" the operation in this path.
2860          */
2861         if (adap->flags & FULL_INIT_DONE)
2862                 mbox = adap->mbox;
2863
2864         ret = t4_fw_upgrade(adap, mbox, fw->data, fw->size, 1);
2865         release_firmware(fw);
2866         if (!ret)
2867                 dev_info(adap->pdev_dev, "loaded firmware %s,"
2868                          " reload cxgb4 driver\n", ef->data);
2869         return ret;
2870 }
2871
2872 #define WOL_SUPPORTED (WAKE_BCAST | WAKE_MAGIC)
2873 #define BCAST_CRC 0xa0ccc1a6
2874
2875 static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2876 {
2877         wol->supported = WAKE_BCAST | WAKE_MAGIC;
2878         wol->wolopts = netdev2adap(dev)->wol;
2879         memset(&wol->sopass, 0, sizeof(wol->sopass));
2880 }
2881
2882 static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2883 {
2884         int err = 0;
2885         struct port_info *pi = netdev_priv(dev);
2886
2887         if (wol->wolopts & ~WOL_SUPPORTED)
2888                 return -EINVAL;
2889         t4_wol_magic_enable(pi->adapter, pi->tx_chan,
2890                             (wol->wolopts & WAKE_MAGIC) ? dev->dev_addr : NULL);
2891         if (wol->wolopts & WAKE_BCAST) {
2892                 err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0xfe, ~0ULL,
2893                                         ~0ULL, 0, false);
2894                 if (!err)
2895                         err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 1,
2896                                                 ~6ULL, ~0ULL, BCAST_CRC, true);
2897         } else
2898                 t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0, 0, 0, 0, false);
2899         return err;
2900 }
2901
2902 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
2903 {
2904         const struct port_info *pi = netdev_priv(dev);
2905         netdev_features_t changed = dev->features ^ features;
2906         int err;
2907
2908         if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
2909                 return 0;
2910
2911         err = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, -1,
2912                             -1, -1, -1,
2913                             !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
2914         if (unlikely(err))
2915                 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
2916         return err;
2917 }
2918
2919 static u32 get_rss_table_size(struct net_device *dev)
2920 {
2921         const struct port_info *pi = netdev_priv(dev);
2922
2923         return pi->rss_size;
2924 }
2925
2926 static int get_rss_table(struct net_device *dev, u32 *p, u8 *key, u8 *hfunc)
2927 {
2928         const struct port_info *pi = netdev_priv(dev);
2929         unsigned int n = pi->rss_size;
2930
2931         if (hfunc)
2932                 *hfunc = ETH_RSS_HASH_TOP;
2933         if (!p)
2934                 return 0;
2935         while (n--)
2936                 p[n] = pi->rss[n];
2937         return 0;
2938 }
2939
2940 static int set_rss_table(struct net_device *dev, const u32 *p, const u8 *key,
2941                          const u8 hfunc)
2942 {
2943         unsigned int i;
2944         struct port_info *pi = netdev_priv(dev);
2945
2946         /* We require at least one supported parameter to be changed and no
2947          * change in any of the unsupported parameters
2948          */
2949         if (key ||
2950             (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
2951                 return -EOPNOTSUPP;
2952         if (!p)
2953                 return 0;
2954
2955         for (i = 0; i < pi->rss_size; i++)
2956                 pi->rss[i] = p[i];
2957         if (pi->adapter->flags & FULL_INIT_DONE)
2958                 return write_rss(pi, pi->rss);
2959         return 0;
2960 }
2961
2962 static int get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2963                      u32 *rules)
2964 {
2965         const struct port_info *pi = netdev_priv(dev);
2966
2967         switch (info->cmd) {
2968         case ETHTOOL_GRXFH: {
2969                 unsigned int v = pi->rss_mode;
2970
2971                 info->data = 0;
2972                 switch (info->flow_type) {
2973                 case TCP_V4_FLOW:
2974                         if (v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F)
2975                                 info->data = RXH_IP_SRC | RXH_IP_DST |
2976                                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
2977                         else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F)
2978                                 info->data = RXH_IP_SRC | RXH_IP_DST;
2979                         break;
2980                 case UDP_V4_FLOW:
2981                         if ((v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F) &&
2982                             (v & FW_RSS_VI_CONFIG_CMD_UDPEN_F))
2983                                 info->data = RXH_IP_SRC | RXH_IP_DST |
2984                                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
2985                         else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F)
2986                                 info->data = RXH_IP_SRC | RXH_IP_DST;
2987                         break;
2988                 case SCTP_V4_FLOW:
2989                 case AH_ESP_V4_FLOW:
2990                 case IPV4_FLOW:
2991                         if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F)
2992                                 info->data = RXH_IP_SRC | RXH_IP_DST;
2993                         break;
2994                 case TCP_V6_FLOW:
2995                         if (v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F)
2996                                 info->data = RXH_IP_SRC | RXH_IP_DST |
2997                                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
2998                         else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F)
2999                                 info->data = RXH_IP_SRC | RXH_IP_DST;
3000                         break;
3001                 case UDP_V6_FLOW:
3002                         if ((v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F) &&
3003                             (v & FW_RSS_VI_CONFIG_CMD_UDPEN_F))
3004                                 info->data = RXH_IP_SRC | RXH_IP_DST |
3005                                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
3006                         else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F)
3007                                 info->data = RXH_IP_SRC | RXH_IP_DST;
3008                         break;
3009                 case SCTP_V6_FLOW:
3010                 case AH_ESP_V6_FLOW:
3011                 case IPV6_FLOW:
3012                         if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F)
3013                                 info->data = RXH_IP_SRC | RXH_IP_DST;
3014                         break;
3015                 }
3016                 return 0;
3017         }
3018         case ETHTOOL_GRXRINGS:
3019                 info->data = pi->nqsets;
3020                 return 0;
3021         }
3022         return -EOPNOTSUPP;
3023 }
3024
3025 static const struct ethtool_ops cxgb_ethtool_ops = {
3026         .get_settings      = get_settings,
3027         .set_settings      = set_settings,
3028         .get_drvinfo       = get_drvinfo,
3029         .get_msglevel      = get_msglevel,
3030         .set_msglevel      = set_msglevel,
3031         .get_ringparam     = get_sge_param,
3032         .set_ringparam     = set_sge_param,
3033         .get_coalesce      = get_coalesce,
3034         .set_coalesce      = set_coalesce,
3035         .get_eeprom_len    = get_eeprom_len,
3036         .get_eeprom        = get_eeprom,
3037         .set_eeprom        = set_eeprom,
3038         .get_pauseparam    = get_pauseparam,
3039         .set_pauseparam    = set_pauseparam,
3040         .get_link          = ethtool_op_get_link,
3041         .get_strings       = get_strings,
3042         .set_phys_id       = identify_port,
3043         .nway_reset        = restart_autoneg,
3044         .get_sset_count    = get_sset_count,
3045         .get_ethtool_stats = get_stats,
3046         .get_regs_len      = get_regs_len,
3047         .get_regs          = get_regs,
3048         .get_wol           = get_wol,
3049         .set_wol           = set_wol,
3050         .get_rxnfc         = get_rxnfc,
3051         .get_rxfh_indir_size = get_rss_table_size,
3052         .get_rxfh          = get_rss_table,
3053         .set_rxfh          = set_rss_table,
3054         .flash_device      = set_flash,
3055 };
3056
3057 static int setup_debugfs(struct adapter *adap)
3058 {
3059         if (IS_ERR_OR_NULL(adap->debugfs_root))
3060                 return -1;
3061
3062 #ifdef CONFIG_DEBUG_FS
3063         t4_setup_debugfs(adap);
3064 #endif
3065         return 0;
3066 }
3067
3068 /*
3069  * upper-layer driver support
3070  */
3071
3072 /*
3073  * Allocate an active-open TID and set it to the supplied value.
3074  */
3075 int cxgb4_alloc_atid(struct tid_info *t, void *data)
3076 {
3077         int atid = -1;
3078
3079         spin_lock_bh(&t->atid_lock);
3080         if (t->afree) {
3081                 union aopen_entry *p = t->afree;
3082
3083                 atid = (p - t->atid_tab) + t->atid_base;
3084                 t->afree = p->next;
3085                 p->data = data;
3086                 t->atids_in_use++;
3087         }
3088         spin_unlock_bh(&t->atid_lock);
3089         return atid;
3090 }
3091 EXPORT_SYMBOL(cxgb4_alloc_atid);
3092
3093 /*
3094  * Release an active-open TID.
3095  */
3096 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
3097 {
3098         union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
3099
3100         spin_lock_bh(&t->atid_lock);
3101         p->next = t->afree;
3102         t->afree = p;
3103         t->atids_in_use--;
3104         spin_unlock_bh(&t->atid_lock);
3105 }
3106 EXPORT_SYMBOL(cxgb4_free_atid);
3107
3108 /*
3109  * Allocate a server TID and set it to the supplied value.
3110  */
3111 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
3112 {
3113         int stid;
3114
3115         spin_lock_bh(&t->stid_lock);
3116         if (family == PF_INET) {
3117                 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
3118                 if (stid < t->nstids)
3119                         __set_bit(stid, t->stid_bmap);
3120                 else
3121                         stid = -1;
3122         } else {
3123                 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 2);
3124                 if (stid < 0)
3125                         stid = -1;
3126         }
3127         if (stid >= 0) {
3128                 t->stid_tab[stid].data = data;
3129                 stid += t->stid_base;
3130                 /* IPv6 requires max of 520 bits or 16 cells in TCAM
3131                  * This is equivalent to 4 TIDs. With CLIP enabled it
3132                  * needs 2 TIDs.
3133                  */
3134                 if (family == PF_INET)
3135                         t->stids_in_use++;
3136                 else
3137                         t->stids_in_use += 4;
3138         }
3139         spin_unlock_bh(&t->stid_lock);
3140         return stid;
3141 }
3142 EXPORT_SYMBOL(cxgb4_alloc_stid);
3143
3144 /* Allocate a server filter TID and set it to the supplied value.
3145  */
3146 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
3147 {
3148         int stid;
3149
3150         spin_lock_bh(&t->stid_lock);
3151         if (family == PF_INET) {
3152                 stid = find_next_zero_bit(t->stid_bmap,
3153                                 t->nstids + t->nsftids, t->nstids);
3154                 if (stid < (t->nstids + t->nsftids))
3155                         __set_bit(stid, t->stid_bmap);
3156                 else
3157                         stid = -1;
3158         } else {
3159                 stid = -1;
3160         }
3161         if (stid >= 0) {
3162                 t->stid_tab[stid].data = data;
3163                 stid -= t->nstids;
3164                 stid += t->sftid_base;
3165                 t->stids_in_use++;
3166         }
3167         spin_unlock_bh(&t->stid_lock);
3168         return stid;
3169 }
3170 EXPORT_SYMBOL(cxgb4_alloc_sftid);
3171
3172 /* Release a server TID.
3173  */
3174 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
3175 {
3176         /* Is it a server filter TID? */
3177         if (t->nsftids && (stid >= t->sftid_base)) {
3178                 stid -= t->sftid_base;
3179                 stid += t->nstids;
3180         } else {
3181                 stid -= t->stid_base;
3182         }
3183
3184         spin_lock_bh(&t->stid_lock);
3185         if (family == PF_INET)
3186                 __clear_bit(stid, t->stid_bmap);
3187         else
3188                 bitmap_release_region(t->stid_bmap, stid, 2);
3189         t->stid_tab[stid].data = NULL;
3190         if (family == PF_INET)
3191                 t->stids_in_use--;
3192         else
3193                 t->stids_in_use -= 4;
3194         spin_unlock_bh(&t->stid_lock);
3195 }
3196 EXPORT_SYMBOL(cxgb4_free_stid);
3197
3198 /*
3199  * Populate a TID_RELEASE WR.  Caller must properly size the skb.
3200  */
3201 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
3202                            unsigned int tid)
3203 {
3204         struct cpl_tid_release *req;
3205
3206         set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
3207         req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
3208         INIT_TP_WR(req, tid);
3209         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
3210 }
3211
3212 /*
3213  * Queue a TID release request and if necessary schedule a work queue to
3214  * process it.
3215  */
3216 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
3217                                     unsigned int tid)
3218 {
3219         void **p = &t->tid_tab[tid];
3220         struct adapter *adap = container_of(t, struct adapter, tids);
3221
3222         spin_lock_bh(&adap->tid_release_lock);
3223         *p = adap->tid_release_head;
3224         /* Low 2 bits encode the Tx channel number */
3225         adap->tid_release_head = (void **)((uintptr_t)p | chan);
3226         if (!adap->tid_release_task_busy) {
3227                 adap->tid_release_task_busy = true;
3228                 queue_work(adap->workq, &adap->tid_release_task);
3229         }
3230         spin_unlock_bh(&adap->tid_release_lock);
3231 }
3232
3233 /*
3234  * Process the list of pending TID release requests.
3235  */
3236 static void process_tid_release_list(struct work_struct *work)
3237 {
3238         struct sk_buff *skb;
3239         struct adapter *adap;
3240
3241         adap = container_of(work, struct adapter, tid_release_task);
3242
3243         spin_lock_bh(&adap->tid_release_lock);
3244         while (adap->tid_release_head) {
3245                 void **p = adap->tid_release_head;
3246                 unsigned int chan = (uintptr_t)p & 3;
3247                 p = (void *)p - chan;
3248
3249                 adap->tid_release_head = *p;
3250                 *p = NULL;
3251                 spin_unlock_bh(&adap->tid_release_lock);
3252
3253                 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
3254                                          GFP_KERNEL)))
3255                         schedule_timeout_uninterruptible(1);
3256
3257                 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
3258                 t4_ofld_send(adap, skb);
3259                 spin_lock_bh(&adap->tid_release_lock);
3260         }
3261         adap->tid_release_task_busy = false;
3262         spin_unlock_bh(&adap->tid_release_lock);
3263 }
3264
3265 /*
3266  * Release a TID and inform HW.  If we are unable to allocate the release
3267  * message we defer to a work queue.
3268  */
3269 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
3270 {
3271         void *old;
3272         struct sk_buff *skb;
3273         struct adapter *adap = container_of(t, struct adapter, tids);
3274
3275         old = t->tid_tab[tid];
3276         skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
3277         if (likely(skb)) {
3278                 t->tid_tab[tid] = NULL;
3279                 mk_tid_release(skb, chan, tid);
3280                 t4_ofld_send(adap, skb);
3281         } else
3282                 cxgb4_queue_tid_release(t, chan, tid);
3283         if (old)
3284                 atomic_dec(&t->tids_in_use);
3285 }
3286 EXPORT_SYMBOL(cxgb4_remove_tid);
3287
3288 /*
3289  * Allocate and initialize the TID tables.  Returns 0 on success.
3290  */
3291 static int tid_init(struct tid_info *t)
3292 {
3293         size_t size;
3294         unsigned int stid_bmap_size;
3295         unsigned int natids = t->natids;
3296         struct adapter *adap = container_of(t, struct adapter, tids);
3297
3298         stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
3299         size = t->ntids * sizeof(*t->tid_tab) +
3300                natids * sizeof(*t->atid_tab) +
3301                t->nstids * sizeof(*t->stid_tab) +
3302                t->nsftids * sizeof(*t->stid_tab) +
3303                stid_bmap_size * sizeof(long) +
3304                t->nftids * sizeof(*t->ftid_tab) +
3305                t->nsftids * sizeof(*t->ftid_tab);
3306
3307         t->tid_tab = t4_alloc_mem(size);
3308         if (!t->tid_tab)
3309                 return -ENOMEM;
3310
3311         t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
3312         t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
3313         t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
3314         t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
3315         spin_lock_init(&t->stid_lock);
3316         spin_lock_init(&t->atid_lock);
3317
3318         t->stids_in_use = 0;
3319         t->afree = NULL;
3320         t->atids_in_use = 0;
3321         atomic_set(&t->tids_in_use, 0);
3322
3323         /* Setup the free list for atid_tab and clear the stid bitmap. */
3324         if (natids) {
3325                 while (--natids)
3326                         t->atid_tab[natids - 1].next = &t->atid_tab[natids];
3327                 t->afree = t->atid_tab;
3328         }
3329         bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
3330         /* Reserve stid 0 for T4/T5 adapters */
3331         if (!t->stid_base &&
3332             (is_t4(adap->params.chip) || is_t5(adap->params.chip)))
3333                 __set_bit(0, t->stid_bmap);
3334
3335         return 0;
3336 }
3337
3338 int cxgb4_clip_get(const struct net_device *dev,
3339                    const struct in6_addr *lip)
3340 {
3341         struct adapter *adap;
3342         struct fw_clip_cmd c;
3343
3344         adap = netdev2adap(dev);
3345         memset(&c, 0, sizeof(c));
3346         c.op_to_write = htonl(FW_CMD_OP_V(FW_CLIP_CMD) |
3347                         FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3348         c.alloc_to_len16 = htonl(FW_CLIP_CMD_ALLOC_F | FW_LEN16(c));
3349         c.ip_hi = *(__be64 *)(lip->s6_addr);
3350         c.ip_lo = *(__be64 *)(lip->s6_addr + 8);
3351         return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, false);
3352 }
3353 EXPORT_SYMBOL(cxgb4_clip_get);
3354
3355 int cxgb4_clip_release(const struct net_device *dev,
3356                        const struct in6_addr *lip)
3357 {
3358         struct adapter *adap;
3359         struct fw_clip_cmd c;
3360
3361         adap = netdev2adap(dev);
3362         memset(&c, 0, sizeof(c));
3363         c.op_to_write = htonl(FW_CMD_OP_V(FW_CLIP_CMD) |
3364                         FW_CMD_REQUEST_F | FW_CMD_READ_F);
3365         c.alloc_to_len16 = htonl(FW_CLIP_CMD_FREE_F | FW_LEN16(c));
3366         c.ip_hi = *(__be64 *)(lip->s6_addr);
3367         c.ip_lo = *(__be64 *)(lip->s6_addr + 8);
3368         return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, false);
3369 }
3370 EXPORT_SYMBOL(cxgb4_clip_release);
3371
3372 /**
3373  *      cxgb4_create_server - create an IP server
3374  *      @dev: the device
3375  *      @stid: the server TID
3376  *      @sip: local IP address to bind server to
3377  *      @sport: the server's TCP port
3378  *      @queue: queue to direct messages from this server to
3379  *
3380  *      Create an IP server for the given port and address.
3381  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
3382  */
3383 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
3384                         __be32 sip, __be16 sport, __be16 vlan,
3385                         unsigned int queue)
3386 {
3387         unsigned int chan;
3388         struct sk_buff *skb;
3389         struct adapter *adap;
3390         struct cpl_pass_open_req *req;
3391         int ret;
3392
3393         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3394         if (!skb)
3395                 return -ENOMEM;
3396
3397         adap = netdev2adap(dev);
3398         req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
3399         INIT_TP_WR(req, 0);
3400         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
3401         req->local_port = sport;
3402         req->peer_port = htons(0);
3403         req->local_ip = sip;
3404         req->peer_ip = htonl(0);
3405         chan = rxq_to_chan(&adap->sge, queue);
3406         req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
3407         req->opt1 = cpu_to_be64(CONN_POLICY_ASK |
3408                                 SYN_RSS_ENABLE | SYN_RSS_QUEUE(queue));
3409         ret = t4_mgmt_tx(adap, skb);
3410         return net_xmit_eval(ret);
3411 }
3412 EXPORT_SYMBOL(cxgb4_create_server);
3413
3414 /*      cxgb4_create_server6 - create an IPv6 server
3415  *      @dev: the device
3416  *      @stid: the server TID
3417  *      @sip: local IPv6 address to bind server to
3418  *      @sport: the server's TCP port
3419  *      @queue: queue to direct messages from this server to
3420  *
3421  *      Create an IPv6 server for the given port and address.
3422  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
3423  */
3424 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
3425                          const struct in6_addr *sip, __be16 sport,
3426                          unsigned int queue)
3427 {
3428         unsigned int chan;
3429         struct sk_buff *skb;
3430         struct adapter *adap;
3431         struct cpl_pass_open_req6 *req;
3432         int ret;
3433
3434         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3435         if (!skb)
3436                 return -ENOMEM;
3437
3438         adap = netdev2adap(dev);
3439         req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req));
3440         INIT_TP_WR(req, 0);
3441         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
3442         req->local_port = sport;
3443         req->peer_port = htons(0);
3444         req->local_ip_hi = *(__be64 *)(sip->s6_addr);
3445         req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
3446         req->peer_ip_hi = cpu_to_be64(0);
3447         req->peer_ip_lo = cpu_to_be64(0);
3448         chan = rxq_to_chan(&adap->sge, queue);
3449         req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
3450         req->opt1 = cpu_to_be64(CONN_POLICY_ASK |
3451                                 SYN_RSS_ENABLE | SYN_RSS_QUEUE(queue));
3452         ret = t4_mgmt_tx(adap, skb);
3453         return net_xmit_eval(ret);
3454 }
3455 EXPORT_SYMBOL(cxgb4_create_server6);
3456
3457 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
3458                         unsigned int queue, bool ipv6)
3459 {
3460         struct sk_buff *skb;
3461         struct adapter *adap;
3462         struct cpl_close_listsvr_req *req;
3463         int ret;
3464
3465         adap = netdev2adap(dev);
3466
3467         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3468         if (!skb)
3469                 return -ENOMEM;
3470
3471         req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req));
3472         INIT_TP_WR(req, 0);
3473         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
3474         req->reply_ctrl = htons(NO_REPLY(0) | (ipv6 ? LISTSVR_IPV6(1) :
3475                                 LISTSVR_IPV6(0)) | QUEUENO(queue));
3476         ret = t4_mgmt_tx(adap, skb);
3477         return net_xmit_eval(ret);
3478 }
3479 EXPORT_SYMBOL(cxgb4_remove_server);
3480
3481 /**
3482  *      cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
3483  *      @mtus: the HW MTU table
3484  *      @mtu: the target MTU
3485  *      @idx: index of selected entry in the MTU table
3486  *
3487  *      Returns the index and the value in the HW MTU table that is closest to
3488  *      but does not exceed @mtu, unless @mtu is smaller than any value in the
3489  *      table, in which case that smallest available value is selected.
3490  */
3491 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
3492                             unsigned int *idx)
3493 {
3494         unsigned int i = 0;
3495
3496         while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
3497                 ++i;
3498         if (idx)
3499                 *idx = i;
3500         return mtus[i];
3501 }
3502 EXPORT_SYMBOL(cxgb4_best_mtu);
3503
3504 /**
3505  *     cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
3506  *     @mtus: the HW MTU table
3507  *     @header_size: Header Size
3508  *     @data_size_max: maximum Data Segment Size
3509  *     @data_size_align: desired Data Segment Size Alignment (2^N)
3510  *     @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
3511  *
3512  *     Similar to cxgb4_best_mtu() but instead of searching the Hardware
3513  *     MTU Table based solely on a Maximum MTU parameter, we break that
3514  *     parameter up into a Header Size and Maximum Data Segment Size, and
3515  *     provide a desired Data Segment Size Alignment.  If we find an MTU in
3516  *     the Hardware MTU Table which will result in a Data Segment Size with
3517  *     the requested alignment _and_ that MTU isn't "too far" from the
3518  *     closest MTU, then we'll return that rather than the closest MTU.
3519  */
3520 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
3521                                     unsigned short header_size,
3522                                     unsigned short data_size_max,
3523                                     unsigned short data_size_align,
3524                                     unsigned int *mtu_idxp)
3525 {
3526         unsigned short max_mtu = header_size + data_size_max;
3527         unsigned short data_size_align_mask = data_size_align - 1;
3528         int mtu_idx, aligned_mtu_idx;
3529
3530         /* Scan the MTU Table till we find an MTU which is larger than our
3531          * Maximum MTU or we reach the end of the table.  Along the way,
3532          * record the last MTU found, if any, which will result in a Data
3533          * Segment Length matching the requested alignment.
3534          */
3535         for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
3536                 unsigned short data_size = mtus[mtu_idx] - header_size;
3537
3538                 /* If this MTU minus the Header Size would result in a
3539                  * Data Segment Size of the desired alignment, remember it.
3540                  */
3541                 if ((data_size & data_size_align_mask) == 0)
3542                         aligned_mtu_idx = mtu_idx;
3543
3544                 /* If we're not at the end of the Hardware MTU Table and the
3545                  * next element is larger than our Maximum MTU, drop out of
3546                  * the loop.
3547                  */
3548                 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
3549                         break;
3550         }
3551
3552         /* If we fell out of the loop because we ran to the end of the table,
3553          * then we just have to use the last [largest] entry.
3554          */
3555         if (mtu_idx == NMTUS)
3556                 mtu_idx--;
3557
3558         /* If we found an MTU which resulted in the requested Data Segment
3559          * Length alignment and that's "not far" from the largest MTU which is
3560          * less than or equal to the maximum MTU, then use that.
3561          */
3562         if (aligned_mtu_idx >= 0 &&
3563             mtu_idx - aligned_mtu_idx <= 1)
3564                 mtu_idx = aligned_mtu_idx;
3565
3566         /* If the caller has passed in an MTU Index pointer, pass the
3567          * MTU Index back.  Return the MTU value.
3568          */
3569         if (mtu_idxp)
3570                 *mtu_idxp = mtu_idx;
3571         return mtus[mtu_idx];
3572 }
3573 EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
3574
3575 /**
3576  *      cxgb4_port_chan - get the HW channel of a port
3577  *      @dev: the net device for the port
3578  *
3579  *      Return the HW Tx channel of the given port.
3580  */
3581 unsigned int cxgb4_port_chan(const struct net_device *dev)
3582 {
3583         return netdev2pinfo(dev)->tx_chan;
3584 }
3585 EXPORT_SYMBOL(cxgb4_port_chan);
3586
3587 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
3588 {
3589         struct adapter *adap = netdev2adap(dev);
3590         u32 v1, v2, lp_count, hp_count;
3591
3592         v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
3593         v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
3594         if (is_t4(adap->params.chip)) {
3595                 lp_count = G_LP_COUNT(v1);
3596                 hp_count = G_HP_COUNT(v1);
3597         } else {
3598                 lp_count = G_LP_COUNT_T5(v1);
3599                 hp_count = G_HP_COUNT_T5(v2);
3600         }
3601         return lpfifo ? lp_count : hp_count;
3602 }
3603 EXPORT_SYMBOL(cxgb4_dbfifo_count);
3604
3605 /**
3606  *      cxgb4_port_viid - get the VI id of a port
3607  *      @dev: the net device for the port
3608  *
3609  *      Return the VI id of the given port.
3610  */
3611 unsigned int cxgb4_port_viid(const struct net_device *dev)
3612 {
3613         return netdev2pinfo(dev)->viid;
3614 }
3615 EXPORT_SYMBOL(cxgb4_port_viid);
3616
3617 /**
3618  *      cxgb4_port_idx - get the index of a port
3619  *      @dev: the net device for the port
3620  *
3621  *      Return the index of the given port.
3622  */
3623 unsigned int cxgb4_port_idx(const struct net_device *dev)
3624 {
3625         return netdev2pinfo(dev)->port_id;
3626 }
3627 EXPORT_SYMBOL(cxgb4_port_idx);
3628
3629 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
3630                          struct tp_tcp_stats *v6)
3631 {
3632         struct adapter *adap = pci_get_drvdata(pdev);
3633
3634         spin_lock(&adap->stats_lock);
3635         t4_tp_get_tcp_stats(adap, v4, v6);
3636         spin_unlock(&adap->stats_lock);
3637 }
3638 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
3639
3640 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
3641                       const unsigned int *pgsz_order)
3642 {
3643         struct adapter *adap = netdev2adap(dev);
3644
3645         t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK, tag_mask);
3646         t4_write_reg(adap, ULP_RX_ISCSI_PSZ, HPZ0(pgsz_order[0]) |
3647                      HPZ1(pgsz_order[1]) | HPZ2(pgsz_order[2]) |
3648                      HPZ3(pgsz_order[3]));
3649 }
3650 EXPORT_SYMBOL(cxgb4_iscsi_init);
3651
3652 int cxgb4_flush_eq_cache(struct net_device *dev)
3653 {
3654         struct adapter *adap = netdev2adap(dev);
3655         int ret;
3656
3657         ret = t4_fwaddrspace_write(adap, adap->mbox,
3658                                    0xe1000000 + A_SGE_CTXT_CMD, 0x20000000);
3659         return ret;
3660 }
3661 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
3662
3663 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
3664 {
3665         u32 addr = t4_read_reg(adap, A_SGE_DBQ_CTXT_BADDR) + 24 * qid + 8;
3666         __be64 indices;
3667         int ret;
3668
3669         spin_lock(&adap->win0_lock);
3670         ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
3671                            sizeof(indices), (__be32 *)&indices,
3672                            T4_MEMORY_READ);
3673         spin_unlock(&adap->win0_lock);
3674         if (!ret) {
3675                 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
3676                 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
3677         }
3678         return ret;
3679 }
3680
3681 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
3682                         u16 size)
3683 {
3684         struct adapter *adap = netdev2adap(dev);
3685         u16 hw_pidx, hw_cidx;
3686         int ret;
3687
3688         ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
3689         if (ret)
3690                 goto out;
3691
3692         if (pidx != hw_pidx) {
3693                 u16 delta;
3694
3695                 if (pidx >= hw_pidx)
3696                         delta = pidx - hw_pidx;
3697                 else
3698                         delta = size - hw_pidx + pidx;
3699                 wmb();
3700                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3701                              QID(qid) | PIDX(delta));
3702         }
3703 out:
3704         return ret;
3705 }
3706 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
3707
3708 void cxgb4_disable_db_coalescing(struct net_device *dev)
3709 {
3710         struct adapter *adap;
3711
3712         adap = netdev2adap(dev);
3713         t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE,
3714                          F_NOCOALESCE);
3715 }
3716 EXPORT_SYMBOL(cxgb4_disable_db_coalescing);
3717
3718 void cxgb4_enable_db_coalescing(struct net_device *dev)
3719 {
3720         struct adapter *adap;
3721
3722         adap = netdev2adap(dev);
3723         t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE, 0);
3724 }
3725 EXPORT_SYMBOL(cxgb4_enable_db_coalescing);
3726
3727 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
3728 {
3729         struct adapter *adap;
3730         u32 offset, memtype, memaddr;
3731         u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
3732         u32 edc0_end, edc1_end, mc0_end, mc1_end;
3733         int ret;
3734
3735         adap = netdev2adap(dev);
3736
3737         offset = ((stag >> 8) * 32) + adap->vres.stag.start;
3738
3739         /* Figure out where the offset lands in the Memory Type/Address scheme.
3740          * This code assumes that the memory is laid out starting at offset 0
3741          * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
3742          * and EDC1.  Some cards will have neither MC0 nor MC1, most cards have
3743          * MC0, and some have both MC0 and MC1.
3744          */
3745         size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
3746         edc0_size = EDRAM0_SIZE_G(size) << 20;
3747         size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
3748         edc1_size = EDRAM1_SIZE_G(size) << 20;
3749         size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
3750         mc0_size = EXT_MEM0_SIZE_G(size) << 20;
3751
3752         edc0_end = edc0_size;
3753         edc1_end = edc0_end + edc1_size;
3754         mc0_end = edc1_end + mc0_size;
3755
3756         if (offset < edc0_end) {
3757                 memtype = MEM_EDC0;
3758                 memaddr = offset;
3759         } else if (offset < edc1_end) {
3760                 memtype = MEM_EDC1;
3761                 memaddr = offset - edc0_end;
3762         } else {
3763                 if (offset < mc0_end) {
3764                         memtype = MEM_MC0;
3765                         memaddr = offset - edc1_end;
3766                 } else if (is_t4(adap->params.chip)) {
3767                         /* T4 only has a single memory channel */
3768                         goto err;
3769                 } else {
3770                         size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
3771                         mc1_size = EXT_MEM1_SIZE_G(size) << 20;
3772                         mc1_end = mc0_end + mc1_size;
3773                         if (offset < mc1_end) {
3774                                 memtype = MEM_MC1;
3775                                 memaddr = offset - mc0_end;
3776                         } else {
3777                                 /* offset beyond the end of any memory */
3778                                 goto err;
3779                         }
3780                 }
3781         }
3782
3783         spin_lock(&adap->win0_lock);
3784         ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
3785         spin_unlock(&adap->win0_lock);
3786         return ret;
3787
3788 err:
3789         dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
3790                 stag, offset);
3791         return -EINVAL;
3792 }
3793 EXPORT_SYMBOL(cxgb4_read_tpte);
3794
3795 u64 cxgb4_read_sge_timestamp(struct net_device *dev)
3796 {
3797         u32 hi, lo;
3798         struct adapter *adap;
3799
3800         adap = netdev2adap(dev);
3801         lo = t4_read_reg(adap, SGE_TIMESTAMP_LO);
3802         hi = GET_TSVAL(t4_read_reg(adap, SGE_TIMESTAMP_HI));
3803
3804         return ((u64)hi << 32) | (u64)lo;
3805 }
3806 EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
3807
3808 int cxgb4_bar2_sge_qregs(struct net_device *dev,
3809                          unsigned int qid,
3810                          enum cxgb4_bar2_qtype qtype,
3811                          u64 *pbar2_qoffset,
3812                          unsigned int *pbar2_qid)
3813 {
3814         return t4_bar2_sge_qregs(netdev2adap(dev),
3815                                  qid,
3816                                  (qtype == CXGB4_BAR2_QTYPE_EGRESS
3817                                   ? T4_BAR2_QTYPE_EGRESS
3818                                   : T4_BAR2_QTYPE_INGRESS),
3819                                  pbar2_qoffset,
3820                                  pbar2_qid);
3821 }
3822 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
3823
3824 static struct pci_driver cxgb4_driver;
3825
3826 static void check_neigh_update(struct neighbour *neigh)
3827 {
3828         const struct device *parent;
3829         const struct net_device *netdev = neigh->dev;
3830
3831         if (netdev->priv_flags & IFF_802_1Q_VLAN)
3832                 netdev = vlan_dev_real_dev(netdev);
3833         parent = netdev->dev.parent;
3834         if (parent && parent->driver == &cxgb4_driver.driver)
3835                 t4_l2t_update(dev_get_drvdata(parent), neigh);
3836 }
3837
3838 static int netevent_cb(struct notifier_block *nb, unsigned long event,
3839                        void *data)
3840 {
3841         switch (event) {
3842         case NETEVENT_NEIGH_UPDATE:
3843                 check_neigh_update(data);
3844                 break;
3845         case NETEVENT_REDIRECT:
3846         default:
3847                 break;
3848         }
3849         return 0;
3850 }
3851
3852 static bool netevent_registered;
3853 static struct notifier_block cxgb4_netevent_nb = {
3854         .notifier_call = netevent_cb
3855 };
3856
3857 static void drain_db_fifo(struct adapter *adap, int usecs)
3858 {
3859         u32 v1, v2, lp_count, hp_count;
3860
3861         do {
3862                 v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
3863                 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
3864                 if (is_t4(adap->params.chip)) {
3865                         lp_count = G_LP_COUNT(v1);
3866                         hp_count = G_HP_COUNT(v1);
3867                 } else {
3868                         lp_count = G_LP_COUNT_T5(v1);
3869                         hp_count = G_HP_COUNT_T5(v2);
3870                 }
3871
3872                 if (lp_count == 0 && hp_count == 0)
3873                         break;
3874                 set_current_state(TASK_UNINTERRUPTIBLE);
3875                 schedule_timeout(usecs_to_jiffies(usecs));
3876         } while (1);
3877 }
3878
3879 static void disable_txq_db(struct sge_txq *q)
3880 {
3881         unsigned long flags;
3882
3883         spin_lock_irqsave(&q->db_lock, flags);
3884         q->db_disabled = 1;
3885         spin_unlock_irqrestore(&q->db_lock, flags);
3886 }
3887
3888 static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
3889 {
3890         spin_lock_irq(&q->db_lock);
3891         if (q->db_pidx_inc) {
3892                 /* Make sure that all writes to the TX descriptors
3893                  * are committed before we tell HW about them.
3894                  */
3895                 wmb();
3896                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3897                              QID(q->cntxt_id) | PIDX(q->db_pidx_inc));
3898                 q->db_pidx_inc = 0;
3899         }
3900         q->db_disabled = 0;
3901         spin_unlock_irq(&q->db_lock);
3902 }
3903
3904 static void disable_dbs(struct adapter *adap)
3905 {
3906         int i;
3907
3908         for_each_ethrxq(&adap->sge, i)
3909                 disable_txq_db(&adap->sge.ethtxq[i].q);
3910         for_each_ofldrxq(&adap->sge, i)
3911                 disable_txq_db(&adap->sge.ofldtxq[i].q);
3912         for_each_port(adap, i)
3913                 disable_txq_db(&adap->sge.ctrlq[i].q);
3914 }
3915
3916 static void enable_dbs(struct adapter *adap)
3917 {
3918         int i;
3919
3920         for_each_ethrxq(&adap->sge, i)
3921                 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
3922         for_each_ofldrxq(&adap->sge, i)
3923                 enable_txq_db(adap, &adap->sge.ofldtxq[i].q);
3924         for_each_port(adap, i)
3925                 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
3926 }
3927
3928 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
3929 {
3930         if (adap->uld_handle[CXGB4_ULD_RDMA])
3931                 ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA],
3932                                 cmd);
3933 }
3934
3935 static void process_db_full(struct work_struct *work)
3936 {
3937         struct adapter *adap;
3938
3939         adap = container_of(work, struct adapter, db_full_task);
3940
3941         drain_db_fifo(adap, dbfifo_drain_delay);
3942         enable_dbs(adap);
3943         notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
3944         t4_set_reg_field(adap, SGE_INT_ENABLE3,
3945                          DBFIFO_HP_INT | DBFIFO_LP_INT,
3946                          DBFIFO_HP_INT | DBFIFO_LP_INT);
3947 }
3948
3949 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
3950 {
3951         u16 hw_pidx, hw_cidx;
3952         int ret;
3953
3954         spin_lock_irq(&q->db_lock);
3955         ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
3956         if (ret)
3957                 goto out;
3958         if (q->db_pidx != hw_pidx) {
3959                 u16 delta;
3960
3961                 if (q->db_pidx >= hw_pidx)
3962                         delta = q->db_pidx - hw_pidx;
3963                 else
3964                         delta = q->size - hw_pidx + q->db_pidx;
3965                 wmb();
3966                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3967                              QID(q->cntxt_id) | PIDX(delta));
3968         }
3969 out:
3970         q->db_disabled = 0;
3971         q->db_pidx_inc = 0;
3972         spin_unlock_irq(&q->db_lock);
3973         if (ret)
3974                 CH_WARN(adap, "DB drop recovery failed.\n");
3975 }
3976 static void recover_all_queues(struct adapter *adap)
3977 {
3978         int i;
3979
3980         for_each_ethrxq(&adap->sge, i)
3981                 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
3982         for_each_ofldrxq(&adap->sge, i)
3983                 sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q);
3984         for_each_port(adap, i)
3985                 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
3986 }
3987
3988 static void process_db_drop(struct work_struct *work)
3989 {
3990         struct adapter *adap;
3991
3992         adap = container_of(work, struct adapter, db_drop_task);
3993
3994         if (is_t4(adap->params.chip)) {
3995                 drain_db_fifo(adap, dbfifo_drain_delay);
3996                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
3997                 drain_db_fifo(adap, dbfifo_drain_delay);
3998                 recover_all_queues(adap);
3999                 drain_db_fifo(adap, dbfifo_drain_delay);
4000                 enable_dbs(adap);
4001                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
4002         } else {
4003                 u32 dropped_db = t4_read_reg(adap, 0x010ac);
4004                 u16 qid = (dropped_db >> 15) & 0x1ffff;
4005                 u16 pidx_inc = dropped_db & 0x1fff;
4006                 u64 bar2_qoffset;
4007                 unsigned int bar2_qid;
4008                 int ret;
4009
4010                 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
4011                                         &bar2_qoffset, &bar2_qid);
4012                 if (ret)
4013                         dev_err(adap->pdev_dev, "doorbell drop recovery: "
4014                                 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
4015                 else
4016                         writel(PIDX_T5(pidx_inc) | QID(bar2_qid),
4017                                adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
4018
4019                 /* Re-enable BAR2 WC */
4020                 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
4021         }
4022
4023         t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_DROPPED_DB, 0);
4024 }
4025
4026 void t4_db_full(struct adapter *adap)
4027 {
4028         if (is_t4(adap->params.chip)) {
4029                 disable_dbs(adap);
4030                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
4031                 t4_set_reg_field(adap, SGE_INT_ENABLE3,
4032                                  DBFIFO_HP_INT | DBFIFO_LP_INT, 0);
4033                 queue_work(adap->workq, &adap->db_full_task);
4034         }
4035 }
4036
4037 void t4_db_dropped(struct adapter *adap)
4038 {
4039         if (is_t4(adap->params.chip)) {
4040                 disable_dbs(adap);
4041                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
4042         }
4043         queue_work(adap->workq, &adap->db_drop_task);
4044 }
4045
4046 static void uld_attach(struct adapter *adap, unsigned int uld)
4047 {
4048         void *handle;
4049         struct cxgb4_lld_info lli;
4050         unsigned short i;
4051
4052         lli.pdev = adap->pdev;
4053         lli.pf = adap->fn;
4054         lli.l2t = adap->l2t;
4055         lli.tids = &adap->tids;
4056         lli.ports = adap->port;
4057         lli.vr = &adap->vres;
4058         lli.mtus = adap->params.mtus;
4059         if (uld == CXGB4_ULD_RDMA) {
4060                 lli.rxq_ids = adap->sge.rdma_rxq;
4061                 lli.ciq_ids = adap->sge.rdma_ciq;
4062                 lli.nrxq = adap->sge.rdmaqs;
4063                 lli.nciq = adap->sge.rdmaciqs;
4064         } else if (uld == CXGB4_ULD_ISCSI) {
4065                 lli.rxq_ids = adap->sge.ofld_rxq;
4066                 lli.nrxq = adap->sge.ofldqsets;
4067         }
4068         lli.ntxq = adap->sge.ofldqsets;
4069         lli.nchan = adap->params.nports;
4070         lli.nports = adap->params.nports;
4071         lli.wr_cred = adap->params.ofldq_wr_cred;
4072         lli.adapter_type = adap->params.chip;
4073         lli.iscsi_iolen = MAXRXDATA_GET(t4_read_reg(adap, TP_PARA_REG2));
4074         lli.cclk_ps = 1000000000 / adap->params.vpd.cclk;
4075         lli.udb_density = 1 << adap->params.sge.eq_qpp;
4076         lli.ucq_density = 1 << adap->params.sge.iq_qpp;
4077         lli.filt_mode = adap->params.tp.vlan_pri_map;
4078         /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
4079         for (i = 0; i < NCHAN; i++)
4080                 lli.tx_modq[i] = i;
4081         lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS);
4082         lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL);
4083         lli.fw_vers = adap->params.fw_vers;
4084         lli.dbfifo_int_thresh = dbfifo_int_thresh;
4085         lli.sge_ingpadboundary = adap->sge.fl_align;
4086         lli.sge_egrstatuspagesize = adap->sge.stat_len;
4087         lli.sge_pktshift = adap->sge.pktshift;
4088         lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
4089         lli.max_ordird_qp = adap->params.max_ordird_qp;
4090         lli.max_ird_adapter = adap->params.max_ird_adapter;
4091         lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
4092
4093         handle = ulds[uld].add(&lli);
4094         if (IS_ERR(handle)) {
4095                 dev_warn(adap->pdev_dev,
4096                          "could not attach to the %s driver, error %ld\n",
4097                          uld_str[uld], PTR_ERR(handle));
4098                 return;
4099         }
4100
4101         adap->uld_handle[uld] = handle;
4102
4103         if (!netevent_registered) {
4104                 register_netevent_notifier(&cxgb4_netevent_nb);
4105                 netevent_registered = true;
4106         }
4107
4108         if (adap->flags & FULL_INIT_DONE)
4109                 ulds[uld].state_change(handle, CXGB4_STATE_UP);
4110 }
4111
4112 static void attach_ulds(struct adapter *adap)
4113 {
4114         unsigned int i;
4115
4116         spin_lock(&adap_rcu_lock);
4117         list_add_tail_rcu(&adap->rcu_node, &adap_rcu_list);
4118         spin_unlock(&adap_rcu_lock);
4119
4120         mutex_lock(&uld_mutex);
4121         list_add_tail(&adap->list_node, &adapter_list);
4122         for (i = 0; i < CXGB4_ULD_MAX; i++)
4123                 if (ulds[i].add)
4124                         uld_attach(adap, i);
4125         mutex_unlock(&uld_mutex);
4126 }
4127
4128 static void detach_ulds(struct adapter *adap)
4129 {
4130         unsigned int i;
4131
4132         mutex_lock(&uld_mutex);
4133         list_del(&adap->list_node);
4134         for (i = 0; i < CXGB4_ULD_MAX; i++)
4135                 if (adap->uld_handle[i]) {
4136                         ulds[i].state_change(adap->uld_handle[i],
4137                                              CXGB4_STATE_DETACH);
4138                         adap->uld_handle[i] = NULL;
4139                 }
4140         if (netevent_registered && list_empty(&adapter_list)) {
4141                 unregister_netevent_notifier(&cxgb4_netevent_nb);
4142                 netevent_registered = false;
4143         }
4144         mutex_unlock(&uld_mutex);
4145
4146         spin_lock(&adap_rcu_lock);
4147         list_del_rcu(&adap->rcu_node);
4148         spin_unlock(&adap_rcu_lock);
4149 }
4150
4151 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
4152 {
4153         unsigned int i;
4154
4155         mutex_lock(&uld_mutex);
4156         for (i = 0; i < CXGB4_ULD_MAX; i++)
4157                 if (adap->uld_handle[i])
4158                         ulds[i].state_change(adap->uld_handle[i], new_state);
4159         mutex_unlock(&uld_mutex);
4160 }
4161
4162 /**
4163  *      cxgb4_register_uld - register an upper-layer driver
4164  *      @type: the ULD type
4165  *      @p: the ULD methods
4166  *
4167  *      Registers an upper-layer driver with this driver and notifies the ULD
4168  *      about any presently available devices that support its type.  Returns
4169  *      %-EBUSY if a ULD of the same type is already registered.
4170  */
4171 int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p)
4172 {
4173         int ret = 0;
4174         struct adapter *adap;
4175
4176         if (type >= CXGB4_ULD_MAX)
4177                 return -EINVAL;
4178         mutex_lock(&uld_mutex);
4179         if (ulds[type].add) {
4180                 ret = -EBUSY;
4181                 goto out;
4182         }
4183         ulds[type] = *p;
4184         list_for_each_entry(adap, &adapter_list, list_node)
4185                 uld_attach(adap, type);
4186 out:    mutex_unlock(&uld_mutex);
4187         return ret;
4188 }
4189 EXPORT_SYMBOL(cxgb4_register_uld);
4190
4191 /**
4192  *      cxgb4_unregister_uld - unregister an upper-layer driver
4193  *      @type: the ULD type
4194  *
4195  *      Unregisters an existing upper-layer driver.
4196  */
4197 int cxgb4_unregister_uld(enum cxgb4_uld type)
4198 {
4199         struct adapter *adap;
4200
4201         if (type >= CXGB4_ULD_MAX)
4202                 return -EINVAL;
4203         mutex_lock(&uld_mutex);
4204         list_for_each_entry(adap, &adapter_list, list_node)
4205                 adap->uld_handle[type] = NULL;
4206         ulds[type].add = NULL;
4207         mutex_unlock(&uld_mutex);
4208         return 0;
4209 }
4210 EXPORT_SYMBOL(cxgb4_unregister_uld);
4211
4212 /* Check if netdev on which event is occured belongs to us or not. Return
4213  * success (true) if it belongs otherwise failure (false).
4214  * Called with rcu_read_lock() held.
4215  */
4216 #if IS_ENABLED(CONFIG_IPV6)
4217 static bool cxgb4_netdev(const struct net_device *netdev)
4218 {
4219         struct adapter *adap;
4220         int i;
4221
4222         list_for_each_entry_rcu(adap, &adap_rcu_list, rcu_node)
4223                 for (i = 0; i < MAX_NPORTS; i++)
4224                         if (adap->port[i] == netdev)
4225                                 return true;
4226         return false;
4227 }
4228
4229 static int clip_add(struct net_device *event_dev, struct inet6_ifaddr *ifa,
4230                     unsigned long event)
4231 {
4232         int ret = NOTIFY_DONE;
4233
4234         rcu_read_lock();
4235         if (cxgb4_netdev(event_dev)) {
4236                 switch (event) {
4237                 case NETDEV_UP:
4238                         ret = cxgb4_clip_get(event_dev, &ifa->addr);
4239                         if (ret < 0) {
4240                                 rcu_read_unlock();
4241                                 return ret;
4242                         }
4243                         ret = NOTIFY_OK;
4244                         break;
4245                 case NETDEV_DOWN:
4246                         cxgb4_clip_release(event_dev, &ifa->addr);
4247                         ret = NOTIFY_OK;
4248                         break;
4249                 default:
4250                         break;
4251                 }
4252         }
4253         rcu_read_unlock();
4254         return ret;
4255 }
4256
4257 static int cxgb4_inet6addr_handler(struct notifier_block *this,
4258                 unsigned long event, void *data)
4259 {
4260         struct inet6_ifaddr *ifa = data;
4261         struct net_device *event_dev;
4262         int ret = NOTIFY_DONE;
4263         struct bonding *bond = netdev_priv(ifa->idev->dev);
4264         struct list_head *iter;
4265         struct slave *slave;
4266         struct pci_dev *first_pdev = NULL;
4267
4268         if (ifa->idev->dev->priv_flags & IFF_802_1Q_VLAN) {
4269                 event_dev = vlan_dev_real_dev(ifa->idev->dev);
4270                 ret = clip_add(event_dev, ifa, event);
4271         } else if (ifa->idev->dev->flags & IFF_MASTER) {
4272                 /* It is possible that two different adapters are bonded in one
4273                  * bond. We need to find such different adapters and add clip
4274                  * in all of them only once.
4275                  */
4276                 bond_for_each_slave(bond, slave, iter) {
4277                         if (!first_pdev) {
4278                                 ret = clip_add(slave->dev, ifa, event);
4279                                 /* If clip_add is success then only initialize
4280                                  * first_pdev since it means it is our device
4281                                  */
4282                                 if (ret == NOTIFY_OK)
4283                                         first_pdev = to_pci_dev(
4284                                                         slave->dev->dev.parent);
4285                         } else if (first_pdev !=
4286                                    to_pci_dev(slave->dev->dev.parent))
4287                                         ret = clip_add(slave->dev, ifa, event);
4288                 }
4289         } else
4290                 ret = clip_add(ifa->idev->dev, ifa, event);
4291
4292         return ret;
4293 }
4294
4295 static struct notifier_block cxgb4_inet6addr_notifier = {
4296         .notifier_call = cxgb4_inet6addr_handler
4297 };
4298
4299 /* Retrieves IPv6 addresses from a root device (bond, vlan) associated with
4300  * a physical device.
4301  * The physical device reference is needed to send the actul CLIP command.
4302  */
4303 static int update_dev_clip(struct net_device *root_dev, struct net_device *dev)
4304 {
4305         struct inet6_dev *idev = NULL;
4306         struct inet6_ifaddr *ifa;
4307         int ret = 0;
4308
4309         idev = __in6_dev_get(root_dev);
4310         if (!idev)
4311                 return ret;
4312
4313         read_lock_bh(&idev->lock);
4314         list_for_each_entry(ifa, &idev->addr_list, if_list) {
4315                 ret = cxgb4_clip_get(dev, &ifa->addr);
4316                 if (ret < 0)
4317                         break;
4318         }
4319         read_unlock_bh(&idev->lock);
4320
4321         return ret;
4322 }
4323
4324 static int update_root_dev_clip(struct net_device *dev)
4325 {
4326         struct net_device *root_dev = NULL;
4327         int i, ret = 0;
4328
4329         /* First populate the real net device's IPv6 addresses */
4330         ret = update_dev_clip(dev, dev);
4331         if (ret)
4332                 return ret;
4333
4334         /* Parse all bond and vlan devices layered on top of the physical dev */
4335         root_dev = netdev_master_upper_dev_get_rcu(dev);
4336         if (root_dev) {
4337                 ret = update_dev_clip(root_dev, dev);
4338                 if (ret)
4339                         return ret;
4340         }
4341
4342         for (i = 0; i < VLAN_N_VID; i++) {
4343                 root_dev = __vlan_find_dev_deep_rcu(dev, htons(ETH_P_8021Q), i);
4344                 if (!root_dev)
4345                         continue;
4346
4347                 ret = update_dev_clip(root_dev, dev);
4348                 if (ret)
4349                         break;
4350         }
4351         return ret;
4352 }
4353
4354 static void update_clip(const struct adapter *adap)
4355 {
4356         int i;
4357         struct net_device *dev;
4358         int ret;
4359
4360         rcu_read_lock();
4361
4362         for (i = 0; i < MAX_NPORTS; i++) {
4363                 dev = adap->port[i];
4364                 ret = 0;
4365
4366                 if (dev)
4367                         ret = update_root_dev_clip(dev);
4368
4369                 if (ret < 0)
4370                         break;
4371         }
4372         rcu_read_unlock();
4373 }
4374 #endif /* IS_ENABLED(CONFIG_IPV6) */
4375
4376 /**
4377  *      cxgb_up - enable the adapter
4378  *      @adap: adapter being enabled
4379  *
4380  *      Called when the first port is enabled, this function performs the
4381  *      actions necessary to make an adapter operational, such as completing
4382  *      the initialization of HW modules, and enabling interrupts.
4383  *
4384  *      Must be called with the rtnl lock held.
4385  */
4386 static int cxgb_up(struct adapter *adap)
4387 {
4388         int err;
4389
4390         err = setup_sge_queues(adap);
4391         if (err)
4392                 goto out;
4393         err = setup_rss(adap);
4394         if (err)
4395                 goto freeq;
4396
4397         if (adap->flags & USING_MSIX) {
4398                 name_msix_vecs(adap);
4399                 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
4400                                   adap->msix_info[0].desc, adap);
4401                 if (err)
4402                         goto irq_err;
4403
4404                 err = request_msix_queue_irqs(adap);
4405                 if (err) {
4406                         free_irq(adap->msix_info[0].vec, adap);
4407                         goto irq_err;
4408                 }
4409         } else {
4410                 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
4411                                   (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
4412                                   adap->port[0]->name, adap);
4413                 if (err)
4414                         goto irq_err;
4415         }
4416         enable_rx(adap);
4417         t4_sge_start(adap);
4418         t4_intr_enable(adap);
4419         adap->flags |= FULL_INIT_DONE;
4420         notify_ulds(adap, CXGB4_STATE_UP);
4421 #if IS_ENABLED(CONFIG_IPV6)
4422         update_clip(adap);
4423 #endif
4424  out:
4425         return err;
4426  irq_err:
4427         dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
4428  freeq:
4429         t4_free_sge_resources(adap);
4430         goto out;
4431 }
4432
4433 static void cxgb_down(struct adapter *adapter)
4434 {
4435         t4_intr_disable(adapter);
4436         cancel_work_sync(&adapter->tid_release_task);
4437         cancel_work_sync(&adapter->db_full_task);
4438         cancel_work_sync(&adapter->db_drop_task);
4439         adapter->tid_release_task_busy = false;
4440         adapter->tid_release_head = NULL;
4441
4442         if (adapter->flags & USING_MSIX) {
4443                 free_msix_queue_irqs(adapter);
4444                 free_irq(adapter->msix_info[0].vec, adapter);
4445         } else
4446                 free_irq(adapter->pdev->irq, adapter);
4447         quiesce_rx(adapter);
4448         t4_sge_stop(adapter);
4449         t4_free_sge_resources(adapter);
4450         adapter->flags &= ~FULL_INIT_DONE;
4451 }
4452
4453 /*
4454  * net_device operations
4455  */
4456 static int cxgb_open(struct net_device *dev)
4457 {
4458         int err;
4459         struct port_info *pi = netdev_priv(dev);
4460         struct adapter *adapter = pi->adapter;
4461
4462         netif_carrier_off(dev);
4463
4464         if (!(adapter->flags & FULL_INIT_DONE)) {
4465                 err = cxgb_up(adapter);
4466                 if (err < 0)
4467                         return err;
4468         }
4469
4470         err = link_start(dev);
4471         if (!err)
4472                 netif_tx_start_all_queues(dev);
4473         return err;
4474 }
4475
4476 static int cxgb_close(struct net_device *dev)
4477 {
4478         struct port_info *pi = netdev_priv(dev);
4479         struct adapter *adapter = pi->adapter;
4480
4481         netif_tx_stop_all_queues(dev);
4482         netif_carrier_off(dev);
4483         return t4_enable_vi(adapter, adapter->fn, pi->viid, false, false);
4484 }
4485
4486 /* Return an error number if the indicated filter isn't writable ...
4487  */
4488 static int writable_filter(struct filter_entry *f)
4489 {
4490         if (f->locked)
4491                 return -EPERM;
4492         if (f->pending)
4493                 return -EBUSY;
4494
4495         return 0;
4496 }
4497
4498 /* Delete the filter at the specified index (if valid).  The checks for all
4499  * the common problems with doing this like the filter being locked, currently
4500  * pending in another operation, etc.
4501  */
4502 static int delete_filter(struct adapter *adapter, unsigned int fidx)
4503 {
4504         struct filter_entry *f;
4505         int ret;
4506
4507         if (fidx >= adapter->tids.nftids + adapter->tids.nsftids)
4508                 return -EINVAL;
4509
4510         f = &adapter->tids.ftid_tab[fidx];
4511         ret = writable_filter(f);
4512         if (ret)
4513                 return ret;
4514         if (f->valid)
4515                 return del_filter_wr(adapter, fidx);
4516
4517         return 0;
4518 }
4519
4520 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
4521                 __be32 sip, __be16 sport, __be16 vlan,
4522                 unsigned int queue, unsigned char port, unsigned char mask)
4523 {
4524         int ret;
4525         struct filter_entry *f;
4526         struct adapter *adap;
4527         int i;
4528         u8 *val;
4529
4530         adap = netdev2adap(dev);
4531
4532         /* Adjust stid to correct filter index */
4533         stid -= adap->tids.sftid_base;
4534         stid += adap->tids.nftids;
4535
4536         /* Check to make sure the filter requested is writable ...
4537          */
4538         f = &adap->tids.ftid_tab[stid];
4539         ret = writable_filter(f);
4540         if (ret)
4541                 return ret;
4542
4543         /* Clear out any old resources being used by the filter before
4544          * we start constructing the new filter.
4545          */
4546         if (f->valid)
4547                 clear_filter(adap, f);
4548
4549         /* Clear out filter specifications */
4550         memset(&f->fs, 0, sizeof(struct ch_filter_specification));
4551         f->fs.val.lport = cpu_to_be16(sport);
4552         f->fs.mask.lport  = ~0;
4553         val = (u8 *)&sip;
4554         if ((val[0] | val[1] | val[2] | val[3]) != 0) {
4555                 for (i = 0; i < 4; i++) {
4556                         f->fs.val.lip[i] = val[i];
4557                         f->fs.mask.lip[i] = ~0;
4558                 }
4559                 if (adap->params.tp.vlan_pri_map & F_PORT) {
4560                         f->fs.val.iport = port;
4561                         f->fs.mask.iport = mask;
4562                 }
4563         }
4564
4565         if (adap->params.tp.vlan_pri_map & F_PROTOCOL) {
4566                 f->fs.val.proto = IPPROTO_TCP;
4567                 f->fs.mask.proto = ~0;
4568         }
4569
4570         f->fs.dirsteer = 1;
4571         f->fs.iq = queue;
4572         /* Mark filter as locked */
4573         f->locked = 1;
4574         f->fs.rpttid = 1;
4575
4576         ret = set_filter_wr(adap, stid);
4577         if (ret) {
4578                 clear_filter(adap, f);
4579                 return ret;
4580         }
4581
4582         return 0;
4583 }
4584 EXPORT_SYMBOL(cxgb4_create_server_filter);
4585
4586 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
4587                 unsigned int queue, bool ipv6)
4588 {
4589         int ret;
4590         struct filter_entry *f;
4591         struct adapter *adap;
4592
4593         adap = netdev2adap(dev);
4594
4595         /* Adjust stid to correct filter index */
4596         stid -= adap->tids.sftid_base;
4597         stid += adap->tids.nftids;
4598
4599         f = &adap->tids.ftid_tab[stid];
4600         /* Unlock the filter */
4601         f->locked = 0;
4602
4603         ret = delete_filter(adap, stid);
4604         if (ret)
4605                 return ret;
4606
4607         return 0;
4608 }
4609 EXPORT_SYMBOL(cxgb4_remove_server_filter);
4610
4611 static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
4612                                                 struct rtnl_link_stats64 *ns)
4613 {
4614         struct port_stats stats;
4615         struct port_info *p = netdev_priv(dev);
4616         struct adapter *adapter = p->adapter;
4617
4618         /* Block retrieving statistics during EEH error
4619          * recovery. Otherwise, the recovery might fail
4620          * and the PCI device will be removed permanently
4621          */
4622         spin_lock(&adapter->stats_lock);
4623         if (!netif_device_present(dev)) {
4624                 spin_unlock(&adapter->stats_lock);
4625                 return ns;
4626         }
4627         t4_get_port_stats(adapter, p->tx_chan, &stats);
4628         spin_unlock(&adapter->stats_lock);
4629
4630         ns->tx_bytes   = stats.tx_octets;
4631         ns->tx_packets = stats.tx_frames;
4632         ns->rx_bytes   = stats.rx_octets;
4633         ns->rx_packets = stats.rx_frames;
4634         ns->multicast  = stats.rx_mcast_frames;
4635
4636         /* detailed rx_errors */
4637         ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
4638                                stats.rx_runt;
4639         ns->rx_over_errors   = 0;
4640         ns->rx_crc_errors    = stats.rx_fcs_err;
4641         ns->rx_frame_errors  = stats.rx_symbol_err;
4642         ns->rx_fifo_errors   = stats.rx_ovflow0 + stats.rx_ovflow1 +
4643                                stats.rx_ovflow2 + stats.rx_ovflow3 +
4644                                stats.rx_trunc0 + stats.rx_trunc1 +
4645                                stats.rx_trunc2 + stats.rx_trunc3;
4646         ns->rx_missed_errors = 0;
4647
4648         /* detailed tx_errors */
4649         ns->tx_aborted_errors   = 0;
4650         ns->tx_carrier_errors   = 0;
4651         ns->tx_fifo_errors      = 0;
4652         ns->tx_heartbeat_errors = 0;
4653         ns->tx_window_errors    = 0;
4654
4655         ns->tx_errors = stats.tx_error_frames;
4656         ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
4657                 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
4658         return ns;
4659 }
4660
4661 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
4662 {
4663         unsigned int mbox;
4664         int ret = 0, prtad, devad;
4665         struct port_info *pi = netdev_priv(dev);
4666         struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
4667
4668         switch (cmd) {
4669         case SIOCGMIIPHY:
4670                 if (pi->mdio_addr < 0)
4671                         return -EOPNOTSUPP;
4672                 data->phy_id = pi->mdio_addr;
4673                 break;
4674         case SIOCGMIIREG:
4675         case SIOCSMIIREG:
4676                 if (mdio_phy_id_is_c45(data->phy_id)) {
4677                         prtad = mdio_phy_id_prtad(data->phy_id);
4678                         devad = mdio_phy_id_devad(data->phy_id);
4679                 } else if (data->phy_id < 32) {
4680                         prtad = data->phy_id;
4681                         devad = 0;
4682                         data->reg_num &= 0x1f;
4683                 } else
4684                         return -EINVAL;
4685
4686                 mbox = pi->adapter->fn;
4687                 if (cmd == SIOCGMIIREG)
4688                         ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
4689                                          data->reg_num, &data->val_out);
4690                 else
4691                         ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
4692                                          data->reg_num, data->val_in);
4693                 break;
4694         default:
4695                 return -EOPNOTSUPP;
4696         }
4697         return ret;
4698 }
4699
4700 static void cxgb_set_rxmode(struct net_device *dev)
4701 {
4702         /* unfortunately we can't return errors to the stack */
4703         set_rxmode(dev, -1, false);
4704 }
4705
4706 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
4707 {
4708         int ret;
4709         struct port_info *pi = netdev_priv(dev);
4710
4711         if (new_mtu < 81 || new_mtu > MAX_MTU)         /* accommodate SACK */
4712                 return -EINVAL;
4713         ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, new_mtu, -1,
4714                             -1, -1, -1, true);
4715         if (!ret)
4716                 dev->mtu = new_mtu;
4717         return ret;
4718 }
4719
4720 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
4721 {
4722         int ret;
4723         struct sockaddr *addr = p;
4724         struct port_info *pi = netdev_priv(dev);
4725
4726         if (!is_valid_ether_addr(addr->sa_data))
4727                 return -EADDRNOTAVAIL;
4728
4729         ret = t4_change_mac(pi->adapter, pi->adapter->fn, pi->viid,
4730                             pi->xact_addr_filt, addr->sa_data, true, true);
4731         if (ret < 0)
4732                 return ret;
4733
4734         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4735         pi->xact_addr_filt = ret;
4736         return 0;
4737 }
4738
4739 #ifdef CONFIG_NET_POLL_CONTROLLER
4740 static void cxgb_netpoll(struct net_device *dev)
4741 {
4742         struct port_info *pi = netdev_priv(dev);
4743         struct adapter *adap = pi->adapter;
4744
4745         if (adap->flags & USING_MSIX) {
4746                 int i;
4747                 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
4748
4749                 for (i = pi->nqsets; i; i--, rx++)
4750                         t4_sge_intr_msix(0, &rx->rspq);
4751         } else
4752                 t4_intr_handler(adap)(0, adap);
4753 }
4754 #endif
4755
4756 static const struct net_device_ops cxgb4_netdev_ops = {
4757         .ndo_open             = cxgb_open,
4758         .ndo_stop             = cxgb_close,
4759         .ndo_start_xmit       = t4_eth_xmit,
4760         .ndo_select_queue     = cxgb_select_queue,
4761         .ndo_get_stats64      = cxgb_get_stats,
4762         .ndo_set_rx_mode      = cxgb_set_rxmode,
4763         .ndo_set_mac_address  = cxgb_set_mac_addr,
4764         .ndo_set_features     = cxgb_set_features,
4765         .ndo_validate_addr    = eth_validate_addr,
4766         .ndo_do_ioctl         = cxgb_ioctl,
4767         .ndo_change_mtu       = cxgb_change_mtu,
4768 #ifdef CONFIG_NET_POLL_CONTROLLER
4769         .ndo_poll_controller  = cxgb_netpoll,
4770 #endif
4771 };
4772
4773 void t4_fatal_err(struct adapter *adap)
4774 {
4775         t4_set_reg_field(adap, SGE_CONTROL, GLOBALENABLE, 0);
4776         t4_intr_disable(adap);
4777         dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
4778 }
4779
4780 /* Return the specified PCI-E Configuration Space register from our Physical
4781  * Function.  We try first via a Firmware LDST Command since we prefer to let
4782  * the firmware own all of these registers, but if that fails we go for it
4783  * directly ourselves.
4784  */
4785 static u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
4786 {
4787         struct fw_ldst_cmd ldst_cmd;
4788         u32 val;
4789         int ret;
4790
4791         /* Construct and send the Firmware LDST Command to retrieve the
4792          * specified PCI-E Configuration Space register.
4793          */
4794         memset(&ldst_cmd, 0, sizeof(ldst_cmd));
4795         ldst_cmd.op_to_addrspace =
4796                 htonl(FW_CMD_OP_V(FW_LDST_CMD) |
4797                       FW_CMD_REQUEST_F |
4798                       FW_CMD_READ_F |
4799                       FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE));
4800         ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));
4801         ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
4802         ldst_cmd.u.pcie.ctrl_to_fn =
4803                 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->fn));
4804         ldst_cmd.u.pcie.r = reg;
4805         ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
4806                          &ldst_cmd);
4807
4808         /* If the LDST Command suucceeded, exctract the returned register
4809          * value.  Otherwise read it directly ourself.
4810          */
4811         if (ret == 0)
4812                 val = ntohl(ldst_cmd.u.pcie.data[0]);
4813         else
4814                 t4_hw_pci_read_cfg4(adap, reg, &val);
4815
4816         return val;
4817 }
4818
4819 static void setup_memwin(struct adapter *adap)
4820 {
4821         u32 mem_win0_base, mem_win1_base, mem_win2_base, mem_win2_aperture;
4822
4823         if (is_t4(adap->params.chip)) {
4824                 u32 bar0;
4825
4826                 /* Truncation intentional: we only read the bottom 32-bits of
4827                  * the 64-bit BAR0/BAR1 ...  We use the hardware backdoor
4828                  * mechanism to read BAR0 instead of using
4829                  * pci_resource_start() because we could be operating from
4830                  * within a Virtual Machine which is trapping our accesses to
4831                  * our Configuration Space and we need to set up the PCI-E
4832                  * Memory Window decoders with the actual addresses which will
4833                  * be coming across the PCI-E link.
4834                  */
4835                 bar0 = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_0);
4836                 bar0 &= PCI_BASE_ADDRESS_MEM_MASK;
4837                 adap->t4_bar0 = bar0;
4838
4839                 mem_win0_base = bar0 + MEMWIN0_BASE;
4840                 mem_win1_base = bar0 + MEMWIN1_BASE;
4841                 mem_win2_base = bar0 + MEMWIN2_BASE;
4842                 mem_win2_aperture = MEMWIN2_APERTURE;
4843         } else {
4844                 /* For T5, only relative offset inside the PCIe BAR is passed */
4845                 mem_win0_base = MEMWIN0_BASE;
4846                 mem_win1_base = MEMWIN1_BASE;
4847                 mem_win2_base = MEMWIN2_BASE_T5;
4848                 mem_win2_aperture = MEMWIN2_APERTURE_T5;
4849         }
4850         t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 0),
4851                      mem_win0_base | BIR(0) |
4852                      WINDOW(ilog2(MEMWIN0_APERTURE) - 10));
4853         t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 1),
4854                      mem_win1_base | BIR(0) |
4855                      WINDOW(ilog2(MEMWIN1_APERTURE) - 10));
4856         t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2),
4857                      mem_win2_base | BIR(0) |
4858                      WINDOW(ilog2(mem_win2_aperture) - 10));
4859         t4_read_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2));
4860 }
4861
4862 static void setup_memwin_rdma(struct adapter *adap)
4863 {
4864         if (adap->vres.ocq.size) {
4865                 u32 start;
4866                 unsigned int sz_kb;
4867
4868                 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
4869                 start &= PCI_BASE_ADDRESS_MEM_MASK;
4870                 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
4871                 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
4872                 t4_write_reg(adap,
4873                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 3),
4874                              start | BIR(1) | WINDOW(ilog2(sz_kb)));
4875                 t4_write_reg(adap,
4876                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3),
4877                              adap->vres.ocq.start);
4878                 t4_read_reg(adap,
4879                             PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3));
4880         }
4881 }
4882
4883 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
4884 {
4885         u32 v;
4886         int ret;
4887
4888         /* get device capabilities */
4889         memset(c, 0, sizeof(*c));
4890         c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4891                                FW_CMD_REQUEST_F | FW_CMD_READ_F);
4892         c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
4893         ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), c);
4894         if (ret < 0)
4895                 return ret;
4896
4897         /* select capabilities we'll be using */
4898         if (c->niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
4899                 if (!vf_acls)
4900                         c->niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
4901                 else
4902                         c->niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
4903         } else if (vf_acls) {
4904                 dev_err(adap->pdev_dev, "virtualization ACLs not supported");
4905                 return ret;
4906         }
4907         c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4908                                FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
4909         ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), NULL);
4910         if (ret < 0)
4911                 return ret;
4912
4913         ret = t4_config_glbl_rss(adap, adap->fn,
4914                                  FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
4915                                  FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
4916                                  FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
4917         if (ret < 0)
4918                 return ret;
4919
4920         ret = t4_cfg_pfvf(adap, adap->fn, adap->fn, 0, MAX_EGRQ, 64, MAX_INGQ,
4921                           0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF, FW_CMD_CAP_PF);
4922         if (ret < 0)
4923                 return ret;
4924
4925         t4_sge_init(adap);
4926
4927         /* tweak some settings */
4928         t4_write_reg(adap, TP_SHIFT_CNT, 0x64f8849);
4929         t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(PAGE_SHIFT - 12));
4930         t4_write_reg(adap, TP_PIO_ADDR, TP_INGRESS_CONFIG);
4931         v = t4_read_reg(adap, TP_PIO_DATA);
4932         t4_write_reg(adap, TP_PIO_DATA, v & ~CSUM_HAS_PSEUDO_HDR);
4933
4934         /* first 4 Tx modulation queues point to consecutive Tx channels */
4935         adap->params.tp.tx_modq_map = 0xE4;
4936         t4_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP,
4937                      V_TX_MOD_QUEUE_REQ_MAP(adap->params.tp.tx_modq_map));
4938
4939         /* associate each Tx modulation queue with consecutive Tx channels */
4940         v = 0x84218421;
4941         t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
4942                           &v, 1, A_TP_TX_SCHED_HDR);
4943         t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
4944                           &v, 1, A_TP_TX_SCHED_FIFO);
4945         t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
4946                           &v, 1, A_TP_TX_SCHED_PCMD);
4947
4948 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
4949         if (is_offload(adap)) {
4950                 t4_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0,
4951                              V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4952                              V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4953                              V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4954                              V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
4955                 t4_write_reg(adap, A_TP_TX_MOD_CHANNEL_WEIGHT,
4956                              V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4957                              V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4958                              V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4959                              V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
4960         }
4961
4962         /* get basic stuff going */
4963         return t4_early_init(adap, adap->fn);
4964 }
4965
4966 /*
4967  * Max # of ATIDs.  The absolute HW max is 16K but we keep it lower.
4968  */
4969 #define MAX_ATIDS 8192U
4970
4971 /*
4972  * Phase 0 of initialization: contact FW, obtain config, perform basic init.
4973  *
4974  * If the firmware we're dealing with has Configuration File support, then
4975  * we use that to perform all configuration
4976  */
4977
4978 /*
4979  * Tweak configuration based on module parameters, etc.  Most of these have
4980  * defaults assigned to them by Firmware Configuration Files (if we're using
4981  * them) but need to be explicitly set if we're using hard-coded
4982  * initialization.  But even in the case of using Firmware Configuration
4983  * Files, we'd like to expose the ability to change these via module
4984  * parameters so these are essentially common tweaks/settings for
4985  * Configuration Files and hard-coded initialization ...
4986  */
4987 static int adap_init0_tweaks(struct adapter *adapter)
4988 {
4989         /*
4990          * Fix up various Host-Dependent Parameters like Page Size, Cache
4991          * Line Size, etc.  The firmware default is for a 4KB Page Size and
4992          * 64B Cache Line Size ...
4993          */
4994         t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
4995
4996         /*
4997          * Process module parameters which affect early initialization.
4998          */
4999         if (rx_dma_offset != 2 && rx_dma_offset != 0) {
5000                 dev_err(&adapter->pdev->dev,
5001                         "Ignoring illegal rx_dma_offset=%d, using 2\n",
5002                         rx_dma_offset);
5003                 rx_dma_offset = 2;
5004         }
5005         t4_set_reg_field(adapter, SGE_CONTROL,
5006                          PKTSHIFT_MASK,
5007                          PKTSHIFT(rx_dma_offset));
5008
5009         /*
5010          * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
5011          * adds the pseudo header itself.
5012          */
5013         t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG,
5014                                CSUM_HAS_PSEUDO_HDR, 0);
5015
5016         return 0;
5017 }
5018
5019 /*
5020  * Attempt to initialize the adapter via a Firmware Configuration File.
5021  */
5022 static int adap_init0_config(struct adapter *adapter, int reset)
5023 {
5024         struct fw_caps_config_cmd caps_cmd;
5025         const struct firmware *cf;
5026         unsigned long mtype = 0, maddr = 0;
5027         u32 finiver, finicsum, cfcsum;
5028         int ret;
5029         int config_issued = 0;
5030         char *fw_config_file, fw_config_file_path[256];
5031         char *config_name = NULL;
5032
5033         /*
5034          * Reset device if necessary.
5035          */
5036         if (reset) {
5037                 ret = t4_fw_reset(adapter, adapter->mbox,
5038                                   PIORSTMODE | PIORST);
5039                 if (ret < 0)
5040                         goto bye;
5041         }
5042
5043         /*
5044          * If we have a T4 configuration file under /lib/firmware/cxgb4/,
5045          * then use that.  Otherwise, use the configuration file stored
5046          * in the adapter flash ...
5047          */
5048         switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
5049         case CHELSIO_T4:
5050                 fw_config_file = FW4_CFNAME;
5051                 break;
5052         case CHELSIO_T5:
5053                 fw_config_file = FW5_CFNAME;
5054                 break;
5055         default:
5056                 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
5057                        adapter->pdev->device);
5058                 ret = -EINVAL;
5059                 goto bye;
5060         }
5061
5062         ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
5063         if (ret < 0) {
5064                 config_name = "On FLASH";
5065                 mtype = FW_MEMTYPE_CF_FLASH;
5066                 maddr = t4_flash_cfg_addr(adapter);
5067         } else {
5068                 u32 params[7], val[7];
5069
5070                 sprintf(fw_config_file_path,
5071                         "/lib/firmware/%s", fw_config_file);
5072                 config_name = fw_config_file_path;
5073
5074                 if (cf->size >= FLASH_CFG_MAX_SIZE)
5075                         ret = -ENOMEM;
5076                 else {
5077                         params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
5078                              FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
5079                         ret = t4_query_params(adapter, adapter->mbox,
5080                                               adapter->fn, 0, 1, params, val);
5081                         if (ret == 0) {
5082                                 /*
5083                                  * For t4_memory_rw() below addresses and
5084                                  * sizes have to be in terms of multiples of 4
5085                                  * bytes.  So, if the Configuration File isn't
5086                                  * a multiple of 4 bytes in length we'll have
5087                                  * to write that out separately since we can't
5088                                  * guarantee that the bytes following the
5089                                  * residual byte in the buffer returned by
5090                                  * request_firmware() are zeroed out ...
5091                                  */
5092                                 size_t resid = cf->size & 0x3;
5093                                 size_t size = cf->size & ~0x3;
5094                                 __be32 *data = (__be32 *)cf->data;
5095
5096                                 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
5097                                 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
5098
5099                                 spin_lock(&adapter->win0_lock);
5100                                 ret = t4_memory_rw(adapter, 0, mtype, maddr,
5101                                                    size, data, T4_MEMORY_WRITE);
5102                                 if (ret == 0 && resid != 0) {
5103                                         union {
5104                                                 __be32 word;
5105                                                 char buf[4];
5106                                         } last;
5107                                         int i;
5108
5109                                         last.word = data[size >> 2];
5110                                         for (i = resid; i < 4; i++)
5111                                                 last.buf[i] = 0;
5112                                         ret = t4_memory_rw(adapter, 0, mtype,
5113                                                            maddr + size,
5114                                                            4, &last.word,
5115                                                            T4_MEMORY_WRITE);
5116                                 }
5117                                 spin_unlock(&adapter->win0_lock);
5118                         }
5119                 }
5120
5121                 release_firmware(cf);
5122                 if (ret)
5123                         goto bye;
5124         }
5125
5126         /*
5127          * Issue a Capability Configuration command to the firmware to get it
5128          * to parse the Configuration File.  We don't use t4_fw_config_file()
5129          * because we want the ability to modify various features after we've
5130          * processed the configuration file ...
5131          */
5132         memset(&caps_cmd, 0, sizeof(caps_cmd));
5133         caps_cmd.op_to_write =
5134                 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
5135                       FW_CMD_REQUEST_F |
5136                       FW_CMD_READ_F);
5137         caps_cmd.cfvalid_to_len16 =
5138                 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
5139                       FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
5140                       FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
5141                       FW_LEN16(caps_cmd));
5142         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5143                          &caps_cmd);
5144
5145         /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
5146          * Configuration File in FLASH), our last gasp effort is to use the
5147          * Firmware Configuration File which is embedded in the firmware.  A
5148          * very few early versions of the firmware didn't have one embedded
5149          * but we can ignore those.
5150          */
5151         if (ret == -ENOENT) {
5152                 memset(&caps_cmd, 0, sizeof(caps_cmd));
5153                 caps_cmd.op_to_write =
5154                         htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
5155                                         FW_CMD_REQUEST_F |
5156                                         FW_CMD_READ_F);
5157                 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5158                 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
5159                                 sizeof(caps_cmd), &caps_cmd);
5160                 config_name = "Firmware Default";
5161         }
5162
5163         config_issued = 1;
5164         if (ret < 0)
5165                 goto bye;
5166
5167         finiver = ntohl(caps_cmd.finiver);
5168         finicsum = ntohl(caps_cmd.finicsum);
5169         cfcsum = ntohl(caps_cmd.cfcsum);
5170         if (finicsum != cfcsum)
5171                 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
5172                          "mismatch: [fini] csum=%#x, computed csum=%#x\n",
5173                          finicsum, cfcsum);
5174
5175         /*
5176          * And now tell the firmware to use the configuration we just loaded.
5177          */
5178         caps_cmd.op_to_write =
5179                 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
5180                       FW_CMD_REQUEST_F |
5181                       FW_CMD_WRITE_F);
5182         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5183         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5184                          NULL);
5185         if (ret < 0)
5186                 goto bye;
5187
5188         /*
5189          * Tweak configuration based on system architecture, module
5190          * parameters, etc.
5191          */
5192         ret = adap_init0_tweaks(adapter);
5193         if (ret < 0)
5194                 goto bye;
5195
5196         /*
5197          * And finally tell the firmware to initialize itself using the
5198          * parameters from the Configuration File.
5199          */
5200         ret = t4_fw_initialize(adapter, adapter->mbox);
5201         if (ret < 0)
5202                 goto bye;
5203
5204         /*
5205          * Return successfully and note that we're operating with parameters
5206          * not supplied by the driver, rather than from hard-wired
5207          * initialization constants burried in the driver.
5208          */
5209         adapter->flags |= USING_SOFT_PARAMS;
5210         dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
5211                  "Configuration File \"%s\", version %#x, computed checksum %#x\n",
5212                  config_name, finiver, cfcsum);
5213         return 0;
5214
5215         /*
5216          * Something bad happened.  Return the error ...  (If the "error"
5217          * is that there's no Configuration File on the adapter we don't
5218          * want to issue a warning since this is fairly common.)
5219          */
5220 bye:
5221         if (config_issued && ret != -ENOENT)
5222                 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
5223                          config_name, -ret);
5224         return ret;
5225 }
5226
5227 /*
5228  * Attempt to initialize the adapter via hard-coded, driver supplied
5229  * parameters ...
5230  */
5231 static int adap_init0_no_config(struct adapter *adapter, int reset)
5232 {
5233         struct sge *s = &adapter->sge;
5234         struct fw_caps_config_cmd caps_cmd;
5235         u32 v;
5236         int i, ret;
5237
5238         /*
5239          * Reset device if necessary
5240          */
5241         if (reset) {
5242                 ret = t4_fw_reset(adapter, adapter->mbox,
5243                                   PIORSTMODE | PIORST);
5244                 if (ret < 0)
5245                         goto bye;
5246         }
5247
5248         /*
5249          * Get device capabilities and select which we'll be using.
5250          */
5251         memset(&caps_cmd, 0, sizeof(caps_cmd));
5252         caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
5253                                      FW_CMD_REQUEST_F | FW_CMD_READ_F);
5254         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5255         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5256                          &caps_cmd);
5257         if (ret < 0)
5258                 goto bye;
5259
5260         if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
5261                 if (!vf_acls)
5262                         caps_cmd.niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
5263                 else
5264                         caps_cmd.niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
5265         } else if (vf_acls) {
5266                 dev_err(adapter->pdev_dev, "virtualization ACLs not supported");
5267                 goto bye;
5268         }
5269         caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
5270                               FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
5271         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5272                          NULL);
5273         if (ret < 0)
5274                 goto bye;
5275
5276         /*
5277          * Tweak configuration based on system architecture, module
5278          * parameters, etc.
5279          */
5280         ret = adap_init0_tweaks(adapter);
5281         if (ret < 0)
5282                 goto bye;
5283
5284         /*
5285          * Select RSS Global Mode we want to use.  We use "Basic Virtual"
5286          * mode which maps each Virtual Interface to its own section of
5287          * the RSS Table and we turn on all map and hash enables ...
5288          */
5289         adapter->flags |= RSS_TNLALLLOOKUP;
5290         ret = t4_config_glbl_rss(adapter, adapter->mbox,
5291                                  FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
5292                                  FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
5293                                  FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F |
5294                                  ((adapter->flags & RSS_TNLALLLOOKUP) ?
5295                                         FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F : 0));
5296         if (ret < 0)
5297                 goto bye;
5298
5299         /*
5300          * Set up our own fundamental resource provisioning ...
5301          */
5302         ret = t4_cfg_pfvf(adapter, adapter->mbox, adapter->fn, 0,
5303                           PFRES_NEQ, PFRES_NETHCTRL,
5304                           PFRES_NIQFLINT, PFRES_NIQ,
5305                           PFRES_TC, PFRES_NVI,
5306                           FW_PFVF_CMD_CMASK_M,
5307                           pfvfres_pmask(adapter, adapter->fn, 0),
5308                           PFRES_NEXACTF,
5309                           PFRES_R_CAPS, PFRES_WX_CAPS);
5310         if (ret < 0)
5311                 goto bye;
5312
5313         /*
5314          * Perform low level SGE initialization.  We need to do this before we
5315          * send the firmware the INITIALIZE command because that will cause
5316          * any other PF Drivers which are waiting for the Master
5317          * Initialization to proceed forward.
5318          */
5319         for (i = 0; i < SGE_NTIMERS - 1; i++)
5320                 s->timer_val[i] = min(intr_holdoff[i], MAX_SGE_TIMERVAL);
5321         s->timer_val[SGE_NTIMERS - 1] = MAX_SGE_TIMERVAL;
5322         s->counter_val[0] = 1;
5323         for (i = 1; i < SGE_NCOUNTERS; i++)
5324                 s->counter_val[i] = min(intr_cnt[i - 1],
5325                                         THRESHOLD_0_GET(THRESHOLD_0_MASK));
5326         t4_sge_init(adapter);
5327
5328 #ifdef CONFIG_PCI_IOV
5329         /*
5330          * Provision resource limits for Virtual Functions.  We currently
5331          * grant them all the same static resource limits except for the Port
5332          * Access Rights Mask which we're assigning based on the PF.  All of
5333          * the static provisioning stuff for both the PF and VF really needs
5334          * to be managed in a persistent manner for each device which the
5335          * firmware controls.
5336          */
5337         {
5338                 int pf, vf;
5339
5340                 for (pf = 0; pf < ARRAY_SIZE(num_vf); pf++) {
5341                         if (num_vf[pf] <= 0)
5342                                 continue;
5343
5344                         /* VF numbering starts at 1! */
5345                         for (vf = 1; vf <= num_vf[pf]; vf++) {
5346                                 ret = t4_cfg_pfvf(adapter, adapter->mbox,
5347                                                   pf, vf,
5348                                                   VFRES_NEQ, VFRES_NETHCTRL,
5349                                                   VFRES_NIQFLINT, VFRES_NIQ,
5350                                                   VFRES_TC, VFRES_NVI,
5351                                                   FW_PFVF_CMD_CMASK_M,
5352                                                   pfvfres_pmask(
5353                                                   adapter, pf, vf),
5354                                                   VFRES_NEXACTF,
5355                                                   VFRES_R_CAPS, VFRES_WX_CAPS);
5356                                 if (ret < 0)
5357                                         dev_warn(adapter->pdev_dev,
5358                                                  "failed to "\
5359                                                  "provision pf/vf=%d/%d; "
5360                                                  "err=%d\n", pf, vf, ret);
5361                         }
5362                 }
5363         }
5364 #endif
5365
5366         /*
5367          * Set up the default filter mode.  Later we'll want to implement this
5368          * via a firmware command, etc. ...  This needs to be done before the
5369          * firmare initialization command ...  If the selected set of fields
5370          * isn't equal to the default value, we'll need to make sure that the
5371          * field selections will fit in the 36-bit budget.
5372          */
5373         if (tp_vlan_pri_map != TP_VLAN_PRI_MAP_DEFAULT) {
5374                 int j, bits = 0;
5375
5376                 for (j = TP_VLAN_PRI_MAP_FIRST; j <= TP_VLAN_PRI_MAP_LAST; j++)
5377                         switch (tp_vlan_pri_map & (1 << j)) {
5378                         case 0:
5379                                 /* compressed filter field not enabled */
5380                                 break;
5381                         case FCOE_MASK:
5382                                 bits +=  1;
5383                                 break;
5384                         case PORT_MASK:
5385                                 bits +=  3;
5386                                 break;
5387                         case VNIC_ID_MASK:
5388                                 bits += 17;
5389                                 break;
5390                         case VLAN_MASK:
5391                                 bits += 17;
5392                                 break;
5393                         case TOS_MASK:
5394                                 bits +=  8;
5395                                 break;
5396                         case PROTOCOL_MASK:
5397                                 bits +=  8;
5398                                 break;
5399                         case ETHERTYPE_MASK:
5400                                 bits += 16;
5401                                 break;
5402                         case MACMATCH_MASK:
5403                                 bits +=  9;
5404                                 break;
5405                         case MPSHITTYPE_MASK:
5406                                 bits +=  3;
5407                                 break;
5408                         case FRAGMENTATION_MASK:
5409                                 bits +=  1;
5410                                 break;
5411                         }
5412
5413                 if (bits > 36) {
5414                         dev_err(adapter->pdev_dev,
5415                                 "tp_vlan_pri_map=%#x needs %d bits > 36;"\
5416                                 " using %#x\n", tp_vlan_pri_map, bits,
5417                                 TP_VLAN_PRI_MAP_DEFAULT);
5418                         tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
5419                 }
5420         }
5421         v = tp_vlan_pri_map;
5422         t4_write_indirect(adapter, TP_PIO_ADDR, TP_PIO_DATA,
5423                           &v, 1, TP_VLAN_PRI_MAP);
5424
5425         /*
5426          * We need Five Tuple Lookup mode to be set in TP_GLOBAL_CONFIG order
5427          * to support any of the compressed filter fields above.  Newer
5428          * versions of the firmware do this automatically but it doesn't hurt
5429          * to set it here.  Meanwhile, we do _not_ need to set Lookup Every
5430          * Packet in TP_INGRESS_CONFIG to support matching non-TCP packets
5431          * since the firmware automatically turns this on and off when we have
5432          * a non-zero number of filters active (since it does have a
5433          * performance impact).
5434          */
5435         if (tp_vlan_pri_map)
5436                 t4_set_reg_field(adapter, TP_GLOBAL_CONFIG,
5437                                  FIVETUPLELOOKUP_MASK,
5438                                  FIVETUPLELOOKUP_MASK);
5439
5440         /*
5441          * Tweak some settings.
5442          */
5443         t4_write_reg(adapter, TP_SHIFT_CNT, SYNSHIFTMAX(6) |
5444                      RXTSHIFTMAXR1(4) | RXTSHIFTMAXR2(15) |
5445                      PERSHIFTBACKOFFMAX(8) | PERSHIFTMAX(8) |
5446                      KEEPALIVEMAXR1(4) | KEEPALIVEMAXR2(9));
5447
5448         /*
5449          * Get basic stuff going by issuing the Firmware Initialize command.
5450          * Note that this _must_ be after all PFVF commands ...
5451          */
5452         ret = t4_fw_initialize(adapter, adapter->mbox);
5453         if (ret < 0)
5454                 goto bye;
5455
5456         /*
5457          * Return successfully!
5458          */
5459         dev_info(adapter->pdev_dev, "Successfully configured using built-in "\
5460                  "driver parameters\n");
5461         return 0;
5462
5463         /*
5464          * Something bad happened.  Return the error ...
5465          */
5466 bye:
5467         return ret;
5468 }
5469
5470 static struct fw_info fw_info_array[] = {
5471         {
5472                 .chip = CHELSIO_T4,
5473                 .fs_name = FW4_CFNAME,
5474                 .fw_mod_name = FW4_FNAME,
5475                 .fw_hdr = {
5476                         .chip = FW_HDR_CHIP_T4,
5477                         .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
5478                         .intfver_nic = FW_INTFVER(T4, NIC),
5479                         .intfver_vnic = FW_INTFVER(T4, VNIC),
5480                         .intfver_ri = FW_INTFVER(T4, RI),
5481                         .intfver_iscsi = FW_INTFVER(T4, ISCSI),
5482                         .intfver_fcoe = FW_INTFVER(T4, FCOE),
5483                 },
5484         }, {
5485                 .chip = CHELSIO_T5,
5486                 .fs_name = FW5_CFNAME,
5487                 .fw_mod_name = FW5_FNAME,
5488                 .fw_hdr = {
5489                         .chip = FW_HDR_CHIP_T5,
5490                         .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
5491                         .intfver_nic = FW_INTFVER(T5, NIC),
5492                         .intfver_vnic = FW_INTFVER(T5, VNIC),
5493                         .intfver_ri = FW_INTFVER(T5, RI),
5494                         .intfver_iscsi = FW_INTFVER(T5, ISCSI),
5495                         .intfver_fcoe = FW_INTFVER(T5, FCOE),
5496                 },
5497         }
5498 };
5499
5500 static struct fw_info *find_fw_info(int chip)
5501 {
5502         int i;
5503
5504         for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
5505                 if (fw_info_array[i].chip == chip)
5506                         return &fw_info_array[i];
5507         }
5508         return NULL;
5509 }
5510
5511 /*
5512  * Phase 0 of initialization: contact FW, obtain config, perform basic init.
5513  */
5514 static int adap_init0(struct adapter *adap)
5515 {
5516         int ret;
5517         u32 v, port_vec;
5518         enum dev_state state;
5519         u32 params[7], val[7];
5520         struct fw_caps_config_cmd caps_cmd;
5521         int reset = 1;
5522
5523         /*
5524          * Contact FW, advertising Master capability (and potentially forcing
5525          * ourselves as the Master PF if our module parameter force_init is
5526          * set).
5527          */
5528         ret = t4_fw_hello(adap, adap->mbox, adap->fn,
5529                           force_init ? MASTER_MUST : MASTER_MAY,
5530                           &state);
5531         if (ret < 0) {
5532                 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
5533                         ret);
5534                 return ret;
5535         }
5536         if (ret == adap->mbox)
5537                 adap->flags |= MASTER_PF;
5538         if (force_init && state == DEV_STATE_INIT)
5539                 state = DEV_STATE_UNINIT;
5540
5541         /*
5542          * If we're the Master PF Driver and the device is uninitialized,
5543          * then let's consider upgrading the firmware ...  (We always want
5544          * to check the firmware version number in order to A. get it for
5545          * later reporting and B. to warn if the currently loaded firmware
5546          * is excessively mismatched relative to the driver.)
5547          */
5548         t4_get_fw_version(adap, &adap->params.fw_vers);
5549         t4_get_tp_version(adap, &adap->params.tp_vers);
5550         if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
5551                 struct fw_info *fw_info;
5552                 struct fw_hdr *card_fw;
5553                 const struct firmware *fw;
5554                 const u8 *fw_data = NULL;
5555                 unsigned int fw_size = 0;
5556
5557                 /* This is the firmware whose headers the driver was compiled
5558                  * against
5559                  */
5560                 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
5561                 if (fw_info == NULL) {
5562                         dev_err(adap->pdev_dev,
5563                                 "unable to get firmware info for chip %d.\n",
5564                                 CHELSIO_CHIP_VERSION(adap->params.chip));
5565                         return -EINVAL;
5566                 }
5567
5568                 /* allocate memory to read the header of the firmware on the
5569                  * card
5570                  */
5571                 card_fw = t4_alloc_mem(sizeof(*card_fw));
5572
5573                 /* Get FW from from /lib/firmware/ */
5574                 ret = request_firmware(&fw, fw_info->fw_mod_name,
5575                                        adap->pdev_dev);
5576                 if (ret < 0) {
5577                         dev_err(adap->pdev_dev,
5578                                 "unable to load firmware image %s, error %d\n",
5579                                 fw_info->fw_mod_name, ret);
5580                 } else {
5581                         fw_data = fw->data;
5582                         fw_size = fw->size;
5583                 }
5584
5585                 /* upgrade FW logic */
5586                 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
5587                                  state, &reset);
5588
5589                 /* Cleaning up */
5590                 if (fw != NULL)
5591                         release_firmware(fw);
5592                 t4_free_mem(card_fw);
5593
5594                 if (ret < 0)
5595                         goto bye;
5596         }
5597
5598         /*
5599          * Grab VPD parameters.  This should be done after we establish a
5600          * connection to the firmware since some of the VPD parameters
5601          * (notably the Core Clock frequency) are retrieved via requests to
5602          * the firmware.  On the other hand, we need these fairly early on
5603          * so we do this right after getting ahold of the firmware.
5604          */
5605         ret = get_vpd_params(adap, &adap->params.vpd);
5606         if (ret < 0)
5607                 goto bye;
5608
5609         /*
5610          * Find out what ports are available to us.  Note that we need to do
5611          * this before calling adap_init0_no_config() since it needs nports
5612          * and portvec ...
5613          */
5614         v =
5615             FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
5616             FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
5617         ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1, &v, &port_vec);
5618         if (ret < 0)
5619                 goto bye;
5620
5621         adap->params.nports = hweight32(port_vec);
5622         adap->params.portvec = port_vec;
5623
5624         /*
5625          * If the firmware is initialized already (and we're not forcing a
5626          * master initialization), note that we're living with existing
5627          * adapter parameters.  Otherwise, it's time to try initializing the
5628          * adapter ...
5629          */
5630         if (state == DEV_STATE_INIT) {
5631                 dev_info(adap->pdev_dev, "Coming up as %s: "\
5632                          "Adapter already initialized\n",
5633                          adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
5634                 adap->flags |= USING_SOFT_PARAMS;
5635         } else {
5636                 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
5637                          "Initializing adapter\n");
5638                 /*
5639                  * If the firmware doesn't support Configuration
5640                  * Files warn user and exit,
5641                  */
5642                 if (ret < 0)
5643                         dev_warn(adap->pdev_dev, "Firmware doesn't support "
5644                                  "configuration file.\n");
5645                 if (force_old_init)
5646                         ret = adap_init0_no_config(adap, reset);
5647                 else {
5648                         /*
5649                          * Find out whether we're dealing with a version of
5650                          * the firmware which has configuration file support.
5651                          */
5652                         params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
5653                                      FW_PARAMS_PARAM_X_V(
5654                                              FW_PARAMS_PARAM_DEV_CF));
5655                         ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1,
5656                                               params, val);
5657
5658                         /*
5659                          * If the firmware doesn't support Configuration
5660                          * Files, use the old Driver-based, hard-wired
5661                          * initialization.  Otherwise, try using the
5662                          * Configuration File support and fall back to the
5663                          * Driver-based initialization if there's no
5664                          * Configuration File found.
5665                          */
5666                         if (ret < 0)
5667                                 ret = adap_init0_no_config(adap, reset);
5668                         else {
5669                                 /*
5670                                  * The firmware provides us with a memory
5671                                  * buffer where we can load a Configuration
5672                                  * File from the host if we want to override
5673                                  * the Configuration File in flash.
5674                                  */
5675
5676                                 ret = adap_init0_config(adap, reset);
5677                                 if (ret == -ENOENT) {
5678                                         dev_info(adap->pdev_dev,
5679                                             "No Configuration File present "
5680                                             "on adapter. Using hard-wired "
5681                                             "configuration parameters.\n");
5682                                         ret = adap_init0_no_config(adap, reset);
5683                                 }
5684                         }
5685                 }
5686                 if (ret < 0) {
5687                         dev_err(adap->pdev_dev,
5688                                 "could not initialize adapter, error %d\n",
5689                                 -ret);
5690                         goto bye;
5691                 }
5692         }
5693
5694         /*
5695          * If we're living with non-hard-coded parameters (either from a
5696          * Firmware Configuration File or values programmed by a different PF
5697          * Driver), give the SGE code a chance to pull in anything that it
5698          * needs ...  Note that this must be called after we retrieve our VPD
5699          * parameters in order to know how to convert core ticks to seconds.
5700          */
5701         if (adap->flags & USING_SOFT_PARAMS) {
5702                 ret = t4_sge_init(adap);
5703                 if (ret < 0)
5704                         goto bye;
5705         }
5706
5707         if (is_bypass_device(adap->pdev->device))
5708                 adap->params.bypass = 1;
5709
5710         /*
5711          * Grab some of our basic fundamental operating parameters.
5712          */
5713 #define FW_PARAM_DEV(param) \
5714         (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
5715         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
5716
5717 #define FW_PARAM_PFVF(param) \
5718         FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
5719         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)|  \
5720         FW_PARAMS_PARAM_Y_V(0) | \
5721         FW_PARAMS_PARAM_Z_V(0)
5722
5723         params[0] = FW_PARAM_PFVF(EQ_START);
5724         params[1] = FW_PARAM_PFVF(L2T_START);
5725         params[2] = FW_PARAM_PFVF(L2T_END);
5726         params[3] = FW_PARAM_PFVF(FILTER_START);
5727         params[4] = FW_PARAM_PFVF(FILTER_END);
5728         params[5] = FW_PARAM_PFVF(IQFLINT_START);
5729         ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params, val);
5730         if (ret < 0)
5731                 goto bye;
5732         adap->sge.egr_start = val[0];
5733         adap->l2t_start = val[1];
5734         adap->l2t_end = val[2];
5735         adap->tids.ftid_base = val[3];
5736         adap->tids.nftids = val[4] - val[3] + 1;
5737         adap->sge.ingr_start = val[5];
5738
5739         /* query params related to active filter region */
5740         params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
5741         params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
5742         ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
5743         /* If Active filter size is set we enable establishing
5744          * offload connection through firmware work request
5745          */
5746         if ((val[0] != val[1]) && (ret >= 0)) {
5747                 adap->flags |= FW_OFLD_CONN;
5748                 adap->tids.aftid_base = val[0];
5749                 adap->tids.aftid_end = val[1];
5750         }
5751
5752         /* If we're running on newer firmware, let it know that we're
5753          * prepared to deal with encapsulated CPL messages.  Older
5754          * firmware won't understand this and we'll just get
5755          * unencapsulated messages ...
5756          */
5757         params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
5758         val[0] = 1;
5759         (void) t4_set_params(adap, adap->mbox, adap->fn, 0, 1, params, val);
5760
5761         /*
5762          * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
5763          * capability.  Earlier versions of the firmware didn't have the
5764          * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
5765          * permission to use ULPTX MEMWRITE DSGL.
5766          */
5767         if (is_t4(adap->params.chip)) {
5768                 adap->params.ulptx_memwrite_dsgl = false;
5769         } else {
5770                 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
5771                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0,
5772                                       1, params, val);
5773                 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
5774         }
5775
5776         /*
5777          * Get device capabilities so we can determine what resources we need
5778          * to manage.
5779          */
5780         memset(&caps_cmd, 0, sizeof(caps_cmd));
5781         caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
5782                                      FW_CMD_REQUEST_F | FW_CMD_READ_F);
5783         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5784         ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
5785                          &caps_cmd);
5786         if (ret < 0)
5787                 goto bye;
5788
5789         if (caps_cmd.ofldcaps) {
5790                 /* query offload-related parameters */
5791                 params[0] = FW_PARAM_DEV(NTID);
5792                 params[1] = FW_PARAM_PFVF(SERVER_START);
5793                 params[2] = FW_PARAM_PFVF(SERVER_END);
5794                 params[3] = FW_PARAM_PFVF(TDDP_START);
5795                 params[4] = FW_PARAM_PFVF(TDDP_END);
5796                 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
5797                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
5798                                       params, val);
5799                 if (ret < 0)
5800                         goto bye;
5801                 adap->tids.ntids = val[0];
5802                 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
5803                 adap->tids.stid_base = val[1];
5804                 adap->tids.nstids = val[2] - val[1] + 1;
5805                 /*
5806                  * Setup server filter region. Divide the availble filter
5807                  * region into two parts. Regular filters get 1/3rd and server
5808                  * filters get 2/3rd part. This is only enabled if workarond
5809                  * path is enabled.
5810                  * 1. For regular filters.
5811                  * 2. Server filter: This are special filters which are used
5812                  * to redirect SYN packets to offload queue.
5813                  */
5814                 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
5815                         adap->tids.sftid_base = adap->tids.ftid_base +
5816                                         DIV_ROUND_UP(adap->tids.nftids, 3);
5817                         adap->tids.nsftids = adap->tids.nftids -
5818                                          DIV_ROUND_UP(adap->tids.nftids, 3);
5819                         adap->tids.nftids = adap->tids.sftid_base -
5820                                                 adap->tids.ftid_base;
5821                 }
5822                 adap->vres.ddp.start = val[3];
5823                 adap->vres.ddp.size = val[4] - val[3] + 1;
5824                 adap->params.ofldq_wr_cred = val[5];
5825
5826                 adap->params.offload = 1;
5827         }
5828         if (caps_cmd.rdmacaps) {
5829                 params[0] = FW_PARAM_PFVF(STAG_START);
5830                 params[1] = FW_PARAM_PFVF(STAG_END);
5831                 params[2] = FW_PARAM_PFVF(RQ_START);
5832                 params[3] = FW_PARAM_PFVF(RQ_END);
5833                 params[4] = FW_PARAM_PFVF(PBL_START);
5834                 params[5] = FW_PARAM_PFVF(PBL_END);
5835                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
5836                                       params, val);
5837                 if (ret < 0)
5838                         goto bye;
5839                 adap->vres.stag.start = val[0];
5840                 adap->vres.stag.size = val[1] - val[0] + 1;
5841                 adap->vres.rq.start = val[2];
5842                 adap->vres.rq.size = val[3] - val[2] + 1;
5843                 adap->vres.pbl.start = val[4];
5844                 adap->vres.pbl.size = val[5] - val[4] + 1;
5845
5846                 params[0] = FW_PARAM_PFVF(SQRQ_START);
5847                 params[1] = FW_PARAM_PFVF(SQRQ_END);
5848                 params[2] = FW_PARAM_PFVF(CQ_START);
5849                 params[3] = FW_PARAM_PFVF(CQ_END);
5850                 params[4] = FW_PARAM_PFVF(OCQ_START);
5851                 params[5] = FW_PARAM_PFVF(OCQ_END);
5852                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params,
5853                                       val);
5854                 if (ret < 0)
5855                         goto bye;
5856                 adap->vres.qp.start = val[0];
5857                 adap->vres.qp.size = val[1] - val[0] + 1;
5858                 adap->vres.cq.start = val[2];
5859                 adap->vres.cq.size = val[3] - val[2] + 1;
5860                 adap->vres.ocq.start = val[4];
5861                 adap->vres.ocq.size = val[5] - val[4] + 1;
5862
5863                 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
5864                 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
5865                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params,
5866                                       val);
5867                 if (ret < 0) {
5868                         adap->params.max_ordird_qp = 8;
5869                         adap->params.max_ird_adapter = 32 * adap->tids.ntids;
5870                         ret = 0;
5871                 } else {
5872                         adap->params.max_ordird_qp = val[0];
5873                         adap->params.max_ird_adapter = val[1];
5874                 }
5875                 dev_info(adap->pdev_dev,
5876                          "max_ordird_qp %d max_ird_adapter %d\n",
5877                          adap->params.max_ordird_qp,
5878                          adap->params.max_ird_adapter);
5879         }
5880         if (caps_cmd.iscsicaps) {
5881                 params[0] = FW_PARAM_PFVF(ISCSI_START);
5882                 params[1] = FW_PARAM_PFVF(ISCSI_END);
5883                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2,
5884                                       params, val);
5885                 if (ret < 0)
5886                         goto bye;
5887                 adap->vres.iscsi.start = val[0];
5888                 adap->vres.iscsi.size = val[1] - val[0] + 1;
5889         }
5890 #undef FW_PARAM_PFVF
5891 #undef FW_PARAM_DEV
5892
5893         /* The MTU/MSS Table is initialized by now, so load their values.  If
5894          * we're initializing the adapter, then we'll make any modifications
5895          * we want to the MTU/MSS Table and also initialize the congestion
5896          * parameters.
5897          */
5898         t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
5899         if (state != DEV_STATE_INIT) {
5900                 int i;
5901
5902                 /* The default MTU Table contains values 1492 and 1500.
5903                  * However, for TCP, it's better to have two values which are
5904                  * a multiple of 8 +/- 4 bytes apart near this popular MTU.
5905                  * This allows us to have a TCP Data Payload which is a
5906                  * multiple of 8 regardless of what combination of TCP Options
5907                  * are in use (always a multiple of 4 bytes) which is
5908                  * important for performance reasons.  For instance, if no
5909                  * options are in use, then we have a 20-byte IP header and a
5910                  * 20-byte TCP header.  In this case, a 1500-byte MSS would
5911                  * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
5912                  * which is not a multiple of 8.  So using an MSS of 1488 in
5913                  * this case results in a TCP Data Payload of 1448 bytes which
5914                  * is a multiple of 8.  On the other hand, if 12-byte TCP Time
5915                  * Stamps have been negotiated, then an MTU of 1500 bytes
5916                  * results in a TCP Data Payload of 1448 bytes which, as
5917                  * above, is a multiple of 8 bytes ...
5918                  */
5919                 for (i = 0; i < NMTUS; i++)
5920                         if (adap->params.mtus[i] == 1492) {
5921                                 adap->params.mtus[i] = 1488;
5922                                 break;
5923                         }
5924
5925                 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
5926                              adap->params.b_wnd);
5927         }
5928         t4_init_sge_params(adap);
5929         t4_init_tp_params(adap);
5930         adap->flags |= FW_OK;
5931         return 0;
5932
5933         /*
5934          * Something bad happened.  If a command timed out or failed with EIO
5935          * FW does not operate within its spec or something catastrophic
5936          * happened to HW/FW, stop issuing commands.
5937          */
5938 bye:
5939         if (ret != -ETIMEDOUT && ret != -EIO)
5940                 t4_fw_bye(adap, adap->mbox);
5941         return ret;
5942 }
5943
5944 /* EEH callbacks */
5945
5946 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
5947                                          pci_channel_state_t state)
5948 {
5949         int i;
5950         struct adapter *adap = pci_get_drvdata(pdev);
5951
5952         if (!adap)
5953                 goto out;
5954
5955         rtnl_lock();
5956         adap->flags &= ~FW_OK;
5957         notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
5958         spin_lock(&adap->stats_lock);
5959         for_each_port(adap, i) {
5960                 struct net_device *dev = adap->port[i];
5961
5962                 netif_device_detach(dev);
5963                 netif_carrier_off(dev);
5964         }
5965         spin_unlock(&adap->stats_lock);
5966         if (adap->flags & FULL_INIT_DONE)
5967                 cxgb_down(adap);
5968         rtnl_unlock();
5969         if ((adap->flags & DEV_ENABLED)) {
5970                 pci_disable_device(pdev);
5971                 adap->flags &= ~DEV_ENABLED;
5972         }
5973 out:    return state == pci_channel_io_perm_failure ?
5974                 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
5975 }
5976
5977 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
5978 {
5979         int i, ret;
5980         struct fw_caps_config_cmd c;
5981         struct adapter *adap = pci_get_drvdata(pdev);
5982
5983         if (!adap) {
5984                 pci_restore_state(pdev);
5985                 pci_save_state(pdev);
5986                 return PCI_ERS_RESULT_RECOVERED;
5987         }
5988
5989         if (!(adap->flags & DEV_ENABLED)) {
5990                 if (pci_enable_device(pdev)) {
5991                         dev_err(&pdev->dev, "Cannot reenable PCI "
5992                                             "device after reset\n");
5993                         return PCI_ERS_RESULT_DISCONNECT;
5994                 }
5995                 adap->flags |= DEV_ENABLED;
5996         }
5997
5998         pci_set_master(pdev);
5999         pci_restore_state(pdev);
6000         pci_save_state(pdev);
6001         pci_cleanup_aer_uncorrect_error_status(pdev);
6002
6003         if (t4_wait_dev_ready(adap->regs) < 0)
6004                 return PCI_ERS_RESULT_DISCONNECT;
6005         if (t4_fw_hello(adap, adap->fn, adap->fn, MASTER_MUST, NULL) < 0)
6006                 return PCI_ERS_RESULT_DISCONNECT;
6007         adap->flags |= FW_OK;
6008         if (adap_init1(adap, &c))
6009                 return PCI_ERS_RESULT_DISCONNECT;
6010
6011         for_each_port(adap, i) {
6012                 struct port_info *p = adap2pinfo(adap, i);
6013
6014                 ret = t4_alloc_vi(adap, adap->fn, p->tx_chan, adap->fn, 0, 1,
6015                                   NULL, NULL);
6016                 if (ret < 0)
6017                         return PCI_ERS_RESULT_DISCONNECT;
6018                 p->viid = ret;
6019                 p->xact_addr_filt = -1;
6020         }
6021
6022         t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
6023                      adap->params.b_wnd);
6024         setup_memwin(adap);
6025         if (cxgb_up(adap))
6026                 return PCI_ERS_RESULT_DISCONNECT;
6027         return PCI_ERS_RESULT_RECOVERED;
6028 }
6029
6030 static void eeh_resume(struct pci_dev *pdev)
6031 {
6032         int i;
6033         struct adapter *adap = pci_get_drvdata(pdev);
6034
6035         if (!adap)
6036                 return;
6037
6038         rtnl_lock();
6039         for_each_port(adap, i) {
6040                 struct net_device *dev = adap->port[i];
6041
6042                 if (netif_running(dev)) {
6043                         link_start(dev);
6044                         cxgb_set_rxmode(dev);
6045                 }
6046                 netif_device_attach(dev);
6047         }
6048         rtnl_unlock();
6049 }
6050
6051 static const struct pci_error_handlers cxgb4_eeh = {
6052         .error_detected = eeh_err_detected,
6053         .slot_reset     = eeh_slot_reset,
6054         .resume         = eeh_resume,
6055 };
6056
6057 static inline bool is_x_10g_port(const struct link_config *lc)
6058 {
6059         return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 ||
6060                (lc->supported & FW_PORT_CAP_SPEED_40G) != 0;
6061 }
6062
6063 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
6064                              unsigned int us, unsigned int cnt,
6065                              unsigned int size, unsigned int iqe_size)
6066 {
6067         q->adap = adap;
6068         set_rspq_intr_params(q, us, cnt);
6069         q->iqe_len = iqe_size;
6070         q->size = size;
6071 }
6072
6073 /*
6074  * Perform default configuration of DMA queues depending on the number and type
6075  * of ports we found and the number of available CPUs.  Most settings can be
6076  * modified by the admin prior to actual use.
6077  */
6078 static void cfg_queues(struct adapter *adap)
6079 {
6080         struct sge *s = &adap->sge;
6081         int i, n10g = 0, qidx = 0;
6082 #ifndef CONFIG_CHELSIO_T4_DCB
6083         int q10g = 0;
6084 #endif
6085         int ciq_size;
6086
6087         for_each_port(adap, i)
6088                 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
6089 #ifdef CONFIG_CHELSIO_T4_DCB
6090         /* For Data Center Bridging support we need to be able to support up
6091          * to 8 Traffic Priorities; each of which will be assigned to its
6092          * own TX Queue in order to prevent Head-Of-Line Blocking.
6093          */
6094         if (adap->params.nports * 8 > MAX_ETH_QSETS) {
6095                 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
6096                         MAX_ETH_QSETS, adap->params.nports * 8);
6097                 BUG_ON(1);
6098         }
6099
6100         for_each_port(adap, i) {
6101                 struct port_info *pi = adap2pinfo(adap, i);
6102
6103                 pi->first_qset = qidx;
6104                 pi->nqsets = 8;
6105                 qidx += pi->nqsets;
6106         }
6107 #else /* !CONFIG_CHELSIO_T4_DCB */
6108         /*
6109          * We default to 1 queue per non-10G port and up to # of cores queues
6110          * per 10G port.
6111          */
6112         if (n10g)
6113                 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
6114         if (q10g > netif_get_num_default_rss_queues())
6115                 q10g = netif_get_num_default_rss_queues();
6116
6117         for_each_port(adap, i) {
6118                 struct port_info *pi = adap2pinfo(adap, i);
6119
6120                 pi->first_qset = qidx;
6121                 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
6122                 qidx += pi->nqsets;
6123         }
6124 #endif /* !CONFIG_CHELSIO_T4_DCB */
6125
6126         s->ethqsets = qidx;
6127         s->max_ethqsets = qidx;   /* MSI-X may lower it later */
6128
6129         if (is_offload(adap)) {
6130                 /*
6131                  * For offload we use 1 queue/channel if all ports are up to 1G,
6132                  * otherwise we divide all available queues amongst the channels
6133                  * capped by the number of available cores.
6134                  */
6135                 if (n10g) {
6136                         i = min_t(int, ARRAY_SIZE(s->ofldrxq),
6137                                   num_online_cpus());
6138                         s->ofldqsets = roundup(i, adap->params.nports);
6139                 } else
6140                         s->ofldqsets = adap->params.nports;
6141                 /* For RDMA one Rx queue per channel suffices */
6142                 s->rdmaqs = adap->params.nports;
6143                 s->rdmaciqs = adap->params.nports;
6144         }
6145
6146         for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
6147                 struct sge_eth_rxq *r = &s->ethrxq[i];
6148
6149                 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
6150                 r->fl.size = 72;
6151         }
6152
6153         for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
6154                 s->ethtxq[i].q.size = 1024;
6155
6156         for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
6157                 s->ctrlq[i].q.size = 512;
6158
6159         for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++)
6160                 s->ofldtxq[i].q.size = 1024;
6161
6162         for (i = 0; i < ARRAY_SIZE(s->ofldrxq); i++) {
6163                 struct sge_ofld_rxq *r = &s->ofldrxq[i];
6164
6165                 init_rspq(adap, &r->rspq, 5, 1, 1024, 64);
6166                 r->rspq.uld = CXGB4_ULD_ISCSI;
6167                 r->fl.size = 72;
6168         }
6169
6170         for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) {
6171                 struct sge_ofld_rxq *r = &s->rdmarxq[i];
6172
6173                 init_rspq(adap, &r->rspq, 5, 1, 511, 64);
6174                 r->rspq.uld = CXGB4_ULD_RDMA;
6175                 r->fl.size = 72;
6176         }
6177
6178         ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids;
6179         if (ciq_size > SGE_MAX_IQ_SIZE) {
6180                 CH_WARN(adap, "CIQ size too small for available IQs\n");
6181                 ciq_size = SGE_MAX_IQ_SIZE;
6182         }
6183
6184         for (i = 0; i < ARRAY_SIZE(s->rdmaciq); i++) {
6185                 struct sge_ofld_rxq *r = &s->rdmaciq[i];
6186
6187                 init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64);
6188                 r->rspq.uld = CXGB4_ULD_RDMA;
6189         }
6190
6191         init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
6192         init_rspq(adap, &s->intrq, 0, 1, 2 * MAX_INGQ, 64);
6193 }
6194
6195 /*
6196  * Reduce the number of Ethernet queues across all ports to at most n.
6197  * n provides at least one queue per port.
6198  */
6199 static void reduce_ethqs(struct adapter *adap, int n)
6200 {
6201         int i;
6202         struct port_info *pi;
6203
6204         while (n < adap->sge.ethqsets)
6205                 for_each_port(adap, i) {
6206                         pi = adap2pinfo(adap, i);
6207                         if (pi->nqsets > 1) {
6208                                 pi->nqsets--;
6209                                 adap->sge.ethqsets--;
6210                                 if (adap->sge.ethqsets <= n)
6211                                         break;
6212                         }
6213                 }
6214
6215         n = 0;
6216         for_each_port(adap, i) {
6217                 pi = adap2pinfo(adap, i);
6218                 pi->first_qset = n;
6219                 n += pi->nqsets;
6220         }
6221 }
6222
6223 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
6224 #define EXTRA_VECS 2
6225
6226 static int enable_msix(struct adapter *adap)
6227 {
6228         int ofld_need = 0;
6229         int i, want, need;
6230         struct sge *s = &adap->sge;
6231         unsigned int nchan = adap->params.nports;
6232         struct msix_entry entries[MAX_INGQ + 1];
6233
6234         for (i = 0; i < ARRAY_SIZE(entries); ++i)
6235                 entries[i].entry = i;
6236
6237         want = s->max_ethqsets + EXTRA_VECS;
6238         if (is_offload(adap)) {
6239                 want += s->rdmaqs + s->rdmaciqs + s->ofldqsets;
6240                 /* need nchan for each possible ULD */
6241                 ofld_need = 3 * nchan;
6242         }
6243 #ifdef CONFIG_CHELSIO_T4_DCB
6244         /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
6245          * each port.
6246          */
6247         need = 8 * adap->params.nports + EXTRA_VECS + ofld_need;
6248 #else
6249         need = adap->params.nports + EXTRA_VECS + ofld_need;
6250 #endif
6251         want = pci_enable_msix_range(adap->pdev, entries, need, want);
6252         if (want < 0)
6253                 return want;
6254
6255         /*
6256          * Distribute available vectors to the various queue groups.
6257          * Every group gets its minimum requirement and NIC gets top
6258          * priority for leftovers.
6259          */
6260         i = want - EXTRA_VECS - ofld_need;
6261         if (i < s->max_ethqsets) {
6262                 s->max_ethqsets = i;
6263                 if (i < s->ethqsets)
6264                         reduce_ethqs(adap, i);
6265         }
6266         if (is_offload(adap)) {
6267                 i = want - EXTRA_VECS - s->max_ethqsets;
6268                 i -= ofld_need - nchan;
6269                 s->ofldqsets = (i / nchan) * nchan;  /* round down */
6270         }
6271         for (i = 0; i < want; ++i)
6272                 adap->msix_info[i].vec = entries[i].vector;
6273
6274         return 0;
6275 }
6276
6277 #undef EXTRA_VECS
6278
6279 static int init_rss(struct adapter *adap)
6280 {
6281         unsigned int i, j;
6282
6283         for_each_port(adap, i) {
6284                 struct port_info *pi = adap2pinfo(adap, i);
6285
6286                 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
6287                 if (!pi->rss)
6288                         return -ENOMEM;
6289                 for (j = 0; j < pi->rss_size; j++)
6290                         pi->rss[j] = ethtool_rxfh_indir_default(j, pi->nqsets);
6291         }
6292         return 0;
6293 }
6294
6295 static void print_port_info(const struct net_device *dev)
6296 {
6297         char buf[80];
6298         char *bufp = buf;
6299         const char *spd = "";
6300         const struct port_info *pi = netdev_priv(dev);
6301         const struct adapter *adap = pi->adapter;
6302
6303         if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
6304                 spd = " 2.5 GT/s";
6305         else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
6306                 spd = " 5 GT/s";
6307         else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
6308                 spd = " 8 GT/s";
6309
6310         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
6311                 bufp += sprintf(bufp, "100/");
6312         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
6313                 bufp += sprintf(bufp, "1000/");
6314         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
6315                 bufp += sprintf(bufp, "10G/");
6316         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
6317                 bufp += sprintf(bufp, "40G/");
6318         if (bufp != buf)
6319                 --bufp;
6320         sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
6321
6322         netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
6323                     adap->params.vpd.id,
6324                     CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
6325                     is_offload(adap) ? "R" : "", adap->params.pci.width, spd,
6326                     (adap->flags & USING_MSIX) ? " MSI-X" :
6327                     (adap->flags & USING_MSI) ? " MSI" : "");
6328         netdev_info(dev, "S/N: %s, P/N: %s\n",
6329                     adap->params.vpd.sn, adap->params.vpd.pn);
6330 }
6331
6332 static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
6333 {
6334         pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
6335 }
6336
6337 /*
6338  * Free the following resources:
6339  * - memory used for tables
6340  * - MSI/MSI-X
6341  * - net devices
6342  * - resources FW is holding for us
6343  */
6344 static void free_some_resources(struct adapter *adapter)
6345 {
6346         unsigned int i;
6347
6348         t4_free_mem(adapter->l2t);
6349         t4_free_mem(adapter->tids.tid_tab);
6350         disable_msi(adapter);
6351
6352         for_each_port(adapter, i)
6353                 if (adapter->port[i]) {
6354                         kfree(adap2pinfo(adapter, i)->rss);
6355                         free_netdev(adapter->port[i]);
6356                 }
6357         if (adapter->flags & FW_OK)
6358                 t4_fw_bye(adapter, adapter->fn);
6359 }
6360
6361 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
6362 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
6363                    NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
6364 #define SEGMENT_SIZE 128
6365
6366 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6367 {
6368         int func, i, err, s_qpp, qpp, num_seg;
6369         struct port_info *pi;
6370         bool highdma = false;
6371         struct adapter *adapter = NULL;
6372         void __iomem *regs;
6373
6374         printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
6375
6376         err = pci_request_regions(pdev, KBUILD_MODNAME);
6377         if (err) {
6378                 /* Just info, some other driver may have claimed the device. */
6379                 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
6380                 return err;
6381         }
6382
6383         err = pci_enable_device(pdev);
6384         if (err) {
6385                 dev_err(&pdev->dev, "cannot enable PCI device\n");
6386                 goto out_release_regions;
6387         }
6388
6389         regs = pci_ioremap_bar(pdev, 0);
6390         if (!regs) {
6391                 dev_err(&pdev->dev, "cannot map device registers\n");
6392                 err = -ENOMEM;
6393                 goto out_disable_device;
6394         }
6395
6396         err = t4_wait_dev_ready(regs);
6397         if (err < 0)
6398                 goto out_unmap_bar0;
6399
6400         /* We control everything through one PF */
6401         func = SOURCEPF_GET(readl(regs + PL_WHOAMI));
6402         if (func != ent->driver_data) {
6403                 iounmap(regs);
6404                 pci_disable_device(pdev);
6405                 pci_save_state(pdev);        /* to restore SR-IOV later */
6406                 goto sriov;
6407         }
6408
6409         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
6410                 highdma = true;
6411                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
6412                 if (err) {
6413                         dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
6414                                 "coherent allocations\n");
6415                         goto out_unmap_bar0;
6416                 }
6417         } else {
6418                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6419                 if (err) {
6420                         dev_err(&pdev->dev, "no usable DMA configuration\n");
6421                         goto out_unmap_bar0;
6422                 }
6423         }
6424
6425         pci_enable_pcie_error_reporting(pdev);
6426         enable_pcie_relaxed_ordering(pdev);
6427         pci_set_master(pdev);
6428         pci_save_state(pdev);
6429
6430         adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
6431         if (!adapter) {
6432                 err = -ENOMEM;
6433                 goto out_unmap_bar0;
6434         }
6435
6436         adapter->workq = create_singlethread_workqueue("cxgb4");
6437         if (!adapter->workq) {
6438                 err = -ENOMEM;
6439                 goto out_free_adapter;
6440         }
6441
6442         /* PCI device has been enabled */
6443         adapter->flags |= DEV_ENABLED;
6444
6445         adapter->regs = regs;
6446         adapter->pdev = pdev;
6447         adapter->pdev_dev = &pdev->dev;
6448         adapter->mbox = func;
6449         adapter->fn = func;
6450         adapter->msg_enable = dflt_msg_enable;
6451         memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
6452
6453         spin_lock_init(&adapter->stats_lock);
6454         spin_lock_init(&adapter->tid_release_lock);
6455         spin_lock_init(&adapter->win0_lock);
6456
6457         INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
6458         INIT_WORK(&adapter->db_full_task, process_db_full);
6459         INIT_WORK(&adapter->db_drop_task, process_db_drop);
6460
6461         err = t4_prep_adapter(adapter);
6462         if (err)
6463                 goto out_free_adapter;
6464
6465
6466         if (!is_t4(adapter->params.chip)) {
6467                 s_qpp = QUEUESPERPAGEPF1 * adapter->fn;
6468                 qpp = 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adapter,
6469                       SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp);
6470                 num_seg = PAGE_SIZE / SEGMENT_SIZE;
6471
6472                 /* Each segment size is 128B. Write coalescing is enabled only
6473                  * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
6474                  * queue is less no of segments that can be accommodated in
6475                  * a page size.
6476                  */
6477                 if (qpp > num_seg) {
6478                         dev_err(&pdev->dev,
6479                                 "Incorrect number of egress queues per page\n");
6480                         err = -EINVAL;
6481                         goto out_free_adapter;
6482                 }
6483                 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
6484                 pci_resource_len(pdev, 2));
6485                 if (!adapter->bar2) {
6486                         dev_err(&pdev->dev, "cannot map device bar2 region\n");
6487                         err = -ENOMEM;
6488                         goto out_free_adapter;
6489                 }
6490         }
6491
6492         setup_memwin(adapter);
6493         err = adap_init0(adapter);
6494         setup_memwin_rdma(adapter);
6495         if (err)
6496                 goto out_unmap_bar;
6497
6498         for_each_port(adapter, i) {
6499                 struct net_device *netdev;
6500
6501                 netdev = alloc_etherdev_mq(sizeof(struct port_info),
6502                                            MAX_ETH_QSETS);
6503                 if (!netdev) {
6504                         err = -ENOMEM;
6505                         goto out_free_dev;
6506                 }
6507
6508                 SET_NETDEV_DEV(netdev, &pdev->dev);
6509
6510                 adapter->port[i] = netdev;
6511                 pi = netdev_priv(netdev);
6512                 pi->adapter = adapter;
6513                 pi->xact_addr_filt = -1;
6514                 pi->port_id = i;
6515                 netdev->irq = pdev->irq;
6516
6517                 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
6518                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6519                         NETIF_F_RXCSUM | NETIF_F_RXHASH |
6520                         NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
6521                 if (highdma)
6522                         netdev->hw_features |= NETIF_F_HIGHDMA;
6523                 netdev->features |= netdev->hw_features;
6524                 netdev->vlan_features = netdev->features & VLAN_FEAT;
6525
6526                 netdev->priv_flags |= IFF_UNICAST_FLT;
6527
6528                 netdev->netdev_ops = &cxgb4_netdev_ops;
6529 #ifdef CONFIG_CHELSIO_T4_DCB
6530                 netdev->dcbnl_ops = &cxgb4_dcb_ops;
6531                 cxgb4_dcb_state_init(netdev);
6532 #endif
6533                 netdev->ethtool_ops = &cxgb_ethtool_ops;
6534         }
6535
6536         pci_set_drvdata(pdev, adapter);
6537
6538         if (adapter->flags & FW_OK) {
6539                 err = t4_port_init(adapter, func, func, 0);
6540                 if (err)
6541                         goto out_free_dev;
6542         }
6543
6544         /*
6545          * Configure queues and allocate tables now, they can be needed as
6546          * soon as the first register_netdev completes.
6547          */
6548         cfg_queues(adapter);
6549
6550         adapter->l2t = t4_init_l2t();
6551         if (!adapter->l2t) {
6552                 /* We tolerate a lack of L2T, giving up some functionality */
6553                 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
6554                 adapter->params.offload = 0;
6555         }
6556
6557         if (is_offload(adapter) && tid_init(&adapter->tids) < 0) {
6558                 dev_warn(&pdev->dev, "could not allocate TID table, "
6559                          "continuing\n");
6560                 adapter->params.offload = 0;
6561         }
6562
6563         /* See what interrupts we'll be using */
6564         if (msi > 1 && enable_msix(adapter) == 0)
6565                 adapter->flags |= USING_MSIX;
6566         else if (msi > 0 && pci_enable_msi(pdev) == 0)
6567                 adapter->flags |= USING_MSI;
6568
6569         err = init_rss(adapter);
6570         if (err)
6571                 goto out_free_dev;
6572
6573         /*
6574          * The card is now ready to go.  If any errors occur during device
6575          * registration we do not fail the whole card but rather proceed only
6576          * with the ports we manage to register successfully.  However we must
6577          * register at least one net device.
6578          */
6579         for_each_port(adapter, i) {
6580                 pi = adap2pinfo(adapter, i);
6581                 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
6582                 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
6583
6584                 err = register_netdev(adapter->port[i]);
6585                 if (err)
6586                         break;
6587                 adapter->chan_map[pi->tx_chan] = i;
6588                 print_port_info(adapter->port[i]);
6589         }
6590         if (i == 0) {
6591                 dev_err(&pdev->dev, "could not register any net devices\n");
6592                 goto out_free_dev;
6593         }
6594         if (err) {
6595                 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
6596                 err = 0;
6597         }
6598
6599         if (cxgb4_debugfs_root) {
6600                 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
6601                                                            cxgb4_debugfs_root);
6602                 setup_debugfs(adapter);
6603         }
6604
6605         /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
6606         pdev->needs_freset = 1;
6607
6608         if (is_offload(adapter))
6609                 attach_ulds(adapter);
6610
6611 sriov:
6612 #ifdef CONFIG_PCI_IOV
6613         if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
6614                 if (pci_enable_sriov(pdev, num_vf[func]) == 0)
6615                         dev_info(&pdev->dev,
6616                                  "instantiated %u virtual functions\n",
6617                                  num_vf[func]);
6618 #endif
6619         return 0;
6620
6621  out_free_dev:
6622         free_some_resources(adapter);
6623  out_unmap_bar:
6624         if (!is_t4(adapter->params.chip))
6625                 iounmap(adapter->bar2);
6626  out_free_adapter:
6627         if (adapter->workq)
6628                 destroy_workqueue(adapter->workq);
6629
6630         kfree(adapter);
6631  out_unmap_bar0:
6632         iounmap(regs);
6633  out_disable_device:
6634         pci_disable_pcie_error_reporting(pdev);
6635         pci_disable_device(pdev);
6636  out_release_regions:
6637         pci_release_regions(pdev);
6638         return err;
6639 }
6640
6641 static void remove_one(struct pci_dev *pdev)
6642 {
6643         struct adapter *adapter = pci_get_drvdata(pdev);
6644
6645 #ifdef CONFIG_PCI_IOV
6646         pci_disable_sriov(pdev);
6647
6648 #endif
6649
6650         if (adapter) {
6651                 int i;
6652
6653                 /* Tear down per-adapter Work Queue first since it can contain
6654                  * references to our adapter data structure.
6655                  */
6656                 destroy_workqueue(adapter->workq);
6657
6658                 if (is_offload(adapter))
6659                         detach_ulds(adapter);
6660
6661                 for_each_port(adapter, i)
6662                         if (adapter->port[i]->reg_state == NETREG_REGISTERED)
6663                                 unregister_netdev(adapter->port[i]);
6664
6665                 debugfs_remove_recursive(adapter->debugfs_root);
6666
6667                 /* If we allocated filters, free up state associated with any
6668                  * valid filters ...
6669                  */
6670                 if (adapter->tids.ftid_tab) {
6671                         struct filter_entry *f = &adapter->tids.ftid_tab[0];
6672                         for (i = 0; i < (adapter->tids.nftids +
6673                                         adapter->tids.nsftids); i++, f++)
6674                                 if (f->valid)
6675                                         clear_filter(adapter, f);
6676                 }
6677
6678                 if (adapter->flags & FULL_INIT_DONE)
6679                         cxgb_down(adapter);
6680
6681                 free_some_resources(adapter);
6682                 iounmap(adapter->regs);
6683                 if (!is_t4(adapter->params.chip))
6684                         iounmap(adapter->bar2);
6685                 pci_disable_pcie_error_reporting(pdev);
6686                 if ((adapter->flags & DEV_ENABLED)) {
6687                         pci_disable_device(pdev);
6688                         adapter->flags &= ~DEV_ENABLED;
6689                 }
6690                 pci_release_regions(pdev);
6691                 synchronize_rcu();
6692                 kfree(adapter);
6693         } else
6694                 pci_release_regions(pdev);
6695 }
6696
6697 static struct pci_driver cxgb4_driver = {
6698         .name     = KBUILD_MODNAME,
6699         .id_table = cxgb4_pci_tbl,
6700         .probe    = init_one,
6701         .remove   = remove_one,
6702         .shutdown = remove_one,
6703         .err_handler = &cxgb4_eeh,
6704 };
6705
6706 static int __init cxgb4_init_module(void)
6707 {
6708         int ret;
6709
6710         /* Debugfs support is optional, just warn if this fails */
6711         cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
6712         if (!cxgb4_debugfs_root)
6713                 pr_warn("could not create debugfs entry, continuing\n");
6714
6715         ret = pci_register_driver(&cxgb4_driver);
6716         if (ret < 0)
6717                 debugfs_remove(cxgb4_debugfs_root);
6718
6719 #if IS_ENABLED(CONFIG_IPV6)
6720         register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6721 #endif
6722
6723         return ret;
6724 }
6725
6726 static void __exit cxgb4_cleanup_module(void)
6727 {
6728 #if IS_ENABLED(CONFIG_IPV6)
6729         unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6730 #endif
6731         pci_unregister_driver(&cxgb4_driver);
6732         debugfs_remove(cxgb4_debugfs_root);  /* NULL ok */
6733 }
6734
6735 module_init(cxgb4_init_module);
6736 module_exit(cxgb4_cleanup_module);