drivers/net/ethernet/freescale/gianfar.c

   1 /* drivers/net/ethernet/freescale/gianfar.c
   2  *
   3  * Gianfar Ethernet Driver
   4  * This driver is designed for the non-CPM ethernet controllers
   5  * on the 85xx and 83xx family of integrated processors
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala
  10  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11  *
  12  * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
  13  * Copyright 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  65 #define DEBUG
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/delay.h>
  74 #include <linux/netdevice.h>
  75 #include <linux/etherdevice.h>
  76 #include <linux/skbuff.h>
  77 #include <linux/if_vlan.h>
  78 #include <linux/spinlock.h>
  79 #include <linux/mm.h>
  80 #include <linux/of_address.h>
  81 #include <linux/of_irq.h>
  82 #include <linux/of_mdio.h>
  83 #include <linux/of_platform.h>
  84 #include <linux/ip.h>
  85 #include <linux/tcp.h>
  86 #include <linux/udp.h>
  87 #include <linux/in.h>
  88 #include <linux/net_tstamp.h>
  89
  90 #include <asm/io.h>
  91 #ifdef CONFIG_PPC
  92 #include <asm/reg.h>
  93 #include <asm/mpc85xx.h>
  94 #endif
  95 #include <asm/irq.h>
  96 #include <asm/uaccess.h>
  97 #include <linux/module.h>
  98 #include <linux/dma-mapping.h>
  99 #include <linux/crc32.h>
 100 #include <linux/mii.h>
 101 #include <linux/phy.h>
 102 #include <linux/phy_fixed.h>
 103 #include <linux/of.h>
 104 #include <linux/of_net.h>
 105 #include <linux/of_address.h>
 106 #include <linux/of_irq.h>
 107
 108 #include "gianfar.h"
 109
 110 #define TX_TIMEOUT      (5*HZ)
 111
 112 const char gfar_driver_version[] = "2.0";
 113
 114 static int gfar_enet_open(struct net_device *dev);
 115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 116 static void gfar_reset_task(struct work_struct *work);
 117 static void gfar_timeout(struct net_device *dev);
 118 static int gfar_close(struct net_device *dev);
 119 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
 120                                 int alloc_cnt);
 121 static int gfar_set_mac_address(struct net_device *dev);
 122 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 123 static irqreturn_t gfar_error(int irq, void *dev_id);
 124 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 125 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 126 static void adjust_link(struct net_device *dev);
 127 static noinline void gfar_update_link_state(struct gfar_private *priv);
 128 static int init_phy(struct net_device *dev);
 129 static int gfar_probe(struct platform_device *ofdev);
 130 static int gfar_remove(struct platform_device *ofdev);
 131 static void free_skb_resources(struct gfar_private *priv);
 132 static void gfar_set_multi(struct net_device *dev);
 133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 134 static void gfar_configure_serdes(struct net_device *dev);
 135 static int gfar_poll_rx(struct napi_struct *napi, int budget);
 136 static int gfar_poll_tx(struct napi_struct *napi, int budget);
 137 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget);
 138 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget);
 139 #ifdef CONFIG_NET_POLL_CONTROLLER
 140 static void gfar_netpoll(struct net_device *dev);
 141 #endif
 142 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 143 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 144 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb);
 145 static void gfar_halt_nodisable(struct gfar_private *priv);
 146 static void gfar_clear_exact_match(struct net_device *dev);
 147 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 148                                   const u8 *addr);
 149 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 150
 151 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 152 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 153 MODULE_LICENSE("GPL");
 154
 155 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 156                             dma_addr_t buf)
 157 {
 158         u32 lstatus;
 159
 160         bdp->bufPtr = cpu_to_be32(buf);
 161
 162         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 163         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 164                 lstatus |= BD_LFLAG(RXBD_WRAP);
 165
 166         gfar_wmb();
 167
 168         bdp->lstatus = cpu_to_be32(lstatus);
 169 }
 170
 171 static void gfar_init_bds(struct net_device *ndev)
 172 {
 173         struct gfar_private *priv = netdev_priv(ndev);
 174         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 175         struct gfar_priv_tx_q *tx_queue = NULL;
 176         struct gfar_priv_rx_q *rx_queue = NULL;
 177         struct txbd8 *txbdp;
 178         u32 __iomem *rfbptr;
 179         int i, j;
 180
 181         for (i = 0; i < priv->num_tx_queues; i++) {
 182                 tx_queue = priv->tx_queue[i];
 183                 /* Initialize some variables in our dev structure */
 184                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 185                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 186                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 187                 tx_queue->skb_curtx = 0;
 188                 tx_queue->skb_dirtytx = 0;
 189
 190                 /* Initialize Transmit Descriptor Ring */
 191                 txbdp = tx_queue->tx_bd_base;
 192                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 193                         txbdp->lstatus = 0;
 194                         txbdp->bufPtr = 0;
 195                         txbdp++;
 196                 }
 197
 198                 /* Set the last descriptor in the ring to indicate wrap */
 199                 txbdp--;
 200                 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
 201                                             TXBD_WRAP);
 202         }
 203
 204         rfbptr = &regs->rfbptr0;
 205         for (i = 0; i < priv->num_rx_queues; i++) {
 206                 rx_queue = priv->rx_queue[i];
 207
 208                 rx_queue->next_to_clean = 0;
 209                 rx_queue->next_to_use = 0;
 210                 rx_queue->next_to_alloc = 0;
 211
 212                 /* make sure next_to_clean != next_to_use after this
 213                  * by leaving at least 1 unused descriptor
 214                  */
 215                 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue));
 216
 217                 rx_queue->rfbptr = rfbptr;
 218                 rfbptr += 2;
 219         }
 220 }
 221
 222 static int gfar_alloc_skb_resources(struct net_device *ndev)
 223 {
 224         void *vaddr;
 225         dma_addr_t addr;
 226         int i, j;
 227         struct gfar_private *priv = netdev_priv(ndev);
 228         struct device *dev = priv->dev;
 229         struct gfar_priv_tx_q *tx_queue = NULL;
 230         struct gfar_priv_rx_q *rx_queue = NULL;
 231
 232         priv->total_tx_ring_size = 0;
 233         for (i = 0; i < priv->num_tx_queues; i++)
 234                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 235
 236         priv->total_rx_ring_size = 0;
 237         for (i = 0; i < priv->num_rx_queues; i++)
 238                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 239
 240         /* Allocate memory for the buffer descriptors */
 241         vaddr = dma_alloc_coherent(dev,
 242                                    (priv->total_tx_ring_size *
 243                                     sizeof(struct txbd8)) +
 244                                    (priv->total_rx_ring_size *
 245                                     sizeof(struct rxbd8)),
 246                                    &addr, GFP_KERNEL);
 247         if (!vaddr)
 248                 return -ENOMEM;
 249
 250         for (i = 0; i < priv->num_tx_queues; i++) {
 251                 tx_queue = priv->tx_queue[i];
 252                 tx_queue->tx_bd_base = vaddr;
 253                 tx_queue->tx_bd_dma_base = addr;
 254                 tx_queue->dev = ndev;
 255                 /* enet DMA only understands physical addresses */
 256                 addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 257                 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 258         }
 259
 260         /* Start the rx descriptor ring where the tx ring leaves off */
 261         for (i = 0; i < priv->num_rx_queues; i++) {
 262                 rx_queue = priv->rx_queue[i];
 263                 rx_queue->rx_bd_base = vaddr;
 264                 rx_queue->rx_bd_dma_base = addr;
 265                 rx_queue->ndev = ndev;
 266                 rx_queue->dev = dev;
 267                 addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 268                 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 269         }
 270
 271         /* Setup the skbuff rings */
 272         for (i = 0; i < priv->num_tx_queues; i++) {
 273                 tx_queue = priv->tx_queue[i];
 274                 tx_queue->tx_skbuff =
 275                         kmalloc_array(tx_queue->tx_ring_size,
 276                                       sizeof(*tx_queue->tx_skbuff),
 277                                       GFP_KERNEL);
 278                 if (!tx_queue->tx_skbuff)
 279                         goto cleanup;
 280
 281                 for (j = 0; j < tx_queue->tx_ring_size; j++)
 282                         tx_queue->tx_skbuff[j] = NULL;
 283         }
 284
 285         for (i = 0; i < priv->num_rx_queues; i++) {
 286                 rx_queue = priv->rx_queue[i];
 287                 rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size,
 288                                             sizeof(*rx_queue->rx_buff),
 289                                             GFP_KERNEL);
 290                 if (!rx_queue->rx_buff)
 291                         goto cleanup;
 292         }
 293
 294         gfar_init_bds(ndev);
 295
 296         return 0;
 297
 298 cleanup:
 299         free_skb_resources(priv);
 300         return -ENOMEM;
 301 }
 302
 303 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 304 {
 305         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 306         u32 __iomem *baddr;
 307         int i;
 308
 309         baddr = &regs->tbase0;
 310         for (i = 0; i < priv->num_tx_queues; i++) {
 311                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 312                 baddr += 2;
 313         }
 314
 315         baddr = &regs->rbase0;
 316         for (i = 0; i < priv->num_rx_queues; i++) {
 317                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 318                 baddr += 2;
 319         }
 320 }
 321
 322 static void gfar_init_rqprm(struct gfar_private *priv)
 323 {
 324         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 325         u32 __iomem *baddr;
 326         int i;
 327
 328         baddr = &regs->rqprm0;
 329         for (i = 0; i < priv->num_rx_queues; i++) {
 330                 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
 331                            (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
 332                 baddr++;
 333         }
 334 }
 335
 336 static void gfar_rx_offload_en(struct gfar_private *priv)
 337 {
 338         /* set this when rx hw offload (TOE) functions are being used */
 339         priv->uses_rxfcb = 0;
 340
 341         if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
 342                 priv->uses_rxfcb = 1;
 343
 344         if (priv->hwts_rx_en || priv->rx_filer_enable)
 345                 priv->uses_rxfcb = 1;
 346 }
 347
 348 static void gfar_mac_rx_config(struct gfar_private *priv)
 349 {
 350         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 351         u32 rctrl = 0;
 352
 353         if (priv->rx_filer_enable) {
 354                 rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
 355                 /* Program the RIR0 reg with the required distribution */
 356                 if (priv->poll_mode == GFAR_SQ_POLLING)
 357                         gfar_write(&regs->rir0, DEFAULT_2RXQ_RIR0);
 358                 else /* GFAR_MQ_POLLING */
 359                         gfar_write(&regs->rir0, DEFAULT_8RXQ_RIR0);
 360         }
 361
 362         /* Restore PROMISC mode */
 363         if (priv->ndev->flags & IFF_PROMISC)
 364                 rctrl |= RCTRL_PROM;
 365
 366         if (priv->ndev->features & NETIF_F_RXCSUM)
 367                 rctrl |= RCTRL_CHECKSUMMING;
 368
 369         if (priv->extended_hash)
 370                 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
 371
 372         if (priv->padding) {
 373                 rctrl &= ~RCTRL_PAL_MASK;
 374                 rctrl |= RCTRL_PADDING(priv->padding);
 375         }
 376
 377         /* Enable HW time stamping if requested from user space */
 378         if (priv->hwts_rx_en)
 379                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 380
 381         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
 382                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 383
 384         /* Clear the LFC bit */
 385         gfar_write(&regs->rctrl, rctrl);
 386         /* Init flow control threshold values */
 387         gfar_init_rqprm(priv);
 388         gfar_write(&regs->ptv, DEFAULT_LFC_PTVVAL);
 389         rctrl |= RCTRL_LFC;
 390
 391         /* Init rctrl based on our settings */
 392         gfar_write(&regs->rctrl, rctrl);
 393 }
 394
 395 static void gfar_mac_tx_config(struct gfar_private *priv)
 396 {
 397         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 398         u32 tctrl = 0;
 399
 400         if (priv->ndev->features & NETIF_F_IP_CSUM)
 401                 tctrl |= TCTRL_INIT_CSUM;
 402
 403         if (priv->prio_sched_en)
 404                 tctrl |= TCTRL_TXSCHED_PRIO;
 405         else {
 406                 tctrl |= TCTRL_TXSCHED_WRRS;
 407                 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
 408                 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
 409         }
 410
 411         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
 412                 tctrl |= TCTRL_VLINS;
 413
 414         gfar_write(&regs->tctrl, tctrl);
 415 }
 416
 417 static void gfar_configure_coalescing(struct gfar_private *priv,
 418                                unsigned long tx_mask, unsigned long rx_mask)
 419 {
 420         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 421         u32 __iomem *baddr;
 422
 423         if (priv->mode == MQ_MG_MODE) {
 424                 int i = 0;
 425
 426                 baddr = &regs->txic0;
 427                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
 428                         gfar_write(baddr + i, 0);
 429                         if (likely(priv->tx_queue[i]->txcoalescing))
 430                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
 431                 }
 432
 433                 baddr = &regs->rxic0;
 434                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
 435                         gfar_write(baddr + i, 0);
 436                         if (likely(priv->rx_queue[i]->rxcoalescing))
 437                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
 438                 }
 439         } else {
 440                 /* Backward compatible case -- even if we enable
 441                  * multiple queues, there's only single reg to program
 442                  */
 443                 gfar_write(&regs->txic, 0);
 444                 if (likely(priv->tx_queue[0]->txcoalescing))
 445                         gfar_write(&regs->txic, priv->tx_queue[0]->txic);
 446
 447                 gfar_write(&regs->rxic, 0);
 448                 if (unlikely(priv->rx_queue[0]->rxcoalescing))
 449                         gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
 450         }
 451 }
 452
 453 void gfar_configure_coalescing_all(struct gfar_private *priv)
 454 {
 455         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 456 }
 457
 458 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 459 {
 460         struct gfar_private *priv = netdev_priv(dev);
 461         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 462         unsigned long tx_packets = 0, tx_bytes = 0;
 463         int i;
 464
 465         for (i = 0; i < priv->num_rx_queues; i++) {
 466                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 467                 rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
 468                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 469         }
 470
 471         dev->stats.rx_packets = rx_packets;
 472         dev->stats.rx_bytes   = rx_bytes;
 473         dev->stats.rx_dropped = rx_dropped;
 474
 475         for (i = 0; i < priv->num_tx_queues; i++) {
 476                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 477                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 478         }
 479
 480         dev->stats.tx_bytes   = tx_bytes;
 481         dev->stats.tx_packets = tx_packets;
 482
 483         return &dev->stats;
 484 }
 485
 486 static int gfar_set_mac_addr(struct net_device *dev, void *p)
 487 {
 488         eth_mac_addr(dev, p);
 489
 490         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
 491
 492         return 0;
 493 }
 494
 495 static const struct net_device_ops gfar_netdev_ops = {
 496         .ndo_open = gfar_enet_open,
 497         .ndo_start_xmit = gfar_start_xmit,
 498         .ndo_stop = gfar_close,
 499         .ndo_change_mtu = gfar_change_mtu,
 500         .ndo_set_features = gfar_set_features,
 501         .ndo_set_rx_mode = gfar_set_multi,
 502         .ndo_tx_timeout = gfar_timeout,
 503         .ndo_do_ioctl = gfar_ioctl,
 504         .ndo_get_stats = gfar_get_stats,
 505         .ndo_set_mac_address = gfar_set_mac_addr,
 506         .ndo_validate_addr = eth_validate_addr,
 507 #ifdef CONFIG_NET_POLL_CONTROLLER
 508         .ndo_poll_controller = gfar_netpoll,
 509 #endif
 510 };
 511
 512 static void gfar_ints_disable(struct gfar_private *priv)
 513 {
 514         int i;
 515         for (i = 0; i < priv->num_grps; i++) {
 516                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 517                 /* Clear IEVENT */
 518                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 519
 520                 /* Initialize IMASK */
 521                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 522         }
 523 }
 524
 525 static void gfar_ints_enable(struct gfar_private *priv)
 526 {
 527         int i;
 528         for (i = 0; i < priv->num_grps; i++) {
 529                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 530                 /* Unmask the interrupts we look for */
 531                 gfar_write(&regs->imask, IMASK_DEFAULT);
 532         }
 533 }
 534
 535 static int gfar_alloc_tx_queues(struct gfar_private *priv)
 536 {
 537         int i;
 538
 539         for (i = 0; i < priv->num_tx_queues; i++) {
 540                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 541                                             GFP_KERNEL);
 542                 if (!priv->tx_queue[i])
 543                         return -ENOMEM;
 544
 545                 priv->tx_queue[i]->tx_skbuff = NULL;
 546                 priv->tx_queue[i]->qindex = i;
 547                 priv->tx_queue[i]->dev = priv->ndev;
 548                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 549         }
 550         return 0;
 551 }
 552
 553 static int gfar_alloc_rx_queues(struct gfar_private *priv)
 554 {
 555         int i;
 556
 557         for (i = 0; i < priv->num_rx_queues; i++) {
 558                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 559                                             GFP_KERNEL);
 560                 if (!priv->rx_queue[i])
 561                         return -ENOMEM;
 562
 563                 priv->rx_queue[i]->qindex = i;
 564                 priv->rx_queue[i]->ndev = priv->ndev;
 565         }
 566         return 0;
 567 }
 568
 569 static void gfar_free_tx_queues(struct gfar_private *priv)
 570 {
 571         int i;
 572
 573         for (i = 0; i < priv->num_tx_queues; i++)
 574                 kfree(priv->tx_queue[i]);
 575 }
 576
 577 static void gfar_free_rx_queues(struct gfar_private *priv)
 578 {
 579         int i;
 580
 581         for (i = 0; i < priv->num_rx_queues; i++)
 582                 kfree(priv->rx_queue[i]);
 583 }
 584
 585 static void unmap_group_regs(struct gfar_private *priv)
 586 {
 587         int i;
 588
 589         for (i = 0; i < MAXGROUPS; i++)
 590                 if (priv->gfargrp[i].regs)
 591                         iounmap(priv->gfargrp[i].regs);
 592 }
 593
 594 static void free_gfar_dev(struct gfar_private *priv)
 595 {
 596         int i, j;
 597
 598         for (i = 0; i < priv->num_grps; i++)
 599                 for (j = 0; j < GFAR_NUM_IRQS; j++) {
 600                         kfree(priv->gfargrp[i].irqinfo[j]);
 601                         priv->gfargrp[i].irqinfo[j] = NULL;
 602                 }
 603
 604         free_netdev(priv->ndev);
 605 }
 606
 607 static void disable_napi(struct gfar_private *priv)
 608 {
 609         int i;
 610
 611         for (i = 0; i < priv->num_grps; i++) {
 612                 napi_disable(&priv->gfargrp[i].napi_rx);
 613                 napi_disable(&priv->gfargrp[i].napi_tx);
 614         }
 615 }
 616
 617 static void enable_napi(struct gfar_private *priv)
 618 {
 619         int i;
 620
 621         for (i = 0; i < priv->num_grps; i++) {
 622                 napi_enable(&priv->gfargrp[i].napi_rx);
 623                 napi_enable(&priv->gfargrp[i].napi_tx);
 624         }
 625 }
 626
 627 static int gfar_parse_group(struct device_node *np,
 628                             struct gfar_private *priv, const char *model)
 629 {
 630         struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
 631         int i;
 632
 633         for (i = 0; i < GFAR_NUM_IRQS; i++) {
 634                 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
 635                                           GFP_KERNEL);
 636                 if (!grp->irqinfo[i])
 637                         return -ENOMEM;
 638         }
 639
 640         grp->regs = of_iomap(np, 0);
 641         if (!grp->regs)
 642                 return -ENOMEM;
 643
 644         gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
 645
 646         /* If we aren't the FEC we have multiple interrupts */
 647         if (model && strcasecmp(model, "FEC")) {
 648                 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
 649                 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
 650                 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
 651                     gfar_irq(grp, RX)->irq == NO_IRQ ||
 652                     gfar_irq(grp, ER)->irq == NO_IRQ)
 653                         return -EINVAL;
 654         }
 655
 656         grp->priv = priv;
 657         spin_lock_init(&grp->grplock);
 658         if (priv->mode == MQ_MG_MODE) {
 659                 u32 rxq_mask, txq_mask;
 660                 int ret;
 661
 662                 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 663                 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 664
 665                 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
 666                 if (!ret) {
 667                         grp->rx_bit_map = rxq_mask ?
 668                         rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 669                 }
 670
 671                 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
 672                 if (!ret) {
 673                         grp->tx_bit_map = txq_mask ?
 674                         txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 675                 }
 676
 677                 if (priv->poll_mode == GFAR_SQ_POLLING) {
 678                         /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
 679                         grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 680                         grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 681                 }
 682         } else {
 683                 grp->rx_bit_map = 0xFF;
 684                 grp->tx_bit_map = 0xFF;
 685         }
 686
 687         /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
 688          * right to left, so we need to revert the 8 bits to get the q index
 689          */
 690         grp->rx_bit_map = bitrev8(grp->rx_bit_map);
 691         grp->tx_bit_map = bitrev8(grp->tx_bit_map);
 692
 693         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
 694          * also assign queues to groups
 695          */
 696         for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
 697                 if (!grp->rx_queue)
 698                         grp->rx_queue = priv->rx_queue[i];
 699                 grp->num_rx_queues++;
 700                 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
 701                 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
 702                 priv->rx_queue[i]->grp = grp;
 703         }
 704
 705         for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
 706                 if (!grp->tx_queue)
 707                         grp->tx_queue = priv->tx_queue[i];
 708                 grp->num_tx_queues++;
 709                 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
 710                 priv->tqueue |= (TQUEUE_EN0 >> i);
 711                 priv->tx_queue[i]->grp = grp;
 712         }
 713
 714         priv->num_grps++;
 715
 716         return 0;
 717 }
 718
 719 static int gfar_of_group_count(struct device_node *np)
 720 {
 721         struct device_node *child;
 722         int num = 0;
 723
 724         for_each_available_child_of_node(np, child)
 725                 if (!of_node_cmp(child->name, "queue-group"))
 726                         num++;
 727
 728         return num;
 729 }
 730
 731 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 732 {
 733         const char *model;
 734         const char *ctype;
 735         const void *mac_addr;
 736         int err = 0, i;
 737         struct net_device *dev = NULL;
 738         struct gfar_private *priv = NULL;
 739         struct device_node *np = ofdev->dev.of_node;
 740         struct device_node *child = NULL;
 741         struct property *stash;
 742         u32 stash_len = 0;
 743         u32 stash_idx = 0;
 744         unsigned int num_tx_qs, num_rx_qs;
 745         unsigned short mode, poll_mode;
 746
 747         if (!np)
 748                 return -ENODEV;
 749
 750         if (of_device_is_compatible(np, "fsl,etsec2")) {
 751                 mode = MQ_MG_MODE;
 752                 poll_mode = GFAR_SQ_POLLING;
 753         } else {
 754                 mode = SQ_SG_MODE;
 755                 poll_mode = GFAR_SQ_POLLING;
 756         }
 757
 758         if (mode == SQ_SG_MODE) {
 759                 num_tx_qs = 1;
 760                 num_rx_qs = 1;
 761         } else { /* MQ_MG_MODE */
 762                 /* get the actual number of supported groups */
 763                 unsigned int num_grps = gfar_of_group_count(np);
 764
 765                 if (num_grps == 0 || num_grps > MAXGROUPS) {
 766                         dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
 767                                 num_grps);
 768                         pr_err("Cannot do alloc_etherdev, aborting\n");
 769                         return -EINVAL;
 770                 }
 771
 772                 if (poll_mode == GFAR_SQ_POLLING) {
 773                         num_tx_qs = num_grps; /* one txq per int group */
 774                         num_rx_qs = num_grps; /* one rxq per int group */
 775                 } else { /* GFAR_MQ_POLLING */
 776                         u32 tx_queues, rx_queues;
 777                         int ret;
 778
 779                         /* parse the num of HW tx and rx queues */
 780                         ret = of_property_read_u32(np, "fsl,num_tx_queues",
 781                                                    &tx_queues);
 782                         num_tx_qs = ret ? 1 : tx_queues;
 783
 784                         ret = of_property_read_u32(np, "fsl,num_rx_queues",
 785                                                    &rx_queues);
 786                         num_rx_qs = ret ? 1 : rx_queues;
 787                 }
 788         }
 789
 790         if (num_tx_qs > MAX_TX_QS) {
 791                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 792                        num_tx_qs, MAX_TX_QS);
 793                 pr_err("Cannot do alloc_etherdev, aborting\n");
 794                 return -EINVAL;
 795         }
 796
 797         if (num_rx_qs > MAX_RX_QS) {
 798                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 799                        num_rx_qs, MAX_RX_QS);
 800                 pr_err("Cannot do alloc_etherdev, aborting\n");
 801                 return -EINVAL;
 802         }
 803
 804         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 805         dev = *pdev;
 806         if (NULL == dev)
 807                 return -ENOMEM;
 808
 809         priv = netdev_priv(dev);
 810         priv->ndev = dev;
 811
 812         priv->mode = mode;
 813         priv->poll_mode = poll_mode;
 814
 815         priv->num_tx_queues = num_tx_qs;
 816         netif_set_real_num_rx_queues(dev, num_rx_qs);
 817         priv->num_rx_queues = num_rx_qs;
 818
 819         err = gfar_alloc_tx_queues(priv);
 820         if (err)
 821                 goto tx_alloc_failed;
 822
 823         err = gfar_alloc_rx_queues(priv);
 824         if (err)
 825                 goto rx_alloc_failed;
 826
 827         err = of_property_read_string(np, "model", &model);
 828         if (err) {
 829                 pr_err("Device model property missing, aborting\n");
 830                 goto rx_alloc_failed;
 831         }
 832
 833         /* Init Rx queue filer rule set linked list */
 834         INIT_LIST_HEAD(&priv->rx_list.list);
 835         priv->rx_list.count = 0;
 836         mutex_init(&priv->rx_queue_access);
 837
 838         for (i = 0; i < MAXGROUPS; i++)
 839                 priv->gfargrp[i].regs = NULL;
 840
 841         /* Parse and initialize group specific information */
 842         if (priv->mode == MQ_MG_MODE) {
 843                 for_each_available_child_of_node(np, child) {
 844                         if (of_node_cmp(child->name, "queue-group"))
 845                                 continue;
 846
 847                         err = gfar_parse_group(child, priv, model);
 848                         if (err)
 849                                 goto err_grp_init;
 850                 }
 851         } else { /* SQ_SG_MODE */
 852                 err = gfar_parse_group(np, priv, model);
 853                 if (err)
 854                         goto err_grp_init;
 855         }
 856
 857         stash = of_find_property(np, "bd-stash", NULL);
 858
 859         if (stash) {
 860                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 861                 priv->bd_stash_en = 1;
 862         }
 863
 864         err = of_property_read_u32(np, "rx-stash-len", &stash_len);
 865
 866         if (err == 0)
 867                 priv->rx_stash_size = stash_len;
 868
 869         err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
 870
 871         if (err == 0)
 872                 priv->rx_stash_index = stash_idx;
 873
 874         if (stash_len || stash_idx)
 875                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 876
 877         mac_addr = of_get_mac_address(np);
 878
 879         if (mac_addr)
 880                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
 881
 882         if (model && !strcasecmp(model, "TSEC"))
 883                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 884                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 885                                      FSL_GIANFAR_DEV_HAS_RMON |
 886                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 887
 888         if (model && !strcasecmp(model, "eTSEC"))
 889                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 890                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 891                                      FSL_GIANFAR_DEV_HAS_RMON |
 892                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 893                                      FSL_GIANFAR_DEV_HAS_CSUM |
 894                                      FSL_GIANFAR_DEV_HAS_VLAN |
 895                                      FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 896                                      FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 897                                      FSL_GIANFAR_DEV_HAS_TIMER;
 898
 899         err = of_property_read_string(np, "phy-connection-type", &ctype);
 900
 901         /* We only care about rgmii-id.  The rest are autodetected */
 902         if (err == 0 && !strcmp(ctype, "rgmii-id"))
 903                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 904         else
 905                 priv->interface = PHY_INTERFACE_MODE_MII;
 906
 907         if (of_find_property(np, "fsl,magic-packet", NULL))
 908                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 909
 910         if (of_get_property(np, "fsl,wake-on-filer", NULL))
 911                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER;
 912
 913         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 914
 915         /* In the case of a fixed PHY, the DT node associated
 916          * to the PHY is the Ethernet MAC DT node.
 917          */
 918         if (!priv->phy_node && of_phy_is_fixed_link(np)) {
 919                 err = of_phy_register_fixed_link(np);
 920                 if (err)
 921                         goto err_grp_init;
 922
 923                 priv->phy_node = of_node_get(np);
 924         }
 925
 926         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 927         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 928
 929         return 0;
 930
 931 err_grp_init:
 932         unmap_group_regs(priv);
 933 rx_alloc_failed:
 934         gfar_free_rx_queues(priv);
 935 tx_alloc_failed:
 936         gfar_free_tx_queues(priv);
 937         free_gfar_dev(priv);
 938         return err;
 939 }
 940
 941 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
 942 {
 943         struct hwtstamp_config config;
 944         struct gfar_private *priv = netdev_priv(netdev);
 945
 946         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 947                 return -EFAULT;
 948
 949         /* reserved for future extensions */
 950         if (config.flags)
 951                 return -EINVAL;
 952
 953         switch (config.tx_type) {
 954         case HWTSTAMP_TX_OFF:
 955                 priv->hwts_tx_en = 0;
 956                 break;
 957         case HWTSTAMP_TX_ON:
 958                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 959                         return -ERANGE;
 960                 priv->hwts_tx_en = 1;
 961                 break;
 962         default:
 963                 return -ERANGE;
 964         }
 965
 966         switch (config.rx_filter) {
 967         case HWTSTAMP_FILTER_NONE:
 968                 if (priv->hwts_rx_en) {
 969                         priv->hwts_rx_en = 0;
 970                         reset_gfar(netdev);
 971                 }
 972                 break;
 973         default:
 974                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 975                         return -ERANGE;
 976                 if (!priv->hwts_rx_en) {
 977                         priv->hwts_rx_en = 1;
 978                         reset_gfar(netdev);
 979                 }
 980                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 981                 break;
 982         }
 983
 984         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 985                 -EFAULT : 0;
 986 }
 987
 988 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
 989 {
 990         struct hwtstamp_config config;
 991         struct gfar_private *priv = netdev_priv(netdev);
 992
 993         config.flags = 0;
 994         config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
 995         config.rx_filter = (priv->hwts_rx_en ?
 996                             HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
 997
 998         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 999                 -EFAULT : 0;
1000 }
1001
1002 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1003 {
1004         struct gfar_private *priv = netdev_priv(dev);
1005
1006         if (!netif_running(dev))
1007                 return -EINVAL;
1008
1009         if (cmd == SIOCSHWTSTAMP)
1010                 return gfar_hwtstamp_set(dev, rq);
1011         if (cmd == SIOCGHWTSTAMP)
1012                 return gfar_hwtstamp_get(dev, rq);
1013
1014         if (!priv->phydev)
1015                 return -ENODEV;
1016
1017         return phy_mii_ioctl(priv->phydev, rq, cmd);
1018 }
1019
1020 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
1021                                    u32 class)
1022 {
1023         u32 rqfpr = FPR_FILER_MASK;
1024         u32 rqfcr = 0x0;
1025
1026         rqfar--;
1027         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
1028         priv->ftp_rqfpr[rqfar] = rqfpr;
1029         priv->ftp_rqfcr[rqfar] = rqfcr;
1030         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1031
1032         rqfar--;
1033         rqfcr = RQFCR_CMP_NOMATCH;
1034         priv->ftp_rqfpr[rqfar] = rqfpr;
1035         priv->ftp_rqfcr[rqfar] = rqfcr;
1036         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1037
1038         rqfar--;
1039         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
1040         rqfpr = class;
1041         priv->ftp_rqfcr[rqfar] = rqfcr;
1042         priv->ftp_rqfpr[rqfar] = rqfpr;
1043         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1044
1045         rqfar--;
1046         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
1047         rqfpr = class;
1048         priv->ftp_rqfcr[rqfar] = rqfcr;
1049         priv->ftp_rqfpr[rqfar] = rqfpr;
1050         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1051
1052         return rqfar;
1053 }
1054
1055 static void gfar_init_filer_table(struct gfar_private *priv)
1056 {
1057         int i = 0x0;
1058         u32 rqfar = MAX_FILER_IDX;
1059         u32 rqfcr = 0x0;
1060         u32 rqfpr = FPR_FILER_MASK;
1061
1062         /* Default rule */
1063         rqfcr = RQFCR_CMP_MATCH;
1064         priv->ftp_rqfcr[rqfar] = rqfcr;
1065         priv->ftp_rqfpr[rqfar] = rqfpr;
1066         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1067
1068         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
1069         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
1070         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
1071         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
1072         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
1073         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
1074
1075         /* cur_filer_idx indicated the first non-masked rule */
1076         priv->cur_filer_idx = rqfar;
1077
1078         /* Rest are masked rules */
1079         rqfcr = RQFCR_CMP_NOMATCH;
1080         for (i = 0; i < rqfar; i++) {
1081                 priv->ftp_rqfcr[i] = rqfcr;
1082                 priv->ftp_rqfpr[i] = rqfpr;
1083                 gfar_write_filer(priv, i, rqfcr, rqfpr);
1084         }
1085 }
1086
1087 #ifdef CONFIG_PPC
1088 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
1089 {
1090         unsigned int pvr = mfspr(SPRN_PVR);
1091         unsigned int svr = mfspr(SPRN_SVR);
1092         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
1093         unsigned int rev = svr & 0xffff;
1094
1095         /* MPC8313 Rev 2.0 and higher; All MPC837x */
1096         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
1097             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1098                 priv->errata |= GFAR_ERRATA_74;
1099
1100         /* MPC8313 and MPC837x all rev */
1101         if ((pvr == 0x80850010 && mod == 0x80b0) ||
1102             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1103                 priv->errata |= GFAR_ERRATA_76;
1104
1105         /* MPC8313 Rev < 2.0 */
1106         if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
1107                 priv->errata |= GFAR_ERRATA_12;
1108 }
1109
1110 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
1111 {
1112         unsigned int svr = mfspr(SPRN_SVR);
1113
1114         if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
1115                 priv->errata |= GFAR_ERRATA_12;
1116         if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
1117             ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)))
1118                 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
1119 }
1120 #endif
1121
1122 static void gfar_detect_errata(struct gfar_private *priv)
1123 {
1124         struct device *dev = &priv->ofdev->dev;
1125
1126         /* no plans to fix */
1127         priv->errata |= GFAR_ERRATA_A002;
1128
1129 #ifdef CONFIG_PPC
1130         if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1131                 __gfar_detect_errata_85xx(priv);
1132         else /* non-mpc85xx parts, i.e. e300 core based */
1133                 __gfar_detect_errata_83xx(priv);
1134 #endif
1135
1136         if (priv->errata)
1137                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1138                          priv->errata);
1139 }
1140
1141 void gfar_mac_reset(struct gfar_private *priv)
1142 {
1143         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1144         u32 tempval;
1145
1146         /* Reset MAC layer */
1147         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1148
1149         /* We need to delay at least 3 TX clocks */
1150         udelay(3);
1151
1152         /* the soft reset bit is not self-resetting, so we need to
1153          * clear it before resuming normal operation
1154          */
1155         gfar_write(&regs->maccfg1, 0);
1156
1157         udelay(3);
1158
1159         gfar_rx_offload_en(priv);
1160
1161         /* Initialize the max receive frame/buffer lengths */
1162         gfar_write(&regs->maxfrm, GFAR_JUMBO_FRAME_SIZE);
1163         gfar_write(&regs->mrblr, GFAR_RXB_SIZE);
1164
1165         /* Initialize the Minimum Frame Length Register */
1166         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1167
1168         /* Initialize MACCFG2. */
1169         tempval = MACCFG2_INIT_SETTINGS;
1170
1171         /* eTSEC74 erratum: Rx frames of length MAXFRM or MAXFRM-1
1172          * are marked as truncated.  Avoid this by MACCFG2[Huge Frame]=1,
1173          * and by checking RxBD[LG] and discarding larger than MAXFRM.
1174          */
1175         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1176                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1177
1178         gfar_write(&regs->maccfg2, tempval);
1179
1180         /* Clear mac addr hash registers */
1181         gfar_write(&regs->igaddr0, 0);
1182         gfar_write(&regs->igaddr1, 0);
1183         gfar_write(&regs->igaddr2, 0);
1184         gfar_write(&regs->igaddr3, 0);
1185         gfar_write(&regs->igaddr4, 0);
1186         gfar_write(&regs->igaddr5, 0);
1187         gfar_write(&regs->igaddr6, 0);
1188         gfar_write(&regs->igaddr7, 0);
1189
1190         gfar_write(&regs->gaddr0, 0);
1191         gfar_write(&regs->gaddr1, 0);
1192         gfar_write(&regs->gaddr2, 0);
1193         gfar_write(&regs->gaddr3, 0);
1194         gfar_write(&regs->gaddr4, 0);
1195         gfar_write(&regs->gaddr5, 0);
1196         gfar_write(&regs->gaddr6, 0);
1197         gfar_write(&regs->gaddr7, 0);
1198
1199         if (priv->extended_hash)
1200                 gfar_clear_exact_match(priv->ndev);
1201
1202         gfar_mac_rx_config(priv);
1203
1204         gfar_mac_tx_config(priv);
1205
1206         gfar_set_mac_address(priv->ndev);
1207
1208         gfar_set_multi(priv->ndev);
1209
1210         /* clear ievent and imask before configuring coalescing */
1211         gfar_ints_disable(priv);
1212
1213         /* Configure the coalescing support */
1214         gfar_configure_coalescing_all(priv);
1215 }
1216
1217 static void gfar_hw_init(struct gfar_private *priv)
1218 {
1219         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1220         u32 attrs;
1221
1222         /* Stop the DMA engine now, in case it was running before
1223          * (The firmware could have used it, and left it running).
1224          */
1225         gfar_halt(priv);
1226
1227         gfar_mac_reset(priv);
1228
1229         /* Zero out the rmon mib registers if it has them */
1230         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1231                 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1232
1233                 /* Mask off the CAM interrupts */
1234                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1235                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1236         }
1237
1238         /* Initialize ECNTRL */
1239         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1240
1241         /* Set the extraction length and index */
1242         attrs = ATTRELI_EL(priv->rx_stash_size) |
1243                 ATTRELI_EI(priv->rx_stash_index);
1244
1245         gfar_write(&regs->attreli, attrs);
1246
1247         /* Start with defaults, and add stashing
1248          * depending on driver parameters
1249          */
1250         attrs = ATTR_INIT_SETTINGS;
1251
1252         if (priv->bd_stash_en)
1253                 attrs |= ATTR_BDSTASH;
1254
1255         if (priv->rx_stash_size != 0)
1256                 attrs |= ATTR_BUFSTASH;
1257
1258         gfar_write(&regs->attr, attrs);
1259
1260         /* FIFO configs */
1261         gfar_write(&regs->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1262         gfar_write(&regs->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1263         gfar_write(&regs->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1264
1265         /* Program the interrupt steering regs, only for MG devices */
1266         if (priv->num_grps > 1)
1267                 gfar_write_isrg(priv);
1268 }
1269
1270 static void gfar_init_addr_hash_table(struct gfar_private *priv)
1271 {
1272         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1273
1274         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1275                 priv->extended_hash = 1;
1276                 priv->hash_width = 9;
1277
1278                 priv->hash_regs[0] = &regs->igaddr0;
1279                 priv->hash_regs[1] = &regs->igaddr1;
1280                 priv->hash_regs[2] = &regs->igaddr2;
1281                 priv->hash_regs[3] = &regs->igaddr3;
1282                 priv->hash_regs[4] = &regs->igaddr4;
1283                 priv->hash_regs[5] = &regs->igaddr5;
1284                 priv->hash_regs[6] = &regs->igaddr6;
1285                 priv->hash_regs[7] = &regs->igaddr7;
1286                 priv->hash_regs[8] = &regs->gaddr0;
1287                 priv->hash_regs[9] = &regs->gaddr1;
1288                 priv->hash_regs[10] = &regs->gaddr2;
1289                 priv->hash_regs[11] = &regs->gaddr3;
1290                 priv->hash_regs[12] = &regs->gaddr4;
1291                 priv->hash_regs[13] = &regs->gaddr5;
1292                 priv->hash_regs[14] = &regs->gaddr6;
1293                 priv->hash_regs[15] = &regs->gaddr7;
1294
1295         } else {
1296                 priv->extended_hash = 0;
1297                 priv->hash_width = 8;
1298
1299                 priv->hash_regs[0] = &regs->gaddr0;
1300                 priv->hash_regs[1] = &regs->gaddr1;
1301                 priv->hash_regs[2] = &regs->gaddr2;
1302                 priv->hash_regs[3] = &regs->gaddr3;
1303                 priv->hash_regs[4] = &regs->gaddr4;
1304                 priv->hash_regs[5] = &regs->gaddr5;
1305                 priv->hash_regs[6] = &regs->gaddr6;
1306                 priv->hash_regs[7] = &regs->gaddr7;
1307         }
1308 }
1309
1310 /* Set up the ethernet device structure, private data,
1311  * and anything else we need before we start
1312  */
1313 static int gfar_probe(struct platform_device *ofdev)
1314 {
1315         struct net_device *dev = NULL;
1316         struct gfar_private *priv = NULL;
1317         int err = 0, i;
1318
1319         err = gfar_of_init(ofdev, &dev);
1320
1321         if (err)
1322                 return err;
1323
1324         priv = netdev_priv(dev);
1325         priv->ndev = dev;
1326         priv->ofdev = ofdev;
1327         priv->dev = &ofdev->dev;
1328         SET_NETDEV_DEV(dev, &ofdev->dev);
1329
1330         INIT_WORK(&priv->reset_task, gfar_reset_task);
1331
1332         platform_set_drvdata(ofdev, priv);
1333
1334         gfar_detect_errata(priv);
1335
1336         /* Set the dev->base_addr to the gfar reg region */
1337         dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1338
1339         /* Fill in the dev structure */
1340         dev->watchdog_timeo = TX_TIMEOUT;
1341         dev->mtu = 1500;
1342         dev->netdev_ops = &gfar_netdev_ops;
1343         dev->ethtool_ops = &gfar_ethtool_ops;
1344
1345         /* Register for napi ...We are registering NAPI for each grp */
1346         for (i = 0; i < priv->num_grps; i++) {
1347                 if (priv->poll_mode == GFAR_SQ_POLLING) {
1348                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1349                                        gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
1350                         netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1351                                        gfar_poll_tx_sq, 2);
1352                 } else {
1353                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1354                                        gfar_poll_rx, GFAR_DEV_WEIGHT);
1355                         netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1356                                        gfar_poll_tx, 2);
1357                 }
1358         }
1359
1360         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1361                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1362                                    NETIF_F_RXCSUM;
1363                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1364                                  NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1365         }
1366
1367         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1368                 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1369                                     NETIF_F_HW_VLAN_CTAG_RX;
1370                 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1371         }
1372
1373         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
1374
1375         gfar_init_addr_hash_table(priv);
1376
1377         /* Insert receive time stamps into padding alignment bytes */
1378         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1379                 priv->padding = 8;
1380
1381         if (dev->features & NETIF_F_IP_CSUM ||
1382             priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1383                 dev->needed_headroom = GMAC_FCB_LEN;
1384
1385         /* Initializing some of the rx/tx queue level parameters */
1386         for (i = 0; i < priv->num_tx_queues; i++) {
1387                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1388                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1389                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1390                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1391         }
1392
1393         for (i = 0; i < priv->num_rx_queues; i++) {
1394                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1395                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1396                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1397         }
1398
1399         /* always enable rx filer */
1400         priv->rx_filer_enable = 1;
1401         /* Enable most messages by default */
1402         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1403         /* use pritority h/w tx queue scheduling for single queue devices */
1404         if (priv->num_tx_queues == 1)
1405                 priv->prio_sched_en = 1;
1406
1407         set_bit(GFAR_DOWN, &priv->state);
1408
1409         gfar_hw_init(priv);
1410
1411         /* Carrier starts down, phylib will bring it up */
1412         netif_carrier_off(dev);
1413
1414         err = register_netdev(dev);
1415
1416         if (err) {
1417                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1418                 goto register_fail;
1419         }
1420
1421         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET)
1422                 priv->wol_supported |= GFAR_WOL_MAGIC;
1423
1424         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER) &&
1425             priv->rx_filer_enable)
1426                 priv->wol_supported |= GFAR_WOL_FILER_UCAST;
1427
1428         device_set_wakeup_capable(&ofdev->dev, priv->wol_supported);
1429
1430         /* fill out IRQ number and name fields */
1431         for (i = 0; i < priv->num_grps; i++) {
1432                 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1433                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1434                         sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1435                                 dev->name, "_g", '0' + i, "_tx");
1436                         sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1437                                 dev->name, "_g", '0' + i, "_rx");
1438                         sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1439                                 dev->name, "_g", '0' + i, "_er");
1440                 } else
1441                         strcpy(gfar_irq(grp, TX)->name, dev->name);
1442         }
1443
1444         /* Initialize the filer table */
1445         gfar_init_filer_table(priv);
1446
1447         /* Print out the device info */
1448         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1449
1450         /* Even more device info helps when determining which kernel
1451          * provided which set of benchmarks.
1452          */
1453         netdev_info(dev, "Running with NAPI enabled\n");
1454         for (i = 0; i < priv->num_rx_queues; i++)
1455                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1456                             i, priv->rx_queue[i]->rx_ring_size);
1457         for (i = 0; i < priv->num_tx_queues; i++)
1458                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1459                             i, priv->tx_queue[i]->tx_ring_size);
1460
1461         return 0;
1462
1463 register_fail:
1464         unmap_group_regs(priv);
1465         gfar_free_rx_queues(priv);
1466         gfar_free_tx_queues(priv);
1467         of_node_put(priv->phy_node);
1468         of_node_put(priv->tbi_node);
1469         free_gfar_dev(priv);
1470         return err;
1471 }
1472
1473 static int gfar_remove(struct platform_device *ofdev)
1474 {
1475         struct gfar_private *priv = platform_get_drvdata(ofdev);
1476
1477         of_node_put(priv->phy_node);
1478         of_node_put(priv->tbi_node);
1479
1480         unregister_netdev(priv->ndev);
1481         unmap_group_regs(priv);
1482         gfar_free_rx_queues(priv);
1483         gfar_free_tx_queues(priv);
1484         free_gfar_dev(priv);
1485
1486         return 0;
1487 }
1488
1489 #ifdef CONFIG_PM
1490
1491 static void __gfar_filer_disable(struct gfar_private *priv)
1492 {
1493         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1494         u32 temp;
1495
1496         temp = gfar_read(&regs->rctrl);
1497         temp &= ~(RCTRL_FILREN | RCTRL_PRSDEP_INIT);
1498         gfar_write(&regs->rctrl, temp);
1499 }
1500
1501 static void __gfar_filer_enable(struct gfar_private *priv)
1502 {
1503         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1504         u32 temp;
1505
1506         temp = gfar_read(&regs->rctrl);
1507         temp |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
1508         gfar_write(&regs->rctrl, temp);
1509 }
1510
1511 /* Filer rules implementing wol capabilities */
1512 static void gfar_filer_config_wol(struct gfar_private *priv)
1513 {
1514         unsigned int i;
1515         u32 rqfcr;
1516
1517         __gfar_filer_disable(priv);
1518
1519         /* clear the filer table, reject any packet by default */
1520         rqfcr = RQFCR_RJE | RQFCR_CMP_MATCH;
1521         for (i = 0; i <= MAX_FILER_IDX; i++)
1522                 gfar_write_filer(priv, i, rqfcr, 0);
1523
1524         i = 0;
1525         if (priv->wol_opts & GFAR_WOL_FILER_UCAST) {
1526                 /* unicast packet, accept it */
1527                 struct net_device *ndev = priv->ndev;
1528                 /* get the default rx queue index */
1529                 u8 qindex = (u8)priv->gfargrp[0].rx_queue->qindex;
1530                 u32 dest_mac_addr = (ndev->dev_addr[0] << 16) |
1531                                     (ndev->dev_addr[1] << 8) |
1532                                      ndev->dev_addr[2];
1533
1534                 rqfcr = (qindex << 10) | RQFCR_AND |
1535                         RQFCR_CMP_EXACT | RQFCR_PID_DAH;
1536
1537                 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
1538
1539                 dest_mac_addr = (ndev->dev_addr[3] << 16) |
1540                                 (ndev->dev_addr[4] << 8) |
1541                                  ndev->dev_addr[5];
1542                 rqfcr = (qindex << 10) | RQFCR_GPI |
1543                         RQFCR_CMP_EXACT | RQFCR_PID_DAL;
1544                 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
1545         }
1546
1547         __gfar_filer_enable(priv);
1548 }
1549
1550 static void gfar_filer_restore_table(struct gfar_private *priv)
1551 {
1552         u32 rqfcr, rqfpr;
1553         unsigned int i;
1554
1555         __gfar_filer_disable(priv);
1556
1557         for (i = 0; i <= MAX_FILER_IDX; i++) {
1558                 rqfcr = priv->ftp_rqfcr[i];
1559                 rqfpr = priv->ftp_rqfpr[i];
1560                 gfar_write_filer(priv, i, rqfcr, rqfpr);
1561         }
1562
1563         __gfar_filer_enable(priv);
1564 }
1565
1566 /* gfar_start() for Rx only and with the FGPI filer interrupt enabled */
1567 static void gfar_start_wol_filer(struct gfar_private *priv)
1568 {
1569         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1570         u32 tempval;
1571         int i = 0;
1572
1573         /* Enable Rx hw queues */
1574         gfar_write(&regs->rqueue, priv->rqueue);
1575
1576         /* Initialize DMACTRL to have WWR and WOP */
1577         tempval = gfar_read(&regs->dmactrl);
1578         tempval |= DMACTRL_INIT_SETTINGS;
1579         gfar_write(&regs->dmactrl, tempval);
1580
1581         /* Make sure we aren't stopped */
1582         tempval = gfar_read(&regs->dmactrl);
1583         tempval &= ~DMACTRL_GRS;
1584         gfar_write(&regs->dmactrl, tempval);
1585
1586         for (i = 0; i < priv->num_grps; i++) {
1587                 regs = priv->gfargrp[i].regs;
1588                 /* Clear RHLT, so that the DMA starts polling now */
1589                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1590                 /* enable the Filer General Purpose Interrupt */
1591                 gfar_write(&regs->imask, IMASK_FGPI);
1592         }
1593
1594         /* Enable Rx DMA */
1595         tempval = gfar_read(&regs->maccfg1);
1596         tempval |= MACCFG1_RX_EN;
1597         gfar_write(&regs->maccfg1, tempval);
1598 }
1599
1600 static int gfar_suspend(struct device *dev)
1601 {
1602         struct gfar_private *priv = dev_get_drvdata(dev);
1603         struct net_device *ndev = priv->ndev;
1604         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1605         u32 tempval;
1606         u16 wol = priv->wol_opts;
1607
1608         if (!netif_running(ndev))
1609                 return 0;
1610
1611         disable_napi(priv);
1612         netif_tx_lock(ndev);
1613         netif_device_detach(ndev);
1614         netif_tx_unlock(ndev);
1615
1616         gfar_halt(priv);
1617
1618         if (wol & GFAR_WOL_MAGIC) {
1619                 /* Enable interrupt on Magic Packet */
1620                 gfar_write(&regs->imask, IMASK_MAG);
1621
1622                 /* Enable Magic Packet mode */
1623                 tempval = gfar_read(&regs->maccfg2);
1624                 tempval |= MACCFG2_MPEN;
1625                 gfar_write(&regs->maccfg2, tempval);
1626
1627                 /* re-enable the Rx block */
1628                 tempval = gfar_read(&regs->maccfg1);
1629                 tempval |= MACCFG1_RX_EN;
1630                 gfar_write(&regs->maccfg1, tempval);
1631
1632         } else if (wol & GFAR_WOL_FILER_UCAST) {
1633                 gfar_filer_config_wol(priv);
1634                 gfar_start_wol_filer(priv);
1635
1636         } else {
1637                 phy_stop(priv->phydev);
1638         }
1639
1640         return 0;
1641 }
1642
1643 static int gfar_resume(struct device *dev)
1644 {
1645         struct gfar_private *priv = dev_get_drvdata(dev);
1646         struct net_device *ndev = priv->ndev;
1647         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1648         u32 tempval;
1649         u16 wol = priv->wol_opts;
1650
1651         if (!netif_running(ndev))
1652                 return 0;
1653
1654         if (wol & GFAR_WOL_MAGIC) {
1655                 /* Disable Magic Packet mode */
1656                 tempval = gfar_read(&regs->maccfg2);
1657                 tempval &= ~MACCFG2_MPEN;
1658                 gfar_write(&regs->maccfg2, tempval);
1659
1660         } else if (wol & GFAR_WOL_FILER_UCAST) {
1661                 /* need to stop rx only, tx is already down */
1662                 gfar_halt(priv);
1663                 gfar_filer_restore_table(priv);
1664
1665         } else {
1666                 phy_start(priv->phydev);
1667         }
1668
1669         gfar_start(priv);
1670
1671         netif_device_attach(ndev);
1672         enable_napi(priv);
1673
1674         return 0;
1675 }
1676
1677 static int gfar_restore(struct device *dev)
1678 {
1679         struct gfar_private *priv = dev_get_drvdata(dev);
1680         struct net_device *ndev = priv->ndev;
1681
1682         if (!netif_running(ndev)) {
1683                 netif_device_attach(ndev);
1684
1685                 return 0;
1686         }
1687
1688         gfar_init_bds(ndev);
1689
1690         gfar_mac_reset(priv);
1691
1692         gfar_init_tx_rx_base(priv);
1693
1694         gfar_start(priv);
1695
1696         priv->oldlink = 0;
1697         priv->oldspeed = 0;
1698         priv->oldduplex = -1;
1699
1700         if (priv->phydev)
1701                 phy_start(priv->phydev);
1702
1703         netif_device_attach(ndev);
1704         enable_napi(priv);
1705
1706         return 0;
1707 }
1708
1709 static struct dev_pm_ops gfar_pm_ops = {
1710         .suspend = gfar_suspend,
1711         .resume = gfar_resume,
1712         .freeze = gfar_suspend,
1713         .thaw = gfar_resume,
1714         .restore = gfar_restore,
1715 };
1716
1717 #define GFAR_PM_OPS (&gfar_pm_ops)
1718
1719 #else
1720
1721 #define GFAR_PM_OPS NULL
1722
1723 #endif
1724
1725 /* Reads the controller's registers to determine what interface
1726  * connects it to the PHY.
1727  */
1728 static phy_interface_t gfar_get_interface(struct net_device *dev)
1729 {
1730         struct gfar_private *priv = netdev_priv(dev);
1731         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1732         u32 ecntrl;
1733
1734         ecntrl = gfar_read(&regs->ecntrl);
1735
1736         if (ecntrl & ECNTRL_SGMII_MODE)
1737                 return PHY_INTERFACE_MODE_SGMII;
1738
1739         if (ecntrl & ECNTRL_TBI_MODE) {
1740                 if (ecntrl & ECNTRL_REDUCED_MODE)
1741                         return PHY_INTERFACE_MODE_RTBI;
1742                 else
1743                         return PHY_INTERFACE_MODE_TBI;
1744         }
1745
1746         if (ecntrl & ECNTRL_REDUCED_MODE) {
1747                 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1748                         return PHY_INTERFACE_MODE_RMII;
1749                 }
1750                 else {
1751                         phy_interface_t interface = priv->interface;
1752
1753                         /* This isn't autodetected right now, so it must
1754                          * be set by the device tree or platform code.
1755                          */
1756                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1757                                 return PHY_INTERFACE_MODE_RGMII_ID;
1758
1759                         return PHY_INTERFACE_MODE_RGMII;
1760                 }
1761         }
1762
1763         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1764                 return PHY_INTERFACE_MODE_GMII;
1765
1766         return PHY_INTERFACE_MODE_MII;
1767 }
1768
1769
1770 /* Initializes driver's PHY state, and attaches to the PHY.
1771  * Returns 0 on success.
1772  */
1773 static int init_phy(struct net_device *dev)
1774 {
1775         struct gfar_private *priv = netdev_priv(dev);
1776         uint gigabit_support =
1777                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1778                 GFAR_SUPPORTED_GBIT : 0;
1779         phy_interface_t interface;
1780
1781         priv->oldlink = 0;
1782         priv->oldspeed = 0;
1783         priv->oldduplex = -1;
1784
1785         interface = gfar_get_interface(dev);
1786
1787         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1788                                       interface);
1789         if (!priv->phydev) {
1790                 dev_err(&dev->dev, "could not attach to PHY\n");
1791                 return -ENODEV;
1792         }
1793
1794         if (interface == PHY_INTERFACE_MODE_SGMII)
1795                 gfar_configure_serdes(dev);
1796
1797         /* Remove any features not supported by the controller */
1798         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1799         priv->phydev->advertising = priv->phydev->supported;
1800
1801         /* Add support for flow control, but don't advertise it by default */
1802         priv->phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
1803
1804         return 0;
1805 }
1806
1807 /* Initialize TBI PHY interface for communicating with the
1808  * SERDES lynx PHY on the chip.  We communicate with this PHY
1809  * through the MDIO bus on each controller, treating it as a
1810  * "normal" PHY at the address found in the TBIPA register.  We assume
1811  * that the TBIPA register is valid.  Either the MDIO bus code will set
1812  * it to a value that doesn't conflict with other PHYs on the bus, or the
1813  * value doesn't matter, as there are no other PHYs on the bus.
1814  */
1815 static void gfar_configure_serdes(struct net_device *dev)
1816 {
1817         struct gfar_private *priv = netdev_priv(dev);
1818         struct phy_device *tbiphy;
1819
1820         if (!priv->tbi_node) {
1821                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1822                                     "device tree specify a tbi-handle\n");
1823                 return;
1824         }
1825
1826         tbiphy = of_phy_find_device(priv->tbi_node);
1827         if (!tbiphy) {
1828                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1829                 return;
1830         }
1831
1832         /* If the link is already up, we must already be ok, and don't need to
1833          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1834          * everything for us?  Resetting it takes the link down and requires
1835          * several seconds for it to come back.
1836          */
1837         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) {
1838                 put_device(&tbiphy->dev);
1839                 return;
1840         }
1841
1842         /* Single clk mode, mii mode off(for serdes communication) */
1843         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1844
1845         phy_write(tbiphy, MII_ADVERTISE,
1846                   ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1847                   ADVERTISE_1000XPSE_ASYM);
1848
1849         phy_write(tbiphy, MII_BMCR,
1850                   BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1851                   BMCR_SPEED1000);
1852
1853         put_device(&tbiphy->dev);
1854 }
1855
1856 static int __gfar_is_rx_idle(struct gfar_private *priv)
1857 {
1858         u32 res;
1859
1860         /* Normaly TSEC should not hang on GRS commands, so we should
1861          * actually wait for IEVENT_GRSC flag.
1862          */
1863         if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1864                 return 0;
1865
1866         /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1867          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1868          * and the Rx can be safely reset.
1869          */
1870         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1871         res &= 0x7f807f80;
1872         if ((res & 0xffff) == (res >> 16))
1873                 return 1;
1874
1875         return 0;
1876 }
1877
1878 /* Halt the receive and transmit queues */
1879 static void gfar_halt_nodisable(struct gfar_private *priv)
1880 {
1881         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1882         u32 tempval;
1883         unsigned int timeout;
1884         int stopped;
1885
1886         gfar_ints_disable(priv);
1887
1888         if (gfar_is_dma_stopped(priv))
1889                 return;
1890
1891         /* Stop the DMA, and wait for it to stop */
1892         tempval = gfar_read(&regs->dmactrl);
1893         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1894         gfar_write(&regs->dmactrl, tempval);
1895
1896 retry:
1897         timeout = 1000;
1898         while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1899                 cpu_relax();
1900                 timeout--;
1901         }
1902
1903         if (!timeout)
1904                 stopped = gfar_is_dma_stopped(priv);
1905
1906         if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1907             !__gfar_is_rx_idle(priv))
1908                 goto retry;
1909 }
1910
1911 /* Halt the receive and transmit queues */
1912 void gfar_halt(struct gfar_private *priv)
1913 {
1914         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1915         u32 tempval;
1916
1917         /* Dissable the Rx/Tx hw queues */
1918         gfar_write(&regs->rqueue, 0);
1919         gfar_write(&regs->tqueue, 0);
1920
1921         mdelay(10);
1922
1923         gfar_halt_nodisable(priv);
1924
1925         /* Disable Rx/Tx DMA */
1926         tempval = gfar_read(&regs->maccfg1);
1927         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1928         gfar_write(&regs->maccfg1, tempval);
1929 }
1930
1931 void stop_gfar(struct net_device *dev)
1932 {
1933         struct gfar_private *priv = netdev_priv(dev);
1934
1935         netif_tx_stop_all_queues(dev);
1936
1937         smp_mb__before_atomic();
1938         set_bit(GFAR_DOWN, &priv->state);
1939         smp_mb__after_atomic();
1940
1941         disable_napi(priv);
1942
1943         /* disable ints and gracefully shut down Rx/Tx DMA */
1944         gfar_halt(priv);
1945
1946         phy_stop(priv->phydev);
1947
1948         free_skb_resources(priv);
1949 }
1950
1951 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1952 {
1953         struct txbd8 *txbdp;
1954         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1955         int i, j;
1956
1957         txbdp = tx_queue->tx_bd_base;
1958
1959         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1960                 if (!tx_queue->tx_skbuff[i])
1961                         continue;
1962
1963                 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1964                                  be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
1965                 txbdp->lstatus = 0;
1966                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1967                      j++) {
1968                         txbdp++;
1969                         dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1970                                        be16_to_cpu(txbdp->length),
1971                                        DMA_TO_DEVICE);
1972                 }
1973                 txbdp++;
1974                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1975                 tx_queue->tx_skbuff[i] = NULL;
1976         }
1977         kfree(tx_queue->tx_skbuff);
1978         tx_queue->tx_skbuff = NULL;
1979 }
1980
1981 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1982 {
1983         int i;
1984
1985         struct rxbd8 *rxbdp = rx_queue->rx_bd_base;
1986
1987         if (rx_queue->skb)
1988                 dev_kfree_skb(rx_queue->skb);
1989
1990         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1991                 struct  gfar_rx_buff *rxb = &rx_queue->rx_buff[i];
1992
1993                 rxbdp->lstatus = 0;
1994                 rxbdp->bufPtr = 0;
1995                 rxbdp++;
1996
1997                 if (!rxb->page)
1998                         continue;
1999
2000                 dma_unmap_single(rx_queue->dev, rxb->dma,
2001                                  PAGE_SIZE, DMA_FROM_DEVICE);
2002                 __free_page(rxb->page);
2003
2004                 rxb->page = NULL;
2005         }
2006
2007         kfree(rx_queue->rx_buff);
2008         rx_queue->rx_buff = NULL;
2009 }
2010
2011 /* If there are any tx skbs or rx skbs still around, free them.
2012  * Then free tx_skbuff and rx_skbuff
2013  */
2014 static void free_skb_resources(struct gfar_private *priv)
2015 {
2016         struct gfar_priv_tx_q *tx_queue = NULL;
2017         struct gfar_priv_rx_q *rx_queue = NULL;
2018         int i;
2019
2020         /* Go through all the buffer descriptors and free their data buffers */
2021         for (i = 0; i < priv->num_tx_queues; i++) {
2022                 struct netdev_queue *txq;
2023
2024                 tx_queue = priv->tx_queue[i];
2025                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
2026                 if (tx_queue->tx_skbuff)
2027                         free_skb_tx_queue(tx_queue);
2028                 netdev_tx_reset_queue(txq);
2029         }
2030
2031         for (i = 0; i < priv->num_rx_queues; i++) {
2032                 rx_queue = priv->rx_queue[i];
2033                 if (rx_queue->rx_buff)
2034                         free_skb_rx_queue(rx_queue);
2035         }
2036
2037         dma_free_coherent(priv->dev,
2038                           sizeof(struct txbd8) * priv->total_tx_ring_size +
2039                           sizeof(struct rxbd8) * priv->total_rx_ring_size,
2040                           priv->tx_queue[0]->tx_bd_base,
2041                           priv->tx_queue[0]->tx_bd_dma_base);
2042 }
2043
2044 void gfar_start(struct gfar_private *priv)
2045 {
2046         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2047         u32 tempval;
2048         int i = 0;
2049
2050         /* Enable Rx/Tx hw queues */
2051         gfar_write(&regs->rqueue, priv->rqueue);
2052         gfar_write(&regs->tqueue, priv->tqueue);
2053
2054         /* Initialize DMACTRL to have WWR and WOP */
2055         tempval = gfar_read(&regs->dmactrl);
2056         tempval |= DMACTRL_INIT_SETTINGS;
2057         gfar_write(&regs->dmactrl, tempval);
2058
2059         /* Make sure we aren't stopped */
2060         tempval = gfar_read(&regs->dmactrl);
2061         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
2062         gfar_write(&regs->dmactrl, tempval);
2063
2064         for (i = 0; i < priv->num_grps; i++) {
2065                 regs = priv->gfargrp[i].regs;
2066                 /* Clear THLT/RHLT, so that the DMA starts polling now */
2067                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
2068                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
2069         }
2070
2071         /* Enable Rx/Tx DMA */
2072         tempval = gfar_read(&regs->maccfg1);
2073         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
2074         gfar_write(&regs->maccfg1, tempval);
2075
2076         gfar_ints_enable(priv);
2077
2078         priv->ndev->trans_start = jiffies; /* prevent tx timeout */
2079 }
2080
2081 static void free_grp_irqs(struct gfar_priv_grp *grp)
2082 {
2083         free_irq(gfar_irq(grp, TX)->irq, grp);
2084         free_irq(gfar_irq(grp, RX)->irq, grp);
2085         free_irq(gfar_irq(grp, ER)->irq, grp);
2086 }
2087
2088 static int register_grp_irqs(struct gfar_priv_grp *grp)
2089 {
2090         struct gfar_private *priv = grp->priv;
2091         struct net_device *dev = priv->ndev;
2092         int err;
2093
2094         /* If the device has multiple interrupts, register for
2095          * them.  Otherwise, only register for the one
2096          */
2097         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2098                 /* Install our interrupt handlers for Error,
2099                  * Transmit, and Receive
2100                  */
2101                 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2102                                   gfar_irq(grp, ER)->name, grp);
2103                 if (err < 0) {
2104                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2105                                   gfar_irq(grp, ER)->irq);
2106
2107                         goto err_irq_fail;
2108                 }
2109                 enable_irq_wake(gfar_irq(grp, ER)->irq);
2110
2111                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2112                                   gfar_irq(grp, TX)->name, grp);
2113                 if (err < 0) {
2114                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2115                                   gfar_irq(grp, TX)->irq);
2116                         goto tx_irq_fail;
2117                 }
2118                 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2119                                   gfar_irq(grp, RX)->name, grp);
2120                 if (err < 0) {
2121                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2122                                   gfar_irq(grp, RX)->irq);
2123                         goto rx_irq_fail;
2124                 }
2125                 enable_irq_wake(gfar_irq(grp, RX)->irq);
2126
2127         } else {
2128                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2129                                   gfar_irq(grp, TX)->name, grp);
2130                 if (err < 0) {
2131                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2132                                   gfar_irq(grp, TX)->irq);
2133                         goto err_irq_fail;
2134                 }
2135                 enable_irq_wake(gfar_irq(grp, TX)->irq);
2136         }
2137
2138         return 0;
2139
2140 rx_irq_fail:
2141         free_irq(gfar_irq(grp, TX)->irq, grp);
2142 tx_irq_fail:
2143         free_irq(gfar_irq(grp, ER)->irq, grp);
2144 err_irq_fail:
2145         return err;
2146
2147 }
2148
2149 static void gfar_free_irq(struct gfar_private *priv)
2150 {
2151         int i;
2152
2153         /* Free the IRQs */
2154         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2155                 for (i = 0; i < priv->num_grps; i++)
2156                         free_grp_irqs(&priv->gfargrp[i]);
2157         } else {
2158                 for (i = 0; i < priv->num_grps; i++)
2159                         free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2160                                  &priv->gfargrp[i]);
2161         }
2162 }
2163
2164 static int gfar_request_irq(struct gfar_private *priv)
2165 {
2166         int err, i, j;
2167
2168         for (i = 0; i < priv->num_grps; i++) {
2169                 err = register_grp_irqs(&priv->gfargrp[i]);
2170                 if (err) {
2171                         for (j = 0; j < i; j++)
2172                                 free_grp_irqs(&priv->gfargrp[j]);
2173                         return err;
2174                 }
2175         }
2176
2177         return 0;
2178 }
2179
2180 /* Bring the controller up and running */
2181 int startup_gfar(struct net_device *ndev)
2182 {
2183         struct gfar_private *priv = netdev_priv(ndev);
2184         int err;
2185
2186         gfar_mac_reset(priv);
2187
2188         err = gfar_alloc_skb_resources(ndev);
2189         if (err)
2190                 return err;
2191
2192         gfar_init_tx_rx_base(priv);
2193
2194         smp_mb__before_atomic();
2195         clear_bit(GFAR_DOWN, &priv->state);
2196         smp_mb__after_atomic();
2197
2198         /* Start Rx/Tx DMA and enable the interrupts */
2199         gfar_start(priv);
2200
2201         /* force link state update after mac reset */
2202         priv->oldlink = 0;
2203         priv->oldspeed = 0;
2204         priv->oldduplex = -1;
2205
2206         phy_start(priv->phydev);
2207
2208         enable_napi(priv);
2209
2210         netif_tx_wake_all_queues(ndev);
2211
2212         return 0;
2213 }
2214
2215 /* Called when something needs to use the ethernet device
2216  * Returns 0 for success.
2217  */
2218 static int gfar_enet_open(struct net_device *dev)
2219 {
2220         struct gfar_private *priv = netdev_priv(dev);
2221         int err;
2222
2223         err = init_phy(dev);
2224         if (err)
2225                 return err;
2226
2227         err = gfar_request_irq(priv);
2228         if (err)
2229                 return err;
2230
2231         err = startup_gfar(dev);
2232         if (err)
2233                 return err;
2234
2235         return err;
2236 }
2237
2238 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2239 {
2240         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2241
2242         memset(fcb, 0, GMAC_FCB_LEN);
2243
2244         return fcb;
2245 }
2246
2247 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2248                                     int fcb_length)
2249 {
2250         /* If we're here, it's a IP packet with a TCP or UDP
2251          * payload.  We set it to checksum, using a pseudo-header
2252          * we provide
2253          */
2254         u8 flags = TXFCB_DEFAULT;
2255
2256         /* Tell the controller what the protocol is
2257          * And provide the already calculated phcs
2258          */
2259         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2260                 flags |= TXFCB_UDP;
2261                 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
2262         } else
2263                 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
2264
2265         /* l3os is the distance between the start of the
2266          * frame (skb->data) and the start of the IP hdr.
2267          * l4os is the distance between the start of the
2268          * l3 hdr and the l4 hdr
2269          */
2270         fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
2271         fcb->l4os = skb_network_header_len(skb);
2272
2273         fcb->flags = flags;
2274 }
2275
2276 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2277 {
2278         fcb->flags |= TXFCB_VLN;
2279         fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
2280 }
2281
2282 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2283                                       struct txbd8 *base, int ring_size)
2284 {
2285         struct txbd8 *new_bd = bdp + stride;
2286
2287         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2288 }
2289
2290 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2291                                       int ring_size)
2292 {
2293         return skip_txbd(bdp, 1, base, ring_size);
2294 }
2295
2296 /* eTSEC12: csum generation not supported for some fcb offsets */
2297 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2298                                        unsigned long fcb_addr)
2299 {
2300         return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2301                (fcb_addr % 0x20) > 0x18);
2302 }
2303
2304 /* eTSEC76: csum generation for frames larger than 2500 may
2305  * cause excess delays before start of transmission
2306  */
2307 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2308                                        unsigned int len)
2309 {
2310         return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2311                (len > 2500));
2312 }
2313
2314 /* This is called by the kernel when a frame is ready for transmission.
2315  * It is pointed to by the dev->hard_start_xmit function pointer
2316  */
2317 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2318 {
2319         struct gfar_private *priv = netdev_priv(dev);
2320         struct gfar_priv_tx_q *tx_queue = NULL;
2321         struct netdev_queue *txq;
2322         struct gfar __iomem *regs = NULL;
2323         struct txfcb *fcb = NULL;
2324         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2325         u32 lstatus;
2326         int i, rq = 0;
2327         int do_tstamp, do_csum, do_vlan;
2328         u32 bufaddr;
2329         unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
2330
2331         rq = skb->queue_mapping;
2332         tx_queue = priv->tx_queue[rq];
2333         txq = netdev_get_tx_queue(dev, rq);
2334         base = tx_queue->tx_bd_base;
2335         regs = tx_queue->grp->regs;
2336
2337         do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2338         do_vlan = skb_vlan_tag_present(skb);
2339         do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2340                     priv->hwts_tx_en;
2341
2342         if (do_csum || do_vlan)
2343                 fcb_len = GMAC_FCB_LEN;
2344
2345         /* check if time stamp should be generated */
2346         if (unlikely(do_tstamp))
2347                 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2348
2349         /* make space for additional header when fcb is needed */
2350         if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
2351                 struct sk_buff *skb_new;
2352
2353                 skb_new = skb_realloc_headroom(skb, fcb_len);
2354                 if (!skb_new) {
2355                         dev->stats.tx_errors++;
2356                         dev_kfree_skb_any(skb);
2357                         return NETDEV_TX_OK;
2358                 }
2359
2360                 if (skb->sk)
2361                         skb_set_owner_w(skb_new, skb->sk);
2362                 dev_consume_skb_any(skb);
2363                 skb = skb_new;
2364         }
2365
2366         /* total number of fragments in the SKB */
2367         nr_frags = skb_shinfo(skb)->nr_frags;
2368
2369         /* calculate the required number of TxBDs for this skb */
2370         if (unlikely(do_tstamp))
2371                 nr_txbds = nr_frags + 2;
2372         else
2373                 nr_txbds = nr_frags + 1;
2374
2375         /* check if there is space to queue this packet */
2376         if (nr_txbds > tx_queue->num_txbdfree) {
2377                 /* no space, stop the queue */
2378                 netif_tx_stop_queue(txq);
2379                 dev->stats.tx_fifo_errors++;
2380                 return NETDEV_TX_BUSY;
2381         }
2382
2383         /* Update transmit stats */
2384         bytes_sent = skb->len;
2385         tx_queue->stats.tx_bytes += bytes_sent;
2386         /* keep Tx bytes on wire for BQL accounting */
2387         GFAR_CB(skb)->bytes_sent = bytes_sent;
2388         tx_queue->stats.tx_packets++;
2389
2390         txbdp = txbdp_start = tx_queue->cur_tx;
2391         lstatus = be32_to_cpu(txbdp->lstatus);
2392
2393         /* Time stamp insertion requires one additional TxBD */
2394         if (unlikely(do_tstamp))
2395                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2396                                                  tx_queue->tx_ring_size);
2397
2398         if (nr_frags == 0) {
2399                 if (unlikely(do_tstamp)) {
2400                         u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2401
2402                         lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2403                         txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2404                 } else {
2405                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2406                 }
2407         } else {
2408                 /* Place the fragment addresses and lengths into the TxBDs */
2409                 for (i = 0; i < nr_frags; i++) {
2410                         unsigned int frag_len;
2411                         /* Point at the next BD, wrapping as needed */
2412                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2413
2414                         frag_len = skb_shinfo(skb)->frags[i].size;
2415
2416                         lstatus = be32_to_cpu(txbdp->lstatus) | frag_len |
2417                                   BD_LFLAG(TXBD_READY);
2418
2419                         /* Handle the last BD specially */
2420                         if (i == nr_frags - 1)
2421                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2422
2423                         bufaddr = skb_frag_dma_map(priv->dev,
2424                                                    &skb_shinfo(skb)->frags[i],
2425                                                    0,
2426                                                    frag_len,
2427                                                    DMA_TO_DEVICE);
2428                         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2429                                 goto dma_map_err;
2430
2431                         /* set the TxBD length and buffer pointer */
2432                         txbdp->bufPtr = cpu_to_be32(bufaddr);
2433                         txbdp->lstatus = cpu_to_be32(lstatus);
2434                 }
2435
2436                 lstatus = be32_to_cpu(txbdp_start->lstatus);
2437         }
2438
2439         /* Add TxPAL between FCB and frame if required */
2440         if (unlikely(do_tstamp)) {
2441                 skb_push(skb, GMAC_TXPAL_LEN);
2442                 memset(skb->data, 0, GMAC_TXPAL_LEN);
2443         }
2444
2445         /* Add TxFCB if required */
2446         if (fcb_len) {
2447                 fcb = gfar_add_fcb(skb);
2448                 lstatus |= BD_LFLAG(TXBD_TOE);
2449         }
2450
2451         /* Set up checksumming */
2452         if (do_csum) {
2453                 gfar_tx_checksum(skb, fcb, fcb_len);
2454
2455                 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2456                     unlikely(gfar_csum_errata_76(priv, skb->len))) {
2457                         __skb_pull(skb, GMAC_FCB_LEN);
2458                         skb_checksum_help(skb);
2459                         if (do_vlan || do_tstamp) {
2460                                 /* put back a new fcb for vlan/tstamp TOE */
2461                                 fcb = gfar_add_fcb(skb);
2462                         } else {
2463                                 /* Tx TOE not used */
2464                                 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2465                                 fcb = NULL;
2466                         }
2467                 }
2468         }
2469
2470         if (do_vlan)
2471                 gfar_tx_vlan(skb, fcb);
2472
2473         /* Setup tx hardware time stamping if requested */
2474         if (unlikely(do_tstamp)) {
2475                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2476                 fcb->ptp = 1;
2477         }
2478
2479         bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
2480                                  DMA_TO_DEVICE);
2481         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2482                 goto dma_map_err;
2483
2484         txbdp_start->bufPtr = cpu_to_be32(bufaddr);
2485
2486         /* If time stamping is requested one additional TxBD must be set up. The
2487          * first TxBD points to the FCB and must have a data length of
2488          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2489          * the full frame length.
2490          */
2491         if (unlikely(do_tstamp)) {
2492                 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2493
2494                 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
2495                 bufaddr += fcb_len;
2496                 lstatus_ts |= BD_LFLAG(TXBD_READY) |
2497                               (skb_headlen(skb) - fcb_len);
2498
2499                 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
2500                 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2501                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2502         } else {
2503                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2504         }
2505
2506         netdev_tx_sent_queue(txq, bytes_sent);
2507
2508         gfar_wmb();
2509
2510         txbdp_start->lstatus = cpu_to_be32(lstatus);
2511
2512         gfar_wmb(); /* force lstatus write before tx_skbuff */
2513
2514         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2515
2516         /* Update the current skb pointer to the next entry we will use
2517          * (wrapping if necessary)
2518          */
2519         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2520                               TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2521
2522         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2523
2524         /* We can work in parallel with gfar_clean_tx_ring(), except
2525          * when modifying num_txbdfree. Note that we didn't grab the lock
2526          * when we were reading the num_txbdfree and checking for available
2527          * space, that's because outside of this function it can only grow.
2528          */
2529         spin_lock_bh(&tx_queue->txlock);
2530         /* reduce TxBD free count */
2531         tx_queue->num_txbdfree -= (nr_txbds);
2532         spin_unlock_bh(&tx_queue->txlock);
2533
2534         /* If the next BD still needs to be cleaned up, then the bds
2535          * are full.  We need to tell the kernel to stop sending us stuff.
2536          */
2537         if (!tx_queue->num_txbdfree) {
2538                 netif_tx_stop_queue(txq);
2539
2540                 dev->stats.tx_fifo_errors++;
2541         }
2542
2543         /* Tell the DMA to go go go */
2544         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2545
2546         return NETDEV_TX_OK;
2547
2548 dma_map_err:
2549         txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2550         if (do_tstamp)
2551                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2552         for (i = 0; i < nr_frags; i++) {
2553                 lstatus = be32_to_cpu(txbdp->lstatus);
2554                 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2555                         break;
2556
2557                 lstatus &= ~BD_LFLAG(TXBD_READY);
2558                 txbdp->lstatus = cpu_to_be32(lstatus);
2559                 bufaddr = be32_to_cpu(txbdp->bufPtr);
2560                 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
2561                                DMA_TO_DEVICE);
2562                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2563         }
2564         gfar_wmb();
2565         dev_kfree_skb_any(skb);
2566         return NETDEV_TX_OK;
2567 }
2568
2569 /* Stops the kernel queue, and halts the controller */
2570 static int gfar_close(struct net_device *dev)
2571 {
2572         struct gfar_private *priv = netdev_priv(dev);
2573
2574         cancel_work_sync(&priv->reset_task);
2575         stop_gfar(dev);
2576
2577         /* Disconnect from the PHY */
2578         phy_disconnect(priv->phydev);
2579         priv->phydev = NULL;
2580
2581         gfar_free_irq(priv);
2582
2583         return 0;
2584 }
2585
2586 /* Changes the mac address if the controller is not running. */
2587 static int gfar_set_mac_address(struct net_device *dev)
2588 {
2589         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2590
2591         return 0;
2592 }
2593
2594 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2595 {
2596         struct gfar_private *priv = netdev_priv(dev);
2597         int frame_size = new_mtu + ETH_HLEN;
2598
2599         if ((frame_size < 64) || (frame_size > GFAR_JUMBO_FRAME_SIZE)) {
2600                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2601                 return -EINVAL;
2602         }
2603
2604         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2605                 cpu_relax();
2606
2607         if (dev->flags & IFF_UP)
2608                 stop_gfar(dev);
2609
2610         dev->mtu = new_mtu;
2611
2612         if (dev->flags & IFF_UP)
2613                 startup_gfar(dev);
2614
2615         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2616
2617         return 0;
2618 }
2619
2620 void reset_gfar(struct net_device *ndev)
2621 {
2622         struct gfar_private *priv = netdev_priv(ndev);
2623
2624         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2625                 cpu_relax();
2626
2627         stop_gfar(ndev);
2628         startup_gfar(ndev);
2629
2630         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2631 }
2632
2633 /* gfar_reset_task gets scheduled when a packet has not been
2634  * transmitted after a set amount of time.
2635  * For now, assume that clearing out all the structures, and
2636  * starting over will fix the problem.
2637  */
2638 static void gfar_reset_task(struct work_struct *work)
2639 {
2640         struct gfar_private *priv = container_of(work, struct gfar_private,
2641                                                  reset_task);
2642         reset_gfar(priv->ndev);
2643 }
2644
2645 static void gfar_timeout(struct net_device *dev)
2646 {
2647         struct gfar_private *priv = netdev_priv(dev);
2648
2649         dev->stats.tx_errors++;
2650         schedule_work(&priv->reset_task);
2651 }
2652
2653 /* Interrupt Handler for Transmit complete */
2654 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2655 {
2656         struct net_device *dev = tx_queue->dev;
2657         struct netdev_queue *txq;
2658         struct gfar_private *priv = netdev_priv(dev);
2659         struct txbd8 *bdp, *next = NULL;
2660         struct txbd8 *lbdp = NULL;
2661         struct txbd8 *base = tx_queue->tx_bd_base;
2662         struct sk_buff *skb;
2663         int skb_dirtytx;
2664         int tx_ring_size = tx_queue->tx_ring_size;
2665         int frags = 0, nr_txbds = 0;
2666         int i;
2667         int howmany = 0;
2668         int tqi = tx_queue->qindex;
2669         unsigned int bytes_sent = 0;
2670         u32 lstatus;
2671         size_t buflen;
2672
2673         txq = netdev_get_tx_queue(dev, tqi);
2674         bdp = tx_queue->dirty_tx;
2675         skb_dirtytx = tx_queue->skb_dirtytx;
2676
2677         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2678
2679                 frags = skb_shinfo(skb)->nr_frags;
2680
2681                 /* When time stamping, one additional TxBD must be freed.
2682                  * Also, we need to dma_unmap_single() the TxPAL.
2683                  */
2684                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2685                         nr_txbds = frags + 2;
2686                 else
2687                         nr_txbds = frags + 1;
2688
2689                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2690
2691                 lstatus = be32_to_cpu(lbdp->lstatus);
2692
2693                 /* Only clean completed frames */
2694                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2695                     (lstatus & BD_LENGTH_MASK))
2696                         break;
2697
2698                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2699                         next = next_txbd(bdp, base, tx_ring_size);
2700                         buflen = be16_to_cpu(next->length) +
2701                                  GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2702                 } else
2703                         buflen = be16_to_cpu(bdp->length);
2704
2705                 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2706                                  buflen, DMA_TO_DEVICE);
2707
2708                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2709                         struct skb_shared_hwtstamps shhwtstamps;
2710                         u64 *ns = (u64 *)(((uintptr_t)skb->data + 0x10) &
2711                                           ~0x7UL);
2712
2713                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2714                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2715                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2716                         skb_tstamp_tx(skb, &shhwtstamps);
2717                         gfar_clear_txbd_status(bdp);
2718                         bdp = next;
2719                 }
2720
2721                 gfar_clear_txbd_status(bdp);
2722                 bdp = next_txbd(bdp, base, tx_ring_size);
2723
2724                 for (i = 0; i < frags; i++) {
2725                         dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2726                                        be16_to_cpu(bdp->length),
2727                                        DMA_TO_DEVICE);
2728                         gfar_clear_txbd_status(bdp);
2729                         bdp = next_txbd(bdp, base, tx_ring_size);
2730                 }
2731
2732                 bytes_sent += GFAR_CB(skb)->bytes_sent;
2733
2734                 dev_kfree_skb_any(skb);
2735
2736                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2737
2738                 skb_dirtytx = (skb_dirtytx + 1) &
2739                               TX_RING_MOD_MASK(tx_ring_size);
2740
2741                 howmany++;
2742                 spin_lock(&tx_queue->txlock);
2743                 tx_queue->num_txbdfree += nr_txbds;
2744                 spin_unlock(&tx_queue->txlock);
2745         }
2746
2747         /* If we freed a buffer, we can restart transmission, if necessary */
2748         if (tx_queue->num_txbdfree &&
2749             netif_tx_queue_stopped(txq) &&
2750             !(test_bit(GFAR_DOWN, &priv->state)))
2751                 netif_wake_subqueue(priv->ndev, tqi);
2752
2753         /* Update dirty indicators */
2754         tx_queue->skb_dirtytx = skb_dirtytx;
2755         tx_queue->dirty_tx = bdp;
2756
2757         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2758 }
2759
2760 static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb)
2761 {
2762         struct page *page;
2763         dma_addr_t addr;
2764
2765         page = dev_alloc_page();
2766         if (unlikely(!page))
2767                 return false;
2768
2769         addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
2770         if (unlikely(dma_mapping_error(rxq->dev, addr))) {
2771                 __free_page(page);
2772
2773                 return false;
2774         }
2775
2776         rxb->dma = addr;
2777         rxb->page = page;
2778         rxb->page_offset = 0;
2779
2780         return true;
2781 }
2782
2783 static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue)
2784 {
2785         struct gfar_private *priv = netdev_priv(rx_queue->ndev);
2786         struct gfar_extra_stats *estats = &priv->extra_stats;
2787
2788         netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n");
2789         atomic64_inc(&estats->rx_alloc_err);
2790 }
2791
2792 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
2793                                 int alloc_cnt)
2794 {
2795         struct rxbd8 *bdp;
2796         struct gfar_rx_buff *rxb;
2797         int i;
2798
2799         i = rx_queue->next_to_use;
2800         bdp = &rx_queue->rx_bd_base[i];
2801         rxb = &rx_queue->rx_buff[i];
2802
2803         while (alloc_cnt--) {
2804                 /* try reuse page */
2805                 if (unlikely(!rxb->page)) {
2806                         if (unlikely(!gfar_new_page(rx_queue, rxb))) {
2807                                 gfar_rx_alloc_err(rx_queue);
2808                                 break;
2809                         }
2810                 }
2811
2812                 /* Setup the new RxBD */
2813                 gfar_init_rxbdp(rx_queue, bdp,
2814                                 rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT);
2815
2816                 /* Update to the next pointer */
2817                 bdp++;
2818                 rxb++;
2819
2820                 if (unlikely(++i == rx_queue->rx_ring_size)) {
2821                         i = 0;
2822                         bdp = rx_queue->rx_bd_base;
2823                         rxb = rx_queue->rx_buff;
2824                 }
2825         }
2826
2827         rx_queue->next_to_use = i;
2828         rx_queue->next_to_alloc = i;
2829 }
2830
2831 static void count_errors(u32 lstatus, struct net_device *ndev)
2832 {
2833         struct gfar_private *priv = netdev_priv(ndev);
2834         struct net_device_stats *stats = &ndev->stats;
2835         struct gfar_extra_stats *estats = &priv->extra_stats;
2836
2837         /* If the packet was truncated, none of the other errors matter */
2838         if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) {
2839                 stats->rx_length_errors++;
2840
2841                 atomic64_inc(&estats->rx_trunc);
2842
2843                 return;
2844         }
2845         /* Count the errors, if there were any */
2846         if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) {
2847                 stats->rx_length_errors++;
2848
2849                 if (lstatus & BD_LFLAG(RXBD_LARGE))
2850                         atomic64_inc(&estats->rx_large);
2851                 else
2852                         atomic64_inc(&estats->rx_short);
2853         }
2854         if (lstatus & BD_LFLAG(RXBD_NONOCTET)) {
2855                 stats->rx_frame_errors++;
2856                 atomic64_inc(&estats->rx_nonoctet);
2857         }
2858         if (lstatus & BD_LFLAG(RXBD_CRCERR)) {
2859                 atomic64_inc(&estats->rx_crcerr);
2860                 stats->rx_crc_errors++;
2861         }
2862         if (lstatus & BD_LFLAG(RXBD_OVERRUN)) {
2863                 atomic64_inc(&estats->rx_overrun);
2864                 stats->rx_over_errors++;
2865         }
2866 }
2867
2868 irqreturn_t gfar_receive(int irq, void *grp_id)
2869 {
2870         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2871         unsigned long flags;
2872         u32 imask, ievent;
2873
2874         ievent = gfar_read(&grp->regs->ievent);
2875
2876         if (unlikely(ievent & IEVENT_FGPI)) {
2877                 gfar_write(&grp->regs->ievent, IEVENT_FGPI);
2878                 return IRQ_HANDLED;
2879         }
2880
2881         if (likely(napi_schedule_prep(&grp->napi_rx))) {
2882                 spin_lock_irqsave(&grp->grplock, flags);
2883                 imask = gfar_read(&grp->regs->imask);
2884                 imask &= IMASK_RX_DISABLED;
2885                 gfar_write(&grp->regs->imask, imask);
2886                 spin_unlock_irqrestore(&grp->grplock, flags);
2887                 __napi_schedule(&grp->napi_rx);
2888         } else {
2889                 /* Clear IEVENT, so interrupts aren't called again
2890                  * because of the packets that have already arrived.
2891                  */
2892                 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2893         }
2894
2895         return IRQ_HANDLED;
2896 }
2897
2898 /* Interrupt Handler for Transmit complete */
2899 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2900 {
2901         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2902         unsigned long flags;
2903         u32 imask;
2904
2905         if (likely(napi_schedule_prep(&grp->napi_tx))) {
2906                 spin_lock_irqsave(&grp->grplock, flags);
2907                 imask = gfar_read(&grp->regs->imask);
2908                 imask &= IMASK_TX_DISABLED;
2909                 gfar_write(&grp->regs->imask, imask);
2910                 spin_unlock_irqrestore(&grp->grplock, flags);
2911                 __napi_schedule(&grp->napi_tx);
2912         } else {
2913                 /* Clear IEVENT, so interrupts aren't called again
2914                  * because of the packets that have already arrived.
2915                  */
2916                 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2917         }
2918
2919         return IRQ_HANDLED;
2920 }
2921
2922 static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus,
2923                              struct sk_buff *skb, bool first)
2924 {
2925         unsigned int size = lstatus & BD_LENGTH_MASK;
2926         struct page *page = rxb->page;
2927
2928         /* Remove the FCS from the packet length */
2929         if (likely(lstatus & BD_LFLAG(RXBD_LAST)))
2930                 size -= ETH_FCS_LEN;
2931
2932         if (likely(first))
2933                 skb_put(skb, size);
2934         else
2935                 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
2936                                 rxb->page_offset + RXBUF_ALIGNMENT,
2937                                 size, GFAR_RXB_TRUESIZE);
2938
2939         /* try reuse page */
2940         if (unlikely(page_count(page) != 1))
2941                 return false;
2942
2943         /* change offset to the other half */
2944         rxb->page_offset ^= GFAR_RXB_TRUESIZE;
2945
2946         atomic_inc(&page->_count);
2947
2948         return true;
2949 }
2950
2951 static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq,
2952                                struct gfar_rx_buff *old_rxb)
2953 {
2954         struct gfar_rx_buff *new_rxb;
2955         u16 nta = rxq->next_to_alloc;
2956
2957         new_rxb = &rxq->rx_buff[nta];
2958
2959         /* find next buf that can reuse a page */
2960         nta++;
2961         rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0;
2962
2963         /* copy page reference */
2964         *new_rxb = *old_rxb;
2965
2966         /* sync for use by the device */
2967         dma_sync_single_range_for_device(rxq->dev, old_rxb->dma,
2968                                          old_rxb->page_offset,
2969                                          GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2970 }
2971
2972 static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue,
2973                                             u32 lstatus, struct sk_buff *skb)
2974 {
2975         struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean];
2976         struct page *page = rxb->page;
2977         bool first = false;
2978
2979         if (likely(!skb)) {
2980                 void *buff_addr = page_address(page) + rxb->page_offset;
2981
2982                 skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE);
2983                 if (unlikely(!skb)) {
2984                         gfar_rx_alloc_err(rx_queue);
2985                         return NULL;
2986                 }
2987                 skb_reserve(skb, RXBUF_ALIGNMENT);
2988                 first = true;
2989         }
2990
2991         dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset,
2992                                       GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2993
2994         if (gfar_add_rx_frag(rxb, lstatus, skb, first)) {
2995                 /* reuse the free half of the page */
2996                 gfar_reuse_rx_page(rx_queue, rxb);
2997         } else {
2998                 /* page cannot be reused, unmap it */
2999                 dma_unmap_page(rx_queue->dev, rxb->dma,
3000                                PAGE_SIZE, DMA_FROM_DEVICE);
3001         }
3002
3003         /* clear rxb content */
3004         rxb->page = NULL;
3005
3006         return skb;
3007 }
3008
3009 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
3010 {
3011         /* If valid headers were found, and valid sums
3012          * were verified, then we tell the kernel that no
3013          * checksumming is necessary.  Otherwise, it is [FIXME]
3014          */
3015         if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
3016             (RXFCB_CIP | RXFCB_CTU))
3017                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3018         else
3019                 skb_checksum_none_assert(skb);
3020 }
3021
3022 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
3023 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb)
3024 {
3025         struct gfar_private *priv = netdev_priv(ndev);
3026         struct rxfcb *fcb = NULL;
3027
3028         /* fcb is at the beginning if exists */
3029         fcb = (struct rxfcb *)skb->data;
3030
3031         /* Remove the FCB from the skb
3032          * Remove the padded bytes, if there are any
3033          */
3034         if (priv->uses_rxfcb)
3035                 skb_pull(skb, GMAC_FCB_LEN);
3036
3037         /* Get receive timestamp from the skb */
3038         if (priv->hwts_rx_en) {
3039                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
3040                 u64 *ns = (u64 *) skb->data;
3041
3042                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
3043                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
3044         }
3045
3046         if (priv->padding)
3047                 skb_pull(skb, priv->padding);
3048
3049         if (ndev->features & NETIF_F_RXCSUM)
3050                 gfar_rx_checksum(skb, fcb);
3051
3052         /* Tell the skb what kind of packet this is */
3053         skb->protocol = eth_type_trans(skb, ndev);
3054
3055         /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
3056          * Even if vlan rx accel is disabled, on some chips
3057          * RXFCB_VLN is pseudo randomly set.
3058          */
3059         if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX &&
3060             be16_to_cpu(fcb->flags) & RXFCB_VLN)
3061                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
3062                                        be16_to_cpu(fcb->vlctl));
3063 }
3064
3065 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
3066  * until the budget/quota has been reached. Returns the number
3067  * of frames handled
3068  */
3069 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
3070 {
3071         struct net_device *ndev = rx_queue->ndev;
3072         struct gfar_private *priv = netdev_priv(ndev);
3073         struct rxbd8 *bdp;
3074         int i, howmany = 0;
3075         struct sk_buff *skb = rx_queue->skb;
3076         int cleaned_cnt = gfar_rxbd_unused(rx_queue);
3077         unsigned int total_bytes = 0, total_pkts = 0;
3078
3079         /* Get the first full descriptor */
3080         i = rx_queue->next_to_clean;
3081
3082         while (rx_work_limit--) {
3083                 u32 lstatus;
3084
3085                 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) {
3086                         gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3087                         cleaned_cnt = 0;
3088                 }
3089
3090                 bdp = &rx_queue->rx_bd_base[i];
3091                 lstatus = be32_to_cpu(bdp->lstatus);
3092                 if (lstatus & BD_LFLAG(RXBD_EMPTY))
3093                         break;
3094
3095                 /* order rx buffer descriptor reads */
3096                 rmb();
3097
3098                 /* fetch next to clean buffer from the ring */
3099                 skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb);
3100                 if (unlikely(!skb))
3101                         break;
3102
3103                 cleaned_cnt++;
3104                 howmany++;
3105
3106                 if (unlikely(++i == rx_queue->rx_ring_size))
3107                         i = 0;
3108
3109                 rx_queue->next_to_clean = i;
3110
3111                 /* fetch next buffer if not the last in frame */
3112                 if (!(lstatus & BD_LFLAG(RXBD_LAST)))
3113                         continue;
3114
3115                 if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) {
3116                         count_errors(lstatus, ndev);
3117
3118                         /* discard faulty buffer */
3119                         dev_kfree_skb(skb);
3120                         skb = NULL;
3121                         rx_queue->stats.rx_dropped++;
3122                         continue;
3123                 }
3124
3125                 /* Increment the number of packets */
3126                 total_pkts++;
3127                 total_bytes += skb->len;
3128
3129                 skb_record_rx_queue(skb, rx_queue->qindex);
3130
3131                 gfar_process_frame(ndev, skb);
3132
3133                 /* Send the packet up the stack */
3134                 napi_gro_receive(&rx_queue->grp->napi_rx, skb);
3135
3136                 skb = NULL;
3137         }
3138
3139         /* Store incomplete frames for completion */
3140         rx_queue->skb = skb;
3141
3142         rx_queue->stats.rx_packets += total_pkts;
3143         rx_queue->stats.rx_bytes += total_bytes;
3144
3145         if (cleaned_cnt)
3146                 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3147
3148         /* Update Last Free RxBD pointer for LFC */
3149         if (unlikely(priv->tx_actual_en)) {
3150                 u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3151
3152                 gfar_write(rx_queue->rfbptr, bdp_dma);
3153         }
3154
3155         return howmany;
3156 }
3157
3158 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
3159 {
3160         struct gfar_priv_grp *gfargrp =
3161                 container_of(napi, struct gfar_priv_grp, napi_rx);
3162         struct gfar __iomem *regs = gfargrp->regs;
3163         struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
3164         int work_done = 0;
3165
3166         /* Clear IEVENT, so interrupts aren't called again
3167          * because of the packets that have already arrived
3168          */
3169         gfar_write(&regs->ievent, IEVENT_RX_MASK);
3170
3171         work_done = gfar_clean_rx_ring(rx_queue, budget);
3172
3173         if (work_done < budget) {
3174                 u32 imask;
3175                 napi_complete(napi);
3176                 /* Clear the halt bit in RSTAT */
3177                 gfar_write(&regs->rstat, gfargrp->rstat);
3178
3179                 spin_lock_irq(&gfargrp->grplock);
3180                 imask = gfar_read(&regs->imask);
3181                 imask |= IMASK_RX_DEFAULT;
3182                 gfar_write(&regs->imask, imask);
3183                 spin_unlock_irq(&gfargrp->grplock);
3184         }
3185
3186         return work_done;
3187 }
3188
3189 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
3190 {
3191         struct gfar_priv_grp *gfargrp =
3192                 container_of(napi, struct gfar_priv_grp, napi_tx);
3193         struct gfar __iomem *regs = gfargrp->regs;
3194         struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
3195         u32 imask;
3196
3197         /* Clear IEVENT, so interrupts aren't called again
3198          * because of the packets that have already arrived
3199          */
3200         gfar_write(&regs->ievent, IEVENT_TX_MASK);
3201
3202         /* run Tx cleanup to completion */
3203         if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
3204                 gfar_clean_tx_ring(tx_queue);
3205
3206         napi_complete(napi);
3207
3208         spin_lock_irq(&gfargrp->grplock);
3209         imask = gfar_read(&regs->imask);
3210         imask |= IMASK_TX_DEFAULT;
3211         gfar_write(&regs->imask, imask);
3212         spin_unlock_irq(&gfargrp->grplock);
3213
3214         return 0;
3215 }
3216
3217 static int gfar_poll_rx(struct napi_struct *napi, int budget)
3218 {
3219         struct gfar_priv_grp *gfargrp =
3220                 container_of(napi, struct gfar_priv_grp, napi_rx);
3221         struct gfar_private *priv = gfargrp->priv;
3222         struct gfar __iomem *regs = gfargrp->regs;
3223         struct gfar_priv_rx_q *rx_queue = NULL;
3224         int work_done = 0, work_done_per_q = 0;
3225         int i, budget_per_q = 0;
3226         unsigned long rstat_rxf;
3227         int num_act_queues;
3228
3229         /* Clear IEVENT, so interrupts aren't called again
3230          * because of the packets that have already arrived
3231          */
3232         gfar_write(&regs->ievent, IEVENT_RX_MASK);
3233
3234         rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
3235
3236         num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
3237         if (num_act_queues)
3238                 budget_per_q = budget/num_act_queues;
3239
3240         for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
3241                 /* skip queue if not active */
3242                 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
3243                         continue;
3244
3245                 rx_queue = priv->rx_queue[i];
3246                 work_done_per_q =
3247                         gfar_clean_rx_ring(rx_queue, budget_per_q);
3248                 work_done += work_done_per_q;
3249
3250                 /* finished processing this queue */
3251                 if (work_done_per_q < budget_per_q) {
3252                         /* clear active queue hw indication */
3253                         gfar_write(&regs->rstat,
3254                                    RSTAT_CLEAR_RXF0 >> i);
3255                         num_act_queues--;
3256
3257                         if (!num_act_queues)
3258                                 break;
3259                 }
3260         }
3261
3262         if (!num_act_queues) {
3263                 u32 imask;
3264                 napi_complete(napi);
3265
3266                 /* Clear the halt bit in RSTAT */
3267                 gfar_write(&regs->rstat, gfargrp->rstat);
3268
3269                 spin_lock_irq(&gfargrp->grplock);
3270                 imask = gfar_read(&regs->imask);
3271                 imask |= IMASK_RX_DEFAULT;
3272                 gfar_write(&regs->imask, imask);
3273                 spin_unlock_irq(&gfargrp->grplock);
3274         }
3275
3276         return work_done;
3277 }
3278
3279 static int gfar_poll_tx(struct napi_struct *napi, int budget)
3280 {
3281         struct gfar_priv_grp *gfargrp =
3282                 container_of(napi, struct gfar_priv_grp, napi_tx);
3283         struct gfar_private *priv = gfargrp->priv;
3284         struct gfar __iomem *regs = gfargrp->regs;
3285         struct gfar_priv_tx_q *tx_queue = NULL;
3286         int has_tx_work = 0;
3287         int i;
3288
3289         /* Clear IEVENT, so interrupts aren't called again
3290          * because of the packets that have already arrived
3291          */
3292         gfar_write(&regs->ievent, IEVENT_TX_MASK);
3293
3294         for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
3295                 tx_queue = priv->tx_queue[i];
3296                 /* run Tx cleanup to completion */
3297                 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
3298                         gfar_clean_tx_ring(tx_queue);
3299                         has_tx_work = 1;
3300                 }
3301         }
3302
3303         if (!has_tx_work) {
3304                 u32 imask;
3305                 napi_complete(napi);
3306
3307                 spin_lock_irq(&gfargrp->grplock);
3308                 imask = gfar_read(&regs->imask);
3309                 imask |= IMASK_TX_DEFAULT;
3310                 gfar_write(&regs->imask, imask);
3311                 spin_unlock_irq(&gfargrp->grplock);
3312         }
3313
3314         return 0;
3315 }
3316
3317
3318 #ifdef CONFIG_NET_POLL_CONTROLLER
3319 /* Polling 'interrupt' - used by things like netconsole to send skbs
3320  * without having to re-enable interrupts. It's not called while
3321  * the interrupt routine is executing.
3322  */
3323 static void gfar_netpoll(struct net_device *dev)
3324 {
3325         struct gfar_private *priv = netdev_priv(dev);
3326         int i;
3327
3328         /* If the device has multiple interrupts, run tx/rx */
3329         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3330                 for (i = 0; i < priv->num_grps; i++) {
3331                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3332
3333                         disable_irq(gfar_irq(grp, TX)->irq);
3334                         disable_irq(gfar_irq(grp, RX)->irq);
3335                         disable_irq(gfar_irq(grp, ER)->irq);
3336                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3337                         enable_irq(gfar_irq(grp, ER)->irq);
3338                         enable_irq(gfar_irq(grp, RX)->irq);
3339                         enable_irq(gfar_irq(grp, TX)->irq);
3340                 }
3341         } else {
3342                 for (i = 0; i < priv->num_grps; i++) {
3343                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3344
3345                         disable_irq(gfar_irq(grp, TX)->irq);
3346                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3347                         enable_irq(gfar_irq(grp, TX)->irq);
3348                 }
3349         }
3350 }
3351 #endif
3352
3353 /* The interrupt handler for devices with one interrupt */
3354 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
3355 {
3356         struct gfar_priv_grp *gfargrp = grp_id;
3357
3358         /* Save ievent for future reference */
3359         u32 events = gfar_read(&gfargrp->regs->ievent);
3360
3361         /* Check for reception */
3362         if (events & IEVENT_RX_MASK)
3363                 gfar_receive(irq, grp_id);
3364
3365         /* Check for transmit completion */
3366         if (events & IEVENT_TX_MASK)
3367                 gfar_transmit(irq, grp_id);
3368
3369         /* Check for errors */
3370         if (events & IEVENT_ERR_MASK)
3371                 gfar_error(irq, grp_id);
3372
3373         return IRQ_HANDLED;
3374 }
3375
3376 /* Called every time the controller might need to be made
3377  * aware of new link state.  The PHY code conveys this
3378  * information through variables in the phydev structure, and this
3379  * function converts those variables into the appropriate
3380  * register values, and can bring down the device if needed.
3381  */
3382 static void adjust_link(struct net_device *dev)
3383 {
3384         struct gfar_private *priv = netdev_priv(dev);
3385         struct phy_device *phydev = priv->phydev;
3386
3387         if (unlikely(phydev->link != priv->oldlink ||
3388                      (phydev->link && (phydev->duplex != priv->oldduplex ||
3389                                        phydev->speed != priv->oldspeed))))
3390                 gfar_update_link_state(priv);
3391 }
3392
3393 /* Update the hash table based on the current list of multicast
3394  * addresses we subscribe to.  Also, change the promiscuity of
3395  * the device based on the flags (this function is called
3396  * whenever dev->flags is changed
3397  */
3398 static void gfar_set_multi(struct net_device *dev)
3399 {
3400         struct netdev_hw_addr *ha;
3401         struct gfar_private *priv = netdev_priv(dev);
3402         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3403         u32 tempval;
3404
3405         if (dev->flags & IFF_PROMISC) {
3406                 /* Set RCTRL to PROM */
3407                 tempval = gfar_read(&regs->rctrl);
3408                 tempval |= RCTRL_PROM;
3409                 gfar_write(&regs->rctrl, tempval);
3410         } else {
3411                 /* Set RCTRL to not PROM */
3412                 tempval = gfar_read(&regs->rctrl);
3413                 tempval &= ~(RCTRL_PROM);
3414                 gfar_write(&regs->rctrl, tempval);
3415         }
3416
3417         if (dev->flags & IFF_ALLMULTI) {
3418                 /* Set the hash to rx all multicast frames */
3419                 gfar_write(&regs->igaddr0, 0xffffffff);
3420                 gfar_write(&regs->igaddr1, 0xffffffff);
3421                 gfar_write(&regs->igaddr2, 0xffffffff);
3422                 gfar_write(&regs->igaddr3, 0xffffffff);
3423                 gfar_write(&regs->igaddr4, 0xffffffff);
3424                 gfar_write(&regs->igaddr5, 0xffffffff);
3425                 gfar_write(&regs->igaddr6, 0xffffffff);
3426                 gfar_write(&regs->igaddr7, 0xffffffff);
3427                 gfar_write(&regs->gaddr0, 0xffffffff);
3428                 gfar_write(&regs->gaddr1, 0xffffffff);
3429                 gfar_write(&regs->gaddr2, 0xffffffff);
3430                 gfar_write(&regs->gaddr3, 0xffffffff);
3431                 gfar_write(&regs->gaddr4, 0xffffffff);
3432                 gfar_write(&regs->gaddr5, 0xffffffff);
3433                 gfar_write(&regs->gaddr6, 0xffffffff);
3434                 gfar_write(&regs->gaddr7, 0xffffffff);
3435         } else {
3436                 int em_num;
3437                 int idx;
3438
3439                 /* zero out the hash */
3440                 gfar_write(&regs->igaddr0, 0x0);
3441                 gfar_write(&regs->igaddr1, 0x0);
3442                 gfar_write(&regs->igaddr2, 0x0);
3443                 gfar_write(&regs->igaddr3, 0x0);
3444                 gfar_write(&regs->igaddr4, 0x0);
3445                 gfar_write(&regs->igaddr5, 0x0);
3446                 gfar_write(&regs->igaddr6, 0x0);
3447                 gfar_write(&regs->igaddr7, 0x0);
3448                 gfar_write(&regs->gaddr0, 0x0);
3449                 gfar_write(&regs->gaddr1, 0x0);
3450                 gfar_write(&regs->gaddr2, 0x0);
3451                 gfar_write(&regs->gaddr3, 0x0);
3452                 gfar_write(&regs->gaddr4, 0x0);
3453                 gfar_write(&regs->gaddr5, 0x0);
3454                 gfar_write(&regs->gaddr6, 0x0);
3455                 gfar_write(&regs->gaddr7, 0x0);
3456
3457                 /* If we have extended hash tables, we need to
3458                  * clear the exact match registers to prepare for
3459                  * setting them
3460                  */
3461                 if (priv->extended_hash) {
3462                         em_num = GFAR_EM_NUM + 1;
3463                         gfar_clear_exact_match(dev);
3464                         idx = 1;
3465                 } else {
3466                         idx = 0;
3467                         em_num = 0;
3468                 }
3469
3470                 if (netdev_mc_empty(dev))
3471                         return;
3472
3473                 /* Parse the list, and set the appropriate bits */
3474                 netdev_for_each_mc_addr(ha, dev) {
3475                         if (idx < em_num) {
3476                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3477                                 idx++;
3478                         } else
3479                                 gfar_set_hash_for_addr(dev, ha->addr);
3480                 }
3481         }
3482 }
3483
3484
3485 /* Clears each of the exact match registers to zero, so they
3486  * don't interfere with normal reception
3487  */
3488 static void gfar_clear_exact_match(struct net_device *dev)
3489 {
3490         int idx;
3491         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3492
3493         for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3494                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3495 }
3496
3497 /* Set the appropriate hash bit for the given addr */
3498 /* The algorithm works like so:
3499  * 1) Take the Destination Address (ie the multicast address), and
3500  * do a CRC on it (little endian), and reverse the bits of the
3501  * result.
3502  * 2) Use the 8 most significant bits as a hash into a 256-entry
3503  * table.  The table is controlled through 8 32-bit registers:
3504  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3505  * gaddr7.  This means that the 3 most significant bits in the
3506  * hash index which gaddr register to use, and the 5 other bits
3507  * indicate which bit (assuming an IBM numbering scheme, which
3508  * for PowerPC (tm) is usually the case) in the register holds
3509  * the entry.
3510  */
3511 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3512 {
3513         u32 tempval;
3514         struct gfar_private *priv = netdev_priv(dev);
3515         u32 result = ether_crc(ETH_ALEN, addr);
3516         int width = priv->hash_width;
3517         u8 whichbit = (result >> (32 - width)) & 0x1f;
3518         u8 whichreg = result >> (32 - width + 5);
3519         u32 value = (1 << (31-whichbit));
3520
3521         tempval = gfar_read(priv->hash_regs[whichreg]);
3522         tempval |= value;
3523         gfar_write(priv->hash_regs[whichreg], tempval);
3524 }
3525
3526
3527 /* There are multiple MAC Address register pairs on some controllers
3528  * This function sets the numth pair to a given address
3529  */
3530 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3531                                   const u8 *addr)
3532 {
3533         struct gfar_private *priv = netdev_priv(dev);
3534         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3535         u32 tempval;
3536         u32 __iomem *macptr = &regs->macstnaddr1;
3537
3538         macptr += num*2;
3539
3540         /* For a station address of 0x12345678ABCD in transmission
3541          * order (BE), MACnADDR1 is set to 0xCDAB7856 and
3542          * MACnADDR2 is set to 0x34120000.
3543          */
3544         tempval = (addr[5] << 24) | (addr[4] << 16) |
3545                   (addr[3] << 8)  |  addr[2];
3546
3547         gfar_write(macptr, tempval);
3548
3549         tempval = (addr[1] << 24) | (addr[0] << 16);
3550
3551         gfar_write(macptr+1, tempval);
3552 }
3553
3554 /* GFAR error interrupt handler */
3555 static irqreturn_t gfar_error(int irq, void *grp_id)
3556 {
3557         struct gfar_priv_grp *gfargrp = grp_id;
3558         struct gfar __iomem *regs = gfargrp->regs;
3559         struct gfar_private *priv= gfargrp->priv;
3560         struct net_device *dev = priv->ndev;
3561
3562         /* Save ievent for future reference */
3563         u32 events = gfar_read(&regs->ievent);
3564
3565         /* Clear IEVENT */
3566         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3567
3568         /* Magic Packet is not an error. */
3569         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3570             (events & IEVENT_MAG))
3571                 events &= ~IEVENT_MAG;
3572
3573         /* Hmm... */
3574         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3575                 netdev_dbg(dev,
3576                            "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3577                            events, gfar_read(&regs->imask));
3578
3579         /* Update the error counters */
3580         if (events & IEVENT_TXE) {
3581                 dev->stats.tx_errors++;
3582
3583                 if (events & IEVENT_LC)
3584                         dev->stats.tx_window_errors++;
3585                 if (events & IEVENT_CRL)
3586                         dev->stats.tx_aborted_errors++;
3587                 if (events & IEVENT_XFUN) {
3588                         netif_dbg(priv, tx_err, dev,
3589                                   "TX FIFO underrun, packet dropped\n");
3590                         dev->stats.tx_dropped++;
3591                         atomic64_inc(&priv->extra_stats.tx_underrun);
3592
3593                         schedule_work(&priv->reset_task);
3594                 }
3595                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3596         }
3597         if (events & IEVENT_BSY) {
3598                 dev->stats.rx_over_errors++;
3599                 atomic64_inc(&priv->extra_stats.rx_bsy);
3600
3601                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3602                           gfar_read(&regs->rstat));
3603         }
3604         if (events & IEVENT_BABR) {
3605                 dev->stats.rx_errors++;
3606                 atomic64_inc(&priv->extra_stats.rx_babr);
3607
3608                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3609         }
3610         if (events & IEVENT_EBERR) {
3611                 atomic64_inc(&priv->extra_stats.eberr);
3612                 netif_dbg(priv, rx_err, dev, "bus error\n");
3613         }
3614         if (events & IEVENT_RXC)
3615                 netif_dbg(priv, rx_status, dev, "control frame\n");
3616
3617         if (events & IEVENT_BABT) {
3618                 atomic64_inc(&priv->extra_stats.tx_babt);
3619                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3620         }
3621         return IRQ_HANDLED;
3622 }
3623
3624 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3625 {
3626         struct phy_device *phydev = priv->phydev;
3627         u32 val = 0;
3628
3629         if (!phydev->duplex)
3630                 return val;
3631
3632         if (!priv->pause_aneg_en) {
3633                 if (priv->tx_pause_en)
3634                         val |= MACCFG1_TX_FLOW;
3635                 if (priv->rx_pause_en)
3636                         val |= MACCFG1_RX_FLOW;
3637         } else {
3638                 u16 lcl_adv, rmt_adv;
3639                 u8 flowctrl;
3640                 /* get link partner capabilities */
3641                 rmt_adv = 0;
3642                 if (phydev->pause)
3643                         rmt_adv = LPA_PAUSE_CAP;
3644                 if (phydev->asym_pause)
3645                         rmt_adv |= LPA_PAUSE_ASYM;
3646
3647                 lcl_adv = 0;
3648                 if (phydev->advertising & ADVERTISED_Pause)
3649                         lcl_adv |= ADVERTISE_PAUSE_CAP;
3650                 if (phydev->advertising & ADVERTISED_Asym_Pause)
3651                         lcl_adv |= ADVERTISE_PAUSE_ASYM;
3652
3653                 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3654                 if (flowctrl & FLOW_CTRL_TX)
3655                         val |= MACCFG1_TX_FLOW;
3656                 if (flowctrl & FLOW_CTRL_RX)
3657                         val |= MACCFG1_RX_FLOW;
3658         }
3659
3660         return val;
3661 }
3662
3663 static noinline void gfar_update_link_state(struct gfar_private *priv)
3664 {
3665         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3666         struct phy_device *phydev = priv->phydev;
3667         struct gfar_priv_rx_q *rx_queue = NULL;
3668         int i;
3669
3670         if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
3671                 return;
3672
3673         if (phydev->link) {
3674                 u32 tempval1 = gfar_read(&regs->maccfg1);
3675                 u32 tempval = gfar_read(&regs->maccfg2);
3676                 u32 ecntrl = gfar_read(&regs->ecntrl);
3677                 u32 tx_flow_oldval = (tempval & MACCFG1_TX_FLOW);
3678
3679                 if (phydev->duplex != priv->oldduplex) {
3680                         if (!(phydev->duplex))
3681                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
3682                         else
3683                                 tempval |= MACCFG2_FULL_DUPLEX;
3684
3685                         priv->oldduplex = phydev->duplex;
3686                 }
3687
3688                 if (phydev->speed != priv->oldspeed) {
3689                         switch (phydev->speed) {
3690                         case 1000:
3691                                 tempval =
3692                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3693
3694                                 ecntrl &= ~(ECNTRL_R100);
3695                                 break;
3696                         case 100:
3697                         case 10:
3698                                 tempval =
3699                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3700
3701                                 /* Reduced mode distinguishes
3702                                  * between 10 and 100
3703                                  */
3704                                 if (phydev->speed == SPEED_100)
3705                                         ecntrl |= ECNTRL_R100;
3706                                 else
3707                                         ecntrl &= ~(ECNTRL_R100);
3708                                 break;
3709                         default:
3710                                 netif_warn(priv, link, priv->ndev,
3711                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
3712                                            phydev->speed);
3713                                 break;
3714                         }
3715
3716                         priv->oldspeed = phydev->speed;
3717                 }
3718
3719                 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3720                 tempval1 |= gfar_get_flowctrl_cfg(priv);
3721
3722                 /* Turn last free buffer recording on */
3723                 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
3724                         for (i = 0; i < priv->num_rx_queues; i++) {
3725                                 u32 bdp_dma;
3726
3727                                 rx_queue = priv->rx_queue[i];
3728                                 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3729                                 gfar_write(rx_queue->rfbptr, bdp_dma);
3730                         }
3731
3732                         priv->tx_actual_en = 1;
3733                 }
3734
3735                 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
3736                         priv->tx_actual_en = 0;
3737
3738                 gfar_write(&regs->maccfg1, tempval1);
3739                 gfar_write(&regs->maccfg2, tempval);
3740                 gfar_write(&regs->ecntrl, ecntrl);
3741
3742                 if (!priv->oldlink)
3743                         priv->oldlink = 1;
3744
3745         } else if (priv->oldlink) {
3746                 priv->oldlink = 0;
3747                 priv->oldspeed = 0;
3748                 priv->oldduplex = -1;
3749         }
3750
3751         if (netif_msg_link(priv))
3752                 phy_print_status(phydev);
3753 }
3754
3755 static const struct of_device_id gfar_match[] =
3756 {
3757         {
3758                 .type = "network",
3759                 .compatible = "gianfar",
3760         },
3761         {
3762                 .compatible = "fsl,etsec2",
3763         },
3764         {},
3765 };
3766 MODULE_DEVICE_TABLE(of, gfar_match);
3767
3768 /* Structure for a device driver */
3769 static struct platform_driver gfar_driver = {
3770         .driver = {
3771                 .name = "fsl-gianfar",
3772                 .pm = GFAR_PM_OPS,
3773                 .of_match_table = gfar_match,
3774         },
3775         .probe = gfar_probe,
3776         .remove = gfar_remove,
3777 };
3778
3779 module_platform_driver(gfar_driver);