drivers/net/ethernet/freescale/gianfar.c

   1 /* drivers/net/ethernet/freescale/gianfar.c
   2  *
   3  * Gianfar Ethernet Driver
   4  * This driver is designed for the non-CPM ethernet controllers
   5  * on the 85xx and 83xx family of integrated processors
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala
  10  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11  *
  12  * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
  13  * Copyright 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  65 #define DEBUG
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/delay.h>
  74 #include <linux/netdevice.h>
  75 #include <linux/etherdevice.h>
  76 #include <linux/skbuff.h>
  77 #include <linux/if_vlan.h>
  78 #include <linux/spinlock.h>
  79 #include <linux/mm.h>
  80 #include <linux/of_address.h>
  81 #include <linux/of_irq.h>
  82 #include <linux/of_mdio.h>
  83 #include <linux/of_platform.h>
  84 #include <linux/ip.h>
  85 #include <linux/tcp.h>
  86 #include <linux/udp.h>
  87 #include <linux/in.h>
  88 #include <linux/net_tstamp.h>
  89
  90 #include <asm/io.h>
  91 #ifdef CONFIG_PPC
  92 #include <asm/reg.h>
  93 #include <asm/mpc85xx.h>
  94 #endif
  95 #include <asm/irq.h>
  96 #include <asm/uaccess.h>
  97 #include <linux/module.h>
  98 #include <linux/dma-mapping.h>
  99 #include <linux/crc32.h>
 100 #include <linux/mii.h>
 101 #include <linux/phy.h>
 102 #include <linux/phy_fixed.h>
 103 #include <linux/of.h>
 104 #include <linux/of_net.h>
 105 #include <linux/of_address.h>
 106 #include <linux/of_irq.h>
 107
 108 #include "gianfar.h"
 109
 110 #define TX_TIMEOUT      (1*HZ)
 111
 112 const char gfar_driver_version[] = "2.0";
 113
 114 static int gfar_enet_open(struct net_device *dev);
 115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 116 static void gfar_reset_task(struct work_struct *work);
 117 static void gfar_timeout(struct net_device *dev);
 118 static int gfar_close(struct net_device *dev);
 119 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
 120                                 int alloc_cnt);
 121 static int gfar_set_mac_address(struct net_device *dev);
 122 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 123 static irqreturn_t gfar_error(int irq, void *dev_id);
 124 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 125 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 126 static void adjust_link(struct net_device *dev);
 127 static noinline void gfar_update_link_state(struct gfar_private *priv);
 128 static int init_phy(struct net_device *dev);
 129 static int gfar_probe(struct platform_device *ofdev);
 130 static int gfar_remove(struct platform_device *ofdev);
 131 static void free_skb_resources(struct gfar_private *priv);
 132 static void gfar_set_multi(struct net_device *dev);
 133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 134 static void gfar_configure_serdes(struct net_device *dev);
 135 static int gfar_poll_rx(struct napi_struct *napi, int budget);
 136 static int gfar_poll_tx(struct napi_struct *napi, int budget);
 137 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget);
 138 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget);
 139 #ifdef CONFIG_NET_POLL_CONTROLLER
 140 static void gfar_netpoll(struct net_device *dev);
 141 #endif
 142 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 143 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 144 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb);
 145 static void gfar_halt_nodisable(struct gfar_private *priv);
 146 static void gfar_clear_exact_match(struct net_device *dev);
 147 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 148                                   const u8 *addr);
 149 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 150
 151 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 152 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 153 MODULE_LICENSE("GPL");
 154
 155 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 156                             dma_addr_t buf)
 157 {
 158         u32 lstatus;
 159
 160         bdp->bufPtr = cpu_to_be32(buf);
 161
 162         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 163         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 164                 lstatus |= BD_LFLAG(RXBD_WRAP);
 165
 166         gfar_wmb();
 167
 168         bdp->lstatus = cpu_to_be32(lstatus);
 169 }
 170
 171 static void gfar_init_bds(struct net_device *ndev)
 172 {
 173         struct gfar_private *priv = netdev_priv(ndev);
 174         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 175         struct gfar_priv_tx_q *tx_queue = NULL;
 176         struct gfar_priv_rx_q *rx_queue = NULL;
 177         struct txbd8 *txbdp;
 178         u32 __iomem *rfbptr;
 179         int i, j;
 180
 181         for (i = 0; i < priv->num_tx_queues; i++) {
 182                 tx_queue = priv->tx_queue[i];
 183                 /* Initialize some variables in our dev structure */
 184                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 185                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 186                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 187                 tx_queue->skb_curtx = 0;
 188                 tx_queue->skb_dirtytx = 0;
 189
 190                 /* Initialize Transmit Descriptor Ring */
 191                 txbdp = tx_queue->tx_bd_base;
 192                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 193                         txbdp->lstatus = 0;
 194                         txbdp->bufPtr = 0;
 195                         txbdp++;
 196                 }
 197
 198                 /* Set the last descriptor in the ring to indicate wrap */
 199                 txbdp--;
 200                 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
 201                                             TXBD_WRAP);
 202         }
 203
 204         rfbptr = &regs->rfbptr0;
 205         for (i = 0; i < priv->num_rx_queues; i++) {
 206                 rx_queue = priv->rx_queue[i];
 207
 208                 rx_queue->next_to_clean = 0;
 209                 rx_queue->next_to_use = 0;
 210                 rx_queue->next_to_alloc = 0;
 211
 212                 /* make sure next_to_clean != next_to_use after this
 213                  * by leaving at least 1 unused descriptor
 214                  */
 215                 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue));
 216
 217                 rx_queue->rfbptr = rfbptr;
 218                 rfbptr += 2;
 219         }
 220 }
 221
 222 static int gfar_alloc_skb_resources(struct net_device *ndev)
 223 {
 224         void *vaddr;
 225         dma_addr_t addr;
 226         int i, j;
 227         struct gfar_private *priv = netdev_priv(ndev);
 228         struct device *dev = priv->dev;
 229         struct gfar_priv_tx_q *tx_queue = NULL;
 230         struct gfar_priv_rx_q *rx_queue = NULL;
 231
 232         priv->total_tx_ring_size = 0;
 233         for (i = 0; i < priv->num_tx_queues; i++)
 234                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 235
 236         priv->total_rx_ring_size = 0;
 237         for (i = 0; i < priv->num_rx_queues; i++)
 238                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 239
 240         /* Allocate memory for the buffer descriptors */
 241         vaddr = dma_alloc_coherent(dev,
 242                                    (priv->total_tx_ring_size *
 243                                     sizeof(struct txbd8)) +
 244                                    (priv->total_rx_ring_size *
 245                                     sizeof(struct rxbd8)),
 246                                    &addr, GFP_KERNEL);
 247         if (!vaddr)
 248                 return -ENOMEM;
 249
 250         for (i = 0; i < priv->num_tx_queues; i++) {
 251                 tx_queue = priv->tx_queue[i];
 252                 tx_queue->tx_bd_base = vaddr;
 253                 tx_queue->tx_bd_dma_base = addr;
 254                 tx_queue->dev = ndev;
 255                 /* enet DMA only understands physical addresses */
 256                 addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 257                 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 258         }
 259
 260         /* Start the rx descriptor ring where the tx ring leaves off */
 261         for (i = 0; i < priv->num_rx_queues; i++) {
 262                 rx_queue = priv->rx_queue[i];
 263                 rx_queue->rx_bd_base = vaddr;
 264                 rx_queue->rx_bd_dma_base = addr;
 265                 rx_queue->ndev = ndev;
 266                 rx_queue->dev = dev;
 267                 addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 268                 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 269         }
 270
 271         /* Setup the skbuff rings */
 272         for (i = 0; i < priv->num_tx_queues; i++) {
 273                 tx_queue = priv->tx_queue[i];
 274                 tx_queue->tx_skbuff =
 275                         kmalloc_array(tx_queue->tx_ring_size,
 276                                       sizeof(*tx_queue->tx_skbuff),
 277                                       GFP_KERNEL);
 278                 if (!tx_queue->tx_skbuff)
 279                         goto cleanup;
 280
 281                 for (j = 0; j < tx_queue->tx_ring_size; j++)
 282                         tx_queue->tx_skbuff[j] = NULL;
 283         }
 284
 285         for (i = 0; i < priv->num_rx_queues; i++) {
 286                 rx_queue = priv->rx_queue[i];
 287                 rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size,
 288                                             sizeof(*rx_queue->rx_buff),
 289                                             GFP_KERNEL);
 290                 if (!rx_queue->rx_buff)
 291                         goto cleanup;
 292         }
 293
 294         gfar_init_bds(ndev);
 295
 296         return 0;
 297
 298 cleanup:
 299         free_skb_resources(priv);
 300         return -ENOMEM;
 301 }
 302
 303 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 304 {
 305         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 306         u32 __iomem *baddr;
 307         int i;
 308
 309         baddr = &regs->tbase0;
 310         for (i = 0; i < priv->num_tx_queues; i++) {
 311                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 312                 baddr += 2;
 313         }
 314
 315         baddr = &regs->rbase0;
 316         for (i = 0; i < priv->num_rx_queues; i++) {
 317                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 318                 baddr += 2;
 319         }
 320 }
 321
 322 static void gfar_init_rqprm(struct gfar_private *priv)
 323 {
 324         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 325         u32 __iomem *baddr;
 326         int i;
 327
 328         baddr = &regs->rqprm0;
 329         for (i = 0; i < priv->num_rx_queues; i++) {
 330                 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
 331                            (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
 332                 baddr++;
 333         }
 334 }
 335
 336 static void gfar_rx_offload_en(struct gfar_private *priv)
 337 {
 338         /* set this when rx hw offload (TOE) functions are being used */
 339         priv->uses_rxfcb = 0;
 340
 341         if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
 342                 priv->uses_rxfcb = 1;
 343
 344         if (priv->hwts_rx_en || priv->rx_filer_enable)
 345                 priv->uses_rxfcb = 1;
 346 }
 347
 348 static void gfar_mac_rx_config(struct gfar_private *priv)
 349 {
 350         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 351         u32 rctrl = 0;
 352
 353         if (priv->rx_filer_enable) {
 354                 rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
 355                 /* Program the RIR0 reg with the required distribution */
 356                 if (priv->poll_mode == GFAR_SQ_POLLING)
 357                         gfar_write(&regs->rir0, DEFAULT_2RXQ_RIR0);
 358                 else /* GFAR_MQ_POLLING */
 359                         gfar_write(&regs->rir0, DEFAULT_8RXQ_RIR0);
 360         }
 361
 362         /* Restore PROMISC mode */
 363         if (priv->ndev->flags & IFF_PROMISC)
 364                 rctrl |= RCTRL_PROM;
 365
 366         if (priv->ndev->features & NETIF_F_RXCSUM)
 367                 rctrl |= RCTRL_CHECKSUMMING;
 368
 369         if (priv->extended_hash)
 370                 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
 371
 372         if (priv->padding) {
 373                 rctrl &= ~RCTRL_PAL_MASK;
 374                 rctrl |= RCTRL_PADDING(priv->padding);
 375         }
 376
 377         /* Enable HW time stamping if requested from user space */
 378         if (priv->hwts_rx_en)
 379                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 380
 381         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
 382                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 383
 384         /* Clear the LFC bit */
 385         gfar_write(&regs->rctrl, rctrl);
 386         /* Init flow control threshold values */
 387         gfar_init_rqprm(priv);
 388         gfar_write(&regs->ptv, DEFAULT_LFC_PTVVAL);
 389         rctrl |= RCTRL_LFC;
 390
 391         /* Init rctrl based on our settings */
 392         gfar_write(&regs->rctrl, rctrl);
 393 }
 394
 395 static void gfar_mac_tx_config(struct gfar_private *priv)
 396 {
 397         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 398         u32 tctrl = 0;
 399
 400         if (priv->ndev->features & NETIF_F_IP_CSUM)
 401                 tctrl |= TCTRL_INIT_CSUM;
 402
 403         if (priv->prio_sched_en)
 404                 tctrl |= TCTRL_TXSCHED_PRIO;
 405         else {
 406                 tctrl |= TCTRL_TXSCHED_WRRS;
 407                 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
 408                 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
 409         }
 410
 411         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
 412                 tctrl |= TCTRL_VLINS;
 413
 414         gfar_write(&regs->tctrl, tctrl);
 415 }
 416
 417 static void gfar_configure_coalescing(struct gfar_private *priv,
 418                                unsigned long tx_mask, unsigned long rx_mask)
 419 {
 420         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 421         u32 __iomem *baddr;
 422
 423         if (priv->mode == MQ_MG_MODE) {
 424                 int i = 0;
 425
 426                 baddr = &regs->txic0;
 427                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
 428                         gfar_write(baddr + i, 0);
 429                         if (likely(priv->tx_queue[i]->txcoalescing))
 430                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
 431                 }
 432
 433                 baddr = &regs->rxic0;
 434                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
 435                         gfar_write(baddr + i, 0);
 436                         if (likely(priv->rx_queue[i]->rxcoalescing))
 437                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
 438                 }
 439         } else {
 440                 /* Backward compatible case -- even if we enable
 441                  * multiple queues, there's only single reg to program
 442                  */
 443                 gfar_write(&regs->txic, 0);
 444                 if (likely(priv->tx_queue[0]->txcoalescing))
 445                         gfar_write(&regs->txic, priv->tx_queue[0]->txic);
 446
 447                 gfar_write(&regs->rxic, 0);
 448                 if (unlikely(priv->rx_queue[0]->rxcoalescing))
 449                         gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
 450         }
 451 }
 452
 453 void gfar_configure_coalescing_all(struct gfar_private *priv)
 454 {
 455         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 456 }
 457
 458 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 459 {
 460         struct gfar_private *priv = netdev_priv(dev);
 461         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 462         unsigned long tx_packets = 0, tx_bytes = 0;
 463         int i;
 464
 465         for (i = 0; i < priv->num_rx_queues; i++) {
 466                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 467                 rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
 468                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 469         }
 470
 471         dev->stats.rx_packets = rx_packets;
 472         dev->stats.rx_bytes   = rx_bytes;
 473         dev->stats.rx_dropped = rx_dropped;
 474
 475         for (i = 0; i < priv->num_tx_queues; i++) {
 476                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 477                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 478         }
 479
 480         dev->stats.tx_bytes   = tx_bytes;
 481         dev->stats.tx_packets = tx_packets;
 482
 483         return &dev->stats;
 484 }
 485
 486 static int gfar_set_mac_addr(struct net_device *dev, void *p)
 487 {
 488         eth_mac_addr(dev, p);
 489
 490         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
 491
 492         return 0;
 493 }
 494
 495 static const struct net_device_ops gfar_netdev_ops = {
 496         .ndo_open = gfar_enet_open,
 497         .ndo_start_xmit = gfar_start_xmit,
 498         .ndo_stop = gfar_close,
 499         .ndo_change_mtu = gfar_change_mtu,
 500         .ndo_set_features = gfar_set_features,
 501         .ndo_set_rx_mode = gfar_set_multi,
 502         .ndo_tx_timeout = gfar_timeout,
 503         .ndo_do_ioctl = gfar_ioctl,
 504         .ndo_get_stats = gfar_get_stats,
 505         .ndo_set_mac_address = gfar_set_mac_addr,
 506         .ndo_validate_addr = eth_validate_addr,
 507 #ifdef CONFIG_NET_POLL_CONTROLLER
 508         .ndo_poll_controller = gfar_netpoll,
 509 #endif
 510 };
 511
 512 static void gfar_ints_disable(struct gfar_private *priv)
 513 {
 514         int i;
 515         for (i = 0; i < priv->num_grps; i++) {
 516                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 517                 /* Clear IEVENT */
 518                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 519
 520                 /* Initialize IMASK */
 521                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 522         }
 523 }
 524
 525 static void gfar_ints_enable(struct gfar_private *priv)
 526 {
 527         int i;
 528         for (i = 0; i < priv->num_grps; i++) {
 529                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 530                 /* Unmask the interrupts we look for */
 531                 gfar_write(&regs->imask, IMASK_DEFAULT);
 532         }
 533 }
 534
 535 static int gfar_alloc_tx_queues(struct gfar_private *priv)
 536 {
 537         int i;
 538
 539         for (i = 0; i < priv->num_tx_queues; i++) {
 540                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 541                                             GFP_KERNEL);
 542                 if (!priv->tx_queue[i])
 543                         return -ENOMEM;
 544
 545                 priv->tx_queue[i]->tx_skbuff = NULL;
 546                 priv->tx_queue[i]->qindex = i;
 547                 priv->tx_queue[i]->dev = priv->ndev;
 548                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 549         }
 550         return 0;
 551 }
 552
 553 static int gfar_alloc_rx_queues(struct gfar_private *priv)
 554 {
 555         int i;
 556
 557         for (i = 0; i < priv->num_rx_queues; i++) {
 558                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 559                                             GFP_KERNEL);
 560                 if (!priv->rx_queue[i])
 561                         return -ENOMEM;
 562
 563                 priv->rx_queue[i]->qindex = i;
 564                 priv->rx_queue[i]->ndev = priv->ndev;
 565         }
 566         return 0;
 567 }
 568
 569 static void gfar_free_tx_queues(struct gfar_private *priv)
 570 {
 571         int i;
 572
 573         for (i = 0; i < priv->num_tx_queues; i++)
 574                 kfree(priv->tx_queue[i]);
 575 }
 576
 577 static void gfar_free_rx_queues(struct gfar_private *priv)
 578 {
 579         int i;
 580
 581         for (i = 0; i < priv->num_rx_queues; i++)
 582                 kfree(priv->rx_queue[i]);
 583 }
 584
 585 static void unmap_group_regs(struct gfar_private *priv)
 586 {
 587         int i;
 588
 589         for (i = 0; i < MAXGROUPS; i++)
 590                 if (priv->gfargrp[i].regs)
 591                         iounmap(priv->gfargrp[i].regs);
 592 }
 593
 594 static void free_gfar_dev(struct gfar_private *priv)
 595 {
 596         int i, j;
 597
 598         for (i = 0; i < priv->num_grps; i++)
 599                 for (j = 0; j < GFAR_NUM_IRQS; j++) {
 600                         kfree(priv->gfargrp[i].irqinfo[j]);
 601                         priv->gfargrp[i].irqinfo[j] = NULL;
 602                 }
 603
 604         free_netdev(priv->ndev);
 605 }
 606
 607 static void disable_napi(struct gfar_private *priv)
 608 {
 609         int i;
 610
 611         for (i = 0; i < priv->num_grps; i++) {
 612                 napi_disable(&priv->gfargrp[i].napi_rx);
 613                 napi_disable(&priv->gfargrp[i].napi_tx);
 614         }
 615 }
 616
 617 static void enable_napi(struct gfar_private *priv)
 618 {
 619         int i;
 620
 621         for (i = 0; i < priv->num_grps; i++) {
 622                 napi_enable(&priv->gfargrp[i].napi_rx);
 623                 napi_enable(&priv->gfargrp[i].napi_tx);
 624         }
 625 }
 626
 627 static int gfar_parse_group(struct device_node *np,
 628                             struct gfar_private *priv, const char *model)
 629 {
 630         struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
 631         int i;
 632
 633         for (i = 0; i < GFAR_NUM_IRQS; i++) {
 634                 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
 635                                           GFP_KERNEL);
 636                 if (!grp->irqinfo[i])
 637                         return -ENOMEM;
 638         }
 639
 640         grp->regs = of_iomap(np, 0);
 641         if (!grp->regs)
 642                 return -ENOMEM;
 643
 644         gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
 645
 646         /* If we aren't the FEC we have multiple interrupts */
 647         if (model && strcasecmp(model, "FEC")) {
 648                 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
 649                 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
 650                 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
 651                     gfar_irq(grp, RX)->irq == NO_IRQ ||
 652                     gfar_irq(grp, ER)->irq == NO_IRQ)
 653                         return -EINVAL;
 654         }
 655
 656         grp->priv = priv;
 657         spin_lock_init(&grp->grplock);
 658         if (priv->mode == MQ_MG_MODE) {
 659                 u32 rxq_mask, txq_mask;
 660                 int ret;
 661
 662                 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 663                 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 664
 665                 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
 666                 if (!ret) {
 667                         grp->rx_bit_map = rxq_mask ?
 668                         rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 669                 }
 670
 671                 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
 672                 if (!ret) {
 673                         grp->tx_bit_map = txq_mask ?
 674                         txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 675                 }
 676
 677                 if (priv->poll_mode == GFAR_SQ_POLLING) {
 678                         /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
 679                         grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 680                         grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 681                 }
 682         } else {
 683                 grp->rx_bit_map = 0xFF;
 684                 grp->tx_bit_map = 0xFF;
 685         }
 686
 687         /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
 688          * right to left, so we need to revert the 8 bits to get the q index
 689          */
 690         grp->rx_bit_map = bitrev8(grp->rx_bit_map);
 691         grp->tx_bit_map = bitrev8(grp->tx_bit_map);
 692
 693         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
 694          * also assign queues to groups
 695          */
 696         for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
 697                 if (!grp->rx_queue)
 698                         grp->rx_queue = priv->rx_queue[i];
 699                 grp->num_rx_queues++;
 700                 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
 701                 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
 702                 priv->rx_queue[i]->grp = grp;
 703         }
 704
 705         for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
 706                 if (!grp->tx_queue)
 707                         grp->tx_queue = priv->tx_queue[i];
 708                 grp->num_tx_queues++;
 709                 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
 710                 priv->tqueue |= (TQUEUE_EN0 >> i);
 711                 priv->tx_queue[i]->grp = grp;
 712         }
 713
 714         priv->num_grps++;
 715
 716         return 0;
 717 }
 718
 719 static int gfar_of_group_count(struct device_node *np)
 720 {
 721         struct device_node *child;
 722         int num = 0;
 723
 724         for_each_available_child_of_node(np, child)
 725                 if (!of_node_cmp(child->name, "queue-group"))
 726                         num++;
 727
 728         return num;
 729 }
 730
 731 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 732 {
 733         const char *model;
 734         const char *ctype;
 735         const void *mac_addr;
 736         int err = 0, i;
 737         struct net_device *dev = NULL;
 738         struct gfar_private *priv = NULL;
 739         struct device_node *np = ofdev->dev.of_node;
 740         struct device_node *child = NULL;
 741         struct property *stash;
 742         u32 stash_len = 0;
 743         u32 stash_idx = 0;
 744         unsigned int num_tx_qs, num_rx_qs;
 745         unsigned short mode, poll_mode;
 746
 747         if (!np)
 748                 return -ENODEV;
 749
 750         if (of_device_is_compatible(np, "fsl,etsec2")) {
 751                 mode = MQ_MG_MODE;
 752                 poll_mode = GFAR_SQ_POLLING;
 753         } else {
 754                 mode = SQ_SG_MODE;
 755                 poll_mode = GFAR_SQ_POLLING;
 756         }
 757
 758         if (mode == SQ_SG_MODE) {
 759                 num_tx_qs = 1;
 760                 num_rx_qs = 1;
 761         } else { /* MQ_MG_MODE */
 762                 /* get the actual number of supported groups */
 763                 unsigned int num_grps = gfar_of_group_count(np);
 764
 765                 if (num_grps == 0 || num_grps > MAXGROUPS) {
 766                         dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
 767                                 num_grps);
 768                         pr_err("Cannot do alloc_etherdev, aborting\n");
 769                         return -EINVAL;
 770                 }
 771
 772                 if (poll_mode == GFAR_SQ_POLLING) {
 773                         num_tx_qs = num_grps; /* one txq per int group */
 774                         num_rx_qs = num_grps; /* one rxq per int group */
 775                 } else { /* GFAR_MQ_POLLING */
 776                         u32 tx_queues, rx_queues;
 777                         int ret;
 778
 779                         /* parse the num of HW tx and rx queues */
 780                         ret = of_property_read_u32(np, "fsl,num_tx_queues",
 781                                                    &tx_queues);
 782                         num_tx_qs = ret ? 1 : tx_queues;
 783
 784                         ret = of_property_read_u32(np, "fsl,num_rx_queues",
 785                                                    &rx_queues);
 786                         num_rx_qs = ret ? 1 : rx_queues;
 787                 }
 788         }
 789
 790         if (num_tx_qs > MAX_TX_QS) {
 791                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 792                        num_tx_qs, MAX_TX_QS);
 793                 pr_err("Cannot do alloc_etherdev, aborting\n");
 794                 return -EINVAL;
 795         }
 796
 797         if (num_rx_qs > MAX_RX_QS) {
 798                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 799                        num_rx_qs, MAX_RX_QS);
 800                 pr_err("Cannot do alloc_etherdev, aborting\n");
 801                 return -EINVAL;
 802         }
 803
 804         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 805         dev = *pdev;
 806         if (NULL == dev)
 807                 return -ENOMEM;
 808
 809         priv = netdev_priv(dev);
 810         priv->ndev = dev;
 811
 812         priv->mode = mode;
 813         priv->poll_mode = poll_mode;
 814
 815         priv->num_tx_queues = num_tx_qs;
 816         netif_set_real_num_rx_queues(dev, num_rx_qs);
 817         priv->num_rx_queues = num_rx_qs;
 818
 819         err = gfar_alloc_tx_queues(priv);
 820         if (err)
 821                 goto tx_alloc_failed;
 822
 823         err = gfar_alloc_rx_queues(priv);
 824         if (err)
 825                 goto rx_alloc_failed;
 826
 827         err = of_property_read_string(np, "model", &model);
 828         if (err) {
 829                 pr_err("Device model property missing, aborting\n");
 830                 goto rx_alloc_failed;
 831         }
 832
 833         /* Init Rx queue filer rule set linked list */
 834         INIT_LIST_HEAD(&priv->rx_list.list);
 835         priv->rx_list.count = 0;
 836         mutex_init(&priv->rx_queue_access);
 837
 838         for (i = 0; i < MAXGROUPS; i++)
 839                 priv->gfargrp[i].regs = NULL;
 840
 841         /* Parse and initialize group specific information */
 842         if (priv->mode == MQ_MG_MODE) {
 843                 for_each_available_child_of_node(np, child) {
 844                         if (of_node_cmp(child->name, "queue-group"))
 845                                 continue;
 846
 847                         err = gfar_parse_group(child, priv, model);
 848                         if (err)
 849                                 goto err_grp_init;
 850                 }
 851         } else { /* SQ_SG_MODE */
 852                 err = gfar_parse_group(np, priv, model);
 853                 if (err)
 854                         goto err_grp_init;
 855         }
 856
 857         stash = of_find_property(np, "bd-stash", NULL);
 858
 859         if (stash) {
 860                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 861                 priv->bd_stash_en = 1;
 862         }
 863
 864         err = of_property_read_u32(np, "rx-stash-len", &stash_len);
 865
 866         if (err == 0)
 867                 priv->rx_stash_size = stash_len;
 868
 869         err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
 870
 871         if (err == 0)
 872                 priv->rx_stash_index = stash_idx;
 873
 874         if (stash_len || stash_idx)
 875                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 876
 877         mac_addr = of_get_mac_address(np);
 878
 879         if (mac_addr)
 880                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
 881
 882         if (model && !strcasecmp(model, "TSEC"))
 883                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 884                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 885                                      FSL_GIANFAR_DEV_HAS_RMON |
 886                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 887
 888         if (model && !strcasecmp(model, "eTSEC"))
 889                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 890                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 891                                      FSL_GIANFAR_DEV_HAS_RMON |
 892                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 893                                      FSL_GIANFAR_DEV_HAS_CSUM |
 894                                      FSL_GIANFAR_DEV_HAS_VLAN |
 895                                      FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 896                                      FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 897                                      FSL_GIANFAR_DEV_HAS_TIMER;
 898
 899         err = of_property_read_string(np, "phy-connection-type", &ctype);
 900
 901         /* We only care about rgmii-id.  The rest are autodetected */
 902         if (err == 0 && !strcmp(ctype, "rgmii-id"))
 903                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 904         else
 905                 priv->interface = PHY_INTERFACE_MODE_MII;
 906
 907         if (of_find_property(np, "fsl,magic-packet", NULL))
 908                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 909
 910         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 911
 912         /* In the case of a fixed PHY, the DT node associated
 913          * to the PHY is the Ethernet MAC DT node.
 914          */
 915         if (!priv->phy_node && of_phy_is_fixed_link(np)) {
 916                 err = of_phy_register_fixed_link(np);
 917                 if (err)
 918                         goto err_grp_init;
 919
 920                 priv->phy_node = of_node_get(np);
 921         }
 922
 923         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 924         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 925
 926         return 0;
 927
 928 err_grp_init:
 929         unmap_group_regs(priv);
 930 rx_alloc_failed:
 931         gfar_free_rx_queues(priv);
 932 tx_alloc_failed:
 933         gfar_free_tx_queues(priv);
 934         free_gfar_dev(priv);
 935         return err;
 936 }
 937
 938 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
 939 {
 940         struct hwtstamp_config config;
 941         struct gfar_private *priv = netdev_priv(netdev);
 942
 943         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 944                 return -EFAULT;
 945
 946         /* reserved for future extensions */
 947         if (config.flags)
 948                 return -EINVAL;
 949
 950         switch (config.tx_type) {
 951         case HWTSTAMP_TX_OFF:
 952                 priv->hwts_tx_en = 0;
 953                 break;
 954         case HWTSTAMP_TX_ON:
 955                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 956                         return -ERANGE;
 957                 priv->hwts_tx_en = 1;
 958                 break;
 959         default:
 960                 return -ERANGE;
 961         }
 962
 963         switch (config.rx_filter) {
 964         case HWTSTAMP_FILTER_NONE:
 965                 if (priv->hwts_rx_en) {
 966                         priv->hwts_rx_en = 0;
 967                         reset_gfar(netdev);
 968                 }
 969                 break;
 970         default:
 971                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 972                         return -ERANGE;
 973                 if (!priv->hwts_rx_en) {
 974                         priv->hwts_rx_en = 1;
 975                         reset_gfar(netdev);
 976                 }
 977                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 978                 break;
 979         }
 980
 981         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 982                 -EFAULT : 0;
 983 }
 984
 985 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
 986 {
 987         struct hwtstamp_config config;
 988         struct gfar_private *priv = netdev_priv(netdev);
 989
 990         config.flags = 0;
 991         config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
 992         config.rx_filter = (priv->hwts_rx_en ?
 993                             HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
 994
 995         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 996                 -EFAULT : 0;
 997 }
 998
 999 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1000 {
1001         struct gfar_private *priv = netdev_priv(dev);
1002
1003         if (!netif_running(dev))
1004                 return -EINVAL;
1005
1006         if (cmd == SIOCSHWTSTAMP)
1007                 return gfar_hwtstamp_set(dev, rq);
1008         if (cmd == SIOCGHWTSTAMP)
1009                 return gfar_hwtstamp_get(dev, rq);
1010
1011         if (!priv->phydev)
1012                 return -ENODEV;
1013
1014         return phy_mii_ioctl(priv->phydev, rq, cmd);
1015 }
1016
1017 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
1018                                    u32 class)
1019 {
1020         u32 rqfpr = FPR_FILER_MASK;
1021         u32 rqfcr = 0x0;
1022
1023         rqfar--;
1024         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
1025         priv->ftp_rqfpr[rqfar] = rqfpr;
1026         priv->ftp_rqfcr[rqfar] = rqfcr;
1027         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1028
1029         rqfar--;
1030         rqfcr = RQFCR_CMP_NOMATCH;
1031         priv->ftp_rqfpr[rqfar] = rqfpr;
1032         priv->ftp_rqfcr[rqfar] = rqfcr;
1033         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1034
1035         rqfar--;
1036         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
1037         rqfpr = class;
1038         priv->ftp_rqfcr[rqfar] = rqfcr;
1039         priv->ftp_rqfpr[rqfar] = rqfpr;
1040         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1041
1042         rqfar--;
1043         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
1044         rqfpr = class;
1045         priv->ftp_rqfcr[rqfar] = rqfcr;
1046         priv->ftp_rqfpr[rqfar] = rqfpr;
1047         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1048
1049         return rqfar;
1050 }
1051
1052 static void gfar_init_filer_table(struct gfar_private *priv)
1053 {
1054         int i = 0x0;
1055         u32 rqfar = MAX_FILER_IDX;
1056         u32 rqfcr = 0x0;
1057         u32 rqfpr = FPR_FILER_MASK;
1058
1059         /* Default rule */
1060         rqfcr = RQFCR_CMP_MATCH;
1061         priv->ftp_rqfcr[rqfar] = rqfcr;
1062         priv->ftp_rqfpr[rqfar] = rqfpr;
1063         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1064
1065         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
1066         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
1067         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
1068         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
1069         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
1070         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
1071
1072         /* cur_filer_idx indicated the first non-masked rule */
1073         priv->cur_filer_idx = rqfar;
1074
1075         /* Rest are masked rules */
1076         rqfcr = RQFCR_CMP_NOMATCH;
1077         for (i = 0; i < rqfar; i++) {
1078                 priv->ftp_rqfcr[i] = rqfcr;
1079                 priv->ftp_rqfpr[i] = rqfpr;
1080                 gfar_write_filer(priv, i, rqfcr, rqfpr);
1081         }
1082 }
1083
1084 #ifdef CONFIG_PPC
1085 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
1086 {
1087         unsigned int pvr = mfspr(SPRN_PVR);
1088         unsigned int svr = mfspr(SPRN_SVR);
1089         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
1090         unsigned int rev = svr & 0xffff;
1091
1092         /* MPC8313 Rev 2.0 and higher; All MPC837x */
1093         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
1094             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1095                 priv->errata |= GFAR_ERRATA_74;
1096
1097         /* MPC8313 and MPC837x all rev */
1098         if ((pvr == 0x80850010 && mod == 0x80b0) ||
1099             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1100                 priv->errata |= GFAR_ERRATA_76;
1101
1102         /* MPC8313 Rev < 2.0 */
1103         if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
1104                 priv->errata |= GFAR_ERRATA_12;
1105 }
1106
1107 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
1108 {
1109         unsigned int svr = mfspr(SPRN_SVR);
1110
1111         if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
1112                 priv->errata |= GFAR_ERRATA_12;
1113         if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
1114             ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)))
1115                 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
1116 }
1117 #endif
1118
1119 static void gfar_detect_errata(struct gfar_private *priv)
1120 {
1121         struct device *dev = &priv->ofdev->dev;
1122
1123         /* no plans to fix */
1124         priv->errata |= GFAR_ERRATA_A002;
1125
1126 #ifdef CONFIG_PPC
1127         if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1128                 __gfar_detect_errata_85xx(priv);
1129         else /* non-mpc85xx parts, i.e. e300 core based */
1130                 __gfar_detect_errata_83xx(priv);
1131 #endif
1132
1133         if (priv->errata)
1134                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1135                          priv->errata);
1136 }
1137
1138 void gfar_mac_reset(struct gfar_private *priv)
1139 {
1140         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1141         u32 tempval;
1142
1143         /* Reset MAC layer */
1144         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1145
1146         /* We need to delay at least 3 TX clocks */
1147         udelay(3);
1148
1149         /* the soft reset bit is not self-resetting, so we need to
1150          * clear it before resuming normal operation
1151          */
1152         gfar_write(&regs->maccfg1, 0);
1153
1154         udelay(3);
1155
1156         gfar_rx_offload_en(priv);
1157
1158         /* Initialize the max receive frame/buffer lengths */
1159         gfar_write(&regs->maxfrm, GFAR_JUMBO_FRAME_SIZE);
1160         gfar_write(&regs->mrblr, GFAR_RXB_SIZE);
1161
1162         /* Initialize the Minimum Frame Length Register */
1163         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1164
1165         /* Initialize MACCFG2. */
1166         tempval = MACCFG2_INIT_SETTINGS;
1167
1168         /* eTSEC74 erratum: Rx frames of length MAXFRM or MAXFRM-1
1169          * are marked as truncated.  Avoid this by MACCFG2[Huge Frame]=1,
1170          * and by checking RxBD[LG] and discarding larger than MAXFRM.
1171          */
1172         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1173                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1174
1175         gfar_write(&regs->maccfg2, tempval);
1176
1177         /* Clear mac addr hash registers */
1178         gfar_write(&regs->igaddr0, 0);
1179         gfar_write(&regs->igaddr1, 0);
1180         gfar_write(&regs->igaddr2, 0);
1181         gfar_write(&regs->igaddr3, 0);
1182         gfar_write(&regs->igaddr4, 0);
1183         gfar_write(&regs->igaddr5, 0);
1184         gfar_write(&regs->igaddr6, 0);
1185         gfar_write(&regs->igaddr7, 0);
1186
1187         gfar_write(&regs->gaddr0, 0);
1188         gfar_write(&regs->gaddr1, 0);
1189         gfar_write(&regs->gaddr2, 0);
1190         gfar_write(&regs->gaddr3, 0);
1191         gfar_write(&regs->gaddr4, 0);
1192         gfar_write(&regs->gaddr5, 0);
1193         gfar_write(&regs->gaddr6, 0);
1194         gfar_write(&regs->gaddr7, 0);
1195
1196         if (priv->extended_hash)
1197                 gfar_clear_exact_match(priv->ndev);
1198
1199         gfar_mac_rx_config(priv);
1200
1201         gfar_mac_tx_config(priv);
1202
1203         gfar_set_mac_address(priv->ndev);
1204
1205         gfar_set_multi(priv->ndev);
1206
1207         /* clear ievent and imask before configuring coalescing */
1208         gfar_ints_disable(priv);
1209
1210         /* Configure the coalescing support */
1211         gfar_configure_coalescing_all(priv);
1212 }
1213
1214 static void gfar_hw_init(struct gfar_private *priv)
1215 {
1216         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1217         u32 attrs;
1218
1219         /* Stop the DMA engine now, in case it was running before
1220          * (The firmware could have used it, and left it running).
1221          */
1222         gfar_halt(priv);
1223
1224         gfar_mac_reset(priv);
1225
1226         /* Zero out the rmon mib registers if it has them */
1227         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1228                 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1229
1230                 /* Mask off the CAM interrupts */
1231                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1232                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1233         }
1234
1235         /* Initialize ECNTRL */
1236         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1237
1238         /* Set the extraction length and index */
1239         attrs = ATTRELI_EL(priv->rx_stash_size) |
1240                 ATTRELI_EI(priv->rx_stash_index);
1241
1242         gfar_write(&regs->attreli, attrs);
1243
1244         /* Start with defaults, and add stashing
1245          * depending on driver parameters
1246          */
1247         attrs = ATTR_INIT_SETTINGS;
1248
1249         if (priv->bd_stash_en)
1250                 attrs |= ATTR_BDSTASH;
1251
1252         if (priv->rx_stash_size != 0)
1253                 attrs |= ATTR_BUFSTASH;
1254
1255         gfar_write(&regs->attr, attrs);
1256
1257         /* FIFO configs */
1258         gfar_write(&regs->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1259         gfar_write(&regs->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1260         gfar_write(&regs->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1261
1262         /* Program the interrupt steering regs, only for MG devices */
1263         if (priv->num_grps > 1)
1264                 gfar_write_isrg(priv);
1265 }
1266
1267 static void gfar_init_addr_hash_table(struct gfar_private *priv)
1268 {
1269         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1270
1271         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1272                 priv->extended_hash = 1;
1273                 priv->hash_width = 9;
1274
1275                 priv->hash_regs[0] = &regs->igaddr0;
1276                 priv->hash_regs[1] = &regs->igaddr1;
1277                 priv->hash_regs[2] = &regs->igaddr2;
1278                 priv->hash_regs[3] = &regs->igaddr3;
1279                 priv->hash_regs[4] = &regs->igaddr4;
1280                 priv->hash_regs[5] = &regs->igaddr5;
1281                 priv->hash_regs[6] = &regs->igaddr6;
1282                 priv->hash_regs[7] = &regs->igaddr7;
1283                 priv->hash_regs[8] = &regs->gaddr0;
1284                 priv->hash_regs[9] = &regs->gaddr1;
1285                 priv->hash_regs[10] = &regs->gaddr2;
1286                 priv->hash_regs[11] = &regs->gaddr3;
1287                 priv->hash_regs[12] = &regs->gaddr4;
1288                 priv->hash_regs[13] = &regs->gaddr5;
1289                 priv->hash_regs[14] = &regs->gaddr6;
1290                 priv->hash_regs[15] = &regs->gaddr7;
1291
1292         } else {
1293                 priv->extended_hash = 0;
1294                 priv->hash_width = 8;
1295
1296                 priv->hash_regs[0] = &regs->gaddr0;
1297                 priv->hash_regs[1] = &regs->gaddr1;
1298                 priv->hash_regs[2] = &regs->gaddr2;
1299                 priv->hash_regs[3] = &regs->gaddr3;
1300                 priv->hash_regs[4] = &regs->gaddr4;
1301                 priv->hash_regs[5] = &regs->gaddr5;
1302                 priv->hash_regs[6] = &regs->gaddr6;
1303                 priv->hash_regs[7] = &regs->gaddr7;
1304         }
1305 }
1306
1307 /* Set up the ethernet device structure, private data,
1308  * and anything else we need before we start
1309  */
1310 static int gfar_probe(struct platform_device *ofdev)
1311 {
1312         struct net_device *dev = NULL;
1313         struct gfar_private *priv = NULL;
1314         int err = 0, i;
1315
1316         err = gfar_of_init(ofdev, &dev);
1317
1318         if (err)
1319                 return err;
1320
1321         priv = netdev_priv(dev);
1322         priv->ndev = dev;
1323         priv->ofdev = ofdev;
1324         priv->dev = &ofdev->dev;
1325         SET_NETDEV_DEV(dev, &ofdev->dev);
1326
1327         INIT_WORK(&priv->reset_task, gfar_reset_task);
1328
1329         platform_set_drvdata(ofdev, priv);
1330
1331         gfar_detect_errata(priv);
1332
1333         /* Set the dev->base_addr to the gfar reg region */
1334         dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1335
1336         /* Fill in the dev structure */
1337         dev->watchdog_timeo = TX_TIMEOUT;
1338         dev->mtu = 1500;
1339         dev->netdev_ops = &gfar_netdev_ops;
1340         dev->ethtool_ops = &gfar_ethtool_ops;
1341
1342         /* Register for napi ...We are registering NAPI for each grp */
1343         for (i = 0; i < priv->num_grps; i++) {
1344                 if (priv->poll_mode == GFAR_SQ_POLLING) {
1345                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1346                                        gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
1347                         netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1348                                        gfar_poll_tx_sq, 2);
1349                 } else {
1350                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1351                                        gfar_poll_rx, GFAR_DEV_WEIGHT);
1352                         netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1353                                        gfar_poll_tx, 2);
1354                 }
1355         }
1356
1357         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1358                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1359                                    NETIF_F_RXCSUM;
1360                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1361                                  NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1362         }
1363
1364         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1365                 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1366                                     NETIF_F_HW_VLAN_CTAG_RX;
1367                 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1368         }
1369
1370         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
1371
1372         gfar_init_addr_hash_table(priv);
1373
1374         /* Insert receive time stamps into padding alignment bytes */
1375         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1376                 priv->padding = 8;
1377
1378         if (dev->features & NETIF_F_IP_CSUM ||
1379             priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1380                 dev->needed_headroom = GMAC_FCB_LEN;
1381
1382         /* Initializing some of the rx/tx queue level parameters */
1383         for (i = 0; i < priv->num_tx_queues; i++) {
1384                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1385                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1386                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1387                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1388         }
1389
1390         for (i = 0; i < priv->num_rx_queues; i++) {
1391                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1392                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1393                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1394         }
1395
1396         /* always enable rx filer */
1397         priv->rx_filer_enable = 1;
1398         /* Enable most messages by default */
1399         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1400         /* use pritority h/w tx queue scheduling for single queue devices */
1401         if (priv->num_tx_queues == 1)
1402                 priv->prio_sched_en = 1;
1403
1404         set_bit(GFAR_DOWN, &priv->state);
1405
1406         gfar_hw_init(priv);
1407
1408         /* Carrier starts down, phylib will bring it up */
1409         netif_carrier_off(dev);
1410
1411         err = register_netdev(dev);
1412
1413         if (err) {
1414                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1415                 goto register_fail;
1416         }
1417
1418         device_set_wakeup_capable(&dev->dev, priv->device_flags &
1419                                   FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1420
1421         /* fill out IRQ number and name fields */
1422         for (i = 0; i < priv->num_grps; i++) {
1423                 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1424                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1425                         sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1426                                 dev->name, "_g", '0' + i, "_tx");
1427                         sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1428                                 dev->name, "_g", '0' + i, "_rx");
1429                         sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1430                                 dev->name, "_g", '0' + i, "_er");
1431                 } else
1432                         strcpy(gfar_irq(grp, TX)->name, dev->name);
1433         }
1434
1435         /* Initialize the filer table */
1436         gfar_init_filer_table(priv);
1437
1438         /* Print out the device info */
1439         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1440
1441         /* Even more device info helps when determining which kernel
1442          * provided which set of benchmarks.
1443          */
1444         netdev_info(dev, "Running with NAPI enabled\n");
1445         for (i = 0; i < priv->num_rx_queues; i++)
1446                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1447                             i, priv->rx_queue[i]->rx_ring_size);
1448         for (i = 0; i < priv->num_tx_queues; i++)
1449                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1450                             i, priv->tx_queue[i]->tx_ring_size);
1451
1452         return 0;
1453
1454 register_fail:
1455         unmap_group_regs(priv);
1456         gfar_free_rx_queues(priv);
1457         gfar_free_tx_queues(priv);
1458         of_node_put(priv->phy_node);
1459         of_node_put(priv->tbi_node);
1460         free_gfar_dev(priv);
1461         return err;
1462 }
1463
1464 static int gfar_remove(struct platform_device *ofdev)
1465 {
1466         struct gfar_private *priv = platform_get_drvdata(ofdev);
1467
1468         of_node_put(priv->phy_node);
1469         of_node_put(priv->tbi_node);
1470
1471         unregister_netdev(priv->ndev);
1472         unmap_group_regs(priv);
1473         gfar_free_rx_queues(priv);
1474         gfar_free_tx_queues(priv);
1475         free_gfar_dev(priv);
1476
1477         return 0;
1478 }
1479
1480 #ifdef CONFIG_PM
1481
1482 static int gfar_suspend(struct device *dev)
1483 {
1484         struct gfar_private *priv = dev_get_drvdata(dev);
1485         struct net_device *ndev = priv->ndev;
1486         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1487         u32 tempval;
1488         int magic_packet = priv->wol_en &&
1489                            (priv->device_flags &
1490                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1491
1492         if (!netif_running(ndev))
1493                 return 0;
1494
1495         disable_napi(priv);
1496         netif_tx_lock(ndev);
1497         netif_device_detach(ndev);
1498         netif_tx_unlock(ndev);
1499
1500         gfar_halt(priv);
1501
1502         if (magic_packet) {
1503                 /* Enable interrupt on Magic Packet */
1504                 gfar_write(&regs->imask, IMASK_MAG);
1505
1506                 /* Enable Magic Packet mode */
1507                 tempval = gfar_read(&regs->maccfg2);
1508                 tempval |= MACCFG2_MPEN;
1509                 gfar_write(&regs->maccfg2, tempval);
1510
1511                 /* re-enable the Rx block */
1512                 tempval = gfar_read(&regs->maccfg1);
1513                 tempval |= MACCFG1_RX_EN;
1514                 gfar_write(&regs->maccfg1, tempval);
1515
1516         } else {
1517                 phy_stop(priv->phydev);
1518         }
1519
1520         return 0;
1521 }
1522
1523 static int gfar_resume(struct device *dev)
1524 {
1525         struct gfar_private *priv = dev_get_drvdata(dev);
1526         struct net_device *ndev = priv->ndev;
1527         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1528         u32 tempval;
1529         int magic_packet = priv->wol_en &&
1530                            (priv->device_flags &
1531                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1532
1533         if (!netif_running(ndev))
1534                 return 0;
1535
1536         if (magic_packet) {
1537                 /* Disable Magic Packet mode */
1538                 tempval = gfar_read(&regs->maccfg2);
1539                 tempval &= ~MACCFG2_MPEN;
1540                 gfar_write(&regs->maccfg2, tempval);
1541         } else {
1542                 phy_start(priv->phydev);
1543         }
1544
1545         gfar_start(priv);
1546
1547         netif_device_attach(ndev);
1548         enable_napi(priv);
1549
1550         return 0;
1551 }
1552
1553 static int gfar_restore(struct device *dev)
1554 {
1555         struct gfar_private *priv = dev_get_drvdata(dev);
1556         struct net_device *ndev = priv->ndev;
1557
1558         if (!netif_running(ndev)) {
1559                 netif_device_attach(ndev);
1560
1561                 return 0;
1562         }
1563
1564         gfar_init_bds(ndev);
1565
1566         gfar_mac_reset(priv);
1567
1568         gfar_init_tx_rx_base(priv);
1569
1570         gfar_start(priv);
1571
1572         priv->oldlink = 0;
1573         priv->oldspeed = 0;
1574         priv->oldduplex = -1;
1575
1576         if (priv->phydev)
1577                 phy_start(priv->phydev);
1578
1579         netif_device_attach(ndev);
1580         enable_napi(priv);
1581
1582         return 0;
1583 }
1584
1585 static struct dev_pm_ops gfar_pm_ops = {
1586         .suspend = gfar_suspend,
1587         .resume = gfar_resume,
1588         .freeze = gfar_suspend,
1589         .thaw = gfar_resume,
1590         .restore = gfar_restore,
1591 };
1592
1593 #define GFAR_PM_OPS (&gfar_pm_ops)
1594
1595 #else
1596
1597 #define GFAR_PM_OPS NULL
1598
1599 #endif
1600
1601 /* Reads the controller's registers to determine what interface
1602  * connects it to the PHY.
1603  */
1604 static phy_interface_t gfar_get_interface(struct net_device *dev)
1605 {
1606         struct gfar_private *priv = netdev_priv(dev);
1607         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1608         u32 ecntrl;
1609
1610         ecntrl = gfar_read(&regs->ecntrl);
1611
1612         if (ecntrl & ECNTRL_SGMII_MODE)
1613                 return PHY_INTERFACE_MODE_SGMII;
1614
1615         if (ecntrl & ECNTRL_TBI_MODE) {
1616                 if (ecntrl & ECNTRL_REDUCED_MODE)
1617                         return PHY_INTERFACE_MODE_RTBI;
1618                 else
1619                         return PHY_INTERFACE_MODE_TBI;
1620         }
1621
1622         if (ecntrl & ECNTRL_REDUCED_MODE) {
1623                 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1624                         return PHY_INTERFACE_MODE_RMII;
1625                 }
1626                 else {
1627                         phy_interface_t interface = priv->interface;
1628
1629                         /* This isn't autodetected right now, so it must
1630                          * be set by the device tree or platform code.
1631                          */
1632                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1633                                 return PHY_INTERFACE_MODE_RGMII_ID;
1634
1635                         return PHY_INTERFACE_MODE_RGMII;
1636                 }
1637         }
1638
1639         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1640                 return PHY_INTERFACE_MODE_GMII;
1641
1642         return PHY_INTERFACE_MODE_MII;
1643 }
1644
1645
1646 /* Initializes driver's PHY state, and attaches to the PHY.
1647  * Returns 0 on success.
1648  */
1649 static int init_phy(struct net_device *dev)
1650 {
1651         struct gfar_private *priv = netdev_priv(dev);
1652         uint gigabit_support =
1653                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1654                 GFAR_SUPPORTED_GBIT : 0;
1655         phy_interface_t interface;
1656
1657         priv->oldlink = 0;
1658         priv->oldspeed = 0;
1659         priv->oldduplex = -1;
1660
1661         interface = gfar_get_interface(dev);
1662
1663         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1664                                       interface);
1665         if (!priv->phydev) {
1666                 dev_err(&dev->dev, "could not attach to PHY\n");
1667                 return -ENODEV;
1668         }
1669
1670         if (interface == PHY_INTERFACE_MODE_SGMII)
1671                 gfar_configure_serdes(dev);
1672
1673         /* Remove any features not supported by the controller */
1674         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1675         priv->phydev->advertising = priv->phydev->supported;
1676
1677         /* Add support for flow control, but don't advertise it by default */
1678         priv->phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
1679
1680         return 0;
1681 }
1682
1683 /* Initialize TBI PHY interface for communicating with the
1684  * SERDES lynx PHY on the chip.  We communicate with this PHY
1685  * through the MDIO bus on each controller, treating it as a
1686  * "normal" PHY at the address found in the TBIPA register.  We assume
1687  * that the TBIPA register is valid.  Either the MDIO bus code will set
1688  * it to a value that doesn't conflict with other PHYs on the bus, or the
1689  * value doesn't matter, as there are no other PHYs on the bus.
1690  */
1691 static void gfar_configure_serdes(struct net_device *dev)
1692 {
1693         struct gfar_private *priv = netdev_priv(dev);
1694         struct phy_device *tbiphy;
1695
1696         if (!priv->tbi_node) {
1697                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1698                                     "device tree specify a tbi-handle\n");
1699                 return;
1700         }
1701
1702         tbiphy = of_phy_find_device(priv->tbi_node);
1703         if (!tbiphy) {
1704                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1705                 return;
1706         }
1707
1708         /* If the link is already up, we must already be ok, and don't need to
1709          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1710          * everything for us?  Resetting it takes the link down and requires
1711          * several seconds for it to come back.
1712          */
1713         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) {
1714                 put_device(&tbiphy->dev);
1715                 return;
1716         }
1717
1718         /* Single clk mode, mii mode off(for serdes communication) */
1719         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1720
1721         phy_write(tbiphy, MII_ADVERTISE,
1722                   ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1723                   ADVERTISE_1000XPSE_ASYM);
1724
1725         phy_write(tbiphy, MII_BMCR,
1726                   BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1727                   BMCR_SPEED1000);
1728
1729         put_device(&tbiphy->dev);
1730 }
1731
1732 static int __gfar_is_rx_idle(struct gfar_private *priv)
1733 {
1734         u32 res;
1735
1736         /* Normaly TSEC should not hang on GRS commands, so we should
1737          * actually wait for IEVENT_GRSC flag.
1738          */
1739         if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1740                 return 0;
1741
1742         /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1743          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1744          * and the Rx can be safely reset.
1745          */
1746         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1747         res &= 0x7f807f80;
1748         if ((res & 0xffff) == (res >> 16))
1749                 return 1;
1750
1751         return 0;
1752 }
1753
1754 /* Halt the receive and transmit queues */
1755 static void gfar_halt_nodisable(struct gfar_private *priv)
1756 {
1757         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1758         u32 tempval;
1759         unsigned int timeout;
1760         int stopped;
1761
1762         gfar_ints_disable(priv);
1763
1764         if (gfar_is_dma_stopped(priv))
1765                 return;
1766
1767         /* Stop the DMA, and wait for it to stop */
1768         tempval = gfar_read(&regs->dmactrl);
1769         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1770         gfar_write(&regs->dmactrl, tempval);
1771
1772 retry:
1773         timeout = 1000;
1774         while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1775                 cpu_relax();
1776                 timeout--;
1777         }
1778
1779         if (!timeout)
1780                 stopped = gfar_is_dma_stopped(priv);
1781
1782         if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1783             !__gfar_is_rx_idle(priv))
1784                 goto retry;
1785 }
1786
1787 /* Halt the receive and transmit queues */
1788 void gfar_halt(struct gfar_private *priv)
1789 {
1790         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1791         u32 tempval;
1792
1793         /* Dissable the Rx/Tx hw queues */
1794         gfar_write(&regs->rqueue, 0);
1795         gfar_write(&regs->tqueue, 0);
1796
1797         mdelay(10);
1798
1799         gfar_halt_nodisable(priv);
1800
1801         /* Disable Rx/Tx DMA */
1802         tempval = gfar_read(&regs->maccfg1);
1803         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1804         gfar_write(&regs->maccfg1, tempval);
1805 }
1806
1807 void stop_gfar(struct net_device *dev)
1808 {
1809         struct gfar_private *priv = netdev_priv(dev);
1810
1811         netif_tx_stop_all_queues(dev);
1812
1813         smp_mb__before_atomic();
1814         set_bit(GFAR_DOWN, &priv->state);
1815         smp_mb__after_atomic();
1816
1817         disable_napi(priv);
1818
1819         /* disable ints and gracefully shut down Rx/Tx DMA */
1820         gfar_halt(priv);
1821
1822         phy_stop(priv->phydev);
1823
1824         free_skb_resources(priv);
1825 }
1826
1827 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1828 {
1829         struct txbd8 *txbdp;
1830         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1831         int i, j;
1832
1833         txbdp = tx_queue->tx_bd_base;
1834
1835         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1836                 if (!tx_queue->tx_skbuff[i])
1837                         continue;
1838
1839                 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1840                                  be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
1841                 txbdp->lstatus = 0;
1842                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1843                      j++) {
1844                         txbdp++;
1845                         dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1846                                        be16_to_cpu(txbdp->length),
1847                                        DMA_TO_DEVICE);
1848                 }
1849                 txbdp++;
1850                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1851                 tx_queue->tx_skbuff[i] = NULL;
1852         }
1853         kfree(tx_queue->tx_skbuff);
1854         tx_queue->tx_skbuff = NULL;
1855 }
1856
1857 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1858 {
1859         int i;
1860
1861         struct rxbd8 *rxbdp = rx_queue->rx_bd_base;
1862
1863         if (rx_queue->skb)
1864                 dev_kfree_skb(rx_queue->skb);
1865
1866         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1867                 struct  gfar_rx_buff *rxb = &rx_queue->rx_buff[i];
1868
1869                 rxbdp->lstatus = 0;
1870                 rxbdp->bufPtr = 0;
1871                 rxbdp++;
1872
1873                 if (!rxb->page)
1874                         continue;
1875
1876                 dma_unmap_single(rx_queue->dev, rxb->dma,
1877                                  PAGE_SIZE, DMA_FROM_DEVICE);
1878                 __free_page(rxb->page);
1879
1880                 rxb->page = NULL;
1881         }
1882
1883         kfree(rx_queue->rx_buff);
1884         rx_queue->rx_buff = NULL;
1885 }
1886
1887 /* If there are any tx skbs or rx skbs still around, free them.
1888  * Then free tx_skbuff and rx_skbuff
1889  */
1890 static void free_skb_resources(struct gfar_private *priv)
1891 {
1892         struct gfar_priv_tx_q *tx_queue = NULL;
1893         struct gfar_priv_rx_q *rx_queue = NULL;
1894         int i;
1895
1896         /* Go through all the buffer descriptors and free their data buffers */
1897         for (i = 0; i < priv->num_tx_queues; i++) {
1898                 struct netdev_queue *txq;
1899
1900                 tx_queue = priv->tx_queue[i];
1901                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1902                 if (tx_queue->tx_skbuff)
1903                         free_skb_tx_queue(tx_queue);
1904                 netdev_tx_reset_queue(txq);
1905         }
1906
1907         for (i = 0; i < priv->num_rx_queues; i++) {
1908                 rx_queue = priv->rx_queue[i];
1909                 if (rx_queue->rx_buff)
1910                         free_skb_rx_queue(rx_queue);
1911         }
1912
1913         dma_free_coherent(priv->dev,
1914                           sizeof(struct txbd8) * priv->total_tx_ring_size +
1915                           sizeof(struct rxbd8) * priv->total_rx_ring_size,
1916                           priv->tx_queue[0]->tx_bd_base,
1917                           priv->tx_queue[0]->tx_bd_dma_base);
1918 }
1919
1920 void gfar_start(struct gfar_private *priv)
1921 {
1922         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1923         u32 tempval;
1924         int i = 0;
1925
1926         /* Enable Rx/Tx hw queues */
1927         gfar_write(&regs->rqueue, priv->rqueue);
1928         gfar_write(&regs->tqueue, priv->tqueue);
1929
1930         /* Initialize DMACTRL to have WWR and WOP */
1931         tempval = gfar_read(&regs->dmactrl);
1932         tempval |= DMACTRL_INIT_SETTINGS;
1933         gfar_write(&regs->dmactrl, tempval);
1934
1935         /* Make sure we aren't stopped */
1936         tempval = gfar_read(&regs->dmactrl);
1937         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1938         gfar_write(&regs->dmactrl, tempval);
1939
1940         for (i = 0; i < priv->num_grps; i++) {
1941                 regs = priv->gfargrp[i].regs;
1942                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1943                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1944                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1945         }
1946
1947         /* Enable Rx/Tx DMA */
1948         tempval = gfar_read(&regs->maccfg1);
1949         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1950         gfar_write(&regs->maccfg1, tempval);
1951
1952         gfar_ints_enable(priv);
1953
1954         priv->ndev->trans_start = jiffies; /* prevent tx timeout */
1955 }
1956
1957 static void free_grp_irqs(struct gfar_priv_grp *grp)
1958 {
1959         free_irq(gfar_irq(grp, TX)->irq, grp);
1960         free_irq(gfar_irq(grp, RX)->irq, grp);
1961         free_irq(gfar_irq(grp, ER)->irq, grp);
1962 }
1963
1964 static int register_grp_irqs(struct gfar_priv_grp *grp)
1965 {
1966         struct gfar_private *priv = grp->priv;
1967         struct net_device *dev = priv->ndev;
1968         int err;
1969
1970         /* If the device has multiple interrupts, register for
1971          * them.  Otherwise, only register for the one
1972          */
1973         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1974                 /* Install our interrupt handlers for Error,
1975                  * Transmit, and Receive
1976                  */
1977                 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
1978                                   gfar_irq(grp, ER)->name, grp);
1979                 if (err < 0) {
1980                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1981                                   gfar_irq(grp, ER)->irq);
1982
1983                         goto err_irq_fail;
1984                 }
1985                 enable_irq_wake(gfar_irq(grp, ER)->irq);
1986
1987                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
1988                                   gfar_irq(grp, TX)->name, grp);
1989                 if (err < 0) {
1990                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1991                                   gfar_irq(grp, TX)->irq);
1992                         goto tx_irq_fail;
1993                 }
1994                 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
1995                                   gfar_irq(grp, RX)->name, grp);
1996                 if (err < 0) {
1997                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1998                                   gfar_irq(grp, RX)->irq);
1999                         goto rx_irq_fail;
2000                 }
2001         } else {
2002                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2003                                   gfar_irq(grp, TX)->name, grp);
2004                 if (err < 0) {
2005                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2006                                   gfar_irq(grp, TX)->irq);
2007                         goto err_irq_fail;
2008                 }
2009                 enable_irq_wake(gfar_irq(grp, TX)->irq);
2010         }
2011
2012         return 0;
2013
2014 rx_irq_fail:
2015         free_irq(gfar_irq(grp, TX)->irq, grp);
2016 tx_irq_fail:
2017         free_irq(gfar_irq(grp, ER)->irq, grp);
2018 err_irq_fail:
2019         return err;
2020
2021 }
2022
2023 static void gfar_free_irq(struct gfar_private *priv)
2024 {
2025         int i;
2026
2027         /* Free the IRQs */
2028         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2029                 for (i = 0; i < priv->num_grps; i++)
2030                         free_grp_irqs(&priv->gfargrp[i]);
2031         } else {
2032                 for (i = 0; i < priv->num_grps; i++)
2033                         free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2034                                  &priv->gfargrp[i]);
2035         }
2036 }
2037
2038 static int gfar_request_irq(struct gfar_private *priv)
2039 {
2040         int err, i, j;
2041
2042         for (i = 0; i < priv->num_grps; i++) {
2043                 err = register_grp_irqs(&priv->gfargrp[i]);
2044                 if (err) {
2045                         for (j = 0; j < i; j++)
2046                                 free_grp_irqs(&priv->gfargrp[j]);
2047                         return err;
2048                 }
2049         }
2050
2051         return 0;
2052 }
2053
2054 /* Bring the controller up and running */
2055 int startup_gfar(struct net_device *ndev)
2056 {
2057         struct gfar_private *priv = netdev_priv(ndev);
2058         int err;
2059
2060         gfar_mac_reset(priv);
2061
2062         err = gfar_alloc_skb_resources(ndev);
2063         if (err)
2064                 return err;
2065
2066         gfar_init_tx_rx_base(priv);
2067
2068         smp_mb__before_atomic();
2069         clear_bit(GFAR_DOWN, &priv->state);
2070         smp_mb__after_atomic();
2071
2072         /* Start Rx/Tx DMA and enable the interrupts */
2073         gfar_start(priv);
2074
2075         /* force link state update after mac reset */
2076         priv->oldlink = 0;
2077         priv->oldspeed = 0;
2078         priv->oldduplex = -1;
2079
2080         phy_start(priv->phydev);
2081
2082         enable_napi(priv);
2083
2084         netif_tx_wake_all_queues(ndev);
2085
2086         return 0;
2087 }
2088
2089 /* Called when something needs to use the ethernet device
2090  * Returns 0 for success.
2091  */
2092 static int gfar_enet_open(struct net_device *dev)
2093 {
2094         struct gfar_private *priv = netdev_priv(dev);
2095         int err;
2096
2097         err = init_phy(dev);
2098         if (err)
2099                 return err;
2100
2101         err = gfar_request_irq(priv);
2102         if (err)
2103                 return err;
2104
2105         err = startup_gfar(dev);
2106         if (err)
2107                 return err;
2108
2109         return err;
2110 }
2111
2112 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2113 {
2114         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2115
2116         memset(fcb, 0, GMAC_FCB_LEN);
2117
2118         return fcb;
2119 }
2120
2121 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2122                                     int fcb_length)
2123 {
2124         /* If we're here, it's a IP packet with a TCP or UDP
2125          * payload.  We set it to checksum, using a pseudo-header
2126          * we provide
2127          */
2128         u8 flags = TXFCB_DEFAULT;
2129
2130         /* Tell the controller what the protocol is
2131          * And provide the already calculated phcs
2132          */
2133         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2134                 flags |= TXFCB_UDP;
2135                 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
2136         } else
2137                 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
2138
2139         /* l3os is the distance between the start of the
2140          * frame (skb->data) and the start of the IP hdr.
2141          * l4os is the distance between the start of the
2142          * l3 hdr and the l4 hdr
2143          */
2144         fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
2145         fcb->l4os = skb_network_header_len(skb);
2146
2147         fcb->flags = flags;
2148 }
2149
2150 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2151 {
2152         fcb->flags |= TXFCB_VLN;
2153         fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
2154 }
2155
2156 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2157                                       struct txbd8 *base, int ring_size)
2158 {
2159         struct txbd8 *new_bd = bdp + stride;
2160
2161         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2162 }
2163
2164 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2165                                       int ring_size)
2166 {
2167         return skip_txbd(bdp, 1, base, ring_size);
2168 }
2169
2170 /* eTSEC12: csum generation not supported for some fcb offsets */
2171 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2172                                        unsigned long fcb_addr)
2173 {
2174         return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2175                (fcb_addr % 0x20) > 0x18);
2176 }
2177
2178 /* eTSEC76: csum generation for frames larger than 2500 may
2179  * cause excess delays before start of transmission
2180  */
2181 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2182                                        unsigned int len)
2183 {
2184         return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2185                (len > 2500));
2186 }
2187
2188 /* This is called by the kernel when a frame is ready for transmission.
2189  * It is pointed to by the dev->hard_start_xmit function pointer
2190  */
2191 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2192 {
2193         struct gfar_private *priv = netdev_priv(dev);
2194         struct gfar_priv_tx_q *tx_queue = NULL;
2195         struct netdev_queue *txq;
2196         struct gfar __iomem *regs = NULL;
2197         struct txfcb *fcb = NULL;
2198         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2199         u32 lstatus;
2200         int i, rq = 0;
2201         int do_tstamp, do_csum, do_vlan;
2202         u32 bufaddr;
2203         unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
2204
2205         rq = skb->queue_mapping;
2206         tx_queue = priv->tx_queue[rq];
2207         txq = netdev_get_tx_queue(dev, rq);
2208         base = tx_queue->tx_bd_base;
2209         regs = tx_queue->grp->regs;
2210
2211         do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2212         do_vlan = skb_vlan_tag_present(skb);
2213         do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2214                     priv->hwts_tx_en;
2215
2216         if (do_csum || do_vlan)
2217                 fcb_len = GMAC_FCB_LEN;
2218
2219         /* check if time stamp should be generated */
2220         if (unlikely(do_tstamp))
2221                 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2222
2223         /* make space for additional header when fcb is needed */
2224         if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
2225                 struct sk_buff *skb_new;
2226
2227                 skb_new = skb_realloc_headroom(skb, fcb_len);
2228                 if (!skb_new) {
2229                         dev->stats.tx_errors++;
2230                         dev_kfree_skb_any(skb);
2231                         return NETDEV_TX_OK;
2232                 }
2233
2234                 if (skb->sk)
2235                         skb_set_owner_w(skb_new, skb->sk);
2236                 dev_consume_skb_any(skb);
2237                 skb = skb_new;
2238         }
2239
2240         /* total number of fragments in the SKB */
2241         nr_frags = skb_shinfo(skb)->nr_frags;
2242
2243         /* calculate the required number of TxBDs for this skb */
2244         if (unlikely(do_tstamp))
2245                 nr_txbds = nr_frags + 2;
2246         else
2247                 nr_txbds = nr_frags + 1;
2248
2249         /* check if there is space to queue this packet */
2250         if (nr_txbds > tx_queue->num_txbdfree) {
2251                 /* no space, stop the queue */
2252                 netif_tx_stop_queue(txq);
2253                 dev->stats.tx_fifo_errors++;
2254                 return NETDEV_TX_BUSY;
2255         }
2256
2257         /* Update transmit stats */
2258         bytes_sent = skb->len;
2259         tx_queue->stats.tx_bytes += bytes_sent;
2260         /* keep Tx bytes on wire for BQL accounting */
2261         GFAR_CB(skb)->bytes_sent = bytes_sent;
2262         tx_queue->stats.tx_packets++;
2263
2264         txbdp = txbdp_start = tx_queue->cur_tx;
2265         lstatus = be32_to_cpu(txbdp->lstatus);
2266
2267         /* Time stamp insertion requires one additional TxBD */
2268         if (unlikely(do_tstamp))
2269                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2270                                                  tx_queue->tx_ring_size);
2271
2272         if (nr_frags == 0) {
2273                 if (unlikely(do_tstamp)) {
2274                         u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2275
2276                         lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2277                         txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2278                 } else {
2279                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2280                 }
2281         } else {
2282                 /* Place the fragment addresses and lengths into the TxBDs */
2283                 for (i = 0; i < nr_frags; i++) {
2284                         unsigned int frag_len;
2285                         /* Point at the next BD, wrapping as needed */
2286                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2287
2288                         frag_len = skb_shinfo(skb)->frags[i].size;
2289
2290                         lstatus = be32_to_cpu(txbdp->lstatus) | frag_len |
2291                                   BD_LFLAG(TXBD_READY);
2292
2293                         /* Handle the last BD specially */
2294                         if (i == nr_frags - 1)
2295                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2296
2297                         bufaddr = skb_frag_dma_map(priv->dev,
2298                                                    &skb_shinfo(skb)->frags[i],
2299                                                    0,
2300                                                    frag_len,
2301                                                    DMA_TO_DEVICE);
2302                         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2303                                 goto dma_map_err;
2304
2305                         /* set the TxBD length and buffer pointer */
2306                         txbdp->bufPtr = cpu_to_be32(bufaddr);
2307                         txbdp->lstatus = cpu_to_be32(lstatus);
2308                 }
2309
2310                 lstatus = be32_to_cpu(txbdp_start->lstatus);
2311         }
2312
2313         /* Add TxPAL between FCB and frame if required */
2314         if (unlikely(do_tstamp)) {
2315                 skb_push(skb, GMAC_TXPAL_LEN);
2316                 memset(skb->data, 0, GMAC_TXPAL_LEN);
2317         }
2318
2319         /* Add TxFCB if required */
2320         if (fcb_len) {
2321                 fcb = gfar_add_fcb(skb);
2322                 lstatus |= BD_LFLAG(TXBD_TOE);
2323         }
2324
2325         /* Set up checksumming */
2326         if (do_csum) {
2327                 gfar_tx_checksum(skb, fcb, fcb_len);
2328
2329                 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2330                     unlikely(gfar_csum_errata_76(priv, skb->len))) {
2331                         __skb_pull(skb, GMAC_FCB_LEN);
2332                         skb_checksum_help(skb);
2333                         if (do_vlan || do_tstamp) {
2334                                 /* put back a new fcb for vlan/tstamp TOE */
2335                                 fcb = gfar_add_fcb(skb);
2336                         } else {
2337                                 /* Tx TOE not used */
2338                                 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2339                                 fcb = NULL;
2340                         }
2341                 }
2342         }
2343
2344         if (do_vlan)
2345                 gfar_tx_vlan(skb, fcb);
2346
2347         /* Setup tx hardware time stamping if requested */
2348         if (unlikely(do_tstamp)) {
2349                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2350                 fcb->ptp = 1;
2351         }
2352
2353         bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
2354                                  DMA_TO_DEVICE);
2355         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2356                 goto dma_map_err;
2357
2358         txbdp_start->bufPtr = cpu_to_be32(bufaddr);
2359
2360         /* If time stamping is requested one additional TxBD must be set up. The
2361          * first TxBD points to the FCB and must have a data length of
2362          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2363          * the full frame length.
2364          */
2365         if (unlikely(do_tstamp)) {
2366                 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2367
2368                 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
2369                 bufaddr += fcb_len;
2370                 lstatus_ts |= BD_LFLAG(TXBD_READY) |
2371                               (skb_headlen(skb) - fcb_len);
2372
2373                 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
2374                 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2375                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2376         } else {
2377                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2378         }
2379
2380         netdev_tx_sent_queue(txq, bytes_sent);
2381
2382         gfar_wmb();
2383
2384         txbdp_start->lstatus = cpu_to_be32(lstatus);
2385
2386         gfar_wmb(); /* force lstatus write before tx_skbuff */
2387
2388         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2389
2390         /* Update the current skb pointer to the next entry we will use
2391          * (wrapping if necessary)
2392          */
2393         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2394                               TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2395
2396         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2397
2398         /* We can work in parallel with gfar_clean_tx_ring(), except
2399          * when modifying num_txbdfree. Note that we didn't grab the lock
2400          * when we were reading the num_txbdfree and checking for available
2401          * space, that's because outside of this function it can only grow.
2402          */
2403         spin_lock_bh(&tx_queue->txlock);
2404         /* reduce TxBD free count */
2405         tx_queue->num_txbdfree -= (nr_txbds);
2406         spin_unlock_bh(&tx_queue->txlock);
2407
2408         /* If the next BD still needs to be cleaned up, then the bds
2409          * are full.  We need to tell the kernel to stop sending us stuff.
2410          */
2411         if (!tx_queue->num_txbdfree) {
2412                 netif_tx_stop_queue(txq);
2413
2414                 dev->stats.tx_fifo_errors++;
2415         }
2416
2417         /* Tell the DMA to go go go */
2418         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2419
2420         return NETDEV_TX_OK;
2421
2422 dma_map_err:
2423         txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2424         if (do_tstamp)
2425                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2426         for (i = 0; i < nr_frags; i++) {
2427                 lstatus = be32_to_cpu(txbdp->lstatus);
2428                 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2429                         break;
2430
2431                 lstatus &= ~BD_LFLAG(TXBD_READY);
2432                 txbdp->lstatus = cpu_to_be32(lstatus);
2433                 bufaddr = be32_to_cpu(txbdp->bufPtr);
2434                 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
2435                                DMA_TO_DEVICE);
2436                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2437         }
2438         gfar_wmb();
2439         dev_kfree_skb_any(skb);
2440         return NETDEV_TX_OK;
2441 }
2442
2443 /* Stops the kernel queue, and halts the controller */
2444 static int gfar_close(struct net_device *dev)
2445 {
2446         struct gfar_private *priv = netdev_priv(dev);
2447
2448         cancel_work_sync(&priv->reset_task);
2449         stop_gfar(dev);
2450
2451         /* Disconnect from the PHY */
2452         phy_disconnect(priv->phydev);
2453         priv->phydev = NULL;
2454
2455         gfar_free_irq(priv);
2456
2457         return 0;
2458 }
2459
2460 /* Changes the mac address if the controller is not running. */
2461 static int gfar_set_mac_address(struct net_device *dev)
2462 {
2463         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2464
2465         return 0;
2466 }
2467
2468 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2469 {
2470         struct gfar_private *priv = netdev_priv(dev);
2471         int frame_size = new_mtu + ETH_HLEN;
2472
2473         if ((frame_size < 64) || (frame_size > GFAR_JUMBO_FRAME_SIZE)) {
2474                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2475                 return -EINVAL;
2476         }
2477
2478         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2479                 cpu_relax();
2480
2481         if (dev->flags & IFF_UP)
2482                 stop_gfar(dev);
2483
2484         dev->mtu = new_mtu;
2485
2486         if (dev->flags & IFF_UP)
2487                 startup_gfar(dev);
2488
2489         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2490
2491         return 0;
2492 }
2493
2494 void reset_gfar(struct net_device *ndev)
2495 {
2496         struct gfar_private *priv = netdev_priv(ndev);
2497
2498         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2499                 cpu_relax();
2500
2501         stop_gfar(ndev);
2502         startup_gfar(ndev);
2503
2504         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2505 }
2506
2507 /* gfar_reset_task gets scheduled when a packet has not been
2508  * transmitted after a set amount of time.
2509  * For now, assume that clearing out all the structures, and
2510  * starting over will fix the problem.
2511  */
2512 static void gfar_reset_task(struct work_struct *work)
2513 {
2514         struct gfar_private *priv = container_of(work, struct gfar_private,
2515                                                  reset_task);
2516         reset_gfar(priv->ndev);
2517 }
2518
2519 static void gfar_timeout(struct net_device *dev)
2520 {
2521         struct gfar_private *priv = netdev_priv(dev);
2522
2523         dev->stats.tx_errors++;
2524         schedule_work(&priv->reset_task);
2525 }
2526
2527 /* Interrupt Handler for Transmit complete */
2528 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2529 {
2530         struct net_device *dev = tx_queue->dev;
2531         struct netdev_queue *txq;
2532         struct gfar_private *priv = netdev_priv(dev);
2533         struct txbd8 *bdp, *next = NULL;
2534         struct txbd8 *lbdp = NULL;
2535         struct txbd8 *base = tx_queue->tx_bd_base;
2536         struct sk_buff *skb;
2537         int skb_dirtytx;
2538         int tx_ring_size = tx_queue->tx_ring_size;
2539         int frags = 0, nr_txbds = 0;
2540         int i;
2541         int howmany = 0;
2542         int tqi = tx_queue->qindex;
2543         unsigned int bytes_sent = 0;
2544         u32 lstatus;
2545         size_t buflen;
2546
2547         txq = netdev_get_tx_queue(dev, tqi);
2548         bdp = tx_queue->dirty_tx;
2549         skb_dirtytx = tx_queue->skb_dirtytx;
2550
2551         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2552
2553                 frags = skb_shinfo(skb)->nr_frags;
2554
2555                 /* When time stamping, one additional TxBD must be freed.
2556                  * Also, we need to dma_unmap_single() the TxPAL.
2557                  */
2558                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2559                         nr_txbds = frags + 2;
2560                 else
2561                         nr_txbds = frags + 1;
2562
2563                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2564
2565                 lstatus = be32_to_cpu(lbdp->lstatus);
2566
2567                 /* Only clean completed frames */
2568                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2569                     (lstatus & BD_LENGTH_MASK))
2570                         break;
2571
2572                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2573                         next = next_txbd(bdp, base, tx_ring_size);
2574                         buflen = be16_to_cpu(next->length) +
2575                                  GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2576                 } else
2577                         buflen = be16_to_cpu(bdp->length);
2578
2579                 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2580                                  buflen, DMA_TO_DEVICE);
2581
2582                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2583                         struct skb_shared_hwtstamps shhwtstamps;
2584                         u64 *ns = (u64 *)(((uintptr_t)skb->data + 0x10) &
2585                                           ~0x7UL);
2586
2587                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2588                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2589                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2590                         skb_tstamp_tx(skb, &shhwtstamps);
2591                         gfar_clear_txbd_status(bdp);
2592                         bdp = next;
2593                 }
2594
2595                 gfar_clear_txbd_status(bdp);
2596                 bdp = next_txbd(bdp, base, tx_ring_size);
2597
2598                 for (i = 0; i < frags; i++) {
2599                         dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2600                                        be16_to_cpu(bdp->length),
2601                                        DMA_TO_DEVICE);
2602                         gfar_clear_txbd_status(bdp);
2603                         bdp = next_txbd(bdp, base, tx_ring_size);
2604                 }
2605
2606                 bytes_sent += GFAR_CB(skb)->bytes_sent;
2607
2608                 dev_kfree_skb_any(skb);
2609
2610                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2611
2612                 skb_dirtytx = (skb_dirtytx + 1) &
2613                               TX_RING_MOD_MASK(tx_ring_size);
2614
2615                 howmany++;
2616                 spin_lock(&tx_queue->txlock);
2617                 tx_queue->num_txbdfree += nr_txbds;
2618                 spin_unlock(&tx_queue->txlock);
2619         }
2620
2621         /* If we freed a buffer, we can restart transmission, if necessary */
2622         if (tx_queue->num_txbdfree &&
2623             netif_tx_queue_stopped(txq) &&
2624             !(test_bit(GFAR_DOWN, &priv->state)))
2625                 netif_wake_subqueue(priv->ndev, tqi);
2626
2627         /* Update dirty indicators */
2628         tx_queue->skb_dirtytx = skb_dirtytx;
2629         tx_queue->dirty_tx = bdp;
2630
2631         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2632 }
2633
2634 static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb)
2635 {
2636         struct page *page;
2637         dma_addr_t addr;
2638
2639         page = dev_alloc_page();
2640         if (unlikely(!page))
2641                 return false;
2642
2643         addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
2644         if (unlikely(dma_mapping_error(rxq->dev, addr))) {
2645                 __free_page(page);
2646
2647                 return false;
2648         }
2649
2650         rxb->dma = addr;
2651         rxb->page = page;
2652         rxb->page_offset = 0;
2653
2654         return true;
2655 }
2656
2657 static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue)
2658 {
2659         struct gfar_private *priv = netdev_priv(rx_queue->ndev);
2660         struct gfar_extra_stats *estats = &priv->extra_stats;
2661
2662         netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n");
2663         atomic64_inc(&estats->rx_alloc_err);
2664 }
2665
2666 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
2667                                 int alloc_cnt)
2668 {
2669         struct rxbd8 *bdp;
2670         struct gfar_rx_buff *rxb;
2671         int i;
2672
2673         i = rx_queue->next_to_use;
2674         bdp = &rx_queue->rx_bd_base[i];
2675         rxb = &rx_queue->rx_buff[i];
2676
2677         while (alloc_cnt--) {
2678                 /* try reuse page */
2679                 if (unlikely(!rxb->page)) {
2680                         if (unlikely(!gfar_new_page(rx_queue, rxb))) {
2681                                 gfar_rx_alloc_err(rx_queue);
2682                                 break;
2683                         }
2684                 }
2685
2686                 /* Setup the new RxBD */
2687                 gfar_init_rxbdp(rx_queue, bdp,
2688                                 rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT);
2689
2690                 /* Update to the next pointer */
2691                 bdp++;
2692                 rxb++;
2693
2694                 if (unlikely(++i == rx_queue->rx_ring_size)) {
2695                         i = 0;
2696                         bdp = rx_queue->rx_bd_base;
2697                         rxb = rx_queue->rx_buff;
2698                 }
2699         }
2700
2701         rx_queue->next_to_use = i;
2702         rx_queue->next_to_alloc = i;
2703 }
2704
2705 static void count_errors(u32 lstatus, struct net_device *ndev)
2706 {
2707         struct gfar_private *priv = netdev_priv(ndev);
2708         struct net_device_stats *stats = &ndev->stats;
2709         struct gfar_extra_stats *estats = &priv->extra_stats;
2710
2711         /* If the packet was truncated, none of the other errors matter */
2712         if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) {
2713                 stats->rx_length_errors++;
2714
2715                 atomic64_inc(&estats->rx_trunc);
2716
2717                 return;
2718         }
2719         /* Count the errors, if there were any */
2720         if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) {
2721                 stats->rx_length_errors++;
2722
2723                 if (lstatus & BD_LFLAG(RXBD_LARGE))
2724                         atomic64_inc(&estats->rx_large);
2725                 else
2726                         atomic64_inc(&estats->rx_short);
2727         }
2728         if (lstatus & BD_LFLAG(RXBD_NONOCTET)) {
2729                 stats->rx_frame_errors++;
2730                 atomic64_inc(&estats->rx_nonoctet);
2731         }
2732         if (lstatus & BD_LFLAG(RXBD_CRCERR)) {
2733                 atomic64_inc(&estats->rx_crcerr);
2734                 stats->rx_crc_errors++;
2735         }
2736         if (lstatus & BD_LFLAG(RXBD_OVERRUN)) {
2737                 atomic64_inc(&estats->rx_overrun);
2738                 stats->rx_over_errors++;
2739         }
2740 }
2741
2742 irqreturn_t gfar_receive(int irq, void *grp_id)
2743 {
2744         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2745         unsigned long flags;
2746         u32 imask;
2747
2748         if (likely(napi_schedule_prep(&grp->napi_rx))) {
2749                 spin_lock_irqsave(&grp->grplock, flags);
2750                 imask = gfar_read(&grp->regs->imask);
2751                 imask &= IMASK_RX_DISABLED;
2752                 gfar_write(&grp->regs->imask, imask);
2753                 spin_unlock_irqrestore(&grp->grplock, flags);
2754                 __napi_schedule(&grp->napi_rx);
2755         } else {
2756                 /* Clear IEVENT, so interrupts aren't called again
2757                  * because of the packets that have already arrived.
2758                  */
2759                 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2760         }
2761
2762         return IRQ_HANDLED;
2763 }
2764
2765 /* Interrupt Handler for Transmit complete */
2766 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2767 {
2768         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2769         unsigned long flags;
2770         u32 imask;
2771
2772         if (likely(napi_schedule_prep(&grp->napi_tx))) {
2773                 spin_lock_irqsave(&grp->grplock, flags);
2774                 imask = gfar_read(&grp->regs->imask);
2775                 imask &= IMASK_TX_DISABLED;
2776                 gfar_write(&grp->regs->imask, imask);
2777                 spin_unlock_irqrestore(&grp->grplock, flags);
2778                 __napi_schedule(&grp->napi_tx);
2779         } else {
2780                 /* Clear IEVENT, so interrupts aren't called again
2781                  * because of the packets that have already arrived.
2782                  */
2783                 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2784         }
2785
2786         return IRQ_HANDLED;
2787 }
2788
2789 static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus,
2790                              struct sk_buff *skb, bool first)
2791 {
2792         unsigned int size = lstatus & BD_LENGTH_MASK;
2793         struct page *page = rxb->page;
2794
2795         /* Remove the FCS from the packet length */
2796         if (likely(lstatus & BD_LFLAG(RXBD_LAST)))
2797                 size -= ETH_FCS_LEN;
2798
2799         if (likely(first))
2800                 skb_put(skb, size);
2801         else
2802                 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
2803                                 rxb->page_offset + RXBUF_ALIGNMENT,
2804                                 size, GFAR_RXB_TRUESIZE);
2805
2806         /* try reuse page */
2807         if (unlikely(page_count(page) != 1))
2808                 return false;
2809
2810         /* change offset to the other half */
2811         rxb->page_offset ^= GFAR_RXB_TRUESIZE;
2812
2813         atomic_inc(&page->_count);
2814
2815         return true;
2816 }
2817
2818 static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq,
2819                                struct gfar_rx_buff *old_rxb)
2820 {
2821         struct gfar_rx_buff *new_rxb;
2822         u16 nta = rxq->next_to_alloc;
2823
2824         new_rxb = &rxq->rx_buff[nta];
2825
2826         /* find next buf that can reuse a page */
2827         nta++;
2828         rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0;
2829
2830         /* copy page reference */
2831         *new_rxb = *old_rxb;
2832
2833         /* sync for use by the device */
2834         dma_sync_single_range_for_device(rxq->dev, old_rxb->dma,
2835                                          old_rxb->page_offset,
2836                                          GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2837 }
2838
2839 static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue,
2840                                             u32 lstatus, struct sk_buff *skb)
2841 {
2842         struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean];
2843         struct page *page = rxb->page;
2844         bool first = false;
2845
2846         if (likely(!skb)) {
2847                 void *buff_addr = page_address(page) + rxb->page_offset;
2848
2849                 skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE);
2850                 if (unlikely(!skb)) {
2851                         gfar_rx_alloc_err(rx_queue);
2852                         return NULL;
2853                 }
2854                 skb_reserve(skb, RXBUF_ALIGNMENT);
2855                 first = true;
2856         }
2857
2858         dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset,
2859                                       GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2860
2861         if (gfar_add_rx_frag(rxb, lstatus, skb, first)) {
2862                 /* reuse the free half of the page */
2863                 gfar_reuse_rx_page(rx_queue, rxb);
2864         } else {
2865                 /* page cannot be reused, unmap it */
2866                 dma_unmap_page(rx_queue->dev, rxb->dma,
2867                                PAGE_SIZE, DMA_FROM_DEVICE);
2868         }
2869
2870         /* clear rxb content */
2871         rxb->page = NULL;
2872
2873         return skb;
2874 }
2875
2876 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2877 {
2878         /* If valid headers were found, and valid sums
2879          * were verified, then we tell the kernel that no
2880          * checksumming is necessary.  Otherwise, it is [FIXME]
2881          */
2882         if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
2883             (RXFCB_CIP | RXFCB_CTU))
2884                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2885         else
2886                 skb_checksum_none_assert(skb);
2887 }
2888
2889 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2890 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb)
2891 {
2892         struct gfar_private *priv = netdev_priv(ndev);
2893         struct rxfcb *fcb = NULL;
2894
2895         /* fcb is at the beginning if exists */
2896         fcb = (struct rxfcb *)skb->data;
2897
2898         /* Remove the FCB from the skb
2899          * Remove the padded bytes, if there are any
2900          */
2901         if (priv->uses_rxfcb)
2902                 skb_pull(skb, GMAC_FCB_LEN);
2903
2904         /* Get receive timestamp from the skb */
2905         if (priv->hwts_rx_en) {
2906                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2907                 u64 *ns = (u64 *) skb->data;
2908
2909                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2910                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2911         }
2912
2913         if (priv->padding)
2914                 skb_pull(skb, priv->padding);
2915
2916         if (ndev->features & NETIF_F_RXCSUM)
2917                 gfar_rx_checksum(skb, fcb);
2918
2919         /* Tell the skb what kind of packet this is */
2920         skb->protocol = eth_type_trans(skb, ndev);
2921
2922         /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
2923          * Even if vlan rx accel is disabled, on some chips
2924          * RXFCB_VLN is pseudo randomly set.
2925          */
2926         if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX &&
2927             be16_to_cpu(fcb->flags) & RXFCB_VLN)
2928                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2929                                        be16_to_cpu(fcb->vlctl));
2930 }
2931
2932 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2933  * until the budget/quota has been reached. Returns the number
2934  * of frames handled
2935  */
2936 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2937 {
2938         struct net_device *ndev = rx_queue->ndev;
2939         struct gfar_private *priv = netdev_priv(ndev);
2940         struct rxbd8 *bdp;
2941         int i, howmany = 0;
2942         struct sk_buff *skb = rx_queue->skb;
2943         int cleaned_cnt = gfar_rxbd_unused(rx_queue);
2944         unsigned int total_bytes = 0, total_pkts = 0;
2945
2946         /* Get the first full descriptor */
2947         i = rx_queue->next_to_clean;
2948
2949         while (rx_work_limit--) {
2950                 u32 lstatus;
2951
2952                 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) {
2953                         gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
2954                         cleaned_cnt = 0;
2955                 }
2956
2957                 bdp = &rx_queue->rx_bd_base[i];
2958                 lstatus = be32_to_cpu(bdp->lstatus);
2959                 if (lstatus & BD_LFLAG(RXBD_EMPTY))
2960                         break;
2961
2962                 /* order rx buffer descriptor reads */
2963                 rmb();
2964
2965                 /* fetch next to clean buffer from the ring */
2966                 skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb);
2967                 if (unlikely(!skb))
2968                         break;
2969
2970                 cleaned_cnt++;
2971                 howmany++;
2972
2973                 if (unlikely(++i == rx_queue->rx_ring_size))
2974                         i = 0;
2975
2976                 rx_queue->next_to_clean = i;
2977
2978                 /* fetch next buffer if not the last in frame */
2979                 if (!(lstatus & BD_LFLAG(RXBD_LAST)))
2980                         continue;
2981
2982                 if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) {
2983                         count_errors(lstatus, ndev);
2984
2985                         /* discard faulty buffer */
2986                         dev_kfree_skb(skb);
2987                         skb = NULL;
2988                         rx_queue->stats.rx_dropped++;
2989                         continue;
2990                 }
2991
2992                 /* Increment the number of packets */
2993                 total_pkts++;
2994                 total_bytes += skb->len;
2995
2996                 skb_record_rx_queue(skb, rx_queue->qindex);
2997
2998                 gfar_process_frame(ndev, skb);
2999
3000                 /* Send the packet up the stack */
3001                 napi_gro_receive(&rx_queue->grp->napi_rx, skb);
3002
3003                 skb = NULL;
3004         }
3005
3006         /* Store incomplete frames for completion */
3007         rx_queue->skb = skb;
3008
3009         rx_queue->stats.rx_packets += total_pkts;
3010         rx_queue->stats.rx_bytes += total_bytes;
3011
3012         if (cleaned_cnt)
3013                 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3014
3015         /* Update Last Free RxBD pointer for LFC */
3016         if (unlikely(priv->tx_actual_en)) {
3017                 u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3018
3019                 gfar_write(rx_queue->rfbptr, bdp_dma);
3020         }
3021
3022         return howmany;
3023 }
3024
3025 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
3026 {
3027         struct gfar_priv_grp *gfargrp =
3028                 container_of(napi, struct gfar_priv_grp, napi_rx);
3029         struct gfar __iomem *regs = gfargrp->regs;
3030         struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
3031         int work_done = 0;
3032
3033         /* Clear IEVENT, so interrupts aren't called again
3034          * because of the packets that have already arrived
3035          */
3036         gfar_write(&regs->ievent, IEVENT_RX_MASK);
3037
3038         work_done = gfar_clean_rx_ring(rx_queue, budget);
3039
3040         if (work_done < budget) {
3041                 u32 imask;
3042                 napi_complete(napi);
3043                 /* Clear the halt bit in RSTAT */
3044                 gfar_write(&regs->rstat, gfargrp->rstat);
3045
3046                 spin_lock_irq(&gfargrp->grplock);
3047                 imask = gfar_read(&regs->imask);
3048                 imask |= IMASK_RX_DEFAULT;
3049                 gfar_write(&regs->imask, imask);
3050                 spin_unlock_irq(&gfargrp->grplock);
3051         }
3052
3053         return work_done;
3054 }
3055
3056 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
3057 {
3058         struct gfar_priv_grp *gfargrp =
3059                 container_of(napi, struct gfar_priv_grp, napi_tx);
3060         struct gfar __iomem *regs = gfargrp->regs;
3061         struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
3062         u32 imask;
3063
3064         /* Clear IEVENT, so interrupts aren't called again
3065          * because of the packets that have already arrived
3066          */
3067         gfar_write(&regs->ievent, IEVENT_TX_MASK);
3068
3069         /* run Tx cleanup to completion */
3070         if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
3071                 gfar_clean_tx_ring(tx_queue);
3072
3073         napi_complete(napi);
3074
3075         spin_lock_irq(&gfargrp->grplock);
3076         imask = gfar_read(&regs->imask);
3077         imask |= IMASK_TX_DEFAULT;
3078         gfar_write(&regs->imask, imask);
3079         spin_unlock_irq(&gfargrp->grplock);
3080
3081         return 0;
3082 }
3083
3084 static int gfar_poll_rx(struct napi_struct *napi, int budget)
3085 {
3086         struct gfar_priv_grp *gfargrp =
3087                 container_of(napi, struct gfar_priv_grp, napi_rx);
3088         struct gfar_private *priv = gfargrp->priv;
3089         struct gfar __iomem *regs = gfargrp->regs;
3090         struct gfar_priv_rx_q *rx_queue = NULL;
3091         int work_done = 0, work_done_per_q = 0;
3092         int i, budget_per_q = 0;
3093         unsigned long rstat_rxf;
3094         int num_act_queues;
3095
3096         /* Clear IEVENT, so interrupts aren't called again
3097          * because of the packets that have already arrived
3098          */
3099         gfar_write(&regs->ievent, IEVENT_RX_MASK);
3100
3101         rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
3102
3103         num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
3104         if (num_act_queues)
3105                 budget_per_q = budget/num_act_queues;
3106
3107         for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
3108                 /* skip queue if not active */
3109                 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
3110                         continue;
3111
3112                 rx_queue = priv->rx_queue[i];
3113                 work_done_per_q =
3114                         gfar_clean_rx_ring(rx_queue, budget_per_q);
3115                 work_done += work_done_per_q;
3116
3117                 /* finished processing this queue */
3118                 if (work_done_per_q < budget_per_q) {
3119                         /* clear active queue hw indication */
3120                         gfar_write(&regs->rstat,
3121                                    RSTAT_CLEAR_RXF0 >> i);
3122                         num_act_queues--;
3123
3124                         if (!num_act_queues)
3125                                 break;
3126                 }
3127         }
3128
3129         if (!num_act_queues) {
3130                 u32 imask;
3131                 napi_complete(napi);
3132
3133                 /* Clear the halt bit in RSTAT */
3134                 gfar_write(&regs->rstat, gfargrp->rstat);
3135
3136                 spin_lock_irq(&gfargrp->grplock);
3137                 imask = gfar_read(&regs->imask);
3138                 imask |= IMASK_RX_DEFAULT;
3139                 gfar_write(&regs->imask, imask);
3140                 spin_unlock_irq(&gfargrp->grplock);
3141         }
3142
3143         return work_done;
3144 }
3145
3146 static int gfar_poll_tx(struct napi_struct *napi, int budget)
3147 {
3148         struct gfar_priv_grp *gfargrp =
3149                 container_of(napi, struct gfar_priv_grp, napi_tx);
3150         struct gfar_private *priv = gfargrp->priv;
3151         struct gfar __iomem *regs = gfargrp->regs;
3152         struct gfar_priv_tx_q *tx_queue = NULL;
3153         int has_tx_work = 0;
3154         int i;
3155
3156         /* Clear IEVENT, so interrupts aren't called again
3157          * because of the packets that have already arrived
3158          */
3159         gfar_write(&regs->ievent, IEVENT_TX_MASK);
3160
3161         for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
3162                 tx_queue = priv->tx_queue[i];
3163                 /* run Tx cleanup to completion */
3164                 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
3165                         gfar_clean_tx_ring(tx_queue);
3166                         has_tx_work = 1;
3167                 }
3168         }
3169
3170         if (!has_tx_work) {
3171                 u32 imask;
3172                 napi_complete(napi);
3173
3174                 spin_lock_irq(&gfargrp->grplock);
3175                 imask = gfar_read(&regs->imask);
3176                 imask |= IMASK_TX_DEFAULT;
3177                 gfar_write(&regs->imask, imask);
3178                 spin_unlock_irq(&gfargrp->grplock);
3179         }
3180
3181         return 0;
3182 }
3183
3184
3185 #ifdef CONFIG_NET_POLL_CONTROLLER
3186 /* Polling 'interrupt' - used by things like netconsole to send skbs
3187  * without having to re-enable interrupts. It's not called while
3188  * the interrupt routine is executing.
3189  */
3190 static void gfar_netpoll(struct net_device *dev)
3191 {
3192         struct gfar_private *priv = netdev_priv(dev);
3193         int i;
3194
3195         /* If the device has multiple interrupts, run tx/rx */
3196         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3197                 for (i = 0; i < priv->num_grps; i++) {
3198                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3199
3200                         disable_irq(gfar_irq(grp, TX)->irq);
3201                         disable_irq(gfar_irq(grp, RX)->irq);
3202                         disable_irq(gfar_irq(grp, ER)->irq);
3203                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3204                         enable_irq(gfar_irq(grp, ER)->irq);
3205                         enable_irq(gfar_irq(grp, RX)->irq);
3206                         enable_irq(gfar_irq(grp, TX)->irq);
3207                 }
3208         } else {
3209                 for (i = 0; i < priv->num_grps; i++) {
3210                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3211
3212                         disable_irq(gfar_irq(grp, TX)->irq);
3213                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3214                         enable_irq(gfar_irq(grp, TX)->irq);
3215                 }
3216         }
3217 }
3218 #endif
3219
3220 /* The interrupt handler for devices with one interrupt */
3221 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
3222 {
3223         struct gfar_priv_grp *gfargrp = grp_id;
3224
3225         /* Save ievent for future reference */
3226         u32 events = gfar_read(&gfargrp->regs->ievent);
3227
3228         /* Check for reception */
3229         if (events & IEVENT_RX_MASK)
3230                 gfar_receive(irq, grp_id);
3231
3232         /* Check for transmit completion */
3233         if (events & IEVENT_TX_MASK)
3234                 gfar_transmit(irq, grp_id);
3235
3236         /* Check for errors */
3237         if (events & IEVENT_ERR_MASK)
3238                 gfar_error(irq, grp_id);
3239
3240         return IRQ_HANDLED;
3241 }
3242
3243 /* Called every time the controller might need to be made
3244  * aware of new link state.  The PHY code conveys this
3245  * information through variables in the phydev structure, and this
3246  * function converts those variables into the appropriate
3247  * register values, and can bring down the device if needed.
3248  */
3249 static void adjust_link(struct net_device *dev)
3250 {
3251         struct gfar_private *priv = netdev_priv(dev);
3252         struct phy_device *phydev = priv->phydev;
3253
3254         if (unlikely(phydev->link != priv->oldlink ||
3255                      (phydev->link && (phydev->duplex != priv->oldduplex ||
3256                                        phydev->speed != priv->oldspeed))))
3257                 gfar_update_link_state(priv);
3258 }
3259
3260 /* Update the hash table based on the current list of multicast
3261  * addresses we subscribe to.  Also, change the promiscuity of
3262  * the device based on the flags (this function is called
3263  * whenever dev->flags is changed
3264  */
3265 static void gfar_set_multi(struct net_device *dev)
3266 {
3267         struct netdev_hw_addr *ha;
3268         struct gfar_private *priv = netdev_priv(dev);
3269         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3270         u32 tempval;
3271
3272         if (dev->flags & IFF_PROMISC) {
3273                 /* Set RCTRL to PROM */
3274                 tempval = gfar_read(&regs->rctrl);
3275                 tempval |= RCTRL_PROM;
3276                 gfar_write(&regs->rctrl, tempval);
3277         } else {
3278                 /* Set RCTRL to not PROM */
3279                 tempval = gfar_read(&regs->rctrl);
3280                 tempval &= ~(RCTRL_PROM);
3281                 gfar_write(&regs->rctrl, tempval);
3282         }
3283
3284         if (dev->flags & IFF_ALLMULTI) {
3285                 /* Set the hash to rx all multicast frames */
3286                 gfar_write(&regs->igaddr0, 0xffffffff);
3287                 gfar_write(&regs->igaddr1, 0xffffffff);
3288                 gfar_write(&regs->igaddr2, 0xffffffff);
3289                 gfar_write(&regs->igaddr3, 0xffffffff);
3290                 gfar_write(&regs->igaddr4, 0xffffffff);
3291                 gfar_write(&regs->igaddr5, 0xffffffff);
3292                 gfar_write(&regs->igaddr6, 0xffffffff);
3293                 gfar_write(&regs->igaddr7, 0xffffffff);
3294                 gfar_write(&regs->gaddr0, 0xffffffff);
3295                 gfar_write(&regs->gaddr1, 0xffffffff);
3296                 gfar_write(&regs->gaddr2, 0xffffffff);
3297                 gfar_write(&regs->gaddr3, 0xffffffff);
3298                 gfar_write(&regs->gaddr4, 0xffffffff);
3299                 gfar_write(&regs->gaddr5, 0xffffffff);
3300                 gfar_write(&regs->gaddr6, 0xffffffff);
3301                 gfar_write(&regs->gaddr7, 0xffffffff);
3302         } else {
3303                 int em_num;
3304                 int idx;
3305
3306                 /* zero out the hash */
3307                 gfar_write(&regs->igaddr0, 0x0);
3308                 gfar_write(&regs->igaddr1, 0x0);
3309                 gfar_write(&regs->igaddr2, 0x0);
3310                 gfar_write(&regs->igaddr3, 0x0);
3311                 gfar_write(&regs->igaddr4, 0x0);
3312                 gfar_write(&regs->igaddr5, 0x0);
3313                 gfar_write(&regs->igaddr6, 0x0);
3314                 gfar_write(&regs->igaddr7, 0x0);
3315                 gfar_write(&regs->gaddr0, 0x0);
3316                 gfar_write(&regs->gaddr1, 0x0);
3317                 gfar_write(&regs->gaddr2, 0x0);
3318                 gfar_write(&regs->gaddr3, 0x0);
3319                 gfar_write(&regs->gaddr4, 0x0);
3320                 gfar_write(&regs->gaddr5, 0x0);
3321                 gfar_write(&regs->gaddr6, 0x0);
3322                 gfar_write(&regs->gaddr7, 0x0);
3323
3324                 /* If we have extended hash tables, we need to
3325                  * clear the exact match registers to prepare for
3326                  * setting them
3327                  */
3328                 if (priv->extended_hash) {
3329                         em_num = GFAR_EM_NUM + 1;
3330                         gfar_clear_exact_match(dev);
3331                         idx = 1;
3332                 } else {
3333                         idx = 0;
3334                         em_num = 0;
3335                 }
3336
3337                 if (netdev_mc_empty(dev))
3338                         return;
3339
3340                 /* Parse the list, and set the appropriate bits */
3341                 netdev_for_each_mc_addr(ha, dev) {
3342                         if (idx < em_num) {
3343                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3344                                 idx++;
3345                         } else
3346                                 gfar_set_hash_for_addr(dev, ha->addr);
3347                 }
3348         }
3349 }
3350
3351
3352 /* Clears each of the exact match registers to zero, so they
3353  * don't interfere with normal reception
3354  */
3355 static void gfar_clear_exact_match(struct net_device *dev)
3356 {
3357         int idx;
3358         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3359
3360         for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3361                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3362 }
3363
3364 /* Set the appropriate hash bit for the given addr */
3365 /* The algorithm works like so:
3366  * 1) Take the Destination Address (ie the multicast address), and
3367  * do a CRC on it (little endian), and reverse the bits of the
3368  * result.
3369  * 2) Use the 8 most significant bits as a hash into a 256-entry
3370  * table.  The table is controlled through 8 32-bit registers:
3371  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3372  * gaddr7.  This means that the 3 most significant bits in the
3373  * hash index which gaddr register to use, and the 5 other bits
3374  * indicate which bit (assuming an IBM numbering scheme, which
3375  * for PowerPC (tm) is usually the case) in the register holds
3376  * the entry.
3377  */
3378 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3379 {
3380         u32 tempval;
3381         struct gfar_private *priv = netdev_priv(dev);
3382         u32 result = ether_crc(ETH_ALEN, addr);
3383         int width = priv->hash_width;
3384         u8 whichbit = (result >> (32 - width)) & 0x1f;
3385         u8 whichreg = result >> (32 - width + 5);
3386         u32 value = (1 << (31-whichbit));
3387
3388         tempval = gfar_read(priv->hash_regs[whichreg]);
3389         tempval |= value;
3390         gfar_write(priv->hash_regs[whichreg], tempval);
3391 }
3392
3393
3394 /* There are multiple MAC Address register pairs on some controllers
3395  * This function sets the numth pair to a given address
3396  */
3397 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3398                                   const u8 *addr)
3399 {
3400         struct gfar_private *priv = netdev_priv(dev);
3401         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3402         u32 tempval;
3403         u32 __iomem *macptr = &regs->macstnaddr1;
3404
3405         macptr += num*2;
3406
3407         /* For a station address of 0x12345678ABCD in transmission
3408          * order (BE), MACnADDR1 is set to 0xCDAB7856 and
3409          * MACnADDR2 is set to 0x34120000.
3410          */
3411         tempval = (addr[5] << 24) | (addr[4] << 16) |
3412                   (addr[3] << 8)  |  addr[2];
3413
3414         gfar_write(macptr, tempval);
3415
3416         tempval = (addr[1] << 24) | (addr[0] << 16);
3417
3418         gfar_write(macptr+1, tempval);
3419 }
3420
3421 /* GFAR error interrupt handler */
3422 static irqreturn_t gfar_error(int irq, void *grp_id)
3423 {
3424         struct gfar_priv_grp *gfargrp = grp_id;
3425         struct gfar __iomem *regs = gfargrp->regs;
3426         struct gfar_private *priv= gfargrp->priv;
3427         struct net_device *dev = priv->ndev;
3428
3429         /* Save ievent for future reference */
3430         u32 events = gfar_read(&regs->ievent);
3431
3432         /* Clear IEVENT */
3433         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3434
3435         /* Magic Packet is not an error. */
3436         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3437             (events & IEVENT_MAG))
3438                 events &= ~IEVENT_MAG;
3439
3440         /* Hmm... */
3441         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3442                 netdev_dbg(dev,
3443                            "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3444                            events, gfar_read(&regs->imask));
3445
3446         /* Update the error counters */
3447         if (events & IEVENT_TXE) {
3448                 dev->stats.tx_errors++;
3449
3450                 if (events & IEVENT_LC)
3451                         dev->stats.tx_window_errors++;
3452                 if (events & IEVENT_CRL)
3453                         dev->stats.tx_aborted_errors++;
3454                 if (events & IEVENT_XFUN) {
3455                         netif_dbg(priv, tx_err, dev,
3456                                   "TX FIFO underrun, packet dropped\n");
3457                         dev->stats.tx_dropped++;
3458                         atomic64_inc(&priv->extra_stats.tx_underrun);
3459
3460                         schedule_work(&priv->reset_task);
3461                 }
3462                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3463         }
3464         if (events & IEVENT_BSY) {
3465                 dev->stats.rx_over_errors++;
3466                 atomic64_inc(&priv->extra_stats.rx_bsy);
3467
3468                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3469                           gfar_read(&regs->rstat));
3470         }
3471         if (events & IEVENT_BABR) {
3472                 dev->stats.rx_errors++;
3473                 atomic64_inc(&priv->extra_stats.rx_babr);
3474
3475                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3476         }
3477         if (events & IEVENT_EBERR) {
3478                 atomic64_inc(&priv->extra_stats.eberr);
3479                 netif_dbg(priv, rx_err, dev, "bus error\n");
3480         }
3481         if (events & IEVENT_RXC)
3482                 netif_dbg(priv, rx_status, dev, "control frame\n");
3483
3484         if (events & IEVENT_BABT) {
3485                 atomic64_inc(&priv->extra_stats.tx_babt);
3486                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3487         }
3488         return IRQ_HANDLED;
3489 }
3490
3491 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3492 {
3493         struct phy_device *phydev = priv->phydev;
3494         u32 val = 0;
3495
3496         if (!phydev->duplex)
3497                 return val;
3498
3499         if (!priv->pause_aneg_en) {
3500                 if (priv->tx_pause_en)
3501                         val |= MACCFG1_TX_FLOW;
3502                 if (priv->rx_pause_en)
3503                         val |= MACCFG1_RX_FLOW;
3504         } else {
3505                 u16 lcl_adv, rmt_adv;
3506                 u8 flowctrl;
3507                 /* get link partner capabilities */
3508                 rmt_adv = 0;
3509                 if (phydev->pause)
3510                         rmt_adv = LPA_PAUSE_CAP;
3511                 if (phydev->asym_pause)
3512                         rmt_adv |= LPA_PAUSE_ASYM;
3513
3514                 lcl_adv = 0;
3515                 if (phydev->advertising & ADVERTISED_Pause)
3516                         lcl_adv |= ADVERTISE_PAUSE_CAP;
3517                 if (phydev->advertising & ADVERTISED_Asym_Pause)
3518                         lcl_adv |= ADVERTISE_PAUSE_ASYM;
3519
3520                 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3521                 if (flowctrl & FLOW_CTRL_TX)
3522                         val |= MACCFG1_TX_FLOW;
3523                 if (flowctrl & FLOW_CTRL_RX)
3524                         val |= MACCFG1_RX_FLOW;
3525         }
3526
3527         return val;
3528 }
3529
3530 static noinline void gfar_update_link_state(struct gfar_private *priv)
3531 {
3532         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3533         struct phy_device *phydev = priv->phydev;
3534         struct gfar_priv_rx_q *rx_queue = NULL;
3535         int i;
3536
3537         if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
3538                 return;
3539
3540         if (phydev->link) {
3541                 u32 tempval1 = gfar_read(&regs->maccfg1);
3542                 u32 tempval = gfar_read(&regs->maccfg2);
3543                 u32 ecntrl = gfar_read(&regs->ecntrl);
3544                 u32 tx_flow_oldval = (tempval & MACCFG1_TX_FLOW);
3545
3546                 if (phydev->duplex != priv->oldduplex) {
3547                         if (!(phydev->duplex))
3548                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
3549                         else
3550                                 tempval |= MACCFG2_FULL_DUPLEX;
3551
3552                         priv->oldduplex = phydev->duplex;
3553                 }
3554
3555                 if (phydev->speed != priv->oldspeed) {
3556                         switch (phydev->speed) {
3557                         case 1000:
3558                                 tempval =
3559                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3560
3561                                 ecntrl &= ~(ECNTRL_R100);
3562                                 break;
3563                         case 100:
3564                         case 10:
3565                                 tempval =
3566                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3567
3568                                 /* Reduced mode distinguishes
3569                                  * between 10 and 100
3570                                  */
3571                                 if (phydev->speed == SPEED_100)
3572                                         ecntrl |= ECNTRL_R100;
3573                                 else
3574                                         ecntrl &= ~(ECNTRL_R100);
3575                                 break;
3576                         default:
3577                                 netif_warn(priv, link, priv->ndev,
3578                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
3579                                            phydev->speed);
3580                                 break;
3581                         }
3582
3583                         priv->oldspeed = phydev->speed;
3584                 }
3585
3586                 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3587                 tempval1 |= gfar_get_flowctrl_cfg(priv);
3588
3589                 /* Turn last free buffer recording on */
3590                 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
3591                         for (i = 0; i < priv->num_rx_queues; i++) {
3592                                 u32 bdp_dma;
3593
3594                                 rx_queue = priv->rx_queue[i];
3595                                 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3596                                 gfar_write(rx_queue->rfbptr, bdp_dma);
3597                         }
3598
3599                         priv->tx_actual_en = 1;
3600                 }
3601
3602                 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
3603                         priv->tx_actual_en = 0;
3604
3605                 gfar_write(&regs->maccfg1, tempval1);
3606                 gfar_write(&regs->maccfg2, tempval);
3607                 gfar_write(&regs->ecntrl, ecntrl);
3608
3609                 if (!priv->oldlink)
3610                         priv->oldlink = 1;
3611
3612         } else if (priv->oldlink) {
3613                 priv->oldlink = 0;
3614                 priv->oldspeed = 0;
3615                 priv->oldduplex = -1;
3616         }
3617
3618         if (netif_msg_link(priv))
3619                 phy_print_status(phydev);
3620 }
3621
3622 static const struct of_device_id gfar_match[] =
3623 {
3624         {
3625                 .type = "network",
3626                 .compatible = "gianfar",
3627         },
3628         {
3629                 .compatible = "fsl,etsec2",
3630         },
3631         {},
3632 };
3633 MODULE_DEVICE_TABLE(of, gfar_match);
3634
3635 /* Structure for a device driver */
3636 static struct platform_driver gfar_driver = {
3637         .driver = {
3638                 .name = "fsl-gianfar",
3639                 .pm = GFAR_PM_OPS,
3640                 .of_match_table = gfar_match,
3641         },
3642         .probe = gfar_probe,
3643         .remove = gfar_remove,
3644 };
3645
3646 module_platform_driver(gfar_driver);