drivers/net/ethernet/intel/i40evf/i40e_type.h

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
   4  * Copyright(c) 2013 - 2015 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #ifndef _I40E_TYPE_H_
  28 #define _I40E_TYPE_H_
  29
  30 #include "i40e_status.h"
  31 #include "i40e_osdep.h"
  32 #include "i40e_register.h"
  33 #include "i40e_adminq.h"
  34 #include "i40e_hmc.h"
  35 #include "i40e_lan_hmc.h"
  36 #include "i40e_devids.h"
  37
  38 /* I40E_MASK is a macro used on 32 bit registers */
  39 #define I40E_MASK(mask, shift) (mask << shift)
  40
  41 #define I40E_MAX_VSI_QP                 16
  42 #define I40E_MAX_VF_VSI                 3
  43 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  44 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  45
  46 /* Max default timeout in ms, */
  47 #define I40E_MAX_NVM_TIMEOUT            18000
  48
  49 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  50 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  51
  52 /* forward declaration */
  53 struct i40e_hw;
  54 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  55
  56 /* Data type manipulation macros. */
  57
  58 #define I40E_DESC_UNUSED(R)     \
  59         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  60         (R)->next_to_clean - (R)->next_to_use - 1)
  61
  62 /* bitfields for Tx queue mapping in QTX_CTL */
  63 #define I40E_QTX_CTL_VF_QUEUE   0x0
  64 #define I40E_QTX_CTL_VM_QUEUE   0x1
  65 #define I40E_QTX_CTL_PF_QUEUE   0x2
  66
  67 /* debug masks - set these bits in hw->debug_mask to control output */
  68 enum i40e_debug_mask {
  69         I40E_DEBUG_INIT                 = 0x00000001,
  70         I40E_DEBUG_RELEASE              = 0x00000002,
  71
  72         I40E_DEBUG_LINK                 = 0x00000010,
  73         I40E_DEBUG_PHY                  = 0x00000020,
  74         I40E_DEBUG_HMC                  = 0x00000040,
  75         I40E_DEBUG_NVM                  = 0x00000080,
  76         I40E_DEBUG_LAN                  = 0x00000100,
  77         I40E_DEBUG_FLOW                 = 0x00000200,
  78         I40E_DEBUG_DCB                  = 0x00000400,
  79         I40E_DEBUG_DIAG                 = 0x00000800,
  80         I40E_DEBUG_FD                   = 0x00001000,
  81
  82         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
  83         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
  84         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
  85         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
  86         I40E_DEBUG_AQ                   = 0x0F000000,
  87
  88         I40E_DEBUG_USER                 = 0xF0000000,
  89
  90         I40E_DEBUG_ALL                  = 0xFFFFFFFF
  91 };
  92
  93 /* These are structs for managing the hardware information and the operations.
  94  * The structures of function pointers are filled out at init time when we
  95  * know for sure exactly which hardware we're working with.  This gives us the
  96  * flexibility of using the same main driver code but adapting to slightly
  97  * different hardware needs as new parts are developed.  For this architecture,
  98  * the Firmware and AdminQ are intended to insulate the driver from most of the
  99  * future changes, but these structures will also do part of the job.
 100  */
 101 enum i40e_mac_type {
 102         I40E_MAC_UNKNOWN = 0,
 103         I40E_MAC_X710,
 104         I40E_MAC_XL710,
 105         I40E_MAC_VF,
 106         I40E_MAC_X722,
 107         I40E_MAC_X722_VF,
 108         I40E_MAC_GENERIC,
 109 };
 110
 111 enum i40e_media_type {
 112         I40E_MEDIA_TYPE_UNKNOWN = 0,
 113         I40E_MEDIA_TYPE_FIBER,
 114         I40E_MEDIA_TYPE_BASET,
 115         I40E_MEDIA_TYPE_BACKPLANE,
 116         I40E_MEDIA_TYPE_CX4,
 117         I40E_MEDIA_TYPE_DA,
 118         I40E_MEDIA_TYPE_VIRTUAL
 119 };
 120
 121 enum i40e_fc_mode {
 122         I40E_FC_NONE = 0,
 123         I40E_FC_RX_PAUSE,
 124         I40E_FC_TX_PAUSE,
 125         I40E_FC_FULL,
 126         I40E_FC_PFC,
 127         I40E_FC_DEFAULT
 128 };
 129
 130 enum i40e_set_fc_aq_failures {
 131         I40E_SET_FC_AQ_FAIL_NONE = 0,
 132         I40E_SET_FC_AQ_FAIL_GET = 1,
 133         I40E_SET_FC_AQ_FAIL_SET = 2,
 134         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 135         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 136 };
 137
 138 enum i40e_vsi_type {
 139         I40E_VSI_MAIN   = 0,
 140         I40E_VSI_VMDQ1  = 1,
 141         I40E_VSI_VMDQ2  = 2,
 142         I40E_VSI_CTRL   = 3,
 143         I40E_VSI_FCOE   = 4,
 144         I40E_VSI_MIRROR = 5,
 145         I40E_VSI_SRIOV  = 6,
 146         I40E_VSI_FDIR   = 7,
 147         I40E_VSI_TYPE_UNKNOWN
 148 };
 149
 150 enum i40e_queue_type {
 151         I40E_QUEUE_TYPE_RX = 0,
 152         I40E_QUEUE_TYPE_TX,
 153         I40E_QUEUE_TYPE_PE_CEQ,
 154         I40E_QUEUE_TYPE_UNKNOWN
 155 };
 156
 157 struct i40e_link_status {
 158         enum i40e_aq_phy_type phy_type;
 159         enum i40e_aq_link_speed link_speed;
 160         u8 link_info;
 161         u8 an_info;
 162         u8 ext_info;
 163         u8 loopback;
 164         /* is Link Status Event notification to SW enabled */
 165         bool lse_enable;
 166         u16 max_frame_size;
 167         bool crc_enable;
 168         u8 pacing;
 169         u8 requested_speeds;
 170         u8 module_type[3];
 171         /* 1st byte: module identifier */
 172 #define I40E_MODULE_TYPE_SFP            0x03
 173 #define I40E_MODULE_TYPE_QSFP           0x0D
 174         /* 2nd byte: ethernet compliance codes for 10/40G */
 175 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 176 #define I40E_MODULE_TYPE_40G_LR4        0x02
 177 #define I40E_MODULE_TYPE_40G_SR4        0x04
 178 #define I40E_MODULE_TYPE_40G_CR4        0x08
 179 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 180 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 181 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 182 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 183         /* 3rd byte: ethernet compliance codes for 1G */
 184 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 185 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 186 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 187 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 188 };
 189
 190 enum i40e_aq_capabilities_phy_type {
 191         I40E_CAP_PHY_TYPE_SGMII           = BIT(I40E_PHY_TYPE_SGMII),
 192         I40E_CAP_PHY_TYPE_1000BASE_KX     = BIT(I40E_PHY_TYPE_1000BASE_KX),
 193         I40E_CAP_PHY_TYPE_10GBASE_KX4     = BIT(I40E_PHY_TYPE_10GBASE_KX4),
 194         I40E_CAP_PHY_TYPE_10GBASE_KR      = BIT(I40E_PHY_TYPE_10GBASE_KR),
 195         I40E_CAP_PHY_TYPE_40GBASE_KR4     = BIT(I40E_PHY_TYPE_40GBASE_KR4),
 196         I40E_CAP_PHY_TYPE_XAUI            = BIT(I40E_PHY_TYPE_XAUI),
 197         I40E_CAP_PHY_TYPE_XFI             = BIT(I40E_PHY_TYPE_XFI),
 198         I40E_CAP_PHY_TYPE_SFI             = BIT(I40E_PHY_TYPE_SFI),
 199         I40E_CAP_PHY_TYPE_XLAUI           = BIT(I40E_PHY_TYPE_XLAUI),
 200         I40E_CAP_PHY_TYPE_XLPPI           = BIT(I40E_PHY_TYPE_XLPPI),
 201         I40E_CAP_PHY_TYPE_40GBASE_CR4_CU  = BIT(I40E_PHY_TYPE_40GBASE_CR4_CU),
 202         I40E_CAP_PHY_TYPE_10GBASE_CR1_CU  = BIT(I40E_PHY_TYPE_10GBASE_CR1_CU),
 203         I40E_CAP_PHY_TYPE_10GBASE_AOC     = BIT(I40E_PHY_TYPE_10GBASE_AOC),
 204         I40E_CAP_PHY_TYPE_40GBASE_AOC     = BIT(I40E_PHY_TYPE_40GBASE_AOC),
 205         I40E_CAP_PHY_TYPE_100BASE_TX      = BIT(I40E_PHY_TYPE_100BASE_TX),
 206         I40E_CAP_PHY_TYPE_1000BASE_T      = BIT(I40E_PHY_TYPE_1000BASE_T),
 207         I40E_CAP_PHY_TYPE_10GBASE_T       = BIT(I40E_PHY_TYPE_10GBASE_T),
 208         I40E_CAP_PHY_TYPE_10GBASE_SR      = BIT(I40E_PHY_TYPE_10GBASE_SR),
 209         I40E_CAP_PHY_TYPE_10GBASE_LR      = BIT(I40E_PHY_TYPE_10GBASE_LR),
 210         I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU = BIT(I40E_PHY_TYPE_10GBASE_SFPP_CU),
 211         I40E_CAP_PHY_TYPE_10GBASE_CR1     = BIT(I40E_PHY_TYPE_10GBASE_CR1),
 212         I40E_CAP_PHY_TYPE_40GBASE_CR4     = BIT(I40E_PHY_TYPE_40GBASE_CR4),
 213         I40E_CAP_PHY_TYPE_40GBASE_SR4     = BIT(I40E_PHY_TYPE_40GBASE_SR4),
 214         I40E_CAP_PHY_TYPE_40GBASE_LR4     = BIT(I40E_PHY_TYPE_40GBASE_LR4),
 215         I40E_CAP_PHY_TYPE_1000BASE_SX     = BIT(I40E_PHY_TYPE_1000BASE_SX),
 216         I40E_CAP_PHY_TYPE_1000BASE_LX     = BIT(I40E_PHY_TYPE_1000BASE_LX),
 217         I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL =
 218                                          BIT(I40E_PHY_TYPE_1000BASE_T_OPTICAL),
 219         I40E_CAP_PHY_TYPE_20GBASE_KR2     = BIT(I40E_PHY_TYPE_20GBASE_KR2)
 220 };
 221
 222 struct i40e_phy_info {
 223         struct i40e_link_status link_info;
 224         struct i40e_link_status link_info_old;
 225         bool get_link_info;
 226         enum i40e_media_type media_type;
 227         /* all the phy types the NVM is capable of */
 228         enum i40e_aq_capabilities_phy_type phy_types;
 229 };
 230
 231 #define I40E_HW_CAP_MAX_GPIO                    30
 232 /* Capabilities of a PF or a VF or the whole device */
 233 struct i40e_hw_capabilities {
 234         u32  switch_mode;
 235 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 236 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 237 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 238
 239         u32  management_mode;
 240         u32  npar_enable;
 241         u32  os2bmc;
 242         u32  valid_functions;
 243         bool sr_iov_1_1;
 244         bool vmdq;
 245         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 246         bool evb_802_1_qbh; /* Bridge Port Extension */
 247         bool dcb;
 248         bool fcoe;
 249         bool iscsi; /* Indicates iSCSI enabled */
 250         bool flex10_enable;
 251         bool flex10_capable;
 252         u32  flex10_mode;
 253 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 254 #define I40E_FLEX10_MODE_DCC            0x1
 255 #define I40E_FLEX10_MODE_DCI            0x2
 256
 257         u32 flex10_status;
 258 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 259 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 260
 261         bool mgmt_cem;
 262         bool ieee_1588;
 263         bool iwarp;
 264         bool fd;
 265         u32 fd_filters_guaranteed;
 266         u32 fd_filters_best_effort;
 267         bool rss;
 268         u32 rss_table_size;
 269         u32 rss_table_entry_width;
 270         bool led[I40E_HW_CAP_MAX_GPIO];
 271         bool sdp[I40E_HW_CAP_MAX_GPIO];
 272         u32 nvm_image_type;
 273         u32 num_flow_director_filters;
 274         u32 num_vfs;
 275         u32 vf_base_id;
 276         u32 num_vsis;
 277         u32 num_rx_qp;
 278         u32 num_tx_qp;
 279         u32 base_queue;
 280         u32 num_msix_vectors;
 281         u32 num_msix_vectors_vf;
 282         u32 led_pin_num;
 283         u32 sdp_pin_num;
 284         u32 mdio_port_num;
 285         u32 mdio_port_mode;
 286         u8 rx_buf_chain_len;
 287         u32 enabled_tcmap;
 288         u32 maxtc;
 289         u64 wr_csr_prot;
 290 };
 291
 292 struct i40e_mac_info {
 293         enum i40e_mac_type type;
 294         u8 addr[ETH_ALEN];
 295         u8 perm_addr[ETH_ALEN];
 296         u8 san_addr[ETH_ALEN];
 297         u16 max_fcoeq;
 298 };
 299
 300 enum i40e_aq_resources_ids {
 301         I40E_NVM_RESOURCE_ID = 1
 302 };
 303
 304 enum i40e_aq_resource_access_type {
 305         I40E_RESOURCE_READ = 1,
 306         I40E_RESOURCE_WRITE
 307 };
 308
 309 struct i40e_nvm_info {
 310         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 311         u32 timeout;              /* [ms] */
 312         u16 sr_size;              /* Shadow RAM size in words */
 313         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 314         u16 version;              /* NVM package version */
 315         u32 eetrack;              /* NVM data version */
 316         u32 oem_ver;              /* OEM version info */
 317 };
 318
 319 /* definitions used in NVM update support */
 320
 321 enum i40e_nvmupd_cmd {
 322         I40E_NVMUPD_INVALID,
 323         I40E_NVMUPD_READ_CON,
 324         I40E_NVMUPD_READ_SNT,
 325         I40E_NVMUPD_READ_LCB,
 326         I40E_NVMUPD_READ_SA,
 327         I40E_NVMUPD_WRITE_ERA,
 328         I40E_NVMUPD_WRITE_CON,
 329         I40E_NVMUPD_WRITE_SNT,
 330         I40E_NVMUPD_WRITE_LCB,
 331         I40E_NVMUPD_WRITE_SA,
 332         I40E_NVMUPD_CSUM_CON,
 333         I40E_NVMUPD_CSUM_SA,
 334         I40E_NVMUPD_CSUM_LCB,
 335         I40E_NVMUPD_STATUS,
 336         I40E_NVMUPD_EXEC_AQ,
 337         I40E_NVMUPD_GET_AQ_RESULT,
 338 };
 339
 340 enum i40e_nvmupd_state {
 341         I40E_NVMUPD_STATE_INIT,
 342         I40E_NVMUPD_STATE_READING,
 343         I40E_NVMUPD_STATE_WRITING,
 344         I40E_NVMUPD_STATE_INIT_WAIT,
 345         I40E_NVMUPD_STATE_WRITE_WAIT,
 346 };
 347
 348 /* nvm_access definition and its masks/shifts need to be accessible to
 349  * application, core driver, and shared code.  Where is the right file?
 350  */
 351 #define I40E_NVM_READ   0xB
 352 #define I40E_NVM_WRITE  0xC
 353
 354 #define I40E_NVM_MOD_PNT_MASK 0xFF
 355
 356 #define I40E_NVM_TRANS_SHIFT    8
 357 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 358 #define I40E_NVM_CON            0x0
 359 #define I40E_NVM_SNT            0x1
 360 #define I40E_NVM_LCB            0x2
 361 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 362 #define I40E_NVM_ERA            0x4
 363 #define I40E_NVM_CSUM           0x8
 364 #define I40E_NVM_EXEC           0xf
 365
 366 #define I40E_NVM_ADAPT_SHIFT    16
 367 #define I40E_NVM_ADAPT_MASK     (0xffff << I40E_NVM_ADAPT_SHIFT)
 368
 369 #define I40E_NVMUPD_MAX_DATA    4096
 370 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 371
 372 struct i40e_nvm_access {
 373         u32 command;
 374         u32 config;
 375         u32 offset;     /* in bytes */
 376         u32 data_size;  /* in bytes */
 377         u8 data[1];
 378 };
 379
 380 /* PCI bus types */
 381 enum i40e_bus_type {
 382         i40e_bus_type_unknown = 0,
 383         i40e_bus_type_pci,
 384         i40e_bus_type_pcix,
 385         i40e_bus_type_pci_express,
 386         i40e_bus_type_reserved
 387 };
 388
 389 /* PCI bus speeds */
 390 enum i40e_bus_speed {
 391         i40e_bus_speed_unknown  = 0,
 392         i40e_bus_speed_33       = 33,
 393         i40e_bus_speed_66       = 66,
 394         i40e_bus_speed_100      = 100,
 395         i40e_bus_speed_120      = 120,
 396         i40e_bus_speed_133      = 133,
 397         i40e_bus_speed_2500     = 2500,
 398         i40e_bus_speed_5000     = 5000,
 399         i40e_bus_speed_8000     = 8000,
 400         i40e_bus_speed_reserved
 401 };
 402
 403 /* PCI bus widths */
 404 enum i40e_bus_width {
 405         i40e_bus_width_unknown  = 0,
 406         i40e_bus_width_pcie_x1  = 1,
 407         i40e_bus_width_pcie_x2  = 2,
 408         i40e_bus_width_pcie_x4  = 4,
 409         i40e_bus_width_pcie_x8  = 8,
 410         i40e_bus_width_32       = 32,
 411         i40e_bus_width_64       = 64,
 412         i40e_bus_width_reserved
 413 };
 414
 415 /* Bus parameters */
 416 struct i40e_bus_info {
 417         enum i40e_bus_speed speed;
 418         enum i40e_bus_width width;
 419         enum i40e_bus_type type;
 420
 421         u16 func;
 422         u16 device;
 423         u16 lan_id;
 424 };
 425
 426 /* Flow control (FC) parameters */
 427 struct i40e_fc_info {
 428         enum i40e_fc_mode current_mode; /* FC mode in effect */
 429         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 430 };
 431
 432 #define I40E_MAX_TRAFFIC_CLASS          8
 433 #define I40E_MAX_USER_PRIORITY          8
 434 #define I40E_DCBX_MAX_APPS              32
 435 #define I40E_LLDPDU_SIZE                1500
 436
 437 /* IEEE 802.1Qaz ETS Configuration data */
 438 struct i40e_ieee_ets_config {
 439         u8 willing;
 440         u8 cbs;
 441         u8 maxtcs;
 442         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 443         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 444         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 445 };
 446
 447 /* IEEE 802.1Qaz ETS Recommendation data */
 448 struct i40e_ieee_ets_recommend {
 449         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 450         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 451         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 452 };
 453
 454 /* IEEE 802.1Qaz PFC Configuration data */
 455 struct i40e_ieee_pfc_config {
 456         u8 willing;
 457         u8 mbc;
 458         u8 pfccap;
 459         u8 pfcenable;
 460 };
 461
 462 /* IEEE 802.1Qaz Application Priority data */
 463 struct i40e_ieee_app_priority_table {
 464         u8  priority;
 465         u8  selector;
 466         u16 protocolid;
 467 };
 468
 469 struct i40e_dcbx_config {
 470         u32 numapps;
 471         u32 tlv_status; /* CEE mode TLV status */
 472         struct i40e_ieee_ets_config etscfg;
 473         struct i40e_ieee_ets_recommend etsrec;
 474         struct i40e_ieee_pfc_config pfc;
 475         struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];
 476 };
 477
 478 /* Port hardware description */
 479 struct i40e_hw {
 480         u8 __iomem *hw_addr;
 481         void *back;
 482
 483         /* subsystem structs */
 484         struct i40e_phy_info phy;
 485         struct i40e_mac_info mac;
 486         struct i40e_bus_info bus;
 487         struct i40e_nvm_info nvm;
 488         struct i40e_fc_info fc;
 489
 490         /* pci info */
 491         u16 device_id;
 492         u16 vendor_id;
 493         u16 subsystem_device_id;
 494         u16 subsystem_vendor_id;
 495         u8 revision_id;
 496         u8 port;
 497         bool adapter_stopped;
 498
 499         /* capabilities for entire device and PCI func */
 500         struct i40e_hw_capabilities dev_caps;
 501         struct i40e_hw_capabilities func_caps;
 502
 503         /* Flow Director shared filter space */
 504         u16 fdir_shared_filter_count;
 505
 506         /* device profile info */
 507         u8  pf_id;
 508         u16 main_vsi_seid;
 509
 510         /* for multi-function MACs */
 511         u16 partition_id;
 512         u16 num_partitions;
 513         u16 num_ports;
 514
 515         /* Closest numa node to the device */
 516         u16 numa_node;
 517
 518         /* Admin Queue info */
 519         struct i40e_adminq_info aq;
 520
 521         /* state of nvm update process */
 522         enum i40e_nvmupd_state nvmupd_state;
 523         struct i40e_aq_desc nvm_wb_desc;
 524         struct i40e_virt_mem nvm_buff;
 525
 526         /* HMC info */
 527         struct i40e_hmc_info hmc; /* HMC info struct */
 528
 529         /* LLDP/DCBX Status */
 530         u16 dcbx_status;
 531
 532         /* DCBX info */
 533         struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 534         struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
 535         struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 536
 537         /* debug mask */
 538         u32 debug_mask;
 539         char err_str[16];
 540 };
 541
 542 static inline bool i40e_is_vf(struct i40e_hw *hw)
 543 {
 544         return (hw->mac.type == I40E_MAC_VF ||
 545                 hw->mac.type == I40E_MAC_X722_VF);
 546 }
 547
 548 struct i40e_driver_version {
 549         u8 major_version;
 550         u8 minor_version;
 551         u8 build_version;
 552         u8 subbuild_version;
 553         u8 driver_string[32];
 554 };
 555
 556 /* RX Descriptors */
 557 union i40e_16byte_rx_desc {
 558         struct {
 559                 __le64 pkt_addr; /* Packet buffer address */
 560                 __le64 hdr_addr; /* Header buffer address */
 561         } read;
 562         struct {
 563                 struct {
 564                         struct {
 565                                 union {
 566                                         __le16 mirroring_status;
 567                                         __le16 fcoe_ctx_id;
 568                                 } mirr_fcoe;
 569                                 __le16 l2tag1;
 570                         } lo_dword;
 571                         union {
 572                                 __le32 rss; /* RSS Hash */
 573                                 __le32 fd_id; /* Flow director filter id */
 574                                 __le32 fcoe_param; /* FCoE DDP Context id */
 575                         } hi_dword;
 576                 } qword0;
 577                 struct {
 578                         /* ext status/error/pktype/length */
 579                         __le64 status_error_len;
 580                 } qword1;
 581         } wb;  /* writeback */
 582 };
 583
 584 union i40e_32byte_rx_desc {
 585         struct {
 586                 __le64  pkt_addr; /* Packet buffer address */
 587                 __le64  hdr_addr; /* Header buffer address */
 588                         /* bit 0 of hdr_buffer_addr is DD bit */
 589                 __le64  rsvd1;
 590                 __le64  rsvd2;
 591         } read;
 592         struct {
 593                 struct {
 594                         struct {
 595                                 union {
 596                                         __le16 mirroring_status;
 597                                         __le16 fcoe_ctx_id;
 598                                 } mirr_fcoe;
 599                                 __le16 l2tag1;
 600                         } lo_dword;
 601                         union {
 602                                 __le32 rss; /* RSS Hash */
 603                                 __le32 fcoe_param; /* FCoE DDP Context id */
 604                                 /* Flow director filter id in case of
 605                                  * Programming status desc WB
 606                                  */
 607                                 __le32 fd_id;
 608                         } hi_dword;
 609                 } qword0;
 610                 struct {
 611                         /* status/error/pktype/length */
 612                         __le64 status_error_len;
 613                 } qword1;
 614                 struct {
 615                         __le16 ext_status; /* extended status */
 616                         __le16 rsvd;
 617                         __le16 l2tag2_1;
 618                         __le16 l2tag2_2;
 619                 } qword2;
 620                 struct {
 621                         union {
 622                                 __le32 flex_bytes_lo;
 623                                 __le32 pe_status;
 624                         } lo_dword;
 625                         union {
 626                                 __le32 flex_bytes_hi;
 627                                 __le32 fd_id;
 628                         } hi_dword;
 629                 } qword3;
 630         } wb;  /* writeback */
 631 };
 632
 633 enum i40e_rx_desc_status_bits {
 634         /* Note: These are predefined bit offsets */
 635         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 636         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 637         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 638         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 639         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 640         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 641         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 642         /* Note: Bit 8 is reserved in X710 and XL710 */
 643         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 644         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 645         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 646         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 647         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 648         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 649         I40E_RX_DESC_STATUS_RESERVED_SHIFT      = 16, /* 2 BITS */
 650         /* Note: For non-tunnel packets INT_UDP_0 is the right status for
 651          * UDP header
 652          */
 653         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 654         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 655 };
 656
 657 #define I40E_RXD_QW1_STATUS_SHIFT       0
 658 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
 659                                          << I40E_RXD_QW1_STATUS_SHIFT)
 660
 661 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 662 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 663                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 664
 665 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 666 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
 667                                     BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 668
 669 enum i40e_rx_desc_fltstat_values {
 670         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 671         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 672         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 673         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 674 };
 675
 676 #define I40E_RXD_QW1_ERROR_SHIFT        19
 677 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 678
 679 enum i40e_rx_desc_error_bits {
 680         /* Note: These are predefined bit offsets */
 681         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 682         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 683         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 684         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 685         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 686         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 687         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 688         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 689         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 690 };
 691
 692 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 693         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 694         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 695         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 696         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 697         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 698 };
 699
 700 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 701 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 702
 703 /* Packet type non-ip values */
 704 enum i40e_rx_l2_ptype {
 705         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 706         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 707         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 708         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 709         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 710         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 711         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 712         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 713         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 714         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 715         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 716         I40E_RX_PTYPE_L2_ARP                            = 11,
 717         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 718         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 719         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 720         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 721         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 722         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 723         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 724         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 725         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 726         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 727         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 728         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 729         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 730         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 731 };
 732
 733 struct i40e_rx_ptype_decoded {
 734         u32 ptype:8;
 735         u32 known:1;
 736         u32 outer_ip:1;
 737         u32 outer_ip_ver:1;
 738         u32 outer_frag:1;
 739         u32 tunnel_type:3;
 740         u32 tunnel_end_prot:2;
 741         u32 tunnel_end_frag:1;
 742         u32 inner_prot:4;
 743         u32 payload_layer:3;
 744 };
 745
 746 enum i40e_rx_ptype_outer_ip {
 747         I40E_RX_PTYPE_OUTER_L2  = 0,
 748         I40E_RX_PTYPE_OUTER_IP  = 1
 749 };
 750
 751 enum i40e_rx_ptype_outer_ip_ver {
 752         I40E_RX_PTYPE_OUTER_NONE        = 0,
 753         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 754         I40E_RX_PTYPE_OUTER_IPV6        = 1
 755 };
 756
 757 enum i40e_rx_ptype_outer_fragmented {
 758         I40E_RX_PTYPE_NOT_FRAG  = 0,
 759         I40E_RX_PTYPE_FRAG      = 1
 760 };
 761
 762 enum i40e_rx_ptype_tunnel_type {
 763         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 764         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 765         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 766         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 767         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 768 };
 769
 770 enum i40e_rx_ptype_tunnel_end_prot {
 771         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 772         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 773         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 774 };
 775
 776 enum i40e_rx_ptype_inner_prot {
 777         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 778         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 779         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 780         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 781         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 782         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 783 };
 784
 785 enum i40e_rx_ptype_payload_layer {
 786         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 787         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 788         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 789         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 790 };
 791
 792 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 793 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 794                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 795
 796 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 797 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 798                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 799
 800 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 801 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 802
 803 enum i40e_rx_desc_ext_status_bits {
 804         /* Note: These are predefined bit offsets */
 805         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 806         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 807         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 808         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 809         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 810         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 811         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 812 };
 813
 814 enum i40e_rx_desc_pe_status_bits {
 815         /* Note: These are predefined bit offsets */
 816         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 817         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 818         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 819         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 820         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 821         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 822         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 823         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 824         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 825 };
 826
 827 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 828 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 829
 830 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 831 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 832                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 833
 834 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 835 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 836                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 837
 838 enum i40e_rx_prog_status_desc_status_bits {
 839         /* Note: These are predefined bit offsets */
 840         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 841         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 842 };
 843
 844 enum i40e_rx_prog_status_desc_prog_id_masks {
 845         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 846         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 847         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 848 };
 849
 850 enum i40e_rx_prog_status_desc_error_bits {
 851         /* Note: These are predefined bit offsets */
 852         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 853         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
 854         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 855         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 856 };
 857
 858 /* TX Descriptor */
 859 struct i40e_tx_desc {
 860         __le64 buffer_addr; /* Address of descriptor's data buf */
 861         __le64 cmd_type_offset_bsz;
 862 };
 863
 864 #define I40E_TXD_QW1_DTYPE_SHIFT        0
 865 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
 866
 867 enum i40e_tx_desc_dtype_value {
 868         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 869         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 870         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 871         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 872         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 873         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 874         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 875         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 876         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 877         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
 878 };
 879
 880 #define I40E_TXD_QW1_CMD_SHIFT  4
 881 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
 882
 883 enum i40e_tx_desc_cmd_bits {
 884         I40E_TX_DESC_CMD_EOP                    = 0x0001,
 885         I40E_TX_DESC_CMD_RS                     = 0x0002,
 886         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
 887         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
 888         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
 889         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 890         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 891         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 892         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 893         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
 894         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 895         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 896         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
 897         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
 898         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
 899         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
 900         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
 901         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
 902 };
 903
 904 #define I40E_TXD_QW1_OFFSET_SHIFT       16
 905 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
 906                                          I40E_TXD_QW1_OFFSET_SHIFT)
 907
 908 enum i40e_tx_desc_length_fields {
 909         /* Note: These are predefined bit offsets */
 910         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
 911         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
 912         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
 913 };
 914
 915 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
 916 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
 917                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
 918
 919 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
 920 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
 921
 922 /* Context descriptors */
 923 struct i40e_tx_context_desc {
 924         __le32 tunneling_params;
 925         __le16 l2tag2;
 926         __le16 rsvd;
 927         __le64 type_cmd_tso_mss;
 928 };
 929
 930 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
 931 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
 932
 933 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
 934 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
 935
 936 enum i40e_tx_ctx_desc_cmd_bits {
 937         I40E_TX_CTX_DESC_TSO            = 0x01,
 938         I40E_TX_CTX_DESC_TSYN           = 0x02,
 939         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
 940         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
 941         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
 942         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
 943         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
 944         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
 945         I40E_TX_CTX_DESC_SWPE           = 0x40
 946 };
 947
 948 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
 949 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
 950                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
 951
 952 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
 953 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
 954                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
 955
 956 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
 957 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
 958
 959 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
 960 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
 961                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
 962
 963 enum i40e_tx_ctx_desc_eipt_offload {
 964         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
 965         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
 966         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
 967         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
 968 };
 969
 970 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
 971 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
 972                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
 973
 974 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
 975 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 976
 977 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
 978 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 979
 980 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
 981 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
 982                                        BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
 983
 984 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
 985
 986 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
 987 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
 988                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
 989
 990 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
 991 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
 992                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
 993
 994 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
 995 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
 996 struct i40e_filter_program_desc {
 997         __le32 qindex_flex_ptype_vsi;
 998         __le32 rsvd;
 999         __le32 dtype_cmd_cntindex;
1000         __le32 fd_id;
1001 };
1002 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1003 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1004                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1005 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1006 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1007                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1008 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1009 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1010                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1011
1012 /* Packet Classifier Types for filters */
1013 enum i40e_filter_pctype {
1014         /* Note: Values 0-28 are reserved for future use.
1015          * Value 29, 30, 32 are not supported on XL710 and X710.
1016          */
1017         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1018         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1019         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1020         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1021         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1022         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1023         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1024         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1025         /* Note: Values 37-38 are reserved for future use.
1026          * Value 39, 40, 42 are not supported on XL710 and X710.
1027          */
1028         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1029         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1030         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1031         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1032         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1033         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1034         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1035         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1036         /* Note: Value 47 is reserved for future use */
1037         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1038         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1039         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1040         /* Note: Values 51-62 are reserved for future use */
1041         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1042 };
1043
1044 enum i40e_filter_program_desc_dest {
1045         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1046         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1047         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1048 };
1049
1050 enum i40e_filter_program_desc_fd_status {
1051         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1052         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1053         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1054         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1055 };
1056
1057 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1058 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1059                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1060
1061 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1062 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1063                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1064
1065 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1066 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1067
1068 enum i40e_filter_program_desc_pcmd {
1069         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1070         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1071 };
1072
1073 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1074 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1075
1076 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1077 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1078
1079 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1080                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1081 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1082                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1083
1084 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1085 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1086                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1087
1088 enum i40e_filter_type {
1089         I40E_FLOW_DIRECTOR_FLTR = 0,
1090         I40E_PE_QUAD_HASH_FLTR = 1,
1091         I40E_ETHERTYPE_FLTR,
1092         I40E_FCOE_CTX_FLTR,
1093         I40E_MAC_VLAN_FLTR,
1094         I40E_HASH_FLTR
1095 };
1096
1097 struct i40e_vsi_context {
1098         u16 seid;
1099         u16 uplink_seid;
1100         u16 vsi_number;
1101         u16 vsis_allocated;
1102         u16 vsis_unallocated;
1103         u16 flags;
1104         u8 pf_num;
1105         u8 vf_num;
1106         u8 connection_type;
1107         struct i40e_aqc_vsi_properties_data info;
1108 };
1109
1110 struct i40e_veb_context {
1111         u16 seid;
1112         u16 uplink_seid;
1113         u16 veb_number;
1114         u16 vebs_allocated;
1115         u16 vebs_unallocated;
1116         u16 flags;
1117         struct i40e_aqc_get_veb_parameters_completion info;
1118 };
1119
1120 /* Statistics collected by each port, VSI, VEB, and S-channel */
1121 struct i40e_eth_stats {
1122         u64 rx_bytes;                   /* gorc */
1123         u64 rx_unicast;                 /* uprc */
1124         u64 rx_multicast;               /* mprc */
1125         u64 rx_broadcast;               /* bprc */
1126         u64 rx_discards;                /* rdpc */
1127         u64 rx_unknown_protocol;        /* rupp */
1128         u64 tx_bytes;                   /* gotc */
1129         u64 tx_unicast;                 /* uptc */
1130         u64 tx_multicast;               /* mptc */
1131         u64 tx_broadcast;               /* bptc */
1132         u64 tx_discards;                /* tdpc */
1133         u64 tx_errors;                  /* tepc */
1134 };
1135
1136 /* Statistics collected per VEB per TC */
1137 struct i40e_veb_tc_stats {
1138         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1139         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1140         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1141         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1142 };
1143
1144 /* Statistics collected by the MAC */
1145 struct i40e_hw_port_stats {
1146         /* eth stats collected by the port */
1147         struct i40e_eth_stats eth;
1148
1149         /* additional port specific stats */
1150         u64 tx_dropped_link_down;       /* tdold */
1151         u64 crc_errors;                 /* crcerrs */
1152         u64 illegal_bytes;              /* illerrc */
1153         u64 error_bytes;                /* errbc */
1154         u64 mac_local_faults;           /* mlfc */
1155         u64 mac_remote_faults;          /* mrfc */
1156         u64 rx_length_errors;           /* rlec */
1157         u64 link_xon_rx;                /* lxonrxc */
1158         u64 link_xoff_rx;               /* lxoffrxc */
1159         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1160         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1161         u64 link_xon_tx;                /* lxontxc */
1162         u64 link_xoff_tx;               /* lxofftxc */
1163         u64 priority_xon_tx[8];         /* pxontxc[8] */
1164         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1165         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1166         u64 rx_size_64;                 /* prc64 */
1167         u64 rx_size_127;                /* prc127 */
1168         u64 rx_size_255;                /* prc255 */
1169         u64 rx_size_511;                /* prc511 */
1170         u64 rx_size_1023;               /* prc1023 */
1171         u64 rx_size_1522;               /* prc1522 */
1172         u64 rx_size_big;                /* prc9522 */
1173         u64 rx_undersize;               /* ruc */
1174         u64 rx_fragments;               /* rfc */
1175         u64 rx_oversize;                /* roc */
1176         u64 rx_jabber;                  /* rjc */
1177         u64 tx_size_64;                 /* ptc64 */
1178         u64 tx_size_127;                /* ptc127 */
1179         u64 tx_size_255;                /* ptc255 */
1180         u64 tx_size_511;                /* ptc511 */
1181         u64 tx_size_1023;               /* ptc1023 */
1182         u64 tx_size_1522;               /* ptc1522 */
1183         u64 tx_size_big;                /* ptc9522 */
1184         u64 mac_short_packet_dropped;   /* mspdc */
1185         u64 checksum_error;             /* xec */
1186         /* flow director stats */
1187         u64 fd_atr_match;
1188         u64 fd_sb_match;
1189         u64 fd_atr_tunnel_match;
1190         u32 fd_atr_status;
1191         u32 fd_sb_status;
1192         /* EEE LPI */
1193         u32 tx_lpi_status;
1194         u32 rx_lpi_status;
1195         u64 tx_lpi_count;               /* etlpic */
1196         u64 rx_lpi_count;               /* erlpic */
1197 };
1198
1199 /* Checksum and Shadow RAM pointers */
1200 #define I40E_SR_NVM_CONTROL_WORD                0x00
1201 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1202 #define I40E_NVM_OEM_VER_OFF                    0x83
1203 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1204 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1205 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1206 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1207 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1208 #define I40E_SR_VPD_PTR                         0x2F
1209 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1210 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1211
1212 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1213 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1214 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1215 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1216 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1217
1218 /* Shadow RAM related */
1219 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1220 #define I40E_SR_WORDS_IN_1KB            512
1221 /* Checksum should be calculated such that after adding all the words,
1222  * including the checksum word itself, the sum should be 0xBABA.
1223  */
1224 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1225
1226 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1227
1228 enum i40e_switch_element_types {
1229         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1230         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1231         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1232         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1233         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1234         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1235         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1236         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1237         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1238 };
1239
1240 /* Supported EtherType filters */
1241 enum i40e_ether_type_index {
1242         I40E_ETHER_TYPE_1588            = 0,
1243         I40E_ETHER_TYPE_FIP             = 1,
1244         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1245         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1246         I40E_ETHER_TYPE_LLDP            = 4,
1247         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1248         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1249         I40E_ETHER_TYPE_QCN_CNM         = 7,
1250         I40E_ETHER_TYPE_8021X           = 8,
1251         I40E_ETHER_TYPE_ARP             = 9,
1252         I40E_ETHER_TYPE_RSV1            = 10,
1253         I40E_ETHER_TYPE_RSV2            = 11,
1254 };
1255
1256 /* Filter context base size is 1K */
1257 #define I40E_HASH_FILTER_BASE_SIZE      1024
1258 /* Supported Hash filter values */
1259 enum i40e_hash_filter_size {
1260         I40E_HASH_FILTER_SIZE_1K        = 0,
1261         I40E_HASH_FILTER_SIZE_2K        = 1,
1262         I40E_HASH_FILTER_SIZE_4K        = 2,
1263         I40E_HASH_FILTER_SIZE_8K        = 3,
1264         I40E_HASH_FILTER_SIZE_16K       = 4,
1265         I40E_HASH_FILTER_SIZE_32K       = 5,
1266         I40E_HASH_FILTER_SIZE_64K       = 6,
1267         I40E_HASH_FILTER_SIZE_128K      = 7,
1268         I40E_HASH_FILTER_SIZE_256K      = 8,
1269         I40E_HASH_FILTER_SIZE_512K      = 9,
1270         I40E_HASH_FILTER_SIZE_1M        = 10,
1271 };
1272
1273 /* DMA context base size is 0.5K */
1274 #define I40E_DMA_CNTX_BASE_SIZE         512
1275 /* Supported DMA context values */
1276 enum i40e_dma_cntx_size {
1277         I40E_DMA_CNTX_SIZE_512          = 0,
1278         I40E_DMA_CNTX_SIZE_1K           = 1,
1279         I40E_DMA_CNTX_SIZE_2K           = 2,
1280         I40E_DMA_CNTX_SIZE_4K           = 3,
1281         I40E_DMA_CNTX_SIZE_8K           = 4,
1282         I40E_DMA_CNTX_SIZE_16K          = 5,
1283         I40E_DMA_CNTX_SIZE_32K          = 6,
1284         I40E_DMA_CNTX_SIZE_64K          = 7,
1285         I40E_DMA_CNTX_SIZE_128K         = 8,
1286         I40E_DMA_CNTX_SIZE_256K         = 9,
1287 };
1288
1289 /* Supported Hash look up table (LUT) sizes */
1290 enum i40e_hash_lut_size {
1291         I40E_HASH_LUT_SIZE_128          = 0,
1292         I40E_HASH_LUT_SIZE_512          = 1,
1293 };
1294
1295 /* Structure to hold a per PF filter control settings */
1296 struct i40e_filter_control_settings {
1297         /* number of PE Quad Hash filter buckets */
1298         enum i40e_hash_filter_size pe_filt_num;
1299         /* number of PE Quad Hash contexts */
1300         enum i40e_dma_cntx_size pe_cntx_num;
1301         /* number of FCoE filter buckets */
1302         enum i40e_hash_filter_size fcoe_filt_num;
1303         /* number of FCoE DDP contexts */
1304         enum i40e_dma_cntx_size fcoe_cntx_num;
1305         /* size of the Hash LUT */
1306         enum i40e_hash_lut_size hash_lut_size;
1307         /* enable FDIR filters for PF and its VFs */
1308         bool enable_fdir;
1309         /* enable Ethertype filters for PF and its VFs */
1310         bool enable_ethtype;
1311         /* enable MAC/VLAN filters for PF and its VFs */
1312         bool enable_macvlan;
1313 };
1314
1315 /* Structure to hold device level control filter counts */
1316 struct i40e_control_filter_stats {
1317         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1318         u16 etype_used;       /* Used perfect EtherType filters */
1319         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1320         u16 etype_free;       /* Un-used perfect EtherType filters */
1321 };
1322
1323 enum i40e_reset_type {
1324         I40E_RESET_POR          = 0,
1325         I40E_RESET_CORER        = 1,
1326         I40E_RESET_GLOBR        = 2,
1327         I40E_RESET_EMPR         = 3,
1328 };
1329
1330 /* RSS Hash Table Size */
1331 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1332 #endif /* _I40E_TYPE_H_ */