drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

   1 /*******************************************************************************
   2  *
   3  *  Intel 10 Gigabit PCI Express Linux driver
   4  *  Copyright(c) 1999 - 2015 Intel Corporation.
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms and conditions of the GNU General Public License,
   8  *  version 2, as published by the Free Software Foundation.
   9  *
  10  *  This program is distributed in the hope it will be useful, but WITHOUT
  11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  *  more details.
  14  *
  15  *  The full GNU General Public License is included in this distribution in
  16  *  the file called "COPYING".
  17  *
  18  *  Contact Information:
  19  *  Linux NICS <linux.nics@intel.com>
  20  *  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  21  *  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  22  *
  23  ******************************************************************************/
  24 #include "ixgbe_x540.h"
  25 #include "ixgbe_type.h"
  26 #include "ixgbe_common.h"
  27 #include "ixgbe_phy.h"
  28
  29 static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw)
  30 {
  31         struct ixgbe_mac_info *mac = &hw->mac;
  32         struct ixgbe_phy_info *phy = &hw->phy;
  33
  34         /* Start with X540 invariants, since so simular */
  35         ixgbe_get_invariants_X540(hw);
  36
  37         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
  38                 phy->ops.set_phy_power = NULL;
  39
  40         return 0;
  41 }
  42
  43 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
  44  *  @hw: pointer to hardware structure
  45  **/
  46 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
  47 {
  48         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
  49
  50         if (hw->bus.lan_id) {
  51                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
  52                 esdp |= IXGBE_ESDP_SDP1_DIR;
  53         }
  54         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
  55         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
  56         IXGBE_WRITE_FLUSH(hw);
  57 }
  58
  59 /**
  60  * ixgbe_read_cs4227 - Read CS4227 register
  61  * @hw: pointer to hardware structure
  62  * @reg: register number to write
  63  * @value: pointer to receive value read
  64  *
  65  * Returns status code
  66  */
  67 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  68 {
  69         return hw->phy.ops.read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg,
  70                                                       value);
  71 }
  72
  73 /**
  74  * ixgbe_write_cs4227 - Write CS4227 register
  75  * @hw: pointer to hardware structure
  76  * @reg: register number to write
  77  * @value: value to write to register
  78  *
  79  * Returns status code
  80  */
  81 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
  82 {
  83         return hw->phy.ops.write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg,
  84                                                        value);
  85 }
  86
  87 /**
  88  * ixgbe_check_cs4227_reg - Perform diag on a CS4227 register
  89  * @hw: pointer to hardware structure
  90  * @reg: the register to check
  91  *
  92  * Performs a diagnostic on a register in the CS4227 chip. Returns an error
  93  * if it is not operating correctly.
  94  * This function assumes that the caller has acquired the proper semaphore.
  95  */
  96 static s32 ixgbe_check_cs4227_reg(struct ixgbe_hw *hw, u16 reg)
  97 {
  98         s32 status;
  99         u32 retry;
 100         u16 reg_val;
 101
 102         reg_val = (IXGBE_CS4227_EDC_MODE_DIAG << 1) | 1;
 103         status = ixgbe_write_cs4227(hw, reg, reg_val);
 104         if (status)
 105                 return status;
 106         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 107                 msleep(IXGBE_CS4227_CHECK_DELAY);
 108                 reg_val = 0xFFFF;
 109                 ixgbe_read_cs4227(hw, reg, &reg_val);
 110                 if (!reg_val)
 111                         break;
 112         }
 113         if (reg_val) {
 114                 hw_err(hw, "CS4227 reg 0x%04X failed diagnostic\n", reg);
 115                 return status;
 116         }
 117
 118         return 0;
 119 }
 120
 121 /**
 122  * ixgbe_get_cs4227_status - Return CS4227 status
 123  * @hw: pointer to hardware structure
 124  *
 125  * Performs a diagnostic on the CS4227 chip. Returns an error if it is
 126  * not operating correctly.
 127  * This function assumes that the caller has acquired the proper semaphore.
 128  */
 129 static s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
 130 {
 131         s32 status;
 132         u16 value = 0;
 133
 134         /* Exit if the diagnostic has already been performed. */
 135         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 136         if (status)
 137                 return status;
 138         if (value == IXGBE_CS4227_RESET_COMPLETE)
 139                 return 0;
 140
 141         /* Check port 0. */
 142         status = ixgbe_check_cs4227_reg(hw, IXGBE_CS4227_LINE_SPARE24_LSB);
 143         if (status)
 144                 return status;
 145
 146         status = ixgbe_check_cs4227_reg(hw, IXGBE_CS4227_HOST_SPARE24_LSB);
 147         if (status)
 148                 return status;
 149
 150         /* Check port 1. */
 151         status = ixgbe_check_cs4227_reg(hw, IXGBE_CS4227_LINE_SPARE24_LSB +
 152                                         (1 << 12));
 153         if (status)
 154                 return status;
 155
 156         return ixgbe_check_cs4227_reg(hw, IXGBE_CS4227_HOST_SPARE24_LSB +
 157                                       (1 << 12));
 158 }
 159
 160 /**
 161  * ixgbe_read_pe - Read register from port expander
 162  * @hw: pointer to hardware structure
 163  * @reg: register number to read
 164  * @value: pointer to receive read value
 165  *
 166  * Returns status code
 167  */
 168 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 169 {
 170         s32 status;
 171
 172         status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value);
 173         if (status)
 174                 hw_err(hw, "port expander access failed with %d\n", status);
 175         return status;
 176 }
 177
 178 /**
 179  * ixgbe_write_pe - Write register to port expander
 180  * @hw: pointer to hardware structure
 181  * @reg: register number to write
 182  * @value: value to write
 183  *
 184  * Returns status code
 185  */
 186 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 187 {
 188         s32 status;
 189
 190         status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE,
 191                                                        value);
 192         if (status)
 193                 hw_err(hw, "port expander access failed with %d\n", status);
 194         return status;
 195 }
 196
 197 /**
 198  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 199  * @hw: pointer to hardware structure
 200  *
 201  * This function assumes that the caller has acquired the proper semaphore.
 202  * Returns error code
 203  */
 204 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 205 {
 206         s32 status;
 207         u32 retry;
 208         u16 value;
 209         u8 reg;
 210
 211         /* Trigger hard reset. */
 212         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 213         if (status)
 214                 return status;
 215         reg |= IXGBE_PE_BIT1;
 216         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 217         if (status)
 218                 return status;
 219
 220         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 221         if (status)
 222                 return status;
 223         reg &= ~IXGBE_PE_BIT1;
 224         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 225         if (status)
 226                 return status;
 227
 228         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 229         if (status)
 230                 return status;
 231         reg &= ~IXGBE_PE_BIT1;
 232         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 233         if (status)
 234                 return status;
 235
 236         usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100);
 237
 238         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 239         if (status)
 240                 return status;
 241         reg |= IXGBE_PE_BIT1;
 242         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 243         if (status)
 244                 return status;
 245
 246         /* Wait for the reset to complete. */
 247         msleep(IXGBE_CS4227_RESET_DELAY);
 248         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 249                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 250                                            &value);
 251                 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK)
 252                         break;
 253                 msleep(IXGBE_CS4227_CHECK_DELAY);
 254         }
 255         if (retry == IXGBE_CS4227_RETRIES) {
 256                 hw_err(hw, "CS4227 reset did not complete\n");
 257                 return IXGBE_ERR_PHY;
 258         }
 259
 260         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 261         if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 262                 hw_err(hw, "CS4227 EEPROM did not load successfully\n");
 263                 return IXGBE_ERR_PHY;
 264         }
 265
 266         return 0;
 267 }
 268
 269 /**
 270  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 271  * @hw: pointer to hardware structure
 272  */
 273 static void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 274 {
 275         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 276         s32 status;
 277         u16 value;
 278         u8 retry;
 279
 280         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 281                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 282                 if (status) {
 283                         hw_err(hw, "semaphore failed with %d\n", status);
 284                         msleep(IXGBE_CS4227_CHECK_DELAY);
 285                         continue;
 286                 }
 287
 288                 /* Get status of reset flow. */
 289                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 290                 if (!status && value == IXGBE_CS4227_RESET_COMPLETE)
 291                         goto out;
 292
 293                 if (status || value != IXGBE_CS4227_RESET_PENDING)
 294                         break;
 295
 296                 /* Reset is pending. Wait and check again. */
 297                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 298                 msleep(IXGBE_CS4227_CHECK_DELAY);
 299         }
 300         /* If still pending, assume other instance failed. */
 301         if (retry == IXGBE_CS4227_RETRIES) {
 302                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 303                 if (status) {
 304                         hw_err(hw, "semaphore failed with %d\n", status);
 305                         return;
 306                 }
 307         }
 308
 309         /* Reset the CS4227. */
 310         status = ixgbe_reset_cs4227(hw);
 311         if (status) {
 312                 hw_err(hw, "CS4227 reset failed: %d", status);
 313                 goto out;
 314         }
 315
 316         /* Reset takes so long, temporarily release semaphore in case the
 317          * other driver instance is waiting for the reset indication.
 318          */
 319         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 320                            IXGBE_CS4227_RESET_PENDING);
 321         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 322         usleep_range(10000, 12000);
 323         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 324         if (status) {
 325                 hw_err(hw, "semaphore failed with %d", status);
 326                 return;
 327         }
 328
 329         /* Is the CS4227 working correctly? */
 330         status = ixgbe_get_cs4227_status(hw);
 331         if (status) {
 332                 hw_err(hw, "CS4227 status failed: %d", status);
 333                 goto out;
 334         }
 335
 336         /* Record completion for next time. */
 337         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 338                                     IXGBE_CS4227_RESET_COMPLETE);
 339
 340 out:
 341         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 342         msleep(hw->eeprom.semaphore_delay);
 343 }
 344
 345 /** ixgbe_identify_phy_x550em - Get PHY type based on device id
 346  *  @hw: pointer to hardware structure
 347  *
 348  *  Returns error code
 349  */
 350 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 351 {
 352         switch (hw->device_id) {
 353         case IXGBE_DEV_ID_X550EM_X_SFP:
 354                 /* set up for CS4227 usage */
 355                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 356                 ixgbe_setup_mux_ctl(hw);
 357                 ixgbe_check_cs4227(hw);
 358                 return ixgbe_identify_module_generic(hw);
 359         case IXGBE_DEV_ID_X550EM_X_KX4:
 360                 hw->phy.type = ixgbe_phy_x550em_kx4;
 361                 break;
 362         case IXGBE_DEV_ID_X550EM_X_KR:
 363                 hw->phy.type = ixgbe_phy_x550em_kr;
 364                 break;
 365         case IXGBE_DEV_ID_X550EM_X_1G_T:
 366         case IXGBE_DEV_ID_X550EM_X_10G_T:
 367                 return ixgbe_identify_phy_generic(hw);
 368         default:
 369                 break;
 370         }
 371         return 0;
 372 }
 373
 374 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 375                                      u32 device_type, u16 *phy_data)
 376 {
 377         return IXGBE_NOT_IMPLEMENTED;
 378 }
 379
 380 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 381                                       u32 device_type, u16 phy_data)
 382 {
 383         return IXGBE_NOT_IMPLEMENTED;
 384 }
 385
 386 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 387  *  @hw: pointer to hardware structure
 388  *
 389  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 390  *  ixgbe_hw struct in order to set up EEPROM access.
 391  **/
 392 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 393 {
 394         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 395         u32 eec;
 396         u16 eeprom_size;
 397
 398         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 399                 eeprom->semaphore_delay = 10;
 400                 eeprom->type = ixgbe_flash;
 401
 402                 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
 403                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 404                                     IXGBE_EEC_SIZE_SHIFT);
 405                 eeprom->word_size = 1 << (eeprom_size +
 406                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 407
 408                 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
 409                        eeprom->type, eeprom->word_size);
 410         }
 411
 412         return 0;
 413 }
 414
 415 /**
 416  * ixgbe_iosf_wait - Wait for IOSF command completion
 417  * @hw: pointer to hardware structure
 418  * @ctrl: pointer to location to receive final IOSF control value
 419  *
 420  * Return: failing status on timeout
 421  *
 422  * Note: ctrl can be NULL if the IOSF control register value is not needed
 423  */
 424 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 425 {
 426         u32 i, command;
 427
 428         /* Check every 10 usec to see if the address cycle completed.
 429          * The SB IOSF BUSY bit will clear when the operation is
 430          * complete.
 431          */
 432         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 433                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 434                 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY))
 435                         break;
 436                 usleep_range(10, 20);
 437         }
 438         if (ctrl)
 439                 *ctrl = command;
 440         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 441                 hw_dbg(hw, "IOSF wait timed out\n");
 442                 return IXGBE_ERR_PHY;
 443         }
 444
 445         return 0;
 446 }
 447
 448 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the
 449  *  IOSF device
 450  *  @hw: pointer to hardware structure
 451  *  @reg_addr: 32 bit PHY register to write
 452  *  @device_type: 3 bit device type
 453  *  @phy_data: Pointer to read data from the register
 454  **/
 455 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 456                                        u32 device_type, u32 *data)
 457 {
 458         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 459         u32 command, error;
 460         s32 ret;
 461
 462         ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
 463         if (ret)
 464                 return ret;
 465
 466         ret = ixgbe_iosf_wait(hw, NULL);
 467         if (ret)
 468                 goto out;
 469
 470         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 471                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 472
 473         /* Write IOSF control register */
 474         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 475
 476         ret = ixgbe_iosf_wait(hw, &command);
 477
 478         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 479                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 480                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 481                 hw_dbg(hw, "Failed to read, error %x\n", error);
 482                 return IXGBE_ERR_PHY;
 483         }
 484
 485         if (!ret)
 486                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 487
 488 out:
 489         hw->mac.ops.release_swfw_sync(hw, gssr);
 490         return ret;
 491 }
 492
 493 /** ixgbe_read_ee_hostif_data_X550 - Read EEPROM word using a host interface
 494  *  command assuming that the semaphore is already obtained.
 495  *  @hw: pointer to hardware structure
 496  *  @offset: offset of  word in the EEPROM to read
 497  *  @data: word read from the EEPROM
 498  *
 499  *  Reads a 16 bit word from the EEPROM using the hostif.
 500  **/
 501 static s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
 502                                           u16 *data)
 503 {
 504         s32 status;
 505         struct ixgbe_hic_read_shadow_ram buffer;
 506
 507         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
 508         buffer.hdr.req.buf_lenh = 0;
 509         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
 510         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 511
 512         /* convert offset from words to bytes */
 513         buffer.address = cpu_to_be32(offset * 2);
 514         /* one word */
 515         buffer.length = cpu_to_be16(sizeof(u16));
 516
 517         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
 518                                               sizeof(buffer),
 519                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 520         if (status)
 521                 return status;
 522
 523         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
 524                                           FW_NVM_DATA_OFFSET);
 525
 526         return 0;
 527 }
 528
 529 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
 530  *  @hw: pointer to hardware structure
 531  *  @offset: offset of  word in the EEPROM to read
 532  *  @words: number of words
 533  *  @data: word(s) read from the EEPROM
 534  *
 535  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
 536  **/
 537 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
 538                                             u16 offset, u16 words, u16 *data)
 539 {
 540         struct ixgbe_hic_read_shadow_ram buffer;
 541         u32 current_word = 0;
 542         u16 words_to_read;
 543         s32 status;
 544         u32 i;
 545
 546         /* Take semaphore for the entire operation. */
 547         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 548         if (status) {
 549                 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n");
 550                 return status;
 551         }
 552
 553         while (words) {
 554                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
 555                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
 556                 else
 557                         words_to_read = words;
 558
 559                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
 560                 buffer.hdr.req.buf_lenh = 0;
 561                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
 562                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 563
 564                 /* convert offset from words to bytes */
 565                 buffer.address = cpu_to_be32((offset + current_word) * 2);
 566                 buffer.length = cpu_to_be16(words_to_read * 2);
 567
 568                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
 569                                                       sizeof(buffer),
 570                                                       IXGBE_HI_COMMAND_TIMEOUT,
 571                                                       false);
 572                 if (status) {
 573                         hw_dbg(hw, "Host interface command failed\n");
 574                         goto out;
 575                 }
 576
 577                 for (i = 0; i < words_to_read; i++) {
 578                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
 579                                   2 * i;
 580                         u32 value = IXGBE_READ_REG(hw, reg);
 581
 582                         data[current_word] = (u16)(value & 0xffff);
 583                         current_word++;
 584                         i++;
 585                         if (i < words_to_read) {
 586                                 value >>= 16;
 587                                 data[current_word] = (u16)(value & 0xffff);
 588                                 current_word++;
 589                         }
 590                 }
 591                 words -= words_to_read;
 592         }
 593
 594 out:
 595         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 596         return status;
 597 }
 598
 599 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region
 600  *  @hw: pointer to hardware structure
 601  *  @ptr: pointer offset in eeprom
 602  *  @size: size of section pointed by ptr, if 0 first word will be used as size
 603  *  @csum: address of checksum to update
 604  *
 605  *  Returns error status for any failure
 606  **/
 607 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
 608                                    u16 size, u16 *csum, u16 *buffer,
 609                                    u32 buffer_size)
 610 {
 611         u16 buf[256];
 612         s32 status;
 613         u16 length, bufsz, i, start;
 614         u16 *local_buffer;
 615
 616         bufsz = sizeof(buf) / sizeof(buf[0]);
 617
 618         /* Read a chunk at the pointer location */
 619         if (!buffer) {
 620                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
 621                 if (status) {
 622                         hw_dbg(hw, "Failed to read EEPROM image\n");
 623                         return status;
 624                 }
 625                 local_buffer = buf;
 626         } else {
 627                 if (buffer_size < ptr)
 628                         return  IXGBE_ERR_PARAM;
 629                 local_buffer = &buffer[ptr];
 630         }
 631
 632         if (size) {
 633                 start = 0;
 634                 length = size;
 635         } else {
 636                 start = 1;
 637                 length = local_buffer[0];
 638
 639                 /* Skip pointer section if length is invalid. */
 640                 if (length == 0xFFFF || length == 0 ||
 641                     (ptr + length) >= hw->eeprom.word_size)
 642                         return 0;
 643         }
 644
 645         if (buffer && ((u32)start + (u32)length > buffer_size))
 646                 return IXGBE_ERR_PARAM;
 647
 648         for (i = start; length; i++, length--) {
 649                 if (i == bufsz && !buffer) {
 650                         ptr += bufsz;
 651                         i = 0;
 652                         if (length < bufsz)
 653                                 bufsz = length;
 654
 655                         /* Read a chunk at the pointer location */
 656                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
 657                                                                   bufsz, buf);
 658                         if (status) {
 659                                 hw_dbg(hw, "Failed to read EEPROM image\n");
 660                                 return status;
 661                         }
 662                 }
 663                 *csum += local_buffer[i];
 664         }
 665         return 0;
 666 }
 667
 668 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum
 669  *  @hw: pointer to hardware structure
 670  *  @buffer: pointer to buffer containing calculated checksum
 671  *  @buffer_size: size of buffer
 672  *
 673  *  Returns a negative error code on error, or the 16-bit checksum
 674  **/
 675 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer,
 676                                     u32 buffer_size)
 677 {
 678         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
 679         u16 *local_buffer;
 680         s32 status;
 681         u16 checksum = 0;
 682         u16 pointer, i, size;
 683
 684         hw->eeprom.ops.init_params(hw);
 685
 686         if (!buffer) {
 687                 /* Read pointer area */
 688                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
 689                                                 IXGBE_EEPROM_LAST_WORD + 1,
 690                                                 eeprom_ptrs);
 691                 if (status) {
 692                         hw_dbg(hw, "Failed to read EEPROM image\n");
 693                         return status;
 694                 }
 695                 local_buffer = eeprom_ptrs;
 696         } else {
 697                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
 698                         return IXGBE_ERR_PARAM;
 699                 local_buffer = buffer;
 700         }
 701
 702         /* For X550 hardware include 0x0-0x41 in the checksum, skip the
 703          * checksum word itself
 704          */
 705         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
 706                 if (i != IXGBE_EEPROM_CHECKSUM)
 707                         checksum += local_buffer[i];
 708
 709         /* Include all data from pointers 0x3, 0x6-0xE.  This excludes the
 710          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
 711          */
 712         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
 713                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
 714                         continue;
 715
 716                 pointer = local_buffer[i];
 717
 718                 /* Skip pointer section if the pointer is invalid. */
 719                 if (pointer == 0xFFFF || pointer == 0 ||
 720                     pointer >= hw->eeprom.word_size)
 721                         continue;
 722
 723                 switch (i) {
 724                 case IXGBE_PCIE_GENERAL_PTR:
 725                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
 726                         break;
 727                 case IXGBE_PCIE_CONFIG0_PTR:
 728                 case IXGBE_PCIE_CONFIG1_PTR:
 729                         size = IXGBE_PCIE_CONFIG_SIZE;
 730                         break;
 731                 default:
 732                         size = 0;
 733                         break;
 734                 }
 735
 736                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
 737                                                  buffer, buffer_size);
 738                 if (status)
 739                         return status;
 740         }
 741
 742         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
 743
 744         return (s32)checksum;
 745 }
 746
 747 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
 748  *  @hw: pointer to hardware structure
 749  *
 750  *  Returns a negative error code on error, or the 16-bit checksum
 751  **/
 752 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
 753 {
 754         return ixgbe_calc_checksum_X550(hw, NULL, 0);
 755 }
 756
 757 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
 758  *  @hw: pointer to hardware structure
 759  *  @offset: offset of  word in the EEPROM to read
 760  *  @data: word read from the EEPROM
 761  *
 762  *   Reads a 16 bit word from the EEPROM using the hostif.
 763  **/
 764 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
 765 {
 766         s32 status = 0;
 767
 768         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
 769                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
 770                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 771         } else {
 772                 status = IXGBE_ERR_SWFW_SYNC;
 773         }
 774
 775         return status;
 776 }
 777
 778 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
 779  *  @hw: pointer to hardware structure
 780  *  @checksum_val: calculated checksum
 781  *
 782  *  Performs checksum calculation and validates the EEPROM checksum.  If the
 783  *  caller does not need checksum_val, the value can be NULL.
 784  **/
 785 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,
 786                                                u16 *checksum_val)
 787 {
 788         s32 status;
 789         u16 checksum;
 790         u16 read_checksum = 0;
 791
 792         /* Read the first word from the EEPROM. If this times out or fails, do
 793          * not continue or we could be in for a very long wait while every
 794          * EEPROM read fails
 795          */
 796         status = hw->eeprom.ops.read(hw, 0, &checksum);
 797         if (status) {
 798                 hw_dbg(hw, "EEPROM read failed\n");
 799                 return status;
 800         }
 801
 802         status = hw->eeprom.ops.calc_checksum(hw);
 803         if (status < 0)
 804                 return status;
 805
 806         checksum = (u16)(status & 0xffff);
 807
 808         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
 809                                            &read_checksum);
 810         if (status)
 811                 return status;
 812
 813         /* Verify read checksum from EEPROM is the same as
 814          * calculated checksum
 815          */
 816         if (read_checksum != checksum) {
 817                 status = IXGBE_ERR_EEPROM_CHECKSUM;
 818                 hw_dbg(hw, "Invalid EEPROM checksum");
 819         }
 820
 821         /* If the user cares, return the calculated checksum */
 822         if (checksum_val)
 823                 *checksum_val = checksum;
 824
 825         return status;
 826 }
 827
 828 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
 829  *  @hw: pointer to hardware structure
 830  *  @offset: offset of  word in the EEPROM to write
 831  *  @data: word write to the EEPROM
 832  *
 833  *  Write a 16 bit word to the EEPROM using the hostif.
 834  **/
 835 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
 836                                            u16 data)
 837 {
 838         s32 status;
 839         struct ixgbe_hic_write_shadow_ram buffer;
 840
 841         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
 842         buffer.hdr.req.buf_lenh = 0;
 843         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
 844         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 845
 846         /* one word */
 847         buffer.length = cpu_to_be16(sizeof(u16));
 848         buffer.data = data;
 849         buffer.address = cpu_to_be32(offset * 2);
 850
 851         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
 852                                               sizeof(buffer),
 853                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 854         return status;
 855 }
 856
 857 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
 858  *  @hw: pointer to hardware structure
 859  *  @offset: offset of  word in the EEPROM to write
 860  *  @data: word write to the EEPROM
 861  *
 862  *  Write a 16 bit word to the EEPROM using the hostif.
 863  **/
 864 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data)
 865 {
 866         s32 status = 0;
 867
 868         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
 869                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
 870                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 871         } else {
 872                 hw_dbg(hw, "write ee hostif failed to get semaphore");
 873                 status = IXGBE_ERR_SWFW_SYNC;
 874         }
 875
 876         return status;
 877 }
 878
 879 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
 880  *  @hw: pointer to hardware structure
 881  *
 882  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
 883  **/
 884 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
 885 {
 886         s32 status = 0;
 887         union ixgbe_hic_hdr2 buffer;
 888
 889         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
 890         buffer.req.buf_lenh = 0;
 891         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
 892         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
 893
 894         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
 895                                               sizeof(buffer),
 896                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 897         return status;
 898 }
 899
 900 /**
 901  * ixgbe_get_bus_info_X550em - Set PCI bus info
 902  * @hw: pointer to hardware structure
 903  *
 904  * Sets bus link width and speed to unknown because X550em is
 905  * not a PCI device.
 906  **/
 907 static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
 908 {
 909         hw->bus.type  = ixgbe_bus_type_internal;
 910         hw->bus.width = ixgbe_bus_width_unknown;
 911         hw->bus.speed = ixgbe_bus_speed_unknown;
 912
 913         hw->mac.ops.set_lan_id(hw);
 914
 915         return 0;
 916 }
 917
 918 /** ixgbe_disable_rx_x550 - Disable RX unit
 919  *
 920  *  Enables the Rx DMA unit for x550
 921  **/
 922 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
 923 {
 924         u32 rxctrl, pfdtxgswc;
 925         s32 status;
 926         struct ixgbe_hic_disable_rxen fw_cmd;
 927
 928         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
 929         if (rxctrl & IXGBE_RXCTRL_RXEN) {
 930                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
 931                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
 932                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
 933                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
 934                         hw->mac.set_lben = true;
 935                 } else {
 936                         hw->mac.set_lben = false;
 937                 }
 938
 939                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
 940                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
 941                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 942                 fw_cmd.port_number = (u8)hw->bus.lan_id;
 943
 944                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
 945                                         sizeof(struct ixgbe_hic_disable_rxen),
 946                                         IXGBE_HI_COMMAND_TIMEOUT, true);
 947
 948                 /* If we fail - disable RX using register write */
 949                 if (status) {
 950                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
 951                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
 952                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
 953                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
 954                         }
 955                 }
 956         }
 957 }
 958
 959 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
 960  *  @hw: pointer to hardware structure
 961  *
 962  *  After writing EEPROM to shadow RAM using EEWR register, software calculates
 963  *  checksum and updates the EEPROM and instructs the hardware to update
 964  *  the flash.
 965  **/
 966 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
 967 {
 968         s32 status;
 969         u16 checksum = 0;
 970
 971         /* Read the first word from the EEPROM. If this times out or fails, do
 972          * not continue or we could be in for a very long wait while every
 973          * EEPROM read fails
 974          */
 975         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
 976         if (status) {
 977                 hw_dbg(hw, "EEPROM read failed\n");
 978                 return status;
 979         }
 980
 981         status = ixgbe_calc_eeprom_checksum_X550(hw);
 982         if (status < 0)
 983                 return status;
 984
 985         checksum = (u16)(status & 0xffff);
 986
 987         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
 988                                             checksum);
 989         if (status)
 990                 return status;
 991
 992         status = ixgbe_update_flash_X550(hw);
 993
 994         return status;
 995 }
 996
 997 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
 998  *  @hw: pointer to hardware structure
 999  *  @offset: offset of  word in the EEPROM to write
1000  *  @words: number of words
1001  *  @data: word(s) write to the EEPROM
1002  *
1003  *
1004  *  Write a 16 bit word(s) to the EEPROM using the hostif.
1005  **/
1006 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1007                                              u16 offset, u16 words,
1008                                              u16 *data)
1009 {
1010         s32 status = 0;
1011         u32 i = 0;
1012
1013         /* Take semaphore for the entire operation. */
1014         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1015         if (status) {
1016                 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n");
1017                 return status;
1018         }
1019
1020         for (i = 0; i < words; i++) {
1021                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1022                                                          data[i]);
1023                 if (status) {
1024                         hw_dbg(hw, "Eeprom buffered write failed\n");
1025                         break;
1026                 }
1027         }
1028
1029         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1030
1031         return status;
1032 }
1033
1034 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the
1035  *  IOSF device
1036  *
1037  *  @hw: pointer to hardware structure
1038  *  @reg_addr: 32 bit PHY register to write
1039  *  @device_type: 3 bit device type
1040  *  @data: Data to write to the register
1041  **/
1042 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1043                                         u32 device_type, u32 data)
1044 {
1045         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1046         u32 command, error;
1047         s32 ret;
1048
1049         ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
1050         if (ret)
1051                 return ret;
1052
1053         ret = ixgbe_iosf_wait(hw, NULL);
1054         if (ret)
1055                 goto out;
1056
1057         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1058                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1059
1060         /* Write IOSF control register */
1061         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1062
1063         /* Write IOSF data register */
1064         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1065
1066         ret = ixgbe_iosf_wait(hw, &command);
1067
1068         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1069                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1070                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1071                 hw_dbg(hw, "Failed to write, error %x\n", error);
1072                 return IXGBE_ERR_PHY;
1073         }
1074
1075 out:
1076         hw->mac.ops.release_swfw_sync(hw, gssr);
1077         return ret;
1078 }
1079
1080 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1081  *  @hw: pointer to hardware structure
1082  *  @speed: the link speed to force
1083  *
1084  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1085  *  internal and external PHY at a specific speed, without autonegotiation.
1086  **/
1087 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1088 {
1089         s32 status;
1090         u32 reg_val;
1091
1092         /* Disable AN and force speed to 10G Serial. */
1093         status = ixgbe_read_iosf_sb_reg_x550(hw,
1094                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1095                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1096         if (status)
1097                 return status;
1098
1099         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1100         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1101
1102         /* Select forced link speed for internal PHY. */
1103         switch (*speed) {
1104         case IXGBE_LINK_SPEED_10GB_FULL:
1105                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1106                 break;
1107         case IXGBE_LINK_SPEED_1GB_FULL:
1108                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1109                 break;
1110         default:
1111                 /* Other link speeds are not supported by internal KR PHY. */
1112                 return IXGBE_ERR_LINK_SETUP;
1113         }
1114
1115         status = ixgbe_write_iosf_sb_reg_x550(hw,
1116                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1117                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1118         if (status)
1119                 return status;
1120
1121         /* Disable training protocol FSM. */
1122         status = ixgbe_read_iosf_sb_reg_x550(hw,
1123                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1124                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1125         if (status)
1126                 return status;
1127
1128         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1129         status = ixgbe_write_iosf_sb_reg_x550(hw,
1130                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1131                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1132         if (status)
1133                 return status;
1134
1135         /* Disable Flex from training TXFFE. */
1136         status = ixgbe_read_iosf_sb_reg_x550(hw,
1137                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1138                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1139         if (status)
1140                 return status;
1141
1142         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1143         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1144         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1145         status = ixgbe_write_iosf_sb_reg_x550(hw,
1146                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1147                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1148         if (status)
1149                 return status;
1150
1151         status = ixgbe_read_iosf_sb_reg_x550(hw,
1152                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1153                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1154         if (status)
1155                 return status;
1156
1157         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1158         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1159         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1160         status = ixgbe_write_iosf_sb_reg_x550(hw,
1161                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1162                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1163         if (status)
1164                 return status;
1165
1166         /* Enable override for coefficients. */
1167         status = ixgbe_read_iosf_sb_reg_x550(hw,
1168                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1169                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1170         if (status)
1171                 return status;
1172
1173         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1174         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1175         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1176         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1177         status = ixgbe_write_iosf_sb_reg_x550(hw,
1178                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1179                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1180         if (status)
1181                 return status;
1182
1183         /* Toggle port SW reset by AN reset. */
1184         status = ixgbe_read_iosf_sb_reg_x550(hw,
1185                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1186                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1187         if (status)
1188                 return status;
1189
1190         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1191         status = ixgbe_write_iosf_sb_reg_x550(hw,
1192                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1193                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1194
1195         return status;
1196 }
1197
1198 /**
1199  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1200  *  @hw: pointer to hardware structure
1201  *  @linear: true if SFP module is linear
1202  */
1203 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1204 {
1205         switch (hw->phy.sfp_type) {
1206         case ixgbe_sfp_type_not_present:
1207                 return IXGBE_ERR_SFP_NOT_PRESENT;
1208         case ixgbe_sfp_type_da_cu_core0:
1209         case ixgbe_sfp_type_da_cu_core1:
1210                 *linear = true;
1211                 break;
1212         case ixgbe_sfp_type_srlr_core0:
1213         case ixgbe_sfp_type_srlr_core1:
1214         case ixgbe_sfp_type_da_act_lmt_core0:
1215         case ixgbe_sfp_type_da_act_lmt_core1:
1216         case ixgbe_sfp_type_1g_sx_core0:
1217         case ixgbe_sfp_type_1g_sx_core1:
1218         case ixgbe_sfp_type_1g_lx_core0:
1219         case ixgbe_sfp_type_1g_lx_core1:
1220                 *linear = false;
1221                 break;
1222         case ixgbe_sfp_type_unknown:
1223         case ixgbe_sfp_type_1g_cu_core0:
1224         case ixgbe_sfp_type_1g_cu_core1:
1225         default:
1226                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1227         }
1228
1229         return 0;
1230 }
1231
1232 /**
1233  *  ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1234  *  @hw: pointer to hardware structure
1235  *
1236  *  Configures the extern PHY and the integrated KR PHY for SFP support.
1237  */
1238 static s32
1239 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1240                                 ixgbe_link_speed speed,
1241                                 __always_unused bool autoneg_wait_to_complete)
1242 {
1243         s32 status;
1244         u16 slice, value;
1245         bool setup_linear = false;
1246
1247         /* Check if SFP module is supported and linear */
1248         status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1249
1250         /* If no SFP module present, then return success. Return success since
1251          * there is no reason to configure CS4227 and SFP not present error is
1252          * not accepted in the setup MAC link flow.
1253          */
1254         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
1255                 return 0;
1256
1257         if (status)
1258                 return status;
1259
1260         /* Configure CS4227 LINE side to 10G SR. */
1261         slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);
1262         value = IXGBE_CS4227_SPEED_10G;
1263         status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227, slice,
1264                                                   value);
1265
1266         /* Configure CS4227 for HOST connection rate then type. */
1267         slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);
1268         value = speed & IXGBE_LINK_SPEED_10GB_FULL ?
1269                 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
1270         status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227, slice,
1271                                                   value);
1272
1273         slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);
1274         if (setup_linear)
1275                 value = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1276         else
1277                 value = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1278         status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227, slice,
1279                                                   value);
1280
1281         /* If internal link mode is XFI, then setup XFI internal link. */
1282         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))
1283                 status = ixgbe_setup_ixfi_x550em(hw, &speed);
1284
1285         return status;
1286 }
1287
1288 /**
1289  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
1290  * @hw: pointer to hardware structure
1291  * @speed: new link speed
1292  * @autoneg_wait_to_complete: true when waiting for completion is needed
1293  *
1294  * Setup internal/external PHY link speed based on link speed, then set
1295  * external PHY auto advertised link speed.
1296  *
1297  * Returns error status for any failure
1298  **/
1299 static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
1300                                          ixgbe_link_speed speed,
1301                                          bool autoneg_wait)
1302 {
1303         s32 status;
1304         ixgbe_link_speed force_speed;
1305
1306         /* Setup internal/external PHY link speed to iXFI (10G), unless
1307          * only 1G is auto advertised then setup KX link.
1308          */
1309         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1310                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1311         else
1312                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1313
1314         /* If internal link mode is XFI, then setup XFI internal link. */
1315         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1316                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
1317
1318                 if (status)
1319                         return status;
1320         }
1321
1322         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1323 }
1324
1325 /** ixgbe_check_link_t_X550em - Determine link and speed status
1326   * @hw: pointer to hardware structure
1327   * @speed: pointer to link speed
1328   * @link_up: true when link is up
1329   * @link_up_wait_to_complete: bool used to wait for link up or not
1330   *
1331   * Check that both the MAC and X557 external PHY have link.
1332   **/
1333 static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw,
1334                                      ixgbe_link_speed *speed,
1335                                      bool *link_up,
1336                                      bool link_up_wait_to_complete)
1337 {
1338         u32 status;
1339         u16 autoneg_status;
1340
1341         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1342                 return IXGBE_ERR_CONFIG;
1343
1344         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
1345                                               link_up_wait_to_complete);
1346
1347         /* If check link fails or MAC link is not up, then return */
1348         if (status || !(*link_up))
1349                 return status;
1350
1351          /* MAC link is up, so check external PHY link.
1352           * Read this twice back to back to indicate current status.
1353           */
1354         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1355                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1356                                       &autoneg_status);
1357         if (status)
1358                 return status;
1359
1360         /* If external PHY link is not up, then indicate link not up */
1361         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1362                 *link_up = false;
1363
1364         return 0;
1365 }
1366
1367 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1368  *  @hw: pointer to hardware structure
1369  **/
1370 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1371 {
1372         struct ixgbe_mac_info *mac = &hw->mac;
1373
1374         switch (mac->ops.get_media_type(hw)) {
1375         case ixgbe_media_type_fiber:
1376                 /* CS4227 does not support autoneg, so disable the laser control
1377                  * functions for SFP+ fiber
1378                  */
1379                 mac->ops.disable_tx_laser = NULL;
1380                 mac->ops.enable_tx_laser = NULL;
1381                 mac->ops.flap_tx_laser = NULL;
1382                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1383                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1384                 mac->ops.set_rate_select_speed =
1385                                         ixgbe_set_soft_rate_select_speed;
1386                 break;
1387         case ixgbe_media_type_copper:
1388                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1389                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1390                 break;
1391         default:
1392                 break;
1393         }
1394 }
1395
1396 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module
1397  * @hw: pointer to hardware structure
1398  */
1399 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1400 {
1401         s32 status;
1402         bool linear;
1403
1404         /* Check if SFP module is supported */
1405         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1406         if (status)
1407                 return status;
1408
1409         ixgbe_init_mac_link_ops_X550em(hw);
1410         hw->phy.ops.reset = NULL;
1411
1412         return 0;
1413 }
1414
1415 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities
1416  * @hw: pointer to hardware structure
1417  * @speed: pointer to link speed
1418  * @autoneg: true when autoneg or autotry is enabled
1419  **/
1420 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1421                                               ixgbe_link_speed *speed,
1422                                               bool *autoneg)
1423 {
1424         /* SFP */
1425         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1426                 /* CS4227 SFP must not enable auto-negotiation */
1427                 *autoneg = false;
1428
1429                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1430                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
1431                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1432                         return 0;
1433                 }
1434
1435                 /* Link capabilities are based on SFP */
1436                 if (hw->phy.multispeed_fiber)
1437                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1438                                  IXGBE_LINK_SPEED_1GB_FULL;
1439                 else
1440                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1441         } else {
1442                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1443                          IXGBE_LINK_SPEED_1GB_FULL;
1444                 *autoneg = true;
1445         }
1446         return 0;
1447 }
1448
1449 /**
1450  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1451  * @hw: pointer to hardware structure
1452  * @lsc: pointer to boolean flag which indicates whether external Base T
1453  *       PHY interrupt is lsc
1454  *
1455  * Determime if external Base T PHY interrupt cause is high temperature
1456  * failure alarm or link status change.
1457  *
1458  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1459  * failure alarm, else return PHY access status.
1460  **/
1461 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1462 {
1463         u32 status;
1464         u16 reg;
1465
1466         *lsc = false;
1467
1468         /* Vendor alarm triggered */
1469         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1470                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1471                                       &reg);
1472
1473         if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1474                 return status;
1475
1476         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1477         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1478                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1479                                       &reg);
1480
1481         if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1482                                 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1483                 return status;
1484
1485         /* High temperature failure alarm triggered */
1486         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1487                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1488                                       &reg);
1489
1490         if (status)
1491                 return status;
1492
1493         /* If high temperature failure, then return over temp error and exit */
1494         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1495                 /* power down the PHY in case the PHY FW didn't already */
1496                 ixgbe_set_copper_phy_power(hw, false);
1497                 return IXGBE_ERR_OVERTEMP;
1498         }
1499
1500         /* Vendor alarm 2 triggered */
1501         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1502                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1503
1504         if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1505                 return status;
1506
1507         /* link connect/disconnect event occurred */
1508         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1509                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1510
1511         if (status)
1512                 return status;
1513
1514         /* Indicate LSC */
1515         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1516                 *lsc = true;
1517
1518         return 0;
1519 }
1520
1521 /**
1522  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1523  * @hw: pointer to hardware structure
1524  *
1525  * Enable link status change and temperature failure alarm for the external
1526  * Base T PHY
1527  *
1528  * Returns PHY access status
1529  **/
1530 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1531 {
1532         u32 status;
1533         u16 reg;
1534         bool lsc;
1535
1536         /* Clear interrupt flags */
1537         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1538
1539         /* Enable link status change alarm */
1540         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1541                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1542         if (status)
1543                 return status;
1544
1545         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1546
1547         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1548                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1549         if (status)
1550                 return status;
1551
1552         /* Enables high temperature failure alarm */
1553         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1554                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1555                                       &reg);
1556         if (status)
1557                 return status;
1558
1559         reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1560
1561         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1562                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1563                                        reg);
1564         if (status)
1565                 return status;
1566
1567         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1568         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1569                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1570                                       &reg);
1571         if (status)
1572                 return status;
1573
1574         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1575                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1576
1577         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1578                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1579                                        reg);
1580         if (status)
1581                 return status;
1582
1583         /* Enable chip-wide vendor alarm */
1584         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1585                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1586                                       &reg);
1587         if (status)
1588                 return status;
1589
1590         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1591
1592         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1593                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1594                                        reg);
1595
1596         return status;
1597 }
1598
1599 /**
1600  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
1601  * @hw: pointer to hardware structure
1602  *
1603  * Handle external Base T PHY interrupt. If high temperature
1604  * failure alarm then return error, else if link status change
1605  * then setup internal/external PHY link
1606  *
1607  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1608  * failure alarm, else return PHY access status.
1609  **/
1610 static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1611 {
1612         struct ixgbe_phy_info *phy = &hw->phy;
1613         bool lsc;
1614         u32 status;
1615
1616         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1617         if (status)
1618                 return status;
1619
1620         if (lsc && phy->ops.setup_internal_link)
1621                 return phy->ops.setup_internal_link(hw);
1622
1623         return 0;
1624 }
1625
1626 /**
1627  * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1628  * @hw: pointer to hardware structure
1629  * @speed: link speed
1630  *
1631  * Configures the integrated KR PHY.
1632  **/
1633 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1634                                        ixgbe_link_speed speed)
1635 {
1636         s32 status;
1637         u32 reg_val;
1638
1639         status = ixgbe_read_iosf_sb_reg_x550(hw,
1640                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1641                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1642         if (status)
1643                 return status;
1644
1645         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1646         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1647                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1648         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1649                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1650
1651         /* Advertise 10G support. */
1652         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1653                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1654
1655         /* Advertise 1G support. */
1656         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1657                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1658
1659         /* Restart auto-negotiation. */
1660         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1661         status = ixgbe_write_iosf_sb_reg_x550(hw,
1662                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1663                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1664
1665         return status;
1666 }
1667
1668 /** ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1669  *  @hw: pointer to hardware structure
1670  *
1671  *   Configures the integrated KX4 PHY.
1672  **/
1673 static s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1674 {
1675         s32 status;
1676         u32 reg_val;
1677
1678         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1679                                              IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
1680                                              hw->bus.lan_id, &reg_val);
1681         if (status)
1682                 return status;
1683
1684         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1685                      IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1686
1687         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1688
1689         /* Advertise 10G support. */
1690         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1691                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1692
1693         /* Advertise 1G support. */
1694         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1695                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1696
1697         /* Restart auto-negotiation. */
1698         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1699         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1700                                               IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
1701                                               hw->bus.lan_id, reg_val);
1702
1703         return status;
1704 }
1705
1706 /**  ixgbe_setup_kr_x550em - Configure the KR PHY.
1707  *   @hw: pointer to hardware structure
1708  *
1709  *   Configures the integrated KR PHY.
1710  **/
1711 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1712 {
1713         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1714 }
1715
1716 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
1717  *  @hw: address of hardware structure
1718  *  @link_up: address of boolean to indicate link status
1719  *
1720  *  Returns error code if unable to get link status.
1721  **/
1722 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
1723 {
1724         u32 ret;
1725         u16 autoneg_status;
1726
1727         *link_up = false;
1728
1729         /* read this twice back to back to indicate current status */
1730         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1731                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1732                                    &autoneg_status);
1733         if (ret)
1734                 return ret;
1735
1736         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1737                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1738                                    &autoneg_status);
1739         if (ret)
1740                 return ret;
1741
1742         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
1743
1744         return 0;
1745 }
1746
1747 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1748  *  @hw: point to hardware structure
1749  *
1750  *  Configures the link between the integrated KR PHY and the external X557 PHY
1751  *  The driver will call this function when it gets a link status change
1752  *  interrupt from the X557 PHY. This function configures the link speed
1753  *  between the PHYs to match the link speed of the BASE-T link.
1754  *
1755  * A return of a non-zero value indicates an error, and the base driver should
1756  * not report link up.
1757  **/
1758 static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1759 {
1760         ixgbe_link_speed force_speed;
1761         bool link_up;
1762         u32 status;
1763         u16 speed;
1764
1765         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1766                 return IXGBE_ERR_CONFIG;
1767
1768         /* If link is not up, then there is no setup necessary so return  */
1769         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1770         if (status)
1771                 return status;
1772
1773         if (!link_up)
1774                 return 0;
1775
1776         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1777                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1778                                       &speed);
1779         if (status)
1780                 return status;
1781
1782         /* If link is not still up, then no setup is necessary so return */
1783         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1784         if (status)
1785                 return status;
1786
1787         if (!link_up)
1788                 return 0;
1789
1790         /* clear everything but the speed and duplex bits */
1791         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1792
1793         switch (speed) {
1794         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1795                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1796                 break;
1797         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1798                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1799                 break;
1800         default:
1801                 /* Internal PHY does not support anything else */
1802                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1803         }
1804
1805         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1806 }
1807
1808 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
1809  *  @hw: pointer to hardware structure
1810  **/
1811 static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
1812 {
1813         s32 status;
1814
1815         status = ixgbe_reset_phy_generic(hw);
1816
1817         if (status)
1818                 return status;
1819
1820         /* Configure Link Status Alarm and Temperature Threshold interrupts */
1821         return ixgbe_enable_lasi_ext_t_x550em(hw);
1822 }
1823
1824 /** ixgbe_get_lcd_x550em - Determine lowest common denominator
1825  *  @hw: pointer to hardware structure
1826  *  @lcd_speed: pointer to lowest common link speed
1827  *
1828  *  Determine lowest common link speed with link partner.
1829  **/
1830 static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw,
1831                                   ixgbe_link_speed *lcd_speed)
1832 {
1833         u16 an_lp_status;
1834         s32 status;
1835         u16 word = hw->eeprom.ctrl_word_3;
1836
1837         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
1838
1839         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
1840                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1841                                       &an_lp_status);
1842         if (status)
1843                 return status;
1844
1845         /* If link partner advertised 1G, return 1G */
1846         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
1847                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
1848                 return status;
1849         }
1850
1851         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
1852         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
1853             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
1854                 return status;
1855
1856         /* Link partner not capable of lower speeds, return 10G */
1857         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
1858         return status;
1859 }
1860
1861 /** ixgbe_enter_lplu_x550em - Transition to low power states
1862  *  @hw: pointer to hardware structure
1863  *
1864  *  Configures Low Power Link Up on transition to low power states
1865  *  (from D0 to non-D0). Link is required to enter LPLU so avoid resetting
1866  *  the X557 PHY immediately prior to entering LPLU.
1867  **/
1868 static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
1869 {
1870         u16 an_10g_cntl_reg, autoneg_reg, speed;
1871         s32 status;
1872         ixgbe_link_speed lcd_speed;
1873         u32 save_autoneg;
1874         bool link_up;
1875
1876         /* SW LPLU not required on later HW revisions. */
1877         if (IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))
1878                 return 0;
1879
1880         /* If blocked by MNG FW, then don't restart AN */
1881         if (ixgbe_check_reset_blocked(hw))
1882                 return 0;
1883
1884         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1885         if (status)
1886                 return status;
1887
1888         status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3,
1889                                      &hw->eeprom.ctrl_word_3);
1890         if (status)
1891                 return status;
1892
1893         /* If link is down, LPLU disabled in NVM, WoL disabled, or
1894          * manageability disabled, then force link down by entering
1895          * low power mode.
1896          */
1897         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
1898             !(hw->wol_enabled || ixgbe_mng_present(hw)))
1899                 return ixgbe_set_copper_phy_power(hw, false);
1900
1901         /* Determine LCD */
1902         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
1903         if (status)
1904                 return status;
1905
1906         /* If no valid LCD link speed, then force link down and exit. */
1907         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
1908                 return ixgbe_set_copper_phy_power(hw, false);
1909
1910         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1911                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1912                                       &speed);
1913         if (status)
1914                 return status;
1915
1916         /* If no link now, speed is invalid so take link down */
1917         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1918         if (status)
1919                 return ixgbe_set_copper_phy_power(hw, false);
1920
1921         /* clear everything but the speed bits */
1922         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
1923
1924         /* If current speed is already LCD, then exit. */
1925         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
1926              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
1927             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
1928              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
1929                 return status;
1930
1931         /* Clear AN completed indication */
1932         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
1933                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1934                                       &autoneg_reg);
1935         if (status)
1936                 return status;
1937
1938         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1939                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1940                                       &an_10g_cntl_reg);
1941         if (status)
1942                 return status;
1943
1944         status = hw->phy.ops.read_reg(hw,
1945                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
1946                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1947                                       &autoneg_reg);
1948         if (status)
1949                 return status;
1950
1951         save_autoneg = hw->phy.autoneg_advertised;
1952
1953         /* Setup link at least common link speed */
1954         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
1955
1956         /* restore autoneg from before setting lplu speed */
1957         hw->phy.autoneg_advertised = save_autoneg;
1958
1959         return status;
1960 }
1961
1962 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1963  *  @hw: pointer to hardware structure
1964  *
1965  *  Initialize any function pointers that were not able to be
1966  *  set during init_shared_code because the PHY/SFP type was
1967  *  not known.  Perform the SFP init if necessary.
1968  **/
1969 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1970 {
1971         struct ixgbe_phy_info *phy = &hw->phy;
1972         ixgbe_link_speed speed;
1973         s32 ret_val;
1974
1975         hw->mac.ops.set_lan_id(hw);
1976
1977         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1978                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1979                 ixgbe_setup_mux_ctl(hw);
1980
1981                 /* Save NW management interface connected on board. This is used
1982                  * to determine internal PHY mode.
1983                  */
1984                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1985
1986                 /* If internal PHY mode is KR, then initialize KR link */
1987                 if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) {
1988                         speed = IXGBE_LINK_SPEED_10GB_FULL |
1989                                 IXGBE_LINK_SPEED_1GB_FULL;
1990                         ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
1991                 }
1992         }
1993
1994         /* Identify the PHY or SFP module */
1995         ret_val = phy->ops.identify(hw);
1996
1997         /* Setup function pointers based on detected hardware */
1998         ixgbe_init_mac_link_ops_X550em(hw);
1999         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2000                 phy->ops.reset = NULL;
2001
2002         /* Set functions pointers based on phy type */
2003         switch (hw->phy.type) {
2004         case ixgbe_phy_x550em_kx4:
2005                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
2006                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2007                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2008                 break;
2009         case ixgbe_phy_x550em_kr:
2010                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2011                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2012                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2013                 break;
2014         case ixgbe_phy_x550em_ext_t:
2015                 /* Save NW management interface connected on board. This is used
2016                  * to determine internal PHY mode
2017                  */
2018                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2019
2020                 /* If internal link mode is XFI, then setup iXFI internal link,
2021                  * else setup KR now.
2022                  */
2023                 if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2024                         phy->ops.setup_internal_link =
2025                                         ixgbe_setup_internal_phy_t_x550em;
2026                 } else {
2027                         speed = IXGBE_LINK_SPEED_10GB_FULL |
2028                                 IXGBE_LINK_SPEED_1GB_FULL;
2029                         ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
2030                 }
2031
2032                 /* setup SW LPLU only for first revision */
2033                 if (!(IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw,
2034                                                         IXGBE_FUSES0_GROUP(0))))
2035                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2036
2037                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2038                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2039                 break;
2040         default:
2041                 break;
2042         }
2043
2044         return ret_val;
2045 }
2046
2047 /** ixgbe_get_media_type_X550em - Get media type
2048  *  @hw: pointer to hardware structure
2049  *
2050  *  Returns the media type (fiber, copper, backplane)
2051  *
2052  */
2053 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
2054 {
2055         enum ixgbe_media_type media_type;
2056
2057         /* Detect if there is a copper PHY attached. */
2058         switch (hw->device_id) {
2059         case IXGBE_DEV_ID_X550EM_X_KR:
2060         case IXGBE_DEV_ID_X550EM_X_KX4:
2061                 media_type = ixgbe_media_type_backplane;
2062                 break;
2063         case IXGBE_DEV_ID_X550EM_X_SFP:
2064                 media_type = ixgbe_media_type_fiber;
2065                 break;
2066         case IXGBE_DEV_ID_X550EM_X_1G_T:
2067         case IXGBE_DEV_ID_X550EM_X_10G_T:
2068                  media_type = ixgbe_media_type_copper;
2069                 break;
2070         default:
2071                 media_type = ixgbe_media_type_unknown;
2072                 break;
2073         }
2074         return media_type;
2075 }
2076
2077 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2078  ** @hw: pointer to hardware structure
2079  **/
2080 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2081 {
2082         s32 status;
2083         u16 reg;
2084
2085         status = hw->phy.ops.read_reg(hw,
2086                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2087                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2088                                       &reg);
2089         if (status)
2090                 return status;
2091
2092         /* If PHY FW reset completed bit is set then this is the first
2093          * SW instance after a power on so the PHY FW must be un-stalled.
2094          */
2095         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2096                 status = hw->phy.ops.read_reg(hw,
2097                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2098                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2099                                         &reg);
2100                 if (status)
2101                         return status;
2102
2103                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2104
2105                 status = hw->phy.ops.write_reg(hw,
2106                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2107                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2108                                         reg);
2109                 if (status)
2110                         return status;
2111         }
2112
2113         return status;
2114 }
2115
2116 /**  ixgbe_reset_hw_X550em - Perform hardware reset
2117  **  @hw: pointer to hardware structure
2118  **
2119  **  Resets the hardware by resetting the transmit and receive units, masks
2120  **  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2121  **  reset.
2122  **/
2123 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2124 {
2125         ixgbe_link_speed link_speed;
2126         s32 status;
2127         u32 ctrl = 0;
2128         u32 i;
2129         u32 hlreg0;
2130         bool link_up = false;
2131
2132         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2133         status = hw->mac.ops.stop_adapter(hw);
2134         if (status)
2135                 return status;
2136
2137         /* flush pending Tx transactions */
2138         ixgbe_clear_tx_pending(hw);
2139
2140         /* PHY ops must be identified and initialized prior to reset */
2141
2142         /* Identify PHY and related function pointers */
2143         status = hw->phy.ops.init(hw);
2144
2145         /* start the external PHY */
2146         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2147                 status = ixgbe_init_ext_t_x550em(hw);
2148                 if (status)
2149                         return status;
2150         }
2151
2152         /* Setup SFP module if there is one present. */
2153         if (hw->phy.sfp_setup_needed) {
2154                 status = hw->mac.ops.setup_sfp(hw);
2155                 hw->phy.sfp_setup_needed = false;
2156         }
2157
2158         /* Reset PHY */
2159         if (!hw->phy.reset_disable && hw->phy.ops.reset)
2160                 hw->phy.ops.reset(hw);
2161
2162 mac_reset_top:
2163         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2164          * If link reset is used when link is up, it might reset the PHY when
2165          * mng is using it.  If link is down or the flag to force full link
2166          * reset is set, then perform link reset.
2167          */
2168         ctrl = IXGBE_CTRL_LNK_RST;
2169
2170         if (!hw->force_full_reset) {
2171                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2172                 if (link_up)
2173                         ctrl = IXGBE_CTRL_RST;
2174         }
2175
2176         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2177         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2178         IXGBE_WRITE_FLUSH(hw);
2179
2180         /* Poll for reset bit to self-clear meaning reset is complete */
2181         for (i = 0; i < 10; i++) {
2182                 udelay(1);
2183                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2184                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2185                         break;
2186         }
2187
2188         if (ctrl & IXGBE_CTRL_RST_MASK) {
2189                 status = IXGBE_ERR_RESET_FAILED;
2190                 hw_dbg(hw, "Reset polling failed to complete.\n");
2191         }
2192
2193         msleep(50);
2194
2195         /* Double resets are required for recovery from certain error
2196          * clear the multicast table.  Also reset num_rar_entries to 128,
2197          * since we modify this value when programming the SAN MAC address.
2198          */
2199         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2200                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2201                 goto mac_reset_top;
2202         }
2203
2204         /* Store the permanent mac address */
2205         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2206
2207         /* Store MAC address from RAR0, clear receive address registers, and
2208          * clear the multicast table.  Also reset num_rar_entries to 128,
2209          * since we modify this value when programming the SAN MAC address.
2210          */
2211         hw->mac.num_rar_entries = 128;
2212         hw->mac.ops.init_rx_addrs(hw);
2213
2214         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
2215                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2216                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2217                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2218         }
2219
2220         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2221                 ixgbe_setup_mux_ctl(hw);
2222
2223         return status;
2224 }
2225
2226 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype
2227  *      anti-spoofing
2228  *  @hw:  pointer to hardware structure
2229  *  @enable: enable or disable switch for Ethertype anti-spoofing
2230  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
2231  **/
2232 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
2233                                                    bool enable, int vf)
2234 {
2235         int vf_target_reg = vf >> 3;
2236         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
2237         u32 pfvfspoof;
2238
2239         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
2240         if (enable)
2241                 pfvfspoof |= (1 << vf_target_shift);
2242         else
2243                 pfvfspoof &= ~(1 << vf_target_shift);
2244
2245         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
2246 }
2247
2248 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning
2249  *  @hw: pointer to hardware structure
2250  *  @enable: enable or disable source address pruning
2251  *  @pool: Rx pool to set source address pruning for
2252  **/
2253 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw,
2254                                                   bool enable,
2255                                                   unsigned int pool)
2256 {
2257         u64 pfflp;
2258
2259         /* max rx pool is 63 */
2260         if (pool > 63)
2261                 return;
2262
2263         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
2264         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
2265
2266         if (enable)
2267                 pfflp |= (1ULL << pool);
2268         else
2269                 pfflp &= ~(1ULL << pool);
2270
2271         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
2272         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
2273 }
2274
2275 /**
2276  * ixgbe_set_mux - Set mux for port 1 access with CS4227
2277  * @hw: pointer to hardware structure
2278  * @state: set mux if 1, clear if 0
2279  */
2280 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2281 {
2282         u32 esdp;
2283
2284         if (!hw->bus.lan_id)
2285                 return;
2286         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2287         if (state)
2288                 esdp |= IXGBE_ESDP_SDP1;
2289         else
2290                 esdp &= ~IXGBE_ESDP_SDP1;
2291         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2292         IXGBE_WRITE_FLUSH(hw);
2293 }
2294
2295 /**
2296  * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2297  * @hw: pointer to hardware structure
2298  * @mask: Mask to specify which semaphore to acquire
2299  *
2300  * Acquires the SWFW semaphore and sets the I2C MUX
2301  */
2302 static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2303 {
2304         s32 status;
2305
2306         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2307         if (status)
2308                 return status;
2309
2310         if (mask & IXGBE_GSSR_I2C_MASK)
2311                 ixgbe_set_mux(hw, 1);
2312
2313         return 0;
2314 }
2315
2316 /**
2317  * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2318  * @hw: pointer to hardware structure
2319  * @mask: Mask to specify which semaphore to release
2320  *
2321  * Releases the SWFW semaphore and sets the I2C MUX
2322  */
2323 static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2324 {
2325         if (mask & IXGBE_GSSR_I2C_MASK)
2326                 ixgbe_set_mux(hw, 0);
2327
2328         ixgbe_release_swfw_sync_X540(hw, mask);
2329 }
2330
2331 #define X550_COMMON_MAC \
2332         .init_hw                        = &ixgbe_init_hw_generic, \
2333         .start_hw                       = &ixgbe_start_hw_X540, \
2334         .clear_hw_cntrs                 = &ixgbe_clear_hw_cntrs_generic, \
2335         .enable_rx_dma                  = &ixgbe_enable_rx_dma_generic, \
2336         .get_mac_addr                   = &ixgbe_get_mac_addr_generic, \
2337         .get_device_caps                = &ixgbe_get_device_caps_generic, \
2338         .stop_adapter                   = &ixgbe_stop_adapter_generic, \
2339         .set_lan_id                     = &ixgbe_set_lan_id_multi_port_pcie, \
2340         .read_analog_reg8               = NULL, \
2341         .write_analog_reg8              = NULL, \
2342         .set_rxpba                      = &ixgbe_set_rxpba_generic, \
2343         .check_link                     = &ixgbe_check_mac_link_generic, \
2344         .led_on                         = &ixgbe_led_on_generic, \
2345         .led_off                        = &ixgbe_led_off_generic, \
2346         .blink_led_start                = &ixgbe_blink_led_start_X540, \
2347         .blink_led_stop                 = &ixgbe_blink_led_stop_X540, \
2348         .set_rar                        = &ixgbe_set_rar_generic, \
2349         .clear_rar                      = &ixgbe_clear_rar_generic, \
2350         .set_vmdq                       = &ixgbe_set_vmdq_generic, \
2351         .set_vmdq_san_mac               = &ixgbe_set_vmdq_san_mac_generic, \
2352         .clear_vmdq                     = &ixgbe_clear_vmdq_generic, \
2353         .init_rx_addrs                  = &ixgbe_init_rx_addrs_generic, \
2354         .update_mc_addr_list            = &ixgbe_update_mc_addr_list_generic, \
2355         .enable_mc                      = &ixgbe_enable_mc_generic, \
2356         .disable_mc                     = &ixgbe_disable_mc_generic, \
2357         .clear_vfta                     = &ixgbe_clear_vfta_generic, \
2358         .set_vfta                       = &ixgbe_set_vfta_generic, \
2359         .fc_enable                      = &ixgbe_fc_enable_generic, \
2360         .set_fw_drv_ver                 = &ixgbe_set_fw_drv_ver_generic, \
2361         .init_uta_tables                = &ixgbe_init_uta_tables_generic, \
2362         .set_mac_anti_spoofing          = &ixgbe_set_mac_anti_spoofing, \
2363         .set_vlan_anti_spoofing         = &ixgbe_set_vlan_anti_spoofing, \
2364         .set_source_address_pruning     = \
2365                                 &ixgbe_set_source_address_pruning_X550, \
2366         .set_ethertype_anti_spoofing    = \
2367                                 &ixgbe_set_ethertype_anti_spoofing_X550, \
2368         .disable_rx_buff                = &ixgbe_disable_rx_buff_generic, \
2369         .enable_rx_buff                 = &ixgbe_enable_rx_buff_generic, \
2370         .get_thermal_sensor_data        = NULL, \
2371         .init_thermal_sensor_thresh     = NULL, \
2372         .prot_autoc_read                = &prot_autoc_read_generic, \
2373         .prot_autoc_write               = &prot_autoc_write_generic, \
2374         .enable_rx                      = &ixgbe_enable_rx_generic, \
2375         .disable_rx                     = &ixgbe_disable_rx_x550, \
2376
2377 static struct ixgbe_mac_operations mac_ops_X550 = {
2378         X550_COMMON_MAC
2379         .reset_hw               = &ixgbe_reset_hw_X540,
2380         .get_media_type         = &ixgbe_get_media_type_X540,
2381         .get_san_mac_addr       = &ixgbe_get_san_mac_addr_generic,
2382         .get_wwn_prefix         = &ixgbe_get_wwn_prefix_generic,
2383         .setup_link             = &ixgbe_setup_mac_link_X540,
2384         .get_link_capabilities  = &ixgbe_get_copper_link_capabilities_generic,
2385         .get_bus_info           = &ixgbe_get_bus_info_generic,
2386         .setup_sfp              = NULL,
2387         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X540,
2388         .release_swfw_sync      = &ixgbe_release_swfw_sync_X540,
2389 };
2390
2391 static struct ixgbe_mac_operations mac_ops_X550EM_x = {
2392         X550_COMMON_MAC
2393         .reset_hw               = &ixgbe_reset_hw_X550em,
2394         .get_media_type         = &ixgbe_get_media_type_X550em,
2395         .get_san_mac_addr       = NULL,
2396         .get_wwn_prefix         = NULL,
2397         .setup_link             = NULL, /* defined later */
2398         .get_link_capabilities  = &ixgbe_get_link_capabilities_X550em,
2399         .get_bus_info           = &ixgbe_get_bus_info_X550em,
2400         .setup_sfp              = ixgbe_setup_sfp_modules_X550em,
2401         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X550em,
2402         .release_swfw_sync      = &ixgbe_release_swfw_sync_X550em,
2403 };
2404
2405 #define X550_COMMON_EEP \
2406         .read                   = &ixgbe_read_ee_hostif_X550, \
2407         .read_buffer            = &ixgbe_read_ee_hostif_buffer_X550, \
2408         .write                  = &ixgbe_write_ee_hostif_X550, \
2409         .write_buffer           = &ixgbe_write_ee_hostif_buffer_X550, \
2410         .validate_checksum      = &ixgbe_validate_eeprom_checksum_X550, \
2411         .update_checksum        = &ixgbe_update_eeprom_checksum_X550, \
2412         .calc_checksum          = &ixgbe_calc_eeprom_checksum_X550, \
2413
2414 static struct ixgbe_eeprom_operations eeprom_ops_X550 = {
2415         X550_COMMON_EEP
2416         .init_params            = &ixgbe_init_eeprom_params_X550,
2417 };
2418
2419 static struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = {
2420         X550_COMMON_EEP
2421         .init_params            = &ixgbe_init_eeprom_params_X540,
2422 };
2423
2424 #define X550_COMMON_PHY \
2425         .identify_sfp           = &ixgbe_identify_module_generic, \
2426         .reset                  = NULL, \
2427         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic, \
2428         .read_i2c_byte          = &ixgbe_read_i2c_byte_generic, \
2429         .write_i2c_byte         = &ixgbe_write_i2c_byte_generic, \
2430         .read_i2c_sff8472       = &ixgbe_read_i2c_sff8472_generic, \
2431         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_generic, \
2432         .write_i2c_eeprom       = &ixgbe_write_i2c_eeprom_generic, \
2433         .read_reg               = &ixgbe_read_phy_reg_generic, \
2434         .write_reg              = &ixgbe_write_phy_reg_generic, \
2435         .setup_link             = &ixgbe_setup_phy_link_generic, \
2436         .set_phy_power          = NULL, \
2437         .check_overtemp         = &ixgbe_tn_check_overtemp, \
2438         .get_firmware_version   = &ixgbe_get_phy_firmware_version_generic,
2439
2440 static struct ixgbe_phy_operations phy_ops_X550 = {
2441         X550_COMMON_PHY
2442         .init                   = NULL,
2443         .identify               = &ixgbe_identify_phy_generic,
2444 };
2445
2446 static struct ixgbe_phy_operations phy_ops_X550EM_x = {
2447         X550_COMMON_PHY
2448         .init                   = &ixgbe_init_phy_ops_X550em,
2449         .identify               = &ixgbe_identify_phy_x550em,
2450         .read_i2c_combined      = &ixgbe_read_i2c_combined_generic,
2451         .write_i2c_combined     = &ixgbe_write_i2c_combined_generic,
2452         .read_i2c_combined_unlocked = &ixgbe_read_i2c_combined_generic_unlocked,
2453         .write_i2c_combined_unlocked =
2454                                      &ixgbe_write_i2c_combined_generic_unlocked,
2455 };
2456
2457 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
2458         IXGBE_MVALS_INIT(X550)
2459 };
2460
2461 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
2462         IXGBE_MVALS_INIT(X550EM_x)
2463 };
2464
2465 struct ixgbe_info ixgbe_X550_info = {
2466         .mac                    = ixgbe_mac_X550,
2467         .get_invariants         = &ixgbe_get_invariants_X540,
2468         .mac_ops                = &mac_ops_X550,
2469         .eeprom_ops             = &eeprom_ops_X550,
2470         .phy_ops                = &phy_ops_X550,
2471         .mbx_ops                = &mbx_ops_generic,
2472         .mvals                  = ixgbe_mvals_X550,
2473 };
2474
2475 struct ixgbe_info ixgbe_X550EM_x_info = {
2476         .mac                    = ixgbe_mac_X550EM_x,
2477         .get_invariants         = &ixgbe_get_invariants_X550_x,
2478         .mac_ops                = &mac_ops_X550EM_x,
2479         .eeprom_ops             = &eeprom_ops_X550EM_x,
2480         .phy_ops                = &phy_ops_X550EM_x,
2481         .mbx_ops                = &mbx_ops_generic,
2482         .mvals                  = ixgbe_mvals_X550EM_x,
2483 };