drivers/net/ethernet/mellanox/mlx4/en_rx.c

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #include <net/busy_poll.h>
  35 #include <linux/mlx4/cq.h>
  36 #include <linux/slab.h>
  37 #include <linux/mlx4/qp.h>
  38 #include <linux/skbuff.h>
  39 #include <linux/rculist.h>
  40 #include <linux/if_ether.h>
  41 #include <linux/if_vlan.h>
  42 #include <linux/vmalloc.h>
  43 #include <linux/irq.h>
  44
  45 #if IS_ENABLED(CONFIG_IPV6)
  46 #include <net/ip6_checksum.h>
  47 #endif
  48
  49 #include "mlx4_en.h"
  50
  51 static int mlx4_alloc_pages(struct mlx4_en_priv *priv,
  52                             struct mlx4_en_rx_alloc *page_alloc,
  53                             const struct mlx4_en_frag_info *frag_info,
  54                             gfp_t _gfp)
  55 {
  56         int order;
  57         struct page *page;
  58         dma_addr_t dma;
  59
  60         for (order = MLX4_EN_ALLOC_PREFER_ORDER; ;) {
  61                 gfp_t gfp = _gfp;
  62
  63                 if (order)
  64                         gfp |= __GFP_COMP | __GFP_NOWARN;
  65                 page = alloc_pages(gfp, order);
  66                 if (likely(page))
  67                         break;
  68                 if (--order < 0 ||
  69                     ((PAGE_SIZE << order) < frag_info->frag_size))
  70                         return -ENOMEM;
  71         }
  72         dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order,
  73                            PCI_DMA_FROMDEVICE);
  74         if (dma_mapping_error(priv->ddev, dma)) {
  75                 put_page(page);
  76                 return -ENOMEM;
  77         }
  78         page_alloc->page_size = PAGE_SIZE << order;
  79         page_alloc->page = page;
  80         page_alloc->dma = dma;
  81         page_alloc->page_offset = 0;
  82         /* Not doing get_page() for each frag is a big win
  83          * on asymetric workloads. Note we can not use atomic_set().
  84          */
  85         atomic_add(page_alloc->page_size / frag_info->frag_stride - 1,
  86                    &page->_count);
  87         return 0;
  88 }
  89
  90 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,
  91                                struct mlx4_en_rx_desc *rx_desc,
  92                                struct mlx4_en_rx_alloc *frags,
  93                                struct mlx4_en_rx_alloc *ring_alloc,
  94                                gfp_t gfp)
  95 {
  96         struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
  97         const struct mlx4_en_frag_info *frag_info;
  98         struct page *page;
  99         dma_addr_t dma;
 100         int i;
 101
 102         for (i = 0; i < priv->num_frags; i++) {
 103                 frag_info = &priv->frag_info[i];
 104                 page_alloc[i] = ring_alloc[i];
 105                 page_alloc[i].page_offset += frag_info->frag_stride;
 106
 107                 if (page_alloc[i].page_offset + frag_info->frag_stride <=
 108                     ring_alloc[i].page_size)
 109                         continue;
 110
 111                 if (mlx4_alloc_pages(priv, &page_alloc[i], frag_info, gfp))
 112                         goto out;
 113         }
 114
 115         for (i = 0; i < priv->num_frags; i++) {
 116                 frags[i] = ring_alloc[i];
 117                 dma = ring_alloc[i].dma + ring_alloc[i].page_offset;
 118                 ring_alloc[i] = page_alloc[i];
 119                 rx_desc->data[i].addr = cpu_to_be64(dma);
 120         }
 121
 122         return 0;
 123
 124 out:
 125         while (i--) {
 126                 if (page_alloc[i].page != ring_alloc[i].page) {
 127                         dma_unmap_page(priv->ddev, page_alloc[i].dma,
 128                                 page_alloc[i].page_size, PCI_DMA_FROMDEVICE);
 129                         page = page_alloc[i].page;
 130                         atomic_set(&page->_count, 1);
 131                         put_page(page);
 132                 }
 133         }
 134         return -ENOMEM;
 135 }
 136
 137 static void mlx4_en_free_frag(struct mlx4_en_priv *priv,
 138                               struct mlx4_en_rx_alloc *frags,
 139                               int i)
 140 {
 141         const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 142         u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride;
 143
 144
 145         if (next_frag_end > frags[i].page_size)
 146                 dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size,
 147                                PCI_DMA_FROMDEVICE);
 148
 149         if (frags[i].page)
 150                 put_page(frags[i].page);
 151 }
 152
 153 static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
 154                                   struct mlx4_en_rx_ring *ring)
 155 {
 156         int i;
 157         struct mlx4_en_rx_alloc *page_alloc;
 158
 159         for (i = 0; i < priv->num_frags; i++) {
 160                 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 161
 162                 if (mlx4_alloc_pages(priv, &ring->page_alloc[i],
 163                                      frag_info, GFP_KERNEL | __GFP_COLD))
 164                         goto out;
 165
 166                 en_dbg(DRV, priv, "  frag %d allocator: - size:%d frags:%d\n",
 167                        i, ring->page_alloc[i].page_size,
 168                        atomic_read(&ring->page_alloc[i].page->_count));
 169         }
 170         return 0;
 171
 172 out:
 173         while (i--) {
 174                 struct page *page;
 175
 176                 page_alloc = &ring->page_alloc[i];
 177                 dma_unmap_page(priv->ddev, page_alloc->dma,
 178                                page_alloc->page_size, PCI_DMA_FROMDEVICE);
 179                 page = page_alloc->page;
 180                 atomic_set(&page->_count, 1);
 181                 put_page(page);
 182                 page_alloc->page = NULL;
 183         }
 184         return -ENOMEM;
 185 }
 186
 187 static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
 188                                       struct mlx4_en_rx_ring *ring)
 189 {
 190         struct mlx4_en_rx_alloc *page_alloc;
 191         int i;
 192
 193         for (i = 0; i < priv->num_frags; i++) {
 194                 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 195
 196                 page_alloc = &ring->page_alloc[i];
 197                 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
 198                        i, page_count(page_alloc->page));
 199
 200                 dma_unmap_page(priv->ddev, page_alloc->dma,
 201                                 page_alloc->page_size, PCI_DMA_FROMDEVICE);
 202                 while (page_alloc->page_offset + frag_info->frag_stride <
 203                        page_alloc->page_size) {
 204                         put_page(page_alloc->page);
 205                         page_alloc->page_offset += frag_info->frag_stride;
 206                 }
 207                 page_alloc->page = NULL;
 208         }
 209 }
 210
 211 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
 212                                  struct mlx4_en_rx_ring *ring, int index)
 213 {
 214         struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
 215         int possible_frags;
 216         int i;
 217
 218         /* Set size and memtype fields */
 219         for (i = 0; i < priv->num_frags; i++) {
 220                 rx_desc->data[i].byte_count =
 221                         cpu_to_be32(priv->frag_info[i].frag_size);
 222                 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
 223         }
 224
 225         /* If the number of used fragments does not fill up the ring stride,
 226          * remaining (unused) fragments must be padded with null address/size
 227          * and a special memory key */
 228         possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
 229         for (i = priv->num_frags; i < possible_frags; i++) {
 230                 rx_desc->data[i].byte_count = 0;
 231                 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
 232                 rx_desc->data[i].addr = 0;
 233         }
 234 }
 235
 236 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
 237                                    struct mlx4_en_rx_ring *ring, int index,
 238                                    gfp_t gfp)
 239 {
 240         struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
 241         struct mlx4_en_rx_alloc *frags = ring->rx_info +
 242                                         (index << priv->log_rx_info);
 243
 244         return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp);
 245 }
 246
 247 static inline bool mlx4_en_is_ring_empty(struct mlx4_en_rx_ring *ring)
 248 {
 249         return ring->prod == ring->cons;
 250 }
 251
 252 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
 253 {
 254         *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
 255 }
 256
 257 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
 258                                  struct mlx4_en_rx_ring *ring,
 259                                  int index)
 260 {
 261         struct mlx4_en_rx_alloc *frags;
 262         int nr;
 263
 264         frags = ring->rx_info + (index << priv->log_rx_info);
 265         for (nr = 0; nr < priv->num_frags; nr++) {
 266                 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
 267                 mlx4_en_free_frag(priv, frags, nr);
 268         }
 269 }
 270
 271 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
 272 {
 273         struct mlx4_en_rx_ring *ring;
 274         int ring_ind;
 275         int buf_ind;
 276         int new_size;
 277
 278         for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
 279                 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 280                         ring = priv->rx_ring[ring_ind];
 281
 282                         if (mlx4_en_prepare_rx_desc(priv, ring,
 283                                                     ring->actual_size,
 284                                                     GFP_KERNEL | __GFP_COLD)) {
 285                                 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
 286                                         en_err(priv, "Failed to allocate enough rx buffers\n");
 287                                         return -ENOMEM;
 288                                 } else {
 289                                         new_size = rounddown_pow_of_two(ring->actual_size);
 290                                         en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n",
 291                                                 ring->actual_size, new_size);
 292                                         goto reduce_rings;
 293                                 }
 294                         }
 295                         ring->actual_size++;
 296                         ring->prod++;
 297                 }
 298         }
 299         return 0;
 300
 301 reduce_rings:
 302         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 303                 ring = priv->rx_ring[ring_ind];
 304                 while (ring->actual_size > new_size) {
 305                         ring->actual_size--;
 306                         ring->prod--;
 307                         mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
 308                 }
 309         }
 310
 311         return 0;
 312 }
 313
 314 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
 315                                 struct mlx4_en_rx_ring *ring)
 316 {
 317         int index;
 318
 319         en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
 320                ring->cons, ring->prod);
 321
 322         /* Unmap and free Rx buffers */
 323         while (!mlx4_en_is_ring_empty(ring)) {
 324                 index = ring->cons & ring->size_mask;
 325                 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
 326                 mlx4_en_free_rx_desc(priv, ring, index);
 327                 ++ring->cons;
 328         }
 329 }
 330
 331 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev)
 332 {
 333         int i;
 334         int num_of_eqs;
 335         int num_rx_rings;
 336         struct mlx4_dev *dev = mdev->dev;
 337
 338         mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
 339                 num_of_eqs = max_t(int, MIN_RX_RINGS,
 340                                    min_t(int,
 341                                          mlx4_get_eqs_per_port(mdev->dev, i),
 342                                          DEF_RX_RINGS));
 343
 344                 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS :
 345                         min_t(int, num_of_eqs,
 346                               netif_get_num_default_rss_queues());
 347                 mdev->profile.prof[i].rx_ring_num =
 348                         rounddown_pow_of_two(num_rx_rings);
 349         }
 350 }
 351
 352 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 353                            struct mlx4_en_rx_ring **pring,
 354                            u32 size, u16 stride, int node)
 355 {
 356         struct mlx4_en_dev *mdev = priv->mdev;
 357         struct mlx4_en_rx_ring *ring;
 358         int err = -ENOMEM;
 359         int tmp;
 360
 361         ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
 362         if (!ring) {
 363                 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 364                 if (!ring) {
 365                         en_err(priv, "Failed to allocate RX ring structure\n");
 366                         return -ENOMEM;
 367                 }
 368         }
 369
 370         ring->prod = 0;
 371         ring->cons = 0;
 372         ring->size = size;
 373         ring->size_mask = size - 1;
 374         ring->stride = stride;
 375         ring->log_stride = ffs(ring->stride) - 1;
 376         ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
 377
 378         tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
 379                                         sizeof(struct mlx4_en_rx_alloc));
 380         ring->rx_info = vmalloc_node(tmp, node);
 381         if (!ring->rx_info) {
 382                 ring->rx_info = vmalloc(tmp);
 383                 if (!ring->rx_info) {
 384                         err = -ENOMEM;
 385                         goto err_ring;
 386                 }
 387         }
 388
 389         en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
 390                  ring->rx_info, tmp);
 391
 392         /* Allocate HW buffers on provided NUMA node */
 393         set_dev_node(&mdev->dev->persist->pdev->dev, node);
 394         err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
 395                                  ring->buf_size, 2 * PAGE_SIZE);
 396         set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
 397         if (err)
 398                 goto err_info;
 399
 400         err = mlx4_en_map_buffer(&ring->wqres.buf);
 401         if (err) {
 402                 en_err(priv, "Failed to map RX buffer\n");
 403                 goto err_hwq;
 404         }
 405         ring->buf = ring->wqres.buf.direct.buf;
 406
 407         ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter;
 408
 409         *pring = ring;
 410         return 0;
 411
 412 err_hwq:
 413         mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
 414 err_info:
 415         vfree(ring->rx_info);
 416         ring->rx_info = NULL;
 417 err_ring:
 418         kfree(ring);
 419         *pring = NULL;
 420
 421         return err;
 422 }
 423
 424 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
 425 {
 426         struct mlx4_en_rx_ring *ring;
 427         int i;
 428         int ring_ind;
 429         int err;
 430         int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
 431                                         DS_SIZE * priv->num_frags);
 432
 433         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 434                 ring = priv->rx_ring[ring_ind];
 435
 436                 ring->prod = 0;
 437                 ring->cons = 0;
 438                 ring->actual_size = 0;
 439                 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn;
 440
 441                 ring->stride = stride;
 442                 if (ring->stride <= TXBB_SIZE)
 443                         ring->buf += TXBB_SIZE;
 444
 445                 ring->log_stride = ffs(ring->stride) - 1;
 446                 ring->buf_size = ring->size * ring->stride;
 447
 448                 memset(ring->buf, 0, ring->buf_size);
 449                 mlx4_en_update_rx_prod_db(ring);
 450
 451                 /* Initialize all descriptors */
 452                 for (i = 0; i < ring->size; i++)
 453                         mlx4_en_init_rx_desc(priv, ring, i);
 454
 455                 /* Initialize page allocators */
 456                 err = mlx4_en_init_allocator(priv, ring);
 457                 if (err) {
 458                         en_err(priv, "Failed initializing ring allocator\n");
 459                         if (ring->stride <= TXBB_SIZE)
 460                                 ring->buf -= TXBB_SIZE;
 461                         ring_ind--;
 462                         goto err_allocator;
 463                 }
 464         }
 465         err = mlx4_en_fill_rx_buffers(priv);
 466         if (err)
 467                 goto err_buffers;
 468
 469         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 470                 ring = priv->rx_ring[ring_ind];
 471
 472                 ring->size_mask = ring->actual_size - 1;
 473                 mlx4_en_update_rx_prod_db(ring);
 474         }
 475
 476         return 0;
 477
 478 err_buffers:
 479         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
 480                 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]);
 481
 482         ring_ind = priv->rx_ring_num - 1;
 483 err_allocator:
 484         while (ring_ind >= 0) {
 485                 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE)
 486                         priv->rx_ring[ring_ind]->buf -= TXBB_SIZE;
 487                 mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]);
 488                 ring_ind--;
 489         }
 490         return err;
 491 }
 492
 493 /* We recover from out of memory by scheduling our napi poll
 494  * function (mlx4_en_process_cq), which tries to allocate
 495  * all missing RX buffers (call to mlx4_en_refill_rx_buffers).
 496  */
 497 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv)
 498 {
 499         int ring;
 500
 501         if (!priv->port_up)
 502                 return;
 503
 504         for (ring = 0; ring < priv->rx_ring_num; ring++) {
 505                 if (mlx4_en_is_ring_empty(priv->rx_ring[ring]))
 506                         napi_reschedule(&priv->rx_cq[ring]->napi);
 507         }
 508 }
 509
 510 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 511                              struct mlx4_en_rx_ring **pring,
 512                              u32 size, u16 stride)
 513 {
 514         struct mlx4_en_dev *mdev = priv->mdev;
 515         struct mlx4_en_rx_ring *ring = *pring;
 516
 517         mlx4_en_unmap_buffer(&ring->wqres.buf);
 518         mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
 519         vfree(ring->rx_info);
 520         ring->rx_info = NULL;
 521         kfree(ring);
 522         *pring = NULL;
 523 #ifdef CONFIG_RFS_ACCEL
 524         mlx4_en_cleanup_filters(priv);
 525 #endif
 526 }
 527
 528 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 529                                 struct mlx4_en_rx_ring *ring)
 530 {
 531         mlx4_en_free_rx_buf(priv, ring);
 532         if (ring->stride <= TXBB_SIZE)
 533                 ring->buf -= TXBB_SIZE;
 534         mlx4_en_destroy_allocator(priv, ring);
 535 }
 536
 537
 538 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
 539                                     struct mlx4_en_rx_desc *rx_desc,
 540                                     struct mlx4_en_rx_alloc *frags,
 541                                     struct sk_buff *skb,
 542                                     int length)
 543 {
 544         struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags;
 545         struct mlx4_en_frag_info *frag_info;
 546         int nr;
 547         dma_addr_t dma;
 548
 549         /* Collect used fragments while replacing them in the HW descriptors */
 550         for (nr = 0; nr < priv->num_frags; nr++) {
 551                 frag_info = &priv->frag_info[nr];
 552                 if (length <= frag_info->frag_prefix_size)
 553                         break;
 554                 if (!frags[nr].page)
 555                         goto fail;
 556
 557                 dma = be64_to_cpu(rx_desc->data[nr].addr);
 558                 dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size,
 559                                         DMA_FROM_DEVICE);
 560
 561                 /* Save page reference in skb */
 562                 __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page);
 563                 skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size);
 564                 skb_frags_rx[nr].page_offset = frags[nr].page_offset;
 565                 skb->truesize += frag_info->frag_stride;
 566                 frags[nr].page = NULL;
 567         }
 568         /* Adjust size of last fragment to match actual length */
 569         if (nr > 0)
 570                 skb_frag_size_set(&skb_frags_rx[nr - 1],
 571                         length - priv->frag_info[nr - 1].frag_prefix_size);
 572         return nr;
 573
 574 fail:
 575         while (nr > 0) {
 576                 nr--;
 577                 __skb_frag_unref(&skb_frags_rx[nr]);
 578         }
 579         return 0;
 580 }
 581
 582
 583 static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
 584                                       struct mlx4_en_rx_desc *rx_desc,
 585                                       struct mlx4_en_rx_alloc *frags,
 586                                       unsigned int length)
 587 {
 588         struct sk_buff *skb;
 589         void *va;
 590         int used_frags;
 591         dma_addr_t dma;
 592
 593         skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN);
 594         if (!skb) {
 595                 en_dbg(RX_ERR, priv, "Failed allocating skb\n");
 596                 return NULL;
 597         }
 598         skb_reserve(skb, NET_IP_ALIGN);
 599         skb->len = length;
 600
 601         /* Get pointer to first fragment so we could copy the headers into the
 602          * (linear part of the) skb */
 603         va = page_address(frags[0].page) + frags[0].page_offset;
 604
 605         if (length <= SMALL_PACKET_SIZE) {
 606                 /* We are copying all relevant data to the skb - temporarily
 607                  * sync buffers for the copy */
 608                 dma = be64_to_cpu(rx_desc->data[0].addr);
 609                 dma_sync_single_for_cpu(priv->ddev, dma, length,
 610                                         DMA_FROM_DEVICE);
 611                 skb_copy_to_linear_data(skb, va, length);
 612                 skb->tail += length;
 613         } else {
 614                 unsigned int pull_len;
 615
 616                 /* Move relevant fragments to skb */
 617                 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags,
 618                                                         skb, length);
 619                 if (unlikely(!used_frags)) {
 620                         kfree_skb(skb);
 621                         return NULL;
 622                 }
 623                 skb_shinfo(skb)->nr_frags = used_frags;
 624
 625                 pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE);
 626                 /* Copy headers into the skb linear buffer */
 627                 memcpy(skb->data, va, pull_len);
 628                 skb->tail += pull_len;
 629
 630                 /* Skip headers in first fragment */
 631                 skb_shinfo(skb)->frags[0].page_offset += pull_len;
 632
 633                 /* Adjust size of first fragment */
 634                 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len);
 635                 skb->data_len = length - pull_len;
 636         }
 637         return skb;
 638 }
 639
 640 static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
 641 {
 642         int i;
 643         int offset = ETH_HLEN;
 644
 645         for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
 646                 if (*(skb->data + offset) != (unsigned char) (i & 0xff))
 647                         goto out_loopback;
 648         }
 649         /* Loopback found */
 650         priv->loopback_ok = 1;
 651
 652 out_loopback:
 653         dev_kfree_skb_any(skb);
 654 }
 655
 656 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,
 657                                      struct mlx4_en_rx_ring *ring)
 658 {
 659         int index = ring->prod & ring->size_mask;
 660
 661         while ((u32) (ring->prod - ring->cons) < ring->actual_size) {
 662                 if (mlx4_en_prepare_rx_desc(priv, ring, index,
 663                                             GFP_ATOMIC | __GFP_COLD))
 664                         break;
 665                 ring->prod++;
 666                 index = ring->prod & ring->size_mask;
 667         }
 668 }
 669
 670 /* When hardware doesn't strip the vlan, we need to calculate the checksum
 671  * over it and add it to the hardware's checksum calculation
 672  */
 673 static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum,
 674                                          struct vlan_hdr *vlanh)
 675 {
 676         return csum_add(hw_checksum, *(__wsum *)vlanh);
 677 }
 678
 679 /* Although the stack expects checksum which doesn't include the pseudo
 680  * header, the HW adds it. To address that, we are subtracting the pseudo
 681  * header checksum from the checksum value provided by the HW.
 682  */
 683 static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb,
 684                                 struct iphdr *iph)
 685 {
 686         __u16 length_for_csum = 0;
 687         __wsum csum_pseudo_header = 0;
 688
 689         length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2));
 690         csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr,
 691                                                 length_for_csum, iph->protocol, 0);
 692         skb->csum = csum_sub(hw_checksum, csum_pseudo_header);
 693 }
 694
 695 #if IS_ENABLED(CONFIG_IPV6)
 696 /* In IPv6 packets, besides subtracting the pseudo header checksum,
 697  * we also compute/add the IP header checksum which
 698  * is not added by the HW.
 699  */
 700 static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb,
 701                                struct ipv6hdr *ipv6h)
 702 {
 703         __wsum csum_pseudo_hdr = 0;
 704
 705         if (ipv6h->nexthdr == IPPROTO_FRAGMENT || ipv6h->nexthdr == IPPROTO_HOPOPTS)
 706                 return -1;
 707         hw_checksum = csum_add(hw_checksum, (__force __wsum)(ipv6h->nexthdr << 8));
 708
 709         csum_pseudo_hdr = csum_partial(&ipv6h->saddr,
 710                                        sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0);
 711         csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len);
 712         csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ntohs(ipv6h->nexthdr));
 713
 714         skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr);
 715         skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0));
 716         return 0;
 717 }
 718 #endif
 719 static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va,
 720                       netdev_features_t dev_features)
 721 {
 722         __wsum hw_checksum = 0;
 723
 724         void *hdr = (u8 *)va + sizeof(struct ethhdr);
 725
 726         hw_checksum = csum_unfold((__force __sum16)cqe->checksum);
 727
 728         if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) &&
 729             !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) {
 730                 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr);
 731                 hdr += sizeof(struct vlan_hdr);
 732         }
 733
 734         if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4))
 735                 get_fixed_ipv4_csum(hw_checksum, skb, hdr);
 736 #if IS_ENABLED(CONFIG_IPV6)
 737         else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6))
 738                 if (get_fixed_ipv6_csum(hw_checksum, skb, hdr))
 739                         return -1;
 740 #endif
 741         return 0;
 742 }
 743
 744 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
 745 {
 746         struct mlx4_en_priv *priv = netdev_priv(dev);
 747         struct mlx4_en_dev *mdev = priv->mdev;
 748         struct mlx4_cqe *cqe;
 749         struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring];
 750         struct mlx4_en_rx_alloc *frags;
 751         struct mlx4_en_rx_desc *rx_desc;
 752         struct sk_buff *skb;
 753         int index;
 754         int nr;
 755         unsigned int length;
 756         int polled = 0;
 757         int ip_summed;
 758         int factor = priv->cqe_factor;
 759         u64 timestamp;
 760         bool l2_tunnel;
 761
 762         if (!priv->port_up)
 763                 return 0;
 764
 765         if (budget <= 0)
 766                 return polled;
 767
 768         /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
 769          * descriptor offset can be deduced from the CQE index instead of
 770          * reading 'cqe->index' */
 771         index = cq->mcq.cons_index & ring->size_mask;
 772         cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
 773
 774         /* Process all completed CQEs */
 775         while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
 776                     cq->mcq.cons_index & cq->size)) {
 777
 778                 frags = ring->rx_info + (index << priv->log_rx_info);
 779                 rx_desc = ring->buf + (index << ring->log_stride);
 780
 781                 /*
 782                  * make sure we read the CQE after we read the ownership bit
 783                  */
 784                 dma_rmb();
 785
 786                 /* Drop packet on bad receive or bad checksum */
 787                 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 788                                                 MLX4_CQE_OPCODE_ERROR)) {
 789                         en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n",
 790                                ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome,
 791                                ((struct mlx4_err_cqe *)cqe)->syndrome);
 792                         goto next;
 793                 }
 794                 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
 795                         en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
 796                         goto next;
 797                 }
 798
 799                 /* Check if we need to drop the packet if SRIOV is not enabled
 800                  * and not performing the selftest or flb disabled
 801                  */
 802                 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {
 803                         struct ethhdr *ethh;
 804                         dma_addr_t dma;
 805                         /* Get pointer to first fragment since we haven't
 806                          * skb yet and cast it to ethhdr struct
 807                          */
 808                         dma = be64_to_cpu(rx_desc->data[0].addr);
 809                         dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),
 810                                                 DMA_FROM_DEVICE);
 811                         ethh = (struct ethhdr *)(page_address(frags[0].page) +
 812                                                  frags[0].page_offset);
 813
 814                         if (is_multicast_ether_addr(ethh->h_dest)) {
 815                                 struct mlx4_mac_entry *entry;
 816                                 struct hlist_head *bucket;
 817                                 unsigned int mac_hash;
 818
 819                                 /* Drop the packet, since HW loopback-ed it */
 820                                 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];
 821                                 bucket = &priv->mac_hash[mac_hash];
 822                                 rcu_read_lock();
 823                                 hlist_for_each_entry_rcu(entry, bucket, hlist) {
 824                                         if (ether_addr_equal_64bits(entry->mac,
 825                                                                     ethh->h_source)) {
 826                                                 rcu_read_unlock();
 827                                                 goto next;
 828                                         }
 829                                 }
 830                                 rcu_read_unlock();
 831                         }
 832                 }
 833
 834                 /*
 835                  * Packet is OK - process it.
 836                  */
 837                 length = be32_to_cpu(cqe->byte_cnt);
 838                 length -= ring->fcs_del;
 839                 ring->bytes += length;
 840                 ring->packets++;
 841                 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) &&
 842                         (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL));
 843
 844                 if (likely(dev->features & NETIF_F_RXCSUM)) {
 845                         if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP |
 846                                                       MLX4_CQE_STATUS_UDP)) {
 847                                 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
 848                                     cqe->checksum == cpu_to_be16(0xffff)) {
 849                                         ip_summed = CHECKSUM_UNNECESSARY;
 850                                         ring->csum_ok++;
 851                                 } else {
 852                                         ip_summed = CHECKSUM_NONE;
 853                                         ring->csum_none++;
 854                                 }
 855                         } else {
 856                                 if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP &&
 857                                     (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
 858                                                                MLX4_CQE_STATUS_IPV6))) {
 859                                         ip_summed = CHECKSUM_COMPLETE;
 860                                         ring->csum_complete++;
 861                                 } else {
 862                                         ip_summed = CHECKSUM_NONE;
 863                                         ring->csum_none++;
 864                                 }
 865                         }
 866                 } else {
 867                         ip_summed = CHECKSUM_NONE;
 868                         ring->csum_none++;
 869                 }
 870
 871                 /* This packet is eligible for GRO if it is:
 872                  * - DIX Ethernet (type interpretation)
 873                  * - TCP/IP (v4)
 874                  * - without IP options
 875                  * - not an IP fragment
 876                  * - no LLS polling in progress
 877                  */
 878                 if (!mlx4_en_cq_busy_polling(cq) &&
 879                     (dev->features & NETIF_F_GRO)) {
 880                         struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
 881                         if (!gro_skb)
 882                                 goto next;
 883
 884                         nr = mlx4_en_complete_rx_desc(priv,
 885                                 rx_desc, frags, gro_skb,
 886                                 length);
 887                         if (!nr)
 888                                 goto next;
 889
 890                         if (ip_summed == CHECKSUM_COMPLETE) {
 891                                 void *va = skb_frag_address(skb_shinfo(gro_skb)->frags);
 892                                 if (check_csum(cqe, gro_skb, va,
 893                                                dev->features)) {
 894                                         ip_summed = CHECKSUM_NONE;
 895                                         ring->csum_none++;
 896                                         ring->csum_complete--;
 897                                 }
 898                         }
 899
 900                         skb_shinfo(gro_skb)->nr_frags = nr;
 901                         gro_skb->len = length;
 902                         gro_skb->data_len = length;
 903                         gro_skb->ip_summed = ip_summed;
 904
 905                         if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
 906                                 gro_skb->csum_level = 1;
 907
 908                         if ((cqe->vlan_my_qpn &
 909                             cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) &&
 910                             (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
 911                                 u16 vid = be16_to_cpu(cqe->sl_vid);
 912
 913                                 __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid);
 914                         } else if ((be32_to_cpu(cqe->vlan_my_qpn) &
 915                                   MLX4_CQE_SVLAN_PRESENT_MASK) &&
 916                                  (dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
 917                                 __vlan_hwaccel_put_tag(gro_skb,
 918                                                        htons(ETH_P_8021AD),
 919                                                        be16_to_cpu(cqe->sl_vid));
 920                         }
 921
 922                         if (dev->features & NETIF_F_RXHASH)
 923                                 skb_set_hash(gro_skb,
 924                                              be32_to_cpu(cqe->immed_rss_invalid),
 925                                              (ip_summed == CHECKSUM_UNNECESSARY) ?
 926                                                 PKT_HASH_TYPE_L4 :
 927                                                 PKT_HASH_TYPE_L3);
 928
 929                         skb_record_rx_queue(gro_skb, cq->ring);
 930                         skb_mark_napi_id(gro_skb, &cq->napi);
 931
 932                         if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
 933                                 timestamp = mlx4_en_get_cqe_ts(cqe);
 934                                 mlx4_en_fill_hwtstamps(mdev,
 935                                                        skb_hwtstamps(gro_skb),
 936                                                        timestamp);
 937                         }
 938
 939                         napi_gro_frags(&cq->napi);
 940                         goto next;
 941                 }
 942
 943                 /* GRO not possible, complete processing here */
 944                 skb = mlx4_en_rx_skb(priv, rx_desc, frags, length);
 945                 if (!skb) {
 946                         priv->stats.rx_dropped++;
 947                         goto next;
 948                 }
 949
 950                 if (unlikely(priv->validate_loopback)) {
 951                         validate_loopback(priv, skb);
 952                         goto next;
 953                 }
 954
 955                 if (ip_summed == CHECKSUM_COMPLETE) {
 956                         if (check_csum(cqe, skb, skb->data, dev->features)) {
 957                                 ip_summed = CHECKSUM_NONE;
 958                                 ring->csum_complete--;
 959                                 ring->csum_none++;
 960                         }
 961                 }
 962
 963                 skb->ip_summed = ip_summed;
 964                 skb->protocol = eth_type_trans(skb, dev);
 965                 skb_record_rx_queue(skb, cq->ring);
 966
 967                 if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
 968                         skb->csum_level = 1;
 969
 970                 if (dev->features & NETIF_F_RXHASH)
 971                         skb_set_hash(skb,
 972                                      be32_to_cpu(cqe->immed_rss_invalid),
 973                                      (ip_summed == CHECKSUM_UNNECESSARY) ?
 974                                         PKT_HASH_TYPE_L4 :
 975                                         PKT_HASH_TYPE_L3);
 976
 977                 if ((be32_to_cpu(cqe->vlan_my_qpn) &
 978                     MLX4_CQE_CVLAN_PRESENT_MASK) &&
 979                     (dev->features & NETIF_F_HW_VLAN_CTAG_RX))
 980                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid));
 981                 else if ((be32_to_cpu(cqe->vlan_my_qpn) &
 982                           MLX4_CQE_SVLAN_PRESENT_MASK) &&
 983                          (dev->features & NETIF_F_HW_VLAN_STAG_RX))
 984                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD),
 985                                                be16_to_cpu(cqe->sl_vid));
 986
 987                 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
 988                         timestamp = mlx4_en_get_cqe_ts(cqe);
 989                         mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb),
 990                                                timestamp);
 991                 }
 992
 993                 skb_mark_napi_id(skb, &cq->napi);
 994
 995                 if (!mlx4_en_cq_busy_polling(cq))
 996                         napi_gro_receive(&cq->napi, skb);
 997                 else
 998                         netif_receive_skb(skb);
 999
1000 next:
1001                 for (nr = 0; nr < priv->num_frags; nr++)
1002                         mlx4_en_free_frag(priv, frags, nr);
1003
1004                 ++cq->mcq.cons_index;
1005                 index = (cq->mcq.cons_index) & ring->size_mask;
1006                 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
1007                 if (++polled == budget)
1008                         goto out;
1009         }
1010
1011 out:
1012         AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
1013         mlx4_cq_set_ci(&cq->mcq);
1014         wmb(); /* ensure HW sees CQ consumer before we post new buffers */
1015         ring->cons = cq->mcq.cons_index;
1016         mlx4_en_refill_rx_buffers(priv, ring);
1017         mlx4_en_update_rx_prod_db(ring);
1018         return polled;
1019 }
1020
1021
1022 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
1023 {
1024         struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
1025         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
1026
1027         if (likely(priv->port_up))
1028                 napi_schedule_irqoff(&cq->napi);
1029         else
1030                 mlx4_en_arm_cq(priv, cq);
1031 }
1032
1033 /* Rx CQ polling - called by NAPI */
1034 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
1035 {
1036         struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
1037         struct net_device *dev = cq->dev;
1038         struct mlx4_en_priv *priv = netdev_priv(dev);
1039         int done;
1040
1041         if (!mlx4_en_cq_lock_napi(cq))
1042                 return budget;
1043
1044         done = mlx4_en_process_rx_cq(dev, cq, budget);
1045
1046         mlx4_en_cq_unlock_napi(cq);
1047
1048         /* If we used up all the quota - we're probably not done yet... */
1049         if (done == budget) {
1050                 const struct cpumask *aff;
1051                 struct irq_data *idata;
1052                 int cpu_curr;
1053
1054                 INC_PERF_COUNTER(priv->pstats.napi_quota);
1055
1056                 cpu_curr = smp_processor_id();
1057                 idata = irq_desc_get_irq_data(cq->irq_desc);
1058                 aff = irq_data_get_affinity_mask(idata);
1059
1060                 if (likely(cpumask_test_cpu(cpu_curr, aff)))
1061                         return budget;
1062
1063                 /* Current cpu is not according to smp_irq_affinity -
1064                  * probably affinity changed. need to stop this NAPI
1065                  * poll, and restart it on the right CPU
1066                  */
1067                 done = 0;
1068         }
1069         /* Done for now */
1070         napi_complete_done(napi, done);
1071         mlx4_en_arm_cq(priv, cq);
1072         return done;
1073 }
1074
1075 static const int frag_sizes[] = {
1076         FRAG_SZ0,
1077         FRAG_SZ1,
1078         FRAG_SZ2,
1079         FRAG_SZ3
1080 };
1081
1082 void mlx4_en_calc_rx_buf(struct net_device *dev)
1083 {
1084         struct mlx4_en_priv *priv = netdev_priv(dev);
1085         /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple
1086          * headers. (For example: ETH_P_8021Q and ETH_P_8021AD).
1087          */
1088         int eff_mtu = dev->mtu + ETH_HLEN + (2 * VLAN_HLEN);
1089         int buf_size = 0;
1090         int i = 0;
1091
1092         while (buf_size < eff_mtu) {
1093                 priv->frag_info[i].frag_size =
1094                         (eff_mtu > buf_size + frag_sizes[i]) ?
1095                                 frag_sizes[i] : eff_mtu - buf_size;
1096                 priv->frag_info[i].frag_prefix_size = buf_size;
1097                 priv->frag_info[i].frag_stride =
1098                                 ALIGN(priv->frag_info[i].frag_size,
1099                                       SMP_CACHE_BYTES);
1100                 buf_size += priv->frag_info[i].frag_size;
1101                 i++;
1102         }
1103
1104         priv->num_frags = i;
1105         priv->rx_skb_size = eff_mtu;
1106         priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));
1107
1108         en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n",
1109                eff_mtu, priv->num_frags);
1110         for (i = 0; i < priv->num_frags; i++) {
1111                 en_err(priv,
1112                        "  frag:%d - size:%d prefix:%d stride:%d\n",
1113                        i,
1114                        priv->frag_info[i].frag_size,
1115                        priv->frag_info[i].frag_prefix_size,
1116                        priv->frag_info[i].frag_stride);
1117         }
1118 }
1119
1120 /* RSS related functions */
1121
1122 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
1123                                  struct mlx4_en_rx_ring *ring,
1124                                  enum mlx4_qp_state *state,
1125                                  struct mlx4_qp *qp)
1126 {
1127         struct mlx4_en_dev *mdev = priv->mdev;
1128         struct mlx4_qp_context *context;
1129         int err = 0;
1130
1131         context = kmalloc(sizeof(*context), GFP_KERNEL);
1132         if (!context)
1133                 return -ENOMEM;
1134
1135         err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL);
1136         if (err) {
1137                 en_err(priv, "Failed to allocate qp #%x\n", qpn);
1138                 goto out;
1139         }
1140         qp->event = mlx4_en_sqp_event;
1141
1142         memset(context, 0, sizeof *context);
1143         mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
1144                                 qpn, ring->cqn, -1, context);
1145         context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
1146
1147         /* Cancel FCS removal if FW allows */
1148         if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
1149                 context->param3 |= cpu_to_be32(1 << 29);
1150                 if (priv->dev->features & NETIF_F_RXFCS)
1151                         ring->fcs_del = 0;
1152                 else
1153                         ring->fcs_del = ETH_FCS_LEN;
1154         } else
1155                 ring->fcs_del = 0;
1156
1157         err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
1158         if (err) {
1159                 mlx4_qp_remove(mdev->dev, qp);
1160                 mlx4_qp_free(mdev->dev, qp);
1161         }
1162         mlx4_en_update_rx_prod_db(ring);
1163 out:
1164         kfree(context);
1165         return err;
1166 }
1167
1168 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
1169 {
1170         int err;
1171         u32 qpn;
1172
1173         err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn,
1174                                     MLX4_RESERVE_A0_QP);
1175         if (err) {
1176                 en_err(priv, "Failed reserving drop qpn\n");
1177                 return err;
1178         }
1179         err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL);
1180         if (err) {
1181                 en_err(priv, "Failed allocating drop qp\n");
1182                 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1183                 return err;
1184         }
1185
1186         return 0;
1187 }
1188
1189 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
1190 {
1191         u32 qpn;
1192
1193         qpn = priv->drop_qp.qpn;
1194         mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
1195         mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
1196         mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1197 }
1198
1199 /* Allocate rx qp's and configure them according to rss map */
1200 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
1201 {
1202         struct mlx4_en_dev *mdev = priv->mdev;
1203         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1204         struct mlx4_qp_context context;
1205         struct mlx4_rss_context *rss_context;
1206         int rss_rings;
1207         void *ptr;
1208         u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
1209                         MLX4_RSS_TCP_IPV6);
1210         int i, qpn;
1211         int err = 0;
1212         int good_qps = 0;
1213
1214         en_dbg(DRV, priv, "Configuring rss steering\n");
1215         err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
1216                                     priv->rx_ring_num,
1217                                     &rss_map->base_qpn, 0);
1218         if (err) {
1219                 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
1220                 return err;
1221         }
1222
1223         for (i = 0; i < priv->rx_ring_num; i++) {
1224                 qpn = rss_map->base_qpn + i;
1225                 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i],
1226                                             &rss_map->state[i],
1227                                             &rss_map->qps[i]);
1228                 if (err)
1229                         goto rss_err;
1230
1231                 ++good_qps;
1232         }
1233
1234         /* Configure RSS indirection qp */
1235         err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL);
1236         if (err) {
1237                 en_err(priv, "Failed to allocate RSS indirection QP\n");
1238                 goto rss_err;
1239         }
1240         rss_map->indir_qp.event = mlx4_en_sqp_event;
1241         mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
1242                                 priv->rx_ring[0]->cqn, -1, &context);
1243
1244         if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
1245                 rss_rings = priv->rx_ring_num;
1246         else
1247                 rss_rings = priv->prof->rss_rings;
1248
1249         ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
1250                                         + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
1251         rss_context = ptr;
1252         rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
1253                                             (rss_map->base_qpn));
1254         rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1255         if (priv->mdev->profile.udp_rss) {
1256                 rss_mask |=  MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
1257                 rss_context->base_qpn_udp = rss_context->default_qpn;
1258         }
1259
1260         if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1261                 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n");
1262                 rss_mask |= MLX4_RSS_BY_INNER_HEADERS;
1263         }
1264
1265         rss_context->flags = rss_mask;
1266         rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1267         if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) {
1268                 rss_context->hash_fn = MLX4_RSS_HASH_XOR;
1269         } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) {
1270                 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1271                 memcpy(rss_context->rss_key, priv->rss_key,
1272                        MLX4_EN_RSS_KEY_SIZE);
1273         } else {
1274                 en_err(priv, "Unknown RSS hash function requested\n");
1275                 err = -EINVAL;
1276                 goto indir_err;
1277         }
1278         err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
1279                                &rss_map->indir_qp, &rss_map->indir_state);
1280         if (err)
1281                 goto indir_err;
1282
1283         return 0;
1284
1285 indir_err:
1286         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1287                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1288         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1289         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1290 rss_err:
1291         for (i = 0; i < good_qps; i++) {
1292                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1293                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1294                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1295                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1296         }
1297         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1298         return err;
1299 }
1300
1301 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
1302 {
1303         struct mlx4_en_dev *mdev = priv->mdev;
1304         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1305         int i;
1306
1307         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1308                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1309         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1310         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1311
1312         for (i = 0; i < priv->rx_ring_num; i++) {
1313                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1314                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1315                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1316                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1317         }
1318         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1319 }