drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c

   1 /*
   2  * drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c
   3  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the names of the copyright holders nor the names of its
  15  *    contributors may be used to endorse or promote products derived from
  16  *    this software without specific prior written permission.
  17  *
  18  * Alternatively, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") version 2 as published by the Free
  20  * Software Foundation.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  26  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  32  * POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <linux/kernel.h>
  36 #include <linux/types.h>
  37
  38 #include "spectrum.h"
  39 #include "core.h"
  40 #include "port.h"
  41 #include "reg.h"
  42
  43 struct mlxsw_sp_pb {
  44         u8 index;
  45         u16 size;
  46 };
  47
  48 #define MLXSW_SP_PB(_index, _size)      \
  49         {                               \
  50                 .index = _index,        \
  51                 .size = _size,          \
  52         }
  53
  54 static const struct mlxsw_sp_pb mlxsw_sp_pbs[] = {
  55         MLXSW_SP_PB(0, 208),
  56         MLXSW_SP_PB(1, 208),
  57         MLXSW_SP_PB(2, 208),
  58         MLXSW_SP_PB(3, 208),
  59         MLXSW_SP_PB(4, 208),
  60         MLXSW_SP_PB(5, 208),
  61         MLXSW_SP_PB(6, 208),
  62         MLXSW_SP_PB(7, 208),
  63         MLXSW_SP_PB(9, 208),
  64 };
  65
  66 #define MLXSW_SP_PBS_LEN ARRAY_SIZE(mlxsw_sp_pbs)
  67
  68 static int mlxsw_sp_port_pb_init(struct mlxsw_sp_port *mlxsw_sp_port)
  69 {
  70         char pbmc_pl[MLXSW_REG_PBMC_LEN];
  71         int i;
  72
  73         mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port,
  74                             0xffff, 0xffff / 2);
  75         for (i = 0; i < MLXSW_SP_PBS_LEN; i++) {
  76                 const struct mlxsw_sp_pb *pb;
  77
  78                 pb = &mlxsw_sp_pbs[i];
  79                 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, pb->index, pb->size);
  80         }
  81         return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core,
  82                                MLXSW_REG(pbmc), pbmc_pl);
  83 }
  84
  85 #define MLXSW_SP_SB_BYTES_PER_CELL 96
  86
  87 struct mlxsw_sp_sb_pool {
  88         u8 pool;
  89         enum mlxsw_reg_sbpr_dir dir;
  90         enum mlxsw_reg_sbpr_mode mode;
  91         u32 size;
  92 };
  93
  94 #define MLXSW_SP_SB_POOL_INGRESS_SIZE                           \
  95         ((15000000 - (2 * 20000 * MLXSW_PORT_MAX_PORTS)) /      \
  96          MLXSW_SP_SB_BYTES_PER_CELL)
  97 #define MLXSW_SP_SB_POOL_EGRESS_SIZE                            \
  98         ((14000000 - (8 * 1500 * MLXSW_PORT_MAX_PORTS)) /       \
  99          MLXSW_SP_SB_BYTES_PER_CELL)
 100
 101 #define MLXSW_SP_SB_POOL(_pool, _dir, _mode, _size)             \
 102         {                                                       \
 103                 .pool = _pool,                                  \
 104                 .dir = _dir,                                    \
 105                 .mode = _mode,                                  \
 106                 .size = _size,                                  \
 107         }
 108
 109 #define MLXSW_SP_SB_POOL_INGRESS(_pool, _size)                  \
 110         MLXSW_SP_SB_POOL(_pool, MLXSW_REG_SBPR_DIR_INGRESS,     \
 111                          MLXSW_REG_SBPR_MODE_DYNAMIC, _size)
 112
 113 #define MLXSW_SP_SB_POOL_EGRESS(_pool, _size)                   \
 114         MLXSW_SP_SB_POOL(_pool, MLXSW_REG_SBPR_DIR_EGRESS,      \
 115                          MLXSW_REG_SBPR_MODE_DYNAMIC, _size)
 116
 117 static const struct mlxsw_sp_sb_pool mlxsw_sp_sb_pools[] = {
 118         MLXSW_SP_SB_POOL_INGRESS(0, MLXSW_SP_SB_POOL_INGRESS_SIZE),
 119         MLXSW_SP_SB_POOL_INGRESS(1, 0),
 120         MLXSW_SP_SB_POOL_INGRESS(2, 0),
 121         MLXSW_SP_SB_POOL_INGRESS(3, 0),
 122         MLXSW_SP_SB_POOL_EGRESS(0, MLXSW_SP_SB_POOL_EGRESS_SIZE),
 123         MLXSW_SP_SB_POOL_EGRESS(1, 0),
 124         MLXSW_SP_SB_POOL_EGRESS(2, 0),
 125         MLXSW_SP_SB_POOL_EGRESS(2, MLXSW_SP_SB_POOL_EGRESS_SIZE),
 126 };
 127
 128 #define MLXSW_SP_SB_POOLS_LEN ARRAY_SIZE(mlxsw_sp_sb_pools)
 129
 130 static int mlxsw_sp_sb_pools_init(struct mlxsw_sp *mlxsw_sp)
 131 {
 132         char sbpr_pl[MLXSW_REG_SBPR_LEN];
 133         int i;
 134         int err;
 135
 136         for (i = 0; i < MLXSW_SP_SB_POOLS_LEN; i++) {
 137                 const struct mlxsw_sp_sb_pool *pool;
 138
 139                 pool = &mlxsw_sp_sb_pools[i];
 140                 mlxsw_reg_sbpr_pack(sbpr_pl, pool->pool, pool->dir,
 141                                     pool->mode, pool->size);
 142                 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbpr), sbpr_pl);
 143                 if (err)
 144                         return err;
 145         }
 146         return 0;
 147 }
 148
 149 struct mlxsw_sp_sb_cm {
 150         union {
 151                 u8 pg;
 152                 u8 tc;
 153         } u;
 154         enum mlxsw_reg_sbcm_dir dir;
 155         u32 min_buff;
 156         u32 max_buff;
 157         u8 pool;
 158 };
 159
 160 #define MLXSW_SP_SB_CM(_pg_tc, _dir, _min_buff, _max_buff, _pool)       \
 161         {                                                               \
 162                 .u.pg = _pg_tc,                                         \
 163                 .dir = _dir,                                            \
 164                 .min_buff = _min_buff,                                  \
 165                 .max_buff = _max_buff,                                  \
 166                 .pool = _pool,                                          \
 167         }
 168
 169 #define MLXSW_SP_SB_CM_INGRESS(_pg, _min_buff, _max_buff)               \
 170         MLXSW_SP_SB_CM(_pg, MLXSW_REG_SBCM_DIR_INGRESS,                 \
 171                        _min_buff, _max_buff, 0)
 172
 173 #define MLXSW_SP_SB_CM_EGRESS(_tc, _min_buff, _max_buff)                \
 174         MLXSW_SP_SB_CM(_tc, MLXSW_REG_SBCM_DIR_EGRESS,                  \
 175                        _min_buff, _max_buff, 0)
 176
 177 #define MLXSW_SP_CPU_PORT_SB_CM_EGRESS(_tc)                             \
 178         MLXSW_SP_SB_CM(_tc, MLXSW_REG_SBCM_DIR_EGRESS, 104, 2, 3)
 179
 180 static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms[] = {
 181         MLXSW_SP_SB_CM_INGRESS(0, 10000 / MLXSW_SP_SB_BYTES_PER_CELL, 8),
 182         MLXSW_SP_SB_CM_INGRESS(1, 0, 0),
 183         MLXSW_SP_SB_CM_INGRESS(2, 0, 0),
 184         MLXSW_SP_SB_CM_INGRESS(3, 0, 0),
 185         MLXSW_SP_SB_CM_INGRESS(4, 0, 0),
 186         MLXSW_SP_SB_CM_INGRESS(5, 0, 0),
 187         MLXSW_SP_SB_CM_INGRESS(6, 0, 0),
 188         MLXSW_SP_SB_CM_INGRESS(7, 0, 0),
 189         MLXSW_SP_SB_CM_INGRESS(9, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff),
 190         MLXSW_SP_SB_CM_EGRESS(0, 1500 / MLXSW_SP_SB_BYTES_PER_CELL, 9),
 191         MLXSW_SP_SB_CM_EGRESS(1, 1500 / MLXSW_SP_SB_BYTES_PER_CELL, 9),
 192         MLXSW_SP_SB_CM_EGRESS(2, 1500 / MLXSW_SP_SB_BYTES_PER_CELL, 9),
 193         MLXSW_SP_SB_CM_EGRESS(3, 1500 / MLXSW_SP_SB_BYTES_PER_CELL, 9),
 194         MLXSW_SP_SB_CM_EGRESS(4, 1500 / MLXSW_SP_SB_BYTES_PER_CELL, 9),
 195         MLXSW_SP_SB_CM_EGRESS(5, 1500 / MLXSW_SP_SB_BYTES_PER_CELL, 9),
 196         MLXSW_SP_SB_CM_EGRESS(6, 1500 / MLXSW_SP_SB_BYTES_PER_CELL, 9),
 197         MLXSW_SP_SB_CM_EGRESS(7, 1500 / MLXSW_SP_SB_BYTES_PER_CELL, 9),
 198         MLXSW_SP_SB_CM_EGRESS(8, 0, 0),
 199         MLXSW_SP_SB_CM_EGRESS(9, 0, 0),
 200         MLXSW_SP_SB_CM_EGRESS(10, 0, 0),
 201         MLXSW_SP_SB_CM_EGRESS(11, 0, 0),
 202         MLXSW_SP_SB_CM_EGRESS(12, 0, 0),
 203         MLXSW_SP_SB_CM_EGRESS(13, 0, 0),
 204         MLXSW_SP_SB_CM_EGRESS(14, 0, 0),
 205         MLXSW_SP_SB_CM_EGRESS(15, 0, 0),
 206         MLXSW_SP_SB_CM_EGRESS(16, 1, 0xff),
 207 };
 208
 209 #define MLXSW_SP_SB_CMS_LEN ARRAY_SIZE(mlxsw_sp_sb_cms)
 210
 211 static const struct mlxsw_sp_sb_cm mlxsw_sp_cpu_port_sb_cms[] = {
 212         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(0),
 213         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(1),
 214         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(2),
 215         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(3),
 216         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(4),
 217         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(5),
 218         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(6),
 219         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(7),
 220         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(8),
 221         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(9),
 222         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(10),
 223         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(11),
 224         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(12),
 225         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(13),
 226         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(14),
 227         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(15),
 228         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(16),
 229         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(17),
 230         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(18),
 231         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(19),
 232         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(20),
 233         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(21),
 234         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(22),
 235         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(23),
 236         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(24),
 237         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(25),
 238         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(26),
 239         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(27),
 240         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(28),
 241         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(29),
 242         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(30),
 243         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(31),
 244 };
 245
 246 #define MLXSW_SP_CPU_PORT_SB_MCS_LEN \
 247         ARRAY_SIZE(mlxsw_sp_cpu_port_sb_cms)
 248
 249 static int mlxsw_sp_sb_cms_init(struct mlxsw_sp *mlxsw_sp, u8 local_port,
 250                                 const struct mlxsw_sp_sb_cm *cms,
 251                                 size_t cms_len)
 252 {
 253         char sbcm_pl[MLXSW_REG_SBCM_LEN];
 254         int i;
 255         int err;
 256
 257         for (i = 0; i < cms_len; i++) {
 258                 const struct mlxsw_sp_sb_cm *cm;
 259
 260                 cm = &cms[i];
 261                 mlxsw_reg_sbcm_pack(sbcm_pl, local_port, cm->u.pg, cm->dir,
 262                                     cm->min_buff, cm->max_buff, cm->pool);
 263                 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbcm), sbcm_pl);
 264                 if (err)
 265                         return err;
 266         }
 267         return 0;
 268 }
 269
 270 static int mlxsw_sp_port_sb_cms_init(struct mlxsw_sp_port *mlxsw_sp_port)
 271 {
 272         return mlxsw_sp_sb_cms_init(mlxsw_sp_port->mlxsw_sp,
 273                                     mlxsw_sp_port->local_port, mlxsw_sp_sb_cms,
 274                                     MLXSW_SP_SB_CMS_LEN);
 275 }
 276
 277 static int mlxsw_sp_cpu_port_sb_cms_init(struct mlxsw_sp *mlxsw_sp)
 278 {
 279         return mlxsw_sp_sb_cms_init(mlxsw_sp, 0, mlxsw_sp_cpu_port_sb_cms,
 280                                     MLXSW_SP_CPU_PORT_SB_MCS_LEN);
 281 }
 282
 283 struct mlxsw_sp_sb_pm {
 284         u8 pool;
 285         enum mlxsw_reg_sbpm_dir dir;
 286         u32 min_buff;
 287         u32 max_buff;
 288 };
 289
 290 #define MLXSW_SP_SB_PM(_pool, _dir, _min_buff, _max_buff)       \
 291         {                                                       \
 292                 .pool = _pool,                                  \
 293                 .dir = _dir,                                    \
 294                 .min_buff = _min_buff,                          \
 295                 .max_buff = _max_buff,                          \
 296         }
 297
 298 #define MLXSW_SP_SB_PM_INGRESS(_pool, _min_buff, _max_buff)     \
 299         MLXSW_SP_SB_PM(_pool, MLXSW_REG_SBPM_DIR_INGRESS,       \
 300                        _min_buff, _max_buff)
 301
 302 #define MLXSW_SP_SB_PM_EGRESS(_pool, _min_buff, _max_buff)      \
 303         MLXSW_SP_SB_PM(_pool, MLXSW_REG_SBPM_DIR_EGRESS,        \
 304                        _min_buff, _max_buff)
 305
 306 static const struct mlxsw_sp_sb_pm mlxsw_sp_sb_pms[] = {
 307         MLXSW_SP_SB_PM_INGRESS(0, 0, 0xff),
 308         MLXSW_SP_SB_PM_INGRESS(1, 0, 0),
 309         MLXSW_SP_SB_PM_INGRESS(2, 0, 0),
 310         MLXSW_SP_SB_PM_INGRESS(3, 0, 0),
 311         MLXSW_SP_SB_PM_EGRESS(0, 0, 7),
 312         MLXSW_SP_SB_PM_EGRESS(1, 0, 0),
 313         MLXSW_SP_SB_PM_EGRESS(2, 0, 0),
 314         MLXSW_SP_SB_PM_EGRESS(3, 0, 0),
 315 };
 316
 317 #define MLXSW_SP_SB_PMS_LEN ARRAY_SIZE(mlxsw_sp_sb_pms)
 318
 319 static int mlxsw_sp_port_sb_pms_init(struct mlxsw_sp_port *mlxsw_sp_port)
 320 {
 321         char sbpm_pl[MLXSW_REG_SBPM_LEN];
 322         int i;
 323         int err;
 324
 325         for (i = 0; i < MLXSW_SP_SB_PMS_LEN; i++) {
 326                 const struct mlxsw_sp_sb_pm *pm;
 327
 328                 pm = &mlxsw_sp_sb_pms[i];
 329                 mlxsw_reg_sbpm_pack(sbpm_pl, mlxsw_sp_port->local_port,
 330                                     pm->pool, pm->dir,
 331                                     pm->min_buff, pm->max_buff);
 332                 err = mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core,
 333                                       MLXSW_REG(sbpm), sbpm_pl);
 334                 if (err)
 335                         return err;
 336         }
 337         return 0;
 338 }
 339
 340 struct mlxsw_sp_sb_mm {
 341         u8 prio;
 342         u32 min_buff;
 343         u32 max_buff;
 344         u8 pool;
 345 };
 346
 347 #define MLXSW_SP_SB_MM(_prio, _min_buff, _max_buff, _pool)      \
 348         {                                                       \
 349                 .prio = _prio,                                  \
 350                 .min_buff = _min_buff,                          \
 351                 .max_buff = _max_buff,                          \
 352                 .pool = _pool,                                  \
 353         }
 354
 355 static const struct mlxsw_sp_sb_mm mlxsw_sp_sb_mms[] = {
 356         MLXSW_SP_SB_MM(0, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
 357         MLXSW_SP_SB_MM(1, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
 358         MLXSW_SP_SB_MM(2, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
 359         MLXSW_SP_SB_MM(3, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
 360         MLXSW_SP_SB_MM(4, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
 361         MLXSW_SP_SB_MM(5, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
 362         MLXSW_SP_SB_MM(6, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
 363         MLXSW_SP_SB_MM(7, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
 364         MLXSW_SP_SB_MM(8, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
 365         MLXSW_SP_SB_MM(9, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
 366         MLXSW_SP_SB_MM(10, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
 367         MLXSW_SP_SB_MM(11, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
 368         MLXSW_SP_SB_MM(12, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
 369         MLXSW_SP_SB_MM(13, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
 370         MLXSW_SP_SB_MM(14, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
 371 };
 372
 373 #define MLXSW_SP_SB_MMS_LEN ARRAY_SIZE(mlxsw_sp_sb_mms)
 374
 375 static int mlxsw_sp_sb_mms_init(struct mlxsw_sp *mlxsw_sp)
 376 {
 377         char sbmm_pl[MLXSW_REG_SBMM_LEN];
 378         int i;
 379         int err;
 380
 381         for (i = 0; i < MLXSW_SP_SB_MMS_LEN; i++) {
 382                 const struct mlxsw_sp_sb_mm *mc;
 383
 384                 mc = &mlxsw_sp_sb_mms[i];
 385                 mlxsw_reg_sbmm_pack(sbmm_pl, mc->prio, mc->min_buff,
 386                                     mc->max_buff, mc->pool);
 387                 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbmm), sbmm_pl);
 388                 if (err)
 389                         return err;
 390         }
 391         return 0;
 392 }
 393
 394 int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp)
 395 {
 396         int err;
 397
 398         err = mlxsw_sp_sb_pools_init(mlxsw_sp);
 399         if (err)
 400                 return err;
 401         err = mlxsw_sp_cpu_port_sb_cms_init(mlxsw_sp);
 402         if (err)
 403                 return err;
 404         err = mlxsw_sp_sb_mms_init(mlxsw_sp);
 405
 406         return err;
 407 }
 408
 409 int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port)
 410 {
 411         int err;
 412
 413         err = mlxsw_sp_port_pb_init(mlxsw_sp_port);
 414         if (err)
 415                 return err;
 416         err = mlxsw_sp_port_sb_cms_init(mlxsw_sp_port);
 417         if (err)
 418                 return err;
 419         err = mlxsw_sp_port_sb_pms_init(mlxsw_sp_port);
 420
 421         return err;
 422 }