drivers/net/ethernet/qlogic/qed/qed_hsi.h

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #ifndef _QED_HSI_H
  10 #define _QED_HSI_H
  11
  12 #include <linux/types.h>
  13 #include <linux/io.h>
  14 #include <linux/bitops.h>
  15 #include <linux/delay.h>
  16 #include <linux/kernel.h>
  17 #include <linux/list.h>
  18 #include <linux/slab.h>
  19 #include <linux/qed/common_hsi.h>
  20 #include <linux/qed/eth_common.h>
  21
  22 struct qed_hwfn;
  23 struct qed_ptt;
  24 /********************************/
  25 /* Add include to common target */
  26 /********************************/
  27
  28 /* opcodes for the event ring */
  29 enum common_event_opcode {
  30         COMMON_EVENT_PF_START,
  31         COMMON_EVENT_PF_STOP,
  32         COMMON_EVENT_RESERVED,
  33         COMMON_EVENT_RESERVED2,
  34         COMMON_EVENT_RESERVED3,
  35         COMMON_EVENT_RESERVED4,
  36         COMMON_EVENT_RESERVED5,
  37         MAX_COMMON_EVENT_OPCODE
  38 };
  39
  40 /* Common Ramrod Command IDs */
  41 enum common_ramrod_cmd_id {
  42         COMMON_RAMROD_UNUSED,
  43         COMMON_RAMROD_PF_START /* PF Function Start Ramrod */,
  44         COMMON_RAMROD_PF_STOP /* PF Function Stop Ramrod */,
  45         COMMON_RAMROD_RESERVED,
  46         COMMON_RAMROD_RESERVED2,
  47         COMMON_RAMROD_RESERVED3,
  48         MAX_COMMON_RAMROD_CMD_ID
  49 };
  50
  51 /* The core storm context for the Ystorm */
  52 struct ystorm_core_conn_st_ctx {
  53         __le32 reserved[4];
  54 };
  55
  56 /* The core storm context for the Pstorm */
  57 struct pstorm_core_conn_st_ctx {
  58         __le32 reserved[4];
  59 };
  60
  61 /* Core Slowpath Connection storm context of Xstorm */
  62 struct xstorm_core_conn_st_ctx {
  63         __le32          spq_base_lo /* SPQ Ring Base Address low dword */;
  64         __le32          spq_base_hi /* SPQ Ring Base Address high dword */;
  65         struct regpair  consolid_base_addr;
  66         __le16          spq_cons /* SPQ Ring Consumer */;
  67         __le16          consolid_cons /* Consolidation Ring Consumer */;
  68         __le32          reserved0[55] /* Pad to 15 cycles */;
  69 };
  70
  71 struct xstorm_core_conn_ag_ctx {
  72         u8      reserved0 /* cdu_validation */;
  73         u8      core_state /* state */;
  74         u8      flags0;
  75 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK         0x1
  76 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT        0
  77 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK            0x1
  78 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT           1
  79 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK            0x1
  80 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT           2
  81 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK         0x1
  82 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT        3
  83 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK            0x1
  84 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT           4
  85 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK            0x1
  86 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT           5
  87 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK            0x1   /* bit6 */
  88 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT           6
  89 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK            0x1   /* bit7 */
  90 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT           7
  91         u8 flags1;
  92 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK            0x1   /* bit8 */
  93 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT           0
  94 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK            0x1   /* bit9 */
  95 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT           1
  96 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK            0x1   /* bit10 */
  97 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT           2
  98 #define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK                0x1   /* bit11 */
  99 #define XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT               3
 100 #define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK                0x1   /* bit12 */
 101 #define XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT               4
 102 #define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK                0x1   /* bit13 */
 103 #define XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT               5
 104 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK       0x1   /* bit14 */
 105 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT      6
 106 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK         0x1   /* bit15 */
 107 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT        7
 108         u8 flags2;
 109 #define XSTORM_CORE_CONN_AG_CTX_CF0_MASK                  0x3   /* timer0cf */
 110 #define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT                 0
 111 #define XSTORM_CORE_CONN_AG_CTX_CF1_MASK                  0x3   /* timer1cf */
 112 #define XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT                 2
 113 #define XSTORM_CORE_CONN_AG_CTX_CF2_MASK                  0x3   /* timer2cf */
 114 #define XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT                 4
 115 #define XSTORM_CORE_CONN_AG_CTX_CF3_MASK                  0x3
 116 #define XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT                 6
 117         u8 flags3;
 118 #define XSTORM_CORE_CONN_AG_CTX_CF4_MASK                  0x3   /* cf4 */
 119 #define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT                 0
 120 #define XSTORM_CORE_CONN_AG_CTX_CF5_MASK                  0x3   /* cf5 */
 121 #define XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT                 2
 122 #define XSTORM_CORE_CONN_AG_CTX_CF6_MASK                  0x3   /* cf6 */
 123 #define XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT                 4
 124 #define XSTORM_CORE_CONN_AG_CTX_CF7_MASK                  0x3   /* cf7 */
 125 #define XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT                 6
 126         u8 flags4;
 127 #define XSTORM_CORE_CONN_AG_CTX_CF8_MASK                  0x3   /* cf8 */
 128 #define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT                 0
 129 #define XSTORM_CORE_CONN_AG_CTX_CF9_MASK                  0x3   /* cf9 */
 130 #define XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT                 2
 131 #define XSTORM_CORE_CONN_AG_CTX_CF10_MASK                 0x3   /* cf10 */
 132 #define XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT                4
 133 #define XSTORM_CORE_CONN_AG_CTX_CF11_MASK                 0x3   /* cf11 */
 134 #define XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT                6
 135         u8 flags5;
 136 #define XSTORM_CORE_CONN_AG_CTX_CF12_MASK                 0x3   /* cf12 */
 137 #define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT                0
 138 #define XSTORM_CORE_CONN_AG_CTX_CF13_MASK                 0x3   /* cf13 */
 139 #define XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT                2
 140 #define XSTORM_CORE_CONN_AG_CTX_CF14_MASK                 0x3   /* cf14 */
 141 #define XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT                4
 142 #define XSTORM_CORE_CONN_AG_CTX_CF15_MASK                 0x3   /* cf15 */
 143 #define XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT                6
 144         u8 flags6;
 145 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK     0x3   /* cf16 */
 146 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT    0
 147 #define XSTORM_CORE_CONN_AG_CTX_CF17_MASK                 0x3
 148 #define XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT                2
 149 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK                0x3   /* cf18 */
 150 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT               4
 151 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK         0x3   /* cf19 */
 152 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT        6
 153         u8 flags7;
 154 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK             0x3   /* cf20 */
 155 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT            0
 156 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK           0x3   /* cf21 */
 157 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT          2
 158 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK            0x3   /* cf22 */
 159 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT           4
 160 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK                0x1   /* cf0en */
 161 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT               6
 162 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK                0x1   /* cf1en */
 163 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT               7
 164         u8 flags8;
 165 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK                0x1   /* cf2en */
 166 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT               0
 167 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK                0x1   /* cf3en */
 168 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT               1
 169 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK                0x1   /* cf4en */
 170 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT               2
 171 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK                0x1   /* cf5en */
 172 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT               3
 173 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK                0x1   /* cf6en */
 174 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT               4
 175 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK                0x1   /* cf7en */
 176 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT               5
 177 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK                0x1   /* cf8en */
 178 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT               6
 179 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK                0x1   /* cf9en */
 180 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT               7
 181         u8 flags9;
 182 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK               0x1   /* cf10en */
 183 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT              0
 184 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK               0x1   /* cf11en */
 185 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT              1
 186 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK               0x1   /* cf12en */
 187 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT              2
 188 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK               0x1   /* cf13en */
 189 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT              3
 190 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK               0x1   /* cf14en */
 191 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT              4
 192 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK               0x1   /* cf15en */
 193 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT              5
 194 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK  0x1   /* cf16en */
 195 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6
 196 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK               0x1
 197 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT              7
 198         u8 flags10;
 199 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK             0x1   /* cf18en */
 200 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT            0
 201 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK      0x1   /* cf19en */
 202 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT     1
 203 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK          0x1   /* cf20en */
 204 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT         2
 205 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK           0x1   /* cf21en */
 206 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT          3
 207 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK         0x1   /* cf22en */
 208 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT        4
 209 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK               0x1   /* cf23en */
 210 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT              5
 211 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK           0x1   /* rule0en */
 212 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT          6
 213 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK           0x1   /* rule1en */
 214 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT          7
 215         u8 flags11;
 216 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK           0x1   /* rule2en */
 217 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT          0
 218 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK           0x1   /* rule3en */
 219 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT          1
 220 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK       0x1   /* rule4en */
 221 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT      2
 222 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK              0x1   /* rule5en */
 223 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT             3
 224 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK              0x1   /* rule6en */
 225 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT             4
 226 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK              0x1   /* rule7en */
 227 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT             5
 228 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK         0x1   /* rule8en */
 229 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT        6
 230 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK              0x1   /* rule9en */
 231 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT             7
 232         u8 flags12;
 233 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK             0x1   /* rule10en */
 234 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT            0
 235 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK             0x1   /* rule11en */
 236 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT            1
 237 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK         0x1   /* rule12en */
 238 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT        2
 239 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK         0x1   /* rule13en */
 240 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT        3
 241 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK             0x1   /* rule14en */
 242 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT            4
 243 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK             0x1   /* rule15en */
 244 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT            5
 245 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK             0x1   /* rule16en */
 246 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT            6
 247 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK             0x1   /* rule17en */
 248 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT            7
 249         u8 flags13;
 250 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK             0x1   /* rule18en */
 251 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT            0
 252 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK             0x1   /* rule19en */
 253 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT            1
 254 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK         0x1   /* rule20en */
 255 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT        2
 256 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK         0x1   /* rule21en */
 257 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT        3
 258 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK         0x1   /* rule22en */
 259 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT        4
 260 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK         0x1   /* rule23en */
 261 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT        5
 262 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK         0x1   /* rule24en */
 263 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT        6
 264 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK         0x1   /* rule25en */
 265 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT        7
 266         u8 flags14;
 267 #define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK                0x1   /* bit16 */
 268 #define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT               0
 269 #define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK                0x1   /* bit17 */
 270 #define XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT               1
 271 #define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK                0x1   /* bit18 */
 272 #define XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT               2
 273 #define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK                0x1   /* bit19 */
 274 #define XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT               3
 275 #define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK                0x1   /* bit20 */
 276 #define XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT               4
 277 #define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK                0x1   /* bit21 */
 278 #define XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT               5
 279 #define XSTORM_CORE_CONN_AG_CTX_CF23_MASK                 0x3   /* cf23 */
 280 #define XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT                6
 281         u8      byte2 /* byte2 */;
 282         __le16  physical_q0 /* physical_q0 */;
 283         __le16  consolid_prod /* physical_q1 */;
 284         __le16  reserved16 /* physical_q2 */;
 285         __le16  tx_bd_cons /* word3 */;
 286         __le16  tx_bd_or_spq_prod /* word4 */;
 287         __le16  word5 /* word5 */;
 288         __le16  conn_dpi /* conn_dpi */;
 289         u8      byte3 /* byte3 */;
 290         u8      byte4 /* byte4 */;
 291         u8      byte5 /* byte5 */;
 292         u8      byte6 /* byte6 */;
 293         __le32  reg0 /* reg0 */;
 294         __le32  reg1 /* reg1 */;
 295         __le32  reg2 /* reg2 */;
 296         __le32  reg3 /* reg3 */;
 297         __le32  reg4 /* reg4 */;
 298         __le32  reg5 /* cf_array0 */;
 299         __le32  reg6 /* cf_array1 */;
 300         __le16  word7 /* word7 */;
 301         __le16  word8 /* word8 */;
 302         __le16  word9 /* word9 */;
 303         __le16  word10 /* word10 */;
 304         __le32  reg7 /* reg7 */;
 305         __le32  reg8 /* reg8 */;
 306         __le32  reg9 /* reg9 */;
 307         u8      byte7 /* byte7 */;
 308         u8      byte8 /* byte8 */;
 309         u8      byte9 /* byte9 */;
 310         u8      byte10 /* byte10 */;
 311         u8      byte11 /* byte11 */;
 312         u8      byte12 /* byte12 */;
 313         u8      byte13 /* byte13 */;
 314         u8      byte14 /* byte14 */;
 315         u8      byte15 /* byte15 */;
 316         u8      byte16 /* byte16 */;
 317         __le16  word11 /* word11 */;
 318         __le32  reg10 /* reg10 */;
 319         __le32  reg11 /* reg11 */;
 320         __le32  reg12 /* reg12 */;
 321         __le32  reg13 /* reg13 */;
 322         __le32  reg14 /* reg14 */;
 323         __le32  reg15 /* reg15 */;
 324         __le32  reg16 /* reg16 */;
 325         __le32  reg17 /* reg17 */;
 326         __le32  reg18 /* reg18 */;
 327         __le32  reg19 /* reg19 */;
 328         __le16  word12 /* word12 */;
 329         __le16  word13 /* word13 */;
 330         __le16  word14 /* word14 */;
 331         __le16  word15 /* word15 */;
 332 };
 333
 334 /* The core storm context for the Mstorm */
 335 struct mstorm_core_conn_st_ctx {
 336         __le32 reserved[24];
 337 };
 338
 339 /* The core storm context for the Ustorm */
 340 struct ustorm_core_conn_st_ctx {
 341         __le32 reserved[4];
 342 };
 343
 344 /* core connection context */
 345 struct core_conn_context {
 346         struct ystorm_core_conn_st_ctx  ystorm_st_context;
 347         struct regpair                  ystorm_st_padding[2] /* padding */;
 348         struct pstorm_core_conn_st_ctx  pstorm_st_context;
 349         struct regpair                  pstorm_st_padding[2];
 350         struct xstorm_core_conn_st_ctx  xstorm_st_context;
 351         struct xstorm_core_conn_ag_ctx  xstorm_ag_context;
 352         struct mstorm_core_conn_st_ctx  mstorm_st_context;
 353         struct regpair                  mstorm_st_padding[2];
 354         struct ustorm_core_conn_st_ctx  ustorm_st_context;
 355         struct regpair                  ustorm_st_padding[2] /* padding */;
 356 };
 357
 358 struct eth_mstorm_per_queue_stat {
 359         struct regpair  ttl0_discard;
 360         struct regpair  packet_too_big_discard;
 361         struct regpair  no_buff_discard;
 362         struct regpair  not_active_discard;
 363         struct regpair  tpa_coalesced_pkts;
 364         struct regpair  tpa_coalesced_events;
 365         struct regpair  tpa_aborts_num;
 366         struct regpair  tpa_coalesced_bytes;
 367 };
 368
 369 struct eth_pstorm_per_queue_stat {
 370         struct regpair  sent_ucast_bytes;
 371         struct regpair  sent_mcast_bytes;
 372         struct regpair  sent_bcast_bytes;
 373         struct regpair  sent_ucast_pkts;
 374         struct regpair  sent_mcast_pkts;
 375         struct regpair  sent_bcast_pkts;
 376         struct regpair  error_drop_pkts;
 377 };
 378
 379 struct eth_ustorm_per_queue_stat {
 380         struct regpair  rcv_ucast_bytes;
 381         struct regpair  rcv_mcast_bytes;
 382         struct regpair  rcv_bcast_bytes;
 383         struct regpair  rcv_ucast_pkts;
 384         struct regpair  rcv_mcast_pkts;
 385         struct regpair  rcv_bcast_pkts;
 386 };
 387
 388 /* Event Ring Next Page Address */
 389 struct event_ring_next_addr {
 390         struct regpair  addr /* Next Page Address */;
 391         __le32          reserved[2] /* Reserved */;
 392 };
 393
 394 union event_ring_element {
 395         struct event_ring_entry         entry /* Event Ring Entry */;
 396         struct event_ring_next_addr     next_addr;
 397 };
 398
 399 enum personality_type {
 400         PERSONALITY_RESERVED,
 401         PERSONALITY_RESERVED2,
 402         PERSONALITY_RDMA_AND_ETH /* Roce or Iwarp */,
 403         PERSONALITY_RESERVED3,
 404         PERSONALITY_ETH /* Ethernet */,
 405         PERSONALITY_RESERVED4,
 406         MAX_PERSONALITY_TYPE
 407 };
 408
 409 struct pf_start_tunnel_config {
 410         u8      set_vxlan_udp_port_flg;
 411         u8      set_geneve_udp_port_flg;
 412         u8      tx_enable_vxlan /* If set, enable VXLAN tunnel in TX path. */;
 413         u8      tx_enable_l2geneve;
 414         u8      tx_enable_ipgeneve;
 415         u8      tx_enable_l2gre /* If set, enable l2 GRE tunnel in TX path. */;
 416         u8      tx_enable_ipgre /* If set, enable IP GRE tunnel in TX path. */;
 417         u8      tunnel_clss_vxlan /* Classification scheme for VXLAN tunnel. */;
 418         u8      tunnel_clss_l2geneve;
 419         u8      tunnel_clss_ipgeneve;
 420         u8      tunnel_clss_l2gre;
 421         u8      tunnel_clss_ipgre;
 422         __le16  vxlan_udp_port /* VXLAN tunnel UDP destination port. */;
 423         __le16  geneve_udp_port /* GENEVE tunnel UDP destination port. */;
 424 };
 425
 426 /* Ramrod data for PF start ramrod */
 427 struct pf_start_ramrod_data {
 428         struct regpair                  event_ring_pbl_addr;
 429         struct regpair                  consolid_q_pbl_addr;
 430         struct pf_start_tunnel_config   tunnel_config;
 431         __le16                          event_ring_sb_id;
 432         u8                              base_vf_id;
 433         u8                              num_vfs;
 434         u8                              event_ring_num_pages;
 435         u8                              event_ring_sb_index;
 436         u8                              path_id;
 437         u8                              warning_as_error;
 438         u8                              dont_log_ramrods;
 439         u8                              personality;
 440         __le16                          log_type_mask;
 441         u8                              mf_mode /* Multi function mode */;
 442         u8                              integ_phase /* Integration phase */;
 443         u8                              allow_npar_tx_switching;
 444         u8                              inner_to_outer_pri_map[8];
 445         u8                              pri_map_valid;
 446         u32                             outer_tag;
 447         u8                              reserved0[4];
 448 };
 449
 450 enum ports_mode {
 451         ENGX2_PORTX1 /* 2 engines x 1 port */,
 452         ENGX2_PORTX2 /* 2 engines x 2 ports */,
 453         ENGX1_PORTX1 /* 1 engine  x 1 port */,
 454         ENGX1_PORTX2 /* 1 engine  x 2 ports */,
 455         ENGX1_PORTX4 /* 1 engine  x 4 ports */,
 456         MAX_PORTS_MODE
 457 };
 458
 459 /* Ramrod Header of SPQE */
 460 struct ramrod_header {
 461         __le32  cid /* Slowpath Connection CID */;
 462         u8      cmd_id /* Ramrod Cmd (Per Protocol Type) */;
 463         u8      protocol_id /* Ramrod Protocol ID */;
 464         __le16  echo /* Ramrod echo */;
 465 };
 466
 467 /* Slowpath Element (SPQE) */
 468 struct slow_path_element {
 469         struct ramrod_header    hdr /* Ramrod Header */;
 470         struct regpair          data_ptr;
 471 };
 472
 473 struct tstorm_per_port_stat {
 474         struct regpair  trunc_error_discard;
 475         struct regpair  mac_error_discard;
 476         struct regpair  mftag_filter_discard;
 477         struct regpair  eth_mac_filter_discard;
 478         struct regpair  ll2_mac_filter_discard;
 479         struct regpair  ll2_conn_disabled_discard;
 480         struct regpair  iscsi_irregular_pkt;
 481         struct regpair  fcoe_irregular_pkt;
 482         struct regpair  roce_irregular_pkt;
 483         struct regpair  eth_irregular_pkt;
 484         struct regpair  toe_irregular_pkt;
 485         struct regpair  preroce_irregular_pkt;
 486 };
 487
 488 struct atten_status_block {
 489         __le32  atten_bits;
 490         __le32  atten_ack;
 491         __le16  reserved0;
 492         __le16  sb_index /* status block running index */;
 493         __le32  reserved1;
 494 };
 495
 496 enum block_addr {
 497         GRCBASE_GRC             = 0x50000,
 498         GRCBASE_MISCS           = 0x9000,
 499         GRCBASE_MISC            = 0x8000,
 500         GRCBASE_DBU             = 0xa000,
 501         GRCBASE_PGLUE_B         = 0x2a8000,
 502         GRCBASE_CNIG            = 0x218000,
 503         GRCBASE_CPMU            = 0x30000,
 504         GRCBASE_NCSI            = 0x40000,
 505         GRCBASE_OPTE            = 0x53000,
 506         GRCBASE_BMB             = 0x540000,
 507         GRCBASE_PCIE            = 0x54000,
 508         GRCBASE_MCP             = 0xe00000,
 509         GRCBASE_MCP2            = 0x52000,
 510         GRCBASE_PSWHST          = 0x2a0000,
 511         GRCBASE_PSWHST2         = 0x29e000,
 512         GRCBASE_PSWRD           = 0x29c000,
 513         GRCBASE_PSWRD2          = 0x29d000,
 514         GRCBASE_PSWWR           = 0x29a000,
 515         GRCBASE_PSWWR2          = 0x29b000,
 516         GRCBASE_PSWRQ           = 0x280000,
 517         GRCBASE_PSWRQ2          = 0x240000,
 518         GRCBASE_PGLCS           = 0x0,
 519         GRCBASE_PTU             = 0x560000,
 520         GRCBASE_DMAE            = 0xc000,
 521         GRCBASE_TCM             = 0x1180000,
 522         GRCBASE_MCM             = 0x1200000,
 523         GRCBASE_UCM             = 0x1280000,
 524         GRCBASE_XCM             = 0x1000000,
 525         GRCBASE_YCM             = 0x1080000,
 526         GRCBASE_PCM             = 0x1100000,
 527         GRCBASE_QM              = 0x2f0000,
 528         GRCBASE_TM              = 0x2c0000,
 529         GRCBASE_DORQ            = 0x100000,
 530         GRCBASE_BRB             = 0x340000,
 531         GRCBASE_SRC             = 0x238000,
 532         GRCBASE_PRS             = 0x1f0000,
 533         GRCBASE_TSDM            = 0xfb0000,
 534         GRCBASE_MSDM            = 0xfc0000,
 535         GRCBASE_USDM            = 0xfd0000,
 536         GRCBASE_XSDM            = 0xf80000,
 537         GRCBASE_YSDM            = 0xf90000,
 538         GRCBASE_PSDM            = 0xfa0000,
 539         GRCBASE_TSEM            = 0x1700000,
 540         GRCBASE_MSEM            = 0x1800000,
 541         GRCBASE_USEM            = 0x1900000,
 542         GRCBASE_XSEM            = 0x1400000,
 543         GRCBASE_YSEM            = 0x1500000,
 544         GRCBASE_PSEM            = 0x1600000,
 545         GRCBASE_RSS             = 0x238800,
 546         GRCBASE_TMLD            = 0x4d0000,
 547         GRCBASE_MULD            = 0x4e0000,
 548         GRCBASE_YULD            = 0x4c8000,
 549         GRCBASE_XYLD            = 0x4c0000,
 550         GRCBASE_PRM             = 0x230000,
 551         GRCBASE_PBF_PB1         = 0xda0000,
 552         GRCBASE_PBF_PB2         = 0xda4000,
 553         GRCBASE_RPB             = 0x23c000,
 554         GRCBASE_BTB             = 0xdb0000,
 555         GRCBASE_PBF             = 0xd80000,
 556         GRCBASE_RDIF            = 0x300000,
 557         GRCBASE_TDIF            = 0x310000,
 558         GRCBASE_CDU             = 0x580000,
 559         GRCBASE_CCFC            = 0x2e0000,
 560         GRCBASE_TCFC            = 0x2d0000,
 561         GRCBASE_IGU             = 0x180000,
 562         GRCBASE_CAU             = 0x1c0000,
 563         GRCBASE_UMAC            = 0x51000,
 564         GRCBASE_XMAC            = 0x210000,
 565         GRCBASE_DBG             = 0x10000,
 566         GRCBASE_NIG             = 0x500000,
 567         GRCBASE_WOL             = 0x600000,
 568         GRCBASE_BMBN            = 0x610000,
 569         GRCBASE_IPC             = 0x20000,
 570         GRCBASE_NWM             = 0x800000,
 571         GRCBASE_NWS             = 0x700000,
 572         GRCBASE_MS              = 0x6a0000,
 573         GRCBASE_PHY_PCIE        = 0x618000,
 574         GRCBASE_MISC_AEU        = 0x8000,
 575         GRCBASE_BAR0_MAP        = 0x1c00000,
 576         MAX_BLOCK_ADDR
 577 };
 578
 579 enum block_id {
 580         BLOCK_GRC,
 581         BLOCK_MISCS,
 582         BLOCK_MISC,
 583         BLOCK_DBU,
 584         BLOCK_PGLUE_B,
 585         BLOCK_CNIG,
 586         BLOCK_CPMU,
 587         BLOCK_NCSI,
 588         BLOCK_OPTE,
 589         BLOCK_BMB,
 590         BLOCK_PCIE,
 591         BLOCK_MCP,
 592         BLOCK_MCP2,
 593         BLOCK_PSWHST,
 594         BLOCK_PSWHST2,
 595         BLOCK_PSWRD,
 596         BLOCK_PSWRD2,
 597         BLOCK_PSWWR,
 598         BLOCK_PSWWR2,
 599         BLOCK_PSWRQ,
 600         BLOCK_PSWRQ2,
 601         BLOCK_PGLCS,
 602         BLOCK_PTU,
 603         BLOCK_DMAE,
 604         BLOCK_TCM,
 605         BLOCK_MCM,
 606         BLOCK_UCM,
 607         BLOCK_XCM,
 608         BLOCK_YCM,
 609         BLOCK_PCM,
 610         BLOCK_QM,
 611         BLOCK_TM,
 612         BLOCK_DORQ,
 613         BLOCK_BRB,
 614         BLOCK_SRC,
 615         BLOCK_PRS,
 616         BLOCK_TSDM,
 617         BLOCK_MSDM,
 618         BLOCK_USDM,
 619         BLOCK_XSDM,
 620         BLOCK_YSDM,
 621         BLOCK_PSDM,
 622         BLOCK_TSEM,
 623         BLOCK_MSEM,
 624         BLOCK_USEM,
 625         BLOCK_XSEM,
 626         BLOCK_YSEM,
 627         BLOCK_PSEM,
 628         BLOCK_RSS,
 629         BLOCK_TMLD,
 630         BLOCK_MULD,
 631         BLOCK_YULD,
 632         BLOCK_XYLD,
 633         BLOCK_PRM,
 634         BLOCK_PBF_PB1,
 635         BLOCK_PBF_PB2,
 636         BLOCK_RPB,
 637         BLOCK_BTB,
 638         BLOCK_PBF,
 639         BLOCK_RDIF,
 640         BLOCK_TDIF,
 641         BLOCK_CDU,
 642         BLOCK_CCFC,
 643         BLOCK_TCFC,
 644         BLOCK_IGU,
 645         BLOCK_CAU,
 646         BLOCK_UMAC,
 647         BLOCK_XMAC,
 648         BLOCK_DBG,
 649         BLOCK_NIG,
 650         BLOCK_WOL,
 651         BLOCK_BMBN,
 652         BLOCK_IPC,
 653         BLOCK_NWM,
 654         BLOCK_NWS,
 655         BLOCK_MS,
 656         BLOCK_PHY_PCIE,
 657         BLOCK_MISC_AEU,
 658         BLOCK_BAR0_MAP,
 659         MAX_BLOCK_ID
 660 };
 661
 662 enum command_type_bit {
 663         IGU_COMMAND_TYPE_NOP    = 0,
 664         IGU_COMMAND_TYPE_SET    = 1,
 665         MAX_COMMAND_TYPE_BIT
 666 };
 667
 668 struct dmae_cmd {
 669         __le32 opcode;
 670 #define DMAE_CMD_SRC_MASK              0x1
 671 #define DMAE_CMD_SRC_SHIFT             0
 672 #define DMAE_CMD_DST_MASK              0x3
 673 #define DMAE_CMD_DST_SHIFT             1
 674 #define DMAE_CMD_C_DST_MASK            0x1
 675 #define DMAE_CMD_C_DST_SHIFT           3
 676 #define DMAE_CMD_CRC_RESET_MASK        0x1
 677 #define DMAE_CMD_CRC_RESET_SHIFT       4
 678 #define DMAE_CMD_SRC_ADDR_RESET_MASK   0x1
 679 #define DMAE_CMD_SRC_ADDR_RESET_SHIFT  5
 680 #define DMAE_CMD_DST_ADDR_RESET_MASK   0x1
 681 #define DMAE_CMD_DST_ADDR_RESET_SHIFT  6
 682 #define DMAE_CMD_COMP_FUNC_MASK        0x1
 683 #define DMAE_CMD_COMP_FUNC_SHIFT       7
 684 #define DMAE_CMD_COMP_WORD_EN_MASK     0x1
 685 #define DMAE_CMD_COMP_WORD_EN_SHIFT    8
 686 #define DMAE_CMD_COMP_CRC_EN_MASK      0x1
 687 #define DMAE_CMD_COMP_CRC_EN_SHIFT     9
 688 #define DMAE_CMD_COMP_CRC_OFFSET_MASK  0x7
 689 #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
 690 #define DMAE_CMD_RESERVED1_MASK        0x1
 691 #define DMAE_CMD_RESERVED1_SHIFT       13
 692 #define DMAE_CMD_ENDIANITY_MODE_MASK   0x3
 693 #define DMAE_CMD_ENDIANITY_MODE_SHIFT  14
 694 #define DMAE_CMD_ERR_HANDLING_MASK     0x3
 695 #define DMAE_CMD_ERR_HANDLING_SHIFT    16
 696 #define DMAE_CMD_PORT_ID_MASK          0x3
 697 #define DMAE_CMD_PORT_ID_SHIFT         18
 698 #define DMAE_CMD_SRC_PF_ID_MASK        0xF
 699 #define DMAE_CMD_SRC_PF_ID_SHIFT       20
 700 #define DMAE_CMD_DST_PF_ID_MASK        0xF
 701 #define DMAE_CMD_DST_PF_ID_SHIFT       24
 702 #define DMAE_CMD_SRC_VF_ID_VALID_MASK  0x1
 703 #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
 704 #define DMAE_CMD_DST_VF_ID_VALID_MASK  0x1
 705 #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
 706 #define DMAE_CMD_RESERVED2_MASK        0x3
 707 #define DMAE_CMD_RESERVED2_SHIFT       30
 708         __le32  src_addr_lo;
 709         __le32  src_addr_hi;
 710         __le32  dst_addr_lo;
 711         __le32  dst_addr_hi;
 712         __le16  length /* Length in DW */;
 713         __le16  opcode_b;
 714 #define DMAE_CMD_SRC_VF_ID_MASK        0xFF     /* Source VF id */
 715 #define DMAE_CMD_SRC_VF_ID_SHIFT       0
 716 #define DMAE_CMD_DST_VF_ID_MASK        0xFF     /* Destination VF id */
 717 #define DMAE_CMD_DST_VF_ID_SHIFT       8
 718         __le32  comp_addr_lo /* PCIe completion address low or grc address */;
 719         __le32  comp_addr_hi;
 720         __le32  comp_val /* Value to write to copmletion address */;
 721         __le32  crc32 /* crc16 result */;
 722         __le32  crc_32_c /* crc32_c result */;
 723         __le16  crc16 /* crc16 result */;
 724         __le16  crc16_c /* crc16_c result */;
 725         __le16  crc10 /* crc_t10 result */;
 726         __le16  reserved;
 727         __le16  xsum16 /* checksum16 result  */;
 728         __le16  xsum8 /* checksum8 result  */;
 729 };
 730
 731 struct igu_cleanup {
 732         __le32 sb_id_and_flags;
 733 #define IGU_CLEANUP_RESERVED0_MASK     0x7FFFFFF
 734 #define IGU_CLEANUP_RESERVED0_SHIFT    0
 735 #define IGU_CLEANUP_CLEANUP_SET_MASK   0x1 /* cleanup clear - 0, set - 1 */
 736 #define IGU_CLEANUP_CLEANUP_SET_SHIFT  27
 737 #define IGU_CLEANUP_CLEANUP_TYPE_MASK  0x7
 738 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28
 739 #define IGU_CLEANUP_COMMAND_TYPE_MASK  0x1
 740 #define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31
 741         __le32 reserved1;
 742 };
 743
 744 union igu_command {
 745         struct igu_prod_cons_update     prod_cons_update;
 746         struct igu_cleanup              cleanup;
 747 };
 748
 749 struct igu_command_reg_ctrl {
 750         __le16  opaque_fid;
 751         __le16  igu_command_reg_ctrl_fields;
 752 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK  0xFFF
 753 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
 754 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK      0x7
 755 #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT     12
 756 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK  0x1
 757 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15
 758 };
 759
 760 struct igu_mapping_line {
 761         __le32 igu_mapping_line_fields;
 762 #define IGU_MAPPING_LINE_VALID_MASK            0x1
 763 #define IGU_MAPPING_LINE_VALID_SHIFT           0
 764 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK    0xFF
 765 #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT   1
 766 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK  0xFF
 767 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9
 768 #define IGU_MAPPING_LINE_PF_VALID_MASK         0x1      /* PF-1, VF-0 */
 769 #define IGU_MAPPING_LINE_PF_VALID_SHIFT        17
 770 #define IGU_MAPPING_LINE_IPS_GROUP_MASK        0x3F
 771 #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT       18
 772 #define IGU_MAPPING_LINE_RESERVED_MASK         0xFF
 773 #define IGU_MAPPING_LINE_RESERVED_SHIFT        24
 774 };
 775
 776 struct igu_msix_vector {
 777         struct regpair  address;
 778         __le32          data;
 779         __le32          msix_vector_fields;
 780 #define IGU_MSIX_VECTOR_MASK_BIT_MASK      0x1
 781 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT     0
 782 #define IGU_MSIX_VECTOR_RESERVED0_MASK     0x7FFF
 783 #define IGU_MSIX_VECTOR_RESERVED0_SHIFT    1
 784 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK  0xFF
 785 #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16
 786 #define IGU_MSIX_VECTOR_RESERVED1_MASK     0xFF
 787 #define IGU_MSIX_VECTOR_RESERVED1_SHIFT    24
 788 };
 789
 790 enum init_modes {
 791         MODE_BB_A0,
 792         MODE_RESERVED,
 793         MODE_RESERVED2,
 794         MODE_ASIC,
 795         MODE_RESERVED3,
 796         MODE_RESERVED4,
 797         MODE_RESERVED5,
 798         MODE_SF,
 799         MODE_MF_SD,
 800         MODE_MF_SI,
 801         MODE_PORTS_PER_ENG_1,
 802         MODE_PORTS_PER_ENG_2,
 803         MODE_PORTS_PER_ENG_4,
 804         MODE_40G,
 805         MODE_100G,
 806         MODE_EAGLE_ENG1_WORKAROUND,
 807         MAX_INIT_MODES
 808 };
 809
 810 enum init_phases {
 811         PHASE_ENGINE,
 812         PHASE_PORT,
 813         PHASE_PF,
 814         PHASE_RESERVED,
 815         PHASE_QM_PF,
 816         MAX_INIT_PHASES
 817 };
 818
 819 struct mstorm_core_conn_ag_ctx {
 820         u8      byte0 /* cdu_validation */;
 821         u8      byte1 /* state */;
 822         u8      flags0;
 823 #define MSTORM_CORE_CONN_AG_CTX_BIT0_MASK     0x1       /* exist_in_qm0 */
 824 #define MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT    0
 825 #define MSTORM_CORE_CONN_AG_CTX_BIT1_MASK     0x1       /* exist_in_qm1 */
 826 #define MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT    1
 827 #define MSTORM_CORE_CONN_AG_CTX_CF0_MASK      0x3       /* cf0 */
 828 #define MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT     2
 829 #define MSTORM_CORE_CONN_AG_CTX_CF1_MASK      0x3       /* cf1 */
 830 #define MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT     4
 831 #define MSTORM_CORE_CONN_AG_CTX_CF2_MASK      0x3       /* cf2 */
 832 #define MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT     6
 833         u8 flags1;
 834 #define MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK    0x1       /* cf0en */
 835 #define MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT   0
 836 #define MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK    0x1       /* cf1en */
 837 #define MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT   1
 838 #define MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK    0x1       /* cf2en */
 839 #define MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT   2
 840 #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK  0x1       /* rule0en */
 841 #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
 842 #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK  0x1       /* rule1en */
 843 #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
 844 #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK  0x1       /* rule2en */
 845 #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
 846 #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK  0x1       /* rule3en */
 847 #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
 848 #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK  0x1       /* rule4en */
 849 #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
 850         __le16  word0 /* word0 */;
 851         __le16  word1 /* word1 */;
 852         __le32  reg0 /* reg0 */;
 853         __le32  reg1 /* reg1 */;
 854 };
 855
 856 /* per encapsulation type enabling flags */
 857 struct prs_reg_encapsulation_type_en {
 858         u8 flags;
 859 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK     0x1
 860 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT    0
 861 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK      0x1
 862 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT     1
 863 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK            0x1
 864 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT           2
 865 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK            0x1
 866 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT           3
 867 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK  0x1
 868 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4
 869 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK   0x1
 870 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT  5
 871 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK                0x3
 872 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT               6
 873 };
 874
 875 enum pxp_tph_st_hint {
 876         TPH_ST_HINT_BIDIR /* Read/Write access by Host and Device */,
 877         TPH_ST_HINT_REQUESTER /* Read/Write access by Device */,
 878         TPH_ST_HINT_TARGET,
 879         TPH_ST_HINT_TARGET_PRIO,
 880         MAX_PXP_TPH_ST_HINT
 881 };
 882
 883 /* QM hardware structure of enable bypass credit mask */
 884 struct qm_rf_bypass_mask {
 885         u8 flags;
 886 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK    0x1
 887 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT   0
 888 #define QM_RF_BYPASS_MASK_RESERVED0_MASK  0x1
 889 #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1
 890 #define QM_RF_BYPASS_MASK_PFWFQ_MASK      0x1
 891 #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT     2
 892 #define QM_RF_BYPASS_MASK_VPWFQ_MASK      0x1
 893 #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT     3
 894 #define QM_RF_BYPASS_MASK_PFRL_MASK       0x1
 895 #define QM_RF_BYPASS_MASK_PFRL_SHIFT      4
 896 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK    0x1
 897 #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT   5
 898 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK    0x1
 899 #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT   6
 900 #define QM_RF_BYPASS_MASK_RESERVED1_MASK  0x1
 901 #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7
 902 };
 903
 904 /* QM hardware structure of opportunistic credit mask */
 905 struct qm_rf_opportunistic_mask {
 906         __le16 flags;
 907 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK     0x1
 908 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT    0
 909 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK     0x1
 910 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT    1
 911 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK       0x1
 912 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT      2
 913 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK       0x1
 914 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT      3
 915 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK        0x1
 916 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT       4
 917 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK     0x1
 918 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT    5
 919 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK     0x1
 920 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT    6
 921 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK   0x1
 922 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT  7
 923 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK  0x1
 924 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8
 925 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK   0x7F
 926 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT  9
 927 };
 928
 929 /* QM hardware structure of QM map memory */
 930 struct qm_rf_pq_map {
 931         u32 reg;
 932 #define QM_RF_PQ_MAP_PQ_VALID_MASK          0x1         /* PQ active */
 933 #define QM_RF_PQ_MAP_PQ_VALID_SHIFT         0
 934 #define QM_RF_PQ_MAP_RL_ID_MASK             0xFF        /* RL ID */
 935 #define QM_RF_PQ_MAP_RL_ID_SHIFT            1
 936 #define QM_RF_PQ_MAP_VP_PQ_ID_MASK          0x1FF
 937 #define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT         9
 938 #define QM_RF_PQ_MAP_VOQ_MASK               0x1F        /* VOQ */
 939 #define QM_RF_PQ_MAP_VOQ_SHIFT              18
 940 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK  0x3         /* WRR weight */
 941 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT 23
 942 #define QM_RF_PQ_MAP_RL_VALID_MASK          0x1         /* RL active */
 943 #define QM_RF_PQ_MAP_RL_VALID_SHIFT         25
 944 #define QM_RF_PQ_MAP_RESERVED_MASK          0x3F
 945 #define QM_RF_PQ_MAP_RESERVED_SHIFT         26
 946 };
 947
 948 /* SDM operation gen command (generate aggregative interrupt) */
 949 struct sdm_op_gen {
 950         __le32 command;
 951 #define SDM_OP_GEN_COMP_PARAM_MASK  0xFFFF      /* completion parameters 0-15 */
 952 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
 953 #define SDM_OP_GEN_COMP_TYPE_MASK   0xF         /* completion type 16-19 */
 954 #define SDM_OP_GEN_COMP_TYPE_SHIFT  16
 955 #define SDM_OP_GEN_RESERVED_MASK    0xFFF       /* reserved 20-31 */
 956 #define SDM_OP_GEN_RESERVED_SHIFT   20
 957 };
 958
 959 struct tstorm_core_conn_ag_ctx {
 960         u8      byte0 /* cdu_validation */;
 961         u8      byte1 /* state */;
 962         u8      flags0;
 963 #define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK     0x1       /* exist_in_qm0 */
 964 #define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT    0
 965 #define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK     0x1       /* exist_in_qm1 */
 966 #define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT    1
 967 #define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK     0x1       /* bit2 */
 968 #define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT    2
 969 #define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK     0x1       /* bit3 */
 970 #define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT    3
 971 #define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK     0x1       /* bit4 */
 972 #define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT    4
 973 #define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK     0x1       /* bit5 */
 974 #define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT    5
 975 #define TSTORM_CORE_CONN_AG_CTX_CF0_MASK      0x3       /* timer0cf */
 976 #define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT     6
 977         u8 flags1;
 978 #define TSTORM_CORE_CONN_AG_CTX_CF1_MASK      0x3       /* timer1cf */
 979 #define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT     0
 980 #define TSTORM_CORE_CONN_AG_CTX_CF2_MASK      0x3       /* timer2cf */
 981 #define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT     2
 982 #define TSTORM_CORE_CONN_AG_CTX_CF3_MASK      0x3       /* timer_stop_all */
 983 #define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT     4
 984 #define TSTORM_CORE_CONN_AG_CTX_CF4_MASK      0x3       /* cf4 */
 985 #define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT     6
 986         u8 flags2;
 987 #define TSTORM_CORE_CONN_AG_CTX_CF5_MASK      0x3       /* cf5 */
 988 #define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT     0
 989 #define TSTORM_CORE_CONN_AG_CTX_CF6_MASK      0x3       /* cf6 */
 990 #define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT     2
 991 #define TSTORM_CORE_CONN_AG_CTX_CF7_MASK      0x3       /* cf7 */
 992 #define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT     4
 993 #define TSTORM_CORE_CONN_AG_CTX_CF8_MASK      0x3       /* cf8 */
 994 #define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT     6
 995         u8 flags3;
 996 #define TSTORM_CORE_CONN_AG_CTX_CF9_MASK      0x3       /* cf9 */
 997 #define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT     0
 998 #define TSTORM_CORE_CONN_AG_CTX_CF10_MASK     0x3       /* cf10 */
 999 #define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT    2
1000 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK    0x1       /* cf0en */
1001 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT   4
1002 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK    0x1       /* cf1en */
1003 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT   5
1004 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK    0x1       /* cf2en */
1005 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT   6
1006 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK    0x1       /* cf3en */
1007 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT   7
1008         u8 flags4;
1009 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK    0x1       /* cf4en */
1010 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT   0
1011 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK    0x1       /* cf5en */
1012 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT   1
1013 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK    0x1       /* cf6en */
1014 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT   2
1015 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK    0x1       /* cf7en */
1016 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT   3
1017 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK    0x1       /* cf8en */
1018 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT   4
1019 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK    0x1       /* cf9en */
1020 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT   5
1021 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK   0x1       /* cf10en */
1022 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT  6
1023 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK  0x1       /* rule0en */
1024 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
1025         u8 flags5;
1026 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK  0x1       /* rule1en */
1027 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
1028 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK  0x1       /* rule2en */
1029 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
1030 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK  0x1       /* rule3en */
1031 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
1032 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK  0x1       /* rule4en */
1033 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
1034 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK  0x1       /* rule5en */
1035 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
1036 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK  0x1       /* rule6en */
1037 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
1038 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK  0x1       /* rule7en */
1039 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
1040 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK  0x1       /* rule8en */
1041 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
1042         __le32  reg0 /* reg0 */;
1043         __le32  reg1 /* reg1 */;
1044         __le32  reg2 /* reg2 */;
1045         __le32  reg3 /* reg3 */;
1046         __le32  reg4 /* reg4 */;
1047         __le32  reg5 /* reg5 */;
1048         __le32  reg6 /* reg6 */;
1049         __le32  reg7 /* reg7 */;
1050         __le32  reg8 /* reg8 */;
1051         u8      byte2 /* byte2 */;
1052         u8      byte3 /* byte3 */;
1053         __le16  word0 /* word0 */;
1054         u8      byte4 /* byte4 */;
1055         u8      byte5 /* byte5 */;
1056         __le16  word1 /* word1 */;
1057         __le16  word2 /* conn_dpi */;
1058         __le16  word3 /* word3 */;
1059         __le32  reg9 /* reg9 */;
1060         __le32  reg10 /* reg10 */;
1061 };
1062
1063 struct ustorm_core_conn_ag_ctx {
1064         u8      reserved /* cdu_validation */;
1065         u8      byte1 /* state */;
1066         u8      flags0;
1067 #define USTORM_CORE_CONN_AG_CTX_BIT0_MASK     0x1       /* exist_in_qm0 */
1068 #define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT    0
1069 #define USTORM_CORE_CONN_AG_CTX_BIT1_MASK     0x1       /* exist_in_qm1 */
1070 #define USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT    1
1071 #define USTORM_CORE_CONN_AG_CTX_CF0_MASK      0x3       /* timer0cf */
1072 #define USTORM_CORE_CONN_AG_CTX_CF0_SHIFT     2
1073 #define USTORM_CORE_CONN_AG_CTX_CF1_MASK      0x3       /* timer1cf */
1074 #define USTORM_CORE_CONN_AG_CTX_CF1_SHIFT     4
1075 #define USTORM_CORE_CONN_AG_CTX_CF2_MASK      0x3       /* timer2cf */
1076 #define USTORM_CORE_CONN_AG_CTX_CF2_SHIFT     6
1077         u8 flags1;
1078 #define USTORM_CORE_CONN_AG_CTX_CF3_MASK      0x3       /* timer_stop_all */
1079 #define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT     0
1080 #define USTORM_CORE_CONN_AG_CTX_CF4_MASK      0x3       /* cf4 */
1081 #define USTORM_CORE_CONN_AG_CTX_CF4_SHIFT     2
1082 #define USTORM_CORE_CONN_AG_CTX_CF5_MASK      0x3       /* cf5 */
1083 #define USTORM_CORE_CONN_AG_CTX_CF5_SHIFT     4
1084 #define USTORM_CORE_CONN_AG_CTX_CF6_MASK      0x3       /* cf6 */
1085 #define USTORM_CORE_CONN_AG_CTX_CF6_SHIFT     6
1086         u8 flags2;
1087 #define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK    0x1       /* cf0en */
1088 #define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT   0
1089 #define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK    0x1       /* cf1en */
1090 #define USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT   1
1091 #define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK    0x1       /* cf2en */
1092 #define USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT   2
1093 #define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK    0x1       /* cf3en */
1094 #define USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT   3
1095 #define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK    0x1       /* cf4en */
1096 #define USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT   4
1097 #define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK    0x1       /* cf5en */
1098 #define USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT   5
1099 #define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK    0x1       /* cf6en */
1100 #define USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT   6
1101 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK  0x1       /* rule0en */
1102 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
1103         u8 flags3;
1104 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK  0x1       /* rule1en */
1105 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
1106 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK  0x1       /* rule2en */
1107 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
1108 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK  0x1       /* rule3en */
1109 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
1110 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK  0x1       /* rule4en */
1111 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
1112 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK  0x1       /* rule5en */
1113 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
1114 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK  0x1       /* rule6en */
1115 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
1116 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK  0x1       /* rule7en */
1117 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
1118 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK  0x1       /* rule8en */
1119 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
1120         u8      byte2 /* byte2 */;
1121         u8      byte3 /* byte3 */;
1122         __le16  word0 /* conn_dpi */;
1123         __le16  word1 /* word1 */;
1124         __le32  rx_producers /* reg0 */;
1125         __le32  reg1 /* reg1 */;
1126         __le32  reg2 /* reg2 */;
1127         __le32  reg3 /* reg3 */;
1128         __le16  word2 /* word2 */;
1129         __le16  word3 /* word3 */;
1130 };
1131
1132 struct ystorm_core_conn_ag_ctx {
1133         u8      byte0 /* cdu_validation */;
1134         u8      byte1 /* state */;
1135         u8      flags0;
1136 #define YSTORM_CORE_CONN_AG_CTX_BIT0_MASK     0x1       /* exist_in_qm0 */
1137 #define YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT    0
1138 #define YSTORM_CORE_CONN_AG_CTX_BIT1_MASK     0x1       /* exist_in_qm1 */
1139 #define YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT    1
1140 #define YSTORM_CORE_CONN_AG_CTX_CF0_MASK      0x3       /* cf0 */
1141 #define YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT     2
1142 #define YSTORM_CORE_CONN_AG_CTX_CF1_MASK      0x3       /* cf1 */
1143 #define YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT     4
1144 #define YSTORM_CORE_CONN_AG_CTX_CF2_MASK      0x3       /* cf2 */
1145 #define YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT     6
1146         u8 flags1;
1147 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK    0x1       /* cf0en */
1148 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT   0
1149 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK    0x1       /* cf1en */
1150 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT   1
1151 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK    0x1       /* cf2en */
1152 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT   2
1153 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK  0x1       /* rule0en */
1154 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
1155 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK  0x1       /* rule1en */
1156 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
1157 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK  0x1       /* rule2en */
1158 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
1159 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK  0x1       /* rule3en */
1160 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
1161 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK  0x1       /* rule4en */
1162 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
1163         u8      byte2 /* byte2 */;
1164         u8      byte3 /* byte3 */;
1165         __le16  word0 /* word0 */;
1166         __le32  reg0 /* reg0 */;
1167         __le32  reg1 /* reg1 */;
1168         __le16  word1 /* word1 */;
1169         __le16  word2 /* word2 */;
1170         __le16  word3 /* word3 */;
1171         __le16  word4 /* word4 */;
1172         __le32  reg2 /* reg2 */;
1173         __le32  reg3 /* reg3 */;
1174 };
1175
1176 /*********************************** Init ************************************/
1177
1178 /* Width of GRC address in bits (addresses are specified in dwords) */
1179 #define GRC_ADDR_BITS                   23
1180 #define MAX_GRC_ADDR                    ((1 << GRC_ADDR_BITS) - 1)
1181
1182 /* indicates an init that should be applied to any phase ID */
1183 #define ANY_PHASE_ID                    0xffff
1184
1185 /* init pattern size in bytes */
1186 #define INIT_PATTERN_SIZE_BITS  4
1187 #define MAX_INIT_PATTERN_SIZE   BIT(INIT_PATTERN_SIZE_BITS)
1188
1189 /* Max size in dwords of a zipped array */
1190 #define MAX_ZIPPED_SIZE                 8192
1191
1192 /* Global PXP window */
1193 #define NUM_OF_PXP_WIN                  19
1194 #define PXP_WIN_DWORD_SIZE_BITS 10
1195 #define PXP_WIN_DWORD_SIZE              BIT(PXP_WIN_DWORD_SIZE_BITS)
1196 #define PXP_WIN_BYTE_SIZE_BITS  (PXP_WIN_DWORD_SIZE_BITS + 2)
1197 #define PXP_WIN_BYTE_SIZE               (PXP_WIN_DWORD_SIZE * 4)
1198
1199 /********************************* GRC Dump **********************************/
1200
1201 /* width of GRC dump register sequence length in bits */
1202 #define DUMP_SEQ_LEN_BITS                       8
1203 #define DUMP_SEQ_LEN_MAX_VAL            ((1 << DUMP_SEQ_LEN_BITS) - 1)
1204
1205 /* width of GRC dump memory length in bits */
1206 #define DUMP_MEM_LEN_BITS                       18
1207 #define DUMP_MEM_LEN_MAX_VAL            ((1 << DUMP_MEM_LEN_BITS) - 1)
1208
1209 /* width of register type ID in bits */
1210 #define REG_TYPE_ID_BITS                        6
1211 #define REG_TYPE_ID_MAX_VAL                     ((1 << REG_TYPE_ID_BITS) - 1)
1212
1213 /* width of block ID in bits */
1214 #define BLOCK_ID_BITS                           8
1215 #define BLOCK_ID_MAX_VAL                        ((1 << BLOCK_ID_BITS) - 1)
1216
1217 /******************************** Idle Check *********************************/
1218
1219 /* max number of idle check predicate immediates */
1220 #define MAX_IDLE_CHK_PRED_IMM           3
1221
1222 /* max number of idle check argument registers */
1223 #define MAX_IDLE_CHK_READ_REGS          3
1224
1225 /* max number of idle check loops */
1226 #define MAX_IDLE_CHK_LOOPS                      0x10000
1227
1228 /* max idle check address increment */
1229 #define MAX_IDLE_CHK_INCREMENT          0x10000
1230
1231 /* inicates an undefined idle check line index */
1232 #define IDLE_CHK_UNDEFINED_LINE_IDX     0xffffff
1233
1234 /* max number of register values following the idle check header */
1235 #define IDLE_CHK_MAX_DUMP_REGS          2
1236
1237 /* arguments for IDLE_CHK_MACRO_TYPE_QM_RD_WR */
1238 #define IDLE_CHK_QM_RD_WR_PTR           0
1239 #define IDLE_CHK_QM_RD_WR_BANK          1
1240
1241 /**************************************/
1242 /* HSI Functions constants and macros */
1243 /**************************************/
1244
1245 /* Number of VLAN priorities */
1246 #define NUM_OF_VLAN_PRIORITIES                  8
1247
1248 /* the MCP Trace meta data signautre is duplicated in the perl script that
1249  * generats the NVRAM images.
1250  */
1251 #define MCP_TRACE_META_IMAGE_SIGNATURE  0x669955aa
1252
1253 /* Binary buffer header */
1254 struct bin_buffer_hdr {
1255         u32     offset;
1256         u32     length /* buffer length in bytes */;
1257 };
1258
1259 /* binary buffer types */
1260 enum bin_buffer_type {
1261         BIN_BUF_FW_VER_INFO /* fw_ver_info struct */,
1262         BIN_BUF_INIT_CMD /* init commands */,
1263         BIN_BUF_INIT_VAL /* init data */,
1264         BIN_BUF_INIT_MODE_TREE /* init modes tree */,
1265         BIN_BUF_IRO /* internal RAM offsets array */,
1266         MAX_BIN_BUFFER_TYPE
1267 };
1268
1269 /* Chip IDs */
1270 enum chip_ids {
1271         CHIP_BB_A0 /* BB A0 chip ID */,
1272         CHIP_BB_B0 /* BB B0 chip ID */,
1273         CHIP_K2 /* AH chip ID */,
1274         MAX_CHIP_IDS
1275 };
1276
1277 enum idle_chk_severity_types {
1278         IDLE_CHK_SEVERITY_ERROR /* idle check failure should cause an error */,
1279         IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC,
1280         IDLE_CHK_SEVERITY_WARNING,
1281         MAX_IDLE_CHK_SEVERITY_TYPES
1282 };
1283
1284 struct init_array_raw_hdr {
1285         __le32 data;
1286 #define INIT_ARRAY_RAW_HDR_TYPE_MASK    0xF
1287 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT   0
1288 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK  0xFFFFFFF       /* init array params */
1289 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
1290 };
1291
1292 struct init_array_standard_hdr {
1293         __le32 data;
1294 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK  0xF
1295 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
1296 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK  0xFFFFFFF
1297 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
1298 };
1299
1300 struct init_array_zipped_hdr {
1301         __le32 data;
1302 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK         0xF
1303 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT        0
1304 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK  0xFFFFFFF
1305 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
1306 };
1307
1308 struct init_array_pattern_hdr {
1309         __le32 data;
1310 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK          0xF
1311 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT         0
1312 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK  0xF
1313 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
1314 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK   0xFFFFFF
1315 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT  8
1316 };
1317
1318 union init_array_hdr {
1319         struct init_array_raw_hdr       raw /* raw init array header */;
1320         struct init_array_standard_hdr  standard;
1321         struct init_array_zipped_hdr    zipped /* zipped init array header */;
1322         struct init_array_pattern_hdr   pattern /* pattern init array header */;
1323 };
1324
1325 enum init_array_types {
1326         INIT_ARR_STANDARD /* standard init array */,
1327         INIT_ARR_ZIPPED /* zipped init array */,
1328         INIT_ARR_PATTERN /* a repeated pattern */,
1329         MAX_INIT_ARRAY_TYPES
1330 };
1331
1332 /* init operation: callback */
1333 struct init_callback_op {
1334         __le32  op_data;
1335 #define INIT_CALLBACK_OP_OP_MASK        0xF
1336 #define INIT_CALLBACK_OP_OP_SHIFT       0
1337 #define INIT_CALLBACK_OP_RESERVED_MASK  0xFFFFFFF
1338 #define INIT_CALLBACK_OP_RESERVED_SHIFT 4
1339         __le16  callback_id /* Callback ID */;
1340         __le16  block_id /* Blocks ID */;
1341 };
1342
1343 /* init comparison types */
1344 enum init_comparison_types {
1345         INIT_COMPARISON_EQ /* init value is included in the init command */,
1346         INIT_COMPARISON_OR /* init value is all zeros */,
1347         INIT_COMPARISON_AND /* init value is an array of values */,
1348         MAX_INIT_COMPARISON_TYPES
1349 };
1350
1351 /* init operation: delay */
1352 struct init_delay_op {
1353         __le32  op_data;
1354 #define INIT_DELAY_OP_OP_MASK        0xF
1355 #define INIT_DELAY_OP_OP_SHIFT       0
1356 #define INIT_DELAY_OP_RESERVED_MASK  0xFFFFFFF
1357 #define INIT_DELAY_OP_RESERVED_SHIFT 4
1358         __le32  delay /* delay in us */;
1359 };
1360
1361 /* init operation: if_mode */
1362 struct init_if_mode_op {
1363         __le32 op_data;
1364 #define INIT_IF_MODE_OP_OP_MASK          0xF
1365 #define INIT_IF_MODE_OP_OP_SHIFT         0
1366 #define INIT_IF_MODE_OP_RESERVED1_MASK   0xFFF
1367 #define INIT_IF_MODE_OP_RESERVED1_SHIFT  4
1368 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK  0xFFFF
1369 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
1370         __le16  reserved2;
1371         __le16  modes_buf_offset;
1372 };
1373
1374 /*  init operation: if_phase */
1375 struct init_if_phase_op {
1376         __le32 op_data;
1377 #define INIT_IF_PHASE_OP_OP_MASK           0xF
1378 #define INIT_IF_PHASE_OP_OP_SHIFT          0
1379 #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK  0x1
1380 #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
1381 #define INIT_IF_PHASE_OP_RESERVED1_MASK    0x7FF
1382 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT   5
1383 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK   0xFFFF
1384 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT  16
1385         __le32 phase_data;
1386 #define INIT_IF_PHASE_OP_PHASE_MASK        0xFF /* Init phase */
1387 #define INIT_IF_PHASE_OP_PHASE_SHIFT       0
1388 #define INIT_IF_PHASE_OP_RESERVED2_MASK    0xFF
1389 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT   8
1390 #define INIT_IF_PHASE_OP_PHASE_ID_MASK     0xFFFF /* Init phase ID */
1391 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT    16
1392 };
1393
1394 /* init mode operators */
1395 enum init_mode_ops {
1396         INIT_MODE_OP_NOT /* init mode not operator */,
1397         INIT_MODE_OP_OR /* init mode or operator */,
1398         INIT_MODE_OP_AND /* init mode and operator */,
1399         MAX_INIT_MODE_OPS
1400 };
1401
1402 /* init operation: raw */
1403 struct init_raw_op {
1404         __le32  op_data;
1405 #define INIT_RAW_OP_OP_MASK      0xF
1406 #define INIT_RAW_OP_OP_SHIFT     0
1407 #define INIT_RAW_OP_PARAM1_MASK  0xFFFFFFF      /* init param 1 */
1408 #define INIT_RAW_OP_PARAM1_SHIFT 4
1409         __le32  param2 /* Init param 2 */;
1410 };
1411
1412 /* init array params */
1413 struct init_op_array_params {
1414         __le16  size /* array size in dwords */;
1415         __le16  offset /* array start offset in dwords */;
1416 };
1417
1418 /* Write init operation arguments */
1419 union init_write_args {
1420         __le32                          inline_val;
1421         __le32                          zeros_count;
1422         __le32                          array_offset;
1423         struct init_op_array_params     runtime;
1424 };
1425
1426 /* init operation: write */
1427 struct init_write_op {
1428         __le32 data;
1429 #define INIT_WRITE_OP_OP_MASK        0xF
1430 #define INIT_WRITE_OP_OP_SHIFT       0
1431 #define INIT_WRITE_OP_SOURCE_MASK    0x7
1432 #define INIT_WRITE_OP_SOURCE_SHIFT   4
1433 #define INIT_WRITE_OP_RESERVED_MASK  0x1
1434 #define INIT_WRITE_OP_RESERVED_SHIFT 7
1435 #define INIT_WRITE_OP_WIDE_BUS_MASK  0x1
1436 #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
1437 #define INIT_WRITE_OP_ADDRESS_MASK   0x7FFFFF
1438 #define INIT_WRITE_OP_ADDRESS_SHIFT  9
1439         union init_write_args args /* Write init operation arguments */;
1440 };
1441
1442 /* init operation: read */
1443 struct init_read_op {
1444         __le32 op_data;
1445 #define INIT_READ_OP_OP_MASK         0xF
1446 #define INIT_READ_OP_OP_SHIFT        0
1447 #define INIT_READ_OP_POLL_COMP_MASK  0x7
1448 #define INIT_READ_OP_POLL_COMP_SHIFT 4
1449 #define INIT_READ_OP_RESERVED_MASK   0x1
1450 #define INIT_READ_OP_RESERVED_SHIFT  7
1451 #define INIT_READ_OP_POLL_MASK       0x1
1452 #define INIT_READ_OP_POLL_SHIFT      8
1453 #define INIT_READ_OP_ADDRESS_MASK    0x7FFFFF
1454 #define INIT_READ_OP_ADDRESS_SHIFT   9
1455         __le32 expected_val;
1456 };
1457
1458 /* Init operations union */
1459 union init_op {
1460         struct init_raw_op      raw /* raw init operation */;
1461         struct init_write_op    write /* write init operation */;
1462         struct init_read_op     read /* read init operation */;
1463         struct init_if_mode_op  if_mode /* if_mode init operation */;
1464         struct init_if_phase_op if_phase /* if_phase init operation */;
1465         struct init_callback_op callback /* callback init operation */;
1466         struct init_delay_op    delay /* delay init operation */;
1467 };
1468
1469 /* Init command operation types */
1470 enum init_op_types {
1471         INIT_OP_READ /* GRC read init command */,
1472         INIT_OP_WRITE /* GRC write init command */,
1473         INIT_OP_IF_MODE,
1474         INIT_OP_IF_PHASE,
1475         INIT_OP_DELAY /* delay init command */,
1476         INIT_OP_CALLBACK /* callback init command */,
1477         MAX_INIT_OP_TYPES
1478 };
1479
1480 /* init source types */
1481 enum init_source_types {
1482         INIT_SRC_INLINE /* init value is included in the init command */,
1483         INIT_SRC_ZEROS /* init value is all zeros */,
1484         INIT_SRC_ARRAY /* init value is an array of values */,
1485         INIT_SRC_RUNTIME /* init value is provided during runtime */,
1486         MAX_INIT_SOURCE_TYPES
1487 };
1488
1489 /* Internal RAM Offsets macro data */
1490 struct iro {
1491         u32     base /* RAM field offset */;
1492         u16     m1 /* multiplier 1 */;
1493         u16     m2 /* multiplier 2 */;
1494         u16     m3 /* multiplier 3 */;
1495         u16     size /* RAM field size */;
1496 };
1497
1498 /* QM per-port init parameters */
1499 struct init_qm_port_params {
1500         u8      active /* Indicates if this port is active */;
1501         u8      num_active_phys_tcs;
1502         u16     num_pbf_cmd_lines;
1503         u16     num_btb_blocks;
1504         __le16  reserved;
1505 };
1506
1507 /* QM per-PQ init parameters */
1508 struct init_qm_pq_params {
1509         u8      vport_id /* VPORT ID */;
1510         u8      tc_id /* TC ID */;
1511         u8      wrr_group /* WRR group */;
1512         u8      reserved;
1513 };
1514
1515 /* QM per-vport init parameters */
1516 struct init_qm_vport_params {
1517         u32     vport_rl;
1518         u16     vport_wfq;
1519         u16     first_tx_pq_id[NUM_OF_TCS];
1520 };
1521
1522 /* Win 2 */
1523 #define GTT_BAR0_MAP_REG_IGU_CMD \
1524         0x00f000UL
1525 /* Win 3 */
1526 #define GTT_BAR0_MAP_REG_TSDM_RAM \
1527         0x010000UL
1528 /* Win 4 */
1529 #define GTT_BAR0_MAP_REG_MSDM_RAM \
1530         0x011000UL
1531 /* Win 5 */
1532 #define GTT_BAR0_MAP_REG_MSDM_RAM_1024 \
1533         0x012000UL
1534 /* Win 6 */
1535 #define GTT_BAR0_MAP_REG_USDM_RAM \
1536         0x013000UL
1537 /* Win 7 */
1538 #define GTT_BAR0_MAP_REG_USDM_RAM_1024 \
1539         0x014000UL
1540 /* Win 8 */
1541 #define GTT_BAR0_MAP_REG_USDM_RAM_2048 \
1542         0x015000UL
1543 /* Win 9 */
1544 #define GTT_BAR0_MAP_REG_XSDM_RAM \
1545         0x016000UL
1546 /* Win 10 */
1547 #define GTT_BAR0_MAP_REG_YSDM_RAM \
1548         0x017000UL
1549 /* Win 11 */
1550 #define GTT_BAR0_MAP_REG_PSDM_RAM \
1551         0x018000UL
1552
1553 /**
1554  * @brief qed_qm_pf_mem_size - prepare QM ILT sizes
1555  *
1556  * Returns the required host memory size in 4KB units.
1557  * Must be called before all QM init HSI functions.
1558  *
1559  * @param pf_id                 - physical function ID
1560  * @param num_pf_cids   - number of connections used by this PF
1561  * @param num_vf_cids   - number of connections used by VFs of this PF
1562  * @param num_tids              - number of tasks used by this PF
1563  * @param num_pf_pqs    - number of PQs used by this PF
1564  * @param num_vf_pqs    - number of PQs used by VFs of this PF
1565  *
1566  * @return The required host memory size in 4KB units.
1567  */
1568 u32 qed_qm_pf_mem_size(u8       pf_id,
1569                        u32      num_pf_cids,
1570                        u32      num_vf_cids,
1571                        u32      num_tids,
1572                        u16      num_pf_pqs,
1573                        u16      num_vf_pqs);
1574
1575 struct qed_qm_common_rt_init_params {
1576         u8                              max_ports_per_engine;
1577         u8                              max_phys_tcs_per_port;
1578         bool                            pf_rl_en;
1579         bool                            pf_wfq_en;
1580         bool                            vport_rl_en;
1581         bool                            vport_wfq_en;
1582         struct init_qm_port_params      *port_params;
1583 };
1584
1585 /**
1586  * @brief qed_qm_common_rt_init - Prepare QM runtime init values for the
1587  * engine phase.
1588  *
1589  * @param p_hwfn
1590  * @param max_ports_per_engine  - max number of ports per engine in HW
1591  * @param max_phys_tcs_per_port - max number of physical TCs per port in HW
1592  * @param pf_rl_en                              - enable per-PF rate limiters
1593  * @param pf_wfq_en                             - enable per-PF WFQ
1594  * @param vport_rl_en                   - enable per-VPORT rate limiters
1595  * @param vport_wfq_en                  - enable per-VPORT WFQ
1596  * @param port_params                   - array of size MAX_NUM_PORTS with
1597  *                                              arameters for each port
1598  *
1599  * @return 0 on success, -1 on error.
1600  */
1601 int qed_qm_common_rt_init(
1602         struct qed_hwfn                         *p_hwfn,
1603         struct qed_qm_common_rt_init_params     *p_params);
1604
1605 struct qed_qm_pf_rt_init_params {
1606         u8                              port_id;
1607         u8                              pf_id;
1608         u8                              max_phys_tcs_per_port;
1609         bool                            is_first_pf;
1610         u32                             num_pf_cids;
1611         u32                             num_vf_cids;
1612         u32                             num_tids;
1613         u16                             start_pq;
1614         u16                             num_pf_pqs;
1615         u16                             num_vf_pqs;
1616         u8                              start_vport;
1617         u8                              num_vports;
1618         u8                              pf_wfq;
1619         u32                             pf_rl;
1620         struct init_qm_pq_params        *pq_params;
1621         struct init_qm_vport_params     *vport_params;
1622 };
1623
1624 int qed_qm_pf_rt_init(struct qed_hwfn                   *p_hwfn,
1625                       struct qed_ptt                    *p_ptt,
1626                       struct qed_qm_pf_rt_init_params   *p_params);
1627
1628 /**
1629  * @brief qed_init_pf_rl  Initializes the rate limit of the specified PF
1630  *
1631  * @param p_hwfn
1632  * @param p_ptt - ptt window used for writing the registers
1633  * @param pf_id - PF ID
1634  * @param pf_rl - rate limit in Mb/sec units
1635  *
1636  * @return 0 on success, -1 on error.
1637  */
1638 int qed_init_pf_rl(struct qed_hwfn      *p_hwfn,
1639                    struct qed_ptt       *p_ptt,
1640                    u8                   pf_id,
1641                    u32                  pf_rl);
1642
1643 /**
1644  * @brief qed_init_vport_rl  Initializes the rate limit of the specified VPORT
1645  *
1646  * @param p_hwfn
1647  * @param p_ptt         - ptt window used for writing the registers
1648  * @param vport_id      - VPORT ID
1649  * @param vport_rl      - rate limit in Mb/sec units
1650  *
1651  * @return 0 on success, -1 on error.
1652  */
1653
1654 int qed_init_vport_rl(struct qed_hwfn   *p_hwfn,
1655                       struct qed_ptt    *p_ptt,
1656                       u8                vport_id,
1657                       u32               vport_rl);
1658 /**
1659  * @brief qed_send_qm_stop_cmd  Sends a stop command to the QM
1660  *
1661  * @param p_hwfn
1662  * @param p_ptt          - ptt window used for writing the registers
1663  * @param is_release_cmd - true for release, false for stop.
1664  * @param is_tx_pq       - true for Tx PQs, false for Other PQs.
1665  * @param start_pq       - first PQ ID to stop
1666  * @param num_pqs        - Number of PQs to stop, starting from start_pq.
1667  *
1668  * @return bool, true if successful, false if timeout occurred while waiting
1669  *                                      for QM command done.
1670  */
1671
1672 bool qed_send_qm_stop_cmd(struct qed_hwfn       *p_hwfn,
1673                           struct qed_ptt        *p_ptt,
1674                           bool                  is_release_cmd,
1675                           bool                  is_tx_pq,
1676                           u16                   start_pq,
1677                           u16                   num_pqs);
1678
1679 /* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */
1680 #define YSTORM_FLOW_CONTROL_MODE_OFFSET                 (IRO[0].base)
1681 #define YSTORM_FLOW_CONTROL_MODE_SIZE                   (IRO[0].size)
1682 /* Tstorm port statistics */
1683 #define TSTORM_PORT_STAT_OFFSET(port_id)                (IRO[1].base + \
1684                                                          ((port_id) * \
1685                                                           IRO[1].m1))
1686 #define TSTORM_PORT_STAT_SIZE                           (IRO[1].size)
1687 /* Ustorm VF-PF Channel ready flag */
1688 #define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id)        (IRO[2].base +  \
1689                                                          ((vf_id) *     \
1690                                                           IRO[2].m1))
1691 #define USTORM_VF_PF_CHANNEL_READY_SIZE                 (IRO[2].size)
1692 /* Ustorm Final flr cleanup ack */
1693 #define USTORM_FLR_FINAL_ACK_OFFSET                     (IRO[3].base)
1694 #define USTORM_FLR_FINAL_ACK_SIZE                       (IRO[3].size)
1695 /* Ustorm Event ring consumer */
1696 #define USTORM_EQE_CONS_OFFSET(pf_id)                   (IRO[4].base +  \
1697                                                          ((pf_id) *     \
1698                                                           IRO[4].m1))
1699 #define USTORM_EQE_CONS_SIZE                            (IRO[4].size)
1700 /* Ustorm Completion ring consumer */
1701 #define USTORM_CQ_CONS_OFFSET(global_queue_id)          (IRO[5].base +  \
1702                                                          ((global_queue_id) * \
1703                                                           IRO[5].m1))
1704 #define USTORM_CQ_CONS_SIZE                             (IRO[5].size)
1705 /* Xstorm Integration Test Data */
1706 #define XSTORM_INTEG_TEST_DATA_OFFSET                   (IRO[6].base)
1707 #define XSTORM_INTEG_TEST_DATA_SIZE                     (IRO[6].size)
1708 /* Ystorm Integration Test Data */
1709 #define YSTORM_INTEG_TEST_DATA_OFFSET                   (IRO[7].base)
1710 #define YSTORM_INTEG_TEST_DATA_SIZE                     (IRO[7].size)
1711 /* Pstorm Integration Test Data */
1712 #define PSTORM_INTEG_TEST_DATA_OFFSET                   (IRO[8].base)
1713 #define PSTORM_INTEG_TEST_DATA_SIZE                     (IRO[8].size)
1714 /* Tstorm Integration Test Data */
1715 #define TSTORM_INTEG_TEST_DATA_OFFSET                   (IRO[9].base)
1716 #define TSTORM_INTEG_TEST_DATA_SIZE                     (IRO[9].size)
1717 /* Mstorm Integration Test Data */
1718 #define MSTORM_INTEG_TEST_DATA_OFFSET                   (IRO[10].base)
1719 #define MSTORM_INTEG_TEST_DATA_SIZE                     (IRO[10].size)
1720 /* Ustorm Integration Test Data */
1721 #define USTORM_INTEG_TEST_DATA_OFFSET                   (IRO[11].base)
1722 #define USTORM_INTEG_TEST_DATA_SIZE                     (IRO[11].size)
1723 /* Tstorm producers */
1724 #define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id)    (IRO[12].base + \
1725                                                          ((core_rx_queue_id) * \
1726                                                           IRO[12].m1))
1727 #define TSTORM_LL2_RX_PRODS_SIZE                        (IRO[12].size)
1728 /* Tstorm LiteL2 queue statistics */
1729 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_q_id) (IRO[13].base + \
1730                                                              ((core_rx_q_id) * \
1731                                                               IRO[13].m1))
1732 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE             (IRO[13].size)
1733 /* Ustorm LiteL2 queue statistics */
1734 #define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_q_id) (IRO[14].base + \
1735                                                              ((core_rx_q_id) * \
1736                                                               IRO[14].m1))
1737 #define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE             (IRO[14].size)
1738 /* Pstorm LiteL2 queue statistics */
1739 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_txst_id) (IRO[15].base + \
1740                                                              ((core_txst_id) * \
1741                                                               IRO[15].m1))
1742 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE             (IRO[15].size)
1743 /* Mstorm queue statistics */
1744 #define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) (IRO[16].base + \
1745                                                    ((stat_counter_id) * \
1746                                                     IRO[16].m1))
1747 #define MSTORM_QUEUE_STAT_SIZE                          (IRO[16].size)
1748 /* Mstorm producers */
1749 #define MSTORM_PRODS_OFFSET(queue_id)                   (IRO[17].base + \
1750                                                          ((queue_id) *  \
1751                                                           IRO[17].m1))
1752 #define MSTORM_PRODS_SIZE                               (IRO[17].size)
1753 /* TPA agregation timeout in us resolution (on ASIC) */
1754 #define MSTORM_TPA_TIMEOUT_US_OFFSET                    (IRO[18].base)
1755 #define MSTORM_TPA_TIMEOUT_US_SIZE                      (IRO[18].size)
1756 /* Ustorm queue statistics */
1757 #define USTORM_QUEUE_STAT_OFFSET(stat_counter_id)       (IRO[19].base + \
1758                                                         ((stat_counter_id) * \
1759                                                          IRO[19].m1))
1760 #define USTORM_QUEUE_STAT_SIZE                          (IRO[19].size)
1761 /* Ustorm queue zone */
1762 #define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_id)          (IRO[20].base + \
1763                                                          ((queue_id) *  \
1764                                                           IRO[20].m1))
1765 #define USTORM_ETH_QUEUE_ZONE_SIZE                      (IRO[20].size)
1766 /* Pstorm queue statistics */
1767 #define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id)       (IRO[21].base + \
1768                                                          ((stat_counter_id) * \
1769                                                           IRO[21].m1))
1770 #define PSTORM_QUEUE_STAT_SIZE                          (IRO[21].size)
1771 /* Tstorm last parser message */
1772 #define TSTORM_ETH_PRS_INPUT_OFFSET(pf_id)              (IRO[22].base + \
1773                                                          ((pf_id) *     \
1774                                                           IRO[22].m1))
1775 #define TSTORM_ETH_PRS_INPUT_SIZE                       (IRO[22].size)
1776 /* Ystorm queue zone */
1777 #define YSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id)          (IRO[23].base + \
1778                                                          ((queue_id) *  \
1779                                                           IRO[23].m1))
1780 #define YSTORM_ETH_QUEUE_ZONE_SIZE                      (IRO[23].size)
1781 /* Ystorm cqe producer */
1782 #define YSTORM_TOE_CQ_PROD_OFFSET(rss_id)               (IRO[24].base + \
1783                                                          ((rss_id) *    \
1784                                                           IRO[24].m1))
1785 #define YSTORM_TOE_CQ_PROD_SIZE                         (IRO[24].size)
1786 /* Ustorm cqe producer */
1787 #define USTORM_TOE_CQ_PROD_OFFSET(rss_id)               (IRO[25].base + \
1788                                                          ((rss_id) *    \
1789                                                           IRO[25].m1))
1790 #define USTORM_TOE_CQ_PROD_SIZE                         (IRO[25].size)
1791 /* Ustorm grq producer */
1792 #define USTORM_TOE_GRQ_PROD_OFFSET(pf_id)               (IRO[26].base + \
1793                                                          ((pf_id) *     \
1794                                                           IRO[26].m1))
1795 #define USTORM_TOE_GRQ_PROD_SIZE                        (IRO[26].size)
1796 /* Tstorm cmdq-cons of given command queue-id */
1797 #define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id)     (IRO[27].base + \
1798                                                          ((cmdq_queue_id) * \
1799                                                           IRO[27].m1))
1800 #define TSTORM_SCSI_CMDQ_CONS_SIZE                      (IRO[27].size)
1801 /* Mstorm rq-cons of given queue-id */
1802 #define MSTORM_SCSI_RQ_CONS_OFFSET(rq_queue_id)         (IRO[28].base + \
1803                                                          ((rq_queue_id) * \
1804                                                           IRO[28].m1))
1805 #define MSTORM_SCSI_RQ_CONS_SIZE                        (IRO[28].size)
1806 /* Pstorm RoCE statistics */
1807 #define PSTORM_ROCE_STAT_OFFSET(stat_counter_id)        (IRO[29].base + \
1808                                                          ((stat_counter_id) * \
1809                                                           IRO[29].m1))
1810 #define PSTORM_ROCE_STAT_SIZE                           (IRO[29].size)
1811 /* Tstorm RoCE statistics */
1812 #define TSTORM_ROCE_STAT_OFFSET(stat_counter_id)        (IRO[30].base + \
1813                                                          ((stat_counter_id) * \
1814                                                           IRO[30].m1))
1815 #define TSTORM_ROCE_STAT_SIZE                           (IRO[30].size)
1816
1817 static const struct iro iro_arr[31] = {
1818         { 0x10,   0x0,   0x0,   0x0,   0x8     },
1819         { 0x4448, 0x60,  0x0,   0x0,   0x60    },
1820         { 0x498,  0x8,   0x0,   0x0,   0x4     },
1821         { 0x494,  0x0,   0x0,   0x0,   0x4     },
1822         { 0x10,   0x8,   0x0,   0x0,   0x2     },
1823         { 0x90,   0x8,   0x0,   0x0,   0x2     },
1824         { 0x4540, 0x0,   0x0,   0x0,   0xf8    },
1825         { 0x39e0, 0x0,   0x0,   0x0,   0xf8    },
1826         { 0x2598, 0x0,   0x0,   0x0,   0xf8    },
1827         { 0x4350, 0x0,   0x0,   0x0,   0xf8    },
1828         { 0x52d0, 0x0,   0x0,   0x0,   0xf8    },
1829         { 0x7a48, 0x0,   0x0,   0x0,   0xf8    },
1830         { 0x100,  0x8,   0x0,   0x0,   0x8     },
1831         { 0x5808, 0x10,  0x0,   0x0,   0x10    },
1832         { 0xb100, 0x30,  0x0,   0x0,   0x30    },
1833         { 0x95c0, 0x30,  0x0,   0x0,   0x30    },
1834         { 0x54f8, 0x40,  0x0,   0x0,   0x40    },
1835         { 0x200,  0x10,  0x0,   0x0,   0x8     },
1836         { 0x9e70, 0x0,   0x0,   0x0,   0x4     },
1837         { 0x7ca0, 0x40,  0x0,   0x0,   0x30    },
1838         { 0xd00,  0x8,   0x0,   0x0,   0x8     },
1839         { 0x2790, 0x80,  0x0,   0x0,   0x38    },
1840         { 0xa520, 0xf0,  0x0,   0x0,   0xf0    },
1841         { 0x80,   0x8,   0x0,   0x0,   0x8     },
1842         { 0xac0,  0x8,   0x0,   0x0,   0x8     },
1843         { 0x2580, 0x8,   0x0,   0x0,   0x8     },
1844         { 0x2500, 0x8,   0x0,   0x0,   0x8     },
1845         { 0x440,  0x8,   0x0,   0x0,   0x2     },
1846         { 0x1800, 0x8,   0x0,   0x0,   0x2     },
1847         { 0x27c8, 0x80,  0x0,   0x0,   0x10    },
1848         { 0x4710, 0x10,  0x0,   0x0,   0x10    },
1849 };
1850
1851 /* Runtime array offsets */
1852 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET                                0
1853 #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET                                1
1854 #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET                                2
1855 #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET                                3
1856 #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET                                4
1857 #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET                                5
1858 #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET                                6
1859 #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET                                7
1860 #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET                                8
1861 #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET                                9
1862 #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET                                10
1863 #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET                                11
1864 #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET                                12
1865 #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET                                13
1866 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET                                14
1867 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET                                15
1868 #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET                                  16
1869 #define IGU_REG_PF_CONFIGURATION_RT_OFFSET                              17
1870 #define IGU_REG_VF_CONFIGURATION_RT_OFFSET                              18
1871 #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET                               19
1872 #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET                               20
1873 #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET                            21
1874 #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET                           22
1875 #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET                             23
1876 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET                                 760
1877 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE                                   736
1878 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET                                 760
1879 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE                                   736
1880 #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET                                1496
1881 #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE                                  736
1882 #define CAU_REG_PI_MEMORY_RT_OFFSET                                     2232
1883 #define CAU_REG_PI_MEMORY_RT_SIZE                                       4416
1884 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET                    6648
1885 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET                      6649
1886 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET                      6650
1887 #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET                         6651
1888 #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET                         6652
1889 #define PRS_REG_SEARCH_TCP_RT_OFFSET                                    6653
1890 #define PRS_REG_SEARCH_FCOE_RT_OFFSET                                   6654
1891 #define PRS_REG_SEARCH_ROCE_RT_OFFSET                                   6655
1892 #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET                           6656
1893 #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET                           6657
1894 #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET                               6658
1895 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET                     6659
1896 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET           6660
1897 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET                      6661
1898 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET                         6662
1899 #define SRC_REG_FIRSTFREE_RT_OFFSET                                     6663
1900 #define SRC_REG_FIRSTFREE_RT_SIZE                                       2
1901 #define SRC_REG_LASTFREE_RT_OFFSET                                      6665
1902 #define SRC_REG_LASTFREE_RT_SIZE                                        2
1903 #define SRC_REG_COUNTFREE_RT_OFFSET                                     6667
1904 #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET                              6668
1905 #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET                                6669
1906 #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET                                6670
1907 #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET                                  6671
1908 #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET                                  6672
1909 #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET                                 6673
1910 #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET                               6674
1911 #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET                                6675
1912 #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET                               6676
1913 #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET                                6677
1914 #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET                              6678
1915 #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET                               6679
1916 #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET                             6680
1917 #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET                              6681
1918 #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET                             6682
1919 #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET                              6683
1920 #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET                             6684
1921 #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET                              6685
1922 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET                     6686
1923 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET                   6687
1924 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET                   6688
1925 #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET                               6689
1926 #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET                             6690
1927 #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET                             6691
1928 #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET                           6692
1929 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET                         6693
1930 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET                         6694
1931 #define PSWRQ2_REG_VF_BASE_RT_OFFSET                                    6695
1932 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET                                6696
1933 #define PSWRQ2_REG_WR_MBS0_RT_OFFSET                                    6697
1934 #define PSWRQ2_REG_RD_MBS0_RT_OFFSET                                    6698
1935 #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET                              6699
1936 #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET                              6700
1937 #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET                                 6701
1938 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE                                   22000
1939 #define PGLUE_REG_B_VF_BASE_RT_OFFSET                                   28701
1940 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET                           28702
1941 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET                              28703
1942 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET                              28704
1943 #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET                              28705
1944 #define TM_REG_VF_ENABLE_CONN_RT_OFFSET                                 28706
1945 #define TM_REG_PF_ENABLE_CONN_RT_OFFSET                                 28707
1946 #define TM_REG_PF_ENABLE_TASK_RT_OFFSET                                 28708
1947 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET                     28709
1948 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET                     28710
1949 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET                                28711
1950 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE                                  416
1951 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET                                29127
1952 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE                                  512
1953 #define QM_REG_MAXPQSIZE_0_RT_OFFSET                                    29639
1954 #define QM_REG_MAXPQSIZE_1_RT_OFFSET                                    29640
1955 #define QM_REG_MAXPQSIZE_2_RT_OFFSET                                    29641
1956 #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET                               29642
1957 #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET                               29643
1958 #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET                               29644
1959 #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET                               29645
1960 #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET                               29646
1961 #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET                               29647
1962 #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET                               29648
1963 #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET                               29649
1964 #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET                               29650
1965 #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET                               29651
1966 #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET                              29652
1967 #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET                              29653
1968 #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET                              29654
1969 #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET                              29655
1970 #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET                              29656
1971 #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET                              29657
1972 #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET                              29658
1973 #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET                              29659
1974 #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET                              29660
1975 #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET                              29661
1976 #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET                              29662
1977 #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET                              29663
1978 #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET                              29664
1979 #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET                              29665
1980 #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET                              29666
1981 #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET                              29667
1982 #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET                              29668
1983 #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET                              29669
1984 #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET                              29670
1985 #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET                              29671
1986 #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET                              29672
1987 #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET                              29673
1988 #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET                              29674
1989 #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET                              29675
1990 #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET                              29676
1991 #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET                              29677
1992 #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET                              29678
1993 #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET                              29679
1994 #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET                              29680
1995 #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET                              29681
1996 #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET                              29682
1997 #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET                              29683
1998 #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET                              29684
1999 #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET                              29685
2000 #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET                              29686
2001 #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET                              29687
2002 #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET                              29688
2003 #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET                              29689
2004 #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET                              29690
2005 #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET                              29691
2006 #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET                              29692
2007 #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET                              29693
2008 #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET                              29694
2009 #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET                              29695
2010 #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET                              29696
2011 #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET                              29697
2012 #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET                              29698
2013 #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET                              29699
2014 #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET                              29700
2015 #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET                              29701
2016 #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET                              29702
2017 #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET                              29703
2018 #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET                              29704
2019 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET                              29705
2020 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET                                29706
2021 #define QM_REG_BASEADDROTHERPQ_RT_SIZE                                  128
2022 #define QM_REG_VOQCRDLINE_RT_OFFSET                                     29834
2023 #define QM_REG_VOQCRDLINE_RT_SIZE                                       20
2024 #define QM_REG_VOQINITCRDLINE_RT_OFFSET                                 29854
2025 #define QM_REG_VOQINITCRDLINE_RT_SIZE                                   20
2026 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET                             29874
2027 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET                             29875
2028 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET                              29876
2029 #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET                            29877
2030 #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET                           29878
2031 #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET                                29879
2032 #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET                                29880
2033 #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET                                29881
2034 #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET                                29882
2035 #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET                                29883
2036 #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET                                29884
2037 #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET                                29885
2038 #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET                                29886
2039 #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET                                29887
2040 #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET                                29888
2041 #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET                               29889
2042 #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET                               29890
2043 #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET                               29891
2044 #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET                               29892
2045 #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET                               29893
2046 #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET                               29894
2047 #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET                            29895
2048 #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET                            29896
2049 #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET                            29897
2050 #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET                            29898
2051 #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET                               29899
2052 #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET                               29900
2053 #define QM_REG_PQTX2PF_0_RT_OFFSET                                      29901
2054 #define QM_REG_PQTX2PF_1_RT_OFFSET                                      29902
2055 #define QM_REG_PQTX2PF_2_RT_OFFSET                                      29903
2056 #define QM_REG_PQTX2PF_3_RT_OFFSET                                      29904
2057 #define QM_REG_PQTX2PF_4_RT_OFFSET                                      29905
2058 #define QM_REG_PQTX2PF_5_RT_OFFSET                                      29906
2059 #define QM_REG_PQTX2PF_6_RT_OFFSET                                      29907
2060 #define QM_REG_PQTX2PF_7_RT_OFFSET                                      29908
2061 #define QM_REG_PQTX2PF_8_RT_OFFSET                                      29909
2062 #define QM_REG_PQTX2PF_9_RT_OFFSET                                      29910
2063 #define QM_REG_PQTX2PF_10_RT_OFFSET                                     29911
2064 #define QM_REG_PQTX2PF_11_RT_OFFSET                                     29912
2065 #define QM_REG_PQTX2PF_12_RT_OFFSET                                     29913
2066 #define QM_REG_PQTX2PF_13_RT_OFFSET                                     29914
2067 #define QM_REG_PQTX2PF_14_RT_OFFSET                                     29915
2068 #define QM_REG_PQTX2PF_15_RT_OFFSET                                     29916
2069 #define QM_REG_PQTX2PF_16_RT_OFFSET                                     29917
2070 #define QM_REG_PQTX2PF_17_RT_OFFSET                                     29918
2071 #define QM_REG_PQTX2PF_18_RT_OFFSET                                     29919
2072 #define QM_REG_PQTX2PF_19_RT_OFFSET                                     29920
2073 #define QM_REG_PQTX2PF_20_RT_OFFSET                                     29921
2074 #define QM_REG_PQTX2PF_21_RT_OFFSET                                     29922
2075 #define QM_REG_PQTX2PF_22_RT_OFFSET                                     29923
2076 #define QM_REG_PQTX2PF_23_RT_OFFSET                                     29924
2077 #define QM_REG_PQTX2PF_24_RT_OFFSET                                     29925
2078 #define QM_REG_PQTX2PF_25_RT_OFFSET                                     29926
2079 #define QM_REG_PQTX2PF_26_RT_OFFSET                                     29927
2080 #define QM_REG_PQTX2PF_27_RT_OFFSET                                     29928
2081 #define QM_REG_PQTX2PF_28_RT_OFFSET                                     29929
2082 #define QM_REG_PQTX2PF_29_RT_OFFSET                                     29930
2083 #define QM_REG_PQTX2PF_30_RT_OFFSET                                     29931
2084 #define QM_REG_PQTX2PF_31_RT_OFFSET                                     29932
2085 #define QM_REG_PQTX2PF_32_RT_OFFSET                                     29933
2086 #define QM_REG_PQTX2PF_33_RT_OFFSET                                     29934
2087 #define QM_REG_PQTX2PF_34_RT_OFFSET                                     29935
2088 #define QM_REG_PQTX2PF_35_RT_OFFSET                                     29936
2089 #define QM_REG_PQTX2PF_36_RT_OFFSET                                     29937
2090 #define QM_REG_PQTX2PF_37_RT_OFFSET                                     29938
2091 #define QM_REG_PQTX2PF_38_RT_OFFSET                                     29939
2092 #define QM_REG_PQTX2PF_39_RT_OFFSET                                     29940
2093 #define QM_REG_PQTX2PF_40_RT_OFFSET                                     29941
2094 #define QM_REG_PQTX2PF_41_RT_OFFSET                                     29942
2095 #define QM_REG_PQTX2PF_42_RT_OFFSET                                     29943
2096 #define QM_REG_PQTX2PF_43_RT_OFFSET                                     29944
2097 #define QM_REG_PQTX2PF_44_RT_OFFSET                                     29945
2098 #define QM_REG_PQTX2PF_45_RT_OFFSET                                     29946
2099 #define QM_REG_PQTX2PF_46_RT_OFFSET                                     29947
2100 #define QM_REG_PQTX2PF_47_RT_OFFSET                                     29948
2101 #define QM_REG_PQTX2PF_48_RT_OFFSET                                     29949
2102 #define QM_REG_PQTX2PF_49_RT_OFFSET                                     29950
2103 #define QM_REG_PQTX2PF_50_RT_OFFSET                                     29951
2104 #define QM_REG_PQTX2PF_51_RT_OFFSET                                     29952
2105 #define QM_REG_PQTX2PF_52_RT_OFFSET                                     29953
2106 #define QM_REG_PQTX2PF_53_RT_OFFSET                                     29954
2107 #define QM_REG_PQTX2PF_54_RT_OFFSET                                     29955
2108 #define QM_REG_PQTX2PF_55_RT_OFFSET                                     29956
2109 #define QM_REG_PQTX2PF_56_RT_OFFSET                                     29957
2110 #define QM_REG_PQTX2PF_57_RT_OFFSET                                     29958
2111 #define QM_REG_PQTX2PF_58_RT_OFFSET                                     29959
2112 #define QM_REG_PQTX2PF_59_RT_OFFSET                                     29960
2113 #define QM_REG_PQTX2PF_60_RT_OFFSET                                     29961
2114 #define QM_REG_PQTX2PF_61_RT_OFFSET                                     29962
2115 #define QM_REG_PQTX2PF_62_RT_OFFSET                                     29963
2116 #define QM_REG_PQTX2PF_63_RT_OFFSET                                     29964
2117 #define QM_REG_PQOTHER2PF_0_RT_OFFSET                                   29965
2118 #define QM_REG_PQOTHER2PF_1_RT_OFFSET                                   29966
2119 #define QM_REG_PQOTHER2PF_2_RT_OFFSET                                   29967
2120 #define QM_REG_PQOTHER2PF_3_RT_OFFSET                                   29968
2121 #define QM_REG_PQOTHER2PF_4_RT_OFFSET                                   29969
2122 #define QM_REG_PQOTHER2PF_5_RT_OFFSET                                   29970
2123 #define QM_REG_PQOTHER2PF_6_RT_OFFSET                                   29971
2124 #define QM_REG_PQOTHER2PF_7_RT_OFFSET                                   29972
2125 #define QM_REG_PQOTHER2PF_8_RT_OFFSET                                   29973
2126 #define QM_REG_PQOTHER2PF_9_RT_OFFSET                                   29974
2127 #define QM_REG_PQOTHER2PF_10_RT_OFFSET                                  29975
2128 #define QM_REG_PQOTHER2PF_11_RT_OFFSET                                  29976
2129 #define QM_REG_PQOTHER2PF_12_RT_OFFSET                                  29977
2130 #define QM_REG_PQOTHER2PF_13_RT_OFFSET                                  29978
2131 #define QM_REG_PQOTHER2PF_14_RT_OFFSET                                  29979
2132 #define QM_REG_PQOTHER2PF_15_RT_OFFSET                                  29980
2133 #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET                                 29981
2134 #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET                                 29982
2135 #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET                            29983
2136 #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET                            29984
2137 #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET                              29985
2138 #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET                              29986
2139 #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET                              29987
2140 #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET                              29988
2141 #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET                              29989
2142 #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET                              29990
2143 #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET                              29991
2144 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET                              29992
2145 #define QM_REG_RLGLBLINCVAL_RT_OFFSET                                   29993
2146 #define QM_REG_RLGLBLINCVAL_RT_SIZE                                     256
2147 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET                               30249
2148 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE                                 256
2149 #define QM_REG_RLGLBLCRD_RT_OFFSET                                      30505
2150 #define QM_REG_RLGLBLCRD_RT_SIZE                                        256
2151 #define QM_REG_RLGLBLENABLE_RT_OFFSET                                   30761
2152 #define QM_REG_RLPFPERIOD_RT_OFFSET                                     30762
2153 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET                                30763
2154 #define QM_REG_RLPFINCVAL_RT_OFFSET                                     30764
2155 #define QM_REG_RLPFINCVAL_RT_SIZE                                       16
2156 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET                                 30780
2157 #define QM_REG_RLPFUPPERBOUND_RT_SIZE                                   16
2158 #define QM_REG_RLPFCRD_RT_OFFSET                                        30796
2159 #define QM_REG_RLPFCRD_RT_SIZE                                          16
2160 #define QM_REG_RLPFENABLE_RT_OFFSET                                     30812
2161 #define QM_REG_RLPFVOQENABLE_RT_OFFSET                                  30813
2162 #define QM_REG_WFQPFWEIGHT_RT_OFFSET                                    30814
2163 #define QM_REG_WFQPFWEIGHT_RT_SIZE                                      16
2164 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET                                30830
2165 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE                                  16
2166 #define QM_REG_WFQPFCRD_RT_OFFSET                                       30846
2167 #define QM_REG_WFQPFCRD_RT_SIZE                                         160
2168 #define QM_REG_WFQPFENABLE_RT_OFFSET                                    31006
2169 #define QM_REG_WFQVPENABLE_RT_OFFSET                                    31007
2170 #define QM_REG_BASEADDRTXPQ_RT_OFFSET                                   31008
2171 #define QM_REG_BASEADDRTXPQ_RT_SIZE                                     512
2172 #define QM_REG_TXPQMAP_RT_OFFSET                                        31520
2173 #define QM_REG_TXPQMAP_RT_SIZE                                          512
2174 #define QM_REG_WFQVPWEIGHT_RT_OFFSET                                    32032
2175 #define QM_REG_WFQVPWEIGHT_RT_SIZE                                      512
2176 #define QM_REG_WFQVPUPPERBOUND_RT_OFFSET                                32544
2177 #define QM_REG_WFQVPUPPERBOUND_RT_SIZE                                  512
2178 #define QM_REG_WFQVPCRD_RT_OFFSET                                       33056
2179 #define QM_REG_WFQVPCRD_RT_SIZE                                         512
2180 #define QM_REG_WFQVPMAP_RT_OFFSET                                       33568
2181 #define QM_REG_WFQVPMAP_RT_SIZE                                         512
2182 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET                                   34080
2183 #define QM_REG_WFQPFCRD_MSB_RT_SIZE                                     160
2184 #define NIG_REG_LLH_CLS_TYPE_DUALMODE_RT_OFFSET                         34240
2185 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET                         34241
2186 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET                         34242
2187 #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET                         34243
2188 #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET                         34244
2189 #define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET                          34245
2190 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET                      34246
2191 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET                               34247
2192 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE                                 4
2193 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET                          34251
2194 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE                            4
2195 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET                            34255
2196 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE                              4
2197 #define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET                               34259
2198 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET                         34260
2199 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE                           32
2200 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET                            34292
2201 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE                              16
2202 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET                          34308
2203 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE                            16
2204 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET                 34324
2205 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE                   16
2206 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET                       34340
2207 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE                         16
2208 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET                                  34356
2209 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET                               34357
2210 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET                               34358
2211 #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET                               34359
2212 #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET                           34360
2213 #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET                           34361
2214 #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET                           34362
2215 #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET                           34363
2216 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET                        34364
2217 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET                        34365
2218 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET                        34366
2219 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET                        34367
2220 #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET                            34368
2221 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET                         34369
2222 #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET                          34370
2223 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET                        34371
2224 #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET                           34372
2225 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET                    34373
2226 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET                        34374
2227 #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET                           34375
2228 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET                    34376
2229 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET                        34377
2230 #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET                           34378
2231 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET                    34379
2232 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET                        34380
2233 #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET                           34381
2234 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET                    34382
2235 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET                        34383
2236 #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET                           34384
2237 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET                    34385
2238 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET                        34386
2239 #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET                           34387
2240 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET                    34388
2241 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET                        34389
2242 #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET                           34390
2243 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET                    34391
2244 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET                        34392
2245 #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET                           34393
2246 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET                    34394
2247 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET                        34395
2248 #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET                           34396
2249 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET                    34397
2250 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET                        34398
2251 #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET                           34399
2252 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET                    34400
2253 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET                       34401
2254 #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET                          34402
2255 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET                   34403
2256 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET                       34404
2257 #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET                          34405
2258 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET                   34406
2259 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET                       34407
2260 #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET                          34408
2261 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET                   34409
2262 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET                       34410
2263 #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET                          34411
2264 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET                   34412
2265 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET                       34413
2266 #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET                          34414
2267 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET                   34415
2268 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET                       34416
2269 #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET                          34417
2270 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET                   34418
2271 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET                       34419
2272 #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET                          34420
2273 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET                   34421
2274 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET                       34422
2275 #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET                          34423
2276 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET                   34424
2277 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET                       34425
2278 #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET                          34426
2279 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET                   34427
2280 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET                       34428
2281 #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET                          34429
2282 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET                   34430
2283 #define XCM_REG_CON_PHY_Q3_RT_OFFSET                                    34431
2284
2285 #define RUNTIME_ARRAY_SIZE 34432
2286
2287 /* The eth storm context for the Ystorm */
2288 struct ystorm_eth_conn_st_ctx {
2289         __le32 reserved[4];
2290 };
2291
2292 /* The eth storm context for the Pstorm */
2293 struct pstorm_eth_conn_st_ctx {
2294         __le32 reserved[8];
2295 };
2296
2297 /* The eth storm context for the Xstorm */
2298 struct xstorm_eth_conn_st_ctx {
2299         __le32 reserved[60];
2300 };
2301
2302 struct xstorm_eth_conn_ag_ctx {
2303         u8      reserved0 /* cdu_validation */;
2304         u8      eth_state /* state */;
2305         u8      flags0;
2306 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK            0x1
2307 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT           0
2308 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK               0x1
2309 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT              1
2310 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK               0x1
2311 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT              2
2312 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK            0x1
2313 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT           3
2314 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK               0x1 /* bit4 */
2315 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT              4
2316 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK               0x1
2317 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT              5
2318 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK               0x1 /* bit6 */
2319 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT              6
2320 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK               0x1 /* bit7 */
2321 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT              7
2322         u8 flags1;
2323 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK               0x1 /* bit8 */
2324 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT              0
2325 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK               0x1 /* bit9 */
2326 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT              1
2327 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK               0x1 /* bit10 */
2328 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT              2
2329 #define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK                   0x1 /* bit11 */
2330 #define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT                  3
2331 #define XSTORM_ETH_CONN_AG_CTX_BIT12_MASK                   0x1 /* bit12 */
2332 #define XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT                  4
2333 #define XSTORM_ETH_CONN_AG_CTX_BIT13_MASK                   0x1 /* bit13 */
2334 #define XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT                  5
2335 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK          0x1 /* bit14 */
2336 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT         6
2337 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK            0x1 /* bit15 */
2338 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT           7
2339         u8 flags2;
2340 #define XSTORM_ETH_CONN_AG_CTX_CF0_MASK                     0x3 /* timer0cf */
2341 #define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT                    0
2342 #define XSTORM_ETH_CONN_AG_CTX_CF1_MASK                     0x3 /* timer1cf */
2343 #define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT                    2
2344 #define XSTORM_ETH_CONN_AG_CTX_CF2_MASK                     0x3 /* timer2cf */
2345 #define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT                    4
2346 #define XSTORM_ETH_CONN_AG_CTX_CF3_MASK                     0x3
2347 #define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT                    6
2348         u8 flags3;
2349 #define XSTORM_ETH_CONN_AG_CTX_CF4_MASK                     0x3 /* cf4 */
2350 #define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT                    0
2351 #define XSTORM_ETH_CONN_AG_CTX_CF5_MASK                     0x3 /* cf5 */
2352 #define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT                    2
2353 #define XSTORM_ETH_CONN_AG_CTX_CF6_MASK                     0x3 /* cf6 */
2354 #define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT                    4
2355 #define XSTORM_ETH_CONN_AG_CTX_CF7_MASK                     0x3 /* cf7 */
2356 #define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT                    6
2357         u8 flags4;
2358 #define XSTORM_ETH_CONN_AG_CTX_CF8_MASK                     0x3 /* cf8 */
2359 #define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT                    0
2360 #define XSTORM_ETH_CONN_AG_CTX_CF9_MASK                     0x3 /* cf9 */
2361 #define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT                    2
2362 #define XSTORM_ETH_CONN_AG_CTX_CF10_MASK                    0x3 /* cf10 */
2363 #define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT                   4
2364 #define XSTORM_ETH_CONN_AG_CTX_CF11_MASK                    0x3 /* cf11 */
2365 #define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT                   6
2366         u8 flags5;
2367 #define XSTORM_ETH_CONN_AG_CTX_CF12_MASK                    0x3 /* cf12 */
2368 #define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT                   0
2369 #define XSTORM_ETH_CONN_AG_CTX_CF13_MASK                    0x3 /* cf13 */
2370 #define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT                   2
2371 #define XSTORM_ETH_CONN_AG_CTX_CF14_MASK                    0x3 /* cf14 */
2372 #define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT                   4
2373 #define XSTORM_ETH_CONN_AG_CTX_CF15_MASK                    0x3 /* cf15 */
2374 #define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT                   6
2375         u8 flags6;
2376 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK        0x3 /* cf16 */
2377 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT       0
2378 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK        0x3
2379 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT       2
2380 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK                   0x3 /* cf18 */
2381 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT                  4
2382 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK            0x3 /* cf19 */
2383 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT           6
2384         u8 flags7;
2385 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK                0x3 /* cf20 */
2386 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT               0
2387 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK              0x3 /* cf21 */
2388 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT             2
2389 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK               0x3 /* cf22 */
2390 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT              4
2391 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK                   0x1 /* cf0en */
2392 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT                  6
2393 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK                   0x1 /* cf1en */
2394 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT                  7
2395         u8 flags8;
2396 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK                   0x1 /* cf2en */
2397 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT                  0
2398 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK                   0x1 /* cf3en */
2399 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT                  1
2400 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK                   0x1 /* cf4en */
2401 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT                  2
2402 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK                   0x1 /* cf5en */
2403 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT                  3
2404 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK                   0x1 /* cf6en */
2405 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT                  4
2406 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK                   0x1 /* cf7en */
2407 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT                  5
2408 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK                   0x1 /* cf8en */
2409 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT                  6
2410 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK                   0x1 /* cf9en */
2411 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT                  7
2412         u8 flags9;
2413 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK                  0x1 /* cf10en */
2414 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT                 0
2415 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK                  0x1 /* cf11en */
2416 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT                 1
2417 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK                  0x1 /* cf12en */
2418 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT                 2
2419 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK                  0x1 /* cf13en */
2420 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT                 3
2421 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK                  0x1 /* cf14en */
2422 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT                 4
2423 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK                  0x1 /* cf15en */
2424 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT                 5
2425 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK     0x1 /* cf16en */
2426 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT    6
2427 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK     0x1
2428 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT    7
2429         u8 flags10;
2430 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK                0x1 /* cf18en */
2431 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT               0
2432 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK         0x1 /* cf19en */
2433 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT        1
2434 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK             0x1 /* cf20en */
2435 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT            2
2436 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK              0x1 /* cf21en */
2437 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT             3
2438 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK            0x1 /* cf22en */
2439 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT           4
2440 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK  0x1 /* cf23en */
2441 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
2442 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK              0x1 /* rule0en */
2443 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT             6
2444 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK              0x1 /* rule1en */
2445 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT             7
2446         u8 flags11;
2447 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK              0x1 /* rule2en */
2448 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT             0
2449 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK              0x1 /* rule3en */
2450 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT             1
2451 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK          0x1 /* rule4en */
2452 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT         2
2453 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK                 0x1 /* rule5en */
2454 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT                3
2455 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK                 0x1 /* rule6en */
2456 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT                4
2457 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK                 0x1 /* rule7en */
2458 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT                5
2459 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK            0x1 /* rule8en */
2460 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT           6
2461 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK                 0x1 /* rule9en */
2462 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT                7
2463         u8 flags12;
2464 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK                0x1 /* rule10en */
2465 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT               0
2466 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK                0x1 /* rule11en */
2467 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT               1
2468 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK            0x1 /* rule12en */
2469 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT           2
2470 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK            0x1 /* rule13en */
2471 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT           3
2472 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK                0x1 /* rule14en */
2473 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT               4
2474 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK                0x1 /* rule15en */
2475 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT               5
2476 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK                0x1 /* rule16en */
2477 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT               6
2478 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK                0x1 /* rule17en */
2479 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT               7
2480         u8 flags13;
2481 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK                0x1 /* rule18en */
2482 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT               0
2483 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK                0x1 /* rule19en */
2484 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT               1
2485 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK            0x1 /* rule20en */
2486 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT           2
2487 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK            0x1 /* rule21en */
2488 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT           3
2489 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK            0x1 /* rule22en */
2490 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT           4
2491 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK            0x1 /* rule23en */
2492 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT           5
2493 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK            0x1 /* rule24en */
2494 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT           6
2495 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK            0x1 /* rule25en */
2496 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT           7
2497         u8 flags14;
2498 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK        0x1 /* bit16 */
2499 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT       0
2500 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK      0x1 /* bit17 */
2501 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT     1
2502 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK    0x1 /* bit18 */
2503 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT   2
2504 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK    0x1 /* bit19 */
2505 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT   3
2506 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK          0x1 /* bit20 */
2507 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT         4
2508 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK        0x1 /* bit21 */
2509 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT       5
2510 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK              0x3 /* cf23 */
2511 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT             6
2512         u8      edpm_event_id /* byte2 */;
2513         __le16  physical_q0 /* physical_q0 */;
2514         __le16  word1 /* physical_q1 */;
2515         __le16  edpm_num_bds /* physical_q2 */;
2516         __le16  tx_bd_cons /* word3 */;
2517         __le16  tx_bd_prod /* word4 */;
2518         __le16  go_to_bd_cons /* word5 */;
2519         __le16  conn_dpi /* conn_dpi */;
2520         u8      byte3 /* byte3 */;
2521         u8      byte4 /* byte4 */;
2522         u8      byte5 /* byte5 */;
2523         u8      byte6 /* byte6 */;
2524         __le32  reg0 /* reg0 */;
2525         __le32  reg1 /* reg1 */;
2526         __le32  reg2 /* reg2 */;
2527         __le32  reg3 /* reg3 */;
2528         __le32  reg4 /* reg4 */;
2529         __le32  reg5 /* cf_array0 */;
2530         __le32  reg6 /* cf_array1 */;
2531         __le16  word7 /* word7 */;
2532         __le16  word8 /* word8 */;
2533         __le16  word9 /* word9 */;
2534         __le16  word10 /* word10 */;
2535         __le32  reg7 /* reg7 */;
2536         __le32  reg8 /* reg8 */;
2537         __le32  reg9 /* reg9 */;
2538         u8      byte7 /* byte7 */;
2539         u8      byte8 /* byte8 */;
2540         u8      byte9 /* byte9 */;
2541         u8      byte10 /* byte10 */;
2542         u8      byte11 /* byte11 */;
2543         u8      byte12 /* byte12 */;
2544         u8      byte13 /* byte13 */;
2545         u8      byte14 /* byte14 */;
2546         u8      byte15 /* byte15 */;
2547         u8      byte16 /* byte16 */;
2548         __le16  word11 /* word11 */;
2549         __le32  reg10 /* reg10 */;
2550         __le32  reg11 /* reg11 */;
2551         __le32  reg12 /* reg12 */;
2552         __le32  reg13 /* reg13 */;
2553         __le32  reg14 /* reg14 */;
2554         __le32  reg15 /* reg15 */;
2555         __le32  reg16 /* reg16 */;
2556         __le32  reg17 /* reg17 */;
2557         __le32  reg18 /* reg18 */;
2558         __le32  reg19 /* reg19 */;
2559         __le16  word12 /* word12 */;
2560         __le16  word13 /* word13 */;
2561         __le16  word14 /* word14 */;
2562         __le16  word15 /* word15 */;
2563 };
2564
2565 /* The eth storm context for the Tstorm */
2566 struct tstorm_eth_conn_st_ctx {
2567         __le32 reserved[4];
2568 };
2569
2570 /* The eth storm context for the Mstorm */
2571 struct mstorm_eth_conn_st_ctx {
2572         __le32 reserved[8];
2573 };
2574
2575 /* The eth storm context for the Ustorm */
2576 struct ustorm_eth_conn_st_ctx {
2577         __le32 reserved[40];
2578 };
2579
2580 /* eth connection context */
2581 struct eth_conn_context {
2582         struct ystorm_eth_conn_st_ctx   ystorm_st_context;
2583         struct regpair                  ystorm_st_padding[2] /* padding */;
2584         struct pstorm_eth_conn_st_ctx   pstorm_st_context;
2585         struct regpair                  pstorm_st_padding[2] /* padding */;
2586         struct xstorm_eth_conn_st_ctx   xstorm_st_context;
2587         struct xstorm_eth_conn_ag_ctx   xstorm_ag_context;
2588         struct tstorm_eth_conn_st_ctx   tstorm_st_context;
2589         struct regpair                  tstorm_st_padding[2] /* padding */;
2590         struct mstorm_eth_conn_st_ctx   mstorm_st_context;
2591         struct ustorm_eth_conn_st_ctx   ustorm_st_context;
2592 };
2593
2594 enum eth_filter_action {
2595         ETH_FILTER_ACTION_REMOVE,
2596         ETH_FILTER_ACTION_ADD,
2597         ETH_FILTER_ACTION_REPLACE,
2598         MAX_ETH_FILTER_ACTION
2599 };
2600
2601 struct eth_filter_cmd {
2602         u8      type /* Filter Type (MAC/VLAN/Pair/VNI) */;
2603         u8      vport_id /* the vport id */;
2604         u8      action /* filter command action: add/remove/replace */;
2605         u8      reserved0;
2606         __le32  vni;
2607         __le16  mac_lsb;
2608         __le16  mac_mid;
2609         __le16  mac_msb;
2610         __le16  vlan_id;
2611 };
2612
2613 struct eth_filter_cmd_header {
2614         u8      rx;
2615         u8      tx;
2616         u8      cmd_cnt;
2617         u8      assert_on_error;
2618         u8      reserved1[4];
2619 };
2620
2621 enum eth_filter_type {
2622         ETH_FILTER_TYPE_MAC,
2623         ETH_FILTER_TYPE_VLAN,
2624         ETH_FILTER_TYPE_PAIR,
2625         ETH_FILTER_TYPE_INNER_MAC,
2626         ETH_FILTER_TYPE_INNER_VLAN,
2627         ETH_FILTER_TYPE_INNER_PAIR,
2628         ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
2629         ETH_FILTER_TYPE_MAC_VNI_PAIR,
2630         ETH_FILTER_TYPE_VNI,
2631         MAX_ETH_FILTER_TYPE
2632 };
2633
2634 enum eth_ramrod_cmd_id {
2635         ETH_RAMROD_UNUSED,
2636         ETH_RAMROD_VPORT_START /* VPort Start Ramrod */,
2637         ETH_RAMROD_VPORT_UPDATE /* VPort Update Ramrod */,
2638         ETH_RAMROD_VPORT_STOP /* VPort Stop Ramrod */,
2639         ETH_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */,
2640         ETH_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */,
2641         ETH_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */,
2642         ETH_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */,
2643         ETH_RAMROD_FILTERS_UPDATE /* Add or Remove Mac/Vlan/Pair filters */,
2644         ETH_RAMROD_RX_QUEUE_UPDATE /* RX Queue Update Ramrod */,
2645         ETH_RAMROD_RESERVED,
2646         ETH_RAMROD_RESERVED2,
2647         ETH_RAMROD_RESERVED3,
2648         ETH_RAMROD_RESERVED4,
2649         ETH_RAMROD_RESERVED5,
2650         ETH_RAMROD_RESERVED6,
2651         ETH_RAMROD_RESERVED7,
2652         ETH_RAMROD_RESERVED8,
2653         MAX_ETH_RAMROD_CMD_ID
2654 };
2655
2656 struct eth_vport_rss_config {
2657         __le16 capabilities;
2658 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK       0x1
2659 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT       0
2660 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK       0x1
2661 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT       1
2662 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK    0x1
2663 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT   2
2664 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK    0x1
2665 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT   3
2666 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK    0x1
2667 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT   4
2668 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK    0x1
2669 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT   5
2670 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK  0x1
2671 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6
2672 #define ETH_VPORT_RSS_CONFIG_CALC_4TUP_TCP_FRAG_MASK     0x1
2673 #define ETH_VPORT_RSS_CONFIG_CALC_4TUP_TCP_FRAG_SHIFT    7
2674 #define ETH_VPORT_RSS_CONFIG_CALC_4TUP_UDP_FRAG_MASK     0x1
2675 #define ETH_VPORT_RSS_CONFIG_CALC_4TUP_UDP_FRAG_SHIFT    8
2676 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK           0x7F
2677 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT         9
2678         u8      rss_id;
2679         u8      rss_mode;
2680         u8      update_rss_key;
2681         u8      update_rss_ind_table;
2682         u8      update_rss_capabilities;
2683         u8      tbl_size;
2684         __le32  reserved2[2];
2685         __le16  indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
2686         __le32  rss_key[ETH_RSS_KEY_SIZE_REGS];
2687         __le32  reserved3[2];
2688 };
2689
2690 enum eth_vport_rss_mode {
2691         ETH_VPORT_RSS_MODE_DISABLED,
2692         ETH_VPORT_RSS_MODE_REGULAR,
2693         MAX_ETH_VPORT_RSS_MODE
2694 };
2695
2696 struct eth_vport_rx_mode {
2697         __le16 state;
2698 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK     0x1
2699 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT   0
2700 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
2701 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT       1
2702 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK  0x1
2703 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2
2704 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK     0x1
2705 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT   3
2706 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
2707 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT       4
2708 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
2709 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT       5
2710 #define ETH_VPORT_RX_MODE_RESERVED1_MASK               0x3FF
2711 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT             6
2712         __le16 reserved2[3];
2713 };
2714
2715 struct eth_vport_tpa_param {
2716         u64     reserved[2];
2717 };
2718
2719 struct eth_vport_tx_mode {
2720         __le16 state;
2721 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK    0x1
2722 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT   0
2723 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK  0x1
2724 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
2725 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK    0x1
2726 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT   2
2727 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK  0x1
2728 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3
2729 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK  0x1
2730 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4
2731 #define ETH_VPORT_TX_MODE_RESERVED1_MASK         0x7FF
2732 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT       5
2733         __le16 reserved2[3];
2734 };
2735
2736 struct rx_queue_start_ramrod_data {
2737         __le16    rx_queue_id;
2738         __le16    num_of_pbl_pages;
2739         __le16    bd_max_bytes;
2740         __le16    sb_id;
2741         u8            sb_index;
2742         u8            vport_id;
2743         u8            default_rss_queue_flg;
2744         u8            complete_cqe_flg;
2745         u8            complete_event_flg;
2746         u8            stats_counter_id;
2747         u8            pin_context;
2748         u8            pxp_tph_valid_bd;
2749         u8            pxp_tph_valid_pkt;
2750         u8            pxp_st_hint;
2751         __le16    pxp_st_index;
2752         u8            reserved[4];
2753         struct regpair  cqe_pbl_addr;
2754         struct regpair  bd_base;
2755         struct regpair  sge_base;
2756 };
2757
2758 struct rx_queue_stop_ramrod_data {
2759         __le16  rx_queue_id;
2760         u8      complete_cqe_flg;
2761         u8      complete_event_flg;
2762         u8      vport_id;
2763         u8      reserved[3];
2764 };
2765
2766 struct rx_queue_update_ramrod_data {
2767         __le16    rx_queue_id;
2768         u8            complete_cqe_flg;
2769         u8            complete_event_flg;
2770         u8            init_sge_ring_flg;
2771         u8            vport_id;
2772         u8            pxp_tph_valid_sge;
2773         u8            pxp_st_hint;
2774         __le16    pxp_st_index;
2775         u8            reserved[6];
2776         struct regpair  sge_base;
2777 };
2778
2779 struct tx_queue_start_ramrod_data {
2780         __le16  sb_id;
2781         u8      sb_index;
2782         u8      vport_id;
2783         u8      tc;
2784         u8      stats_counter_id;
2785         __le16  qm_pq_id;
2786         u8      flags;
2787 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK  0x1
2788 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
2789 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK      0x1
2790 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT     1
2791 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK      0x1
2792 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT     2
2793 #define TX_QUEUE_START_RAMROD_DATA_RESERVED0_MASK             0x1F
2794 #define TX_QUEUE_START_RAMROD_DATA_RESERVED0_SHIFT           3
2795         u8            pin_context;
2796         u8            pxp_tph_valid_bd;
2797         u8            pxp_tph_valid_pkt;
2798         __le16    pxp_st_index;
2799         u8            pxp_st_hint;
2800         u8            reserved1[3];
2801         __le16    queue_zone_id;
2802         __le16    test_dup_count;
2803         __le16    pbl_size;
2804         struct regpair  pbl_base_addr;
2805 };
2806
2807 struct tx_queue_stop_ramrod_data {
2808         __le16 reserved[4];
2809 };
2810
2811 struct vport_filter_update_ramrod_data {
2812         struct eth_filter_cmd_header    filter_cmd_hdr;
2813         struct eth_filter_cmd      filter_cmds[ETH_FILTER_RULES_COUNT];
2814 };
2815
2816 struct vport_start_ramrod_data {
2817         u8                            vport_id;
2818         u8                            sw_fid;
2819         __le16                    mtu;
2820         u8                            drop_ttl0_en;
2821         u8                            inner_vlan_removal_en;
2822         struct eth_vport_rx_mode        rx_mode;
2823         struct eth_vport_tx_mode        tx_mode;
2824         struct eth_vport_tpa_param      tpa_param;
2825         __le16                    sge_buff_size;
2826         u8                            max_sges_num;
2827         u8                            tx_switching_en;
2828         u8                            anti_spoofing_en;
2829         u8                            default_vlan_en;
2830         u8                            handle_ptp_pkts;
2831         u8                            silent_vlan_removal_en;
2832         __le16                    default_vlan;
2833         u8                            untagged;
2834         u8                            reserved[7];
2835 };
2836
2837 struct vport_stop_ramrod_data {
2838         u8      vport_id;
2839         u8      reserved[7];
2840 };
2841
2842 struct vport_update_ramrod_data_cmn {
2843         u8      vport_id;
2844         u8      update_rx_active_flg;
2845         u8      rx_active_flg;
2846         u8      update_tx_active_flg;
2847         u8      tx_active_flg;
2848         u8      update_rx_mode_flg;
2849         u8      update_tx_mode_flg;
2850         u8      update_approx_mcast_flg;
2851         u8      update_rss_flg;
2852         u8      update_inner_vlan_removal_en_flg;
2853         u8      inner_vlan_removal_en;
2854         u8      update_tpa_param_flg;
2855         u8      update_tpa_en_flg;
2856         u8      update_sge_param_flg;
2857         __le16  sge_buff_size;
2858         u8      max_sges_num;
2859         u8      update_tx_switching_en_flg;
2860         u8      tx_switching_en;
2861         u8      update_anti_spoofing_en_flg;
2862         u8      anti_spoofing_en;
2863         u8      update_handle_ptp_pkts;
2864         u8      handle_ptp_pkts;
2865         u8      update_default_vlan_en_flg;
2866         u8      default_vlan_en;
2867         u8      update_default_vlan_flg;
2868         __le16  default_vlan;
2869         u8      update_accept_any_vlan_flg;
2870         u8      accept_any_vlan;
2871         u8      silent_vlan_removal_en;
2872         u8      reserved;
2873 };
2874
2875 struct vport_update_ramrod_mcast {
2876         __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
2877 };
2878
2879 struct vport_update_ramrod_data {
2880         struct vport_update_ramrod_data_cmn     common;
2881         struct eth_vport_rx_mode                rx_mode;
2882         struct eth_vport_tx_mode                tx_mode;
2883         struct eth_vport_tpa_param            tpa_param;
2884         struct vport_update_ramrod_mcast        approx_mcast;
2885         struct eth_vport_rss_config          rss_config;
2886 };
2887
2888 struct mstorm_eth_conn_ag_ctx {
2889         u8      byte0 /* cdu_validation */;
2890         u8      byte1 /* state */;
2891         u8      flags0;
2892 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK  0x1   /* exist_in_qm0 */
2893 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
2894 #define MSTORM_ETH_CONN_AG_CTX_BIT1_MASK          0x1   /* exist_in_qm1 */
2895 #define MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT         1
2896 #define MSTORM_ETH_CONN_AG_CTX_CF0_MASK           0x3   /* cf0 */
2897 #define MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT          2
2898 #define MSTORM_ETH_CONN_AG_CTX_CF1_MASK           0x3   /* cf1 */
2899 #define MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT          4
2900 #define MSTORM_ETH_CONN_AG_CTX_CF2_MASK           0x3   /* cf2 */
2901 #define MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT          6
2902         u8 flags1;
2903 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK         0x1   /* cf0en */
2904 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT        0
2905 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK         0x1   /* cf1en */
2906 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT        1
2907 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK         0x1   /* cf2en */
2908 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT        2
2909 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK       0x1   /* rule0en */
2910 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT      3
2911 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK       0x1   /* rule1en */
2912 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT      4
2913 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK       0x1   /* rule2en */
2914 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT      5
2915 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK       0x1   /* rule3en */
2916 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT      6
2917 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK       0x1   /* rule4en */
2918 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT      7
2919         __le16  word0 /* word0 */;
2920         __le16  word1 /* word1 */;
2921         __le32  reg0 /* reg0 */;
2922         __le32  reg1 /* reg1 */;
2923 };
2924
2925 struct tstorm_eth_conn_ag_ctx {
2926         u8      byte0 /* cdu_validation */;
2927         u8      byte1 /* state */;
2928         u8      flags0;
2929 #define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK      0x1       /* exist_in_qm0 */
2930 #define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT     0
2931 #define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK      0x1       /* exist_in_qm1 */
2932 #define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT     1
2933 #define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK      0x1       /* bit2 */
2934 #define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT     2
2935 #define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK      0x1       /* bit3 */
2936 #define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT     3
2937 #define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK      0x1       /* bit4 */
2938 #define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT     4
2939 #define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK      0x1       /* bit5 */
2940 #define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT     5
2941 #define TSTORM_ETH_CONN_AG_CTX_CF0_MASK       0x3       /* timer0cf */
2942 #define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT      6
2943         u8 flags1;
2944 #define TSTORM_ETH_CONN_AG_CTX_CF1_MASK       0x3       /* timer1cf */
2945 #define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT      0
2946 #define TSTORM_ETH_CONN_AG_CTX_CF2_MASK       0x3       /* timer2cf */
2947 #define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT      2
2948 #define TSTORM_ETH_CONN_AG_CTX_CF3_MASK       0x3       /* timer_stop_all */
2949 #define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT      4
2950 #define TSTORM_ETH_CONN_AG_CTX_CF4_MASK       0x3       /* cf4 */
2951 #define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT      6
2952         u8 flags2;
2953 #define TSTORM_ETH_CONN_AG_CTX_CF5_MASK       0x3       /* cf5 */
2954 #define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT      0
2955 #define TSTORM_ETH_CONN_AG_CTX_CF6_MASK       0x3       /* cf6 */
2956 #define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT      2
2957 #define TSTORM_ETH_CONN_AG_CTX_CF7_MASK       0x3       /* cf7 */
2958 #define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT      4
2959 #define TSTORM_ETH_CONN_AG_CTX_CF8_MASK       0x3       /* cf8 */
2960 #define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT      6
2961         u8 flags3;
2962 #define TSTORM_ETH_CONN_AG_CTX_CF9_MASK       0x3       /* cf9 */
2963 #define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT      0
2964 #define TSTORM_ETH_CONN_AG_CTX_CF10_MASK      0x3       /* cf10 */
2965 #define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT     2
2966 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK     0x1       /* cf0en */
2967 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT    4
2968 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK     0x1       /* cf1en */
2969 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT    5
2970 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK     0x1       /* cf2en */
2971 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT    6
2972 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK     0x1       /* cf3en */
2973 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT    7
2974         u8 flags4;
2975 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK     0x1       /* cf4en */
2976 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT    0
2977 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK     0x1       /* cf5en */
2978 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT    1
2979 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK     0x1       /* cf6en */
2980 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT    2
2981 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK     0x1       /* cf7en */
2982 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT    3
2983 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK     0x1       /* cf8en */
2984 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT    4
2985 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK     0x1       /* cf9en */
2986 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT    5
2987 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK    0x1       /* cf10en */
2988 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT   6
2989 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK   0x1       /* rule0en */
2990 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT  7
2991         u8 flags5;
2992 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK   0x1       /* rule1en */
2993 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT  0
2994 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK   0x1       /* rule2en */
2995 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT  1
2996 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK   0x1       /* rule3en */
2997 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT  2
2998 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK   0x1       /* rule4en */
2999 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT  3
3000 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK   0x1       /* rule5en */
3001 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT  4
3002 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK  0x1       /* rule6en */
3003 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
3004 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK   0x1       /* rule7en */
3005 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT  6
3006 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK   0x1       /* rule8en */
3007 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT  7
3008         __le32  reg0 /* reg0 */;
3009         __le32  reg1 /* reg1 */;
3010         __le32  reg2 /* reg2 */;
3011         __le32  reg3 /* reg3 */;
3012         __le32  reg4 /* reg4 */;
3013         __le32  reg5 /* reg5 */;
3014         __le32  reg6 /* reg6 */;
3015         __le32  reg7 /* reg7 */;
3016         __le32  reg8 /* reg8 */;
3017         u8      byte2 /* byte2 */;
3018         u8      byte3 /* byte3 */;
3019         __le16  rx_bd_cons /* word0 */;
3020         u8      byte4 /* byte4 */;
3021         u8      byte5 /* byte5 */;
3022         __le16  rx_bd_prod /* word1 */;
3023         __le16  word2 /* conn_dpi */;
3024         __le16  word3 /* word3 */;
3025         __le32  reg9 /* reg9 */;
3026         __le32  reg10 /* reg10 */;
3027 };
3028
3029 struct ustorm_eth_conn_ag_ctx {
3030         u8      byte0 /* cdu_validation */;
3031         u8      byte1 /* state */;
3032         u8      flags0;
3033 #define USTORM_ETH_CONN_AG_CTX_BIT0_MASK                  0x1
3034 #define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT                 0
3035 #define USTORM_ETH_CONN_AG_CTX_BIT1_MASK                  0x1
3036 #define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT                 1
3037 #define USTORM_ETH_CONN_AG_CTX_CF0_MASK                   0x3   /* timer0cf */
3038 #define USTORM_ETH_CONN_AG_CTX_CF0_SHIFT                  2
3039 #define USTORM_ETH_CONN_AG_CTX_CF1_MASK                   0x3   /* timer1cf */
3040 #define USTORM_ETH_CONN_AG_CTX_CF1_SHIFT                  4
3041 #define USTORM_ETH_CONN_AG_CTX_CF2_MASK                   0x3   /* timer2cf */
3042 #define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT                  6
3043         u8 flags1;
3044 #define USTORM_ETH_CONN_AG_CTX_CF3_MASK                   0x3
3045 #define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT                  0
3046 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK             0x3   /* cf4 */
3047 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT            2
3048 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK             0x3   /* cf5 */
3049 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT            4
3050 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK     0x3   /* cf6 */
3051 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT    6
3052         u8 flags2;
3053 #define USTORM_ETH_CONN_AG_CTX_CF0EN_MASK                 0x1   /* cf0en */
3054 #define USTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT                0
3055 #define USTORM_ETH_CONN_AG_CTX_CF1EN_MASK                 0x1   /* cf1en */
3056 #define USTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT                1
3057 #define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK                 0x1   /* cf2en */
3058 #define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT                2
3059 #define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK                 0x1   /* cf3en */
3060 #define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT                3
3061 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK          0x1   /* cf4en */
3062 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT         4
3063 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK          0x1   /* cf5en */
3064 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT         5
3065 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK  0x1   /* cf6en */
3066 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6
3067 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK               0x1   /* rule0en */
3068 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT              7
3069         u8 flags3;
3070 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK               0x1   /* rule1en */
3071 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT              0
3072 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK               0x1   /* rule2en */
3073 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT              1
3074 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK               0x1   /* rule3en */
3075 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT              2
3076 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK               0x1   /* rule4en */
3077 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT              3
3078 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK               0x1   /* rule5en */
3079 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT              4
3080 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK               0x1   /* rule6en */
3081 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT              5
3082 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK               0x1   /* rule7en */
3083 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT              6
3084 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK               0x1   /* rule8en */
3085 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT              7
3086         u8      byte2 /* byte2 */;
3087         u8      byte3 /* byte3 */;
3088         __le16  word0 /* conn_dpi */;
3089         __le16  tx_bd_cons /* word1 */;
3090         __le32  reg0 /* reg0 */;
3091         __le32  reg1 /* reg1 */;
3092         __le32  reg2 /* reg2 */;
3093         __le32  reg3 /* reg3 */;
3094         __le16  tx_drv_bd_cons /* word2 */;
3095         __le16  rx_drv_cqe_cons /* word3 */;
3096 };
3097
3098 struct xstorm_eth_hw_conn_ag_ctx {
3099         u8      reserved0 /* cdu_validation */;
3100         u8      eth_state /* state */;
3101         u8      flags0;
3102 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK            0x1
3103 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT           0
3104 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK               0x1
3105 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT              1
3106 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK               0x1
3107 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT              2
3108 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK            0x1
3109 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT           3
3110 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK               0x1
3111 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT              4
3112 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK               0x1
3113 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT              5
3114 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK               0x1
3115 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT              6
3116 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK               0x1
3117 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT              7
3118         u8 flags1;
3119 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK               0x1
3120 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT              0
3121 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK               0x1
3122 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT              1
3123 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK               0x1
3124 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT              2
3125 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK                   0x1
3126 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT                  3
3127 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_MASK                   0x1
3128 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_SHIFT                  4
3129 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_MASK                   0x1
3130 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_SHIFT                  5
3131 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK          0x1
3132 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT         6
3133 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK            0x1
3134 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT           7
3135         u8 flags2;
3136 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK                     0x3
3137 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT                    0
3138 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK                     0x3
3139 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT                    2
3140 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK                     0x3
3141 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT                    4
3142 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK                     0x3
3143 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT                    6
3144         u8 flags3;
3145 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK                     0x3
3146 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT                    0
3147 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK                     0x3
3148 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT                    2
3149 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK                     0x3
3150 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT                    4
3151 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK                     0x3
3152 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT                    6
3153         u8 flags4;
3154 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK                     0x3
3155 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT                    0
3156 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK                     0x3
3157 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT                    2
3158 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK                    0x3
3159 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT                   4
3160 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK                    0x3
3161 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT                   6
3162         u8 flags5;
3163 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK                    0x3
3164 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT                   0
3165 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK                    0x3
3166 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT                   2
3167 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK                    0x3
3168 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT                   4
3169 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK                    0x3
3170 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT                   6
3171         u8 flags6;
3172 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK        0x3
3173 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT       0
3174 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK        0x3
3175 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT       2
3176 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK                   0x3
3177 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT                  4
3178 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK            0x3
3179 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT           6
3180         u8 flags7;
3181 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK                0x3
3182 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT               0
3183 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK              0x3
3184 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT             2
3185 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK               0x3
3186 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT              4
3187 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK                   0x1
3188 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT                  6
3189 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK                   0x1
3190 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT                  7
3191         u8 flags8;
3192 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK                   0x1
3193 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT                  0
3194 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK                   0x1
3195 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT                  1
3196 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK                   0x1
3197 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT                  2
3198 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK                   0x1
3199 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT                  3
3200 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK                   0x1
3201 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT                  4
3202 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK                   0x1
3203 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT                  5
3204 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK                   0x1
3205 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT                  6
3206 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK                   0x1
3207 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT                  7
3208         u8 flags9;
3209 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK                  0x1
3210 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT                 0
3211 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK                  0x1
3212 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT                 1
3213 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK                  0x1
3214 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT                 2
3215 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK                  0x1
3216 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT                 3
3217 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK                  0x1
3218 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT                 4
3219 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK                  0x1
3220 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT                 5
3221 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK     0x1
3222 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT    6
3223 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK     0x1
3224 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT    7
3225         u8 flags10;
3226 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK                0x1
3227 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT               0
3228 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK         0x1
3229 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT        1
3230 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK             0x1
3231 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT            2
3232 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK              0x1
3233 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT             3
3234 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK            0x1
3235 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT           4
3236 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK  0x1
3237 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
3238 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK              0x1
3239 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT             6
3240 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK              0x1
3241 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT             7
3242         u8 flags11;
3243 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK              0x1
3244 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT             0
3245 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK              0x1
3246 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT             1
3247 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK          0x1
3248 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT         2
3249 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK                 0x1
3250 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT                3
3251 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK                 0x1
3252 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT                4
3253 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK                 0x1
3254 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT                5
3255 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK            0x1
3256 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT           6
3257 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK                 0x1
3258 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT                7
3259         u8 flags12;
3260 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK                0x1
3261 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT               0
3262 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK                0x1
3263 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT               1
3264 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK            0x1
3265 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT           2
3266 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK            0x1
3267 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT           3
3268 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK                0x1
3269 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT               4
3270 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK                0x1
3271 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT               5
3272 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK                0x1
3273 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT               6
3274 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK                0x1
3275 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT               7
3276         u8 flags13;
3277 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK                0x1
3278 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT               0
3279 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK                0x1
3280 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT               1
3281 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK            0x1
3282 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT           2
3283 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK            0x1
3284 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT           3
3285 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK            0x1
3286 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT           4
3287 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK            0x1
3288 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT           5
3289 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK            0x1
3290 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT           6
3291 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK            0x1
3292 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT           7
3293         u8 flags14;
3294 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK        0x1
3295 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT       0
3296 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK      0x1
3297 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT     1
3298 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK    0x1
3299 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT   2
3300 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK    0x1
3301 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT   3
3302 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK          0x1
3303 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT         4
3304 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK        0x1
3305 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT       5
3306 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK              0x3
3307 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT             6
3308         u8      edpm_event_id /* byte2 */;
3309         __le16  physical_q0 /* physical_q0 */;
3310         __le16  word1 /* physical_q1 */;
3311         __le16  edpm_num_bds /* physical_q2 */;
3312         __le16  tx_bd_cons /* word3 */;
3313         __le16  tx_bd_prod /* word4 */;
3314         __le16  go_to_bd_cons /* word5 */;
3315         __le16  conn_dpi /* conn_dpi */;
3316 };
3317
3318 #define VF_MAX_STATIC 192       /* In case of K2 */
3319
3320 #define MCP_GLOB_PATH_MAX       2
3321 #define MCP_PORT_MAX            2       /* Global */
3322 #define MCP_GLOB_PORT_MAX       4       /* Global */
3323 #define MCP_GLOB_FUNC_MAX       16      /* Global */
3324
3325 typedef u32 offsize_t;                  /* In DWORDS !!! */
3326 /* Offset from the beginning of the MCP scratchpad */
3327 #define OFFSIZE_OFFSET_SHIFT    0
3328 #define OFFSIZE_OFFSET_MASK     0x0000ffff
3329 /* Size of specific element (not the whole array if any) */
3330 #define OFFSIZE_SIZE_SHIFT      16
3331 #define OFFSIZE_SIZE_MASK       0xffff0000
3332
3333 /* SECTION_OFFSET is calculating the offset in bytes out of offsize */
3334 #define SECTION_OFFSET(_offsize)        ((((_offsize &              \
3335                                             OFFSIZE_OFFSET_MASK) >> \
3336                                            OFFSIZE_OFFSET_SHIFT) << 2))
3337
3338 /* QED_SECTION_SIZE is calculating the size in bytes out of offsize */
3339 #define QED_SECTION_SIZE(_offsize)              (((_offsize &            \
3340                                                    OFFSIZE_SIZE_MASK) >> \
3341                                                   OFFSIZE_SIZE_SHIFT) << 2)
3342
3343 /* SECTION_ADDR returns the GRC addr of a section, given offsize and index
3344  * within section.
3345  */
3346 #define SECTION_ADDR(_offsize, idx)     (MCP_REG_SCRATCH +          \
3347                                          SECTION_OFFSET(_offsize) + \
3348                                          (QED_SECTION_SIZE(_offsize) * idx))
3349
3350 /* SECTION_OFFSIZE_ADDR returns the GRC addr to the offsize address.
3351  * Use offsetof, since the OFFSETUP collide with the firmware definition
3352  */
3353 #define SECTION_OFFSIZE_ADDR(_pub_base, _section) (_pub_base +               \
3354                                                    offsetof(struct           \
3355                                                             mcp_public_data, \
3356                                                             sections[_section]))
3357 /* PHY configuration */
3358 struct pmm_phy_cfg {
3359         u32     speed;
3360 #define PMM_SPEED_AUTONEG   0
3361
3362         u32     pause;  /* bitmask */
3363 #define PMM_PAUSE_NONE          0x0
3364 #define PMM_PAUSE_AUTONEG       0x1
3365 #define PMM_PAUSE_RX            0x2
3366 #define PMM_PAUSE_TX            0x4
3367
3368         u32     adv_speed;  /* Default should be the speed_cap_mask */
3369         u32     loopback_mode;
3370 #define PMM_LOOPBACK_NONE               0
3371 #define PMM_LOOPBACK_INT_PHY    1
3372 #define PMM_LOOPBACK_EXT_PHY    2
3373 #define PMM_LOOPBACK_EXT                3
3374 #define PMM_LOOPBACK_MAC                4
3375
3376         /* features */
3377         u32 feature_config_flags;
3378 };
3379
3380 struct port_mf_cfg {
3381         u32     dynamic_cfg; /* device control channel */
3382 #define PORT_MF_CFG_OV_TAG_MASK              0x0000ffff
3383 #define PORT_MF_CFG_OV_TAG_SHIFT             0
3384 #define PORT_MF_CFG_OV_TAG_DEFAULT         PORT_MF_CFG_OV_TAG_MASK
3385
3386         u32     reserved[1];
3387 };
3388
3389 /* DO NOT add new fields in the middle
3390  * MUST be synced with struct pmm_stats_map
3391  */
3392 struct pmm_stats {
3393         u64     r64;    /* 0x00 (Offset 0x00 ) RX 64-byte frame counter*/
3394         u64     r127;   /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter*/
3395         u64     r255;
3396         u64     r511;
3397         u64     r1023;
3398         u64     r1518;
3399         u64     r1522;
3400         u64     r2047;
3401         u64     r4095;
3402         u64     r9216;
3403         u64     r16383;
3404         u64     rfcs;   /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/
3405         u64     rxcf;   /* 0x10 (Offset 0x60 ) RX control frame counter*/
3406         u64     rxpf;   /* 0x11 (Offset 0x68 ) RX pause frame counter*/
3407         u64     rxpp;   /* 0x12 (Offset 0x70 ) RX PFC frame counter*/
3408         u64     raln;   /* 0x16 (Offset 0x78 ) RX alignment error counter*/
3409         u64     rfcr;   /* 0x19 (Offset 0x80 ) RX false carrier counter */
3410         u64     rovr;   /* 0x1A (Offset 0x88 ) RX oversized frame counter*/
3411         u64     rjbr;   /* 0x1B (Offset 0x90 ) RX jabber frame counter */
3412         u64     rund;   /* 0x34 (Offset 0x98 ) RX undersized frame counter */
3413         u64     rfrg;   /* 0x35 (Offset 0xa0 ) RX fragment counter */
3414         u64     t64;    /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */
3415         u64     t127;
3416         u64     t255;
3417         u64     t511;
3418         u64     t1023;
3419         u64     t1518;
3420         u64     t2047;
3421         u64     t4095;
3422         u64     t9216;
3423         u64     t16383;
3424         u64     txpf;   /* 0x50 (Offset 0xf8 ) TX pause frame counter */
3425         u64     txpp;   /* 0x51 (Offset 0x100) TX PFC frame counter */
3426         u64     tlpiec;
3427         u64     tncl;
3428         u64     rbyte;  /* 0x3d (Offset 0x118) RX byte counter */
3429         u64     rxuca;  /* 0x0c (Offset 0x120) RX UC frame counter */
3430         u64     rxmca;  /* 0x0d (Offset 0x128) RX MC frame counter */
3431         u64     rxbca;  /* 0x0e (Offset 0x130) RX BC frame counter */
3432         u64     rxpok;
3433         u64     tbyte;  /* 0x6f (Offset 0x140) TX byte counter */
3434         u64     txuca;  /* 0x4d (Offset 0x148) TX UC frame counter */
3435         u64     txmca;  /* 0x4e (Offset 0x150) TX MC frame counter */
3436         u64     txbca;  /* 0x4f (Offset 0x158) TX BC frame counter */
3437         u64     txcf;   /* 0x54 (Offset 0x160) TX control frame counter */
3438 };
3439
3440 struct brb_stats {
3441         u64     brb_truncate[8];
3442         u64     brb_discard[8];
3443 };
3444
3445 struct port_stats {
3446         struct brb_stats        brb;
3447         struct pmm_stats        pmm;
3448 };
3449
3450 #define CMT_TEAM0 0
3451 #define CMT_TEAM1 1
3452 #define CMT_TEAM_MAX 2
3453
3454 struct couple_mode_teaming {
3455         u8 port_cmt[MCP_GLOB_PORT_MAX];
3456 #define PORT_CMT_IN_TEAM                BIT(0)
3457
3458 #define PORT_CMT_PORT_ROLE              BIT(1)
3459 #define PORT_CMT_PORT_INACTIVE      (0 << 1)
3460 #define PORT_CMT_PORT_ACTIVE            BIT(1)
3461
3462 #define PORT_CMT_TEAM_MASK              BIT(2)
3463 #define PORT_CMT_TEAM0              (0 << 2)
3464 #define PORT_CMT_TEAM1                  BIT(2)
3465 };
3466
3467 /**************************************
3468 *     LLDP and DCBX HSI structures
3469 **************************************/
3470 #define LLDP_CHASSIS_ID_STAT_LEN 4
3471 #define LLDP_PORT_ID_STAT_LEN 4
3472 #define DCBX_MAX_APP_PROTOCOL           32
3473 #define MAX_SYSTEM_LLDP_TLV_DATA    32
3474
3475 enum lldp_agent_e {
3476         LLDP_NEAREST_BRIDGE = 0,
3477         LLDP_NEAREST_NON_TPMR_BRIDGE,
3478         LLDP_NEAREST_CUSTOMER_BRIDGE,
3479         LLDP_MAX_LLDP_AGENTS
3480 };
3481
3482 struct lldp_config_params_s {
3483         u32 config;
3484 #define LLDP_CONFIG_TX_INTERVAL_MASK        0x000000ff
3485 #define LLDP_CONFIG_TX_INTERVAL_SHIFT       0
3486 #define LLDP_CONFIG_HOLD_MASK               0x00000f00
3487 #define LLDP_CONFIG_HOLD_SHIFT              8
3488 #define LLDP_CONFIG_MAX_CREDIT_MASK         0x0000f000
3489 #define LLDP_CONFIG_MAX_CREDIT_SHIFT        12
3490 #define LLDP_CONFIG_ENABLE_RX_MASK          0x40000000
3491 #define LLDP_CONFIG_ENABLE_RX_SHIFT         30
3492 #define LLDP_CONFIG_ENABLE_TX_MASK          0x80000000
3493 #define LLDP_CONFIG_ENABLE_TX_SHIFT         31
3494         u32     local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
3495         u32     local_port_id[LLDP_PORT_ID_STAT_LEN];
3496 };
3497
3498 struct lldp_status_params_s {
3499         u32     prefix_seq_num;
3500         u32     status; /* TBD */
3501
3502         /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
3503         u32     peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
3504
3505         /* Holds remote Port ID TLV header, subtype and 9B of payload. */
3506         u32     peer_port_id[LLDP_PORT_ID_STAT_LEN];
3507         u32     suffix_seq_num;
3508 };
3509
3510 struct dcbx_ets_feature {
3511         u32 flags;
3512 #define DCBX_ETS_ENABLED_MASK                   0x00000001
3513 #define DCBX_ETS_ENABLED_SHIFT                  0
3514 #define DCBX_ETS_WILLING_MASK                   0x00000002
3515 #define DCBX_ETS_WILLING_SHIFT                  1
3516 #define DCBX_ETS_ERROR_MASK                     0x00000004
3517 #define DCBX_ETS_ERROR_SHIFT                    2
3518 #define DCBX_ETS_CBS_MASK                       0x00000008
3519 #define DCBX_ETS_CBS_SHIFT                      3
3520 #define DCBX_ETS_MAX_TCS_MASK                   0x000000f0
3521 #define DCBX_ETS_MAX_TCS_SHIFT                  4
3522         u32     pri_tc_tbl[1];
3523 #define DCBX_ISCSI_OOO_TC                       4
3524 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET         (DCBX_ISCSI_OOO_TC + 1)
3525         u32     tc_bw_tbl[2];
3526         u32     tc_tsa_tbl[2];
3527 #define DCBX_ETS_TSA_STRICT                     0
3528 #define DCBX_ETS_TSA_CBS                        1
3529 #define DCBX_ETS_TSA_ETS                        2
3530 };
3531
3532 struct dcbx_app_priority_entry {
3533         u32 entry;
3534 #define DCBX_APP_PRI_MAP_MASK       0x000000ff
3535 #define DCBX_APP_PRI_MAP_SHIFT      0
3536 #define DCBX_APP_PRI_0              0x01
3537 #define DCBX_APP_PRI_1              0x02
3538 #define DCBX_APP_PRI_2              0x04
3539 #define DCBX_APP_PRI_3              0x08
3540 #define DCBX_APP_PRI_4              0x10
3541 #define DCBX_APP_PRI_5              0x20
3542 #define DCBX_APP_PRI_6              0x40
3543 #define DCBX_APP_PRI_7              0x80
3544 #define DCBX_APP_SF_MASK            0x00000300
3545 #define DCBX_APP_SF_SHIFT           8
3546 #define DCBX_APP_SF_ETHTYPE         0
3547 #define DCBX_APP_SF_PORT            1
3548 #define DCBX_APP_PROTOCOL_ID_MASK   0xffff0000
3549 #define DCBX_APP_PROTOCOL_ID_SHIFT  16
3550 };
3551
3552 /* FW structure in BE */
3553 struct dcbx_app_priority_feature {
3554         u32 flags;
3555 #define DCBX_APP_ENABLED_MASK           0x00000001
3556 #define DCBX_APP_ENABLED_SHIFT          0
3557 #define DCBX_APP_WILLING_MASK           0x00000002
3558 #define DCBX_APP_WILLING_SHIFT          1
3559 #define DCBX_APP_ERROR_MASK             0x00000004
3560 #define DCBX_APP_ERROR_SHIFT            2
3561 /* Not in use
3562  * #define DCBX_APP_DEFAULT_PRI_MASK       0x00000f00
3563  * #define DCBX_APP_DEFAULT_PRI_SHIFT      8
3564  */
3565 #define DCBX_APP_MAX_TCS_MASK           0x0000f000
3566 #define DCBX_APP_MAX_TCS_SHIFT          12
3567 #define DCBX_APP_NUM_ENTRIES_MASK       0x00ff0000
3568 #define DCBX_APP_NUM_ENTRIES_SHIFT      16
3569         struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
3570 };
3571
3572 /* FW structure in BE */
3573 struct dcbx_features {
3574         /* PG feature */
3575         struct dcbx_ets_feature ets;
3576
3577         /* PFC feature */
3578         u32                     pfc;
3579 #define DCBX_PFC_PRI_EN_BITMAP_MASK             0x000000ff
3580 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT            0
3581 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0            0x01
3582 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1            0x02
3583 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2            0x04
3584 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3            0x08
3585 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4            0x10
3586 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5            0x20
3587 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6            0x40
3588 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7            0x80
3589
3590 #define DCBX_PFC_FLAGS_MASK                     0x0000ff00
3591 #define DCBX_PFC_FLAGS_SHIFT                    8
3592 #define DCBX_PFC_CAPS_MASK                      0x00000f00
3593 #define DCBX_PFC_CAPS_SHIFT                     8
3594 #define DCBX_PFC_MBC_MASK                       0x00004000
3595 #define DCBX_PFC_MBC_SHIFT                      14
3596 #define DCBX_PFC_WILLING_MASK                   0x00008000
3597 #define DCBX_PFC_WILLING_SHIFT                  15
3598 #define DCBX_PFC_ENABLED_MASK                   0x00010000
3599 #define DCBX_PFC_ENABLED_SHIFT                  16
3600 #define DCBX_PFC_ERROR_MASK                     0x00020000
3601 #define DCBX_PFC_ERROR_SHIFT                    17
3602
3603         /* APP feature */
3604         struct dcbx_app_priority_feature app;
3605 };
3606
3607 struct dcbx_local_params {
3608         u32 config;
3609 #define DCBX_CONFIG_VERSION_MASK            0x00000003
3610 #define DCBX_CONFIG_VERSION_SHIFT           0
3611 #define DCBX_CONFIG_VERSION_DISABLED        0
3612 #define DCBX_CONFIG_VERSION_IEEE            1
3613 #define DCBX_CONFIG_VERSION_CEE             2
3614
3615         u32                     flags;
3616         struct dcbx_features    features;
3617 };
3618
3619 struct dcbx_mib {
3620         u32     prefix_seq_num;
3621         u32     flags;
3622         struct dcbx_features    features;
3623         u32                     suffix_seq_num;
3624 };
3625
3626 struct lldp_system_tlvs_buffer_s {
3627         u16     valid;
3628         u16     length;
3629         u32     data[MAX_SYSTEM_LLDP_TLV_DATA];
3630 };
3631
3632 /**************************************/
3633 /*                                    */
3634 /*     P U B L I C      G L O B A L   */
3635 /*                                    */
3636 /**************************************/
3637 struct public_global {
3638         u32                             max_path;
3639 #define MAX_PATH_BIG_BEAR       2
3640 #define MAX_PATH_K2             1
3641         u32                             max_ports;
3642 #define MODE_1P 1
3643 #define MODE_2P 2
3644 #define MODE_3P 3
3645 #define MODE_4P 4
3646         u32                             debug_mb_offset;
3647         u32                             phymod_dbg_mb_offset;
3648         struct couple_mode_teaming      cmt;
3649         s32                             internal_temperature;
3650         u32                             mfw_ver;
3651         u32                             running_bundle_id;
3652 };
3653
3654 /**************************************/
3655 /*                                    */
3656 /*     P U B L I C      P A T H       */
3657 /*                                    */
3658 /**************************************/
3659
3660 /****************************************************************************
3661 * Shared Memory 2 Region                                                   *
3662 ****************************************************************************/
3663 /* The fw_flr_ack is actually built in the following way:                   */
3664 /* 8 bit:  PF ack                                                           */
3665 /* 128 bit: VF ack                                                           */
3666 /* 8 bit:  ios_dis_ack                                                      */
3667 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
3668 /* u32. The fw must have the VF right after the PF since this is how it     */
3669 /* access arrays(it expects always the VF to reside after the PF, and that  */
3670 /* makes the calculation much easier for it. )                              */
3671 /* In order to answer both limitations, and keep the struct small, the code */
3672 /* will abuse the structure defined here to achieve the actual partition    */
3673 /* above                                                                    */
3674 /****************************************************************************/
3675 struct fw_flr_mb {
3676         u32     aggint;
3677         u32     opgen_addr;
3678         u32     accum_ack;  /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */
3679 #define ACCUM_ACK_PF_BASE       0
3680 #define ACCUM_ACK_PF_SHIFT      0
3681
3682 #define ACCUM_ACK_VF_BASE       8
3683 #define ACCUM_ACK_VF_SHIFT      3
3684
3685 #define ACCUM_ACK_IOV_DIS_BASE  256
3686 #define ACCUM_ACK_IOV_DIS_SHIFT 8
3687 };
3688
3689 struct public_path {
3690         struct fw_flr_mb        flr_mb;
3691         u32                     mcp_vf_disabled[VF_MAX_STATIC / 32];
3692
3693         u32                     process_kill;
3694 #define PROCESS_KILL_COUNTER_MASK               0x0000ffff
3695 #define PROCESS_KILL_COUNTER_SHIFT              0
3696 #define PROCESS_KILL_GLOB_AEU_BIT_MASK          0xffff0000
3697 #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT         16
3698 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit)
3699 };
3700
3701 /**************************************/
3702 /*                                    */
3703 /*     P U B L I C      P O R T       */
3704 /*                                    */
3705 /**************************************/
3706
3707 /****************************************************************************
3708 * Driver <-> FW Mailbox                                                    *
3709 ****************************************************************************/
3710
3711 struct public_port {
3712         u32 validity_map;   /* 0x0 (4*2 = 0x8) */
3713
3714         /* validity bits */
3715 #define MCP_VALIDITY_PCI_CFG                    0x00100000
3716 #define MCP_VALIDITY_MB                         0x00200000
3717 #define MCP_VALIDITY_DEV_INFO                   0x00400000
3718 #define MCP_VALIDITY_RESERVED                   0x00000007
3719
3720         /* One licensing bit should be set */
3721 #define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK     0x00000038
3722 #define MCP_VALIDITY_LIC_MANUF_KEY_IN_EFFECT    0x00000008
3723 #define MCP_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT  0x00000010
3724 #define MCP_VALIDITY_LIC_NO_KEY_IN_EFFECT       0x00000020
3725
3726         /* Active MFW */
3727 #define MCP_VALIDITY_ACTIVE_MFW_UNKNOWN         0x00000000
3728 #define MCP_VALIDITY_ACTIVE_MFW_MASK            0x000001c0
3729 #define MCP_VALIDITY_ACTIVE_MFW_NCSI            0x00000040
3730 #define MCP_VALIDITY_ACTIVE_MFW_NONE            0x000001c0
3731
3732         u32 link_status;
3733 #define LINK_STATUS_LINK_UP \
3734         0x00000001
3735 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK                       0x0000001e
3736 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD            BIT(1)
3737 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD            (2 << 1)
3738 #define LINK_STATUS_SPEED_AND_DUPLEX_10G                        (3 << 1)
3739 #define LINK_STATUS_SPEED_AND_DUPLEX_20G                        (4 << 1)
3740 #define LINK_STATUS_SPEED_AND_DUPLEX_40G                        (5 << 1)
3741 #define LINK_STATUS_SPEED_AND_DUPLEX_50G                        (6 << 1)
3742 #define LINK_STATUS_SPEED_AND_DUPLEX_100G                       (7 << 1)
3743 #define LINK_STATUS_SPEED_AND_DUPLEX_25G                        (8 << 1)
3744
3745 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED                      0x00000020
3746
3747 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE                     0x00000040
3748 #define LINK_STATUS_PARALLEL_DETECTION_USED                     0x00000080
3749
3750 #define LINK_STATUS_PFC_ENABLED \
3751         0x00000100
3752 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE        0x00000200
3753 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE        0x00000400
3754 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE            0x00000800
3755 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE            0x00001000
3756 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE            0x00002000
3757 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE            0x00004000
3758 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE           0x00008000
3759 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE            0x00010000
3760
3761 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK      0x000C0000
3762 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE      (0 << 18)
3763 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE        BIT(18)
3764 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE       (2 << 18)
3765 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE                     (3 << 18)
3766
3767 #define LINK_STATUS_SFP_TX_FAULT \
3768         0x00100000
3769 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED                     0x00200000
3770 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED                     0x00400000
3771
3772         u32                     link_status1;
3773         u32                     ext_phy_fw_version;
3774         u32                     drv_phy_cfg_addr;
3775
3776         u32                     port_stx;
3777
3778         u32                     stat_nig_timer;
3779
3780         struct port_mf_cfg      port_mf_config;
3781         struct port_stats       stats;
3782
3783         u32                     media_type;
3784 #define MEDIA_UNSPECIFIED       0x0
3785 #define MEDIA_SFPP_10G_FIBER    0x1
3786 #define MEDIA_XFP_FIBER         0x2
3787 #define MEDIA_DA_TWINAX         0x3
3788 #define MEDIA_BASE_T            0x4
3789 #define MEDIA_SFP_1G_FIBER      0x5
3790 #define MEDIA_KR                0xf0
3791 #define MEDIA_NOT_PRESENT       0xff
3792
3793         u32 lfa_status;
3794 #define LFA_LINK_FLAP_REASON_OFFSET             0
3795 #define LFA_LINK_FLAP_REASON_MASK               0x000000ff
3796 #define LFA_NO_REASON                                   (0 << 0)
3797 #define LFA_LINK_DOWN                                   BIT(0)
3798 #define LFA_FORCE_INIT                                  BIT(1)
3799 #define LFA_LOOPBACK_MISMATCH                           BIT(2)
3800 #define LFA_SPEED_MISMATCH                              BIT(3)
3801 #define LFA_FLOW_CTRL_MISMATCH                          BIT(4)
3802 #define LFA_ADV_SPEED_MISMATCH                          BIT(5)
3803 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET        8
3804 #define LINK_FLAP_AVOIDANCE_COUNT_MASK          0x0000ff00
3805 #define LINK_FLAP_COUNT_OFFSET                  16
3806 #define LINK_FLAP_COUNT_MASK                    0x00ff0000
3807
3808         u32                                     link_change_count;
3809
3810         /* LLDP params */
3811         struct lldp_config_params_s             lldp_config_params[
3812                 LLDP_MAX_LLDP_AGENTS];
3813         struct lldp_status_params_s             lldp_status_params[
3814                 LLDP_MAX_LLDP_AGENTS];
3815         struct lldp_system_tlvs_buffer_s        system_lldp_tlvs_buf;
3816
3817         /* DCBX related MIB */
3818         struct dcbx_local_params                local_admin_dcbx_mib;
3819         struct dcbx_mib                         remote_dcbx_mib;
3820         struct dcbx_mib                         operational_dcbx_mib;
3821 };
3822
3823 /**************************************/
3824 /*                                    */
3825 /*     P U B L I C      F U N C       */
3826 /*                                    */
3827 /**************************************/
3828
3829 struct public_func {
3830         u32     iscsi_boot_signature;
3831         u32     iscsi_boot_block_offset;
3832
3833         u32     reserved[8];
3834
3835         u32     config;
3836
3837         /* E/R/I/D */
3838         /* function 0 of each port cannot be hidden */
3839 #define FUNC_MF_CFG_FUNC_HIDE                   0x00000001
3840 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING          0x00000002
3841 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT    0x00000001
3842
3843 #define FUNC_MF_CFG_PROTOCOL_MASK               0x000000f0
3844 #define FUNC_MF_CFG_PROTOCOL_SHIFT              4
3845 #define FUNC_MF_CFG_PROTOCOL_ETHERNET           0x00000000
3846 #define FUNC_MF_CFG_PROTOCOL_ISCSI              0x00000010
3847 #define FUNC_MF_CFG_PROTOCOL_FCOE               0x00000020
3848 #define FUNC_MF_CFG_PROTOCOL_ROCE               0x00000030
3849 #define FUNC_MF_CFG_PROTOCOL_MAX                0x00000030
3850
3851         /* MINBW, MAXBW */
3852         /* value range - 0..100, increments in 1 %  */
3853 #define FUNC_MF_CFG_MIN_BW_MASK                 0x0000ff00
3854 #define FUNC_MF_CFG_MIN_BW_SHIFT                8
3855 #define FUNC_MF_CFG_MIN_BW_DEFAULT              0x00000000
3856 #define FUNC_MF_CFG_MAX_BW_MASK                 0x00ff0000
3857 #define FUNC_MF_CFG_MAX_BW_SHIFT                16
3858 #define FUNC_MF_CFG_MAX_BW_DEFAULT              0x00640000
3859
3860         u32     status;
3861 #define FUNC_STATUS_VLINK_DOWN                  0x00000001
3862
3863         u32     mac_upper;  /* MAC */
3864 #define FUNC_MF_CFG_UPPERMAC_MASK               0x0000ffff
3865 #define FUNC_MF_CFG_UPPERMAC_SHIFT              0
3866 #define FUNC_MF_CFG_UPPERMAC_DEFAULT            FUNC_MF_CFG_UPPERMAC_MASK
3867         u32     mac_lower;
3868 #define FUNC_MF_CFG_LOWERMAC_DEFAULT            0xffffffff
3869
3870         u32     fcoe_wwn_port_name_upper;
3871         u32     fcoe_wwn_port_name_lower;
3872
3873         u32     fcoe_wwn_node_name_upper;
3874         u32     fcoe_wwn_node_name_lower;
3875
3876         u32     ovlan_stag; /* tags */
3877 #define FUNC_MF_CFG_OV_STAG_MASK              0x0000ffff
3878 #define FUNC_MF_CFG_OV_STAG_SHIFT             0
3879 #define FUNC_MF_CFG_OV_STAG_DEFAULT           FUNC_MF_CFG_OV_STAG_MASK
3880
3881         u32     pf_allocation;  /* vf per pf */
3882
3883         u32     preserve_data;  /* Will be used bt CCM */
3884
3885         u32     driver_last_activity_ts;
3886
3887         u32     drv_ack_vf_disabled[VF_MAX_STATIC / 32]; /* 0x0044 */
3888
3889         u32     drv_id;
3890 #define DRV_ID_PDA_COMP_VER_MASK        0x0000ffff
3891 #define DRV_ID_PDA_COMP_VER_SHIFT       0
3892
3893 #define DRV_ID_MCP_HSI_VER_MASK         0x00ff0000
3894 #define DRV_ID_MCP_HSI_VER_SHIFT        16
3895 #define DRV_ID_MCP_HSI_VER_CURRENT      BIT(DRV_ID_MCP_HSI_VER_SHIFT)
3896
3897 #define DRV_ID_DRV_TYPE_MASK            0xff000000
3898 #define DRV_ID_DRV_TYPE_SHIFT           24
3899 #define DRV_ID_DRV_TYPE_UNKNOWN         (0 << DRV_ID_DRV_TYPE_SHIFT)
3900 #define DRV_ID_DRV_TYPE_LINUX           BIT(DRV_ID_DRV_TYPE_SHIFT)
3901 #define DRV_ID_DRV_TYPE_WINDOWS         (2 << DRV_ID_DRV_TYPE_SHIFT)
3902 #define DRV_ID_DRV_TYPE_DIAG            (3 << DRV_ID_DRV_TYPE_SHIFT)
3903 #define DRV_ID_DRV_TYPE_PREBOOT         (4 << DRV_ID_DRV_TYPE_SHIFT)
3904 #define DRV_ID_DRV_TYPE_SOLARIS         (5 << DRV_ID_DRV_TYPE_SHIFT)
3905 #define DRV_ID_DRV_TYPE_VMWARE          (6 << DRV_ID_DRV_TYPE_SHIFT)
3906 #define DRV_ID_DRV_TYPE_FREEBSD         (7 << DRV_ID_DRV_TYPE_SHIFT)
3907 #define DRV_ID_DRV_TYPE_AIX             (8 << DRV_ID_DRV_TYPE_SHIFT)
3908 };
3909
3910 /**************************************/
3911 /*                                    */
3912 /*     P U B L I C       M B          */
3913 /*                                    */
3914 /**************************************/
3915 /* This is the only section that the driver can write to, and each */
3916 /* Basically each driver request to set feature parameters,
3917  * will be done using a different command, which will be linked
3918  * to a specific data structure from the union below.
3919  * For huge strucuture, the common blank structure should be used.
3920  */
3921
3922 struct mcp_mac {
3923         u32     mac_upper;  /* Upper 16 bits are always zeroes */
3924         u32     mac_lower;
3925 };
3926
3927 struct mcp_val64 {
3928         u32     lo;
3929         u32     hi;
3930 };
3931
3932 struct mcp_file_att {
3933         u32     nvm_start_addr;
3934         u32     len;
3935 };
3936
3937 #define MCP_DRV_VER_STR_SIZE 16
3938 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
3939 #define MCP_DRV_NVM_BUF_LEN 32
3940 struct drv_version_stc {
3941         u32     version;
3942         u8      name[MCP_DRV_VER_STR_SIZE - 4];
3943 };
3944
3945 union drv_union_data {
3946         u32                     ver_str[MCP_DRV_VER_STR_SIZE_DWORD];
3947         struct mcp_mac          wol_mac;
3948
3949         struct pmm_phy_cfg      drv_phy_cfg;
3950
3951         struct mcp_val64        val64; /* For PHY / AVS commands */
3952
3953         u8                      raw_data[MCP_DRV_NVM_BUF_LEN];
3954
3955         struct mcp_file_att     file_att;
3956
3957         u32                     ack_vf_disabled[VF_MAX_STATIC / 32];
3958
3959         struct drv_version_stc  drv_version;
3960 };
3961
3962 struct public_drv_mb {
3963         u32 drv_mb_header;
3964 #define DRV_MSG_CODE_MASK                       0xffff0000
3965 #define DRV_MSG_CODE_LOAD_REQ                   0x10000000
3966 #define DRV_MSG_CODE_LOAD_DONE                  0x11000000
3967 #define DRV_MSG_CODE_UNLOAD_REQ                 0x20000000
3968 #define DRV_MSG_CODE_UNLOAD_DONE                0x21000000
3969 #define DRV_MSG_CODE_INIT_PHY                   0x22000000
3970         /* Params - FORCE - Reinitialize the link regardless of LFA */
3971         /*        - DONT_CARE - Don't flap the link if up */
3972 #define DRV_MSG_CODE_LINK_RESET                 0x23000000
3973
3974 #define DRV_MSG_CODE_SET_LLDP                   0x24000000
3975 #define DRV_MSG_CODE_SET_DCBX                   0x25000000
3976
3977 #define DRV_MSG_CODE_NIG_DRAIN                  0x30000000
3978
3979 #define DRV_MSG_CODE_INITIATE_FLR               0x02000000
3980 #define DRV_MSG_CODE_VF_DISABLED_DONE           0xc0000000
3981 #define DRV_MSG_CODE_CFG_VF_MSIX                0xc0010000
3982 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN         0x00010000
3983 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA          0x00020000
3984 #define DRV_MSG_CODE_NVM_GET_FILE_ATT           0x00030000
3985 #define DRV_MSG_CODE_NVM_READ_NVRAM             0x00050000
3986 #define DRV_MSG_CODE_NVM_WRITE_NVRAM            0x00060000
3987 #define DRV_MSG_CODE_NVM_DEL_FILE               0x00080000
3988 #define DRV_MSG_CODE_MCP_RESET                  0x00090000
3989 #define DRV_MSG_CODE_SET_SECURE_MODE            0x000a0000
3990 #define DRV_MSG_CODE_PHY_RAW_READ               0x000b0000
3991 #define DRV_MSG_CODE_PHY_RAW_WRITE              0x000c0000
3992 #define DRV_MSG_CODE_PHY_CORE_READ              0x000d0000
3993 #define DRV_MSG_CODE_PHY_CORE_WRITE             0x000e0000
3994 #define DRV_MSG_CODE_SET_VERSION                0x000f0000
3995
3996 #define DRV_MSG_SEQ_NUMBER_MASK                 0x0000ffff
3997
3998         u32 drv_mb_param;
3999
4000         /* UNLOAD_REQ params */
4001 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN         0x00000000
4002 #define DRV_MB_PARAM_UNLOAD_WOL_MCP             0x00000001
4003 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED        0x00000002
4004 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED         0x00000003
4005
4006         /* UNLOAD_DONE_params */
4007 #define DRV_MB_PARAM_UNLOAD_NON_D3_POWER        0x00000001
4008
4009         /* INIT_PHY params */
4010 #define DRV_MB_PARAM_INIT_PHY_FORCE             0x00000001
4011 #define DRV_MB_PARAM_INIT_PHY_DONT_CARE         0x00000002
4012
4013         /* LLDP / DCBX params*/
4014 #define DRV_MB_PARAM_LLDP_SEND_MASK             0x00000001
4015 #define DRV_MB_PARAM_LLDP_SEND_SHIFT            0
4016 #define DRV_MB_PARAM_LLDP_AGENT_MASK            0x00000006
4017 #define DRV_MB_PARAM_LLDP_AGENT_SHIFT           1
4018 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK           0x00000008
4019 #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT          3
4020
4021 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK   0x000000FF
4022 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_SHIFT  0
4023
4024 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW     0x1
4025 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE   0x2
4026
4027 #define DRV_MB_PARAM_NVM_OFFSET_SHIFT           0
4028 #define DRV_MB_PARAM_NVM_OFFSET_MASK            0x00FFFFFF
4029 #define DRV_MB_PARAM_NVM_LEN_SHIFT              24
4030 #define DRV_MB_PARAM_NVM_LEN_MASK               0xFF000000
4031
4032 #define DRV_MB_PARAM_PHY_ADDR_SHIFT             0
4033 #define DRV_MB_PARAM_PHY_ADDR_MASK              0x1FF0FFFF
4034 #define DRV_MB_PARAM_PHY_LANE_SHIFT             16
4035 #define DRV_MB_PARAM_PHY_LANE_MASK              0x000F0000
4036 #define DRV_MB_PARAM_PHY_SELECT_PORT_SHIFT      29
4037 #define DRV_MB_PARAM_PHY_SELECT_PORT_MASK       0x20000000
4038 #define DRV_MB_PARAM_PHY_PORT_SHIFT             30
4039 #define DRV_MB_PARAM_PHY_PORT_MASK              0xc0000000
4040
4041 /* configure vf MSIX params*/
4042 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT    0
4043 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK     0x000000FF
4044 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT   8
4045 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK    0x0000FF00
4046
4047         u32 fw_mb_header;
4048 #define FW_MSG_CODE_MASK                        0xffff0000
4049 #define FW_MSG_CODE_DRV_LOAD_ENGINE             0x10100000
4050 #define FW_MSG_CODE_DRV_LOAD_PORT               0x10110000
4051 #define FW_MSG_CODE_DRV_LOAD_FUNCTION           0x10120000
4052 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA        0x10200000
4053 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI        0x10210000
4054 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG       0x10220000
4055 #define FW_MSG_CODE_DRV_LOAD_DONE               0x11100000
4056 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE           0x20110000
4057 #define FW_MSG_CODE_DRV_UNLOAD_PORT             0x20120000
4058 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION         0x20130000
4059 #define FW_MSG_CODE_DRV_UNLOAD_DONE             0x21100000
4060 #define FW_MSG_CODE_INIT_PHY_DONE               0x21200000
4061 #define FW_MSG_CODE_INIT_PHY_ERR_INVALID_ARGS   0x21300000
4062 #define FW_MSG_CODE_LINK_RESET_DONE             0x23000000
4063 #define FW_MSG_CODE_SET_LLDP_DONE               0x24000000
4064 #define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT  0x24010000
4065 #define FW_MSG_CODE_SET_DCBX_DONE               0x25000000
4066 #define FW_MSG_CODE_NIG_DRAIN_DONE              0x30000000
4067 #define FW_MSG_CODE_VF_DISABLED_DONE            0xb0000000
4068 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE        0xb0010000
4069 #define FW_MSG_CODE_FLR_ACK                     0x02000000
4070 #define FW_MSG_CODE_FLR_NACK                    0x02100000
4071
4072 #define FW_MSG_CODE_NVM_OK                      0x00010000
4073 #define FW_MSG_CODE_NVM_INVALID_MODE            0x00020000
4074 #define FW_MSG_CODE_NVM_PREV_CMD_WAS_NOT_FINISHED       0x00030000
4075 #define FW_MSG_CODE_NVM_FAILED_TO_ALLOCATE_PAGE 0x00040000
4076 #define FW_MSG_CODE_NVM_INVALID_DIR_FOUND       0x00050000
4077 #define FW_MSG_CODE_NVM_PAGE_NOT_FOUND          0x00060000
4078 #define FW_MSG_CODE_NVM_FAILED_PARSING_BNDLE_HEADER 0x00070000
4079 #define FW_MSG_CODE_NVM_FAILED_PARSING_IMAGE_HEADER 0x00080000
4080 #define FW_MSG_CODE_NVM_PARSING_OUT_OF_SYNC     0x00090000
4081 #define FW_MSG_CODE_NVM_FAILED_UPDATING_DIR     0x000a0000
4082 #define FW_MSG_CODE_NVM_FAILED_TO_FREE_PAGE     0x000b0000
4083 #define FW_MSG_CODE_NVM_FILE_NOT_FOUND          0x000c0000
4084 #define FW_MSG_CODE_NVM_OPERATION_FAILED        0x000d0000
4085 #define FW_MSG_CODE_NVM_FAILED_UNALIGNED        0x000e0000
4086 #define FW_MSG_CODE_NVM_BAD_OFFSET              0x000f0000
4087 #define FW_MSG_CODE_NVM_BAD_SIGNATURE           0x00100000
4088 #define FW_MSG_CODE_NVM_FILE_READ_ONLY          0x00200000
4089 #define FW_MSG_CODE_NVM_UNKNOWN_FILE            0x00300000
4090 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK      0x00400000
4091 #define FW_MSG_CODE_MCP_RESET_REJECT            0x00600000
4092 #define FW_MSG_CODE_PHY_OK                      0x00110000
4093 #define FW_MSG_CODE_PHY_ERROR                   0x00120000
4094 #define FW_MSG_CODE_SET_SECURE_MODE_ERROR       0x00130000
4095 #define FW_MSG_CODE_SET_SECURE_MODE_OK          0x00140000
4096 #define FW_MSG_MODE_PHY_PRIVILEGE_ERROR         0x00150000
4097
4098 #define FW_MSG_SEQ_NUMBER_MASK                  0x0000ffff
4099
4100         u32     fw_mb_param;
4101
4102         u32     drv_pulse_mb;
4103 #define DRV_PULSE_SEQ_MASK                      0x00007fff
4104 #define DRV_PULSE_SYSTEM_TIME_MASK              0xffff0000
4105 #define DRV_PULSE_ALWAYS_ALIVE                  0x00008000
4106         u32 mcp_pulse_mb;
4107 #define MCP_PULSE_SEQ_MASK                      0x00007fff
4108 #define MCP_PULSE_ALWAYS_ALIVE                  0x00008000
4109 #define MCP_EVENT_MASK                          0xffff0000
4110 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ        0x00010000
4111
4112         union drv_union_data union_data;
4113 };
4114
4115 /* MFW - DRV MB */
4116 /**********************************************************************
4117 * Description
4118 *   Incremental Aggregative
4119 *   8-bit MFW counter per message
4120 *   8-bit ack-counter per message
4121 * Capabilities
4122 *   Provides up to 256 aggregative message per type
4123 *   Provides 4 message types in dword
4124 *   Message type pointers to byte offset
4125 *   Backward Compatibility by using sizeof for the counters.
4126 *   No lock requires for 32bit messages
4127 * Limitations:
4128 * In case of messages greater than 32bit, a dedicated mechanism(e.g lock)
4129 * is required to prevent data corruption.
4130 **********************************************************************/
4131 enum MFW_DRV_MSG_TYPE {
4132         MFW_DRV_MSG_LINK_CHANGE,
4133         MFW_DRV_MSG_FLR_FW_ACK_FAILED,
4134         MFW_DRV_MSG_VF_DISABLED,
4135         MFW_DRV_MSG_LLDP_DATA_UPDATED,
4136         MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
4137         MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
4138         MFW_DRV_MSG_ERROR_RECOVERY,
4139         MFW_DRV_MSG_MAX
4140 };
4141
4142 #define MFW_DRV_MSG_MAX_DWORDS(msgs)    (((msgs - 1) >> 2) + 1)
4143 #define MFW_DRV_MSG_DWORD(msg_id)       (msg_id >> 2)
4144 #define MFW_DRV_MSG_OFFSET(msg_id)      ((msg_id & 0x3) << 3)
4145 #define MFW_DRV_MSG_MASK(msg_id)        (0xff << MFW_DRV_MSG_OFFSET(msg_id))
4146
4147 struct public_mfw_mb {
4148         u32     sup_msgs;
4149         u32     msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
4150         u32     ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
4151 };
4152
4153 /**************************************/
4154 /*                                    */
4155 /*     P U B L I C       D A T A      */
4156 /*                                    */
4157 /**************************************/
4158 enum public_sections {
4159         PUBLIC_DRV_MB,          /* Points to the first drv_mb of path0 */
4160         PUBLIC_MFW_MB,          /* Points to the first mfw_mb of path0 */
4161         PUBLIC_GLOBAL,
4162         PUBLIC_PATH,
4163         PUBLIC_PORT,
4164         PUBLIC_FUNC,
4165         PUBLIC_MAX_SECTIONS
4166 };
4167
4168 struct drv_ver_info_stc {
4169         u32     ver;
4170         u8      name[32];
4171 };
4172
4173 struct mcp_public_data {
4174         /* The sections fields is an array */
4175         u32                     num_sections;
4176         offsize_t               sections[PUBLIC_MAX_SECTIONS];
4177         struct public_drv_mb    drv_mb[MCP_GLOB_FUNC_MAX];
4178         struct public_mfw_mb    mfw_mb[MCP_GLOB_FUNC_MAX];
4179         struct public_global    global;
4180         struct public_path      path[MCP_GLOB_PATH_MAX];
4181         struct public_port      port[MCP_GLOB_PORT_MAX];
4182         struct public_func      func[MCP_GLOB_FUNC_MAX];
4183         struct drv_ver_info_stc drv_info;
4184 };
4185
4186 struct nvm_cfg_mac_address {
4187         u32     mac_addr_hi;
4188 #define NVM_CFG_MAC_ADDRESS_HI_MASK                             0x0000FFFF
4189 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET                           0
4190
4191         u32     mac_addr_lo;
4192 };
4193
4194 /******************************************
4195 * nvm_cfg1 structs
4196 ******************************************/
4197
4198 struct nvm_cfg1_glob {
4199         u32 generic_cont0;                                      /* 0x0 */
4200 #define NVM_CFG1_GLOB_BOARD_SWAP_MASK                           0x0000000F
4201 #define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET                         0
4202 #define NVM_CFG1_GLOB_BOARD_SWAP_NONE                           0x0
4203 #define NVM_CFG1_GLOB_BOARD_SWAP_PATH                           0x1
4204 #define NVM_CFG1_GLOB_BOARD_SWAP_PORT                           0x2
4205 #define NVM_CFG1_GLOB_BOARD_SWAP_BOTH                           0x3
4206 #define NVM_CFG1_GLOB_MF_MODE_MASK                              0x00000FF0
4207 #define NVM_CFG1_GLOB_MF_MODE_OFFSET                            4
4208 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED                        0x0
4209 #define NVM_CFG1_GLOB_MF_MODE_FORCED_SF                         0x1
4210 #define NVM_CFG1_GLOB_MF_MODE_SPIO4                             0x2
4211 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0                           0x3
4212 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5                           0x4
4213 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0                           0x5
4214 #define NVM_CFG1_GLOB_MF_MODE_BD                                0x6
4215 #define NVM_CFG1_GLOB_MF_MODE_UFP                               0x7
4216 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK              0x00001000
4217 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET            12
4218 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED          0x0
4219 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED           0x1
4220 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK                       0x001FE000
4221 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET                     13
4222 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK                      0x1FE00000
4223 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET                    21
4224 #define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK                         0x20000000
4225 #define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET                       29
4226 #define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED                     0x0
4227 #define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED                      0x1
4228 #define NVM_CFG1_GLOB_ENABLE_ATC_MASK                           0x40000000
4229 #define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET                         30
4230 #define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED                       0x0
4231 #define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED                        0x1
4232 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_MASK                       0x80000000
4233 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_OFFSET                     31
4234 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_DISABLED                   0x0
4235 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_ENABLED                    0x1
4236
4237         u32     engineering_change[3];                          /* 0x4 */
4238
4239         u32     manufacturing_id;                               /* 0x10 */
4240
4241         u32     serial_number[4];                               /* 0x14 */
4242
4243         u32     pcie_cfg;                                       /* 0x24 */
4244 #define NVM_CFG1_GLOB_PCI_GEN_MASK                              0x00000003
4245 #define NVM_CFG1_GLOB_PCI_GEN_OFFSET                            0
4246 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1                          0x0
4247 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2                          0x1
4248 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3                          0x2
4249 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK                   0x00000004
4250 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET                 2
4251 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED               0x0
4252 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED                0x1
4253 #define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK                         0x00000018
4254 #define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET                       3
4255 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED               0x0
4256 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_DISABLED                 0x1
4257 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED                  0x2
4258 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_DISABLED              0x3
4259 #define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_MASK               0x00000020
4260 #define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_OFFSET             5
4261 #define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_DISABLED           0x0
4262 #define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_ENABLED            0x1
4263 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK                 0x000003C0
4264 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET               6
4265 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK                     0x00001C00
4266 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET                   10
4267 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW                       0x0
4268 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB                      0x1
4269 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB                    0x2
4270 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB                    0x3
4271 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK                     0x001FE000
4272 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET                   13
4273 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK                     0x1FE00000
4274 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET                   21
4275 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK                      0x60000000
4276 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET                    29
4277
4278         u32 mgmt_traffic;                                       /* 0x28 */
4279 #define NVM_CFG1_GLOB_RESERVED60_MASK                           0x00000001
4280 #define NVM_CFG1_GLOB_RESERVED60_OFFSET                         0
4281 #define NVM_CFG1_GLOB_RESERVED60_100KHZ                         0x0
4282 #define NVM_CFG1_GLOB_RESERVED60_400KHZ                         0x1
4283 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK                     0x000001FE
4284 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET                   1
4285 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK                     0x0001FE00
4286 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET                   9
4287 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK                        0x01FE0000
4288 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET                      17
4289 #define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK                        0x06000000
4290 #define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET                      25
4291 #define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED                    0x0
4292 #define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII                        0x1
4293 #define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII                       0x2
4294
4295         u32 core_cfg;                                           /* 0x2C */
4296 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK                    0x000000FF
4297 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET                  0
4298 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G                0x0
4299 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G                0x1
4300 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G               0x2
4301 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_F              0x3
4302 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_E              0x4
4303 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X20G                0x5
4304 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X40G                0xB
4305 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X25G                0xC
4306 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X25G                0xD
4307 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_MASK             0x00000100
4308 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_OFFSET           8
4309 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_DISABLED         0x0
4310 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_ENABLED          0x1
4311 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_MASK            0x00000200
4312 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_OFFSET          9
4313 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_DISABLED        0x0
4314 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_ENABLED         0x1
4315 #define NVM_CFG1_GLOB_EAGLE_CORE_ADDR_MASK                      0x0003FC00
4316 #define NVM_CFG1_GLOB_EAGLE_CORE_ADDR_OFFSET                    10
4317 #define NVM_CFG1_GLOB_FALCON_CORE_ADDR_MASK                     0x03FC0000
4318 #define NVM_CFG1_GLOB_FALCON_CORE_ADDR_OFFSET                   18
4319 #define NVM_CFG1_GLOB_AVS_MODE_MASK                             0x1C000000
4320 #define NVM_CFG1_GLOB_AVS_MODE_OFFSET                           26
4321 #define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP                       0x0
4322 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP                        0x1
4323 #define NVM_CFG1_GLOB_AVS_MODE_DISABLED                         0x3
4324 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK                 0x60000000
4325 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET               29
4326 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED             0x0
4327 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED              0x1
4328
4329         u32 e_lane_cfg1;                                        /* 0x30 */
4330 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK                        0x0000000F
4331 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET                      0
4332 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK                        0x000000F0
4333 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET                      4
4334 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK                        0x00000F00
4335 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET                      8
4336 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK                        0x0000F000
4337 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET                      12
4338 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK                        0x000F0000
4339 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET                      16
4340 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK                        0x00F00000
4341 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET                      20
4342 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK                        0x0F000000
4343 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET                      24
4344 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK                        0xF0000000
4345 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET                      28
4346
4347         u32 e_lane_cfg2;                                        /* 0x34 */
4348 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK                    0x00000001
4349 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET                  0
4350 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK                    0x00000002
4351 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET                  1
4352 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK                    0x00000004
4353 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET                  2
4354 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK                    0x00000008
4355 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET                  3
4356 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK                    0x00000010
4357 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET                  4
4358 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK                    0x00000020
4359 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET                  5
4360 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK                    0x00000040
4361 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET                  6
4362 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK                    0x00000080
4363 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET                  7
4364 #define NVM_CFG1_GLOB_SMBUS_MODE_MASK                           0x00000F00
4365 #define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET                         8
4366 #define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED                       0x0
4367 #define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ                         0x1
4368 #define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ                         0x2
4369 #define NVM_CFG1_GLOB_NCSI_MASK                                 0x0000F000
4370 #define NVM_CFG1_GLOB_NCSI_OFFSET                               12
4371 #define NVM_CFG1_GLOB_NCSI_DISABLED                             0x0
4372 #define NVM_CFG1_GLOB_NCSI_ENABLED                              0x1
4373
4374         u32 f_lane_cfg1;                                        /* 0x38 */
4375 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK                        0x0000000F
4376 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET                      0
4377 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK                        0x000000F0
4378 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET                      4
4379 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK                        0x00000F00
4380 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET                      8
4381 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK                        0x0000F000
4382 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET                      12
4383 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK                        0x000F0000
4384 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET                      16
4385 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK                        0x00F00000
4386 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET                      20
4387 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK                        0x0F000000
4388 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET                      24
4389 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK                        0xF0000000
4390 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET                      28
4391
4392         u32 f_lane_cfg2;                                        /* 0x3C */
4393 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK                    0x00000001
4394 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET                  0
4395 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK                    0x00000002
4396 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET                  1
4397 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK                    0x00000004
4398 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET                  2
4399 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK                    0x00000008
4400 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET                  3
4401 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK                    0x00000010
4402 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET                  4
4403 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK                    0x00000020
4404 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET                  5
4405 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK                    0x00000040
4406 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET                  6
4407 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK                    0x00000080
4408 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET                  7
4409
4410         u32 eagle_preemphasis;                                  /* 0x40 */
4411 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK                         0x000000FF
4412 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET                       0
4413 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK                         0x0000FF00
4414 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET                       8
4415 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK                         0x00FF0000
4416 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET                       16
4417 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK                         0xFF000000
4418 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET                       24
4419
4420         u32 eagle_driver_current;                               /* 0x44 */
4421 #define NVM_CFG1_GLOB_LANE0_AMP_MASK                            0x000000FF
4422 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET                          0
4423 #define NVM_CFG1_GLOB_LANE1_AMP_MASK                            0x0000FF00
4424 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET                          8
4425 #define NVM_CFG1_GLOB_LANE2_AMP_MASK                            0x00FF0000
4426 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET                          16
4427 #define NVM_CFG1_GLOB_LANE3_AMP_MASK                            0xFF000000
4428 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET                          24
4429
4430         u32 falcon_preemphasis;                                 /* 0x48 */
4431 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK                         0x000000FF
4432 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET                       0
4433 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK                         0x0000FF00
4434 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET                       8
4435 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK                         0x00FF0000
4436 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET                       16
4437 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK                         0xFF000000
4438 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET                       24
4439
4440         u32 falcon_driver_current;                              /* 0x4C */
4441 #define NVM_CFG1_GLOB_LANE0_AMP_MASK                            0x000000FF
4442 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET                          0
4443 #define NVM_CFG1_GLOB_LANE1_AMP_MASK                            0x0000FF00
4444 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET                          8
4445 #define NVM_CFG1_GLOB_LANE2_AMP_MASK                            0x00FF0000
4446 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET                          16
4447 #define NVM_CFG1_GLOB_LANE3_AMP_MASK                            0xFF000000
4448 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET                          24
4449
4450         u32     pci_id;                                         /* 0x50 */
4451 #define NVM_CFG1_GLOB_VENDOR_ID_MASK                            0x0000FFFF
4452 #define NVM_CFG1_GLOB_VENDOR_ID_OFFSET                          0
4453
4454         u32     pci_subsys_id;                                  /* 0x54 */
4455 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK                  0x0000FFFF
4456 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET                0
4457 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK                  0xFFFF0000
4458 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET                16
4459
4460         u32     bar;                                            /* 0x58 */
4461 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK                   0x0000000F
4462 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET                 0
4463 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED               0x0
4464 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K                     0x1
4465 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K                     0x2
4466 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K                     0x3
4467 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K                    0x4
4468 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K                    0x5
4469 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K                    0x6
4470 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K                   0x7
4471 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K                   0x8
4472 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K                   0x9
4473 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M                     0xA
4474 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M                     0xB
4475 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M                     0xC
4476 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M                     0xD
4477 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M                    0xE
4478 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M                    0xF
4479 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK                     0x000000F0
4480 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET                   4
4481 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED                 0x0
4482 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K                       0x1
4483 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K                       0x2
4484 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K                      0x3
4485 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K                      0x4
4486 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K                      0x5
4487 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K                     0x6
4488 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K                     0x7
4489 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K                     0x8
4490 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M                       0x9
4491 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M                       0xA
4492 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M                       0xB
4493 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M                       0xC
4494 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M                      0xD
4495 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M                      0xE
4496 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M                      0xF
4497 #define NVM_CFG1_GLOB_BAR2_SIZE_MASK                            0x00000F00
4498 #define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET                          8
4499 #define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED                        0x0
4500 #define NVM_CFG1_GLOB_BAR2_SIZE_64K                             0x1
4501 #define NVM_CFG1_GLOB_BAR2_SIZE_128K                            0x2
4502 #define NVM_CFG1_GLOB_BAR2_SIZE_256K                            0x3
4503 #define NVM_CFG1_GLOB_BAR2_SIZE_512K                            0x4
4504 #define NVM_CFG1_GLOB_BAR2_SIZE_1M                              0x5
4505 #define NVM_CFG1_GLOB_BAR2_SIZE_2M                              0x6
4506 #define NVM_CFG1_GLOB_BAR2_SIZE_4M                              0x7
4507 #define NVM_CFG1_GLOB_BAR2_SIZE_8M                              0x8
4508 #define NVM_CFG1_GLOB_BAR2_SIZE_16M                             0x9
4509 #define NVM_CFG1_GLOB_BAR2_SIZE_32M                             0xA
4510 #define NVM_CFG1_GLOB_BAR2_SIZE_64M                             0xB
4511 #define NVM_CFG1_GLOB_BAR2_SIZE_128M                            0xC
4512 #define NVM_CFG1_GLOB_BAR2_SIZE_256M                            0xD
4513 #define NVM_CFG1_GLOB_BAR2_SIZE_512M                            0xE
4514 #define NVM_CFG1_GLOB_BAR2_SIZE_1G                              0xF
4515
4516         u32 eagle_txfir_main;                                   /* 0x5C */
4517 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK                     0x000000FF
4518 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET                   0
4519 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK                     0x0000FF00
4520 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET                   8
4521 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK                     0x00FF0000
4522 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET                   16
4523 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK                     0xFF000000
4524 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET                   24
4525
4526         u32 eagle_txfir_post;                                   /* 0x60 */
4527 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK                     0x000000FF
4528 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET                   0
4529 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK                     0x0000FF00
4530 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET                   8
4531 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK                     0x00FF0000
4532 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET                   16
4533 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK                     0xFF000000
4534 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET                   24
4535
4536         u32 falcon_txfir_main;                                  /* 0x64 */
4537 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK                     0x000000FF
4538 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET                   0
4539 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK                     0x0000FF00
4540 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET                   8
4541 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK                     0x00FF0000
4542 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET                   16
4543 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK                     0xFF000000
4544 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET                   24
4545
4546         u32 falcon_txfir_post;                                  /* 0x68 */
4547 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK                     0x000000FF
4548 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET                   0
4549 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK                     0x0000FF00
4550 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET                   8
4551 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK                     0x00FF0000
4552 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET                   16
4553 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK                     0xFF000000
4554 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET                   24
4555
4556         u32 manufacture_ver;                                    /* 0x6C */
4557 #define NVM_CFG1_GLOB_MANUF0_VER_MASK                           0x0000003F
4558 #define NVM_CFG1_GLOB_MANUF0_VER_OFFSET                         0
4559 #define NVM_CFG1_GLOB_MANUF1_VER_MASK                           0x00000FC0
4560 #define NVM_CFG1_GLOB_MANUF1_VER_OFFSET                         6
4561 #define NVM_CFG1_GLOB_MANUF2_VER_MASK                           0x0003F000
4562 #define NVM_CFG1_GLOB_MANUF2_VER_OFFSET                         12
4563 #define NVM_CFG1_GLOB_MANUF3_VER_MASK                           0x00FC0000
4564 #define NVM_CFG1_GLOB_MANUF3_VER_OFFSET                         18
4565 #define NVM_CFG1_GLOB_MANUF4_VER_MASK                           0x3F000000
4566 #define NVM_CFG1_GLOB_MANUF4_VER_OFFSET                         24
4567
4568         u32 manufacture_time;                                   /* 0x70 */
4569 #define NVM_CFG1_GLOB_MANUF0_TIME_MASK                          0x0000003F
4570 #define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET                        0
4571 #define NVM_CFG1_GLOB_MANUF1_TIME_MASK                          0x00000FC0
4572 #define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET                        6
4573 #define NVM_CFG1_GLOB_MANUF2_TIME_MASK                          0x0003F000
4574 #define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET                        12
4575
4576         u32 led_global_settings;                                /* 0x74 */
4577 #define NVM_CFG1_GLOB_LED_SWAP_0_MASK                           0x0000000F
4578 #define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET                         0
4579 #define NVM_CFG1_GLOB_LED_SWAP_1_MASK                           0x000000F0
4580 #define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET                         4
4581 #define NVM_CFG1_GLOB_LED_SWAP_2_MASK                           0x00000F00
4582 #define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET                         8
4583 #define NVM_CFG1_GLOB_LED_SWAP_3_MASK                           0x0000F000
4584 #define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET                         12
4585
4586         u32     generic_cont1;                                  /* 0x78 */
4587 #define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK                         0x000003FF
4588 #define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET                       0
4589
4590         u32     mbi_version;                                    /* 0x7C */
4591 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK                        0x000000FF
4592 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET                      0
4593 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK                        0x0000FF00
4594 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET                      8
4595 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK                        0x00FF0000
4596 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET                      16
4597
4598         u32     mbi_date;                                       /* 0x80 */
4599
4600         u32     misc_sig;                                       /* 0x84 */
4601
4602         /*  Define the GPIO mapping to switch i2c mux */
4603 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK                   0x000000FF
4604 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET                 0
4605 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK                   0x0000FF00
4606 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET                 8
4607 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA                      0x0
4608 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0                   0x1
4609 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1                   0x2
4610 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2                   0x3
4611 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3                   0x4
4612 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4                   0x5
4613 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5                   0x6
4614 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6                   0x7
4615 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7                   0x8
4616 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8                   0x9
4617 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9                   0xA
4618 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10                  0xB
4619 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11                  0xC
4620 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12                  0xD
4621 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13                  0xE
4622 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14                  0xF
4623 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15                  0x10
4624 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16                  0x11
4625 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17                  0x12
4626 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18                  0x13
4627 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19                  0x14
4628 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20                  0x15
4629 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21                  0x16
4630 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22                  0x17
4631 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23                  0x18
4632 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24                  0x19
4633 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25                  0x1A
4634 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26                  0x1B
4635 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27                  0x1C
4636 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28                  0x1D
4637 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29                  0x1E
4638 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30                  0x1F
4639 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31                  0x20
4640
4641         u32 reserved[46];                                       /* 0x88 */
4642 };
4643
4644 struct nvm_cfg1_path {
4645         u32 reserved[30];                                       /* 0x0 */
4646 };
4647
4648 struct nvm_cfg1_port {
4649         u32 power_dissipated;                                   /* 0x0 */
4650 #define NVM_CFG1_PORT_POWER_DIS_D0_MASK                         0x000000FF
4651 #define NVM_CFG1_PORT_POWER_DIS_D0_OFFSET                       0
4652 #define NVM_CFG1_PORT_POWER_DIS_D1_MASK                         0x0000FF00
4653 #define NVM_CFG1_PORT_POWER_DIS_D1_OFFSET                       8
4654 #define NVM_CFG1_PORT_POWER_DIS_D2_MASK                         0x00FF0000
4655 #define NVM_CFG1_PORT_POWER_DIS_D2_OFFSET                       16
4656 #define NVM_CFG1_PORT_POWER_DIS_D3_MASK                         0xFF000000
4657 #define NVM_CFG1_PORT_POWER_DIS_D3_OFFSET                       24
4658
4659         u32 power_consumed;                                     /* 0x4 */
4660 #define NVM_CFG1_PORT_POWER_CONS_D0_MASK                        0x000000FF
4661 #define NVM_CFG1_PORT_POWER_CONS_D0_OFFSET                      0
4662 #define NVM_CFG1_PORT_POWER_CONS_D1_MASK                        0x0000FF00
4663 #define NVM_CFG1_PORT_POWER_CONS_D1_OFFSET                      8
4664 #define NVM_CFG1_PORT_POWER_CONS_D2_MASK                        0x00FF0000
4665 #define NVM_CFG1_PORT_POWER_CONS_D2_OFFSET                      16
4666 #define NVM_CFG1_PORT_POWER_CONS_D3_MASK                        0xFF000000
4667 #define NVM_CFG1_PORT_POWER_CONS_D3_OFFSET                      24
4668
4669         u32 generic_cont0;                                      /* 0x8 */
4670 #define NVM_CFG1_PORT_LED_MODE_MASK                             0x000000FF
4671 #define NVM_CFG1_PORT_LED_MODE_OFFSET                           0
4672 #define NVM_CFG1_PORT_LED_MODE_MAC1                             0x0
4673 #define NVM_CFG1_PORT_LED_MODE_PHY1                             0x1
4674 #define NVM_CFG1_PORT_LED_MODE_PHY2                             0x2
4675 #define NVM_CFG1_PORT_LED_MODE_PHY3                             0x3
4676 #define NVM_CFG1_PORT_LED_MODE_MAC2                             0x4
4677 #define NVM_CFG1_PORT_LED_MODE_PHY4                             0x5
4678 #define NVM_CFG1_PORT_LED_MODE_PHY5                             0x6
4679 #define NVM_CFG1_PORT_LED_MODE_PHY6                             0x7
4680 #define NVM_CFG1_PORT_LED_MODE_MAC3                             0x8
4681 #define NVM_CFG1_PORT_LED_MODE_PHY7                             0x9
4682 #define NVM_CFG1_PORT_LED_MODE_PHY8                             0xA
4683 #define NVM_CFG1_PORT_LED_MODE_PHY9                             0xB
4684 #define NVM_CFG1_PORT_LED_MODE_MAC4                             0xC
4685 #define NVM_CFG1_PORT_LED_MODE_PHY10                            0xD
4686 #define NVM_CFG1_PORT_LED_MODE_PHY11                            0xE
4687 #define NVM_CFG1_PORT_LED_MODE_PHY12                            0xF
4688 #define NVM_CFG1_PORT_ROCE_PRIORITY_MASK                        0x0000FF00
4689 #define NVM_CFG1_PORT_ROCE_PRIORITY_OFFSET                      8
4690 #define NVM_CFG1_PORT_DCBX_MODE_MASK                            0x000F0000
4691 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET                          16
4692 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED                        0x0
4693 #define NVM_CFG1_PORT_DCBX_MODE_IEEE                            0x1
4694 #define NVM_CFG1_PORT_DCBX_MODE_CEE                             0x2
4695 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC                         0x3
4696
4697         u32     pcie_cfg;                                       /* 0xC */
4698 #define NVM_CFG1_PORT_RESERVED15_MASK                           0x00000007
4699 #define NVM_CFG1_PORT_RESERVED15_OFFSET                         0
4700
4701         u32     features;                                       /* 0x10 */
4702 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK           0x00000001
4703 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET         0
4704 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED       0x0
4705 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED        0x1
4706 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK                     0x00000002
4707 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET                   1
4708 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED                 0x0
4709 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED                  0x1
4710
4711         u32 speed_cap_mask;                                     /* 0x14 */
4712 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK            0x0000FFFF
4713 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET          0
4714 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G              0x1
4715 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G             0x2
4716 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G             0x8
4717 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G             0x10
4718 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G             0x20
4719 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G            0x40
4720 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK            0xFFFF0000
4721 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET          16
4722 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G              0x1
4723 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G             0x2
4724 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G             0x8
4725 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G             0x10
4726 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G             0x20
4727 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_100G            0x40
4728
4729         u32 link_settings;                                      /* 0x18 */
4730 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK                       0x0000000F
4731 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET                     0
4732 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG                    0x0
4733 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G                         0x1
4734 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G                        0x2
4735 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G                        0x4
4736 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G                        0x5
4737 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G                        0x6
4738 #define NVM_CFG1_PORT_DRV_LINK_SPEED_100G                       0x7
4739 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK                     0x00000070
4740 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET                   4
4741 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG                  0x1
4742 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX                       0x2
4743 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX                       0x4
4744 #define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK                       0x00000780
4745 #define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET                     7
4746 #define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG                    0x0
4747 #define NVM_CFG1_PORT_MFW_LINK_SPEED_1G                         0x1
4748 #define NVM_CFG1_PORT_MFW_LINK_SPEED_10G                        0x2
4749 #define NVM_CFG1_PORT_MFW_LINK_SPEED_25G                        0x4
4750 #define NVM_CFG1_PORT_MFW_LINK_SPEED_40G                        0x5
4751 #define NVM_CFG1_PORT_MFW_LINK_SPEED_50G                        0x6
4752 #define NVM_CFG1_PORT_MFW_LINK_SPEED_100G                       0x7
4753 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK                     0x00003800
4754 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET                   11
4755 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG                  0x1
4756 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX                       0x2
4757 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX                       0x4
4758 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK      0x00004000
4759 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET    14
4760 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED  0x0
4761 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED   0x1
4762
4763         u32 phy_cfg;                                            /* 0x1C */
4764 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK                  0x0000FFFF
4765 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET                0
4766 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG                 0x1
4767 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER             0x2
4768 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER                 0x4
4769 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN       0x8
4770 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN        0x10
4771 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK                 0x00FF0000
4772 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET               16
4773 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS               0x0
4774 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR                   0x2
4775 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2                  0x3
4776 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4                  0x4
4777 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI                  0x8
4778 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI                  0x9
4779 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X                0xB
4780 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII                0xC
4781 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI                0xD
4782 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI                 0xE
4783 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI                0xF
4784 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI                 0x10
4785 #define NVM_CFG1_PORT_AN_MODE_MASK                              0xFF000000
4786 #define NVM_CFG1_PORT_AN_MODE_OFFSET                            24
4787 #define NVM_CFG1_PORT_AN_MODE_NONE                              0x0
4788 #define NVM_CFG1_PORT_AN_MODE_CL73                              0x1
4789 #define NVM_CFG1_PORT_AN_MODE_CL37                              0x2
4790 #define NVM_CFG1_PORT_AN_MODE_CL73_BAM                          0x3
4791 #define NVM_CFG1_PORT_AN_MODE_CL37_BAM                          0x4
4792 #define NVM_CFG1_PORT_AN_MODE_HPAM                              0x5
4793 #define NVM_CFG1_PORT_AN_MODE_SGMII                             0x6
4794
4795         u32 mgmt_traffic;                                       /* 0x20 */
4796 #define NVM_CFG1_PORT_RESERVED61_MASK                           0x0000000F
4797 #define NVM_CFG1_PORT_RESERVED61_OFFSET                         0
4798 #define NVM_CFG1_PORT_RESERVED61_DISABLED                       0x0
4799 #define NVM_CFG1_PORT_RESERVED61_NCSI_OVER_RMII                 0x1
4800 #define NVM_CFG1_PORT_RESERVED61_NCSI_OVER_SMBUS                0x2
4801
4802         u32 ext_phy;                                            /* 0x24 */
4803 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK                    0x000000FF
4804 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET                  0
4805 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE                    0x0
4806 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM84844                0x1
4807 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK                 0x0000FF00
4808 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET               8
4809
4810         u32 mba_cfg1;                                           /* 0x28 */
4811 #define NVM_CFG1_PORT_MBA_MASK                                  0x00000001
4812 #define NVM_CFG1_PORT_MBA_OFFSET                                0
4813 #define NVM_CFG1_PORT_MBA_DISABLED                              0x0
4814 #define NVM_CFG1_PORT_MBA_ENABLED                               0x1
4815 #define NVM_CFG1_PORT_MBA_BOOT_TYPE_MASK                        0x00000006
4816 #define NVM_CFG1_PORT_MBA_BOOT_TYPE_OFFSET                      1
4817 #define NVM_CFG1_PORT_MBA_BOOT_TYPE_AUTO                        0x0
4818 #define NVM_CFG1_PORT_MBA_BOOT_TYPE_BBS                         0x1
4819 #define NVM_CFG1_PORT_MBA_BOOT_TYPE_INT18H                      0x2
4820 #define NVM_CFG1_PORT_MBA_BOOT_TYPE_INT19H                      0x3
4821 #define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK                       0x00000078
4822 #define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET                     3
4823 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK                    0x00000080
4824 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET                  7
4825 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S                  0x0
4826 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B                  0x1
4827 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK                0x00000100
4828 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET              8
4829 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED            0x0
4830 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED             0x1
4831 #define NVM_CFG1_PORT_RESERVED5_MASK                            0x0001FE00
4832 #define NVM_CFG1_PORT_RESERVED5_OFFSET                          9
4833 #define NVM_CFG1_PORT_RESERVED5_DISABLED                        0x0
4834 #define NVM_CFG1_PORT_RESERVED5_2K                              0x1
4835 #define NVM_CFG1_PORT_RESERVED5_4K                              0x2
4836 #define NVM_CFG1_PORT_RESERVED5_8K                              0x3
4837 #define NVM_CFG1_PORT_RESERVED5_16K                             0x4
4838 #define NVM_CFG1_PORT_RESERVED5_32K                             0x5
4839 #define NVM_CFG1_PORT_RESERVED5_64K                             0x6
4840 #define NVM_CFG1_PORT_RESERVED5_128K                            0x7
4841 #define NVM_CFG1_PORT_RESERVED5_256K                            0x8
4842 #define NVM_CFG1_PORT_RESERVED5_512K                            0x9
4843 #define NVM_CFG1_PORT_RESERVED5_1M                              0xA
4844 #define NVM_CFG1_PORT_RESERVED5_2M                              0xB
4845 #define NVM_CFG1_PORT_RESERVED5_4M                              0xC
4846 #define NVM_CFG1_PORT_RESERVED5_8M                              0xD
4847 #define NVM_CFG1_PORT_RESERVED5_16M                             0xE
4848 #define NVM_CFG1_PORT_RESERVED5_32M                             0xF
4849 #define NVM_CFG1_PORT_MBA_LINK_SPEED_MASK                       0x001E0000
4850 #define NVM_CFG1_PORT_MBA_LINK_SPEED_OFFSET                     17
4851 #define NVM_CFG1_PORT_MBA_LINK_SPEED_AUTONEG                    0x0
4852 #define NVM_CFG1_PORT_MBA_LINK_SPEED_1G                         0x1
4853 #define NVM_CFG1_PORT_MBA_LINK_SPEED_10G                        0x2
4854 #define NVM_CFG1_PORT_MBA_LINK_SPEED_25G                        0x4
4855 #define NVM_CFG1_PORT_MBA_LINK_SPEED_40G                        0x5
4856 #define NVM_CFG1_PORT_MBA_LINK_SPEED_50G                        0x6
4857 #define NVM_CFG1_PORT_MBA_LINK_SPEED_100G                       0x7
4858 #define NVM_CFG1_PORT_MBA_BOOT_RETRY_COUNT_MASK                 0x00E00000
4859 #define NVM_CFG1_PORT_MBA_BOOT_RETRY_COUNT_OFFSET               21
4860
4861         u32     mba_cfg2;                                       /* 0x2C */
4862 #define NVM_CFG1_PORT_MBA_VLAN_VALUE_MASK                       0x0000FFFF
4863 #define NVM_CFG1_PORT_MBA_VLAN_VALUE_OFFSET                     0
4864 #define NVM_CFG1_PORT_MBA_VLAN_MASK                             0x00010000
4865 #define NVM_CFG1_PORT_MBA_VLAN_OFFSET                           16
4866
4867         u32     vf_cfg;                                         /* 0x30 */
4868 #define NVM_CFG1_PORT_RESERVED8_MASK                            0x0000FFFF
4869 #define NVM_CFG1_PORT_RESERVED8_OFFSET                          0
4870 #define NVM_CFG1_PORT_RESERVED6_MASK                            0x000F0000
4871 #define NVM_CFG1_PORT_RESERVED6_OFFSET                          16
4872 #define NVM_CFG1_PORT_RESERVED6_DISABLED                        0x0
4873 #define NVM_CFG1_PORT_RESERVED6_4K                              0x1
4874 #define NVM_CFG1_PORT_RESERVED6_8K                              0x2
4875 #define NVM_CFG1_PORT_RESERVED6_16K                             0x3
4876 #define NVM_CFG1_PORT_RESERVED6_32K                             0x4
4877 #define NVM_CFG1_PORT_RESERVED6_64K                             0x5
4878 #define NVM_CFG1_PORT_RESERVED6_128K                            0x6
4879 #define NVM_CFG1_PORT_RESERVED6_256K                            0x7
4880 #define NVM_CFG1_PORT_RESERVED6_512K                            0x8
4881 #define NVM_CFG1_PORT_RESERVED6_1M                              0x9
4882 #define NVM_CFG1_PORT_RESERVED6_2M                              0xA
4883 #define NVM_CFG1_PORT_RESERVED6_4M                              0xB
4884 #define NVM_CFG1_PORT_RESERVED6_8M                              0xC
4885 #define NVM_CFG1_PORT_RESERVED6_16M                             0xD
4886 #define NVM_CFG1_PORT_RESERVED6_32M                             0xE
4887 #define NVM_CFG1_PORT_RESERVED6_64M                             0xF
4888
4889         struct nvm_cfg_mac_address      lldp_mac_address;       /* 0x34 */
4890
4891         u32                             led_port_settings;      /* 0x3C */
4892 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK                   0x000000FF
4893 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET                 0
4894 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK                   0x0000FF00
4895 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET                 8
4896 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK                   0x00FF0000
4897 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET                 16
4898 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G                      0x1
4899 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G                     0x2
4900 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_25G                     0x8
4901 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_40G                     0x10
4902 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_50G                     0x20
4903 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_100G                    0x40
4904
4905         u32 transceiver_00;                                     /* 0x40 */
4906
4907         /*  Define for mapping of transceiver signal module absent */
4908 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK                     0x000000FF
4909 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET                   0
4910 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA                       0x0
4911 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0                    0x1
4912 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1                    0x2
4913 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2                    0x3
4914 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3                    0x4
4915 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4                    0x5
4916 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5                    0x6
4917 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6                    0x7
4918 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7                    0x8
4919 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8                    0x9
4920 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9                    0xA
4921 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10                   0xB
4922 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11                   0xC
4923 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12                   0xD
4924 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13                   0xE
4925 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14                   0xF
4926 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15                   0x10
4927 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16                   0x11
4928 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17                   0x12
4929 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18                   0x13
4930 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19                   0x14
4931 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20                   0x15
4932 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21                   0x16
4933 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22                   0x17
4934 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23                   0x18
4935 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24                   0x19
4936 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25                   0x1A
4937 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26                   0x1B
4938 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27                   0x1C
4939 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28                   0x1D
4940 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29                   0x1E
4941 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30                   0x1F
4942 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31                   0x20
4943         /*  Define the GPIO mux settings  to switch i2c mux to this port */
4944 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK                  0x00000F00
4945 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET                8
4946 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK                  0x0000F000
4947 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET                12
4948
4949         u32 reserved[133];                                      /* 0x44 */
4950 };
4951
4952 struct nvm_cfg1_func {
4953         struct nvm_cfg_mac_address      mac_address;            /* 0x0 */
4954
4955         u32                             rsrv1;                  /* 0x8 */
4956 #define NVM_CFG1_FUNC_RESERVED1_MASK                            0x0000FFFF
4957 #define NVM_CFG1_FUNC_RESERVED1_OFFSET                          0
4958 #define NVM_CFG1_FUNC_RESERVED2_MASK                            0xFFFF0000
4959 #define NVM_CFG1_FUNC_RESERVED2_OFFSET                          16
4960
4961         u32                             rsrv2;                  /* 0xC */
4962 #define NVM_CFG1_FUNC_RESERVED3_MASK                            0x0000FFFF
4963 #define NVM_CFG1_FUNC_RESERVED3_OFFSET                          0
4964 #define NVM_CFG1_FUNC_RESERVED4_MASK                            0xFFFF0000
4965 #define NVM_CFG1_FUNC_RESERVED4_OFFSET                          16
4966
4967         u32                             device_id;              /* 0x10 */
4968 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK                  0x0000FFFF
4969 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET                0
4970 #define NVM_CFG1_FUNC_VENDOR_DEVICE_ID_MASK                     0xFFFF0000
4971 #define NVM_CFG1_FUNC_VENDOR_DEVICE_ID_OFFSET                   16
4972
4973         u32                             cmn_cfg;                /* 0x14 */
4974 #define NVM_CFG1_FUNC_MBA_BOOT_PROTOCOL_MASK                    0x00000007
4975 #define NVM_CFG1_FUNC_MBA_BOOT_PROTOCOL_OFFSET                  0
4976 #define NVM_CFG1_FUNC_MBA_BOOT_PROTOCOL_PXE                     0x0
4977 #define NVM_CFG1_FUNC_MBA_BOOT_PROTOCOL_RPL                     0x1
4978 #define NVM_CFG1_FUNC_MBA_BOOT_PROTOCOL_BOOTP                   0x2
4979 #define NVM_CFG1_FUNC_MBA_BOOT_PROTOCOL_ISCSI_BOOT              0x3
4980 #define NVM_CFG1_FUNC_MBA_BOOT_PROTOCOL_FCOE_BOOT               0x4
4981 #define NVM_CFG1_FUNC_MBA_BOOT_PROTOCOL_NONE                    0x7
4982 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK                     0x0007FFF8
4983 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET                   3
4984 #define NVM_CFG1_FUNC_PERSONALITY_MASK                          0x00780000
4985 #define NVM_CFG1_FUNC_PERSONALITY_OFFSET                        19
4986 #define NVM_CFG1_FUNC_PERSONALITY_ETHERNET                      0x0
4987 #define NVM_CFG1_FUNC_PERSONALITY_ISCSI                         0x1
4988 #define NVM_CFG1_FUNC_PERSONALITY_FCOE                          0x2
4989 #define NVM_CFG1_FUNC_PERSONALITY_ROCE                          0x3
4990 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK                     0x7F800000
4991 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET                   23
4992 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK                   0x80000000
4993 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET                 31
4994 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED               0x0
4995 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED                0x1
4996
4997         u32 pci_cfg;                                            /* 0x18 */
4998 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK                 0x0000007F
4999 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET               0
5000 #define NVM_CFG1_FUNC_RESERVESD12_MASK                          0x00003F80
5001 #define NVM_CFG1_FUNC_RESERVESD12_OFFSET                        7
5002 #define NVM_CFG1_FUNC_BAR1_SIZE_MASK                            0x0003C000
5003 #define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET                          14
5004 #define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED                        0x0
5005 #define NVM_CFG1_FUNC_BAR1_SIZE_64K                             0x1
5006 #define NVM_CFG1_FUNC_BAR1_SIZE_128K                            0x2
5007 #define NVM_CFG1_FUNC_BAR1_SIZE_256K                            0x3
5008 #define NVM_CFG1_FUNC_BAR1_SIZE_512K                            0x4
5009 #define NVM_CFG1_FUNC_BAR1_SIZE_1M                              0x5
5010 #define NVM_CFG1_FUNC_BAR1_SIZE_2M                              0x6
5011 #define NVM_CFG1_FUNC_BAR1_SIZE_4M                              0x7
5012 #define NVM_CFG1_FUNC_BAR1_SIZE_8M                              0x8
5013 #define NVM_CFG1_FUNC_BAR1_SIZE_16M                             0x9
5014 #define NVM_CFG1_FUNC_BAR1_SIZE_32M                             0xA
5015 #define NVM_CFG1_FUNC_BAR1_SIZE_64M                             0xB
5016 #define NVM_CFG1_FUNC_BAR1_SIZE_128M                            0xC
5017 #define NVM_CFG1_FUNC_BAR1_SIZE_256M                            0xD
5018 #define NVM_CFG1_FUNC_BAR1_SIZE_512M                            0xE
5019 #define NVM_CFG1_FUNC_BAR1_SIZE_1G                              0xF
5020 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK                        0x03FC0000
5021 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET                      18
5022
5023         struct nvm_cfg_mac_address      fcoe_node_wwn_mac_addr; /* 0x1C */
5024
5025         struct nvm_cfg_mac_address      fcoe_port_wwn_mac_addr; /* 0x24 */
5026
5027         u32                             reserved[9];            /* 0x2C */
5028 };
5029
5030 struct nvm_cfg1 {
5031         struct nvm_cfg1_glob    glob;                           /* 0x0 */
5032
5033         struct nvm_cfg1_path    path[MCP_GLOB_PATH_MAX];        /* 0x140 */
5034
5035         struct nvm_cfg1_port    port[MCP_GLOB_PORT_MAX];        /* 0x230 */
5036
5037         struct nvm_cfg1_func    func[MCP_GLOB_FUNC_MAX];        /* 0xB90 */
5038 };
5039
5040 /******************************************
5041 * nvm_cfg structs
5042 ******************************************/
5043
5044 enum nvm_cfg_sections {
5045         NVM_CFG_SECTION_NVM_CFG1,
5046         NVM_CFG_SECTION_MAX
5047 };
5048
5049 struct nvm_cfg {
5050         u32             num_sections;
5051         u32             sections_offset[NVM_CFG_SECTION_MAX];
5052         struct nvm_cfg1 cfg1;
5053 };
5054
5055 #define PORT_0          0
5056 #define PORT_1          1
5057 #define PORT_2          2
5058 #define PORT_3          3
5059
5060 extern struct spad_layout g_spad;
5061
5062 #define MCP_SPAD_SIZE                       0x00028000  /* 160 KB */
5063
5064 #define SPAD_OFFSET(addr) (((u32)addr - (u32)CPU_SPAD_BASE))
5065
5066 #define TO_OFFSIZE(_offset, _size)                              \
5067         (u32)((((u32)(_offset) >> 2) << OFFSIZE_OFFSET_SHIFT) | \
5068               (((u32)(_size) >> 2) << OFFSIZE_SIZE_SHIFT))
5069
5070 enum spad_sections {
5071         SPAD_SECTION_TRACE,
5072         SPAD_SECTION_NVM_CFG,
5073         SPAD_SECTION_PUBLIC,
5074         SPAD_SECTION_PRIVATE,
5075         SPAD_SECTION_MAX
5076 };
5077
5078 struct spad_layout {
5079         struct nvm_cfg          nvm_cfg;
5080         struct mcp_public_data  public_data;
5081 };
5082
5083 #define CRC_MAGIC_VALUE                     0xDEBB20E3
5084 #define CRC32_POLYNOMIAL                    0xEDB88320
5085 #define NVM_CRC_SIZE                            (sizeof(u32))
5086
5087 enum nvm_sw_arbitrator {
5088         NVM_SW_ARB_HOST,
5089         NVM_SW_ARB_MCP,
5090         NVM_SW_ARB_UART,
5091         NVM_SW_ARB_RESERVED
5092 };
5093
5094 /****************************************************************************
5095 * Boot Strap Region                                                        *
5096 ****************************************************************************/
5097 struct legacy_bootstrap_region {
5098         u32     magic_value;
5099 #define NVM_MAGIC_VALUE          0x669955aa
5100         u32     sram_start_addr;
5101         u32     code_len;               /* boot code length (in dwords) */
5102         u32     code_start_addr;
5103         u32     crc;                    /* 32-bit CRC */
5104 };
5105
5106 /****************************************************************************
5107 * Directories Region                                                       *
5108 ****************************************************************************/
5109 struct nvm_code_entry {
5110         u32     image_type;             /* Image type */
5111         u32     nvm_start_addr;         /* NVM address of the image */
5112         u32     len;                    /* Include CRC */
5113         u32     sram_start_addr;
5114         u32     sram_run_addr;          /* Relevant in case of MIM only */
5115 };
5116
5117 enum nvm_image_type {
5118         NVM_TYPE_TIM1           = 0x01,
5119         NVM_TYPE_TIM2           = 0x02,
5120         NVM_TYPE_MIM1           = 0x03,
5121         NVM_TYPE_MIM2           = 0x04,
5122         NVM_TYPE_MBA            = 0x05,
5123         NVM_TYPE_MODULES_PN     = 0x06,
5124         NVM_TYPE_VPD            = 0x07,
5125         NVM_TYPE_MFW_TRACE1     = 0x08,
5126         NVM_TYPE_MFW_TRACE2     = 0x09,
5127         NVM_TYPE_NVM_CFG1       = 0x0a,
5128         NVM_TYPE_L2B            = 0x0b,
5129         NVM_TYPE_DIR1           = 0x0c,
5130         NVM_TYPE_EAGLE_FW1      = 0x0d,
5131         NVM_TYPE_FALCON_FW1     = 0x0e,
5132         NVM_TYPE_PCIE_FW1       = 0x0f,
5133         NVM_TYPE_HW_SET         = 0x10,
5134         NVM_TYPE_LIM            = 0x11,
5135         NVM_TYPE_AVS_FW1        = 0x12,
5136         NVM_TYPE_DIR2           = 0x13,
5137         NVM_TYPE_CCM            = 0x14,
5138         NVM_TYPE_EAGLE_FW2      = 0x15,
5139         NVM_TYPE_FALCON_FW2     = 0x16,
5140         NVM_TYPE_PCIE_FW2       = 0x17,
5141         NVM_TYPE_AVS_FW2        = 0x18,
5142
5143         NVM_TYPE_MAX,
5144 };
5145
5146 #define MAX_NVM_DIR_ENTRIES 200
5147
5148 struct nvm_dir {
5149         s32 seq;
5150 #define NVM_DIR_NEXT_MFW_MASK   0x00000001
5151 #define NVM_DIR_SEQ_MASK        0xfffffffe
5152 #define NVM_DIR_NEXT_MFW(seq) ((seq) & NVM_DIR_NEXT_MFW_MASK)
5153
5154 #define IS_DIR_SEQ_VALID(seq) ((seq & NVM_DIR_SEQ_MASK) != NVM_DIR_SEQ_MASK)
5155
5156         u32                     num_images;
5157         u32                     rsrv;
5158         struct nvm_code_entry   code[1]; /* Up to MAX_NVM_DIR_ENTRIES */
5159 };
5160
5161 #define NVM_DIR_SIZE(_num_images) (sizeof(struct nvm_dir) +              \
5162                                    (_num_images -                        \
5163                                     1) * sizeof(struct nvm_code_entry) + \
5164                                    NVM_CRC_SIZE)
5165
5166 struct nvm_vpd_image {
5167         u32     format_revision;
5168 #define VPD_IMAGE_VERSION        1
5169
5170         /* This array length depends on the number of VPD fields */
5171         u8      vpd_data[1];
5172 };
5173
5174 /****************************************************************************
5175 * NVRAM FULL MAP                                                           *
5176 ****************************************************************************/
5177 #define DIR_ID_1    (0)
5178 #define DIR_ID_2    (1)
5179 #define MAX_DIR_IDS (2)
5180
5181 #define MFW_BUNDLE_1    (0)
5182 #define MFW_BUNDLE_2    (1)
5183 #define MAX_MFW_BUNDLES (2)
5184
5185 #define FLASH_PAGE_SIZE 0x1000
5186 #define NVM_DIR_MAX_SIZE    (FLASH_PAGE_SIZE)           /* 4Kb */
5187 #define ASIC_MIM_MAX_SIZE   (300 * FLASH_PAGE_SIZE)     /* 1.2Mb */
5188 #define FPGA_MIM_MAX_SIZE   (25 * FLASH_PAGE_SIZE)      /* 60Kb */
5189
5190 #define LIM_MAX_SIZE        ((2 *                                     \
5191                               FLASH_PAGE_SIZE) -                      \
5192                              sizeof(struct legacy_bootstrap_region) - \
5193                              NVM_RSV_SIZE)
5194 #define LIM_OFFSET          (NVM_OFFSET(lim_image))
5195 #define NVM_RSV_SIZE            (44)
5196 #define MIM_MAX_SIZE(is_asic) ((is_asic) ? ASIC_MIM_MAX_SIZE : \
5197                                FPGA_MIM_MAX_SIZE)
5198 #define MIM_OFFSET(idx, is_asic) (NVM_OFFSET(dir[MAX_MFW_BUNDLES]) + \
5199                                   ((idx ==                           \
5200                                     NVM_TYPE_MIM2) ? MIM_MAX_SIZE(is_asic) : 0))
5201 #define NVM_FIXED_AREA_SIZE(is_asic) (sizeof(struct nvm_image) + \
5202                                       MIM_MAX_SIZE(is_asic) * 2)
5203
5204 union nvm_dir_union {
5205         struct nvm_dir  dir;
5206         u8              page[FLASH_PAGE_SIZE];
5207 };
5208
5209 /*                        Address
5210  *  +-------------------+ 0x000000
5211  *  |    Bootstrap:     |
5212  *  | magic_number      |
5213  *  | sram_start_addr   |
5214  *  | code_len          |
5215  *  | code_start_addr   |
5216  *  | crc               |
5217  *  +-------------------+ 0x000014
5218  *  | rsrv              |
5219  *  +-------------------+ 0x000040
5220  *  | LIM               |
5221  *  +-------------------+ 0x002000
5222  *  | Dir1              |
5223  *  +-------------------+ 0x003000
5224  *  | Dir2              |
5225  *  +-------------------+ 0x004000
5226  *  | MIM1              |
5227  *  +-------------------+ 0x130000
5228  *  | MIM2              |
5229  *  +-------------------+ 0x25C000
5230  *  | Rest Images:      |
5231  *  | TIM1/2            |
5232  *  | MFW_TRACE1/2      |
5233  *  | Eagle/Falcon FW   |
5234  *  | PCIE/AVS FW       |
5235  *  | MBA/CCM/L2B       |
5236  *  | VPD               |
5237  *  | optic_modules     |
5238  *  |  ...              |
5239  *  +-------------------+ 0x400000
5240  */
5241 struct nvm_image {
5242 /*********** !!!  FIXED SECTIONS  !!! DO NOT MODIFY !!! **********************/
5243         /* NVM Offset  (size) */
5244         struct legacy_bootstrap_region  bootstrap;
5245         u8                              rsrv[NVM_RSV_SIZE];
5246         u8                              lim_image[LIM_MAX_SIZE];
5247         union nvm_dir_union             dir[MAX_MFW_BUNDLES];
5248
5249         /* MIM1_IMAGE                              0x004000 (0x12c000) */
5250         /* MIM2_IMAGE                              0x130000 (0x12c000) */
5251 /*********** !!!  FIXED SECTIONS  !!! DO NOT MODIFY !!! **********************/
5252 };                              /* 0x134 */
5253
5254 #define NVM_OFFSET(f)   ((u32_t)((int_ptr_t)(&(((struct nvm_image *)0)->f))))
5255
5256 struct hw_set_info {
5257         u32     reg_type;
5258 #define GRC_REG_TYPE 1
5259 #define PHY_REG_TYPE 2
5260 #define PCI_REG_TYPE 4
5261
5262         u32     bank_num;
5263         u32     pf_num;
5264         u32     operation;
5265 #define READ_OP     1
5266 #define WRITE_OP    2
5267 #define RMW_SET_OP  3
5268 #define RMW_CLR_OP  4
5269
5270         u32     reg_addr;
5271         u32     reg_data;
5272
5273         u32     reset_type;
5274 #define POR_RESET_TYPE  BIT(0)
5275 #define HARD_RESET_TYPE BIT(1)
5276 #define CORE_RESET_TYPE BIT(2)
5277 #define MCP_RESET_TYPE  BIT(3)
5278 #define PERSET_ASSERT   BIT(4)
5279 #define PERSET_DEASSERT BIT(5)
5280 };
5281
5282 struct hw_set_image {
5283         u32                     format_version;
5284 #define HW_SET_IMAGE_VERSION        1
5285         u32                     no_hw_sets;
5286
5287         /* This array length depends on the no_hw_sets */
5288         struct hw_set_info      hw_sets[1];
5289 };
5290
5291 #endif