drivers/net/ethernet/qlogic/qed/qed_int.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #include <linux/types.h>
  10 #include <asm/byteorder.h>
  11 #include <linux/io.h>
  12 #include <linux/bitops.h>
  13 #include <linux/delay.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/errno.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/kernel.h>
  18 #include <linux/pci.h>
  19 #include <linux/slab.h>
  20 #include <linux/string.h>
  21 #include "qed.h"
  22 #include "qed_hsi.h"
  23 #include "qed_hw.h"
  24 #include "qed_init_ops.h"
  25 #include "qed_int.h"
  26 #include "qed_mcp.h"
  27 #include "qed_reg_addr.h"
  28 #include "qed_sp.h"
  29
  30 struct qed_pi_info {
  31         qed_int_comp_cb_t       comp_cb;
  32         void                    *cookie;
  33 };
  34
  35 struct qed_sb_sp_info {
  36         struct qed_sb_info      sb_info;
  37
  38         /* per protocol index data */
  39         struct qed_pi_info      pi_info_arr[PIS_PER_SB];
  40 };
  41
  42 #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \
  43         ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn)
  44
  45 #define ATTN_STATE_BITS (0xfff)
  46 #define ATTN_BITS_MASKABLE      (0x3ff)
  47 struct qed_sb_attn_info {
  48         /* Virtual & Physical address of the SB */
  49         struct atten_status_block       *sb_attn;
  50         dma_addr_t                    sb_phys;
  51
  52         /* Last seen running index */
  53         u16                          index;
  54
  55         /* Previously asserted attentions, which are still unasserted */
  56         u16                          known_attn;
  57
  58         /* Cleanup address for the link's general hw attention */
  59         u32                          mfw_attn_addr;
  60 };
  61
  62 static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn,
  63                                       struct qed_sb_attn_info   *p_sb_desc)
  64 {
  65         u16     rc = 0;
  66         u16     index;
  67
  68         /* Make certain HW write took affect */
  69         mmiowb();
  70
  71         index = le16_to_cpu(p_sb_desc->sb_attn->sb_index);
  72         if (p_sb_desc->index != index) {
  73                 p_sb_desc->index        = index;
  74                 rc                    = QED_SB_ATT_IDX;
  75         }
  76
  77         /* Make certain we got a consistent view with HW */
  78         mmiowb();
  79
  80         return rc;
  81 }
  82
  83 /**
  84  *  @brief qed_int_assertion - handles asserted attention bits
  85  *
  86  *  @param p_hwfn
  87  *  @param asserted_bits newly asserted bits
  88  *  @return int
  89  */
  90 static int qed_int_assertion(struct qed_hwfn *p_hwfn,
  91                              u16 asserted_bits)
  92 {
  93         struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
  94         u32 igu_mask;
  95
  96         /* Mask the source of the attention in the IGU */
  97         igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
  98                           IGU_REG_ATTENTION_ENABLE);
  99         DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n",
 100                    igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE));
 101         igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE);
 102         qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask);
 103
 104         DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
 105                    "inner known ATTN state: 0x%04x --> 0x%04x\n",
 106                    sb_attn_sw->known_attn,
 107                    sb_attn_sw->known_attn | asserted_bits);
 108         sb_attn_sw->known_attn |= asserted_bits;
 109
 110         /* Handle MCP events */
 111         if (asserted_bits & 0x100) {
 112                 qed_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt);
 113                 /* Clean the MCP attention */
 114                 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt,
 115                        sb_attn_sw->mfw_attn_addr, 0);
 116         }
 117
 118         DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview +
 119                       GTT_BAR0_MAP_REG_IGU_CMD +
 120                       ((IGU_CMD_ATTN_BIT_SET_UPPER -
 121                         IGU_CMD_INT_ACK_BASE) << 3),
 122                       (u32)asserted_bits);
 123
 124         DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "set cmd IGU: 0x%04x\n",
 125                    asserted_bits);
 126
 127         return 0;
 128 }
 129
 130 /**
 131  * @brief - handles deassertion of previously asserted attentions.
 132  *
 133  * @param p_hwfn
 134  * @param deasserted_bits - newly deasserted bits
 135  * @return int
 136  *
 137  */
 138 static int qed_int_deassertion(struct qed_hwfn  *p_hwfn,
 139                                u16 deasserted_bits)
 140 {
 141         struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
 142         u32 aeu_mask;
 143
 144         if (deasserted_bits != 0x100)
 145                 DP_ERR(p_hwfn, "Unexpected - non-link deassertion\n");
 146
 147         /* Clear IGU indication for the deasserted bits */
 148         DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview +
 149                       GTT_BAR0_MAP_REG_IGU_CMD +
 150                       ((IGU_CMD_ATTN_BIT_CLR_UPPER -
 151                         IGU_CMD_INT_ACK_BASE) << 3),
 152                       ~((u32)deasserted_bits));
 153
 154         /* Unmask deasserted attentions in IGU */
 155         aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 156                           IGU_REG_ATTENTION_ENABLE);
 157         aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE);
 158         qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask);
 159
 160         /* Clear deassertion from inner state */
 161         sb_attn_sw->known_attn &= ~deasserted_bits;
 162
 163         return 0;
 164 }
 165
 166 static int qed_int_attentions(struct qed_hwfn *p_hwfn)
 167 {
 168         struct qed_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn;
 169         struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn;
 170         u32 attn_bits = 0, attn_acks = 0;
 171         u16 asserted_bits, deasserted_bits;
 172         __le16 index;
 173         int rc = 0;
 174
 175         /* Read current attention bits/acks - safeguard against attentions
 176          * by guaranting work on a synchronized timeframe
 177          */
 178         do {
 179                 index = p_sb_attn->sb_index;
 180                 attn_bits = le32_to_cpu(p_sb_attn->atten_bits);
 181                 attn_acks = le32_to_cpu(p_sb_attn->atten_ack);
 182         } while (index != p_sb_attn->sb_index);
 183         p_sb_attn->sb_index = index;
 184
 185         /* Attention / Deassertion are meaningful (and in correct state)
 186          * only when they differ and consistent with known state - deassertion
 187          * when previous attention & current ack, and assertion when current
 188          * attention with no previous attention
 189          */
 190         asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) &
 191                 ~p_sb_attn_sw->known_attn;
 192         deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) &
 193                 p_sb_attn_sw->known_attn;
 194
 195         if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100)) {
 196                 DP_INFO(p_hwfn,
 197                         "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n",
 198                         index, attn_bits, attn_acks, asserted_bits,
 199                         deasserted_bits, p_sb_attn_sw->known_attn);
 200         } else if (asserted_bits == 0x100) {
 201                 DP_INFO(p_hwfn,
 202                         "MFW indication via attention\n");
 203         } else {
 204                 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
 205                            "MFW indication [deassertion]\n");
 206         }
 207
 208         if (asserted_bits) {
 209                 rc = qed_int_assertion(p_hwfn, asserted_bits);
 210                 if (rc)
 211                         return rc;
 212         }
 213
 214         if (deasserted_bits) {
 215                 rc = qed_int_deassertion(p_hwfn, deasserted_bits);
 216                 if (rc)
 217                         return rc;
 218         }
 219
 220         return rc;
 221 }
 222
 223 static void qed_sb_ack_attn(struct qed_hwfn *p_hwfn,
 224                             void __iomem *igu_addr,
 225                             u32 ack_cons)
 226 {
 227         struct igu_prod_cons_update igu_ack = { 0 };
 228
 229         igu_ack.sb_id_and_flags =
 230                 ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
 231                  (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
 232                  (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
 233                  (IGU_SEG_ACCESS_ATTN <<
 234                   IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
 235
 236         DIRECT_REG_WR(igu_addr, igu_ack.sb_id_and_flags);
 237
 238         /* Both segments (interrupts & acks) are written to same place address;
 239          * Need to guarantee all commands will be received (in-order) by HW.
 240          */
 241         mmiowb();
 242         barrier();
 243 }
 244
 245 void qed_int_sp_dpc(unsigned long hwfn_cookie)
 246 {
 247         struct qed_hwfn *p_hwfn = (struct qed_hwfn *)hwfn_cookie;
 248         struct qed_pi_info *pi_info = NULL;
 249         struct qed_sb_attn_info *sb_attn;
 250         struct qed_sb_info *sb_info;
 251         int arr_size;
 252         u16 rc = 0;
 253
 254         if (!p_hwfn) {
 255                 DP_ERR(p_hwfn->cdev, "DPC called - no hwfn!\n");
 256                 return;
 257         }
 258
 259         if (!p_hwfn->p_sp_sb) {
 260                 DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n");
 261                 return;
 262         }
 263
 264         sb_info = &p_hwfn->p_sp_sb->sb_info;
 265         arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr);
 266         if (!sb_info) {
 267                 DP_ERR(p_hwfn->cdev,
 268                        "Status block is NULL - cannot ack interrupts\n");
 269                 return;
 270         }
 271
 272         if (!p_hwfn->p_sb_attn) {
 273                 DP_ERR(p_hwfn->cdev, "DPC called - no p_sb_attn");
 274                 return;
 275         }
 276         sb_attn = p_hwfn->p_sb_attn;
 277
 278         DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "DPC Called! (hwfn %p %d)\n",
 279                    p_hwfn, p_hwfn->my_id);
 280
 281         /* Disable ack for def status block. Required both for msix +
 282          * inta in non-mask mode, in inta does no harm.
 283          */
 284         qed_sb_ack(sb_info, IGU_INT_DISABLE, 0);
 285
 286         /* Gather Interrupts/Attentions information */
 287         if (!sb_info->sb_virt) {
 288                 DP_ERR(
 289                         p_hwfn->cdev,
 290                         "Interrupt Status block is NULL - cannot check for new interrupts!\n");
 291         } else {
 292                 u32 tmp_index = sb_info->sb_ack;
 293
 294                 rc = qed_sb_update_sb_idx(sb_info);
 295                 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR,
 296                            "Interrupt indices: 0x%08x --> 0x%08x\n",
 297                            tmp_index, sb_info->sb_ack);
 298         }
 299
 300         if (!sb_attn || !sb_attn->sb_attn) {
 301                 DP_ERR(
 302                         p_hwfn->cdev,
 303                         "Attentions Status block is NULL - cannot check for new attentions!\n");
 304         } else {
 305                 u16 tmp_index = sb_attn->index;
 306
 307                 rc |= qed_attn_update_idx(p_hwfn, sb_attn);
 308                 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR,
 309                            "Attention indices: 0x%08x --> 0x%08x\n",
 310                            tmp_index, sb_attn->index);
 311         }
 312
 313         /* Check if we expect interrupts at this time. if not just ack them */
 314         if (!(rc & QED_SB_EVENT_MASK)) {
 315                 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
 316                 return;
 317         }
 318
 319         /* Check the validity of the DPC ptt. If not ack interrupts and fail */
 320         if (!p_hwfn->p_dpc_ptt) {
 321                 DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n");
 322                 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
 323                 return;
 324         }
 325
 326         if (rc & QED_SB_ATT_IDX)
 327                 qed_int_attentions(p_hwfn);
 328
 329         if (rc & QED_SB_IDX) {
 330                 int pi;
 331
 332                 /* Look for a free index */
 333                 for (pi = 0; pi < arr_size; pi++) {
 334                         pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi];
 335                         if (pi_info->comp_cb)
 336                                 pi_info->comp_cb(p_hwfn, pi_info->cookie);
 337                 }
 338         }
 339
 340         if (sb_attn && (rc & QED_SB_ATT_IDX))
 341                 /* This should be done before the interrupts are enabled,
 342                  * since otherwise a new attention will be generated.
 343                  */
 344                 qed_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index);
 345
 346         qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
 347 }
 348
 349 static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn)
 350 {
 351         struct qed_dev *cdev   = p_hwfn->cdev;
 352         struct qed_sb_attn_info *p_sb   = p_hwfn->p_sb_attn;
 353
 354         if (p_sb) {
 355                 if (p_sb->sb_attn)
 356                         dma_free_coherent(&cdev->pdev->dev,
 357                                           SB_ATTN_ALIGNED_SIZE(p_hwfn),
 358                                           p_sb->sb_attn,
 359                                           p_sb->sb_phys);
 360                 kfree(p_sb);
 361         }
 362 }
 363
 364 static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn,
 365                                   struct qed_ptt *p_ptt)
 366 {
 367         struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
 368
 369         memset(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn));
 370
 371         sb_info->index = 0;
 372         sb_info->known_attn = 0;
 373
 374         /* Configure Attention Status Block in IGU */
 375         qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L,
 376                lower_32_bits(p_hwfn->p_sb_attn->sb_phys));
 377         qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H,
 378                upper_32_bits(p_hwfn->p_sb_attn->sb_phys));
 379 }
 380
 381 static void qed_int_sb_attn_init(struct qed_hwfn *p_hwfn,
 382                                  struct qed_ptt *p_ptt,
 383                                  void *sb_virt_addr,
 384                                  dma_addr_t sb_phy_addr)
 385 {
 386         struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
 387
 388         sb_info->sb_attn = sb_virt_addr;
 389         sb_info->sb_phys = sb_phy_addr;
 390
 391         /* Set the address of cleanup for the mcp attention */
 392         sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) +
 393                                  MISC_REG_AEU_GENERAL_ATTN_0;
 394
 395         qed_int_sb_attn_setup(p_hwfn, p_ptt);
 396 }
 397
 398 static int qed_int_sb_attn_alloc(struct qed_hwfn *p_hwfn,
 399                                  struct qed_ptt *p_ptt)
 400 {
 401         struct qed_dev *cdev = p_hwfn->cdev;
 402         struct qed_sb_attn_info *p_sb;
 403         void *p_virt;
 404         dma_addr_t p_phys = 0;
 405
 406         /* SB struct */
 407         p_sb = kmalloc(sizeof(*p_sb), GFP_ATOMIC);
 408         if (!p_sb) {
 409                 DP_NOTICE(cdev, "Failed to allocate `struct qed_sb_attn_info'\n");
 410                 return -ENOMEM;
 411         }
 412
 413         /* SB ring  */
 414         p_virt = dma_alloc_coherent(&cdev->pdev->dev,
 415                                     SB_ATTN_ALIGNED_SIZE(p_hwfn),
 416                                     &p_phys, GFP_KERNEL);
 417
 418         if (!p_virt) {
 419                 DP_NOTICE(cdev, "Failed to allocate status block (attentions)\n");
 420                 kfree(p_sb);
 421                 return -ENOMEM;
 422         }
 423
 424         /* Attention setup */
 425         p_hwfn->p_sb_attn = p_sb;
 426         qed_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys);
 427
 428         return 0;
 429 }
 430
 431 /* coalescing timeout = timeset << (timer_res + 1) */
 432 #define QED_CAU_DEF_RX_USECS 24
 433 #define QED_CAU_DEF_TX_USECS 48
 434
 435 void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
 436                            struct cau_sb_entry *p_sb_entry,
 437                            u8 pf_id,
 438                            u16 vf_number,
 439                            u8 vf_valid)
 440 {
 441         u32 cau_state;
 442
 443         memset(p_sb_entry, 0, sizeof(*p_sb_entry));
 444
 445         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id);
 446         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number);
 447         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid);
 448         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F);
 449         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F);
 450
 451         /* setting the time resultion to a fixed value ( = 1) */
 452         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0,
 453                   QED_CAU_DEF_RX_TIMER_RES);
 454         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1,
 455                   QED_CAU_DEF_TX_TIMER_RES);
 456
 457         cau_state = CAU_HC_DISABLE_STATE;
 458
 459         if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) {
 460                 cau_state = CAU_HC_ENABLE_STATE;
 461                 if (!p_hwfn->cdev->rx_coalesce_usecs)
 462                         p_hwfn->cdev->rx_coalesce_usecs =
 463                                 QED_CAU_DEF_RX_USECS;
 464                 if (!p_hwfn->cdev->tx_coalesce_usecs)
 465                         p_hwfn->cdev->tx_coalesce_usecs =
 466                                 QED_CAU_DEF_TX_USECS;
 467         }
 468
 469         SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state);
 470         SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state);
 471 }
 472
 473 void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,
 474                          struct qed_ptt *p_ptt,
 475                          dma_addr_t sb_phys,
 476                          u16 igu_sb_id,
 477                          u16 vf_number,
 478                          u8 vf_valid)
 479 {
 480         struct cau_sb_entry sb_entry;
 481         u32 val;
 482
 483         qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id,
 484                               vf_number, vf_valid);
 485
 486         if (p_hwfn->hw_init_done) {
 487                 val = CAU_REG_SB_ADDR_MEMORY + igu_sb_id * sizeof(u64);
 488                 qed_wr(p_hwfn, p_ptt, val, lower_32_bits(sb_phys));
 489                 qed_wr(p_hwfn, p_ptt, val + sizeof(u32),
 490                        upper_32_bits(sb_phys));
 491
 492                 val = CAU_REG_SB_VAR_MEMORY + igu_sb_id * sizeof(u64);
 493                 qed_wr(p_hwfn, p_ptt, val, sb_entry.data);
 494                 qed_wr(p_hwfn, p_ptt, val + sizeof(u32), sb_entry.params);
 495         } else {
 496                 /* Initialize Status Block Address */
 497                 STORE_RT_REG_AGG(p_hwfn,
 498                                  CAU_REG_SB_ADDR_MEMORY_RT_OFFSET +
 499                                  igu_sb_id * 2,
 500                                  sb_phys);
 501
 502                 STORE_RT_REG_AGG(p_hwfn,
 503                                  CAU_REG_SB_VAR_MEMORY_RT_OFFSET +
 504                                  igu_sb_id * 2,
 505                                  sb_entry);
 506         }
 507
 508         /* Configure pi coalescing if set */
 509         if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) {
 510                 u8 timeset = p_hwfn->cdev->rx_coalesce_usecs >>
 511                              (QED_CAU_DEF_RX_TIMER_RES + 1);
 512                 u8 num_tc = 1, i;
 513
 514                 qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI,
 515                                     QED_COAL_RX_STATE_MACHINE,
 516                                     timeset);
 517
 518                 timeset = p_hwfn->cdev->tx_coalesce_usecs >>
 519                           (QED_CAU_DEF_TX_TIMER_RES + 1);
 520
 521                 for (i = 0; i < num_tc; i++) {
 522                         qed_int_cau_conf_pi(p_hwfn, p_ptt,
 523                                             igu_sb_id, TX_PI(i),
 524                                             QED_COAL_TX_STATE_MACHINE,
 525                                             timeset);
 526                 }
 527         }
 528 }
 529
 530 void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn,
 531                          struct qed_ptt *p_ptt,
 532                          u16 igu_sb_id,
 533                          u32 pi_index,
 534                          enum qed_coalescing_fsm coalescing_fsm,
 535                          u8 timeset)
 536 {
 537         struct cau_pi_entry pi_entry;
 538         u32 sb_offset;
 539         u32 pi_offset;
 540
 541         sb_offset = igu_sb_id * PIS_PER_SB;
 542         memset(&pi_entry, 0, sizeof(struct cau_pi_entry));
 543
 544         SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
 545         if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE)
 546                 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0);
 547         else
 548                 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1);
 549
 550         pi_offset = sb_offset + pi_index;
 551         if (p_hwfn->hw_init_done) {
 552                 qed_wr(p_hwfn, p_ptt,
 553                        CAU_REG_PI_MEMORY + pi_offset * sizeof(u32),
 554                        *((u32 *)&(pi_entry)));
 555         } else {
 556                 STORE_RT_REG(p_hwfn,
 557                              CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset,
 558                              *((u32 *)&(pi_entry)));
 559         }
 560 }
 561
 562 void qed_int_sb_setup(struct qed_hwfn *p_hwfn,
 563                       struct qed_ptt *p_ptt,
 564                       struct qed_sb_info *sb_info)
 565 {
 566         /* zero status block and ack counter */
 567         sb_info->sb_ack = 0;
 568         memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
 569
 570         qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys,
 571                             sb_info->igu_sb_id, 0, 0);
 572 }
 573
 574 /**
 575  * @brief qed_get_igu_sb_id - given a sw sb_id return the
 576  *        igu_sb_id
 577  *
 578  * @param p_hwfn
 579  * @param sb_id
 580  *
 581  * @return u16
 582  */
 583 static u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn,
 584                              u16 sb_id)
 585 {
 586         u16 igu_sb_id;
 587
 588         /* Assuming continuous set of IGU SBs dedicated for given PF */
 589         if (sb_id == QED_SP_SB_ID)
 590                 igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
 591         else
 592                 igu_sb_id = sb_id + p_hwfn->hw_info.p_igu_info->igu_base_sb;
 593
 594         DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "SB [%s] index is 0x%04x\n",
 595                    (sb_id == QED_SP_SB_ID) ? "DSB" : "non-DSB", igu_sb_id);
 596
 597         return igu_sb_id;
 598 }
 599
 600 int qed_int_sb_init(struct qed_hwfn *p_hwfn,
 601                     struct qed_ptt *p_ptt,
 602                     struct qed_sb_info *sb_info,
 603                     void *sb_virt_addr,
 604                     dma_addr_t sb_phy_addr,
 605                     u16 sb_id)
 606 {
 607         sb_info->sb_virt = sb_virt_addr;
 608         sb_info->sb_phys = sb_phy_addr;
 609
 610         sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id);
 611
 612         if (sb_id != QED_SP_SB_ID) {
 613                 p_hwfn->sbs_info[sb_id] = sb_info;
 614                 p_hwfn->num_sbs++;
 615         }
 616
 617         sb_info->cdev = p_hwfn->cdev;
 618
 619         /* The igu address will hold the absolute address that needs to be
 620          * written to for a specific status block
 621          */
 622         sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview +
 623                                           GTT_BAR0_MAP_REG_IGU_CMD +
 624                                           (sb_info->igu_sb_id << 3);
 625
 626         sb_info->flags |= QED_SB_INFO_INIT;
 627
 628         qed_int_sb_setup(p_hwfn, p_ptt, sb_info);
 629
 630         return 0;
 631 }
 632
 633 int qed_int_sb_release(struct qed_hwfn *p_hwfn,
 634                        struct qed_sb_info *sb_info,
 635                        u16 sb_id)
 636 {
 637         if (sb_id == QED_SP_SB_ID) {
 638                 DP_ERR(p_hwfn, "Do Not free sp sb using this function");
 639                 return -EINVAL;
 640         }
 641
 642         /* zero status block and ack counter */
 643         sb_info->sb_ack = 0;
 644         memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
 645
 646         p_hwfn->sbs_info[sb_id] = NULL;
 647         p_hwfn->num_sbs--;
 648
 649         return 0;
 650 }
 651
 652 static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn)
 653 {
 654         struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb;
 655
 656         if (p_sb) {
 657                 if (p_sb->sb_info.sb_virt)
 658                         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
 659                                           SB_ALIGNED_SIZE(p_hwfn),
 660                                           p_sb->sb_info.sb_virt,
 661                                           p_sb->sb_info.sb_phys);
 662                 kfree(p_sb);
 663         }
 664 }
 665
 666 static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn,
 667                                struct qed_ptt *p_ptt)
 668 {
 669         struct qed_sb_sp_info *p_sb;
 670         dma_addr_t p_phys = 0;
 671         void *p_virt;
 672
 673         /* SB struct */
 674         p_sb = kmalloc(sizeof(*p_sb), GFP_ATOMIC);
 675         if (!p_sb) {
 676                 DP_NOTICE(p_hwfn, "Failed to allocate `struct qed_sb_info'\n");
 677                 return -ENOMEM;
 678         }
 679
 680         /* SB ring  */
 681         p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
 682                                     SB_ALIGNED_SIZE(p_hwfn),
 683                                     &p_phys, GFP_KERNEL);
 684         if (!p_virt) {
 685                 DP_NOTICE(p_hwfn, "Failed to allocate status block\n");
 686                 kfree(p_sb);
 687                 return -ENOMEM;
 688         }
 689
 690         /* Status Block setup */
 691         p_hwfn->p_sp_sb = p_sb;
 692         qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt,
 693                         p_phys, QED_SP_SB_ID);
 694
 695         memset(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr));
 696
 697         return 0;
 698 }
 699
 700 static void qed_int_sp_sb_setup(struct qed_hwfn *p_hwfn,
 701                                 struct qed_ptt *p_ptt)
 702 {
 703         if (!p_hwfn)
 704                 return;
 705
 706         if (p_hwfn->p_sp_sb)
 707                 qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info);
 708         else
 709                 DP_NOTICE(p_hwfn->cdev,
 710                           "Failed to setup Slow path status block - NULL pointer\n");
 711
 712         if (p_hwfn->p_sb_attn)
 713                 qed_int_sb_attn_setup(p_hwfn, p_ptt);
 714         else
 715                 DP_NOTICE(p_hwfn->cdev,
 716                           "Failed to setup attentions status block - NULL pointer\n");
 717 }
 718
 719 int qed_int_register_cb(struct qed_hwfn *p_hwfn,
 720                         qed_int_comp_cb_t comp_cb,
 721                         void *cookie,
 722                         u8 *sb_idx,
 723                         __le16 **p_fw_cons)
 724 {
 725         struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
 726         int qed_status = -ENOMEM;
 727         u8 pi;
 728
 729         /* Look for a free index */
 730         for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) {
 731                 if (!p_sp_sb->pi_info_arr[pi].comp_cb) {
 732                         p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb;
 733                         p_sp_sb->pi_info_arr[pi].cookie = cookie;
 734                         *sb_idx = pi;
 735                         *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi];
 736                         qed_status = 0;
 737                         break;
 738                 }
 739         }
 740
 741         return qed_status;
 742 }
 743
 744 int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi)
 745 {
 746         struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
 747         int qed_status = -ENOMEM;
 748
 749         if (p_sp_sb->pi_info_arr[pi].comp_cb) {
 750                 p_sp_sb->pi_info_arr[pi].comp_cb = NULL;
 751                 p_sp_sb->pi_info_arr[pi].cookie = NULL;
 752                 qed_status = 0;
 753         }
 754
 755         return qed_status;
 756 }
 757
 758 u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn)
 759 {
 760         return p_hwfn->p_sp_sb->sb_info.igu_sb_id;
 761 }
 762
 763 void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn,
 764                             struct qed_ptt *p_ptt,
 765                             enum qed_int_mode int_mode)
 766 {
 767         u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN;
 768
 769         p_hwfn->cdev->int_mode = int_mode;
 770         switch (p_hwfn->cdev->int_mode) {
 771         case QED_INT_MODE_INTA:
 772                 igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN;
 773                 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
 774                 break;
 775
 776         case QED_INT_MODE_MSI:
 777                 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
 778                 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
 779                 break;
 780
 781         case QED_INT_MODE_MSIX:
 782                 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
 783                 break;
 784         case QED_INT_MODE_POLL:
 785                 break;
 786         }
 787
 788         qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf);
 789 }
 790
 791 void qed_int_igu_enable(struct qed_hwfn *p_hwfn,
 792                         struct qed_ptt *p_ptt,
 793                         enum qed_int_mode int_mode)
 794 {
 795         int i;
 796
 797         p_hwfn->b_int_enabled = 1;
 798
 799         /* Mask non-link attentions */
 800         for (i = 0; i < 9; i++)
 801                 qed_wr(p_hwfn, p_ptt,
 802                        MISC_REG_AEU_ENABLE1_IGU_OUT_0 + (i << 2), 0);
 803
 804         /* Enable interrupt Generation */
 805         qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode);
 806
 807         /* Configure AEU signal change to produce attentions for link */
 808         qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff);
 809         qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff);
 810
 811         /* Flush the writes to IGU */
 812         mmiowb();
 813
 814         /* Unmask AEU signals toward IGU */
 815         qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff);
 816 }
 817
 818 void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn,
 819                              struct qed_ptt *p_ptt)
 820 {
 821         p_hwfn->b_int_enabled = 0;
 822
 823         qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
 824 }
 825
 826 #define IGU_CLEANUP_SLEEP_LENGTH                (1000)
 827 void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn,
 828                             struct qed_ptt *p_ptt,
 829                             u32 sb_id,
 830                             bool cleanup_set,
 831                             u16 opaque_fid
 832                             )
 833 {
 834         u32 pxp_addr = IGU_CMD_INT_ACK_BASE + sb_id;
 835         u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH;
 836         u32 data = 0;
 837         u32 cmd_ctrl = 0;
 838         u32 val = 0;
 839         u32 sb_bit = 0;
 840         u32 sb_bit_addr = 0;
 841
 842         /* Set the data field */
 843         SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0);
 844         SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, 0);
 845         SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET);
 846
 847         /* Set the control register */
 848         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr);
 849         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid);
 850         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR);
 851
 852         qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data);
 853
 854         barrier();
 855
 856         qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl);
 857
 858         /* Flush the write to IGU */
 859         mmiowb();
 860
 861         /* calculate where to read the status bit from */
 862         sb_bit = 1 << (sb_id % 32);
 863         sb_bit_addr = sb_id / 32 * sizeof(u32);
 864
 865         sb_bit_addr += IGU_REG_CLEANUP_STATUS_0;
 866
 867         /* Now wait for the command to complete */
 868         do {
 869                 val = qed_rd(p_hwfn, p_ptt, sb_bit_addr);
 870
 871                 if ((val & sb_bit) == (cleanup_set ? sb_bit : 0))
 872                         break;
 873
 874                 usleep_range(5000, 10000);
 875         } while (--sleep_cnt);
 876
 877         if (!sleep_cnt)
 878                 DP_NOTICE(p_hwfn,
 879                           "Timeout waiting for clear status 0x%08x [for sb %d]\n",
 880                           val, sb_id);
 881 }
 882
 883 void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn,
 884                                      struct qed_ptt *p_ptt,
 885                                      u32 sb_id,
 886                                      u16 opaque,
 887                                      bool b_set)
 888 {
 889         int pi;
 890
 891         /* Set */
 892         if (b_set)
 893                 qed_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 1, opaque);
 894
 895         /* Clear */
 896         qed_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 0, opaque);
 897
 898         /* Clear the CAU for the SB */
 899         for (pi = 0; pi < 12; pi++)
 900                 qed_wr(p_hwfn, p_ptt,
 901                        CAU_REG_PI_MEMORY + (sb_id * 12 + pi) * 4, 0);
 902 }
 903
 904 void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn,
 905                               struct qed_ptt *p_ptt,
 906                               bool b_set,
 907                               bool b_slowpath)
 908 {
 909         u32 igu_base_sb = p_hwfn->hw_info.p_igu_info->igu_base_sb;
 910         u32 igu_sb_cnt = p_hwfn->hw_info.p_igu_info->igu_sb_cnt;
 911         u32 sb_id = 0;
 912         u32 val = 0;
 913
 914         val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION);
 915         val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN;
 916         val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN;
 917         qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val);
 918
 919         DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
 920                    "IGU cleaning SBs [%d,...,%d]\n",
 921                    igu_base_sb, igu_base_sb + igu_sb_cnt - 1);
 922
 923         for (sb_id = igu_base_sb; sb_id < igu_base_sb + igu_sb_cnt; sb_id++)
 924                 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id,
 925                                                 p_hwfn->hw_info.opaque_fid,
 926                                                 b_set);
 927
 928         if (b_slowpath) {
 929                 sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
 930                 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
 931                            "IGU cleaning slowpath SB [%d]\n", sb_id);
 932                 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id,
 933                                                 p_hwfn->hw_info.opaque_fid,
 934                                                 b_set);
 935         }
 936 }
 937
 938 int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn,
 939                          struct qed_ptt *p_ptt)
 940 {
 941         struct qed_igu_info *p_igu_info;
 942         struct qed_igu_block *blk;
 943         u32 val;
 944         u16 sb_id;
 945         u16 prev_sb_id = 0xFF;
 946
 947         p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_ATOMIC);
 948
 949         if (!p_hwfn->hw_info.p_igu_info)
 950                 return -ENOMEM;
 951
 952         p_igu_info = p_hwfn->hw_info.p_igu_info;
 953
 954         /* Initialize base sb / sb cnt for PFs */
 955         p_igu_info->igu_base_sb         = 0xffff;
 956         p_igu_info->igu_sb_cnt          = 0;
 957         p_igu_info->igu_dsb_id          = 0xffff;
 958         p_igu_info->igu_base_sb_iov     = 0xffff;
 959
 960         for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev);
 961              sb_id++) {
 962                 blk = &p_igu_info->igu_map.igu_blocks[sb_id];
 963
 964                 val = qed_rd(p_hwfn, p_ptt,
 965                              IGU_REG_MAPPING_MEMORY + sizeof(u32) * sb_id);
 966
 967                 /* stop scanning when hit first invalid PF entry */
 968                 if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) &&
 969                     GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID))
 970                         break;
 971
 972                 blk->status = QED_IGU_STATUS_VALID;
 973                 blk->function_id = GET_FIELD(val,
 974                                              IGU_MAPPING_LINE_FUNCTION_NUMBER);
 975                 blk->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID);
 976                 blk->vector_number = GET_FIELD(val,
 977                                                IGU_MAPPING_LINE_VECTOR_NUMBER);
 978
 979                 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
 980                            "IGU_BLOCK[sb_id]:%x:func_id = %d is_pf = %d vector_num = 0x%x\n",
 981                            val, blk->function_id, blk->is_pf,
 982                            blk->vector_number);
 983
 984                 if (blk->is_pf) {
 985                         if (blk->function_id == p_hwfn->rel_pf_id) {
 986                                 blk->status |= QED_IGU_STATUS_PF;
 987
 988                                 if (blk->vector_number == 0) {
 989                                         if (p_igu_info->igu_dsb_id == 0xffff)
 990                                                 p_igu_info->igu_dsb_id = sb_id;
 991                                 } else {
 992                                         if (p_igu_info->igu_base_sb ==
 993                                             0xffff) {
 994                                                 p_igu_info->igu_base_sb = sb_id;
 995                                         } else if (prev_sb_id != sb_id - 1) {
 996                                                 DP_NOTICE(p_hwfn->cdev,
 997                                                           "consecutive igu vectors for HWFN %x broken",
 998                                                           p_hwfn->rel_pf_id);
 999                                                 break;
1000                                         }
1001                                         prev_sb_id = sb_id;
1002                                         /* we don't count the default */
1003                                         (p_igu_info->igu_sb_cnt)++;
1004                                 }
1005                         }
1006                 }
1007         }
1008
1009         DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1010                    "IGU igu_base_sb=0x%x igu_sb_cnt=%d igu_dsb_id=0x%x\n",
1011                    p_igu_info->igu_base_sb,
1012                    p_igu_info->igu_sb_cnt,
1013                    p_igu_info->igu_dsb_id);
1014
1015         if (p_igu_info->igu_base_sb == 0xffff ||
1016             p_igu_info->igu_dsb_id == 0xffff ||
1017             p_igu_info->igu_sb_cnt == 0) {
1018                 DP_NOTICE(p_hwfn,
1019                           "IGU CAM returned invalid values igu_base_sb=0x%x igu_sb_cnt=%d igu_dsb_id=0x%x\n",
1020                            p_igu_info->igu_base_sb,
1021                            p_igu_info->igu_sb_cnt,
1022                            p_igu_info->igu_dsb_id);
1023                 return -EINVAL;
1024         }
1025
1026         return 0;
1027 }
1028
1029 /**
1030  * @brief Initialize igu runtime registers
1031  *
1032  * @param p_hwfn
1033  */
1034 void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn)
1035 {
1036         u32 igu_pf_conf = 0;
1037
1038         igu_pf_conf |= IGU_PF_CONF_FUNC_EN;
1039
1040         STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf);
1041 }
1042
1043 u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn)
1044 {
1045         u64 intr_status = 0;
1046         u32 intr_status_lo = 0;
1047         u32 intr_status_hi = 0;
1048         u32 lsb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_LSB_UPPER -
1049                                IGU_CMD_INT_ACK_BASE;
1050         u32 msb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_MSB_UPPER -
1051                                IGU_CMD_INT_ACK_BASE;
1052
1053         intr_status_lo = REG_RD(p_hwfn,
1054                                 GTT_BAR0_MAP_REG_IGU_CMD +
1055                                 lsb_igu_cmd_addr * 8);
1056         intr_status_hi = REG_RD(p_hwfn,
1057                                 GTT_BAR0_MAP_REG_IGU_CMD +
1058                                 msb_igu_cmd_addr * 8);
1059         intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo;
1060
1061         return intr_status;
1062 }
1063
1064 static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn)
1065 {
1066         tasklet_init(p_hwfn->sp_dpc,
1067                      qed_int_sp_dpc, (unsigned long)p_hwfn);
1068         p_hwfn->b_sp_dpc_enabled = true;
1069 }
1070
1071 static int qed_int_sp_dpc_alloc(struct qed_hwfn *p_hwfn)
1072 {
1073         p_hwfn->sp_dpc = kmalloc(sizeof(*p_hwfn->sp_dpc), GFP_ATOMIC);
1074         if (!p_hwfn->sp_dpc)
1075                 return -ENOMEM;
1076
1077         return 0;
1078 }
1079
1080 static void qed_int_sp_dpc_free(struct qed_hwfn *p_hwfn)
1081 {
1082         kfree(p_hwfn->sp_dpc);
1083 }
1084
1085 int qed_int_alloc(struct qed_hwfn *p_hwfn,
1086                   struct qed_ptt *p_ptt)
1087 {
1088         int rc = 0;
1089
1090         rc = qed_int_sp_dpc_alloc(p_hwfn);
1091         if (rc) {
1092                 DP_ERR(p_hwfn->cdev, "Failed to allocate sp dpc mem\n");
1093                 return rc;
1094         }
1095         rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt);
1096         if (rc) {
1097                 DP_ERR(p_hwfn->cdev, "Failed to allocate sp sb mem\n");
1098                 return rc;
1099         }
1100         rc = qed_int_sb_attn_alloc(p_hwfn, p_ptt);
1101         if (rc) {
1102                 DP_ERR(p_hwfn->cdev, "Failed to allocate sb attn mem\n");
1103                 return rc;
1104         }
1105         return rc;
1106 }
1107
1108 void qed_int_free(struct qed_hwfn *p_hwfn)
1109 {
1110         qed_int_sp_sb_free(p_hwfn);
1111         qed_int_sb_attn_free(p_hwfn);
1112         qed_int_sp_dpc_free(p_hwfn);
1113 }
1114
1115 void qed_int_setup(struct qed_hwfn *p_hwfn,
1116                    struct qed_ptt *p_ptt)
1117 {
1118         qed_int_sp_sb_setup(p_hwfn, p_ptt);
1119         qed_int_sp_dpc_setup(p_hwfn);
1120 }
1121
1122 int qed_int_get_num_sbs(struct qed_hwfn *p_hwfn,
1123                         int *p_iov_blks)
1124 {
1125         struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info;
1126
1127         if (!info)
1128                 return 0;
1129
1130         if (p_iov_blks)
1131                 *p_iov_blks = info->free_blks;
1132
1133         return info->igu_sb_cnt;
1134 }