1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, see <http://www.gnu.org/licenses/>.
23 . Information contained in this file was obtained from the LAN91C111
24 . manual from SMC. To get a copy, if you really want one, you can find
25 . information under www.smsc.com.
28 . Erik Stahlman <erik@vt.edu>
29 . Daris A Nevil <dnevil@snmc.com>
30 . Nicolas Pitre <nico@fluxnic.net>
32 ---------------------------------------------------------------------------*/
36 #include <linux/dmaengine.h>
37 #include <linux/smc91x.h>
40 * Define your architecture specific bus configuration parameters here.
43 #if defined(CONFIG_ARM)
45 #include <asm/mach-types.h>
47 /* Now the bus width is specified in the platform data
48 * pretend here to support all I/O access types
50 #define SMC_CAN_USE_8BIT 1
51 #define SMC_CAN_USE_16BIT 1
52 #define SMC_CAN_USE_32BIT 1
55 #define SMC_IO_SHIFT (lp->io_shift)
57 #define SMC_inb(a, r) readb((a) + (r))
58 #define SMC_inw(a, r) readw((a) + (r))
59 #define SMC_inl(a, r) readl((a) + (r))
60 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
61 #define SMC_outl(v, a, r) writel(v, (a) + (r))
62 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
63 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
64 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
65 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
66 #define SMC_IRQ_FLAGS (-1) /* from resource */
68 /* We actually can't write halfwords properly if not word aligned */
69 static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
71 if ((machine_is_mainstone() || machine_is_stargate2() ||
72 machine_is_pxa_idp()) && reg & 2) {
73 unsigned int v = val << 16;
74 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
75 writel(v, ioaddr + (reg & ~2));
77 writew(val, ioaddr + reg);
81 #elif defined(CONFIG_SH_SH4202_MICRODEV)
83 #define SMC_CAN_USE_8BIT 0
84 #define SMC_CAN_USE_16BIT 1
85 #define SMC_CAN_USE_32BIT 0
87 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
88 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
89 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
90 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
91 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
92 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
93 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
94 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
95 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
96 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
98 #define SMC_IRQ_FLAGS (0)
100 #elif defined(CONFIG_M32R)
102 #define SMC_CAN_USE_8BIT 0
103 #define SMC_CAN_USE_16BIT 1
104 #define SMC_CAN_USE_32BIT 0
106 #define SMC_inb(a, r) inb(((u32)a) + (r))
107 #define SMC_inw(a, r) inw(((u32)a) + (r))
108 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
109 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
110 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
111 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
113 #define SMC_IRQ_FLAGS (0)
115 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
116 #define RPC_LSB_DEFAULT RPC_LED_100_10
118 #elif defined(CONFIG_MN10300)
121 * MN10300/AM33 configuration
124 #include <unit/smc91111.h>
126 #elif defined(CONFIG_ATARI)
128 #define SMC_CAN_USE_8BIT 1
129 #define SMC_CAN_USE_16BIT 1
130 #define SMC_CAN_USE_32BIT 1
133 #define SMC_inb(a, r) readb((a) + (r))
134 #define SMC_inw(a, r) readw((a) + (r))
135 #define SMC_inl(a, r) readl((a) + (r))
136 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
137 #define SMC_outw(v, a, r) writew(v, (a) + (r))
138 #define SMC_outl(v, a, r) writel(v, (a) + (r))
139 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
140 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
141 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
142 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
144 #define RPC_LSA_DEFAULT RPC_LED_100_10
145 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
147 #elif defined(CONFIG_COLDFIRE)
149 #define SMC_CAN_USE_8BIT 0
150 #define SMC_CAN_USE_16BIT 1
151 #define SMC_CAN_USE_32BIT 0
154 static inline void mcf_insw(void *a, unsigned char *p, int l)
161 static inline void mcf_outsw(void *a, unsigned char *p, int l)
168 #define SMC_inw(a, r) _swapw(readw((a) + (r)))
169 #define SMC_outw(v, a, r) writew(_swapw(v), (a) + (r))
170 #define SMC_insw(a, r, p, l) mcf_insw(a + r, p, l)
171 #define SMC_outsw(a, r, p, l) mcf_outsw(a + r, p, l)
173 #define SMC_IRQ_FLAGS 0
178 * Default configuration
181 #define SMC_CAN_USE_8BIT 1
182 #define SMC_CAN_USE_16BIT 1
183 #define SMC_CAN_USE_32BIT 1
186 #define SMC_IO_SHIFT (lp->io_shift)
188 #define SMC_inb(a, r) ioread8((a) + (r))
189 #define SMC_inw(a, r) ioread16((a) + (r))
190 #define SMC_inl(a, r) ioread32((a) + (r))
191 #define SMC_outb(v, a, r) iowrite8(v, (a) + (r))
192 #define SMC_outw(v, a, r) iowrite16(v, (a) + (r))
193 #define SMC_outl(v, a, r) iowrite32(v, (a) + (r))
194 #define SMC_insw(a, r, p, l) ioread16_rep((a) + (r), p, l)
195 #define SMC_outsw(a, r, p, l) iowrite16_rep((a) + (r), p, l)
196 #define SMC_insl(a, r, p, l) ioread32_rep((a) + (r), p, l)
197 #define SMC_outsl(a, r, p, l) iowrite32_rep((a) + (r), p, l)
199 #define RPC_LSA_DEFAULT RPC_LED_100_10
200 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
205 /* store this information for the driver.. */
208 * If I have to wait until memory is available to send a
209 * packet, I will store the skbuff here, until I get the
210 * desired memory. Then, I'll send it out and free it.
212 struct sk_buff *pending_tx_skb;
213 struct tasklet_struct tx_task;
215 struct gpio_desc *power_gpio;
216 struct gpio_desc *reset_gpio;
218 /* version/revision of the SMC91x chip */
221 /* Contains the current active transmission mode */
224 /* Contains the current active receive mode */
227 /* Contains the current active receive/phy mode */
234 struct mii_if_info mii;
237 struct work_struct phy_configure;
238 struct net_device *dev;
243 #ifdef CONFIG_ARCH_PXA
244 /* DMA needs the physical address of the chip */
246 struct device *device;
248 struct dma_chan *dma_chan;
250 void __iomem *datacs;
252 /* the low address lines on some platforms aren't connected... */
255 struct smc91x_platdata cfg;
258 #define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT)
259 #define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT)
260 #define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT)
262 #ifdef CONFIG_ARCH_PXA
264 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
265 * always happening in irq context so no need to worry about races. TX is
266 * different and probably not worth it for that reason, and not as critical
267 * as RX which can overrun memory and lose packets.
269 #include <linux/dma-mapping.h>
270 #include <linux/dma/pxa-dma.h>
274 #define SMC_insl(a, r, p, l) \
275 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
277 smc_pxa_dma_inpump(struct smc_local *lp, u_char *buf, int len)
280 struct dma_async_tx_descriptor *tx;
282 enum dma_status status;
283 struct dma_tx_state state;
285 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
286 tx = dmaengine_prep_slave_single(lp->dma_chan, dmabuf, len,
289 cookie = dmaengine_submit(tx);
290 dma_async_issue_pending(lp->dma_chan);
292 status = dmaengine_tx_status(lp->dma_chan, cookie,
295 } while (status != DMA_COMPLETE && status != DMA_ERROR &&
297 dmaengine_terminate_all(lp->dma_chan);
299 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
303 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
304 u_char *buf, int len)
306 struct dma_slave_config config;
309 /* fallback if no DMA available */
311 readsl(ioaddr + reg, buf, len);
315 /* 64 bit alignment is required for memory to memory DMA */
317 *((u32 *)buf) = SMC_inl(ioaddr, reg);
322 memset(&config, 0, sizeof(config));
323 config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
324 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
325 config.src_addr = lp->physaddr + reg;
326 config.dst_addr = lp->physaddr + reg;
327 config.src_maxburst = 32;
328 config.dst_maxburst = 32;
329 ret = dmaengine_slave_config(lp->dma_chan, &config);
331 dev_err(lp->device, "dma channel configuration failed: %d\n",
337 smc_pxa_dma_inpump(lp, buf, len);
343 #define SMC_insw(a, r, p, l) \
344 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
346 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
347 u_char *buf, int len)
349 struct dma_slave_config config;
352 /* fallback if no DMA available */
354 readsw(ioaddr + reg, buf, len);
358 /* 64 bit alignment is required for memory to memory DMA */
359 while ((long)buf & 6) {
360 *((u16 *)buf) = SMC_inw(ioaddr, reg);
365 memset(&config, 0, sizeof(config));
366 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
367 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
368 config.src_addr = lp->physaddr + reg;
369 config.dst_addr = lp->physaddr + reg;
370 config.src_maxburst = 32;
371 config.dst_maxburst = 32;
372 ret = dmaengine_slave_config(lp->dma_chan, &config);
374 dev_err(lp->device, "dma channel configuration failed: %d\n",
380 smc_pxa_dma_inpump(lp, buf, len);
384 #endif /* CONFIG_ARCH_PXA */
388 * Everything a particular hardware setup needs should have been defined
389 * at this point. Add stubs for the undefined cases, mainly to avoid
390 * compilation warnings since they'll be optimized away, or to prevent buggy
394 #if ! SMC_CAN_USE_32BIT
395 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
396 #define SMC_outl(x, ioaddr, reg) BUG()
397 #define SMC_insl(a, r, p, l) BUG()
398 #define SMC_outsl(a, r, p, l) BUG()
401 #if !defined(SMC_insl) || !defined(SMC_outsl)
402 #define SMC_insl(a, r, p, l) BUG()
403 #define SMC_outsl(a, r, p, l) BUG()
406 #if ! SMC_CAN_USE_16BIT
409 * Any 16-bit access is performed with two 8-bit accesses if the hardware
410 * can't do it directly. Most registers are 16-bit so those are mandatory.
412 #define SMC_outw(x, ioaddr, reg) \
414 unsigned int __val16 = (x); \
415 SMC_outb( __val16, ioaddr, reg ); \
416 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
418 #define SMC_inw(ioaddr, reg) \
420 unsigned int __val16; \
421 __val16 = SMC_inb( ioaddr, reg ); \
422 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
426 #define SMC_insw(a, r, p, l) BUG()
427 #define SMC_outsw(a, r, p, l) BUG()
431 #if !defined(SMC_insw) || !defined(SMC_outsw)
432 #define SMC_insw(a, r, p, l) BUG()
433 #define SMC_outsw(a, r, p, l) BUG()
436 #if ! SMC_CAN_USE_8BIT
437 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
438 #define SMC_outb(x, ioaddr, reg) BUG()
439 #define SMC_insb(a, r, p, l) BUG()
440 #define SMC_outsb(a, r, p, l) BUG()
443 #if !defined(SMC_insb) || !defined(SMC_outsb)
444 #define SMC_insb(a, r, p, l) BUG()
445 #define SMC_outsb(a, r, p, l) BUG()
448 #ifndef SMC_CAN_USE_DATACS
449 #define SMC_CAN_USE_DATACS 0
453 #define SMC_IO_SHIFT 0
456 #ifndef SMC_IRQ_FLAGS
457 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
460 #ifndef SMC_INTERRUPT_PREAMBLE
461 #define SMC_INTERRUPT_PREAMBLE
465 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
466 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
467 #define SMC_DATA_EXTENT (4)
470 . Bank Select Register:
472 . yyyy yyyy 0000 00xx
474 . yyyy yyyy = 0x33, for identification purposes.
476 #define BANK_SELECT (14 << SMC_IO_SHIFT)
479 // Transmit Control Register
481 #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
482 #define TCR_ENABLE 0x0001 // When 1 we can transmit
483 #define TCR_LOOP 0x0002 // Controls output pin LBK
484 #define TCR_FORCOL 0x0004 // When 1 will force a collision
485 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
486 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
487 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
488 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
489 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
490 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
491 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
493 #define TCR_CLEAR 0 /* do NOTHING */
494 /* the default settings for the TCR register : */
495 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
498 // EPH Status Register
500 #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
501 #define ES_TX_SUC 0x0001 // Last TX was successful
502 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
503 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
504 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
505 #define ES_16COL 0x0010 // 16 Collisions Reached
506 #define ES_SQET 0x0020 // Signal Quality Error Test
507 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
508 #define ES_TXDEFR 0x0080 // Transmit Deferred
509 #define ES_LATCOL 0x0200 // Late collision detected on last tx
510 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
511 #define ES_EXC_DEF 0x0800 // Excessive Deferral
512 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
513 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
514 #define ES_TXUNRN 0x8000 // Tx Underrun
517 // Receive Control Register
519 #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
520 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
521 #define RCR_PRMS 0x0002 // Enable promiscuous mode
522 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
523 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
524 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
525 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
526 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
527 #define RCR_SOFTRST 0x8000 // resets the chip
529 /* the normal settings for the RCR register : */
530 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
531 #define RCR_CLEAR 0x0 // set it to a base state
536 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
539 // Memory Information Register
541 #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
544 // Receive/Phy Control Register
546 #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
547 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
548 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
549 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
550 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
551 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
553 #ifndef RPC_LSA_DEFAULT
554 #define RPC_LSA_DEFAULT RPC_LED_100
556 #ifndef RPC_LSB_DEFAULT
557 #define RPC_LSB_DEFAULT RPC_LED_FD
560 #define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX)
563 /* Bank 0 0x0C is reserved */
565 // Bank Select Register
567 #define BSR_REG 0x000E
572 #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
573 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
574 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
575 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
576 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
578 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
579 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
582 // Base Address Register
584 #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
587 // Individual Address Registers
589 #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
590 #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
591 #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
594 // General Purpose Register
596 #define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
601 #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
602 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
603 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
604 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
605 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
606 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
607 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
608 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
609 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
612 // MMU Command Register
614 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
615 #define MC_BUSY 1 // When 1 the last release has not completed
616 #define MC_NOP (0<<5) // No Op
617 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
618 #define MC_RESET (2<<5) // Reset MMU to initial state
619 #define MC_REMOVE (3<<5) // Remove the current rx packet
620 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
621 #define MC_FREEPKT (5<<5) // Release packet in PNR register
622 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
623 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
626 // Packet Number Register
628 #define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
631 // Allocation Result Register
633 #define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
634 #define AR_FAILED 0x80 // Alocation Failed
637 // TX FIFO Ports Register
639 #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
640 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
642 // RX FIFO Ports Register
644 #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
645 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
647 #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
651 #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
652 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
653 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
654 #define PTR_READ 0x2000 // When 1 the operation is a read
659 #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
662 // Interrupt Status/Acknowledge Register
664 #define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
667 // Interrupt Mask Register
669 #define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
670 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
671 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
672 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
673 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
674 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
675 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
676 #define IM_TX_INT 0x02 // Transmit Interrupt
677 #define IM_RCV_INT 0x01 // Receive Interrupt
680 // Multicast Table Registers
682 #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
683 #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
684 #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
685 #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
688 // Management Interface Register (MII)
690 #define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
691 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
692 #define MII_MDOE 0x0008 // MII Output Enable
693 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
694 #define MII_MDI 0x0002 // MII Input, pin MDI
695 #define MII_MDO 0x0001 // MII Output, pin MDO
700 /* ( hi: chip id low: rev # ) */
701 #define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
704 // Early RCV Register
706 /* this is NOT on SMC9192 */
707 #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
708 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
709 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
714 #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
722 #define CHIP_91100FD 8
723 #define CHIP_91111FD 9
725 static const char * chip_ids[ 16 ] = {
727 /* 3 */ "SMC91C90/91C92",
732 /* 8 */ "SMC91C100FD",
733 /* 9 */ "SMC91C11xFD",
739 . Receive status bits
741 #define RS_ALGNERR 0x8000
742 #define RS_BRODCAST 0x4000
743 #define RS_BADCRC 0x2000
744 #define RS_ODDFRAME 0x1000
745 #define RS_TOOLONG 0x0800
746 #define RS_TOOSHORT 0x0400
747 #define RS_MULTICAST 0x0001
748 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
753 * LAN83C183 == LAN91C111 Internal PHY
755 #define PHY_LAN83C183 0x0016f840
756 #define PHY_LAN83C180 0x02821c50
759 * PHY Register Addresses (LAN91C111 Internal PHY)
761 * Generic PHY registers can be found in <linux/mii.h>
763 * These phy registers are specific to our on-board phy.
766 // PHY Configuration Register 1
767 #define PHY_CFG1_REG 0x10
768 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
769 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
770 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
771 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
772 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
773 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
774 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
775 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
776 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
777 #define PHY_CFG1_TLVL_MASK 0x003C
778 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
781 // PHY Configuration Register 2
782 #define PHY_CFG2_REG 0x11
783 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
784 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
785 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
786 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
788 // PHY Status Output (and Interrupt status) Register
789 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
790 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
791 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
792 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
793 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
794 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
795 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
796 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
797 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
798 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
799 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
801 // PHY Interrupt/Status Mask Register
802 #define PHY_MASK_REG 0x13 // Interrupt Mask
803 // Uses the same bit definitions as PHY_INT_REG
807 * SMC91C96 ethernet config and status registers.
808 * These are in the "attribute" space.
811 #define ECOR_RESET 0x80
812 #define ECOR_LEVEL_IRQ 0x40
813 #define ECOR_WR_ATTRIB 0x04
814 #define ECOR_ENABLE 0x01
817 #define ECSR_IOIS8 0x20
818 #define ECSR_PWRDWN 0x04
819 #define ECSR_INT 0x02
821 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
825 * Macros to abstract register access according to the data bus
826 * capabilities. Please use those and not the in/out primitives.
827 * Note: the following macros do *not* select the bank -- this must
828 * be done separately as needed in the main code. The SMC_REG() macro
829 * only uses the bank argument for debugging purposes (when enabled).
831 * Note: despite inline functions being safer, everything leading to this
832 * should preferably be macros to let BUG() display the line number in
833 * the core source code since we're interested in the top call site
834 * not in any inline function location.
838 #define SMC_REG(lp, reg, bank) \
840 int __b = SMC_CURRENT_BANK(lp); \
841 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
842 pr_err("%s: bank reg screwed (0x%04x)\n", \
849 #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
853 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
854 * aligned to a 32 bit boundary. I tell you that does exist!
855 * Fortunately the affected register accesses can be easily worked around
856 * since we can write zeroes to the preceding 16 bits without adverse
857 * effects and use a 32-bit access.
859 * Enforce it on any 32-bit capable setup for now.
861 #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
863 #define SMC_GET_PN(lp) \
864 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
865 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
867 #define SMC_SET_PN(lp, x) \
869 if (SMC_MUST_ALIGN_WRITE(lp)) \
870 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
871 else if (SMC_8BIT(lp)) \
872 SMC_outb(x, ioaddr, PN_REG(lp)); \
874 SMC_outw(x, ioaddr, PN_REG(lp)); \
877 #define SMC_GET_AR(lp) \
878 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
879 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
881 #define SMC_GET_TXFIFO(lp) \
882 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
883 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
885 #define SMC_GET_RXFIFO(lp) \
886 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
887 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
889 #define SMC_GET_INT(lp) \
890 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
891 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
893 #define SMC_ACK_INT(lp, x) \
896 SMC_outb(x, ioaddr, INT_REG(lp)); \
898 unsigned long __flags; \
900 local_irq_save(__flags); \
901 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
902 SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
903 local_irq_restore(__flags); \
907 #define SMC_GET_INT_MASK(lp) \
908 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
909 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
911 #define SMC_SET_INT_MASK(lp, x) \
914 SMC_outb(x, ioaddr, IM_REG(lp)); \
916 SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
919 #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
921 #define SMC_SELECT_BANK(lp, x) \
923 if (SMC_MUST_ALIGN_WRITE(lp)) \
924 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
926 SMC_outw(x, ioaddr, BANK_SELECT); \
929 #define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
931 #define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
933 #define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
935 #define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
937 #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
939 #define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
941 #define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
943 #define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
945 #define SMC_GET_GP(lp) SMC_inw(ioaddr, GP_REG(lp))
947 #define SMC_SET_GP(lp, x) \
949 if (SMC_MUST_ALIGN_WRITE(lp)) \
950 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1)); \
952 SMC_outw(x, ioaddr, GP_REG(lp)); \
955 #define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
957 #define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
959 #define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
961 #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
963 #define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
965 #define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
967 #define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
969 #define SMC_SET_PTR(lp, x) \
971 if (SMC_MUST_ALIGN_WRITE(lp)) \
972 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
974 SMC_outw(x, ioaddr, PTR_REG(lp)); \
977 #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
979 #define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
981 #define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
983 #define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
985 #define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
987 #define SMC_SET_RPC(lp, x) \
989 if (SMC_MUST_ALIGN_WRITE(lp)) \
990 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
992 SMC_outw(x, ioaddr, RPC_REG(lp)); \
995 #define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
997 #define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
999 #ifndef SMC_GET_MAC_ADDR
1000 #define SMC_GET_MAC_ADDR(lp, addr) \
1003 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
1004 addr[0] = __v; addr[1] = __v >> 8; \
1005 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
1006 addr[2] = __v; addr[3] = __v >> 8; \
1007 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
1008 addr[4] = __v; addr[5] = __v >> 8; \
1012 #define SMC_SET_MAC_ADDR(lp, addr) \
1014 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1015 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1016 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1019 #define SMC_SET_MCAST(lp, x) \
1021 const unsigned char *mt = (x); \
1022 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1023 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1024 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1025 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1028 #define SMC_PUT_PKT_HDR(lp, status, length) \
1030 if (SMC_32BIT(lp)) \
1031 SMC_outl((status) | (length)<<16, ioaddr, \
1034 SMC_outw(status, ioaddr, DATA_REG(lp)); \
1035 SMC_outw(length, ioaddr, DATA_REG(lp)); \
1039 #define SMC_GET_PKT_HDR(lp, status, length) \
1041 if (SMC_32BIT(lp)) { \
1042 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1043 (status) = __val & 0xffff; \
1044 (length) = __val >> 16; \
1046 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1047 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
1051 #define SMC_PUSH_DATA(lp, p, l) \
1053 if (SMC_32BIT(lp)) { \
1054 void *__ptr = (p); \
1056 void __iomem *__ioaddr = ioaddr; \
1057 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1059 SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1062 if (SMC_CAN_USE_DATACS && lp->datacs) \
1063 __ioaddr = lp->datacs; \
1064 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1066 __ptr += (__len & ~3); \
1067 SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1069 } else if (SMC_16BIT(lp)) \
1070 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1071 else if (SMC_8BIT(lp)) \
1072 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
1075 #define SMC_PULL_DATA(lp, p, l) \
1077 if (SMC_32BIT(lp)) { \
1078 void *__ptr = (p); \
1080 void __iomem *__ioaddr = ioaddr; \
1081 if ((unsigned long)__ptr & 2) { \
1083 * We want 32bit alignment here. \
1084 * Since some buses perform a full \
1085 * 32bit fetch even for 16bit data \
1086 * we can't use SMC_inw() here. \
1087 * Back both source (on-chip) and \
1088 * destination pointers of 2 bytes. \
1089 * This is possible since the call to \
1090 * SMC_GET_PKT_HDR() already advanced \
1091 * the source pointer of 4 bytes, and \
1092 * the skb_reserve(skb, 2) advanced \
1093 * the destination pointer of 2 bytes. \
1098 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1100 if (SMC_CAN_USE_DATACS && lp->datacs) \
1101 __ioaddr = lp->datacs; \
1103 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1104 } else if (SMC_16BIT(lp)) \
1105 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1106 else if (SMC_8BIT(lp)) \
1107 SMC_insb(ioaddr, DATA_REG(lp), p, l); \
1110 #endif /* _SMC91X_H_ */