drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/gpio.h>
  33 #include <linux/of.h>
  34 #include <linux/of_mdio.h>
  35 #include <linux/of_net.h>
  36 #include <linux/of_device.h>
  37 #include <linux/if_vlan.h>
  38
  39 #include <linux/pinctrl/consumer.h>
  40
  41 #include "cpsw.h"
  42 #include "cpsw_ale.h"
  43 #include "cpts.h"
  44 #include "davinci_cpdma.h"
  45
  46 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  47                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  48                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  49                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  50                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  51                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  52                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  53                          NETIF_MSG_RX_STATUS)
  54
  55 #define cpsw_info(priv, type, format, ...)              \
  56 do {                                                            \
  57         if (netif_msg_##type(priv) && net_ratelimit())          \
  58                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  59 } while (0)
  60
  61 #define cpsw_err(priv, type, format, ...)               \
  62 do {                                                            \
  63         if (netif_msg_##type(priv) && net_ratelimit())          \
  64                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  65 } while (0)
  66
  67 #define cpsw_dbg(priv, type, format, ...)               \
  68 do {                                                            \
  69         if (netif_msg_##type(priv) && net_ratelimit())          \
  70                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  71 } while (0)
  72
  73 #define cpsw_notice(priv, type, format, ...)            \
  74 do {                                                            \
  75         if (netif_msg_##type(priv) && net_ratelimit())          \
  76                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  77 } while (0)
  78
  79 #define ALE_ALL_PORTS           0x7
  80
  81 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  82 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  83 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  84
  85 #define CPSW_VERSION_1          0x19010a
  86 #define CPSW_VERSION_2          0x19010c
  87 #define CPSW_VERSION_3          0x19010f
  88 #define CPSW_VERSION_4          0x190112
  89
  90 #define HOST_PORT_NUM           0
  91 #define SLIVER_SIZE             0x40
  92
  93 #define CPSW1_HOST_PORT_OFFSET  0x028
  94 #define CPSW1_SLAVE_OFFSET      0x050
  95 #define CPSW1_SLAVE_SIZE        0x040
  96 #define CPSW1_CPDMA_OFFSET      0x100
  97 #define CPSW1_STATERAM_OFFSET   0x200
  98 #define CPSW1_HW_STATS          0x400
  99 #define CPSW1_CPTS_OFFSET       0x500
 100 #define CPSW1_ALE_OFFSET        0x600
 101 #define CPSW1_SLIVER_OFFSET     0x700
 102
 103 #define CPSW2_HOST_PORT_OFFSET  0x108
 104 #define CPSW2_SLAVE_OFFSET      0x200
 105 #define CPSW2_SLAVE_SIZE        0x100
 106 #define CPSW2_CPDMA_OFFSET      0x800
 107 #define CPSW2_HW_STATS          0x900
 108 #define CPSW2_STATERAM_OFFSET   0xa00
 109 #define CPSW2_CPTS_OFFSET       0xc00
 110 #define CPSW2_ALE_OFFSET        0xd00
 111 #define CPSW2_SLIVER_OFFSET     0xd80
 112 #define CPSW2_BD_OFFSET         0x2000
 113
 114 #define CPDMA_RXTHRESH          0x0c0
 115 #define CPDMA_RXFREE            0x0e0
 116 #define CPDMA_TXHDP             0x00
 117 #define CPDMA_RXHDP             0x20
 118 #define CPDMA_TXCP              0x40
 119 #define CPDMA_RXCP              0x60
 120
 121 #define CPSW_POLL_WEIGHT        64
 122 #define CPSW_MIN_PACKET_SIZE    60
 123 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
 124
 125 #define RX_PRIORITY_MAPPING     0x76543210
 126 #define TX_PRIORITY_MAPPING     0x33221100
 127 #define CPDMA_TX_PRIORITY_MAP   0x76543210
 128
 129 #define CPSW_VLAN_AWARE         BIT(1)
 130 #define CPSW_ALE_VLAN_AWARE     1
 131
 132 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
 133 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
 134 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
 135
 136 #define CPSW_INTPACEEN          (0x3f << 16)
 137 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 138 #define CPSW_CMINTMAX_CNT       63
 139 #define CPSW_CMINTMIN_CNT       2
 140 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 141 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 142
 143 #define cpsw_slave_index(priv)                          \
 144                 ((priv->data.dual_emac) ? priv->emac_port :     \
 145                 priv->data.active_slave)
 146
 147 static int debug_level;
 148 module_param(debug_level, int, 0);
 149 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 150
 151 static int ale_ageout = 10;
 152 module_param(ale_ageout, int, 0);
 153 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 154
 155 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 156 module_param(rx_packet_max, int, 0);
 157 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 158
 159 struct cpsw_wr_regs {
 160         u32     id_ver;
 161         u32     soft_reset;
 162         u32     control;
 163         u32     int_control;
 164         u32     rx_thresh_en;
 165         u32     rx_en;
 166         u32     tx_en;
 167         u32     misc_en;
 168         u32     mem_allign1[8];
 169         u32     rx_thresh_stat;
 170         u32     rx_stat;
 171         u32     tx_stat;
 172         u32     misc_stat;
 173         u32     mem_allign2[8];
 174         u32     rx_imax;
 175         u32     tx_imax;
 176
 177 };
 178
 179 struct cpsw_ss_regs {
 180         u32     id_ver;
 181         u32     control;
 182         u32     soft_reset;
 183         u32     stat_port_en;
 184         u32     ptype;
 185         u32     soft_idle;
 186         u32     thru_rate;
 187         u32     gap_thresh;
 188         u32     tx_start_wds;
 189         u32     flow_control;
 190         u32     vlan_ltype;
 191         u32     ts_ltype;
 192         u32     dlr_ltype;
 193 };
 194
 195 /* CPSW_PORT_V1 */
 196 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 197 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 198 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 199 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 200 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 201 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 202 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 203 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 204
 205 /* CPSW_PORT_V2 */
 206 #define CPSW2_CONTROL       0x00 /* Control Register */
 207 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 208 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 209 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 210 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 211 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 212 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 213
 214 /* CPSW_PORT_V1 and V2 */
 215 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 216 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 217 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 218
 219 /* CPSW_PORT_V2 only */
 220 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 221 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 222 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 223 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 224 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 225 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 226 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 227 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 228
 229 /* Bit definitions for the CPSW2_CONTROL register */
 230 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 231 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 232 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 233 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 234 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 235 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 236 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 237 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 238 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 239 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 240 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
 241 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
 242 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 243 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 244 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 245 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 246 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 247
 248 #define CTRL_V2_TS_BITS \
 249         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 250          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
 251
 252 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
 253 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
 254 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
 255
 256
 257 #define CTRL_V3_TS_BITS \
 258         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 259          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
 260          TS_LTYPE1_EN)
 261
 262 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
 263 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
 264 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
 265
 266 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 267 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 268 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 269 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 270 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 271
 272 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 273 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 274
 275 /* Bit definitions for the CPSW1_TS_CTL register */
 276 #define CPSW_V1_TS_RX_EN                BIT(0)
 277 #define CPSW_V1_TS_TX_EN                BIT(4)
 278 #define CPSW_V1_MSG_TYPE_OFS            16
 279
 280 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 281 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 282
 283 struct cpsw_host_regs {
 284         u32     max_blks;
 285         u32     blk_cnt;
 286         u32     tx_in_ctl;
 287         u32     port_vlan;
 288         u32     tx_pri_map;
 289         u32     cpdma_tx_pri_map;
 290         u32     cpdma_rx_chan_map;
 291 };
 292
 293 struct cpsw_sliver_regs {
 294         u32     id_ver;
 295         u32     mac_control;
 296         u32     mac_status;
 297         u32     soft_reset;
 298         u32     rx_maxlen;
 299         u32     __reserved_0;
 300         u32     rx_pause;
 301         u32     tx_pause;
 302         u32     __reserved_1;
 303         u32     rx_pri_map;
 304 };
 305
 306 struct cpsw_hw_stats {
 307         u32     rxgoodframes;
 308         u32     rxbroadcastframes;
 309         u32     rxmulticastframes;
 310         u32     rxpauseframes;
 311         u32     rxcrcerrors;
 312         u32     rxaligncodeerrors;
 313         u32     rxoversizedframes;
 314         u32     rxjabberframes;
 315         u32     rxundersizedframes;
 316         u32     rxfragments;
 317         u32     __pad_0[2];
 318         u32     rxoctets;
 319         u32     txgoodframes;
 320         u32     txbroadcastframes;
 321         u32     txmulticastframes;
 322         u32     txpauseframes;
 323         u32     txdeferredframes;
 324         u32     txcollisionframes;
 325         u32     txsinglecollframes;
 326         u32     txmultcollframes;
 327         u32     txexcessivecollisions;
 328         u32     txlatecollisions;
 329         u32     txunderrun;
 330         u32     txcarriersenseerrors;
 331         u32     txoctets;
 332         u32     octetframes64;
 333         u32     octetframes65t127;
 334         u32     octetframes128t255;
 335         u32     octetframes256t511;
 336         u32     octetframes512t1023;
 337         u32     octetframes1024tup;
 338         u32     netoctets;
 339         u32     rxsofoverruns;
 340         u32     rxmofoverruns;
 341         u32     rxdmaoverruns;
 342 };
 343
 344 struct cpsw_slave {
 345         void __iomem                    *regs;
 346         struct cpsw_sliver_regs __iomem *sliver;
 347         int                             slave_num;
 348         u32                             mac_control;
 349         struct cpsw_slave_data          *data;
 350         struct phy_device               *phy;
 351         struct net_device               *ndev;
 352         u32                             port_vlan;
 353         u32                             open_stat;
 354 };
 355
 356 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 357 {
 358         return __raw_readl(slave->regs + offset);
 359 }
 360
 361 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 362 {
 363         __raw_writel(val, slave->regs + offset);
 364 }
 365
 366 struct cpsw_priv {
 367         spinlock_t                      lock;
 368         struct platform_device          *pdev;
 369         struct net_device               *ndev;
 370         struct device_node              *phy_node;
 371         struct napi_struct              napi_rx;
 372         struct napi_struct              napi_tx;
 373         struct device                   *dev;
 374         struct cpsw_platform_data       data;
 375         struct cpsw_ss_regs __iomem     *regs;
 376         struct cpsw_wr_regs __iomem     *wr_regs;
 377         u8 __iomem                      *hw_stats;
 378         struct cpsw_host_regs __iomem   *host_port_regs;
 379         u32                             msg_enable;
 380         u32                             version;
 381         u32                             coal_intvl;
 382         u32                             bus_freq_mhz;
 383         int                             rx_packet_max;
 384         int                             host_port;
 385         struct clk                      *clk;
 386         u8                              mac_addr[ETH_ALEN];
 387         struct cpsw_slave               *slaves;
 388         struct cpdma_ctlr               *dma;
 389         struct cpdma_chan               *txch, *rxch;
 390         struct cpsw_ale                 *ale;
 391         bool                            rx_pause;
 392         bool                            tx_pause;
 393         bool                            quirk_irq;
 394         bool                            rx_irq_disabled;
 395         bool                            tx_irq_disabled;
 396         /* snapshot of IRQ numbers */
 397         u32 irqs_table[4];
 398         u32 num_irqs;
 399         struct cpts *cpts;
 400         u32 emac_port;
 401 };
 402
 403 struct cpsw_stats {
 404         char stat_string[ETH_GSTRING_LEN];
 405         int type;
 406         int sizeof_stat;
 407         int stat_offset;
 408 };
 409
 410 enum {
 411         CPSW_STATS,
 412         CPDMA_RX_STATS,
 413         CPDMA_TX_STATS,
 414 };
 415
 416 #define CPSW_STAT(m)            CPSW_STATS,                             \
 417                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
 418                                 offsetof(struct cpsw_hw_stats, m)
 419 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
 420                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 421                                 offsetof(struct cpdma_chan_stats, m)
 422 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
 423                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 424                                 offsetof(struct cpdma_chan_stats, m)
 425
 426 static const struct cpsw_stats cpsw_gstrings_stats[] = {
 427         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
 428         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
 429         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
 430         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
 431         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
 432         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
 433         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
 434         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
 435         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
 436         { "Rx Fragments", CPSW_STAT(rxfragments) },
 437         { "Rx Octets", CPSW_STAT(rxoctets) },
 438         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
 439         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
 440         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
 441         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
 442         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
 443         { "Collisions", CPSW_STAT(txcollisionframes) },
 444         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
 445         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
 446         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
 447         { "Late Collisions", CPSW_STAT(txlatecollisions) },
 448         { "Tx Underrun", CPSW_STAT(txunderrun) },
 449         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
 450         { "Tx Octets", CPSW_STAT(txoctets) },
 451         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
 452         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
 453         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
 454         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
 455         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
 456         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
 457         { "Net Octets", CPSW_STAT(netoctets) },
 458         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
 459         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
 460         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
 461         { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
 462         { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
 463         { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
 464         { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
 465         { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
 466         { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
 467         { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
 468         { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
 469         { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
 470         { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
 471         { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
 472         { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
 473         { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
 474         { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
 475         { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
 476         { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
 477         { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
 478         { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
 479         { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
 480         { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
 481         { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
 482         { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
 483         { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
 484         { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
 485         { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
 486         { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
 487 };
 488
 489 #define CPSW_STATS_LEN  ARRAY_SIZE(cpsw_gstrings_stats)
 490
 491 #define napi_to_priv(napi)      container_of(napi, struct cpsw_priv, napi)
 492 #define for_each_slave(priv, func, arg...)                              \
 493         do {                                                            \
 494                 struct cpsw_slave *slave;                               \
 495                 int n;                                                  \
 496                 if (priv->data.dual_emac)                               \
 497                         (func)((priv)->slaves + priv->emac_port, ##arg);\
 498                 else                                                    \
 499                         for (n = (priv)->data.slaves,                   \
 500                                         slave = (priv)->slaves;         \
 501                                         n; n--)                         \
 502                                 (func)(slave++, ##arg);                 \
 503         } while (0)
 504 #define cpsw_get_slave_ndev(priv, __slave_no__)                         \
 505         ((__slave_no__ < priv->data.slaves) ?                           \
 506                 priv->slaves[__slave_no__].ndev : NULL)
 507 #define cpsw_get_slave_priv(priv, __slave_no__)                         \
 508         (((__slave_no__ < priv->data.slaves) &&                         \
 509                 (priv->slaves[__slave_no__].ndev)) ?                    \
 510                 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL)    \
 511
 512 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb)         \
 513         do {                                                            \
 514                 if (!priv->data.dual_emac)                              \
 515                         break;                                          \
 516                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
 517                         ndev = cpsw_get_slave_ndev(priv, 0);            \
 518                         priv = netdev_priv(ndev);                       \
 519                         skb->dev = ndev;                                \
 520                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
 521                         ndev = cpsw_get_slave_ndev(priv, 1);            \
 522                         priv = netdev_priv(ndev);                       \
 523                         skb->dev = ndev;                                \
 524                 }                                                       \
 525         } while (0)
 526 #define cpsw_add_mcast(priv, addr)                                      \
 527         do {                                                            \
 528                 if (priv->data.dual_emac) {                             \
 529                         struct cpsw_slave *slave = priv->slaves +       \
 530                                                 priv->emac_port;        \
 531                         int slave_port = cpsw_get_slave_port(priv,      \
 532                                                 slave->slave_num);      \
 533                         cpsw_ale_add_mcast(priv->ale, addr,             \
 534                                 1 << slave_port | 1 << priv->host_port, \
 535                                 ALE_VLAN, slave->port_vlan, 0);         \
 536                 } else {                                                \
 537                         cpsw_ale_add_mcast(priv->ale, addr,             \
 538                                 ALE_ALL_PORTS << priv->host_port,       \
 539                                 0, 0, 0);                               \
 540                 }                                                       \
 541         } while (0)
 542
 543 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 544 {
 545         if (priv->host_port == 0)
 546                 return slave_num + 1;
 547         else
 548                 return slave_num;
 549 }
 550
 551 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
 552 {
 553         struct cpsw_priv *priv = netdev_priv(ndev);
 554         struct cpsw_ale *ale = priv->ale;
 555         int i;
 556
 557         if (priv->data.dual_emac) {
 558                 bool flag = false;
 559
 560                 /* Enabling promiscuous mode for one interface will be
 561                  * common for both the interface as the interface shares
 562                  * the same hardware resource.
 563                  */
 564                 for (i = 0; i < priv->data.slaves; i++)
 565                         if (priv->slaves[i].ndev->flags & IFF_PROMISC)
 566                                 flag = true;
 567
 568                 if (!enable && flag) {
 569                         enable = true;
 570                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
 571                 }
 572
 573                 if (enable) {
 574                         /* Enable Bypass */
 575                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
 576
 577                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 578                 } else {
 579                         /* Disable Bypass */
 580                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
 581                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 582                 }
 583         } else {
 584                 if (enable) {
 585                         unsigned long timeout = jiffies + HZ;
 586
 587                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
 588                         for (i = 0; i <= priv->data.slaves; i++) {
 589                                 cpsw_ale_control_set(ale, i,
 590                                                      ALE_PORT_NOLEARN, 1);
 591                                 cpsw_ale_control_set(ale, i,
 592                                                      ALE_PORT_NO_SA_UPDATE, 1);
 593                         }
 594
 595                         /* Clear All Untouched entries */
 596                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 597                         do {
 598                                 cpu_relax();
 599                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
 600                                         break;
 601                         } while (time_after(timeout, jiffies));
 602                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 603
 604                         /* Clear all mcast from ALE */
 605                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<
 606                                                  priv->host_port, -1);
 607
 608                         /* Flood All Unicast Packets to Host port */
 609                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
 610                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 611                 } else {
 612                         /* Don't Flood All Unicast Packets to Host port */
 613                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
 614
 615                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
 616                         for (i = 0; i <= priv->data.slaves; i++) {
 617                                 cpsw_ale_control_set(ale, i,
 618                                                      ALE_PORT_NOLEARN, 0);
 619                                 cpsw_ale_control_set(ale, i,
 620                                                      ALE_PORT_NO_SA_UPDATE, 0);
 621                         }
 622                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 623                 }
 624         }
 625 }
 626
 627 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 628 {
 629         struct cpsw_priv *priv = netdev_priv(ndev);
 630         int vid;
 631
 632         if (priv->data.dual_emac)
 633                 vid = priv->slaves[priv->emac_port].port_vlan;
 634         else
 635                 vid = priv->data.default_vlan;
 636
 637         if (ndev->flags & IFF_PROMISC) {
 638                 /* Enable promiscuous mode */
 639                 cpsw_set_promiscious(ndev, true);
 640                 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
 641                 return;
 642         } else {
 643                 /* Disable promiscuous mode */
 644                 cpsw_set_promiscious(ndev, false);
 645         }
 646
 647         /* Restore allmulti on vlans if necessary */
 648         cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
 649
 650         /* Clear all mcast from ALE */
 651         cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port,
 652                                  vid);
 653
 654         if (!netdev_mc_empty(ndev)) {
 655                 struct netdev_hw_addr *ha;
 656
 657                 /* program multicast address list into ALE register */
 658                 netdev_for_each_mc_addr(ha, ndev) {
 659                         cpsw_add_mcast(priv, (u8 *)ha->addr);
 660                 }
 661         }
 662 }
 663
 664 static void cpsw_intr_enable(struct cpsw_priv *priv)
 665 {
 666         __raw_writel(0xFF, &priv->wr_regs->tx_en);
 667         __raw_writel(0xFF, &priv->wr_regs->rx_en);
 668
 669         cpdma_ctlr_int_ctrl(priv->dma, true);
 670         return;
 671 }
 672
 673 static void cpsw_intr_disable(struct cpsw_priv *priv)
 674 {
 675         __raw_writel(0, &priv->wr_regs->tx_en);
 676         __raw_writel(0, &priv->wr_regs->rx_en);
 677
 678         cpdma_ctlr_int_ctrl(priv->dma, false);
 679         return;
 680 }
 681
 682 static void cpsw_tx_handler(void *token, int len, int status)
 683 {
 684         struct sk_buff          *skb = token;
 685         struct net_device       *ndev = skb->dev;
 686         struct cpsw_priv        *priv = netdev_priv(ndev);
 687
 688         /* Check whether the queue is stopped due to stalled tx dma, if the
 689          * queue is stopped then start the queue as we have free desc for tx
 690          */
 691         if (unlikely(netif_queue_stopped(ndev)))
 692                 netif_wake_queue(ndev);
 693         cpts_tx_timestamp(priv->cpts, skb);
 694         ndev->stats.tx_packets++;
 695         ndev->stats.tx_bytes += len;
 696         dev_kfree_skb_any(skb);
 697 }
 698
 699 static void cpsw_rx_handler(void *token, int len, int status)
 700 {
 701         struct sk_buff          *skb = token;
 702         struct sk_buff          *new_skb;
 703         struct net_device       *ndev = skb->dev;
 704         struct cpsw_priv        *priv = netdev_priv(ndev);
 705         int                     ret = 0;
 706
 707         cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
 708
 709         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
 710                 bool ndev_status = false;
 711                 struct cpsw_slave *slave = priv->slaves;
 712                 int n;
 713
 714                 if (priv->data.dual_emac) {
 715                         /* In dual emac mode check for all interfaces */
 716                         for (n = priv->data.slaves; n; n--, slave++)
 717                                 if (netif_running(slave->ndev))
 718                                         ndev_status = true;
 719                 }
 720
 721                 if (ndev_status && (status >= 0)) {
 722                         /* The packet received is for the interface which
 723                          * is already down and the other interface is up
 724                          * and running, instead of freeing which results
 725                          * in reducing of the number of rx descriptor in
 726                          * DMA engine, requeue skb back to cpdma.
 727                          */
 728                         new_skb = skb;
 729                         goto requeue;
 730                 }
 731
 732                 /* the interface is going down, skbs are purged */
 733                 dev_kfree_skb_any(skb);
 734                 return;
 735         }
 736
 737         new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
 738         if (new_skb) {
 739                 skb_put(skb, len);
 740                 cpts_rx_timestamp(priv->cpts, skb);
 741                 skb->protocol = eth_type_trans(skb, ndev);
 742                 netif_receive_skb(skb);
 743                 ndev->stats.rx_bytes += len;
 744                 ndev->stats.rx_packets++;
 745         } else {
 746                 ndev->stats.rx_dropped++;
 747                 new_skb = skb;
 748         }
 749
 750 requeue:
 751         ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
 752                         skb_tailroom(new_skb), 0);
 753         if (WARN_ON(ret < 0))
 754                 dev_kfree_skb_any(new_skb);
 755 }
 756
 757 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
 758 {
 759         struct cpsw_priv *priv = dev_id;
 760
 761         writel(0, &priv->wr_regs->tx_en);
 762         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
 763
 764         if (priv->quirk_irq) {
 765                 disable_irq_nosync(priv->irqs_table[1]);
 766                 priv->tx_irq_disabled = true;
 767         }
 768
 769         napi_schedule(&priv->napi_tx);
 770         return IRQ_HANDLED;
 771 }
 772
 773 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
 774 {
 775         struct cpsw_priv *priv = dev_id;
 776
 777         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
 778         writel(0, &priv->wr_regs->rx_en);
 779
 780         if (priv->quirk_irq) {
 781                 disable_irq_nosync(priv->irqs_table[0]);
 782                 priv->rx_irq_disabled = true;
 783         }
 784
 785         napi_schedule(&priv->napi_rx);
 786         return IRQ_HANDLED;
 787 }
 788
 789 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
 790 {
 791         struct cpsw_priv        *priv = napi_to_priv(napi_tx);
 792         int                     num_tx;
 793
 794         num_tx = cpdma_chan_process(priv->txch, budget);
 795         if (num_tx < budget) {
 796                 napi_complete(napi_tx);
 797                 writel(0xff, &priv->wr_regs->tx_en);
 798                 if (priv->quirk_irq && priv->tx_irq_disabled) {
 799                         priv->tx_irq_disabled = false;
 800                         enable_irq(priv->irqs_table[1]);
 801                 }
 802         }
 803
 804         if (num_tx)
 805                 cpsw_dbg(priv, intr, "poll %d tx pkts\n", num_tx);
 806
 807         return num_tx;
 808 }
 809
 810 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
 811 {
 812         struct cpsw_priv        *priv = napi_to_priv(napi_rx);
 813         int                     num_rx;
 814
 815         num_rx = cpdma_chan_process(priv->rxch, budget);
 816         if (num_rx < budget) {
 817                 napi_complete(napi_rx);
 818                 writel(0xff, &priv->wr_regs->rx_en);
 819                 if (priv->quirk_irq && priv->rx_irq_disabled) {
 820                         priv->rx_irq_disabled = false;
 821                         enable_irq(priv->irqs_table[0]);
 822                 }
 823         }
 824
 825         if (num_rx)
 826                 cpsw_dbg(priv, intr, "poll %d rx pkts\n", num_rx);
 827
 828         return num_rx;
 829 }
 830
 831 static inline void soft_reset(const char *module, void __iomem *reg)
 832 {
 833         unsigned long timeout = jiffies + HZ;
 834
 835         __raw_writel(1, reg);
 836         do {
 837                 cpu_relax();
 838         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
 839
 840         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
 841 }
 842
 843 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 844                          ((mac)[2] << 16) | ((mac)[3] << 24))
 845 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 846
 847 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 848                                struct cpsw_priv *priv)
 849 {
 850         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
 851         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
 852 }
 853
 854 static void _cpsw_adjust_link(struct cpsw_slave *slave,
 855                               struct cpsw_priv *priv, bool *link)
 856 {
 857         struct phy_device       *phy = slave->phy;
 858         u32                     mac_control = 0;
 859         u32                     slave_port;
 860
 861         if (!phy)
 862                 return;
 863
 864         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 865
 866         if (phy->link) {
 867                 mac_control = priv->data.mac_control;
 868
 869                 /* enable forwarding */
 870                 cpsw_ale_control_set(priv->ale, slave_port,
 871                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 872
 873                 if (phy->speed == 1000)
 874                         mac_control |= BIT(7);  /* GIGABITEN    */
 875                 if (phy->duplex)
 876                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
 877
 878                 /* set speed_in input in case RMII mode is used in 100Mbps */
 879                 if (phy->speed == 100)
 880                         mac_control |= BIT(15);
 881                 else if (phy->speed == 10)
 882                         mac_control |= BIT(18); /* In Band mode */
 883
 884                 if (priv->rx_pause)
 885                         mac_control |= BIT(3);
 886
 887                 if (priv->tx_pause)
 888                         mac_control |= BIT(4);
 889
 890                 *link = true;
 891         } else {
 892                 mac_control = 0;
 893                 /* disable forwarding */
 894                 cpsw_ale_control_set(priv->ale, slave_port,
 895                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
 896         }
 897
 898         if (mac_control != slave->mac_control) {
 899                 phy_print_status(phy);
 900                 __raw_writel(mac_control, &slave->sliver->mac_control);
 901         }
 902
 903         slave->mac_control = mac_control;
 904 }
 905
 906 static void cpsw_adjust_link(struct net_device *ndev)
 907 {
 908         struct cpsw_priv        *priv = netdev_priv(ndev);
 909         bool                    link = false;
 910
 911         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
 912
 913         if (link) {
 914                 netif_carrier_on(ndev);
 915                 if (netif_running(ndev))
 916                         netif_wake_queue(ndev);
 917         } else {
 918                 netif_carrier_off(ndev);
 919                 netif_stop_queue(ndev);
 920         }
 921 }
 922
 923 static int cpsw_get_coalesce(struct net_device *ndev,
 924                                 struct ethtool_coalesce *coal)
 925 {
 926         struct cpsw_priv *priv = netdev_priv(ndev);
 927
 928         coal->rx_coalesce_usecs = priv->coal_intvl;
 929         return 0;
 930 }
 931
 932 static int cpsw_set_coalesce(struct net_device *ndev,
 933                                 struct ethtool_coalesce *coal)
 934 {
 935         struct cpsw_priv *priv = netdev_priv(ndev);
 936         u32 int_ctrl;
 937         u32 num_interrupts = 0;
 938         u32 prescale = 0;
 939         u32 addnl_dvdr = 1;
 940         u32 coal_intvl = 0;
 941
 942         coal_intvl = coal->rx_coalesce_usecs;
 943
 944         int_ctrl =  readl(&priv->wr_regs->int_control);
 945         prescale = priv->bus_freq_mhz * 4;
 946
 947         if (!coal->rx_coalesce_usecs) {
 948                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
 949                 goto update_return;
 950         }
 951
 952         if (coal_intvl < CPSW_CMINTMIN_INTVL)
 953                 coal_intvl = CPSW_CMINTMIN_INTVL;
 954
 955         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
 956                 /* Interrupt pacer works with 4us Pulse, we can
 957                  * throttle further by dilating the 4us pulse.
 958                  */
 959                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
 960
 961                 if (addnl_dvdr > 1) {
 962                         prescale *= addnl_dvdr;
 963                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
 964                                 coal_intvl = (CPSW_CMINTMAX_INTVL
 965                                                 * addnl_dvdr);
 966                 } else {
 967                         addnl_dvdr = 1;
 968                         coal_intvl = CPSW_CMINTMAX_INTVL;
 969                 }
 970         }
 971
 972         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
 973         writel(num_interrupts, &priv->wr_regs->rx_imax);
 974         writel(num_interrupts, &priv->wr_regs->tx_imax);
 975
 976         int_ctrl |= CPSW_INTPACEEN;
 977         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
 978         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
 979
 980 update_return:
 981         writel(int_ctrl, &priv->wr_regs->int_control);
 982
 983         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
 984         if (priv->data.dual_emac) {
 985                 int i;
 986
 987                 for (i = 0; i < priv->data.slaves; i++) {
 988                         priv = netdev_priv(priv->slaves[i].ndev);
 989                         priv->coal_intvl = coal_intvl;
 990                 }
 991         } else {
 992                 priv->coal_intvl = coal_intvl;
 993         }
 994
 995         return 0;
 996 }
 997
 998 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
 999 {
1000         switch (sset) {
1001         case ETH_SS_STATS:
1002                 return CPSW_STATS_LEN;
1003         default:
1004                 return -EOPNOTSUPP;
1005         }
1006 }
1007
1008 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1009 {
1010         u8 *p = data;
1011         int i;
1012
1013         switch (stringset) {
1014         case ETH_SS_STATS:
1015                 for (i = 0; i < CPSW_STATS_LEN; i++) {
1016                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
1017                                ETH_GSTRING_LEN);
1018                         p += ETH_GSTRING_LEN;
1019                 }
1020                 break;
1021         }
1022 }
1023
1024 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1025                                     struct ethtool_stats *stats, u64 *data)
1026 {
1027         struct cpsw_priv *priv = netdev_priv(ndev);
1028         struct cpdma_chan_stats rx_stats;
1029         struct cpdma_chan_stats tx_stats;
1030         u32 val;
1031         u8 *p;
1032         int i;
1033
1034         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1035         cpdma_chan_get_stats(priv->rxch, &rx_stats);
1036         cpdma_chan_get_stats(priv->txch, &tx_stats);
1037
1038         for (i = 0; i < CPSW_STATS_LEN; i++) {
1039                 switch (cpsw_gstrings_stats[i].type) {
1040                 case CPSW_STATS:
1041                         val = readl(priv->hw_stats +
1042                                     cpsw_gstrings_stats[i].stat_offset);
1043                         data[i] = val;
1044                         break;
1045
1046                 case CPDMA_RX_STATS:
1047                         p = (u8 *)&rx_stats +
1048                                 cpsw_gstrings_stats[i].stat_offset;
1049                         data[i] = *(u32 *)p;
1050                         break;
1051
1052                 case CPDMA_TX_STATS:
1053                         p = (u8 *)&tx_stats +
1054                                 cpsw_gstrings_stats[i].stat_offset;
1055                         data[i] = *(u32 *)p;
1056                         break;
1057                 }
1058         }
1059 }
1060
1061 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1062 {
1063         u32 i;
1064         u32 usage_count = 0;
1065
1066         if (!priv->data.dual_emac)
1067                 return 0;
1068
1069         for (i = 0; i < priv->data.slaves; i++)
1070                 if (priv->slaves[i].open_stat)
1071                         usage_count++;
1072
1073         return usage_count;
1074 }
1075
1076 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1077                         struct cpsw_priv *priv, struct sk_buff *skb)
1078 {
1079         if (!priv->data.dual_emac)
1080                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1081                                   skb->len, 0);
1082
1083         if (ndev == cpsw_get_slave_ndev(priv, 0))
1084                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1085                                   skb->len, 1);
1086         else
1087                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1088                                   skb->len, 2);
1089 }
1090
1091 static inline void cpsw_add_dual_emac_def_ale_entries(
1092                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1093                 u32 slave_port)
1094 {
1095         u32 port_mask = 1 << slave_port | 1 << priv->host_port;
1096
1097         if (priv->version == CPSW_VERSION_1)
1098                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1099         else
1100                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1101         cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1102                           port_mask, port_mask, 0);
1103         cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1104                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1105         cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1106                 priv->host_port, ALE_VLAN | ALE_SECURE, slave->port_vlan);
1107 }
1108
1109 static void soft_reset_slave(struct cpsw_slave *slave)
1110 {
1111         char name[32];
1112
1113         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1114         soft_reset(name, &slave->sliver->soft_reset);
1115 }
1116
1117 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1118 {
1119         u32 slave_port;
1120
1121         soft_reset_slave(slave);
1122
1123         /* setup priority mapping */
1124         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1125
1126         switch (priv->version) {
1127         case CPSW_VERSION_1:
1128                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1129                 break;
1130         case CPSW_VERSION_2:
1131         case CPSW_VERSION_3:
1132         case CPSW_VERSION_4:
1133                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1134                 break;
1135         }
1136
1137         /* setup max packet size, and mac address */
1138         __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1139         cpsw_set_slave_mac(slave, priv);
1140
1141         slave->mac_control = 0; /* no link yet */
1142
1143         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1144
1145         if (priv->data.dual_emac)
1146                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1147         else
1148                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1149                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1150
1151         if (priv->phy_node)
1152                 slave->phy = of_phy_connect(priv->ndev, priv->phy_node,
1153                                  &cpsw_adjust_link, 0, slave->data->phy_if);
1154         else
1155                 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1156                                  &cpsw_adjust_link, slave->data->phy_if);
1157         if (IS_ERR(slave->phy)) {
1158                 dev_err(priv->dev, "phy %s not found on slave %d\n",
1159                         slave->data->phy_id, slave->slave_num);
1160                 slave->phy = NULL;
1161         } else {
1162                 dev_info(priv->dev, "phy found : id is : 0x%x\n",
1163                          slave->phy->phy_id);
1164                 phy_start(slave->phy);
1165
1166                 /* Configure GMII_SEL register */
1167                 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
1168                              slave->slave_num);
1169         }
1170 }
1171
1172 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1173 {
1174         const int vlan = priv->data.default_vlan;
1175         const int port = priv->host_port;
1176         u32 reg;
1177         int i;
1178         int unreg_mcast_mask;
1179
1180         reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1181                CPSW2_PORT_VLAN;
1182
1183         writel(vlan, &priv->host_port_regs->port_vlan);
1184
1185         for (i = 0; i < priv->data.slaves; i++)
1186                 slave_write(priv->slaves + i, vlan, reg);
1187
1188         if (priv->ndev->flags & IFF_ALLMULTI)
1189                 unreg_mcast_mask = ALE_ALL_PORTS;
1190         else
1191                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1192
1193         cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1194                           ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1195                           unreg_mcast_mask << port);
1196 }
1197
1198 static void cpsw_init_host_port(struct cpsw_priv *priv)
1199 {
1200         u32 control_reg;
1201         u32 fifo_mode;
1202
1203         /* soft reset the controller and initialize ale */
1204         soft_reset("cpsw", &priv->regs->soft_reset);
1205         cpsw_ale_start(priv->ale);
1206
1207         /* switch to vlan unaware mode */
1208         cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1209                              CPSW_ALE_VLAN_AWARE);
1210         control_reg = readl(&priv->regs->control);
1211         control_reg |= CPSW_VLAN_AWARE;
1212         writel(control_reg, &priv->regs->control);
1213         fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1214                      CPSW_FIFO_NORMAL_MODE;
1215         writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
1216
1217         /* setup host port priority mapping */
1218         __raw_writel(CPDMA_TX_PRIORITY_MAP,
1219                      &priv->host_port_regs->cpdma_tx_pri_map);
1220         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1221
1222         cpsw_ale_control_set(priv->ale, priv->host_port,
1223                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1224
1225         if (!priv->data.dual_emac) {
1226                 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1227                                    0, 0);
1228                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1229                                    1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1230         }
1231 }
1232
1233 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1234 {
1235         u32 slave_port;
1236
1237         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1238
1239         if (!slave->phy)
1240                 return;
1241         phy_stop(slave->phy);
1242         phy_disconnect(slave->phy);
1243         slave->phy = NULL;
1244         cpsw_ale_control_set(priv->ale, slave_port,
1245                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1246 }
1247
1248 static int cpsw_ndo_open(struct net_device *ndev)
1249 {
1250         struct cpsw_priv *priv = netdev_priv(ndev);
1251         int i, ret;
1252         u32 reg;
1253
1254         if (!cpsw_common_res_usage_state(priv))
1255                 cpsw_intr_disable(priv);
1256         netif_carrier_off(ndev);
1257
1258         pm_runtime_get_sync(&priv->pdev->dev);
1259
1260         reg = priv->version;
1261
1262         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1263                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1264                  CPSW_RTL_VERSION(reg));
1265
1266         /* initialize host and slave ports */
1267         if (!cpsw_common_res_usage_state(priv))
1268                 cpsw_init_host_port(priv);
1269         for_each_slave(priv, cpsw_slave_open, priv);
1270
1271         /* Add default VLAN */
1272         if (!priv->data.dual_emac)
1273                 cpsw_add_default_vlan(priv);
1274         else
1275                 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1276                                   ALE_ALL_PORTS << priv->host_port,
1277                                   ALE_ALL_PORTS << priv->host_port, 0, 0);
1278
1279         if (!cpsw_common_res_usage_state(priv)) {
1280                 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1281
1282                 /* setup tx dma to fixed prio and zero offset */
1283                 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1284                 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1285
1286                 /* disable priority elevation */
1287                 __raw_writel(0, &priv->regs->ptype);
1288
1289                 /* enable statistics collection only on all ports */
1290                 __raw_writel(0x7, &priv->regs->stat_port_en);
1291
1292                 /* Enable internal fifo flow control */
1293                 writel(0x7, &priv->regs->flow_control);
1294
1295                 napi_enable(&priv_sl0->napi_rx);
1296                 napi_enable(&priv_sl0->napi_tx);
1297
1298                 if (priv_sl0->tx_irq_disabled) {
1299                         priv_sl0->tx_irq_disabled = false;
1300                         enable_irq(priv->irqs_table[1]);
1301                 }
1302
1303                 if (priv_sl0->rx_irq_disabled) {
1304                         priv_sl0->rx_irq_disabled = false;
1305                         enable_irq(priv->irqs_table[0]);
1306                 }
1307
1308                 if (WARN_ON(!priv->data.rx_descs))
1309                         priv->data.rx_descs = 128;
1310
1311                 for (i = 0; i < priv->data.rx_descs; i++) {
1312                         struct sk_buff *skb;
1313
1314                         ret = -ENOMEM;
1315                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1316                                         priv->rx_packet_max, GFP_KERNEL);
1317                         if (!skb)
1318                                 goto err_cleanup;
1319                         ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
1320                                         skb_tailroom(skb), 0);
1321                         if (ret < 0) {
1322                                 kfree_skb(skb);
1323                                 goto err_cleanup;
1324                         }
1325                 }
1326                 /* continue even if we didn't manage to submit all
1327                  * receive descs
1328                  */
1329                 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
1330
1331                 if (cpts_register(&priv->pdev->dev, priv->cpts,
1332                                   priv->data.cpts_clock_mult,
1333                                   priv->data.cpts_clock_shift))
1334                         dev_err(priv->dev, "error registering cpts device\n");
1335
1336         }
1337
1338         /* Enable Interrupt pacing if configured */
1339         if (priv->coal_intvl != 0) {
1340                 struct ethtool_coalesce coal;
1341
1342                 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1343                 cpsw_set_coalesce(ndev, &coal);
1344         }
1345
1346         cpdma_ctlr_start(priv->dma);
1347         cpsw_intr_enable(priv);
1348
1349         if (priv->data.dual_emac)
1350                 priv->slaves[priv->emac_port].open_stat = true;
1351         return 0;
1352
1353 err_cleanup:
1354         cpdma_ctlr_stop(priv->dma);
1355         for_each_slave(priv, cpsw_slave_stop, priv);
1356         pm_runtime_put_sync(&priv->pdev->dev);
1357         netif_carrier_off(priv->ndev);
1358         return ret;
1359 }
1360
1361 static int cpsw_ndo_stop(struct net_device *ndev)
1362 {
1363         struct cpsw_priv *priv = netdev_priv(ndev);
1364
1365         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1366         netif_stop_queue(priv->ndev);
1367         netif_carrier_off(priv->ndev);
1368
1369         if (cpsw_common_res_usage_state(priv) <= 1) {
1370                 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1371
1372                 napi_disable(&priv_sl0->napi_rx);
1373                 napi_disable(&priv_sl0->napi_tx);
1374                 cpts_unregister(priv->cpts);
1375                 cpsw_intr_disable(priv);
1376                 cpdma_ctlr_stop(priv->dma);
1377                 cpsw_ale_stop(priv->ale);
1378         }
1379         for_each_slave(priv, cpsw_slave_stop, priv);
1380         pm_runtime_put_sync(&priv->pdev->dev);
1381         if (priv->data.dual_emac)
1382                 priv->slaves[priv->emac_port].open_stat = false;
1383         return 0;
1384 }
1385
1386 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1387                                        struct net_device *ndev)
1388 {
1389         struct cpsw_priv *priv = netdev_priv(ndev);
1390         int ret;
1391
1392         ndev->trans_start = jiffies;
1393
1394         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1395                 cpsw_err(priv, tx_err, "packet pad failed\n");
1396                 ndev->stats.tx_dropped++;
1397                 return NETDEV_TX_OK;
1398         }
1399
1400         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1401                                 priv->cpts->tx_enable)
1402                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1403
1404         skb_tx_timestamp(skb);
1405
1406         ret = cpsw_tx_packet_submit(ndev, priv, skb);
1407         if (unlikely(ret != 0)) {
1408                 cpsw_err(priv, tx_err, "desc submit failed\n");
1409                 goto fail;
1410         }
1411
1412         /* If there is no more tx desc left free then we need to
1413          * tell the kernel to stop sending us tx frames.
1414          */
1415         if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1416                 netif_stop_queue(ndev);
1417
1418         return NETDEV_TX_OK;
1419 fail:
1420         ndev->stats.tx_dropped++;
1421         netif_stop_queue(ndev);
1422         return NETDEV_TX_BUSY;
1423 }
1424
1425 #ifdef CONFIG_TI_CPTS
1426
1427 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1428 {
1429         struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1430         u32 ts_en, seq_id;
1431
1432         if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1433                 slave_write(slave, 0, CPSW1_TS_CTL);
1434                 return;
1435         }
1436
1437         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1438         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1439
1440         if (priv->cpts->tx_enable)
1441                 ts_en |= CPSW_V1_TS_TX_EN;
1442
1443         if (priv->cpts->rx_enable)
1444                 ts_en |= CPSW_V1_TS_RX_EN;
1445
1446         slave_write(slave, ts_en, CPSW1_TS_CTL);
1447         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1448 }
1449
1450 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1451 {
1452         struct cpsw_slave *slave;
1453         u32 ctrl, mtype;
1454
1455         if (priv->data.dual_emac)
1456                 slave = &priv->slaves[priv->emac_port];
1457         else
1458                 slave = &priv->slaves[priv->data.active_slave];
1459
1460         ctrl = slave_read(slave, CPSW2_CONTROL);
1461         switch (priv->version) {
1462         case CPSW_VERSION_2:
1463                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1464
1465                 if (priv->cpts->tx_enable)
1466                         ctrl |= CTRL_V2_TX_TS_BITS;
1467
1468                 if (priv->cpts->rx_enable)
1469                         ctrl |= CTRL_V2_RX_TS_BITS;
1470                 break;
1471         case CPSW_VERSION_3:
1472         default:
1473                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1474
1475                 if (priv->cpts->tx_enable)
1476                         ctrl |= CTRL_V3_TX_TS_BITS;
1477
1478                 if (priv->cpts->rx_enable)
1479                         ctrl |= CTRL_V3_RX_TS_BITS;
1480                 break;
1481         }
1482
1483         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1484
1485         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1486         slave_write(slave, ctrl, CPSW2_CONTROL);
1487         __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1488 }
1489
1490 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1491 {
1492         struct cpsw_priv *priv = netdev_priv(dev);
1493         struct cpts *cpts = priv->cpts;
1494         struct hwtstamp_config cfg;
1495
1496         if (priv->version != CPSW_VERSION_1 &&
1497             priv->version != CPSW_VERSION_2 &&
1498             priv->version != CPSW_VERSION_3)
1499                 return -EOPNOTSUPP;
1500
1501         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1502                 return -EFAULT;
1503
1504         /* reserved for future extensions */
1505         if (cfg.flags)
1506                 return -EINVAL;
1507
1508         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1509                 return -ERANGE;
1510
1511         switch (cfg.rx_filter) {
1512         case HWTSTAMP_FILTER_NONE:
1513                 cpts->rx_enable = 0;
1514                 break;
1515         case HWTSTAMP_FILTER_ALL:
1516         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1517         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1518         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1519                 return -ERANGE;
1520         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1521         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1522         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1523         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1524         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1525         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1526         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1527         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1528         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1529                 cpts->rx_enable = 1;
1530                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1531                 break;
1532         default:
1533                 return -ERANGE;
1534         }
1535
1536         cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1537
1538         switch (priv->version) {
1539         case CPSW_VERSION_1:
1540                 cpsw_hwtstamp_v1(priv);
1541                 break;
1542         case CPSW_VERSION_2:
1543         case CPSW_VERSION_3:
1544                 cpsw_hwtstamp_v2(priv);
1545                 break;
1546         default:
1547                 WARN_ON(1);
1548         }
1549
1550         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1551 }
1552
1553 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1554 {
1555         struct cpsw_priv *priv = netdev_priv(dev);
1556         struct cpts *cpts = priv->cpts;
1557         struct hwtstamp_config cfg;
1558
1559         if (priv->version != CPSW_VERSION_1 &&
1560             priv->version != CPSW_VERSION_2 &&
1561             priv->version != CPSW_VERSION_3)
1562                 return -EOPNOTSUPP;
1563
1564         cfg.flags = 0;
1565         cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1566         cfg.rx_filter = (cpts->rx_enable ?
1567                          HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1568
1569         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1570 }
1571
1572 #endif /*CONFIG_TI_CPTS*/
1573
1574 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1575 {
1576         struct cpsw_priv *priv = netdev_priv(dev);
1577         int slave_no = cpsw_slave_index(priv);
1578
1579         if (!netif_running(dev))
1580                 return -EINVAL;
1581
1582         switch (cmd) {
1583 #ifdef CONFIG_TI_CPTS
1584         case SIOCSHWTSTAMP:
1585                 return cpsw_hwtstamp_set(dev, req);
1586         case SIOCGHWTSTAMP:
1587                 return cpsw_hwtstamp_get(dev, req);
1588 #endif
1589         }
1590
1591         if (!priv->slaves[slave_no].phy)
1592                 return -EOPNOTSUPP;
1593         return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
1594 }
1595
1596 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1597 {
1598         struct cpsw_priv *priv = netdev_priv(ndev);
1599
1600         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1601         ndev->stats.tx_errors++;
1602         cpsw_intr_disable(priv);
1603         cpdma_chan_stop(priv->txch);
1604         cpdma_chan_start(priv->txch);
1605         cpsw_intr_enable(priv);
1606 }
1607
1608 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1609 {
1610         struct cpsw_priv *priv = netdev_priv(ndev);
1611         struct sockaddr *addr = (struct sockaddr *)p;
1612         int flags = 0;
1613         u16 vid = 0;
1614
1615         if (!is_valid_ether_addr(addr->sa_data))
1616                 return -EADDRNOTAVAIL;
1617
1618         if (priv->data.dual_emac) {
1619                 vid = priv->slaves[priv->emac_port].port_vlan;
1620                 flags = ALE_VLAN;
1621         }
1622
1623         cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1624                            flags, vid);
1625         cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1626                            flags, vid);
1627
1628         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1629         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1630         for_each_slave(priv, cpsw_set_slave_mac, priv);
1631
1632         return 0;
1633 }
1634
1635 #ifdef CONFIG_NET_POLL_CONTROLLER
1636 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1637 {
1638         struct cpsw_priv *priv = netdev_priv(ndev);
1639
1640         cpsw_intr_disable(priv);
1641         cpsw_rx_interrupt(priv->irqs_table[0], priv);
1642         cpsw_tx_interrupt(priv->irqs_table[1], priv);
1643         cpsw_intr_enable(priv);
1644 }
1645 #endif
1646
1647 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1648                                 unsigned short vid)
1649 {
1650         int ret;
1651         int unreg_mcast_mask = 0;
1652         u32 port_mask;
1653
1654         if (priv->data.dual_emac) {
1655                 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1656
1657                 if (priv->ndev->flags & IFF_ALLMULTI)
1658                         unreg_mcast_mask = port_mask;
1659         } else {
1660                 port_mask = ALE_ALL_PORTS;
1661
1662                 if (priv->ndev->flags & IFF_ALLMULTI)
1663                         unreg_mcast_mask = ALE_ALL_PORTS;
1664                 else
1665                         unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1666         }
1667
1668         ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask,
1669                                 unreg_mcast_mask << priv->host_port);
1670         if (ret != 0)
1671                 return ret;
1672
1673         ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1674                                  priv->host_port, ALE_VLAN, vid);
1675         if (ret != 0)
1676                 goto clean_vid;
1677
1678         ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1679                                  port_mask, ALE_VLAN, vid, 0);
1680         if (ret != 0)
1681                 goto clean_vlan_ucast;
1682         return 0;
1683
1684 clean_vlan_ucast:
1685         cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1686                             priv->host_port, ALE_VLAN, vid);
1687 clean_vid:
1688         cpsw_ale_del_vlan(priv->ale, vid, 0);
1689         return ret;
1690 }
1691
1692 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1693                                     __be16 proto, u16 vid)
1694 {
1695         struct cpsw_priv *priv = netdev_priv(ndev);
1696
1697         if (vid == priv->data.default_vlan)
1698                 return 0;
1699
1700         if (priv->data.dual_emac) {
1701                 /* In dual EMAC, reserved VLAN id should not be used for
1702                  * creating VLAN interfaces as this can break the dual
1703                  * EMAC port separation
1704                  */
1705                 int i;
1706
1707                 for (i = 0; i < priv->data.slaves; i++) {
1708                         if (vid == priv->slaves[i].port_vlan)
1709                                 return -EINVAL;
1710                 }
1711         }
1712
1713         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1714         return cpsw_add_vlan_ale_entry(priv, vid);
1715 }
1716
1717 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1718                                      __be16 proto, u16 vid)
1719 {
1720         struct cpsw_priv *priv = netdev_priv(ndev);
1721         int ret;
1722
1723         if (vid == priv->data.default_vlan)
1724                 return 0;
1725
1726         if (priv->data.dual_emac) {
1727                 int i;
1728
1729                 for (i = 0; i < priv->data.slaves; i++) {
1730                         if (vid == priv->slaves[i].port_vlan)
1731                                 return -EINVAL;
1732                 }
1733         }
1734
1735         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1736         ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1737         if (ret != 0)
1738                 return ret;
1739
1740         ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1741                                  priv->host_port, ALE_VLAN, vid);
1742         if (ret != 0)
1743                 return ret;
1744
1745         return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1746                                   0, ALE_VLAN, vid);
1747 }
1748
1749 static const struct net_device_ops cpsw_netdev_ops = {
1750         .ndo_open               = cpsw_ndo_open,
1751         .ndo_stop               = cpsw_ndo_stop,
1752         .ndo_start_xmit         = cpsw_ndo_start_xmit,
1753         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
1754         .ndo_do_ioctl           = cpsw_ndo_ioctl,
1755         .ndo_validate_addr      = eth_validate_addr,
1756         .ndo_change_mtu         = eth_change_mtu,
1757         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
1758         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
1759 #ifdef CONFIG_NET_POLL_CONTROLLER
1760         .ndo_poll_controller    = cpsw_ndo_poll_controller,
1761 #endif
1762         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
1763         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
1764 };
1765
1766 static int cpsw_get_regs_len(struct net_device *ndev)
1767 {
1768         struct cpsw_priv *priv = netdev_priv(ndev);
1769
1770         return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1771 }
1772
1773 static void cpsw_get_regs(struct net_device *ndev,
1774                           struct ethtool_regs *regs, void *p)
1775 {
1776         struct cpsw_priv *priv = netdev_priv(ndev);
1777         u32 *reg = p;
1778
1779         /* update CPSW IP version */
1780         regs->version = priv->version;
1781
1782         cpsw_ale_dump(priv->ale, reg);
1783 }
1784
1785 static void cpsw_get_drvinfo(struct net_device *ndev,
1786                              struct ethtool_drvinfo *info)
1787 {
1788         struct cpsw_priv *priv = netdev_priv(ndev);
1789
1790         strlcpy(info->driver, "cpsw", sizeof(info->driver));
1791         strlcpy(info->version, "1.0", sizeof(info->version));
1792         strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1793 }
1794
1795 static u32 cpsw_get_msglevel(struct net_device *ndev)
1796 {
1797         struct cpsw_priv *priv = netdev_priv(ndev);
1798         return priv->msg_enable;
1799 }
1800
1801 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1802 {
1803         struct cpsw_priv *priv = netdev_priv(ndev);
1804         priv->msg_enable = value;
1805 }
1806
1807 static int cpsw_get_ts_info(struct net_device *ndev,
1808                             struct ethtool_ts_info *info)
1809 {
1810 #ifdef CONFIG_TI_CPTS
1811         struct cpsw_priv *priv = netdev_priv(ndev);
1812
1813         info->so_timestamping =
1814                 SOF_TIMESTAMPING_TX_HARDWARE |
1815                 SOF_TIMESTAMPING_TX_SOFTWARE |
1816                 SOF_TIMESTAMPING_RX_HARDWARE |
1817                 SOF_TIMESTAMPING_RX_SOFTWARE |
1818                 SOF_TIMESTAMPING_SOFTWARE |
1819                 SOF_TIMESTAMPING_RAW_HARDWARE;
1820         info->phc_index = priv->cpts->phc_index;
1821         info->tx_types =
1822                 (1 << HWTSTAMP_TX_OFF) |
1823                 (1 << HWTSTAMP_TX_ON);
1824         info->rx_filters =
1825                 (1 << HWTSTAMP_FILTER_NONE) |
1826                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1827 #else
1828         info->so_timestamping =
1829                 SOF_TIMESTAMPING_TX_SOFTWARE |
1830                 SOF_TIMESTAMPING_RX_SOFTWARE |
1831                 SOF_TIMESTAMPING_SOFTWARE;
1832         info->phc_index = -1;
1833         info->tx_types = 0;
1834         info->rx_filters = 0;
1835 #endif
1836         return 0;
1837 }
1838
1839 static int cpsw_get_settings(struct net_device *ndev,
1840                              struct ethtool_cmd *ecmd)
1841 {
1842         struct cpsw_priv *priv = netdev_priv(ndev);
1843         int slave_no = cpsw_slave_index(priv);
1844
1845         if (priv->slaves[slave_no].phy)
1846                 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1847         else
1848                 return -EOPNOTSUPP;
1849 }
1850
1851 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1852 {
1853         struct cpsw_priv *priv = netdev_priv(ndev);
1854         int slave_no = cpsw_slave_index(priv);
1855
1856         if (priv->slaves[slave_no].phy)
1857                 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1858         else
1859                 return -EOPNOTSUPP;
1860 }
1861
1862 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1863 {
1864         struct cpsw_priv *priv = netdev_priv(ndev);
1865         int slave_no = cpsw_slave_index(priv);
1866
1867         wol->supported = 0;
1868         wol->wolopts = 0;
1869
1870         if (priv->slaves[slave_no].phy)
1871                 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1872 }
1873
1874 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1875 {
1876         struct cpsw_priv *priv = netdev_priv(ndev);
1877         int slave_no = cpsw_slave_index(priv);
1878
1879         if (priv->slaves[slave_no].phy)
1880                 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1881         else
1882                 return -EOPNOTSUPP;
1883 }
1884
1885 static void cpsw_get_pauseparam(struct net_device *ndev,
1886                                 struct ethtool_pauseparam *pause)
1887 {
1888         struct cpsw_priv *priv = netdev_priv(ndev);
1889
1890         pause->autoneg = AUTONEG_DISABLE;
1891         pause->rx_pause = priv->rx_pause ? true : false;
1892         pause->tx_pause = priv->tx_pause ? true : false;
1893 }
1894
1895 static int cpsw_set_pauseparam(struct net_device *ndev,
1896                                struct ethtool_pauseparam *pause)
1897 {
1898         struct cpsw_priv *priv = netdev_priv(ndev);
1899         bool link;
1900
1901         priv->rx_pause = pause->rx_pause ? true : false;
1902         priv->tx_pause = pause->tx_pause ? true : false;
1903
1904         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1905
1906         return 0;
1907 }
1908
1909 static const struct ethtool_ops cpsw_ethtool_ops = {
1910         .get_drvinfo    = cpsw_get_drvinfo,
1911         .get_msglevel   = cpsw_get_msglevel,
1912         .set_msglevel   = cpsw_set_msglevel,
1913         .get_link       = ethtool_op_get_link,
1914         .get_ts_info    = cpsw_get_ts_info,
1915         .get_settings   = cpsw_get_settings,
1916         .set_settings   = cpsw_set_settings,
1917         .get_coalesce   = cpsw_get_coalesce,
1918         .set_coalesce   = cpsw_set_coalesce,
1919         .get_sset_count         = cpsw_get_sset_count,
1920         .get_strings            = cpsw_get_strings,
1921         .get_ethtool_stats      = cpsw_get_ethtool_stats,
1922         .get_pauseparam         = cpsw_get_pauseparam,
1923         .set_pauseparam         = cpsw_set_pauseparam,
1924         .get_wol        = cpsw_get_wol,
1925         .set_wol        = cpsw_set_wol,
1926         .get_regs_len   = cpsw_get_regs_len,
1927         .get_regs       = cpsw_get_regs,
1928 };
1929
1930 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1931                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
1932 {
1933         void __iomem            *regs = priv->regs;
1934         int                     slave_num = slave->slave_num;
1935         struct cpsw_slave_data  *data = priv->data.slave_data + slave_num;
1936
1937         slave->data     = data;
1938         slave->regs     = regs + slave_reg_ofs;
1939         slave->sliver   = regs + sliver_reg_ofs;
1940         slave->port_vlan = data->dual_emac_res_vlan;
1941 }
1942
1943 static int cpsw_probe_dt(struct cpsw_priv *priv,
1944                          struct platform_device *pdev)
1945 {
1946         struct device_node *node = pdev->dev.of_node;
1947         struct device_node *slave_node;
1948         struct cpsw_platform_data *data = &priv->data;
1949         int i = 0, ret;
1950         u32 prop;
1951
1952         if (!node)
1953                 return -EINVAL;
1954
1955         if (of_property_read_u32(node, "slaves", &prop)) {
1956                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
1957                 return -EINVAL;
1958         }
1959         data->slaves = prop;
1960
1961         if (of_property_read_u32(node, "active_slave", &prop)) {
1962                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
1963                 return -EINVAL;
1964         }
1965         data->active_slave = prop;
1966
1967         if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1968                 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
1969                 return -EINVAL;
1970         }
1971         data->cpts_clock_mult = prop;
1972
1973         if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1974                 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
1975                 return -EINVAL;
1976         }
1977         data->cpts_clock_shift = prop;
1978
1979         data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1980                                         * sizeof(struct cpsw_slave_data),
1981                                         GFP_KERNEL);
1982         if (!data->slave_data)
1983                 return -ENOMEM;
1984
1985         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1986                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
1987                 return -EINVAL;
1988         }
1989         data->channels = prop;
1990
1991         if (of_property_read_u32(node, "ale_entries", &prop)) {
1992                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
1993                 return -EINVAL;
1994         }
1995         data->ale_entries = prop;
1996
1997         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1998                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
1999                 return -EINVAL;
2000         }
2001         data->bd_ram_size = prop;
2002
2003         if (of_property_read_u32(node, "rx_descs", &prop)) {
2004                 dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
2005                 return -EINVAL;
2006         }
2007         data->rx_descs = prop;
2008
2009         if (of_property_read_u32(node, "mac_control", &prop)) {
2010                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2011                 return -EINVAL;
2012         }
2013         data->mac_control = prop;
2014
2015         if (of_property_read_bool(node, "dual_emac"))
2016                 data->dual_emac = 1;
2017
2018         /*
2019          * Populate all the child nodes here...
2020          */
2021         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2022         /* We do not want to force this, as in some cases may not have child */
2023         if (ret)
2024                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2025
2026         for_each_child_of_node(node, slave_node) {
2027                 struct cpsw_slave_data *slave_data = data->slave_data + i;
2028                 const void *mac_addr = NULL;
2029                 u32 phyid;
2030                 int lenp;
2031                 const __be32 *parp;
2032                 struct device_node *mdio_node;
2033                 struct platform_device *mdio;
2034
2035                 /* This is no slave child node, continue */
2036                 if (strcmp(slave_node->name, "slave"))
2037                         continue;
2038
2039                 priv->phy_node = of_parse_phandle(slave_node, "phy-handle", 0);
2040                 parp = of_get_property(slave_node, "phy_id", &lenp);
2041                 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
2042                         dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i);
2043                         goto no_phy_slave;
2044                 }
2045                 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2046                 phyid = be32_to_cpup(parp+1);
2047                 mdio = of_find_device_by_node(mdio_node);
2048                 of_node_put(mdio_node);
2049                 if (!mdio) {
2050                         dev_err(&pdev->dev, "Missing mdio platform device\n");
2051                         return -EINVAL;
2052                 }
2053                 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2054                          PHY_ID_FMT, mdio->name, phyid);
2055                 slave_data->phy_if = of_get_phy_mode(slave_node);
2056                 if (slave_data->phy_if < 0) {
2057                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2058                                 i);
2059                         return slave_data->phy_if;
2060                 }
2061
2062 no_phy_slave:
2063                 mac_addr = of_get_mac_address(slave_node);
2064                 if (mac_addr) {
2065                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2066                 } else {
2067                         ret = ti_cm_get_macid(&pdev->dev, i,
2068                                               slave_data->mac_addr);
2069                         if (ret)
2070                                 return ret;
2071                 }
2072                 if (data->dual_emac) {
2073                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2074                                                  &prop)) {
2075                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2076                                 slave_data->dual_emac_res_vlan = i+1;
2077                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2078                                         slave_data->dual_emac_res_vlan, i);
2079                         } else {
2080                                 slave_data->dual_emac_res_vlan = prop;
2081                         }
2082                 }
2083
2084                 i++;
2085                 if (i == data->slaves)
2086                         break;
2087         }
2088
2089         return 0;
2090 }
2091
2092 static int cpsw_probe_dual_emac(struct platform_device *pdev,
2093                                 struct cpsw_priv *priv)
2094 {
2095         struct cpsw_platform_data       *data = &priv->data;
2096         struct net_device               *ndev;
2097         struct cpsw_priv                *priv_sl2;
2098         int ret = 0, i;
2099
2100         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2101         if (!ndev) {
2102                 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
2103                 return -ENOMEM;
2104         }
2105
2106         priv_sl2 = netdev_priv(ndev);
2107         spin_lock_init(&priv_sl2->lock);
2108         priv_sl2->data = *data;
2109         priv_sl2->pdev = pdev;
2110         priv_sl2->ndev = ndev;
2111         priv_sl2->dev  = &ndev->dev;
2112         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2113         priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2114
2115         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2116                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2117                         ETH_ALEN);
2118                 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
2119         } else {
2120                 random_ether_addr(priv_sl2->mac_addr);
2121                 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
2122         }
2123         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2124
2125         priv_sl2->slaves = priv->slaves;
2126         priv_sl2->clk = priv->clk;
2127
2128         priv_sl2->coal_intvl = 0;
2129         priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2130
2131         priv_sl2->regs = priv->regs;
2132         priv_sl2->host_port = priv->host_port;
2133         priv_sl2->host_port_regs = priv->host_port_regs;
2134         priv_sl2->wr_regs = priv->wr_regs;
2135         priv_sl2->hw_stats = priv->hw_stats;
2136         priv_sl2->dma = priv->dma;
2137         priv_sl2->txch = priv->txch;
2138         priv_sl2->rxch = priv->rxch;
2139         priv_sl2->ale = priv->ale;
2140         priv_sl2->emac_port = 1;
2141         priv->slaves[1].ndev = ndev;
2142         priv_sl2->cpts = priv->cpts;
2143         priv_sl2->version = priv->version;
2144
2145         for (i = 0; i < priv->num_irqs; i++) {
2146                 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2147                 priv_sl2->num_irqs = priv->num_irqs;
2148         }
2149         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2150
2151         ndev->netdev_ops = &cpsw_netdev_ops;
2152         ndev->ethtool_ops = &cpsw_ethtool_ops;
2153
2154         /* register the network device */
2155         SET_NETDEV_DEV(ndev, &pdev->dev);
2156         ret = register_netdev(ndev);
2157         if (ret) {
2158                 dev_err(&pdev->dev, "cpsw: error registering net device\n");
2159                 free_netdev(ndev);
2160                 ret = -ENODEV;
2161         }
2162
2163         return ret;
2164 }
2165
2166 #define CPSW_QUIRK_IRQ          BIT(0)
2167
2168 static struct platform_device_id cpsw_devtype[] = {
2169         {
2170                 /* keep it for existing comaptibles */
2171                 .name = "cpsw",
2172                 .driver_data = CPSW_QUIRK_IRQ,
2173         }, {
2174                 .name = "am335x-cpsw",
2175                 .driver_data = CPSW_QUIRK_IRQ,
2176         }, {
2177                 .name = "am4372-cpsw",
2178                 .driver_data = 0,
2179         }, {
2180                 .name = "dra7-cpsw",
2181                 .driver_data = 0,
2182         }, {
2183                 /* sentinel */
2184         }
2185 };
2186 MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2187
2188 enum ti_cpsw_type {
2189         CPSW = 0,
2190         AM335X_CPSW,
2191         AM4372_CPSW,
2192         DRA7_CPSW,
2193 };
2194
2195 static const struct of_device_id cpsw_of_mtable[] = {
2196         { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2197         { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2198         { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2199         { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2200         { /* sentinel */ },
2201 };
2202 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2203
2204 static int cpsw_probe(struct platform_device *pdev)
2205 {
2206         struct cpsw_platform_data       *data;
2207         struct net_device               *ndev;
2208         struct cpsw_priv                *priv;
2209         struct cpdma_params             dma_params;
2210         struct cpsw_ale_params          ale_params;
2211         void __iomem                    *ss_regs;
2212         struct resource                 *res, *ss_res;
2213         const struct of_device_id       *of_id;
2214         struct gpio_descs               *mode;
2215         u32 slave_offset, sliver_offset, slave_size;
2216         int ret = 0, i;
2217         int irq;
2218
2219         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2220         if (!ndev) {
2221                 dev_err(&pdev->dev, "error allocating net_device\n");
2222                 return -ENOMEM;
2223         }
2224
2225         platform_set_drvdata(pdev, ndev);
2226         priv = netdev_priv(ndev);
2227         spin_lock_init(&priv->lock);
2228         priv->pdev = pdev;
2229         priv->ndev = ndev;
2230         priv->dev  = &ndev->dev;
2231         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2232         priv->rx_packet_max = max(rx_packet_max, 128);
2233         priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2234         if (!priv->cpts) {
2235                 dev_err(&pdev->dev, "error allocating cpts\n");
2236                 ret = -ENOMEM;
2237                 goto clean_ndev_ret;
2238         }
2239
2240         mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2241         if (IS_ERR(mode)) {
2242                 ret = PTR_ERR(mode);
2243                 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2244                 goto clean_ndev_ret;
2245         }
2246
2247         /*
2248          * This may be required here for child devices.
2249          */
2250         pm_runtime_enable(&pdev->dev);
2251
2252         /* Select default pin state */
2253         pinctrl_pm_select_default_state(&pdev->dev);
2254
2255         if (cpsw_probe_dt(priv, pdev)) {
2256                 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2257                 ret = -ENODEV;
2258                 goto clean_runtime_disable_ret;
2259         }
2260         data = &priv->data;
2261
2262         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2263                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2264                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2265         } else {
2266                 eth_random_addr(priv->mac_addr);
2267                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2268         }
2269
2270         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2271
2272         priv->slaves = devm_kzalloc(&pdev->dev,
2273                                     sizeof(struct cpsw_slave) * data->slaves,
2274                                     GFP_KERNEL);
2275         if (!priv->slaves) {
2276                 ret = -ENOMEM;
2277                 goto clean_runtime_disable_ret;
2278         }
2279         for (i = 0; i < data->slaves; i++)
2280                 priv->slaves[i].slave_num = i;
2281
2282         priv->slaves[0].ndev = ndev;
2283         priv->emac_port = 0;
2284
2285         priv->clk = devm_clk_get(&pdev->dev, "fck");
2286         if (IS_ERR(priv->clk)) {
2287                 dev_err(priv->dev, "fck is not found\n");
2288                 ret = -ENODEV;
2289                 goto clean_runtime_disable_ret;
2290         }
2291         priv->coal_intvl = 0;
2292         priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
2293
2294         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2295         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2296         if (IS_ERR(ss_regs)) {
2297                 ret = PTR_ERR(ss_regs);
2298                 goto clean_runtime_disable_ret;
2299         }
2300         priv->regs = ss_regs;
2301         priv->host_port = HOST_PORT_NUM;
2302
2303         /* Need to enable clocks with runtime PM api to access module
2304          * registers
2305          */
2306         pm_runtime_get_sync(&pdev->dev);
2307         priv->version = readl(&priv->regs->id_ver);
2308         pm_runtime_put_sync(&pdev->dev);
2309
2310         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2311         priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2312         if (IS_ERR(priv->wr_regs)) {
2313                 ret = PTR_ERR(priv->wr_regs);
2314                 goto clean_runtime_disable_ret;
2315         }
2316
2317         memset(&dma_params, 0, sizeof(dma_params));
2318         memset(&ale_params, 0, sizeof(ale_params));
2319
2320         switch (priv->version) {
2321         case CPSW_VERSION_1:
2322                 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2323                 priv->cpts->reg      = ss_regs + CPSW1_CPTS_OFFSET;
2324                 priv->hw_stats       = ss_regs + CPSW1_HW_STATS;
2325                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
2326                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
2327                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
2328                 slave_offset         = CPSW1_SLAVE_OFFSET;
2329                 slave_size           = CPSW1_SLAVE_SIZE;
2330                 sliver_offset        = CPSW1_SLIVER_OFFSET;
2331                 dma_params.desc_mem_phys = 0;
2332                 break;
2333         case CPSW_VERSION_2:
2334         case CPSW_VERSION_3:
2335         case CPSW_VERSION_4:
2336                 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2337                 priv->cpts->reg      = ss_regs + CPSW2_CPTS_OFFSET;
2338                 priv->hw_stats       = ss_regs + CPSW2_HW_STATS;
2339                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
2340                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
2341                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
2342                 slave_offset         = CPSW2_SLAVE_OFFSET;
2343                 slave_size           = CPSW2_SLAVE_SIZE;
2344                 sliver_offset        = CPSW2_SLIVER_OFFSET;
2345                 dma_params.desc_mem_phys =
2346                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2347                 break;
2348         default:
2349                 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2350                 ret = -ENODEV;
2351                 goto clean_runtime_disable_ret;
2352         }
2353         for (i = 0; i < priv->data.slaves; i++) {
2354                 struct cpsw_slave *slave = &priv->slaves[i];
2355                 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2356                 slave_offset  += slave_size;
2357                 sliver_offset += SLIVER_SIZE;
2358         }
2359
2360         dma_params.dev          = &pdev->dev;
2361         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
2362         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
2363         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
2364         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
2365         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
2366
2367         dma_params.num_chan             = data->channels;
2368         dma_params.has_soft_reset       = true;
2369         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
2370         dma_params.desc_mem_size        = data->bd_ram_size;
2371         dma_params.desc_align           = 16;
2372         dma_params.has_ext_regs         = true;
2373         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
2374
2375         priv->dma = cpdma_ctlr_create(&dma_params);
2376         if (!priv->dma) {
2377                 dev_err(priv->dev, "error initializing dma\n");
2378                 ret = -ENOMEM;
2379                 goto clean_runtime_disable_ret;
2380         }
2381
2382         priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2383                                        cpsw_tx_handler);
2384         priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2385                                        cpsw_rx_handler);
2386
2387         if (WARN_ON(!priv->txch || !priv->rxch)) {
2388                 dev_err(priv->dev, "error initializing dma channels\n");
2389                 ret = -ENOMEM;
2390                 goto clean_dma_ret;
2391         }
2392
2393         ale_params.dev                  = &ndev->dev;
2394         ale_params.ale_ageout           = ale_ageout;
2395         ale_params.ale_entries          = data->ale_entries;
2396         ale_params.ale_ports            = data->slaves;
2397
2398         priv->ale = cpsw_ale_create(&ale_params);
2399         if (!priv->ale) {
2400                 dev_err(priv->dev, "error initializing ale engine\n");
2401                 ret = -ENODEV;
2402                 goto clean_dma_ret;
2403         }
2404
2405         ndev->irq = platform_get_irq(pdev, 1);
2406         if (ndev->irq < 0) {
2407                 dev_err(priv->dev, "error getting irq resource\n");
2408                 ret = -ENOENT;
2409                 goto clean_ale_ret;
2410         }
2411
2412         of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
2413         if (of_id) {
2414                 pdev->id_entry = of_id->data;
2415                 if (pdev->id_entry->driver_data)
2416                         priv->quirk_irq = true;
2417         }
2418
2419         /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2420          * MISC IRQs which are always kept disabled with this driver so
2421          * we will not request them.
2422          *
2423          * If anyone wants to implement support for those, make sure to
2424          * first request and append them to irqs_table array.
2425          */
2426
2427         /* RX IRQ */
2428         irq = platform_get_irq(pdev, 1);
2429         if (irq < 0)
2430                 goto clean_ale_ret;
2431
2432         priv->irqs_table[0] = irq;
2433         ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
2434                                0, dev_name(&pdev->dev), priv);
2435         if (ret < 0) {
2436                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2437                 goto clean_ale_ret;
2438         }
2439
2440         /* TX IRQ */
2441         irq = platform_get_irq(pdev, 2);
2442         if (irq < 0)
2443                 goto clean_ale_ret;
2444
2445         priv->irqs_table[1] = irq;
2446         ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
2447                                0, dev_name(&pdev->dev), priv);
2448         if (ret < 0) {
2449                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2450                 goto clean_ale_ret;
2451         }
2452         priv->num_irqs = 2;
2453
2454         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2455
2456         ndev->netdev_ops = &cpsw_netdev_ops;
2457         ndev->ethtool_ops = &cpsw_ethtool_ops;
2458         netif_napi_add(ndev, &priv->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
2459         netif_napi_add(ndev, &priv->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
2460
2461         /* register the network device */
2462         SET_NETDEV_DEV(ndev, &pdev->dev);
2463         ret = register_netdev(ndev);
2464         if (ret) {
2465                 dev_err(priv->dev, "error registering net device\n");
2466                 ret = -ENODEV;
2467                 goto clean_ale_ret;
2468         }
2469
2470         cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2471                     &ss_res->start, ndev->irq);
2472
2473         if (priv->data.dual_emac) {
2474                 ret = cpsw_probe_dual_emac(pdev, priv);
2475                 if (ret) {
2476                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2477                         goto clean_ale_ret;
2478                 }
2479         }
2480
2481         return 0;
2482
2483 clean_ale_ret:
2484         cpsw_ale_destroy(priv->ale);
2485 clean_dma_ret:
2486         cpdma_chan_destroy(priv->txch);
2487         cpdma_chan_destroy(priv->rxch);
2488         cpdma_ctlr_destroy(priv->dma);
2489 clean_runtime_disable_ret:
2490         pm_runtime_disable(&pdev->dev);
2491 clean_ndev_ret:
2492         free_netdev(priv->ndev);
2493         return ret;
2494 }
2495
2496 static int cpsw_remove_child_device(struct device *dev, void *c)
2497 {
2498         struct platform_device *pdev = to_platform_device(dev);
2499
2500         of_device_unregister(pdev);
2501
2502         return 0;
2503 }
2504
2505 static int cpsw_remove(struct platform_device *pdev)
2506 {
2507         struct net_device *ndev = platform_get_drvdata(pdev);
2508         struct cpsw_priv *priv = netdev_priv(ndev);
2509
2510         if (priv->data.dual_emac)
2511                 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2512         unregister_netdev(ndev);
2513
2514         cpsw_ale_destroy(priv->ale);
2515         cpdma_chan_destroy(priv->txch);
2516         cpdma_chan_destroy(priv->rxch);
2517         cpdma_ctlr_destroy(priv->dma);
2518         pm_runtime_disable(&pdev->dev);
2519         device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device);
2520         if (priv->data.dual_emac)
2521                 free_netdev(cpsw_get_slave_ndev(priv, 1));
2522         free_netdev(ndev);
2523         return 0;
2524 }
2525
2526 #ifdef CONFIG_PM_SLEEP
2527 static int cpsw_suspend(struct device *dev)
2528 {
2529         struct platform_device  *pdev = to_platform_device(dev);
2530         struct net_device       *ndev = platform_get_drvdata(pdev);
2531         struct cpsw_priv        *priv = netdev_priv(ndev);
2532
2533         if (priv->data.dual_emac) {
2534                 int i;
2535
2536                 for (i = 0; i < priv->data.slaves; i++) {
2537                         if (netif_running(priv->slaves[i].ndev))
2538                                 cpsw_ndo_stop(priv->slaves[i].ndev);
2539                         soft_reset_slave(priv->slaves + i);
2540                 }
2541         } else {
2542                 if (netif_running(ndev))
2543                         cpsw_ndo_stop(ndev);
2544                 for_each_slave(priv, soft_reset_slave);
2545         }
2546
2547         pm_runtime_put_sync(&pdev->dev);
2548
2549         /* Select sleep pin state */
2550         pinctrl_pm_select_sleep_state(&pdev->dev);
2551
2552         return 0;
2553 }
2554
2555 static int cpsw_resume(struct device *dev)
2556 {
2557         struct platform_device  *pdev = to_platform_device(dev);
2558         struct net_device       *ndev = platform_get_drvdata(pdev);
2559         struct cpsw_priv        *priv = netdev_priv(ndev);
2560
2561         pm_runtime_get_sync(&pdev->dev);
2562
2563         /* Select default pin state */
2564         pinctrl_pm_select_default_state(&pdev->dev);
2565
2566         if (priv->data.dual_emac) {
2567                 int i;
2568
2569                 for (i = 0; i < priv->data.slaves; i++) {
2570                         if (netif_running(priv->slaves[i].ndev))
2571                                 cpsw_ndo_open(priv->slaves[i].ndev);
2572                 }
2573         } else {
2574                 if (netif_running(ndev))
2575                         cpsw_ndo_open(ndev);
2576         }
2577         return 0;
2578 }
2579 #endif
2580
2581 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
2582
2583 static struct platform_driver cpsw_driver = {
2584         .driver = {
2585                 .name    = "cpsw",
2586                 .pm      = &cpsw_pm_ops,
2587                 .of_match_table = cpsw_of_mtable,
2588         },
2589         .probe = cpsw_probe,
2590         .remove = cpsw_remove,
2591 };
2592
2593 module_platform_driver(cpsw_driver);
2594
2595 MODULE_LICENSE("GPL");
2596 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2597 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2598 MODULE_DESCRIPTION("TI CPSW Ethernet driver");