drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/of.h>
  33 #include <linux/of_mdio.h>
  34 #include <linux/of_net.h>
  35 #include <linux/of_device.h>
  36 #include <linux/if_vlan.h>
  37
  38 #include <linux/pinctrl/consumer.h>
  39
  40 #include "cpsw.h"
  41 #include "cpsw_ale.h"
  42 #include "cpts.h"
  43 #include "davinci_cpdma.h"
  44
  45 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  46                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  47                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  48                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  49                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  50                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  51                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  52                          NETIF_MSG_RX_STATUS)
  53
  54 #define cpsw_info(priv, type, format, ...)              \
  55 do {                                                            \
  56         if (netif_msg_##type(priv) && net_ratelimit())          \
  57                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  58 } while (0)
  59
  60 #define cpsw_err(priv, type, format, ...)               \
  61 do {                                                            \
  62         if (netif_msg_##type(priv) && net_ratelimit())          \
  63                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  64 } while (0)
  65
  66 #define cpsw_dbg(priv, type, format, ...)               \
  67 do {                                                            \
  68         if (netif_msg_##type(priv) && net_ratelimit())          \
  69                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  70 } while (0)
  71
  72 #define cpsw_notice(priv, type, format, ...)            \
  73 do {                                                            \
  74         if (netif_msg_##type(priv) && net_ratelimit())          \
  75                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  76 } while (0)
  77
  78 #define ALE_ALL_PORTS           0x7
  79
  80 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  81 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  82 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  83
  84 #define CPSW_VERSION_1          0x19010a
  85 #define CPSW_VERSION_2          0x19010c
  86 #define CPSW_VERSION_3          0x19010f
  87 #define CPSW_VERSION_4          0x190112
  88
  89 #define HOST_PORT_NUM           0
  90 #define SLIVER_SIZE             0x40
  91
  92 #define CPSW1_HOST_PORT_OFFSET  0x028
  93 #define CPSW1_SLAVE_OFFSET      0x050
  94 #define CPSW1_SLAVE_SIZE        0x040
  95 #define CPSW1_CPDMA_OFFSET      0x100
  96 #define CPSW1_STATERAM_OFFSET   0x200
  97 #define CPSW1_HW_STATS          0x400
  98 #define CPSW1_CPTS_OFFSET       0x500
  99 #define CPSW1_ALE_OFFSET        0x600
 100 #define CPSW1_SLIVER_OFFSET     0x700
 101
 102 #define CPSW2_HOST_PORT_OFFSET  0x108
 103 #define CPSW2_SLAVE_OFFSET      0x200
 104 #define CPSW2_SLAVE_SIZE        0x100
 105 #define CPSW2_CPDMA_OFFSET      0x800
 106 #define CPSW2_HW_STATS          0x900
 107 #define CPSW2_STATERAM_OFFSET   0xa00
 108 #define CPSW2_CPTS_OFFSET       0xc00
 109 #define CPSW2_ALE_OFFSET        0xd00
 110 #define CPSW2_SLIVER_OFFSET     0xd80
 111 #define CPSW2_BD_OFFSET         0x2000
 112
 113 #define CPDMA_RXTHRESH          0x0c0
 114 #define CPDMA_RXFREE            0x0e0
 115 #define CPDMA_TXHDP             0x00
 116 #define CPDMA_RXHDP             0x20
 117 #define CPDMA_TXCP              0x40
 118 #define CPDMA_RXCP              0x60
 119
 120 #define CPSW_POLL_WEIGHT        64
 121 #define CPSW_MIN_PACKET_SIZE    60
 122 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
 123
 124 #define RX_PRIORITY_MAPPING     0x76543210
 125 #define TX_PRIORITY_MAPPING     0x33221100
 126 #define CPDMA_TX_PRIORITY_MAP   0x76543210
 127
 128 #define CPSW_VLAN_AWARE         BIT(1)
 129 #define CPSW_ALE_VLAN_AWARE     1
 130
 131 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
 132 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
 133 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
 134
 135 #define CPSW_INTPACEEN          (0x3f << 16)
 136 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 137 #define CPSW_CMINTMAX_CNT       63
 138 #define CPSW_CMINTMIN_CNT       2
 139 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 140 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 141
 142 #define cpsw_slave_index(priv)                          \
 143                 ((priv->data.dual_emac) ? priv->emac_port :     \
 144                 priv->data.active_slave)
 145
 146 static int debug_level;
 147 module_param(debug_level, int, 0);
 148 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 149
 150 static int ale_ageout = 10;
 151 module_param(ale_ageout, int, 0);
 152 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 153
 154 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 155 module_param(rx_packet_max, int, 0);
 156 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 157
 158 struct cpsw_wr_regs {
 159         u32     id_ver;
 160         u32     soft_reset;
 161         u32     control;
 162         u32     int_control;
 163         u32     rx_thresh_en;
 164         u32     rx_en;
 165         u32     tx_en;
 166         u32     misc_en;
 167         u32     mem_allign1[8];
 168         u32     rx_thresh_stat;
 169         u32     rx_stat;
 170         u32     tx_stat;
 171         u32     misc_stat;
 172         u32     mem_allign2[8];
 173         u32     rx_imax;
 174         u32     tx_imax;
 175
 176 };
 177
 178 struct cpsw_ss_regs {
 179         u32     id_ver;
 180         u32     control;
 181         u32     soft_reset;
 182         u32     stat_port_en;
 183         u32     ptype;
 184         u32     soft_idle;
 185         u32     thru_rate;
 186         u32     gap_thresh;
 187         u32     tx_start_wds;
 188         u32     flow_control;
 189         u32     vlan_ltype;
 190         u32     ts_ltype;
 191         u32     dlr_ltype;
 192 };
 193
 194 /* CPSW_PORT_V1 */
 195 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 196 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 197 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 198 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 199 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 200 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 201 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 202 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 203
 204 /* CPSW_PORT_V2 */
 205 #define CPSW2_CONTROL       0x00 /* Control Register */
 206 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 207 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 208 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 209 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 210 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 211 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 212
 213 /* CPSW_PORT_V1 and V2 */
 214 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 215 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 216 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 217
 218 /* CPSW_PORT_V2 only */
 219 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 220 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 221 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 222 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 223 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 224 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 225 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 226 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 227
 228 /* Bit definitions for the CPSW2_CONTROL register */
 229 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 230 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 231 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 232 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 233 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 234 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 235 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 236 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 237 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 238 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 239 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
 240 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
 241 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 242 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 243 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 244 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 245 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 246
 247 #define CTRL_V2_TS_BITS \
 248         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 249          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
 250
 251 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
 252 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
 253 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
 254
 255
 256 #define CTRL_V3_TS_BITS \
 257         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 258          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
 259          TS_LTYPE1_EN)
 260
 261 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
 262 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
 263 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
 264
 265 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 266 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 267 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 268 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 269 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 270
 271 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 272 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 273
 274 /* Bit definitions for the CPSW1_TS_CTL register */
 275 #define CPSW_V1_TS_RX_EN                BIT(0)
 276 #define CPSW_V1_TS_TX_EN                BIT(4)
 277 #define CPSW_V1_MSG_TYPE_OFS            16
 278
 279 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 280 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 281
 282 struct cpsw_host_regs {
 283         u32     max_blks;
 284         u32     blk_cnt;
 285         u32     tx_in_ctl;
 286         u32     port_vlan;
 287         u32     tx_pri_map;
 288         u32     cpdma_tx_pri_map;
 289         u32     cpdma_rx_chan_map;
 290 };
 291
 292 struct cpsw_sliver_regs {
 293         u32     id_ver;
 294         u32     mac_control;
 295         u32     mac_status;
 296         u32     soft_reset;
 297         u32     rx_maxlen;
 298         u32     __reserved_0;
 299         u32     rx_pause;
 300         u32     tx_pause;
 301         u32     __reserved_1;
 302         u32     rx_pri_map;
 303 };
 304
 305 struct cpsw_hw_stats {
 306         u32     rxgoodframes;
 307         u32     rxbroadcastframes;
 308         u32     rxmulticastframes;
 309         u32     rxpauseframes;
 310         u32     rxcrcerrors;
 311         u32     rxaligncodeerrors;
 312         u32     rxoversizedframes;
 313         u32     rxjabberframes;
 314         u32     rxundersizedframes;
 315         u32     rxfragments;
 316         u32     __pad_0[2];
 317         u32     rxoctets;
 318         u32     txgoodframes;
 319         u32     txbroadcastframes;
 320         u32     txmulticastframes;
 321         u32     txpauseframes;
 322         u32     txdeferredframes;
 323         u32     txcollisionframes;
 324         u32     txsinglecollframes;
 325         u32     txmultcollframes;
 326         u32     txexcessivecollisions;
 327         u32     txlatecollisions;
 328         u32     txunderrun;
 329         u32     txcarriersenseerrors;
 330         u32     txoctets;
 331         u32     octetframes64;
 332         u32     octetframes65t127;
 333         u32     octetframes128t255;
 334         u32     octetframes256t511;
 335         u32     octetframes512t1023;
 336         u32     octetframes1024tup;
 337         u32     netoctets;
 338         u32     rxsofoverruns;
 339         u32     rxmofoverruns;
 340         u32     rxdmaoverruns;
 341 };
 342
 343 struct cpsw_slave {
 344         void __iomem                    *regs;
 345         struct cpsw_sliver_regs __iomem *sliver;
 346         int                             slave_num;
 347         u32                             mac_control;
 348         struct cpsw_slave_data          *data;
 349         struct phy_device               *phy;
 350         struct net_device               *ndev;
 351         u32                             port_vlan;
 352         u32                             open_stat;
 353 };
 354
 355 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 356 {
 357         return __raw_readl(slave->regs + offset);
 358 }
 359
 360 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 361 {
 362         __raw_writel(val, slave->regs + offset);
 363 }
 364
 365 struct cpsw_priv {
 366         spinlock_t                      lock;
 367         struct platform_device          *pdev;
 368         struct net_device               *ndev;
 369         struct device_node              *phy_node;
 370         struct napi_struct              napi_rx;
 371         struct napi_struct              napi_tx;
 372         struct device                   *dev;
 373         struct cpsw_platform_data       data;
 374         struct cpsw_ss_regs __iomem     *regs;
 375         struct cpsw_wr_regs __iomem     *wr_regs;
 376         u8 __iomem                      *hw_stats;
 377         struct cpsw_host_regs __iomem   *host_port_regs;
 378         u32                             msg_enable;
 379         u32                             version;
 380         u32                             coal_intvl;
 381         u32                             bus_freq_mhz;
 382         int                             rx_packet_max;
 383         int                             host_port;
 384         struct clk                      *clk;
 385         u8                              mac_addr[ETH_ALEN];
 386         struct cpsw_slave               *slaves;
 387         struct cpdma_ctlr               *dma;
 388         struct cpdma_chan               *txch, *rxch;
 389         struct cpsw_ale                 *ale;
 390         bool                            rx_pause;
 391         bool                            tx_pause;
 392         bool                            quirk_irq;
 393         bool                            rx_irq_disabled;
 394         bool                            tx_irq_disabled;
 395         /* snapshot of IRQ numbers */
 396         u32 irqs_table[4];
 397         u32 num_irqs;
 398         struct cpts *cpts;
 399         u32 emac_port;
 400 };
 401
 402 struct cpsw_stats {
 403         char stat_string[ETH_GSTRING_LEN];
 404         int type;
 405         int sizeof_stat;
 406         int stat_offset;
 407 };
 408
 409 enum {
 410         CPSW_STATS,
 411         CPDMA_RX_STATS,
 412         CPDMA_TX_STATS,
 413 };
 414
 415 #define CPSW_STAT(m)            CPSW_STATS,                             \
 416                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
 417                                 offsetof(struct cpsw_hw_stats, m)
 418 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
 419                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 420                                 offsetof(struct cpdma_chan_stats, m)
 421 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
 422                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 423                                 offsetof(struct cpdma_chan_stats, m)
 424
 425 static const struct cpsw_stats cpsw_gstrings_stats[] = {
 426         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
 427         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
 428         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
 429         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
 430         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
 431         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
 432         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
 433         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
 434         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
 435         { "Rx Fragments", CPSW_STAT(rxfragments) },
 436         { "Rx Octets", CPSW_STAT(rxoctets) },
 437         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
 438         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
 439         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
 440         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
 441         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
 442         { "Collisions", CPSW_STAT(txcollisionframes) },
 443         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
 444         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
 445         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
 446         { "Late Collisions", CPSW_STAT(txlatecollisions) },
 447         { "Tx Underrun", CPSW_STAT(txunderrun) },
 448         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
 449         { "Tx Octets", CPSW_STAT(txoctets) },
 450         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
 451         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
 452         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
 453         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
 454         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
 455         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
 456         { "Net Octets", CPSW_STAT(netoctets) },
 457         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
 458         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
 459         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
 460         { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
 461         { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
 462         { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
 463         { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
 464         { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
 465         { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
 466         { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
 467         { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
 468         { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
 469         { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
 470         { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
 471         { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
 472         { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
 473         { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
 474         { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
 475         { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
 476         { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
 477         { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
 478         { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
 479         { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
 480         { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
 481         { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
 482         { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
 483         { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
 484         { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
 485         { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
 486 };
 487
 488 #define CPSW_STATS_LEN  ARRAY_SIZE(cpsw_gstrings_stats)
 489
 490 #define napi_to_priv(napi)      container_of(napi, struct cpsw_priv, napi)
 491 #define for_each_slave(priv, func, arg...)                              \
 492         do {                                                            \
 493                 struct cpsw_slave *slave;                               \
 494                 int n;                                                  \
 495                 if (priv->data.dual_emac)                               \
 496                         (func)((priv)->slaves + priv->emac_port, ##arg);\
 497                 else                                                    \
 498                         for (n = (priv)->data.slaves,                   \
 499                                         slave = (priv)->slaves;         \
 500                                         n; n--)                         \
 501                                 (func)(slave++, ##arg);                 \
 502         } while (0)
 503 #define cpsw_get_slave_ndev(priv, __slave_no__)                         \
 504         ((__slave_no__ < priv->data.slaves) ?                           \
 505                 priv->slaves[__slave_no__].ndev : NULL)
 506 #define cpsw_get_slave_priv(priv, __slave_no__)                         \
 507         (((__slave_no__ < priv->data.slaves) &&                         \
 508                 (priv->slaves[__slave_no__].ndev)) ?                    \
 509                 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL)    \
 510
 511 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb)         \
 512         do {                                                            \
 513                 if (!priv->data.dual_emac)                              \
 514                         break;                                          \
 515                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
 516                         ndev = cpsw_get_slave_ndev(priv, 0);            \
 517                         priv = netdev_priv(ndev);                       \
 518                         skb->dev = ndev;                                \
 519                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
 520                         ndev = cpsw_get_slave_ndev(priv, 1);            \
 521                         priv = netdev_priv(ndev);                       \
 522                         skb->dev = ndev;                                \
 523                 }                                                       \
 524         } while (0)
 525 #define cpsw_add_mcast(priv, addr)                                      \
 526         do {                                                            \
 527                 if (priv->data.dual_emac) {                             \
 528                         struct cpsw_slave *slave = priv->slaves +       \
 529                                                 priv->emac_port;        \
 530                         int slave_port = cpsw_get_slave_port(priv,      \
 531                                                 slave->slave_num);      \
 532                         cpsw_ale_add_mcast(priv->ale, addr,             \
 533                                 1 << slave_port | 1 << priv->host_port, \
 534                                 ALE_VLAN, slave->port_vlan, 0);         \
 535                 } else {                                                \
 536                         cpsw_ale_add_mcast(priv->ale, addr,             \
 537                                 ALE_ALL_PORTS << priv->host_port,       \
 538                                 0, 0, 0);                               \
 539                 }                                                       \
 540         } while (0)
 541
 542 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 543 {
 544         if (priv->host_port == 0)
 545                 return slave_num + 1;
 546         else
 547                 return slave_num;
 548 }
 549
 550 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
 551 {
 552         struct cpsw_priv *priv = netdev_priv(ndev);
 553         struct cpsw_ale *ale = priv->ale;
 554         int i;
 555
 556         if (priv->data.dual_emac) {
 557                 bool flag = false;
 558
 559                 /* Enabling promiscuous mode for one interface will be
 560                  * common for both the interface as the interface shares
 561                  * the same hardware resource.
 562                  */
 563                 for (i = 0; i < priv->data.slaves; i++)
 564                         if (priv->slaves[i].ndev->flags & IFF_PROMISC)
 565                                 flag = true;
 566
 567                 if (!enable && flag) {
 568                         enable = true;
 569                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
 570                 }
 571
 572                 if (enable) {
 573                         /* Enable Bypass */
 574                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
 575
 576                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 577                 } else {
 578                         /* Disable Bypass */
 579                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
 580                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 581                 }
 582         } else {
 583                 if (enable) {
 584                         unsigned long timeout = jiffies + HZ;
 585
 586                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
 587                         for (i = 0; i <= priv->data.slaves; i++) {
 588                                 cpsw_ale_control_set(ale, i,
 589                                                      ALE_PORT_NOLEARN, 1);
 590                                 cpsw_ale_control_set(ale, i,
 591                                                      ALE_PORT_NO_SA_UPDATE, 1);
 592                         }
 593
 594                         /* Clear All Untouched entries */
 595                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 596                         do {
 597                                 cpu_relax();
 598                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
 599                                         break;
 600                         } while (time_after(timeout, jiffies));
 601                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 602
 603                         /* Clear all mcast from ALE */
 604                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<
 605                                                  priv->host_port, -1);
 606
 607                         /* Flood All Unicast Packets to Host port */
 608                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
 609                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 610                 } else {
 611                         /* Don't Flood All Unicast Packets to Host port */
 612                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
 613
 614                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
 615                         for (i = 0; i <= priv->data.slaves; i++) {
 616                                 cpsw_ale_control_set(ale, i,
 617                                                      ALE_PORT_NOLEARN, 0);
 618                                 cpsw_ale_control_set(ale, i,
 619                                                      ALE_PORT_NO_SA_UPDATE, 0);
 620                         }
 621                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 622                 }
 623         }
 624 }
 625
 626 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 627 {
 628         struct cpsw_priv *priv = netdev_priv(ndev);
 629         int vid;
 630
 631         if (priv->data.dual_emac)
 632                 vid = priv->slaves[priv->emac_port].port_vlan;
 633         else
 634                 vid = priv->data.default_vlan;
 635
 636         if (ndev->flags & IFF_PROMISC) {
 637                 /* Enable promiscuous mode */
 638                 cpsw_set_promiscious(ndev, true);
 639                 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
 640                 return;
 641         } else {
 642                 /* Disable promiscuous mode */
 643                 cpsw_set_promiscious(ndev, false);
 644         }
 645
 646         /* Restore allmulti on vlans if necessary */
 647         cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
 648
 649         /* Clear all mcast from ALE */
 650         cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port,
 651                                  vid);
 652
 653         if (!netdev_mc_empty(ndev)) {
 654                 struct netdev_hw_addr *ha;
 655
 656                 /* program multicast address list into ALE register */
 657                 netdev_for_each_mc_addr(ha, ndev) {
 658                         cpsw_add_mcast(priv, (u8 *)ha->addr);
 659                 }
 660         }
 661 }
 662
 663 static void cpsw_intr_enable(struct cpsw_priv *priv)
 664 {
 665         __raw_writel(0xFF, &priv->wr_regs->tx_en);
 666         __raw_writel(0xFF, &priv->wr_regs->rx_en);
 667
 668         cpdma_ctlr_int_ctrl(priv->dma, true);
 669         return;
 670 }
 671
 672 static void cpsw_intr_disable(struct cpsw_priv *priv)
 673 {
 674         __raw_writel(0, &priv->wr_regs->tx_en);
 675         __raw_writel(0, &priv->wr_regs->rx_en);
 676
 677         cpdma_ctlr_int_ctrl(priv->dma, false);
 678         return;
 679 }
 680
 681 static void cpsw_tx_handler(void *token, int len, int status)
 682 {
 683         struct sk_buff          *skb = token;
 684         struct net_device       *ndev = skb->dev;
 685         struct cpsw_priv        *priv = netdev_priv(ndev);
 686
 687         /* Check whether the queue is stopped due to stalled tx dma, if the
 688          * queue is stopped then start the queue as we have free desc for tx
 689          */
 690         if (unlikely(netif_queue_stopped(ndev)))
 691                 netif_wake_queue(ndev);
 692         cpts_tx_timestamp(priv->cpts, skb);
 693         ndev->stats.tx_packets++;
 694         ndev->stats.tx_bytes += len;
 695         dev_kfree_skb_any(skb);
 696 }
 697
 698 static void cpsw_rx_handler(void *token, int len, int status)
 699 {
 700         struct sk_buff          *skb = token;
 701         struct sk_buff          *new_skb;
 702         struct net_device       *ndev = skb->dev;
 703         struct cpsw_priv        *priv = netdev_priv(ndev);
 704         int                     ret = 0;
 705
 706         cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
 707
 708         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
 709                 bool ndev_status = false;
 710                 struct cpsw_slave *slave = priv->slaves;
 711                 int n;
 712
 713                 if (priv->data.dual_emac) {
 714                         /* In dual emac mode check for all interfaces */
 715                         for (n = priv->data.slaves; n; n--, slave++)
 716                                 if (netif_running(slave->ndev))
 717                                         ndev_status = true;
 718                 }
 719
 720                 if (ndev_status && (status >= 0)) {
 721                         /* The packet received is for the interface which
 722                          * is already down and the other interface is up
 723                          * and running, instead of freeing which results
 724                          * in reducing of the number of rx descriptor in
 725                          * DMA engine, requeue skb back to cpdma.
 726                          */
 727                         new_skb = skb;
 728                         goto requeue;
 729                 }
 730
 731                 /* the interface is going down, skbs are purged */
 732                 dev_kfree_skb_any(skb);
 733                 return;
 734         }
 735
 736         new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
 737         if (new_skb) {
 738                 skb_put(skb, len);
 739                 cpts_rx_timestamp(priv->cpts, skb);
 740                 skb->protocol = eth_type_trans(skb, ndev);
 741                 netif_receive_skb(skb);
 742                 ndev->stats.rx_bytes += len;
 743                 ndev->stats.rx_packets++;
 744         } else {
 745                 ndev->stats.rx_dropped++;
 746                 new_skb = skb;
 747         }
 748
 749 requeue:
 750         ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
 751                         skb_tailroom(new_skb), 0);
 752         if (WARN_ON(ret < 0))
 753                 dev_kfree_skb_any(new_skb);
 754 }
 755
 756 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
 757 {
 758         struct cpsw_priv *priv = dev_id;
 759
 760         writel(0, &priv->wr_regs->tx_en);
 761         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
 762
 763         if (priv->quirk_irq) {
 764                 disable_irq_nosync(priv->irqs_table[1]);
 765                 priv->tx_irq_disabled = true;
 766         }
 767
 768         napi_schedule(&priv->napi_tx);
 769         return IRQ_HANDLED;
 770 }
 771
 772 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
 773 {
 774         struct cpsw_priv *priv = dev_id;
 775
 776         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
 777         writel(0, &priv->wr_regs->rx_en);
 778
 779         if (priv->quirk_irq) {
 780                 disable_irq_nosync(priv->irqs_table[0]);
 781                 priv->rx_irq_disabled = true;
 782         }
 783
 784         napi_schedule(&priv->napi_rx);
 785         return IRQ_HANDLED;
 786 }
 787
 788 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
 789 {
 790         struct cpsw_priv        *priv = napi_to_priv(napi_tx);
 791         int                     num_tx;
 792
 793         num_tx = cpdma_chan_process(priv->txch, budget);
 794         if (num_tx < budget) {
 795                 napi_complete(napi_tx);
 796                 writel(0xff, &priv->wr_regs->tx_en);
 797                 if (priv->quirk_irq && priv->tx_irq_disabled) {
 798                         priv->tx_irq_disabled = false;
 799                         enable_irq(priv->irqs_table[1]);
 800                 }
 801         }
 802
 803         if (num_tx)
 804                 cpsw_dbg(priv, intr, "poll %d tx pkts\n", num_tx);
 805
 806         return num_tx;
 807 }
 808
 809 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
 810 {
 811         struct cpsw_priv        *priv = napi_to_priv(napi_rx);
 812         int                     num_rx;
 813
 814         num_rx = cpdma_chan_process(priv->rxch, budget);
 815         if (num_rx < budget) {
 816                 napi_complete(napi_rx);
 817                 writel(0xff, &priv->wr_regs->rx_en);
 818                 if (priv->quirk_irq && priv->rx_irq_disabled) {
 819                         priv->rx_irq_disabled = false;
 820                         enable_irq(priv->irqs_table[0]);
 821                 }
 822         }
 823
 824         if (num_rx)
 825                 cpsw_dbg(priv, intr, "poll %d rx pkts\n", num_rx);
 826
 827         return num_rx;
 828 }
 829
 830 static inline void soft_reset(const char *module, void __iomem *reg)
 831 {
 832         unsigned long timeout = jiffies + HZ;
 833
 834         __raw_writel(1, reg);
 835         do {
 836                 cpu_relax();
 837         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
 838
 839         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
 840 }
 841
 842 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 843                          ((mac)[2] << 16) | ((mac)[3] << 24))
 844 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 845
 846 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 847                                struct cpsw_priv *priv)
 848 {
 849         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
 850         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
 851 }
 852
 853 static void _cpsw_adjust_link(struct cpsw_slave *slave,
 854                               struct cpsw_priv *priv, bool *link)
 855 {
 856         struct phy_device       *phy = slave->phy;
 857         u32                     mac_control = 0;
 858         u32                     slave_port;
 859
 860         if (!phy)
 861                 return;
 862
 863         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 864
 865         if (phy->link) {
 866                 mac_control = priv->data.mac_control;
 867
 868                 /* enable forwarding */
 869                 cpsw_ale_control_set(priv->ale, slave_port,
 870                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 871
 872                 if (phy->speed == 1000)
 873                         mac_control |= BIT(7);  /* GIGABITEN    */
 874                 if (phy->duplex)
 875                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
 876
 877                 /* set speed_in input in case RMII mode is used in 100Mbps */
 878                 if (phy->speed == 100)
 879                         mac_control |= BIT(15);
 880                 else if (phy->speed == 10)
 881                         mac_control |= BIT(18); /* In Band mode */
 882
 883                 if (priv->rx_pause)
 884                         mac_control |= BIT(3);
 885
 886                 if (priv->tx_pause)
 887                         mac_control |= BIT(4);
 888
 889                 *link = true;
 890         } else {
 891                 mac_control = 0;
 892                 /* disable forwarding */
 893                 cpsw_ale_control_set(priv->ale, slave_port,
 894                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
 895         }
 896
 897         if (mac_control != slave->mac_control) {
 898                 phy_print_status(phy);
 899                 __raw_writel(mac_control, &slave->sliver->mac_control);
 900         }
 901
 902         slave->mac_control = mac_control;
 903 }
 904
 905 static void cpsw_adjust_link(struct net_device *ndev)
 906 {
 907         struct cpsw_priv        *priv = netdev_priv(ndev);
 908         bool                    link = false;
 909
 910         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
 911
 912         if (link) {
 913                 netif_carrier_on(ndev);
 914                 if (netif_running(ndev))
 915                         netif_wake_queue(ndev);
 916         } else {
 917                 netif_carrier_off(ndev);
 918                 netif_stop_queue(ndev);
 919         }
 920 }
 921
 922 static int cpsw_get_coalesce(struct net_device *ndev,
 923                                 struct ethtool_coalesce *coal)
 924 {
 925         struct cpsw_priv *priv = netdev_priv(ndev);
 926
 927         coal->rx_coalesce_usecs = priv->coal_intvl;
 928         return 0;
 929 }
 930
 931 static int cpsw_set_coalesce(struct net_device *ndev,
 932                                 struct ethtool_coalesce *coal)
 933 {
 934         struct cpsw_priv *priv = netdev_priv(ndev);
 935         u32 int_ctrl;
 936         u32 num_interrupts = 0;
 937         u32 prescale = 0;
 938         u32 addnl_dvdr = 1;
 939         u32 coal_intvl = 0;
 940
 941         coal_intvl = coal->rx_coalesce_usecs;
 942
 943         int_ctrl =  readl(&priv->wr_regs->int_control);
 944         prescale = priv->bus_freq_mhz * 4;
 945
 946         if (!coal->rx_coalesce_usecs) {
 947                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
 948                 goto update_return;
 949         }
 950
 951         if (coal_intvl < CPSW_CMINTMIN_INTVL)
 952                 coal_intvl = CPSW_CMINTMIN_INTVL;
 953
 954         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
 955                 /* Interrupt pacer works with 4us Pulse, we can
 956                  * throttle further by dilating the 4us pulse.
 957                  */
 958                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
 959
 960                 if (addnl_dvdr > 1) {
 961                         prescale *= addnl_dvdr;
 962                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
 963                                 coal_intvl = (CPSW_CMINTMAX_INTVL
 964                                                 * addnl_dvdr);
 965                 } else {
 966                         addnl_dvdr = 1;
 967                         coal_intvl = CPSW_CMINTMAX_INTVL;
 968                 }
 969         }
 970
 971         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
 972         writel(num_interrupts, &priv->wr_regs->rx_imax);
 973         writel(num_interrupts, &priv->wr_regs->tx_imax);
 974
 975         int_ctrl |= CPSW_INTPACEEN;
 976         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
 977         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
 978
 979 update_return:
 980         writel(int_ctrl, &priv->wr_regs->int_control);
 981
 982         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
 983         if (priv->data.dual_emac) {
 984                 int i;
 985
 986                 for (i = 0; i < priv->data.slaves; i++) {
 987                         priv = netdev_priv(priv->slaves[i].ndev);
 988                         priv->coal_intvl = coal_intvl;
 989                 }
 990         } else {
 991                 priv->coal_intvl = coal_intvl;
 992         }
 993
 994         return 0;
 995 }
 996
 997 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
 998 {
 999         switch (sset) {
1000         case ETH_SS_STATS:
1001                 return CPSW_STATS_LEN;
1002         default:
1003                 return -EOPNOTSUPP;
1004         }
1005 }
1006
1007 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1008 {
1009         u8 *p = data;
1010         int i;
1011
1012         switch (stringset) {
1013         case ETH_SS_STATS:
1014                 for (i = 0; i < CPSW_STATS_LEN; i++) {
1015                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
1016                                ETH_GSTRING_LEN);
1017                         p += ETH_GSTRING_LEN;
1018                 }
1019                 break;
1020         }
1021 }
1022
1023 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1024                                     struct ethtool_stats *stats, u64 *data)
1025 {
1026         struct cpsw_priv *priv = netdev_priv(ndev);
1027         struct cpdma_chan_stats rx_stats;
1028         struct cpdma_chan_stats tx_stats;
1029         u32 val;
1030         u8 *p;
1031         int i;
1032
1033         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1034         cpdma_chan_get_stats(priv->rxch, &rx_stats);
1035         cpdma_chan_get_stats(priv->txch, &tx_stats);
1036
1037         for (i = 0; i < CPSW_STATS_LEN; i++) {
1038                 switch (cpsw_gstrings_stats[i].type) {
1039                 case CPSW_STATS:
1040                         val = readl(priv->hw_stats +
1041                                     cpsw_gstrings_stats[i].stat_offset);
1042                         data[i] = val;
1043                         break;
1044
1045                 case CPDMA_RX_STATS:
1046                         p = (u8 *)&rx_stats +
1047                                 cpsw_gstrings_stats[i].stat_offset;
1048                         data[i] = *(u32 *)p;
1049                         break;
1050
1051                 case CPDMA_TX_STATS:
1052                         p = (u8 *)&tx_stats +
1053                                 cpsw_gstrings_stats[i].stat_offset;
1054                         data[i] = *(u32 *)p;
1055                         break;
1056                 }
1057         }
1058 }
1059
1060 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1061 {
1062         u32 i;
1063         u32 usage_count = 0;
1064
1065         if (!priv->data.dual_emac)
1066                 return 0;
1067
1068         for (i = 0; i < priv->data.slaves; i++)
1069                 if (priv->slaves[i].open_stat)
1070                         usage_count++;
1071
1072         return usage_count;
1073 }
1074
1075 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1076                         struct cpsw_priv *priv, struct sk_buff *skb)
1077 {
1078         if (!priv->data.dual_emac)
1079                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1080                                   skb->len, 0);
1081
1082         if (ndev == cpsw_get_slave_ndev(priv, 0))
1083                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1084                                   skb->len, 1);
1085         else
1086                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1087                                   skb->len, 2);
1088 }
1089
1090 static inline void cpsw_add_dual_emac_def_ale_entries(
1091                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1092                 u32 slave_port)
1093 {
1094         u32 port_mask = 1 << slave_port | 1 << priv->host_port;
1095
1096         if (priv->version == CPSW_VERSION_1)
1097                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1098         else
1099                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1100         cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1101                           port_mask, port_mask, 0);
1102         cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1103                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1104         cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1105                 priv->host_port, ALE_VLAN | ALE_SECURE, slave->port_vlan);
1106 }
1107
1108 static void soft_reset_slave(struct cpsw_slave *slave)
1109 {
1110         char name[32];
1111
1112         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1113         soft_reset(name, &slave->sliver->soft_reset);
1114 }
1115
1116 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1117 {
1118         u32 slave_port;
1119
1120         soft_reset_slave(slave);
1121
1122         /* setup priority mapping */
1123         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1124
1125         switch (priv->version) {
1126         case CPSW_VERSION_1:
1127                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1128                 break;
1129         case CPSW_VERSION_2:
1130         case CPSW_VERSION_3:
1131         case CPSW_VERSION_4:
1132                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1133                 break;
1134         }
1135
1136         /* setup max packet size, and mac address */
1137         __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1138         cpsw_set_slave_mac(slave, priv);
1139
1140         slave->mac_control = 0; /* no link yet */
1141
1142         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1143
1144         if (priv->data.dual_emac)
1145                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1146         else
1147                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1148                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1149
1150         if (priv->phy_node)
1151                 slave->phy = of_phy_connect(priv->ndev, priv->phy_node,
1152                                  &cpsw_adjust_link, 0, slave->data->phy_if);
1153         else
1154                 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1155                                  &cpsw_adjust_link, slave->data->phy_if);
1156         if (IS_ERR(slave->phy)) {
1157                 dev_err(priv->dev, "phy %s not found on slave %d\n",
1158                         slave->data->phy_id, slave->slave_num);
1159                 slave->phy = NULL;
1160         } else {
1161                 dev_info(priv->dev, "phy found : id is : 0x%x\n",
1162                          slave->phy->phy_id);
1163                 phy_start(slave->phy);
1164
1165                 /* Configure GMII_SEL register */
1166                 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
1167                              slave->slave_num);
1168         }
1169 }
1170
1171 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1172 {
1173         const int vlan = priv->data.default_vlan;
1174         const int port = priv->host_port;
1175         u32 reg;
1176         int i;
1177         int unreg_mcast_mask;
1178
1179         reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1180                CPSW2_PORT_VLAN;
1181
1182         writel(vlan, &priv->host_port_regs->port_vlan);
1183
1184         for (i = 0; i < priv->data.slaves; i++)
1185                 slave_write(priv->slaves + i, vlan, reg);
1186
1187         if (priv->ndev->flags & IFF_ALLMULTI)
1188                 unreg_mcast_mask = ALE_ALL_PORTS;
1189         else
1190                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1191
1192         cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1193                           ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1194                           unreg_mcast_mask << port);
1195 }
1196
1197 static void cpsw_init_host_port(struct cpsw_priv *priv)
1198 {
1199         u32 control_reg;
1200         u32 fifo_mode;
1201
1202         /* soft reset the controller and initialize ale */
1203         soft_reset("cpsw", &priv->regs->soft_reset);
1204         cpsw_ale_start(priv->ale);
1205
1206         /* switch to vlan unaware mode */
1207         cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1208                              CPSW_ALE_VLAN_AWARE);
1209         control_reg = readl(&priv->regs->control);
1210         control_reg |= CPSW_VLAN_AWARE;
1211         writel(control_reg, &priv->regs->control);
1212         fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1213                      CPSW_FIFO_NORMAL_MODE;
1214         writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
1215
1216         /* setup host port priority mapping */
1217         __raw_writel(CPDMA_TX_PRIORITY_MAP,
1218                      &priv->host_port_regs->cpdma_tx_pri_map);
1219         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1220
1221         cpsw_ale_control_set(priv->ale, priv->host_port,
1222                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1223
1224         if (!priv->data.dual_emac) {
1225                 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1226                                    0, 0);
1227                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1228                                    1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1229         }
1230 }
1231
1232 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1233 {
1234         u32 slave_port;
1235
1236         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1237
1238         if (!slave->phy)
1239                 return;
1240         phy_stop(slave->phy);
1241         phy_disconnect(slave->phy);
1242         slave->phy = NULL;
1243         cpsw_ale_control_set(priv->ale, slave_port,
1244                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1245 }
1246
1247 static int cpsw_ndo_open(struct net_device *ndev)
1248 {
1249         struct cpsw_priv *priv = netdev_priv(ndev);
1250         int i, ret;
1251         u32 reg;
1252
1253         if (!cpsw_common_res_usage_state(priv))
1254                 cpsw_intr_disable(priv);
1255         netif_carrier_off(ndev);
1256
1257         pm_runtime_get_sync(&priv->pdev->dev);
1258
1259         reg = priv->version;
1260
1261         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1262                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1263                  CPSW_RTL_VERSION(reg));
1264
1265         /* initialize host and slave ports */
1266         if (!cpsw_common_res_usage_state(priv))
1267                 cpsw_init_host_port(priv);
1268         for_each_slave(priv, cpsw_slave_open, priv);
1269
1270         /* Add default VLAN */
1271         if (!priv->data.dual_emac)
1272                 cpsw_add_default_vlan(priv);
1273         else
1274                 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1275                                   ALE_ALL_PORTS << priv->host_port,
1276                                   ALE_ALL_PORTS << priv->host_port, 0, 0);
1277
1278         if (!cpsw_common_res_usage_state(priv)) {
1279                 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1280
1281                 /* setup tx dma to fixed prio and zero offset */
1282                 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1283                 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1284
1285                 /* disable priority elevation */
1286                 __raw_writel(0, &priv->regs->ptype);
1287
1288                 /* enable statistics collection only on all ports */
1289                 __raw_writel(0x7, &priv->regs->stat_port_en);
1290
1291                 /* Enable internal fifo flow control */
1292                 writel(0x7, &priv->regs->flow_control);
1293
1294                 napi_enable(&priv_sl0->napi_rx);
1295                 napi_enable(&priv_sl0->napi_tx);
1296
1297                 if (priv_sl0->tx_irq_disabled) {
1298                         priv_sl0->tx_irq_disabled = false;
1299                         enable_irq(priv->irqs_table[1]);
1300                 }
1301
1302                 if (priv_sl0->rx_irq_disabled) {
1303                         priv_sl0->rx_irq_disabled = false;
1304                         enable_irq(priv->irqs_table[0]);
1305                 }
1306
1307                 if (WARN_ON(!priv->data.rx_descs))
1308                         priv->data.rx_descs = 128;
1309
1310                 for (i = 0; i < priv->data.rx_descs; i++) {
1311                         struct sk_buff *skb;
1312
1313                         ret = -ENOMEM;
1314                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1315                                         priv->rx_packet_max, GFP_KERNEL);
1316                         if (!skb)
1317                                 goto err_cleanup;
1318                         ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
1319                                         skb_tailroom(skb), 0);
1320                         if (ret < 0) {
1321                                 kfree_skb(skb);
1322                                 goto err_cleanup;
1323                         }
1324                 }
1325                 /* continue even if we didn't manage to submit all
1326                  * receive descs
1327                  */
1328                 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
1329
1330                 if (cpts_register(&priv->pdev->dev, priv->cpts,
1331                                   priv->data.cpts_clock_mult,
1332                                   priv->data.cpts_clock_shift))
1333                         dev_err(priv->dev, "error registering cpts device\n");
1334
1335         }
1336
1337         /* Enable Interrupt pacing if configured */
1338         if (priv->coal_intvl != 0) {
1339                 struct ethtool_coalesce coal;
1340
1341                 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1342                 cpsw_set_coalesce(ndev, &coal);
1343         }
1344
1345         cpdma_ctlr_start(priv->dma);
1346         cpsw_intr_enable(priv);
1347
1348         if (priv->data.dual_emac)
1349                 priv->slaves[priv->emac_port].open_stat = true;
1350         return 0;
1351
1352 err_cleanup:
1353         cpdma_ctlr_stop(priv->dma);
1354         for_each_slave(priv, cpsw_slave_stop, priv);
1355         pm_runtime_put_sync(&priv->pdev->dev);
1356         netif_carrier_off(priv->ndev);
1357         return ret;
1358 }
1359
1360 static int cpsw_ndo_stop(struct net_device *ndev)
1361 {
1362         struct cpsw_priv *priv = netdev_priv(ndev);
1363
1364         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1365         netif_stop_queue(priv->ndev);
1366         netif_carrier_off(priv->ndev);
1367
1368         if (cpsw_common_res_usage_state(priv) <= 1) {
1369                 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1370
1371                 napi_disable(&priv_sl0->napi_rx);
1372                 napi_disable(&priv_sl0->napi_tx);
1373                 cpts_unregister(priv->cpts);
1374                 cpsw_intr_disable(priv);
1375                 cpdma_ctlr_stop(priv->dma);
1376                 cpsw_ale_stop(priv->ale);
1377         }
1378         for_each_slave(priv, cpsw_slave_stop, priv);
1379         pm_runtime_put_sync(&priv->pdev->dev);
1380         if (priv->data.dual_emac)
1381                 priv->slaves[priv->emac_port].open_stat = false;
1382         return 0;
1383 }
1384
1385 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1386                                        struct net_device *ndev)
1387 {
1388         struct cpsw_priv *priv = netdev_priv(ndev);
1389         int ret;
1390
1391         ndev->trans_start = jiffies;
1392
1393         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1394                 cpsw_err(priv, tx_err, "packet pad failed\n");
1395                 ndev->stats.tx_dropped++;
1396                 return NETDEV_TX_OK;
1397         }
1398
1399         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1400                                 priv->cpts->tx_enable)
1401                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1402
1403         skb_tx_timestamp(skb);
1404
1405         ret = cpsw_tx_packet_submit(ndev, priv, skb);
1406         if (unlikely(ret != 0)) {
1407                 cpsw_err(priv, tx_err, "desc submit failed\n");
1408                 goto fail;
1409         }
1410
1411         /* If there is no more tx desc left free then we need to
1412          * tell the kernel to stop sending us tx frames.
1413          */
1414         if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1415                 netif_stop_queue(ndev);
1416
1417         return NETDEV_TX_OK;
1418 fail:
1419         ndev->stats.tx_dropped++;
1420         netif_stop_queue(ndev);
1421         return NETDEV_TX_BUSY;
1422 }
1423
1424 #ifdef CONFIG_TI_CPTS
1425
1426 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1427 {
1428         struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1429         u32 ts_en, seq_id;
1430
1431         if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1432                 slave_write(slave, 0, CPSW1_TS_CTL);
1433                 return;
1434         }
1435
1436         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1437         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1438
1439         if (priv->cpts->tx_enable)
1440                 ts_en |= CPSW_V1_TS_TX_EN;
1441
1442         if (priv->cpts->rx_enable)
1443                 ts_en |= CPSW_V1_TS_RX_EN;
1444
1445         slave_write(slave, ts_en, CPSW1_TS_CTL);
1446         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1447 }
1448
1449 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1450 {
1451         struct cpsw_slave *slave;
1452         u32 ctrl, mtype;
1453
1454         if (priv->data.dual_emac)
1455                 slave = &priv->slaves[priv->emac_port];
1456         else
1457                 slave = &priv->slaves[priv->data.active_slave];
1458
1459         ctrl = slave_read(slave, CPSW2_CONTROL);
1460         switch (priv->version) {
1461         case CPSW_VERSION_2:
1462                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1463
1464                 if (priv->cpts->tx_enable)
1465                         ctrl |= CTRL_V2_TX_TS_BITS;
1466
1467                 if (priv->cpts->rx_enable)
1468                         ctrl |= CTRL_V2_RX_TS_BITS;
1469                 break;
1470         case CPSW_VERSION_3:
1471         default:
1472                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1473
1474                 if (priv->cpts->tx_enable)
1475                         ctrl |= CTRL_V3_TX_TS_BITS;
1476
1477                 if (priv->cpts->rx_enable)
1478                         ctrl |= CTRL_V3_RX_TS_BITS;
1479                 break;
1480         }
1481
1482         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1483
1484         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1485         slave_write(slave, ctrl, CPSW2_CONTROL);
1486         __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1487 }
1488
1489 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1490 {
1491         struct cpsw_priv *priv = netdev_priv(dev);
1492         struct cpts *cpts = priv->cpts;
1493         struct hwtstamp_config cfg;
1494
1495         if (priv->version != CPSW_VERSION_1 &&
1496             priv->version != CPSW_VERSION_2 &&
1497             priv->version != CPSW_VERSION_3)
1498                 return -EOPNOTSUPP;
1499
1500         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1501                 return -EFAULT;
1502
1503         /* reserved for future extensions */
1504         if (cfg.flags)
1505                 return -EINVAL;
1506
1507         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1508                 return -ERANGE;
1509
1510         switch (cfg.rx_filter) {
1511         case HWTSTAMP_FILTER_NONE:
1512                 cpts->rx_enable = 0;
1513                 break;
1514         case HWTSTAMP_FILTER_ALL:
1515         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1516         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1517         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1518                 return -ERANGE;
1519         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1520         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1521         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1522         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1523         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1524         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1525         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1526         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1527         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1528                 cpts->rx_enable = 1;
1529                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1530                 break;
1531         default:
1532                 return -ERANGE;
1533         }
1534
1535         cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1536
1537         switch (priv->version) {
1538         case CPSW_VERSION_1:
1539                 cpsw_hwtstamp_v1(priv);
1540                 break;
1541         case CPSW_VERSION_2:
1542         case CPSW_VERSION_3:
1543                 cpsw_hwtstamp_v2(priv);
1544                 break;
1545         default:
1546                 WARN_ON(1);
1547         }
1548
1549         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1550 }
1551
1552 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1553 {
1554         struct cpsw_priv *priv = netdev_priv(dev);
1555         struct cpts *cpts = priv->cpts;
1556         struct hwtstamp_config cfg;
1557
1558         if (priv->version != CPSW_VERSION_1 &&
1559             priv->version != CPSW_VERSION_2 &&
1560             priv->version != CPSW_VERSION_3)
1561                 return -EOPNOTSUPP;
1562
1563         cfg.flags = 0;
1564         cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1565         cfg.rx_filter = (cpts->rx_enable ?
1566                          HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1567
1568         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1569 }
1570
1571 #endif /*CONFIG_TI_CPTS*/
1572
1573 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1574 {
1575         struct cpsw_priv *priv = netdev_priv(dev);
1576         int slave_no = cpsw_slave_index(priv);
1577
1578         if (!netif_running(dev))
1579                 return -EINVAL;
1580
1581         switch (cmd) {
1582 #ifdef CONFIG_TI_CPTS
1583         case SIOCSHWTSTAMP:
1584                 return cpsw_hwtstamp_set(dev, req);
1585         case SIOCGHWTSTAMP:
1586                 return cpsw_hwtstamp_get(dev, req);
1587 #endif
1588         }
1589
1590         if (!priv->slaves[slave_no].phy)
1591                 return -EOPNOTSUPP;
1592         return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
1593 }
1594
1595 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1596 {
1597         struct cpsw_priv *priv = netdev_priv(ndev);
1598
1599         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1600         ndev->stats.tx_errors++;
1601         cpsw_intr_disable(priv);
1602         cpdma_chan_stop(priv->txch);
1603         cpdma_chan_start(priv->txch);
1604         cpsw_intr_enable(priv);
1605 }
1606
1607 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1608 {
1609         struct cpsw_priv *priv = netdev_priv(ndev);
1610         struct sockaddr *addr = (struct sockaddr *)p;
1611         int flags = 0;
1612         u16 vid = 0;
1613
1614         if (!is_valid_ether_addr(addr->sa_data))
1615                 return -EADDRNOTAVAIL;
1616
1617         if (priv->data.dual_emac) {
1618                 vid = priv->slaves[priv->emac_port].port_vlan;
1619                 flags = ALE_VLAN;
1620         }
1621
1622         cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1623                            flags, vid);
1624         cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1625                            flags, vid);
1626
1627         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1628         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1629         for_each_slave(priv, cpsw_set_slave_mac, priv);
1630
1631         return 0;
1632 }
1633
1634 #ifdef CONFIG_NET_POLL_CONTROLLER
1635 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1636 {
1637         struct cpsw_priv *priv = netdev_priv(ndev);
1638
1639         cpsw_intr_disable(priv);
1640         cpsw_rx_interrupt(priv->irqs_table[0], priv);
1641         cpsw_tx_interrupt(priv->irqs_table[1], priv);
1642         cpsw_intr_enable(priv);
1643 }
1644 #endif
1645
1646 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1647                                 unsigned short vid)
1648 {
1649         int ret;
1650         int unreg_mcast_mask = 0;
1651         u32 port_mask;
1652
1653         if (priv->data.dual_emac) {
1654                 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1655
1656                 if (priv->ndev->flags & IFF_ALLMULTI)
1657                         unreg_mcast_mask = port_mask;
1658         } else {
1659                 port_mask = ALE_ALL_PORTS;
1660
1661                 if (priv->ndev->flags & IFF_ALLMULTI)
1662                         unreg_mcast_mask = ALE_ALL_PORTS;
1663                 else
1664                         unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1665         }
1666
1667         ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask,
1668                                 unreg_mcast_mask << priv->host_port);
1669         if (ret != 0)
1670                 return ret;
1671
1672         ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1673                                  priv->host_port, ALE_VLAN, vid);
1674         if (ret != 0)
1675                 goto clean_vid;
1676
1677         ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1678                                  port_mask, ALE_VLAN, vid, 0);
1679         if (ret != 0)
1680                 goto clean_vlan_ucast;
1681         return 0;
1682
1683 clean_vlan_ucast:
1684         cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1685                             priv->host_port, ALE_VLAN, vid);
1686 clean_vid:
1687         cpsw_ale_del_vlan(priv->ale, vid, 0);
1688         return ret;
1689 }
1690
1691 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1692                                     __be16 proto, u16 vid)
1693 {
1694         struct cpsw_priv *priv = netdev_priv(ndev);
1695
1696         if (vid == priv->data.default_vlan)
1697                 return 0;
1698
1699         if (priv->data.dual_emac) {
1700                 /* In dual EMAC, reserved VLAN id should not be used for
1701                  * creating VLAN interfaces as this can break the dual
1702                  * EMAC port separation
1703                  */
1704                 int i;
1705
1706                 for (i = 0; i < priv->data.slaves; i++) {
1707                         if (vid == priv->slaves[i].port_vlan)
1708                                 return -EINVAL;
1709                 }
1710         }
1711
1712         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1713         return cpsw_add_vlan_ale_entry(priv, vid);
1714 }
1715
1716 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1717                                      __be16 proto, u16 vid)
1718 {
1719         struct cpsw_priv *priv = netdev_priv(ndev);
1720         int ret;
1721
1722         if (vid == priv->data.default_vlan)
1723                 return 0;
1724
1725         if (priv->data.dual_emac) {
1726                 int i;
1727
1728                 for (i = 0; i < priv->data.slaves; i++) {
1729                         if (vid == priv->slaves[i].port_vlan)
1730                                 return -EINVAL;
1731                 }
1732         }
1733
1734         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1735         ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1736         if (ret != 0)
1737                 return ret;
1738
1739         ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1740                                  priv->host_port, ALE_VLAN, vid);
1741         if (ret != 0)
1742                 return ret;
1743
1744         return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1745                                   0, ALE_VLAN, vid);
1746 }
1747
1748 static const struct net_device_ops cpsw_netdev_ops = {
1749         .ndo_open               = cpsw_ndo_open,
1750         .ndo_stop               = cpsw_ndo_stop,
1751         .ndo_start_xmit         = cpsw_ndo_start_xmit,
1752         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
1753         .ndo_do_ioctl           = cpsw_ndo_ioctl,
1754         .ndo_validate_addr      = eth_validate_addr,
1755         .ndo_change_mtu         = eth_change_mtu,
1756         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
1757         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
1758 #ifdef CONFIG_NET_POLL_CONTROLLER
1759         .ndo_poll_controller    = cpsw_ndo_poll_controller,
1760 #endif
1761         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
1762         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
1763 };
1764
1765 static int cpsw_get_regs_len(struct net_device *ndev)
1766 {
1767         struct cpsw_priv *priv = netdev_priv(ndev);
1768
1769         return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1770 }
1771
1772 static void cpsw_get_regs(struct net_device *ndev,
1773                           struct ethtool_regs *regs, void *p)
1774 {
1775         struct cpsw_priv *priv = netdev_priv(ndev);
1776         u32 *reg = p;
1777
1778         /* update CPSW IP version */
1779         regs->version = priv->version;
1780
1781         cpsw_ale_dump(priv->ale, reg);
1782 }
1783
1784 static void cpsw_get_drvinfo(struct net_device *ndev,
1785                              struct ethtool_drvinfo *info)
1786 {
1787         struct cpsw_priv *priv = netdev_priv(ndev);
1788
1789         strlcpy(info->driver, "cpsw", sizeof(info->driver));
1790         strlcpy(info->version, "1.0", sizeof(info->version));
1791         strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1792         info->regdump_len = cpsw_get_regs_len(ndev);
1793 }
1794
1795 static u32 cpsw_get_msglevel(struct net_device *ndev)
1796 {
1797         struct cpsw_priv *priv = netdev_priv(ndev);
1798         return priv->msg_enable;
1799 }
1800
1801 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1802 {
1803         struct cpsw_priv *priv = netdev_priv(ndev);
1804         priv->msg_enable = value;
1805 }
1806
1807 static int cpsw_get_ts_info(struct net_device *ndev,
1808                             struct ethtool_ts_info *info)
1809 {
1810 #ifdef CONFIG_TI_CPTS
1811         struct cpsw_priv *priv = netdev_priv(ndev);
1812
1813         info->so_timestamping =
1814                 SOF_TIMESTAMPING_TX_HARDWARE |
1815                 SOF_TIMESTAMPING_TX_SOFTWARE |
1816                 SOF_TIMESTAMPING_RX_HARDWARE |
1817                 SOF_TIMESTAMPING_RX_SOFTWARE |
1818                 SOF_TIMESTAMPING_SOFTWARE |
1819                 SOF_TIMESTAMPING_RAW_HARDWARE;
1820         info->phc_index = priv->cpts->phc_index;
1821         info->tx_types =
1822                 (1 << HWTSTAMP_TX_OFF) |
1823                 (1 << HWTSTAMP_TX_ON);
1824         info->rx_filters =
1825                 (1 << HWTSTAMP_FILTER_NONE) |
1826                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1827 #else
1828         info->so_timestamping =
1829                 SOF_TIMESTAMPING_TX_SOFTWARE |
1830                 SOF_TIMESTAMPING_RX_SOFTWARE |
1831                 SOF_TIMESTAMPING_SOFTWARE;
1832         info->phc_index = -1;
1833         info->tx_types = 0;
1834         info->rx_filters = 0;
1835 #endif
1836         return 0;
1837 }
1838
1839 static int cpsw_get_settings(struct net_device *ndev,
1840                              struct ethtool_cmd *ecmd)
1841 {
1842         struct cpsw_priv *priv = netdev_priv(ndev);
1843         int slave_no = cpsw_slave_index(priv);
1844
1845         if (priv->slaves[slave_no].phy)
1846                 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1847         else
1848                 return -EOPNOTSUPP;
1849 }
1850
1851 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1852 {
1853         struct cpsw_priv *priv = netdev_priv(ndev);
1854         int slave_no = cpsw_slave_index(priv);
1855
1856         if (priv->slaves[slave_no].phy)
1857                 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1858         else
1859                 return -EOPNOTSUPP;
1860 }
1861
1862 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1863 {
1864         struct cpsw_priv *priv = netdev_priv(ndev);
1865         int slave_no = cpsw_slave_index(priv);
1866
1867         wol->supported = 0;
1868         wol->wolopts = 0;
1869
1870         if (priv->slaves[slave_no].phy)
1871                 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1872 }
1873
1874 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1875 {
1876         struct cpsw_priv *priv = netdev_priv(ndev);
1877         int slave_no = cpsw_slave_index(priv);
1878
1879         if (priv->slaves[slave_no].phy)
1880                 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1881         else
1882                 return -EOPNOTSUPP;
1883 }
1884
1885 static void cpsw_get_pauseparam(struct net_device *ndev,
1886                                 struct ethtool_pauseparam *pause)
1887 {
1888         struct cpsw_priv *priv = netdev_priv(ndev);
1889
1890         pause->autoneg = AUTONEG_DISABLE;
1891         pause->rx_pause = priv->rx_pause ? true : false;
1892         pause->tx_pause = priv->tx_pause ? true : false;
1893 }
1894
1895 static int cpsw_set_pauseparam(struct net_device *ndev,
1896                                struct ethtool_pauseparam *pause)
1897 {
1898         struct cpsw_priv *priv = netdev_priv(ndev);
1899         bool link;
1900
1901         priv->rx_pause = pause->rx_pause ? true : false;
1902         priv->tx_pause = pause->tx_pause ? true : false;
1903
1904         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1905
1906         return 0;
1907 }
1908
1909 static const struct ethtool_ops cpsw_ethtool_ops = {
1910         .get_drvinfo    = cpsw_get_drvinfo,
1911         .get_msglevel   = cpsw_get_msglevel,
1912         .set_msglevel   = cpsw_set_msglevel,
1913         .get_link       = ethtool_op_get_link,
1914         .get_ts_info    = cpsw_get_ts_info,
1915         .get_settings   = cpsw_get_settings,
1916         .set_settings   = cpsw_set_settings,
1917         .get_coalesce   = cpsw_get_coalesce,
1918         .set_coalesce   = cpsw_set_coalesce,
1919         .get_sset_count         = cpsw_get_sset_count,
1920         .get_strings            = cpsw_get_strings,
1921         .get_ethtool_stats      = cpsw_get_ethtool_stats,
1922         .get_pauseparam         = cpsw_get_pauseparam,
1923         .set_pauseparam         = cpsw_set_pauseparam,
1924         .get_wol        = cpsw_get_wol,
1925         .set_wol        = cpsw_set_wol,
1926         .get_regs_len   = cpsw_get_regs_len,
1927         .get_regs       = cpsw_get_regs,
1928 };
1929
1930 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1931                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
1932 {
1933         void __iomem            *regs = priv->regs;
1934         int                     slave_num = slave->slave_num;
1935         struct cpsw_slave_data  *data = priv->data.slave_data + slave_num;
1936
1937         slave->data     = data;
1938         slave->regs     = regs + slave_reg_ofs;
1939         slave->sliver   = regs + sliver_reg_ofs;
1940         slave->port_vlan = data->dual_emac_res_vlan;
1941 }
1942
1943 static int cpsw_probe_dt(struct cpsw_priv *priv,
1944                          struct platform_device *pdev)
1945 {
1946         struct device_node *node = pdev->dev.of_node;
1947         struct device_node *slave_node;
1948         struct cpsw_platform_data *data = &priv->data;
1949         int i = 0, ret;
1950         u32 prop;
1951
1952         if (!node)
1953                 return -EINVAL;
1954
1955         if (of_property_read_u32(node, "slaves", &prop)) {
1956                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
1957                 return -EINVAL;
1958         }
1959         data->slaves = prop;
1960
1961         if (of_property_read_u32(node, "active_slave", &prop)) {
1962                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
1963                 return -EINVAL;
1964         }
1965         data->active_slave = prop;
1966
1967         if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1968                 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
1969                 return -EINVAL;
1970         }
1971         data->cpts_clock_mult = prop;
1972
1973         if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1974                 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
1975                 return -EINVAL;
1976         }
1977         data->cpts_clock_shift = prop;
1978
1979         data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1980                                         * sizeof(struct cpsw_slave_data),
1981                                         GFP_KERNEL);
1982         if (!data->slave_data)
1983                 return -ENOMEM;
1984
1985         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1986                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
1987                 return -EINVAL;
1988         }
1989         data->channels = prop;
1990
1991         if (of_property_read_u32(node, "ale_entries", &prop)) {
1992                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
1993                 return -EINVAL;
1994         }
1995         data->ale_entries = prop;
1996
1997         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1998                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
1999                 return -EINVAL;
2000         }
2001         data->bd_ram_size = prop;
2002
2003         if (of_property_read_u32(node, "rx_descs", &prop)) {
2004                 dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
2005                 return -EINVAL;
2006         }
2007         data->rx_descs = prop;
2008
2009         if (of_property_read_u32(node, "mac_control", &prop)) {
2010                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2011                 return -EINVAL;
2012         }
2013         data->mac_control = prop;
2014
2015         if (of_property_read_bool(node, "dual_emac"))
2016                 data->dual_emac = 1;
2017
2018         /*
2019          * Populate all the child nodes here...
2020          */
2021         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2022         /* We do not want to force this, as in some cases may not have child */
2023         if (ret)
2024                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2025
2026         for_each_child_of_node(node, slave_node) {
2027                 struct cpsw_slave_data *slave_data = data->slave_data + i;
2028                 const void *mac_addr = NULL;
2029                 u32 phyid;
2030                 int lenp;
2031                 const __be32 *parp;
2032                 struct device_node *mdio_node;
2033                 struct platform_device *mdio;
2034
2035                 /* This is no slave child node, continue */
2036                 if (strcmp(slave_node->name, "slave"))
2037                         continue;
2038
2039                 priv->phy_node = of_parse_phandle(slave_node, "phy-handle", 0);
2040                 parp = of_get_property(slave_node, "phy_id", &lenp);
2041                 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
2042                         dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i);
2043                         goto no_phy_slave;
2044                 }
2045                 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2046                 phyid = be32_to_cpup(parp+1);
2047                 mdio = of_find_device_by_node(mdio_node);
2048                 of_node_put(mdio_node);
2049                 if (!mdio) {
2050                         dev_err(&pdev->dev, "Missing mdio platform device\n");
2051                         return -EINVAL;
2052                 }
2053                 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2054                          PHY_ID_FMT, mdio->name, phyid);
2055                 slave_data->phy_if = of_get_phy_mode(slave_node);
2056                 if (slave_data->phy_if < 0) {
2057                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2058                                 i);
2059                         return slave_data->phy_if;
2060                 }
2061
2062 no_phy_slave:
2063                 mac_addr = of_get_mac_address(slave_node);
2064                 if (mac_addr) {
2065                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2066                 } else {
2067                         if (of_machine_is_compatible("ti,am33xx")) {
2068                                 ret = cpsw_am33xx_cm_get_macid(&pdev->dev,
2069                                                         0x630, i,
2070                                                         slave_data->mac_addr);
2071                                 if (ret)
2072                                         return ret;
2073                         }
2074                 }
2075                 if (data->dual_emac) {
2076                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2077                                                  &prop)) {
2078                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2079                                 slave_data->dual_emac_res_vlan = i+1;
2080                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2081                                         slave_data->dual_emac_res_vlan, i);
2082                         } else {
2083                                 slave_data->dual_emac_res_vlan = prop;
2084                         }
2085                 }
2086
2087                 i++;
2088                 if (i == data->slaves)
2089                         break;
2090         }
2091
2092         return 0;
2093 }
2094
2095 static int cpsw_probe_dual_emac(struct platform_device *pdev,
2096                                 struct cpsw_priv *priv)
2097 {
2098         struct cpsw_platform_data       *data = &priv->data;
2099         struct net_device               *ndev;
2100         struct cpsw_priv                *priv_sl2;
2101         int ret = 0, i;
2102
2103         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2104         if (!ndev) {
2105                 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
2106                 return -ENOMEM;
2107         }
2108
2109         priv_sl2 = netdev_priv(ndev);
2110         spin_lock_init(&priv_sl2->lock);
2111         priv_sl2->data = *data;
2112         priv_sl2->pdev = pdev;
2113         priv_sl2->ndev = ndev;
2114         priv_sl2->dev  = &ndev->dev;
2115         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2116         priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2117
2118         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2119                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2120                         ETH_ALEN);
2121                 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
2122         } else {
2123                 random_ether_addr(priv_sl2->mac_addr);
2124                 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
2125         }
2126         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2127
2128         priv_sl2->slaves = priv->slaves;
2129         priv_sl2->clk = priv->clk;
2130
2131         priv_sl2->coal_intvl = 0;
2132         priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2133
2134         priv_sl2->regs = priv->regs;
2135         priv_sl2->host_port = priv->host_port;
2136         priv_sl2->host_port_regs = priv->host_port_regs;
2137         priv_sl2->wr_regs = priv->wr_regs;
2138         priv_sl2->hw_stats = priv->hw_stats;
2139         priv_sl2->dma = priv->dma;
2140         priv_sl2->txch = priv->txch;
2141         priv_sl2->rxch = priv->rxch;
2142         priv_sl2->ale = priv->ale;
2143         priv_sl2->emac_port = 1;
2144         priv->slaves[1].ndev = ndev;
2145         priv_sl2->cpts = priv->cpts;
2146         priv_sl2->version = priv->version;
2147
2148         for (i = 0; i < priv->num_irqs; i++) {
2149                 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2150                 priv_sl2->num_irqs = priv->num_irqs;
2151         }
2152         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2153
2154         ndev->netdev_ops = &cpsw_netdev_ops;
2155         ndev->ethtool_ops = &cpsw_ethtool_ops;
2156
2157         /* register the network device */
2158         SET_NETDEV_DEV(ndev, &pdev->dev);
2159         ret = register_netdev(ndev);
2160         if (ret) {
2161                 dev_err(&pdev->dev, "cpsw: error registering net device\n");
2162                 free_netdev(ndev);
2163                 ret = -ENODEV;
2164         }
2165
2166         return ret;
2167 }
2168
2169 #define CPSW_QUIRK_IRQ          BIT(0)
2170
2171 static struct platform_device_id cpsw_devtype[] = {
2172         {
2173                 /* keep it for existing comaptibles */
2174                 .name = "cpsw",
2175                 .driver_data = CPSW_QUIRK_IRQ,
2176         }, {
2177                 .name = "am335x-cpsw",
2178                 .driver_data = CPSW_QUIRK_IRQ,
2179         }, {
2180                 .name = "am4372-cpsw",
2181                 .driver_data = 0,
2182         }, {
2183                 .name = "dra7-cpsw",
2184                 .driver_data = 0,
2185         }, {
2186                 /* sentinel */
2187         }
2188 };
2189 MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2190
2191 enum ti_cpsw_type {
2192         CPSW = 0,
2193         AM335X_CPSW,
2194         AM4372_CPSW,
2195         DRA7_CPSW,
2196 };
2197
2198 static const struct of_device_id cpsw_of_mtable[] = {
2199         { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2200         { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2201         { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2202         { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2203         { /* sentinel */ },
2204 };
2205 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2206
2207 static int cpsw_probe(struct platform_device *pdev)
2208 {
2209         struct cpsw_platform_data       *data;
2210         struct net_device               *ndev;
2211         struct cpsw_priv                *priv;
2212         struct cpdma_params             dma_params;
2213         struct cpsw_ale_params          ale_params;
2214         void __iomem                    *ss_regs;
2215         struct resource                 *res, *ss_res;
2216         const struct of_device_id       *of_id;
2217         u32 slave_offset, sliver_offset, slave_size;
2218         int ret = 0, i;
2219         int irq;
2220
2221         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2222         if (!ndev) {
2223                 dev_err(&pdev->dev, "error allocating net_device\n");
2224                 return -ENOMEM;
2225         }
2226
2227         platform_set_drvdata(pdev, ndev);
2228         priv = netdev_priv(ndev);
2229         spin_lock_init(&priv->lock);
2230         priv->pdev = pdev;
2231         priv->ndev = ndev;
2232         priv->dev  = &ndev->dev;
2233         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2234         priv->rx_packet_max = max(rx_packet_max, 128);
2235         priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2236         if (!priv->cpts) {
2237                 dev_err(&pdev->dev, "error allocating cpts\n");
2238                 ret = -ENOMEM;
2239                 goto clean_ndev_ret;
2240         }
2241
2242         /*
2243          * This may be required here for child devices.
2244          */
2245         pm_runtime_enable(&pdev->dev);
2246
2247         /* Select default pin state */
2248         pinctrl_pm_select_default_state(&pdev->dev);
2249
2250         if (cpsw_probe_dt(priv, pdev)) {
2251                 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2252                 ret = -ENODEV;
2253                 goto clean_runtime_disable_ret;
2254         }
2255         data = &priv->data;
2256
2257         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2258                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2259                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2260         } else {
2261                 eth_random_addr(priv->mac_addr);
2262                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2263         }
2264
2265         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2266
2267         priv->slaves = devm_kzalloc(&pdev->dev,
2268                                     sizeof(struct cpsw_slave) * data->slaves,
2269                                     GFP_KERNEL);
2270         if (!priv->slaves) {
2271                 ret = -ENOMEM;
2272                 goto clean_runtime_disable_ret;
2273         }
2274         for (i = 0; i < data->slaves; i++)
2275                 priv->slaves[i].slave_num = i;
2276
2277         priv->slaves[0].ndev = ndev;
2278         priv->emac_port = 0;
2279
2280         priv->clk = devm_clk_get(&pdev->dev, "fck");
2281         if (IS_ERR(priv->clk)) {
2282                 dev_err(priv->dev, "fck is not found\n");
2283                 ret = -ENODEV;
2284                 goto clean_runtime_disable_ret;
2285         }
2286         priv->coal_intvl = 0;
2287         priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
2288
2289         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2290         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2291         if (IS_ERR(ss_regs)) {
2292                 ret = PTR_ERR(ss_regs);
2293                 goto clean_runtime_disable_ret;
2294         }
2295         priv->regs = ss_regs;
2296         priv->host_port = HOST_PORT_NUM;
2297
2298         /* Need to enable clocks with runtime PM api to access module
2299          * registers
2300          */
2301         pm_runtime_get_sync(&pdev->dev);
2302         priv->version = readl(&priv->regs->id_ver);
2303         pm_runtime_put_sync(&pdev->dev);
2304
2305         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2306         priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2307         if (IS_ERR(priv->wr_regs)) {
2308                 ret = PTR_ERR(priv->wr_regs);
2309                 goto clean_runtime_disable_ret;
2310         }
2311
2312         memset(&dma_params, 0, sizeof(dma_params));
2313         memset(&ale_params, 0, sizeof(ale_params));
2314
2315         switch (priv->version) {
2316         case CPSW_VERSION_1:
2317                 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2318                 priv->cpts->reg      = ss_regs + CPSW1_CPTS_OFFSET;
2319                 priv->hw_stats       = ss_regs + CPSW1_HW_STATS;
2320                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
2321                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
2322                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
2323                 slave_offset         = CPSW1_SLAVE_OFFSET;
2324                 slave_size           = CPSW1_SLAVE_SIZE;
2325                 sliver_offset        = CPSW1_SLIVER_OFFSET;
2326                 dma_params.desc_mem_phys = 0;
2327                 break;
2328         case CPSW_VERSION_2:
2329         case CPSW_VERSION_3:
2330         case CPSW_VERSION_4:
2331                 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2332                 priv->cpts->reg      = ss_regs + CPSW2_CPTS_OFFSET;
2333                 priv->hw_stats       = ss_regs + CPSW2_HW_STATS;
2334                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
2335                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
2336                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
2337                 slave_offset         = CPSW2_SLAVE_OFFSET;
2338                 slave_size           = CPSW2_SLAVE_SIZE;
2339                 sliver_offset        = CPSW2_SLIVER_OFFSET;
2340                 dma_params.desc_mem_phys =
2341                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2342                 break;
2343         default:
2344                 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2345                 ret = -ENODEV;
2346                 goto clean_runtime_disable_ret;
2347         }
2348         for (i = 0; i < priv->data.slaves; i++) {
2349                 struct cpsw_slave *slave = &priv->slaves[i];
2350                 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2351                 slave_offset  += slave_size;
2352                 sliver_offset += SLIVER_SIZE;
2353         }
2354
2355         dma_params.dev          = &pdev->dev;
2356         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
2357         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
2358         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
2359         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
2360         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
2361
2362         dma_params.num_chan             = data->channels;
2363         dma_params.has_soft_reset       = true;
2364         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
2365         dma_params.desc_mem_size        = data->bd_ram_size;
2366         dma_params.desc_align           = 16;
2367         dma_params.has_ext_regs         = true;
2368         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
2369
2370         priv->dma = cpdma_ctlr_create(&dma_params);
2371         if (!priv->dma) {
2372                 dev_err(priv->dev, "error initializing dma\n");
2373                 ret = -ENOMEM;
2374                 goto clean_runtime_disable_ret;
2375         }
2376
2377         priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2378                                        cpsw_tx_handler);
2379         priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2380                                        cpsw_rx_handler);
2381
2382         if (WARN_ON(!priv->txch || !priv->rxch)) {
2383                 dev_err(priv->dev, "error initializing dma channels\n");
2384                 ret = -ENOMEM;
2385                 goto clean_dma_ret;
2386         }
2387
2388         ale_params.dev                  = &ndev->dev;
2389         ale_params.ale_ageout           = ale_ageout;
2390         ale_params.ale_entries          = data->ale_entries;
2391         ale_params.ale_ports            = data->slaves;
2392
2393         priv->ale = cpsw_ale_create(&ale_params);
2394         if (!priv->ale) {
2395                 dev_err(priv->dev, "error initializing ale engine\n");
2396                 ret = -ENODEV;
2397                 goto clean_dma_ret;
2398         }
2399
2400         ndev->irq = platform_get_irq(pdev, 1);
2401         if (ndev->irq < 0) {
2402                 dev_err(priv->dev, "error getting irq resource\n");
2403                 ret = -ENOENT;
2404                 goto clean_ale_ret;
2405         }
2406
2407         of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
2408         if (of_id) {
2409                 pdev->id_entry = of_id->data;
2410                 if (pdev->id_entry->driver_data)
2411                         priv->quirk_irq = true;
2412         }
2413
2414         /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2415          * MISC IRQs which are always kept disabled with this driver so
2416          * we will not request them.
2417          *
2418          * If anyone wants to implement support for those, make sure to
2419          * first request and append them to irqs_table array.
2420          */
2421
2422         /* RX IRQ */
2423         irq = platform_get_irq(pdev, 1);
2424         if (irq < 0)
2425                 goto clean_ale_ret;
2426
2427         priv->irqs_table[0] = irq;
2428         ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
2429                                0, dev_name(&pdev->dev), priv);
2430         if (ret < 0) {
2431                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2432                 goto clean_ale_ret;
2433         }
2434
2435         /* TX IRQ */
2436         irq = platform_get_irq(pdev, 2);
2437         if (irq < 0)
2438                 goto clean_ale_ret;
2439
2440         priv->irqs_table[1] = irq;
2441         ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
2442                                0, dev_name(&pdev->dev), priv);
2443         if (ret < 0) {
2444                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2445                 goto clean_ale_ret;
2446         }
2447         priv->num_irqs = 2;
2448
2449         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2450
2451         ndev->netdev_ops = &cpsw_netdev_ops;
2452         ndev->ethtool_ops = &cpsw_ethtool_ops;
2453         netif_napi_add(ndev, &priv->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
2454         netif_napi_add(ndev, &priv->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
2455
2456         /* register the network device */
2457         SET_NETDEV_DEV(ndev, &pdev->dev);
2458         ret = register_netdev(ndev);
2459         if (ret) {
2460                 dev_err(priv->dev, "error registering net device\n");
2461                 ret = -ENODEV;
2462                 goto clean_ale_ret;
2463         }
2464
2465         cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2466                     &ss_res->start, ndev->irq);
2467
2468         if (priv->data.dual_emac) {
2469                 ret = cpsw_probe_dual_emac(pdev, priv);
2470                 if (ret) {
2471                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2472                         goto clean_ale_ret;
2473                 }
2474         }
2475
2476         return 0;
2477
2478 clean_ale_ret:
2479         cpsw_ale_destroy(priv->ale);
2480 clean_dma_ret:
2481         cpdma_chan_destroy(priv->txch);
2482         cpdma_chan_destroy(priv->rxch);
2483         cpdma_ctlr_destroy(priv->dma);
2484 clean_runtime_disable_ret:
2485         pm_runtime_disable(&pdev->dev);
2486 clean_ndev_ret:
2487         free_netdev(priv->ndev);
2488         return ret;
2489 }
2490
2491 static int cpsw_remove_child_device(struct device *dev, void *c)
2492 {
2493         struct platform_device *pdev = to_platform_device(dev);
2494
2495         of_device_unregister(pdev);
2496
2497         return 0;
2498 }
2499
2500 static int cpsw_remove(struct platform_device *pdev)
2501 {
2502         struct net_device *ndev = platform_get_drvdata(pdev);
2503         struct cpsw_priv *priv = netdev_priv(ndev);
2504
2505         if (priv->data.dual_emac)
2506                 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2507         unregister_netdev(ndev);
2508
2509         cpsw_ale_destroy(priv->ale);
2510         cpdma_chan_destroy(priv->txch);
2511         cpdma_chan_destroy(priv->rxch);
2512         cpdma_ctlr_destroy(priv->dma);
2513         pm_runtime_disable(&pdev->dev);
2514         device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device);
2515         if (priv->data.dual_emac)
2516                 free_netdev(cpsw_get_slave_ndev(priv, 1));
2517         free_netdev(ndev);
2518         return 0;
2519 }
2520
2521 #ifdef CONFIG_PM_SLEEP
2522 static int cpsw_suspend(struct device *dev)
2523 {
2524         struct platform_device  *pdev = to_platform_device(dev);
2525         struct net_device       *ndev = platform_get_drvdata(pdev);
2526         struct cpsw_priv        *priv = netdev_priv(ndev);
2527
2528         if (priv->data.dual_emac) {
2529                 int i;
2530
2531                 for (i = 0; i < priv->data.slaves; i++) {
2532                         if (netif_running(priv->slaves[i].ndev))
2533                                 cpsw_ndo_stop(priv->slaves[i].ndev);
2534                         soft_reset_slave(priv->slaves + i);
2535                 }
2536         } else {
2537                 if (netif_running(ndev))
2538                         cpsw_ndo_stop(ndev);
2539                 for_each_slave(priv, soft_reset_slave);
2540         }
2541
2542         pm_runtime_put_sync(&pdev->dev);
2543
2544         /* Select sleep pin state */
2545         pinctrl_pm_select_sleep_state(&pdev->dev);
2546
2547         return 0;
2548 }
2549
2550 static int cpsw_resume(struct device *dev)
2551 {
2552         struct platform_device  *pdev = to_platform_device(dev);
2553         struct net_device       *ndev = platform_get_drvdata(pdev);
2554         struct cpsw_priv        *priv = netdev_priv(ndev);
2555
2556         pm_runtime_get_sync(&pdev->dev);
2557
2558         /* Select default pin state */
2559         pinctrl_pm_select_default_state(&pdev->dev);
2560
2561         if (priv->data.dual_emac) {
2562                 int i;
2563
2564                 for (i = 0; i < priv->data.slaves; i++) {
2565                         if (netif_running(priv->slaves[i].ndev))
2566                                 cpsw_ndo_open(priv->slaves[i].ndev);
2567                 }
2568         } else {
2569                 if (netif_running(ndev))
2570                         cpsw_ndo_open(ndev);
2571         }
2572         return 0;
2573 }
2574 #endif
2575
2576 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
2577
2578 static struct platform_driver cpsw_driver = {
2579         .driver = {
2580                 .name    = "cpsw",
2581                 .pm      = &cpsw_pm_ops,
2582                 .of_match_table = cpsw_of_mtable,
2583         },
2584         .probe = cpsw_probe,
2585         .remove = cpsw_remove,
2586 };
2587
2588 static int __init cpsw_init(void)
2589 {
2590         return platform_driver_register(&cpsw_driver);
2591 }
2592 late_initcall(cpsw_init);
2593
2594 static void __exit cpsw_exit(void)
2595 {
2596         platform_driver_unregister(&cpsw_driver);
2597 }
2598 module_exit(cpsw_exit);
2599
2600 MODULE_LICENSE("GPL");
2601 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2602 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2603 MODULE_DESCRIPTION("TI CPSW Ethernet driver");