drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2013  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../efuse.h"
  28 #include "../base.h"
  29 #include "../regd.h"
  30 #include "../cam.h"
  31 #include "../ps.h"
  32 #include "../pci.h"
  33 #include "../pwrseqcmd.h"
  34 #include "reg.h"
  35 #include "def.h"
  36 #include "phy.h"
  37 #include "dm.h"
  38 #include "fw.h"
  39 #include "led.h"
  40 #include "hw.h"
  41 #include "pwrseq.h"
  42
  43 #define LLT_CONFIG              5
  44
  45 static void _rtl88ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  46                                       u8 set_bits, u8 clear_bits)
  47 {
  48         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  49         struct rtl_priv *rtlpriv = rtl_priv(hw);
  50
  51         rtlpci->reg_bcn_ctrl_val |= set_bits;
  52         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  53
  54         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
  55 }
  56
  57 static void _rtl88ee_stop_tx_beacon(struct ieee80211_hw *hw)
  58 {
  59         struct rtl_priv *rtlpriv = rtl_priv(hw);
  60         u8 tmp1byte;
  61
  62         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  63         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  64         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  65         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  66         tmp1byte &= ~(BIT(0));
  67         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  68 }
  69
  70 static void _rtl88ee_resume_tx_beacon(struct ieee80211_hw *hw)
  71 {
  72         struct rtl_priv *rtlpriv = rtl_priv(hw);
  73         u8 tmp1byte;
  74
  75         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  76         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
  77         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
  78         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  79         tmp1byte |= BIT(0);
  80         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  81 }
  82
  83 static void _rtl88ee_enable_bcn_sub_func(struct ieee80211_hw *hw)
  84 {
  85         _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(1));
  86 }
  87
  88 static void _rtl88ee_return_beacon_queue_skb(struct ieee80211_hw *hw)
  89 {
  90         struct rtl_priv *rtlpriv = rtl_priv(hw);
  91         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  92         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
  93         unsigned long flags;
  94
  95         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  96         while (skb_queue_len(&ring->queue)) {
  97                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
  98                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
  99
 100                 pci_unmap_single(rtlpci->pdev,
 101                                  rtlpriv->cfg->ops->get_desc(
 102                                  (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
 103                                  skb->len, PCI_DMA_TODEVICE);
 104                 kfree_skb(skb);
 105                 ring->idx = (ring->idx + 1) % ring->entries;
 106         }
 107         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
 108 }
 109
 110 static void _rtl88ee_disable_bcn_sub_func(struct ieee80211_hw *hw)
 111 {
 112         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(1), 0);
 113 }
 114
 115 static void _rtl88ee_set_fw_clock_on(struct ieee80211_hw *hw,
 116                                      u8 rpwm_val, bool b_need_turn_off_ckk)
 117 {
 118         struct rtl_priv *rtlpriv = rtl_priv(hw);
 119         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 120         bool b_support_remote_wake_up;
 121         u32 count = 0, isr_regaddr, content;
 122         bool schedule_timer = b_need_turn_off_ckk;
 123         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
 124                                         (u8 *)(&b_support_remote_wake_up));
 125
 126         if (!rtlhal->fw_ready)
 127                 return;
 128         if (!rtlpriv->psc.fw_current_inpsmode)
 129                 return;
 130
 131         while (1) {
 132                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 133                 if (rtlhal->fw_clk_change_in_progress) {
 134                         while (rtlhal->fw_clk_change_in_progress) {
 135                                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 136                                 count++;
 137                                 udelay(100);
 138                                 if (count > 1000)
 139                                         return;
 140                                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 141                         }
 142                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 143                 } else {
 144                         rtlhal->fw_clk_change_in_progress = false;
 145                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 146                         break;
 147                 }
 148         }
 149
 150         if (IS_IN_LOW_POWER_STATE_88E(rtlhal->fw_ps_state)) {
 151                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
 152                 if (FW_PS_IS_ACK(rpwm_val)) {
 153                         isr_regaddr = REG_HISR;
 154                         content = rtl_read_dword(rtlpriv, isr_regaddr);
 155                         while (!(content & IMR_CPWM) && (count < 500)) {
 156                                 udelay(50);
 157                                 count++;
 158                                 content = rtl_read_dword(rtlpriv, isr_regaddr);
 159                         }
 160
 161                         if (content & IMR_CPWM) {
 162                                 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
 163                                 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_88E;
 164                                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 165                                          "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n",
 166                                          rtlhal->fw_ps_state);
 167                         }
 168                 }
 169
 170                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 171                 rtlhal->fw_clk_change_in_progress = false;
 172                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 173                 if (schedule_timer) {
 174                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 175                                   jiffies + MSECS(10));
 176                 }
 177
 178         } else  {
 179                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 180                 rtlhal->fw_clk_change_in_progress = false;
 181                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 182         }
 183 }
 184
 185 static void _rtl88ee_set_fw_clock_off(struct ieee80211_hw *hw,
 186                                       u8 rpwm_val)
 187 {
 188         struct rtl_priv *rtlpriv = rtl_priv(hw);
 189         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 190         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 191         struct rtl8192_tx_ring *ring;
 192         enum rf_pwrstate rtstate;
 193         bool schedule_timer = false;
 194         u8 queue;
 195
 196         if (!rtlhal->fw_ready)
 197                 return;
 198         if (!rtlpriv->psc.fw_current_inpsmode)
 199                 return;
 200         if (!rtlhal->allow_sw_to_change_hwclc)
 201                 return;
 202         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
 203         if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
 204                 return;
 205
 206         for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
 207                 ring = &rtlpci->tx_ring[queue];
 208                 if (skb_queue_len(&ring->queue)) {
 209                         schedule_timer = true;
 210                         break;
 211                 }
 212         }
 213
 214         if (schedule_timer) {
 215                 mod_timer(&rtlpriv->works.fw_clockoff_timer,
 216                           jiffies + MSECS(10));
 217                 return;
 218         }
 219
 220         if (FW_PS_STATE(rtlhal->fw_ps_state) !=
 221             FW_PS_STATE_RF_OFF_LOW_PWR_88E) {
 222                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 223                 if (!rtlhal->fw_clk_change_in_progress) {
 224                         rtlhal->fw_clk_change_in_progress = true;
 225                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 226                         rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
 227                         rtl_write_word(rtlpriv, REG_HISR, 0x0100);
 228                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 229                                                       &rpwm_val);
 230                         spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 231                         rtlhal->fw_clk_change_in_progress = false;
 232                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 233                 } else {
 234                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 235                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 236                                   jiffies + MSECS(10));
 237                 }
 238         }
 239 }
 240
 241 static void _rtl88ee_set_fw_ps_rf_on(struct ieee80211_hw *hw)
 242 {
 243         u8 rpwm_val = 0;
 244
 245         rpwm_val |= (FW_PS_STATE_RF_OFF_88E | FW_PS_ACK);
 246         _rtl88ee_set_fw_clock_on(hw, rpwm_val, true);
 247 }
 248
 249 static void _rtl88ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw)
 250 {
 251         u8 rpwm_val = 0;
 252         rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR_88E;
 253         _rtl88ee_set_fw_clock_off(hw, rpwm_val);
 254 }
 255 void rtl88ee_fw_clk_off_timer_callback(unsigned long data)
 256 {
 257         struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
 258
 259         _rtl88ee_set_fw_ps_rf_off_low_power(hw);
 260 }
 261
 262 static void _rtl88ee_fwlps_leave(struct ieee80211_hw *hw)
 263 {
 264         struct rtl_priv *rtlpriv = rtl_priv(hw);
 265         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 266         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 267         bool fw_current_inps = false;
 268         u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
 269
 270         if (ppsc->low_power_enable) {
 271                 rpwm_val = (FW_PS_STATE_ALL_ON_88E|FW_PS_ACK);/* RF on */
 272                 _rtl88ee_set_fw_clock_on(hw, rpwm_val, false);
 273                 rtlhal->allow_sw_to_change_hwclc = false;
 274                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 275                                               &fw_pwrmode);
 276                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 277                                               (u8 *)(&fw_current_inps));
 278         } else {
 279                 rpwm_val = FW_PS_STATE_ALL_ON_88E;      /* RF on */
 280                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
 281                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 282                                               &fw_pwrmode);
 283                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 284                                               (u8 *)(&fw_current_inps));
 285         }
 286 }
 287
 288 static void _rtl88ee_fwlps_enter(struct ieee80211_hw *hw)
 289 {
 290         struct rtl_priv *rtlpriv = rtl_priv(hw);
 291         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 292         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 293         bool fw_current_inps = true;
 294         u8 rpwm_val;
 295
 296         if (ppsc->low_power_enable) {
 297                 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_88E;      /* RF off */
 298                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 299                                               (u8 *)(&fw_current_inps));
 300                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 301                                               &ppsc->fwctrl_psmode);
 302                 rtlhal->allow_sw_to_change_hwclc = true;
 303                 _rtl88ee_set_fw_clock_off(hw, rpwm_val);
 304         } else {
 305                 rpwm_val = FW_PS_STATE_RF_OFF_88E;      /* RF off */
 306                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 307                                               (u8 *)(&fw_current_inps));
 308                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 309                                               &ppsc->fwctrl_psmode);
 310                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
 311         }
 312 }
 313
 314 void rtl88ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 315 {
 316         struct rtl_priv *rtlpriv = rtl_priv(hw);
 317         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 318         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 319
 320         switch (variable) {
 321         case HW_VAR_RCR:
 322                 *((u32 *)(val)) = rtlpci->receive_config;
 323                 break;
 324         case HW_VAR_RF_STATE:
 325                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 326                 break;
 327         case HW_VAR_FWLPS_RF_ON:{
 328                 enum rf_pwrstate rfstate;
 329                 u32 val_rcr;
 330
 331                 rtlpriv->cfg->ops->get_hw_reg(hw,
 332                                               HW_VAR_RF_STATE,
 333                                               (u8 *)(&rfstate));
 334                 if (rfstate == ERFOFF) {
 335                         *((bool *)(val)) = true;
 336                 } else {
 337                         val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 338                         val_rcr &= 0x00070000;
 339                         if (val_rcr)
 340                                 *((bool *)(val)) = false;
 341                         else
 342                                 *((bool *)(val)) = true;
 343                 }
 344                 break; }
 345         case HW_VAR_FW_PSMODE_STATUS:
 346                 *((bool *)(val)) = ppsc->fw_current_inpsmode;
 347                 break;
 348         case HW_VAR_CORRECT_TSF:{
 349                 u64 tsf;
 350                 u32 *ptsf_low = (u32 *)&tsf;
 351                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 352
 353                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 354                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 355
 356                 *((u64 *)(val)) = tsf;
 357                 break; }
 358         default:
 359                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 360                          "switch case not process %x\n", variable);
 361                 break;
 362         }
 363 }
 364
 365 void rtl88ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 366 {
 367         struct rtl_priv *rtlpriv = rtl_priv(hw);
 368         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 369         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 370         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 371         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 372         u8 idx;
 373
 374         switch (variable) {
 375         case HW_VAR_ETHER_ADDR:
 376                 for (idx = 0; idx < ETH_ALEN; idx++) {
 377                         rtl_write_byte(rtlpriv, (REG_MACID + idx),
 378                                        val[idx]);
 379                 }
 380                 break;
 381         case HW_VAR_BASIC_RATE:{
 382                 u16 b_rate_cfg = ((u16 *)val)[0];
 383                 u8 rate_index = 0;
 384                 b_rate_cfg = b_rate_cfg & 0x15f;
 385                 b_rate_cfg |= 0x01;
 386                 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
 387                 rtl_write_byte(rtlpriv, REG_RRSR + 1,
 388                                (b_rate_cfg >> 8) & 0xff);
 389                 while (b_rate_cfg > 0x1) {
 390                         b_rate_cfg = (b_rate_cfg >> 1);
 391                         rate_index++;
 392                 }
 393                 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
 394                                rate_index);
 395                 break;
 396                 }
 397         case HW_VAR_BSSID:
 398                 for (idx = 0; idx < ETH_ALEN; idx++) {
 399                         rtl_write_byte(rtlpriv, (REG_BSSID + idx),
 400                                        val[idx]);
 401                 }
 402                 break;
 403         case HW_VAR_SIFS:
 404                 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 405                 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 406
 407                 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 408                 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 409
 410                 if (!mac->ht_enable)
 411                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 412                                        0x0e0e);
 413                 else
 414                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 415                                        *((u16 *)val));
 416                 break;
 417         case HW_VAR_SLOT_TIME:{
 418                 u8 e_aci;
 419
 420                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 421                          "HW_VAR_SLOT_TIME %x\n", val[0]);
 422
 423                 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 424
 425                 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 426                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
 427                                                       &e_aci);
 428                 }
 429                 break;
 430                 }
 431         case HW_VAR_ACK_PREAMBLE:{
 432                 u8 reg_tmp;
 433                 u8 short_preamble = (bool)*val;
 434                 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
 435                 if (short_preamble) {
 436                         reg_tmp |= 0x02;
 437                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL +
 438                                        2, reg_tmp);
 439                 } else {
 440                         reg_tmp |= 0xFD;
 441                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL +
 442                                        2, reg_tmp);
 443                 }
 444                 break; }
 445         case HW_VAR_WPA_CONFIG:
 446                 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
 447                 break;
 448         case HW_VAR_AMPDU_MIN_SPACE:{
 449                 u8 min_spacing_to_set;
 450                 u8 sec_min_space;
 451
 452                 min_spacing_to_set = *val;
 453                 if (min_spacing_to_set <= 7) {
 454                         sec_min_space = 0;
 455
 456                         if (min_spacing_to_set < sec_min_space)
 457                                 min_spacing_to_set = sec_min_space;
 458
 459                         mac->min_space_cfg = ((mac->min_space_cfg &
 460                                                0xf8) |
 461                                               min_spacing_to_set);
 462
 463                         *val = min_spacing_to_set;
 464
 465                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 466                                  "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 467                                   mac->min_space_cfg);
 468
 469                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 470                                        mac->min_space_cfg);
 471                 }
 472                 break; }
 473         case HW_VAR_SHORTGI_DENSITY:{
 474                 u8 density_to_set;
 475
 476                 density_to_set = *val;
 477                 mac->min_space_cfg |= (density_to_set << 3);
 478
 479                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 480                          "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 481                           mac->min_space_cfg);
 482
 483                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 484                                mac->min_space_cfg);
 485                 break;
 486                 }
 487         case HW_VAR_AMPDU_FACTOR:{
 488                 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
 489                 u8 factor_toset;
 490                 u8 *p_regtoset = NULL;
 491                 u8 index = 0;
 492
 493                 p_regtoset = regtoset_normal;
 494
 495                 factor_toset = *val;
 496                 if (factor_toset <= 3) {
 497                         factor_toset = (1 << (factor_toset + 2));
 498                         if (factor_toset > 0xf)
 499                                 factor_toset = 0xf;
 500
 501                         for (index = 0; index < 4; index++) {
 502                                 if ((p_regtoset[index] & 0xf0) >
 503                                     (factor_toset << 4))
 504                                         p_regtoset[index] =
 505                                             (p_regtoset[index] & 0x0f) |
 506                                             (factor_toset << 4);
 507
 508                                 if ((p_regtoset[index] & 0x0f) >
 509                                     factor_toset)
 510                                         p_regtoset[index] =
 511                                             (p_regtoset[index] & 0xf0) |
 512                                             (factor_toset);
 513
 514                                 rtl_write_byte(rtlpriv,
 515                                                (REG_AGGLEN_LMT + index),
 516                                                p_regtoset[index]);
 517
 518                         }
 519
 520                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 521                                  "Set HW_VAR_AMPDU_FACTOR: %#x\n",
 522                                   factor_toset);
 523                 }
 524                 break; }
 525         case HW_VAR_AC_PARAM:{
 526                 u8 e_aci = *val;
 527                 rtl88e_dm_init_edca_turbo(hw);
 528
 529                 if (rtlpci->acm_method != EACMWAY2_SW)
 530                         rtlpriv->cfg->ops->set_hw_reg(hw,
 531                                                       HW_VAR_ACM_CTRL,
 532                                                       &e_aci);
 533                 break; }
 534         case HW_VAR_ACM_CTRL:{
 535                 u8 e_aci = *val;
 536                 union aci_aifsn *p_aci_aifsn =
 537                     (union aci_aifsn *)(&(mac->ac[0].aifs));
 538                 u8 acm = p_aci_aifsn->f.acm;
 539                 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 540
 541                 acm_ctrl = acm_ctrl |
 542                            ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 543
 544                 if (acm) {
 545                         switch (e_aci) {
 546                         case AC0_BE:
 547                                 acm_ctrl |= ACMHW_BEQEN;
 548                                 break;
 549                         case AC2_VI:
 550                                 acm_ctrl |= ACMHW_VIQEN;
 551                                 break;
 552                         case AC3_VO:
 553                                 acm_ctrl |= ACMHW_VOQEN;
 554                                 break;
 555                         default:
 556                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 557                                          "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 558                                          acm);
 559                                 break;
 560                         }
 561                 } else {
 562                         switch (e_aci) {
 563                         case AC0_BE:
 564                                 acm_ctrl &= (~ACMHW_BEQEN);
 565                                 break;
 566                         case AC2_VI:
 567                                 acm_ctrl &= (~ACMHW_VIQEN);
 568                                 break;
 569                         case AC3_VO:
 570                                 acm_ctrl &= (~ACMHW_VOQEN);
 571                                 break;
 572                         default:
 573                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 574                                          "switch case not process\n");
 575                                 break;
 576                         }
 577                 }
 578
 579                 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 580                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 581                          acm_ctrl);
 582                 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 583                 break; }
 584         case HW_VAR_RCR:
 585                 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
 586                 rtlpci->receive_config = ((u32 *)(val))[0];
 587                 break;
 588         case HW_VAR_RETRY_LIMIT:{
 589                 u8 retry_limit = *val;
 590
 591                 rtl_write_word(rtlpriv, REG_RL,
 592                                retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 593                                retry_limit << RETRY_LIMIT_LONG_SHIFT);
 594                 break; }
 595         case HW_VAR_DUAL_TSF_RST:
 596                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 597                 break;
 598         case HW_VAR_EFUSE_BYTES:
 599                 rtlefuse->efuse_usedbytes = *((u16 *)val);
 600                 break;
 601         case HW_VAR_EFUSE_USAGE:
 602                 rtlefuse->efuse_usedpercentage = *val;
 603                 break;
 604         case HW_VAR_IO_CMD:
 605                 rtl88e_phy_set_io_cmd(hw, (*(enum io_type *)val));
 606                 break;
 607         case HW_VAR_SET_RPWM:{
 608                 u8 rpwm_val;
 609
 610                 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 611                 udelay(1);
 612
 613                 if (rpwm_val & BIT(7)) {
 614                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val);
 615                 } else {
 616                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val | BIT(7));
 617                 }
 618                 break; }
 619         case HW_VAR_H2C_FW_PWRMODE:
 620                 rtl88e_set_fw_pwrmode_cmd(hw, *val);
 621                 break;
 622         case HW_VAR_FW_PSMODE_STATUS:
 623                 ppsc->fw_current_inpsmode = *((bool *)val);
 624                 break;
 625         case HW_VAR_RESUME_CLK_ON:
 626                 _rtl88ee_set_fw_ps_rf_on(hw);
 627                 break;
 628         case HW_VAR_FW_LPS_ACTION:{
 629                 bool enter_fwlps = *((bool *)val);
 630
 631                 if (enter_fwlps)
 632                         _rtl88ee_fwlps_enter(hw);
 633                  else
 634                         _rtl88ee_fwlps_leave(hw);
 635
 636                  break; }
 637         case HW_VAR_H2C_FW_JOINBSSRPT:{
 638                 u8 mstatus = *val;
 639                 u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
 640                 u8 count = 0, dlbcn_count = 0;
 641                 bool b_recover = false;
 642
 643                 if (mstatus == RT_MEDIA_CONNECT) {
 644                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
 645                                                       NULL);
 646
 647                         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 648                         rtl_write_byte(rtlpriv, REG_CR + 1,
 649                                        (tmp_regcr | BIT(0)));
 650
 651                         _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
 652                         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
 653
 654                         tmp_reg422 =
 655                             rtl_read_byte(rtlpriv,
 656                                           REG_FWHW_TXQ_CTRL + 2);
 657                         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 658                                        tmp_reg422 & (~BIT(6)));
 659                         if (tmp_reg422 & BIT(6))
 660                                 b_recover = true;
 661
 662                         do {
 663                                 bcnvalid_reg = rtl_read_byte(rtlpriv,
 664                                                              REG_TDECTRL+2);
 665                                 rtl_write_byte(rtlpriv, REG_TDECTRL+2,
 666                                                (bcnvalid_reg | BIT(0)));
 667                                 _rtl88ee_return_beacon_queue_skb(hw);
 668
 669                                 rtl88e_set_fw_rsvdpagepkt(hw, 0);
 670                                 bcnvalid_reg = rtl_read_byte(rtlpriv,
 671                                                              REG_TDECTRL+2);
 672                                 count = 0;
 673                                 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
 674                                         count++;
 675                                         udelay(10);
 676                                         bcnvalid_reg =
 677                                           rtl_read_byte(rtlpriv, REG_TDECTRL+2);
 678                                 }
 679                                 dlbcn_count++;
 680                         } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
 681
 682                         if (bcnvalid_reg & BIT(0))
 683                                 rtl_write_byte(rtlpriv, REG_TDECTRL+2, BIT(0));
 684
 685                         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
 686                         _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
 687
 688                         if (b_recover) {
 689                                 rtl_write_byte(rtlpriv,
 690                                                REG_FWHW_TXQ_CTRL + 2,
 691                                                tmp_reg422);
 692                         }
 693
 694                         rtl_write_byte(rtlpriv, REG_CR + 1,
 695                                        (tmp_regcr & ~(BIT(0))));
 696                 }
 697                 rtl88e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val));
 698                 break; }
 699         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
 700                 rtl88e_set_p2p_ps_offload_cmd(hw, *val);
 701                 break;
 702         case HW_VAR_AID:{
 703                 u16 u2btmp;
 704
 705                 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 706                 u2btmp &= 0xC000;
 707                 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
 708                                mac->assoc_id));
 709                 break; }
 710         case HW_VAR_CORRECT_TSF:{
 711                 u8 btype_ibss = *val;
 712
 713                 if (btype_ibss)
 714                         _rtl88ee_stop_tx_beacon(hw);
 715
 716                 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
 717
 718                 rtl_write_dword(rtlpriv, REG_TSFTR,
 719                                 (u32)(mac->tsf & 0xffffffff));
 720                 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 721                                 (u32)((mac->tsf >> 32) & 0xffffffff));
 722
 723                 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
 724
 725                 if (btype_ibss)
 726                         _rtl88ee_resume_tx_beacon(hw);
 727                 break; }
 728         case HW_VAR_KEEP_ALIVE: {
 729                 u8 array[2];
 730
 731                 array[0] = 0xff;
 732                 array[1] = *((u8 *)val);
 733                 rtl88e_fill_h2c_cmd(hw, H2C_88E_KEEP_ALIVE_CTRL,
 734                                     2, array);
 735                 break; }
 736         default:
 737                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 738                          "switch case not process %x\n", variable);
 739                 break;
 740         }
 741 }
 742
 743 static bool _rtl88ee_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 744 {
 745         struct rtl_priv *rtlpriv = rtl_priv(hw);
 746         bool status = true;
 747         long count = 0;
 748         u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
 749                     _LLT_OP(_LLT_WRITE_ACCESS);
 750
 751         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 752
 753         do {
 754                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 755                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 756                         break;
 757
 758                 if (count > POLLING_LLT_THRESHOLD) {
 759                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 760                                  "Failed to polling write LLT done at address %d!\n",
 761                                  address);
 762                         status = false;
 763                         break;
 764                 }
 765         } while (++count);
 766
 767         return status;
 768 }
 769
 770 static bool _rtl88ee_llt_table_init(struct ieee80211_hw *hw)
 771 {
 772         struct rtl_priv *rtlpriv = rtl_priv(hw);
 773         unsigned short i;
 774         u8 txpktbuf_bndy;
 775         u8 maxpage;
 776         bool status;
 777
 778         maxpage = 0xAF;
 779         txpktbuf_bndy = 0xAB;
 780
 781         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x01);
 782         rtl_write_dword(rtlpriv, REG_RQPN, 0x80730d29);
 783
 784         /*0x2600   MaxRxBuff=10k-max(TxReportSize(64*8), WOLPattern(16*24)) */
 785         rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x25FF0000 | txpktbuf_bndy));
 786         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 787
 788         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 789         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 790
 791         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 792         rtl_write_byte(rtlpriv, REG_PBP, 0x11);
 793         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 794
 795         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 796                 status = _rtl88ee_llt_write(hw, i, i + 1);
 797                 if (true != status)
 798                         return status;
 799         }
 800
 801         status = _rtl88ee_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 802         if (true != status)
 803                 return status;
 804
 805         for (i = txpktbuf_bndy; i < maxpage; i++) {
 806                 status = _rtl88ee_llt_write(hw, i, (i + 1));
 807                 if (true != status)
 808                         return status;
 809         }
 810
 811         status = _rtl88ee_llt_write(hw, maxpage, txpktbuf_bndy);
 812         if (true != status)
 813                 return status;
 814
 815         return true;
 816 }
 817
 818 static void _rtl88ee_gen_refresh_led_state(struct ieee80211_hw *hw)
 819 {
 820         struct rtl_priv *rtlpriv = rtl_priv(hw);
 821         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 822         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 823         struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 824
 825         if (rtlpriv->rtlhal.up_first_time)
 826                 return;
 827
 828         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 829                 rtl88ee_sw_led_on(hw, pLed0);
 830         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 831                 rtl88ee_sw_led_on(hw, pLed0);
 832         else
 833                 rtl88ee_sw_led_off(hw, pLed0);
 834 }
 835
 836 static bool _rtl88ee_init_mac(struct ieee80211_hw *hw)
 837 {
 838         struct rtl_priv *rtlpriv = rtl_priv(hw);
 839         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 840         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 841
 842         u8 bytetmp;
 843         u16 wordtmp;
 844
 845         /*Disable XTAL OUTPUT for power saving. YJ,add,111206. */
 846         bytetmp = rtl_read_byte(rtlpriv, REG_XCK_OUT_CTRL) & (~BIT(0));
 847         rtl_write_byte(rtlpriv, REG_XCK_OUT_CTRL, bytetmp);
 848         /*Auto Power Down to CHIP-off State*/
 849         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
 850         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 851
 852         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 853         /* HW Power on sequence */
 854         if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
 855                                       PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
 856                                       RTL8188EE_NIC_ENABLE_FLOW)) {
 857                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 858                          "init MAC Fail as rtl_hal_pwrseqcmdparsing\n");
 859                 return false;
 860         }
 861
 862         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
 863         rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
 864
 865         bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2);
 866         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp|BIT(2));
 867
 868         bytetmp = rtl_read_byte(rtlpriv, REG_WATCH_DOG+1);
 869         rtl_write_byte(rtlpriv, REG_WATCH_DOG+1, bytetmp|BIT(7));
 870
 871         bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1);
 872         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1, bytetmp|BIT(1));
 873
 874         bytetmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);
 875         rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, bytetmp|BIT(1)|BIT(0));
 876         rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL+1, 2);
 877         rtl_write_word(rtlpriv, REG_TX_RPT_TIME, 0xcdf0);
 878
 879         /*Add for wake up online*/
 880         bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
 881
 882         rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp|BIT(3));
 883         bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG+1);
 884         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+1, (bytetmp & (~BIT(4))));
 885         rtl_write_byte(rtlpriv, 0x367, 0x80);
 886
 887         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 888         rtl_write_byte(rtlpriv, REG_CR+1, 0x06);
 889         rtl_write_byte(rtlpriv, MSR, 0x00);
 890
 891         if (!rtlhal->mac_func_enable) {
 892                 if (_rtl88ee_llt_table_init(hw) == false) {
 893                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 894                                  "LLT table init fail\n");
 895                         return false;
 896                 }
 897         }
 898         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 899         rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
 900
 901         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 902         wordtmp &= 0xf;
 903         wordtmp |= 0xE771;
 904         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 905
 906         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 907         rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff);
 908         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 909
 910         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 911                         ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
 912                         DMA_BIT_MASK(32));
 913         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 914                         (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
 915                         DMA_BIT_MASK(32));
 916         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 917                         (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
 918         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 919                         (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
 920         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 921                         (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
 922         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 923                         (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
 924         rtl_write_dword(rtlpriv, REG_HQ_DESA,
 925                         (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
 926                         DMA_BIT_MASK(32));
 927         rtl_write_dword(rtlpriv, REG_RX_DESA,
 928                         (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
 929                         DMA_BIT_MASK(32));
 930
 931         /* if we want to support 64 bit DMA, we should set it here,
 932          * but now we do not support 64 bit DMA
 933          */
 934         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 935
 936         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 937         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0);/*Enable RX DMA */
 938
 939         if (rtlhal->earlymode_enable) {/*Early mode enable*/
 940                 bytetmp = rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL);
 941                 bytetmp |= 0x1f;
 942                 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, bytetmp);
 943                 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL+3, 0x81);
 944         }
 945         _rtl88ee_gen_refresh_led_state(hw);
 946         return true;
 947 }
 948
 949 static void _rtl88ee_hw_configure(struct ieee80211_hw *hw)
 950 {
 951         struct rtl_priv *rtlpriv = rtl_priv(hw);
 952         u8 reg_bw_opmode;
 953         u32 reg_ratr, reg_prsr;
 954
 955         reg_bw_opmode = BW_OPMODE_20MHZ;
 956         reg_ratr = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
 957             RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
 958         reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 959
 960         rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
 961         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
 962 }
 963
 964 static void _rtl88ee_enable_aspm_back_door(struct ieee80211_hw *hw)
 965 {
 966         struct rtl_priv *rtlpriv = rtl_priv(hw);
 967         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 968         u8 tmp1byte = 0;
 969         u32 tmp4byte = 0, count = 0;
 970
 971         rtl_write_word(rtlpriv, 0x354, 0x8104);
 972         rtl_write_word(rtlpriv, 0x358, 0x24);
 973
 974         rtl_write_word(rtlpriv, 0x350, 0x70c);
 975         rtl_write_byte(rtlpriv, 0x352, 0x2);
 976         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 977         count = 0;
 978         while (tmp1byte && count < 20) {
 979                 udelay(10);
 980                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 981                 count++;
 982         }
 983         if (0 == tmp1byte) {
 984                 tmp4byte = rtl_read_dword(rtlpriv, 0x34c);
 985                 rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(31));
 986                 rtl_write_word(rtlpriv, 0x350, 0xf70c);
 987                 rtl_write_byte(rtlpriv, 0x352, 0x1);
 988         }
 989
 990         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 991         count = 0;
 992         while (tmp1byte && count < 20) {
 993                 udelay(10);
 994                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 995                 count++;
 996         }
 997
 998         rtl_write_word(rtlpriv, 0x350, 0x718);
 999         rtl_write_byte(rtlpriv, 0x352, 0x2);
1000         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1001         count = 0;
1002         while (tmp1byte && count < 20) {
1003                 udelay(10);
1004                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1005                 count++;
1006         }
1007
1008         if (ppsc->support_backdoor || (0 == tmp1byte)) {
1009                 tmp4byte = rtl_read_dword(rtlpriv, 0x34c);
1010                 rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(11)|BIT(12));
1011                 rtl_write_word(rtlpriv, 0x350, 0xf718);
1012                 rtl_write_byte(rtlpriv, 0x352, 0x1);
1013         }
1014
1015         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1016         count = 0;
1017         while (tmp1byte && count < 20) {
1018                 udelay(10);
1019                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1020                 count++;
1021         }
1022 }
1023
1024 void rtl88ee_enable_hw_security_config(struct ieee80211_hw *hw)
1025 {
1026         struct rtl_priv *rtlpriv = rtl_priv(hw);
1027         u8 sec_reg_value;
1028
1029         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1030                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1031                   rtlpriv->sec.pairwise_enc_algorithm,
1032                   rtlpriv->sec.group_enc_algorithm);
1033
1034         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1035                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1036                          "not open hw encryption\n");
1037                 return;
1038         }
1039
1040         sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1041
1042         if (rtlpriv->sec.use_defaultkey) {
1043                 sec_reg_value |= SCR_TXUSEDK;
1044                 sec_reg_value |= SCR_RXUSEDK;
1045         }
1046
1047         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1048
1049         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1050
1051         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1052                  "The SECR-value %x\n", sec_reg_value);
1053
1054         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1055 }
1056
1057 int rtl88ee_hw_init(struct ieee80211_hw *hw)
1058 {
1059         struct rtl_priv *rtlpriv = rtl_priv(hw);
1060         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1061         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1062         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1063         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1064         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1065         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1066         bool rtstatus = true;
1067         int err = 0;
1068         u8 tmp_u1b, u1byte;
1069         unsigned long flags;
1070
1071         rtlpriv->rtlhal.being_init_adapter = true;
1072         /* As this function can take a very long time (up to 350 ms)
1073          * and can be called with irqs disabled, reenable the irqs
1074          * to let the other devices continue being serviced.
1075          *
1076          * It is safe doing so since our own interrupts will only be enabled
1077          * in a subsequent step.
1078          */
1079         local_save_flags(flags);
1080         local_irq_enable();
1081         rtlhal->fw_ready = false;
1082
1083         rtlpriv->intf_ops->disable_aspm(hw);
1084
1085         tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR+1);
1086         u1byte = rtl_read_byte(rtlpriv, REG_CR);
1087         if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) {
1088                 rtlhal->mac_func_enable = true;
1089         } else {
1090                 rtlhal->mac_func_enable = false;
1091                 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;
1092         }
1093
1094         rtstatus = _rtl88ee_init_mac(hw);
1095         if (rtstatus != true) {
1096                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1097                 err = 1;
1098                 goto exit;
1099         }
1100
1101         err = rtl88e_download_fw(hw, false);
1102         if (err) {
1103                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1104                          "Failed to download FW. Init HW without FW now..\n");
1105                 err = 1;
1106                 goto exit;
1107         }
1108         rtlhal->fw_ready = true;
1109         /*fw related variable initialize */
1110         rtlhal->last_hmeboxnum = 0;
1111         rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;
1112         rtlhal->fw_clk_change_in_progress = false;
1113         rtlhal->allow_sw_to_change_hwclc = false;
1114         ppsc->fw_current_inpsmode = false;
1115
1116         rtl88e_phy_mac_config(hw);
1117         /* because last function modify RCR, so we update
1118          * rcr var here, or TP will unstable for receive_config
1119          * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1120          * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1121          */
1122         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1123         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1124
1125         rtl88e_phy_bb_config(hw);
1126         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1127         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1128
1129         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1130         rtl88e_phy_rf_config(hw);
1131
1132         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1133                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1134         rtlphy->rfreg_chnlval[0] = rtlphy->rfreg_chnlval[0] & 0xfff00fff;
1135
1136         _rtl88ee_hw_configure(hw);
1137         rtl_cam_reset_all_entry(hw);
1138         rtl88ee_enable_hw_security_config(hw);
1139
1140         rtlhal->mac_func_enable = true;
1141         ppsc->rfpwr_state = ERFON;
1142
1143         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1144         _rtl88ee_enable_aspm_back_door(hw);
1145         rtlpriv->intf_ops->enable_aspm(hw);
1146
1147         if (ppsc->rfpwr_state == ERFON) {
1148                 if ((rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) ||
1149                     ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) &&
1150                      (rtlhal->oem_id == RT_CID_819X_HP))) {
1151                         rtl88e_phy_set_rfpath_switch(hw, true);
1152                         rtlpriv->dm.fat_table.rx_idle_ant = MAIN_ANT;
1153                 } else {
1154                         rtl88e_phy_set_rfpath_switch(hw, false);
1155                         rtlpriv->dm.fat_table.rx_idle_ant = AUX_ANT;
1156                 }
1157                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rx idle ant %s\n",
1158                          (rtlpriv->dm.fat_table.rx_idle_ant == MAIN_ANT) ?
1159                          ("MAIN_ANT") : ("AUX_ANT"));
1160
1161                 if (rtlphy->iqk_initialized) {
1162                         rtl88e_phy_iq_calibrate(hw, true);
1163                 } else {
1164                         rtl88e_phy_iq_calibrate(hw, false);
1165                         rtlphy->iqk_initialized = true;
1166                 }
1167
1168                 rtl88e_dm_check_txpower_tracking(hw);
1169                 rtl88e_phy_lc_calibrate(hw);
1170         }
1171
1172         tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1173         if (!(tmp_u1b & BIT(0))) {
1174                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1175                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n");
1176         }
1177
1178         if (!(tmp_u1b & BIT(4))) {
1179                 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1180                 tmp_u1b &= 0x0F;
1181                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1182                 udelay(10);
1183                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1184                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "under 1.5V\n");
1185         }
1186         rtl_write_byte(rtlpriv, REG_NAV_CTRL+2,  ((30000+127)/128));
1187         rtl88e_dm_init(hw);
1188 exit:
1189         local_irq_restore(flags);
1190         rtlpriv->rtlhal.being_init_adapter = false;
1191         return err;
1192 }
1193
1194 static enum version_8188e _rtl88ee_read_chip_version(struct ieee80211_hw *hw)
1195 {
1196         struct rtl_priv *rtlpriv = rtl_priv(hw);
1197         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1198         enum version_8188e version = VERSION_UNKNOWN;
1199         u32 value32;
1200
1201         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1202         if (value32 & TRP_VAUX_EN) {
1203                 version = (enum version_8188e) VERSION_TEST_CHIP_88E;
1204         } else {
1205                 version = NORMAL_CHIP;
1206                 version = version | ((value32 & TYPE_ID) ? RF_TYPE_2T2R : 0);
1207                 version = version | ((value32 & VENDOR_ID) ?
1208                           CHIP_VENDOR_UMC : 0);
1209         }
1210
1211         rtlphy->rf_type = RF_1T1R;
1212         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1213                  "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1214                  "RF_2T2R" : "RF_1T1R");
1215
1216         return version;
1217 }
1218
1219 static int _rtl88ee_set_media_status(struct ieee80211_hw *hw,
1220                                      enum nl80211_iftype type)
1221 {
1222         struct rtl_priv *rtlpriv = rtl_priv(hw);
1223         u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1224         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1225         u8 mode = MSR_NOLINK;
1226
1227         switch (type) {
1228         case NL80211_IFTYPE_UNSPECIFIED:
1229                 mode = MSR_NOLINK;
1230                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1231                          "Set Network type to NO LINK!\n");
1232                 break;
1233         case NL80211_IFTYPE_ADHOC:
1234         case NL80211_IFTYPE_MESH_POINT:
1235                 mode = MSR_ADHOC;
1236                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1237                          "Set Network type to Ad Hoc!\n");
1238                 break;
1239         case NL80211_IFTYPE_STATION:
1240                 mode = MSR_INFRA;
1241                 ledaction = LED_CTL_LINK;
1242                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1243                          "Set Network type to STA!\n");
1244                 break;
1245         case NL80211_IFTYPE_AP:
1246                 mode = MSR_AP;
1247                 ledaction = LED_CTL_LINK;
1248                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1249                          "Set Network type to AP!\n");
1250                 break;
1251         default:
1252                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1253                          "Network type %d not support!\n", type);
1254                 return 1;
1255                 break;
1256         }
1257
1258         /* MSR_INFRA == Link in infrastructure network;
1259          * MSR_ADHOC == Link in ad hoc network;
1260          * Therefore, check link state is necessary.
1261          *
1262          * MSR_AP == AP mode; link state is not cared here.
1263          */
1264         if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1265                 mode = MSR_NOLINK;
1266                 ledaction = LED_CTL_NO_LINK;
1267         }
1268
1269         if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1270                 _rtl88ee_stop_tx_beacon(hw);
1271                 _rtl88ee_enable_bcn_sub_func(hw);
1272         } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1273                 _rtl88ee_resume_tx_beacon(hw);
1274                 _rtl88ee_disable_bcn_sub_func(hw);
1275         } else {
1276                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1277                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1278                          mode);
1279         }
1280
1281         rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1282         rtlpriv->cfg->ops->led_control(hw, ledaction);
1283         if (mode == MSR_AP)
1284                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1285         else
1286                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1287         return 0;
1288 }
1289
1290 void rtl88ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1291 {
1292         struct rtl_priv *rtlpriv = rtl_priv(hw);
1293         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1294         u32 reg_rcr = rtlpci->receive_config;
1295
1296         if (rtlpriv->psc.rfpwr_state != ERFON)
1297                 return;
1298
1299         if (check_bssid == true) {
1300                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1301                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1302                                               (u8 *)(&reg_rcr));
1303                 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
1304         } else if (check_bssid == false) {
1305                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1306                 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
1307                 rtlpriv->cfg->ops->set_hw_reg(hw,
1308                         HW_VAR_RCR, (u8 *)(&reg_rcr));
1309         }
1310
1311 }
1312
1313 int rtl88ee_set_network_type(struct ieee80211_hw *hw,
1314                              enum nl80211_iftype type)
1315 {
1316         struct rtl_priv *rtlpriv = rtl_priv(hw);
1317
1318         if (_rtl88ee_set_media_status(hw, type))
1319                 return -EOPNOTSUPP;
1320
1321         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1322                 if (type != NL80211_IFTYPE_AP &&
1323                     type != NL80211_IFTYPE_MESH_POINT)
1324                         rtl88ee_set_check_bssid(hw, true);
1325         } else {
1326                 rtl88ee_set_check_bssid(hw, false);
1327         }
1328
1329         return 0;
1330 }
1331
1332 /* don't set REG_EDCA_BE_PARAM here
1333  * because mac80211 will send pkt when scan
1334  */
1335 void rtl88ee_set_qos(struct ieee80211_hw *hw, int aci)
1336 {
1337         struct rtl_priv *rtlpriv = rtl_priv(hw);
1338         rtl88e_dm_init_edca_turbo(hw);
1339         switch (aci) {
1340         case AC1_BK:
1341                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1342                 break;
1343         case AC0_BE:
1344                 break;
1345         case AC2_VI:
1346                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1347                 break;
1348         case AC3_VO:
1349                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1350                 break;
1351         default:
1352                 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1353                 break;
1354         }
1355 }
1356
1357 void rtl88ee_enable_interrupt(struct ieee80211_hw *hw)
1358 {
1359         struct rtl_priv *rtlpriv = rtl_priv(hw);
1360         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1361
1362         rtl_write_dword(rtlpriv, REG_HIMR,
1363                         rtlpci->irq_mask[0] & 0xFFFFFFFF);
1364         rtl_write_dword(rtlpriv, REG_HIMRE,
1365                         rtlpci->irq_mask[1] & 0xFFFFFFFF);
1366         rtlpci->irq_enabled = true;
1367         /* there are some C2H CMDs have been sent
1368          * before system interrupt is enabled, e.g., C2H, CPWM.
1369          * So we need to clear all C2H events that FW has notified,
1370          * otherwise FW won't schedule any commands anymore.
1371          */
1372         rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0);
1373         /*enable system interrupt*/
1374         rtl_write_dword(rtlpriv, REG_HSIMR,
1375                         rtlpci->sys_irq_mask & 0xFFFFFFFF);
1376 }
1377
1378 void rtl88ee_disable_interrupt(struct ieee80211_hw *hw)
1379 {
1380         struct rtl_priv *rtlpriv = rtl_priv(hw);
1381         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1382
1383         rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1384         rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1385         rtlpci->irq_enabled = false;
1386         /*synchronize_irq(rtlpci->pdev->irq);*/
1387 }
1388
1389 static void _rtl88ee_poweroff_adapter(struct ieee80211_hw *hw)
1390 {
1391         struct rtl_priv *rtlpriv = rtl_priv(hw);
1392         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1393         u8 u1b_tmp;
1394         u32 count = 0;
1395         rtlhal->mac_func_enable = false;
1396         rtlpriv->intf_ops->enable_aspm(hw);
1397
1398         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n");
1399         u1b_tmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);
1400         rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, u1b_tmp & (~BIT(1)));
1401
1402         u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1403         while (!(u1b_tmp & BIT(1)) && (count++ < 100)) {
1404                 udelay(10);
1405                 u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1406                 count++;
1407         }
1408         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0xFF);
1409
1410         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1411                                  PWR_INTF_PCI_MSK,
1412                                  RTL8188EE_NIC_LPS_ENTER_FLOW);
1413
1414         rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1415
1416         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1417                 rtl88e_firmware_selfreset(hw);
1418
1419         u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1420         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1421         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1422
1423         u1b_tmp = rtl_read_byte(rtlpriv, REG_32K_CTRL);
1424         rtl_write_byte(rtlpriv, REG_32K_CTRL, (u1b_tmp & (~BIT(0))));
1425
1426         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1427                                  PWR_INTF_PCI_MSK, RTL8188EE_NIC_DISABLE_FLOW);
1428
1429         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1430         rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(3))));
1431         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1432         rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp | BIT(3)));
1433
1434         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1435
1436         u1b_tmp = rtl_read_byte(rtlpriv, GPIO_IN);
1437         rtl_write_byte(rtlpriv, GPIO_OUT, u1b_tmp);
1438         rtl_write_byte(rtlpriv, GPIO_IO_SEL, 0x7F);
1439
1440         u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
1441         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL, (u1b_tmp << 4) | u1b_tmp);
1442         u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL+1);
1443         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL+1, u1b_tmp | 0x0F);
1444
1445         rtl_write_dword(rtlpriv, REG_GPIO_IO_SEL_2+2, 0x00080808);
1446 }
1447
1448 void rtl88ee_card_disable(struct ieee80211_hw *hw)
1449 {
1450         struct rtl_priv *rtlpriv = rtl_priv(hw);
1451         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1452         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1453         enum nl80211_iftype opmode;
1454
1455         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8188ee card disable\n");
1456
1457         mac->link_state = MAC80211_NOLINK;
1458         opmode = NL80211_IFTYPE_UNSPECIFIED;
1459
1460         _rtl88ee_set_media_status(hw, opmode);
1461
1462         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1463             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1464                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1465
1466         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1467         _rtl88ee_poweroff_adapter(hw);
1468
1469         /* after power off we should do iqk again */
1470         rtlpriv->phy.iqk_initialized = false;
1471 }
1472
1473 void rtl88ee_interrupt_recognized(struct ieee80211_hw *hw,
1474                                   u32 *p_inta, u32 *p_intb)
1475 {
1476         struct rtl_priv *rtlpriv = rtl_priv(hw);
1477         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1478
1479         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1480         rtl_write_dword(rtlpriv, ISR, *p_inta);
1481
1482         *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1483         rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
1484
1485 }
1486
1487 void rtl88ee_set_beacon_related_registers(struct ieee80211_hw *hw)
1488 {
1489         struct rtl_priv *rtlpriv = rtl_priv(hw);
1490         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1491         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1492         u16 bcn_interval, atim_window;
1493
1494         bcn_interval = mac->beacon_interval;
1495         atim_window = 2;        /*FIX MERGE */
1496         rtl88ee_disable_interrupt(hw);
1497         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1498         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1499         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1500         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1501         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1502         rtl_write_byte(rtlpriv, 0x606, 0x30);
1503         rtlpci->reg_bcn_ctrl_val |= BIT(3);
1504         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
1505         /*rtl88ee_enable_interrupt(hw);*/
1506 }
1507
1508 void rtl88ee_set_beacon_interval(struct ieee80211_hw *hw)
1509 {
1510         struct rtl_priv *rtlpriv = rtl_priv(hw);
1511         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1512         u16 bcn_interval = mac->beacon_interval;
1513
1514         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1515                  "beacon_interval:%d\n", bcn_interval);
1516         /*rtl88ee_disable_interrupt(hw);*/
1517         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1518         /*rtl88ee_enable_interrupt(hw);*/
1519 }
1520
1521 void rtl88ee_update_interrupt_mask(struct ieee80211_hw *hw,
1522                                    u32 add_msr, u32 rm_msr)
1523 {
1524         struct rtl_priv *rtlpriv = rtl_priv(hw);
1525         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1526
1527         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1528                  "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1529
1530         if (add_msr)
1531                 rtlpci->irq_mask[0] |= add_msr;
1532         if (rm_msr)
1533                 rtlpci->irq_mask[0] &= (~rm_msr);
1534         rtl88ee_disable_interrupt(hw);
1535         rtl88ee_enable_interrupt(hw);
1536 }
1537
1538 static u8 _rtl88e_get_chnl_group(u8 chnl)
1539 {
1540         u8 group = 0;
1541
1542         if (chnl < 3)
1543                 group = 0;
1544         else if (chnl < 6)
1545                 group = 1;
1546         else if (chnl < 9)
1547                 group = 2;
1548         else if (chnl < 12)
1549                 group = 3;
1550         else if (chnl < 14)
1551                 group = 4;
1552         else if (chnl == 14)
1553                 group = 5;
1554
1555         return group;
1556 }
1557
1558 static void set_24g_base(struct txpower_info_2g *pwrinfo24g, u32 rfpath)
1559 {
1560         int group, txcnt;
1561
1562         for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1563                 pwrinfo24g->index_cck_base[rfpath][group] = 0x2D;
1564                 pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D;
1565         }
1566         for (txcnt = 0; txcnt < MAX_TX_COUNT; txcnt++) {
1567                 if (txcnt == 0) {
1568                         pwrinfo24g->bw20_diff[rfpath][0] = 0x02;
1569                         pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;
1570                 } else {
1571                         pwrinfo24g->bw20_diff[rfpath][txcnt] = 0xFE;
1572                         pwrinfo24g->bw40_diff[rfpath][txcnt] = 0xFE;
1573                         pwrinfo24g->cck_diff[rfpath][txcnt] =   0xFE;
1574                         pwrinfo24g->ofdm_diff[rfpath][txcnt] = 0xFE;
1575                 }
1576         }
1577 }
1578
1579 static void read_power_value_fromprom(struct ieee80211_hw *hw,
1580                                       struct txpower_info_2g *pwrinfo24g,
1581                                       struct txpower_info_5g *pwrinfo5g,
1582                                       bool autoload_fail, u8 *hwinfo)
1583 {
1584         struct rtl_priv *rtlpriv = rtl_priv(hw);
1585         u32 rfpath, eeaddr = EEPROM_TX_PWR_INX, group, txcnt = 0;
1586
1587         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1588                  "hal_ReadPowerValueFromPROM88E():PROMContent[0x%x]=0x%x\n",
1589                  (eeaddr+1), hwinfo[eeaddr+1]);
1590         if (0xFF == hwinfo[eeaddr+1])  /*YJ,add,120316*/
1591                 autoload_fail = true;
1592
1593         if (autoload_fail) {
1594                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1595                          "auto load fail : Use Default value!\n");
1596                 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
1597                         /* 2.4G default value */
1598                         set_24g_base(pwrinfo24g, rfpath);
1599                 }
1600                 return;
1601         }
1602
1603         for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
1604                 /*2.4G default value*/
1605                 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1606                         pwrinfo24g->index_cck_base[rfpath][group] =
1607                           hwinfo[eeaddr++];
1608                         if (pwrinfo24g->index_cck_base[rfpath][group] == 0xFF)
1609                                 pwrinfo24g->index_cck_base[rfpath][group] =
1610                                   0x2D;
1611                 }
1612                 for (group = 0 ; group < MAX_CHNL_GROUP_24G-1; group++) {
1613                         pwrinfo24g->index_bw40_base[rfpath][group] =
1614                                 hwinfo[eeaddr++];
1615                         if (pwrinfo24g->index_bw40_base[rfpath][group] == 0xFF)
1616                                 pwrinfo24g->index_bw40_base[rfpath][group] =
1617                                         0x2D;
1618                 }
1619                 pwrinfo24g->bw40_diff[rfpath][0] = 0;
1620                 if (hwinfo[eeaddr] == 0xFF) {
1621                         pwrinfo24g->bw20_diff[rfpath][0] = 0x02;
1622                 } else {
1623                         pwrinfo24g->bw20_diff[rfpath][0] =
1624                                 (hwinfo[eeaddr]&0xf0)>>4;
1625                         /*bit sign number to 8 bit sign number*/
1626                         if (pwrinfo24g->bw20_diff[rfpath][0] & BIT(3))
1627                                 pwrinfo24g->bw20_diff[rfpath][0] |= 0xF0;
1628                 }
1629
1630                 if (hwinfo[eeaddr] == 0xFF) {
1631                         pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;
1632                 } else {
1633                         pwrinfo24g->ofdm_diff[rfpath][0] =
1634                                 (hwinfo[eeaddr]&0x0f);
1635                                 /*bit sign number to 8 bit sign number*/
1636                         if (pwrinfo24g->ofdm_diff[rfpath][0] & BIT(3))
1637                                 pwrinfo24g->ofdm_diff[rfpath][0] |= 0xF0;
1638                 }
1639                 pwrinfo24g->cck_diff[rfpath][0] = 0;
1640                 eeaddr++;
1641                 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1642                         if (hwinfo[eeaddr] == 0xFF) {
1643                                 pwrinfo24g->bw40_diff[rfpath][txcnt] = 0xFE;
1644                         } else {
1645                                 pwrinfo24g->bw40_diff[rfpath][txcnt] =
1646                                   (hwinfo[eeaddr]&0xf0)>>4;
1647                                 if (pwrinfo24g->bw40_diff[rfpath][txcnt] &
1648                                     BIT(3))
1649                                         pwrinfo24g->bw40_diff[rfpath][txcnt] |=
1650                                           0xF0;
1651                         }
1652
1653                         if (hwinfo[eeaddr] == 0xFF) {
1654                                 pwrinfo24g->bw20_diff[rfpath][txcnt] =
1655                                         0xFE;
1656                         } else {
1657                                 pwrinfo24g->bw20_diff[rfpath][txcnt] =
1658                                   (hwinfo[eeaddr]&0x0f);
1659                                 if (pwrinfo24g->bw20_diff[rfpath][txcnt] &
1660                                     BIT(3))
1661                                         pwrinfo24g->bw20_diff[rfpath][txcnt] |=
1662                                           0xF0;
1663                         }
1664                         eeaddr++;
1665
1666                         if (hwinfo[eeaddr] == 0xFF) {
1667                                 pwrinfo24g->ofdm_diff[rfpath][txcnt] = 0xFE;
1668                         } else {
1669                                 pwrinfo24g->ofdm_diff[rfpath][txcnt] =
1670                                   (hwinfo[eeaddr]&0xf0)>>4;
1671                                 if (pwrinfo24g->ofdm_diff[rfpath][txcnt] &
1672                                     BIT(3))
1673                                         pwrinfo24g->ofdm_diff[rfpath][txcnt] |=
1674                                           0xF0;
1675                         }
1676
1677                         if (hwinfo[eeaddr] == 0xFF) {
1678                                 pwrinfo24g->cck_diff[rfpath][txcnt] =   0xFE;
1679                         } else {
1680                                 pwrinfo24g->cck_diff[rfpath][txcnt] =
1681                                   (hwinfo[eeaddr]&0x0f);
1682                                 if (pwrinfo24g->cck_diff[rfpath][txcnt] &
1683                                     BIT(3))
1684                                         pwrinfo24g->cck_diff[rfpath][txcnt] |=
1685                                           0xF0;
1686                         }
1687                         eeaddr++;
1688                 }
1689
1690                 /*5G default value*/
1691                 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
1692                         pwrinfo5g->index_bw40_base[rfpath][group] =
1693                                 hwinfo[eeaddr++];
1694                         if (pwrinfo5g->index_bw40_base[rfpath][group] == 0xFF)
1695                                 pwrinfo5g->index_bw40_base[rfpath][group] =
1696                                   0xFE;
1697                 }
1698
1699                 pwrinfo5g->bw40_diff[rfpath][0] = 0;
1700
1701                 if (hwinfo[eeaddr] == 0xFF) {
1702                         pwrinfo5g->bw20_diff[rfpath][0] = 0;
1703                 } else {
1704                         pwrinfo5g->bw20_diff[rfpath][0] =
1705                           (hwinfo[eeaddr]&0xf0)>>4;
1706                         if (pwrinfo5g->bw20_diff[rfpath][0] & BIT(3))
1707                                 pwrinfo5g->bw20_diff[rfpath][0] |= 0xF0;
1708                 }
1709
1710                 if (hwinfo[eeaddr] == 0xFF) {
1711                         pwrinfo5g->ofdm_diff[rfpath][0] = 0x04;
1712                 } else {
1713                         pwrinfo5g->ofdm_diff[rfpath][0] = (hwinfo[eeaddr]&0x0f);
1714                         if (pwrinfo5g->ofdm_diff[rfpath][0] & BIT(3))
1715                                 pwrinfo5g->ofdm_diff[rfpath][0] |= 0xF0;
1716                 }
1717                 eeaddr++;
1718                 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1719                         if (hwinfo[eeaddr] == 0xFF) {
1720                                 pwrinfo5g->bw40_diff[rfpath][txcnt] =   0xFE;
1721                         } else {
1722                                 pwrinfo5g->bw40_diff[rfpath][txcnt] =
1723                                   (hwinfo[eeaddr]&0xf0)>>4;
1724                                 if (pwrinfo5g->bw40_diff[rfpath][txcnt] &
1725                                     BIT(3))
1726                                         pwrinfo5g->bw40_diff[rfpath][txcnt] |=
1727                                           0xF0;
1728                         }
1729
1730                         if (hwinfo[eeaddr] == 0xFF) {
1731                                 pwrinfo5g->bw20_diff[rfpath][txcnt] =   0xFE;
1732                         } else {
1733                                 pwrinfo5g->bw20_diff[rfpath][txcnt] =
1734                                   (hwinfo[eeaddr]&0x0f);
1735                                 if (pwrinfo5g->bw20_diff[rfpath][txcnt] &
1736                                     BIT(3))
1737                                         pwrinfo5g->bw20_diff[rfpath][txcnt] |=
1738                                           0xF0;
1739                         }
1740                         eeaddr++;
1741                 }
1742
1743                 if (hwinfo[eeaddr] == 0xFF) {
1744                         pwrinfo5g->ofdm_diff[rfpath][1] = 0xFE;
1745                         pwrinfo5g->ofdm_diff[rfpath][2] = 0xFE;
1746                 } else {
1747                         pwrinfo5g->ofdm_diff[rfpath][1] =
1748                                         (hwinfo[eeaddr]&0xf0)>>4;
1749                         pwrinfo5g->ofdm_diff[rfpath][2] =
1750                                         (hwinfo[eeaddr]&0x0f);
1751                 }
1752                 eeaddr++;
1753
1754                 if (hwinfo[eeaddr] == 0xFF)
1755                         pwrinfo5g->ofdm_diff[rfpath][3] = 0xFE;
1756                 else
1757                         pwrinfo5g->ofdm_diff[rfpath][3] = (hwinfo[eeaddr]&0x0f);
1758                 eeaddr++;
1759
1760                 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1761                         if (pwrinfo5g->ofdm_diff[rfpath][txcnt] == 0xFF)
1762                                 pwrinfo5g->ofdm_diff[rfpath][txcnt] =   0xFE;
1763                         else if (pwrinfo5g->ofdm_diff[rfpath][txcnt] & BIT(3))
1764                                 pwrinfo5g->ofdm_diff[rfpath][txcnt] |= 0xF0;
1765                 }
1766         }
1767 }
1768
1769 static void _rtl88ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1770                                                  bool autoload_fail,
1771                                                  u8 *hwinfo)
1772 {
1773         struct rtl_priv *rtlpriv = rtl_priv(hw);
1774         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1775         struct txpower_info_2g pwrinfo24g;
1776         struct txpower_info_5g pwrinfo5g;
1777         u8 rf_path, index;
1778         u8 i;
1779
1780         read_power_value_fromprom(hw, &pwrinfo24g,
1781                                   &pwrinfo5g, autoload_fail, hwinfo);
1782
1783         for (rf_path = 0; rf_path < 2; rf_path++) {
1784                 for (i = 0; i < 14; i++) {
1785                         index = _rtl88e_get_chnl_group(i+1);
1786
1787                         rtlefuse->txpwrlevel_cck[rf_path][i] =
1788                                 pwrinfo24g.index_cck_base[rf_path][index];
1789                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1790                                 pwrinfo24g.index_bw40_base[rf_path][index];
1791                         rtlefuse->txpwr_ht20diff[rf_path][i] =
1792                                 pwrinfo24g.bw20_diff[rf_path][0];
1793                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
1794                                 pwrinfo24g.ofdm_diff[rf_path][0];
1795                 }
1796
1797                 for (i = 0; i < 14; i++) {
1798                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1799                                 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = [0x%x / 0x%x ]\n",
1800                                 rf_path, i,
1801                                 rtlefuse->txpwrlevel_cck[rf_path][i],
1802                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]);
1803                 }
1804         }
1805
1806         if (!autoload_fail)
1807                 rtlefuse->eeprom_thermalmeter =
1808                         hwinfo[EEPROM_THERMAL_METER_88E];
1809         else
1810                 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1811
1812         if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) {
1813                 rtlefuse->apk_thermalmeterignore = true;
1814                 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1815         }
1816
1817         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1818         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1819                 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1820
1821         if (!autoload_fail) {
1822                 rtlefuse->eeprom_regulatory =
1823                         hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x07;/*bit0~2*/
1824                 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
1825                         rtlefuse->eeprom_regulatory = 0;
1826         } else {
1827                 rtlefuse->eeprom_regulatory = 0;
1828         }
1829         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1830                 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1831 }
1832
1833 static void _rtl88ee_read_adapter_info(struct ieee80211_hw *hw)
1834 {
1835         struct rtl_priv *rtlpriv = rtl_priv(hw);
1836         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1837         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1838         u16 i, usvalue;
1839         u8 hwinfo[HWSET_MAX_SIZE];
1840         u16 eeprom_id;
1841
1842         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1843                 rtl_efuse_shadow_map_update(hw);
1844
1845                 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1846                        HWSET_MAX_SIZE);
1847         } else if (rtlefuse->epromtype == EEPROM_93C46) {
1848                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1849                          "RTL819X Not boot from eeprom, check it !!");
1850                 return;
1851         } else {
1852                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1853                          "boot from neither eeprom nor efuse, check it !!");
1854                 return;
1855         }
1856
1857         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP\n",
1858                       hwinfo, HWSET_MAX_SIZE);
1859
1860         eeprom_id = *((u16 *)&hwinfo[0]);
1861         if (eeprom_id != RTL8188E_EEPROM_ID) {
1862                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1863                          "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1864                 rtlefuse->autoload_failflag = true;
1865         } else {
1866                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1867                 rtlefuse->autoload_failflag = false;
1868         }
1869
1870         if (rtlefuse->autoload_failflag == true)
1871                 return;
1872         /*VID DID SVID SDID*/
1873         rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1874         rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1875         rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1876         rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1877         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1878                  "EEPROMId = 0x%4x\n", eeprom_id);
1879         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1880                  "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1881         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1882                  "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1883         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1884                  "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1885         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1886                  "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1887         /*customer ID*/
1888         rtlefuse->eeprom_oemid = hwinfo[EEPROM_CUSTOMER_ID];
1889         if (rtlefuse->eeprom_oemid == 0xFF)
1890                 rtlefuse->eeprom_oemid =        0;
1891
1892         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1893                  "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
1894         /*EEPROM version*/
1895         rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1896         /*mac address*/
1897         for (i = 0; i < 6; i += 2) {
1898                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1899                 *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue;
1900         }
1901
1902         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1903                  "dev_addr: %pM\n", rtlefuse->dev_addr);
1904         /*channel plan */
1905         rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN];
1906         /* set channel plan from efuse */
1907         rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
1908         /*tx power*/
1909         _rtl88ee_read_txpower_info_from_hwpg(hw,
1910                                              rtlefuse->autoload_failflag,
1911                                              hwinfo);
1912         rtlefuse->txpwr_fromeprom = true;
1913
1914         rtl8188ee_read_bt_coexist_info_from_hwpg(hw,
1915                                                  rtlefuse->autoload_failflag,
1916                                                  hwinfo);
1917
1918         /*board type*/
1919         rtlefuse->board_type =
1920                 ((hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0xE0) >> 5);
1921         rtlhal->board_type = rtlefuse->board_type;
1922         /*Wake on wlan*/
1923         rtlefuse->wowlan_enable =
1924                 ((hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & 0x40) >> 6);
1925         /*parse xtal*/
1926         rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_88E];
1927         if (hwinfo[EEPROM_XTAL_88E])
1928                 rtlefuse->crystalcap = 0x20;
1929         /*antenna diversity*/
1930         rtlefuse->antenna_div_cfg =
1931                 (hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x18) >> 3;
1932         if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
1933                 rtlefuse->antenna_div_cfg = 0;
1934         if (rtlpriv->btcoexist.eeprom_bt_coexist != 0 &&
1935             rtlpriv->btcoexist.eeprom_bt_ant_num == ANT_X1)
1936                 rtlefuse->antenna_div_cfg = 0;
1937
1938         rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
1939         if (rtlefuse->antenna_div_type == 0xFF)
1940                 rtlefuse->antenna_div_type = 0x01;
1941         if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV ||
1942                 rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1943                 rtlefuse->antenna_div_cfg = 1;
1944
1945         if (rtlhal->oem_id == RT_CID_DEFAULT) {
1946                 switch (rtlefuse->eeprom_oemid) {
1947                 case EEPROM_CID_DEFAULT:
1948                         if (rtlefuse->eeprom_did == 0x8179) {
1949                                 if (rtlefuse->eeprom_svid == 0x1025) {
1950                                         rtlhal->oem_id = RT_CID_819X_ACER;
1951                                 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
1952                                      rtlefuse->eeprom_smid == 0x0179) ||
1953                                      (rtlefuse->eeprom_svid == 0x17AA &&
1954                                      rtlefuse->eeprom_smid == 0x0179)) {
1955                                         rtlhal->oem_id = RT_CID_819X_LENOVO;
1956                                 } else if (rtlefuse->eeprom_svid == 0x103c &&
1957                                            rtlefuse->eeprom_smid == 0x197d) {
1958                                         rtlhal->oem_id = RT_CID_819X_HP;
1959                                 } else {
1960                                         rtlhal->oem_id = RT_CID_DEFAULT;
1961                                 }
1962                         } else {
1963                                 rtlhal->oem_id = RT_CID_DEFAULT;
1964                         }
1965                         break;
1966                 case EEPROM_CID_TOSHIBA:
1967                         rtlhal->oem_id = RT_CID_TOSHIBA;
1968                         break;
1969                 case EEPROM_CID_QMI:
1970                         rtlhal->oem_id = RT_CID_819X_QMI;
1971                         break;
1972                 case EEPROM_CID_WHQL:
1973                 default:
1974                         rtlhal->oem_id = RT_CID_DEFAULT;
1975                         break;
1976
1977                 }
1978         }
1979 }
1980
1981 static void _rtl88ee_hal_customized_behavior(struct ieee80211_hw *hw)
1982 {
1983         struct rtl_priv *rtlpriv = rtl_priv(hw);
1984         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1985         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1986
1987         pcipriv->ledctl.led_opendrain = true;
1988
1989         switch (rtlhal->oem_id) {
1990         case RT_CID_819X_HP:
1991                 pcipriv->ledctl.led_opendrain = true;
1992                 break;
1993         case RT_CID_819X_LENOVO:
1994         case RT_CID_DEFAULT:
1995         case RT_CID_TOSHIBA:
1996         case RT_CID_CCX:
1997         case RT_CID_819X_ACER:
1998         case RT_CID_WHQL:
1999         default:
2000                 break;
2001         }
2002         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2003                  "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
2004 }
2005
2006 void rtl88ee_read_eeprom_info(struct ieee80211_hw *hw)
2007 {
2008         struct rtl_priv *rtlpriv = rtl_priv(hw);
2009         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2010         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2011         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2012         u8 tmp_u1b;
2013
2014         rtlhal->version = _rtl88ee_read_chip_version(hw);
2015         if (get_rf_type(rtlphy) == RF_1T1R)
2016                 rtlpriv->dm.rfpath_rxenable[0] = true;
2017         else
2018                 rtlpriv->dm.rfpath_rxenable[0] =
2019                     rtlpriv->dm.rfpath_rxenable[1] = true;
2020         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
2021                                                 rtlhal->version);
2022         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
2023         if (tmp_u1b & BIT(4)) {
2024                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2025                 rtlefuse->epromtype = EEPROM_93C46;
2026         } else {
2027                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2028                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2029         }
2030         if (tmp_u1b & BIT(5)) {
2031                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2032                 rtlefuse->autoload_failflag = false;
2033                 _rtl88ee_read_adapter_info(hw);
2034         } else {
2035                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
2036         }
2037         _rtl88ee_hal_customized_behavior(hw);
2038 }
2039
2040 static void rtl88ee_update_hal_rate_table(struct ieee80211_hw *hw,
2041                 struct ieee80211_sta *sta)
2042 {
2043         struct rtl_priv *rtlpriv = rtl_priv(hw);
2044         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2045         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2046         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2047         u32 ratr_value;
2048         u8 ratr_index = 0;
2049         u8 b_nmode = mac->ht_enable;
2050         /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
2051         u16 shortgi_rate;
2052         u32 tmp_ratr_value;
2053         u8 curtxbw_40mhz = mac->bw_40;
2054         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2055                                 1 : 0;
2056         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2057                                 1 : 0;
2058         enum wireless_mode wirelessmode = mac->mode;
2059         u32 ratr_mask;
2060
2061         if (rtlhal->current_bandtype == BAND_ON_5G)
2062                 ratr_value = sta->supp_rates[1] << 4;
2063         else
2064                 ratr_value = sta->supp_rates[0];
2065         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2066                 ratr_value = 0xfff;
2067         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2068                        sta->ht_cap.mcs.rx_mask[0] << 12);
2069         switch (wirelessmode) {
2070         case WIRELESS_MODE_B:
2071                 if (ratr_value & 0x0000000c)
2072                         ratr_value &= 0x0000000d;
2073                 else
2074                         ratr_value &= 0x0000000f;
2075                 break;
2076         case WIRELESS_MODE_G:
2077                 ratr_value &= 0x00000FF5;
2078                 break;
2079         case WIRELESS_MODE_N_24G:
2080         case WIRELESS_MODE_N_5G:
2081                 b_nmode = 1;
2082                 if (get_rf_type(rtlphy) == RF_1T2R ||
2083                     get_rf_type(rtlphy) == RF_1T1R)
2084                         ratr_mask = 0x000ff005;
2085                 else
2086                         ratr_mask = 0x0f0ff005;
2087
2088                 ratr_value &= ratr_mask;
2089                 break;
2090         default:
2091                 if (rtlphy->rf_type == RF_1T2R)
2092                         ratr_value &= 0x000ff0ff;
2093                 else
2094                         ratr_value &= 0x0f0ff0ff;
2095
2096                 break;
2097         }
2098
2099         if ((rtlpriv->btcoexist.bt_coexistence) &&
2100             (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
2101             (rtlpriv->btcoexist.bt_cur_state) &&
2102             (rtlpriv->btcoexist.bt_ant_isolation) &&
2103             ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
2104              (rtlpriv->btcoexist.bt_service == BT_BUSY)))
2105                 ratr_value &= 0x0fffcfc0;
2106         else
2107                 ratr_value &= 0x0FFFFFFF;
2108
2109         if (b_nmode &&
2110             ((curtxbw_40mhz && curshortgi_40mhz) ||
2111              (!curtxbw_40mhz && curshortgi_20mhz))) {
2112                 ratr_value |= 0x10000000;
2113                 tmp_ratr_value = (ratr_value >> 12);
2114
2115                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2116                         if ((1 << shortgi_rate) & tmp_ratr_value)
2117                                 break;
2118                 }
2119
2120                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2121                     (shortgi_rate << 4) | (shortgi_rate);
2122         }
2123
2124         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2125
2126         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2127                  "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
2128 }
2129
2130 static void rtl88ee_update_hal_rate_mask(struct ieee80211_hw *hw,
2131                 struct ieee80211_sta *sta, u8 rssi_level)
2132 {
2133         struct rtl_priv *rtlpriv = rtl_priv(hw);
2134         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2135         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2136         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2137         struct rtl_sta_info *sta_entry = NULL;
2138         u32 ratr_bitmap;
2139         u8 ratr_index;
2140         u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2141                                 ? 1 : 0;
2142         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2143                                 1 : 0;
2144         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2145                                 1 : 0;
2146         enum wireless_mode wirelessmode = 0;
2147         bool b_shortgi = false;
2148         u8 rate_mask[5];
2149         u8 macid = 0;
2150         /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
2151
2152         sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2153         wirelessmode = sta_entry->wireless_mode;
2154         if (mac->opmode == NL80211_IFTYPE_STATION ||
2155                 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2156                 curtxbw_40mhz = mac->bw_40;
2157         else if (mac->opmode == NL80211_IFTYPE_AP ||
2158                 mac->opmode == NL80211_IFTYPE_ADHOC)
2159                 macid = sta->aid + 1;
2160
2161         if (rtlhal->current_bandtype == BAND_ON_5G)
2162                 ratr_bitmap = sta->supp_rates[1] << 4;
2163         else
2164                 ratr_bitmap = sta->supp_rates[0];
2165         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2166                 ratr_bitmap = 0xfff;
2167         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2168                         sta->ht_cap.mcs.rx_mask[0] << 12);
2169         switch (wirelessmode) {
2170         case WIRELESS_MODE_B:
2171                 ratr_index = RATR_INX_WIRELESS_B;
2172                 if (ratr_bitmap & 0x0000000c)
2173                         ratr_bitmap &= 0x0000000d;
2174                 else
2175                         ratr_bitmap &= 0x0000000f;
2176                 break;
2177         case WIRELESS_MODE_G:
2178                 ratr_index = RATR_INX_WIRELESS_GB;
2179
2180                 if (rssi_level == 1)
2181                         ratr_bitmap &= 0x00000f00;
2182                 else if (rssi_level == 2)
2183                         ratr_bitmap &= 0x00000ff0;
2184                 else
2185                         ratr_bitmap &= 0x00000ff5;
2186                 break;
2187         case WIRELESS_MODE_N_24G:
2188         case WIRELESS_MODE_N_5G:
2189                 ratr_index = RATR_INX_WIRELESS_NGB;
2190                 if (rtlphy->rf_type == RF_1T2R ||
2191                     rtlphy->rf_type == RF_1T1R) {
2192                         if (curtxbw_40mhz) {
2193                                 if (rssi_level == 1)
2194                                         ratr_bitmap &= 0x000f0000;
2195                                 else if (rssi_level == 2)
2196                                         ratr_bitmap &= 0x000ff000;
2197                                 else
2198                                         ratr_bitmap &= 0x000ff015;
2199                         } else {
2200                                 if (rssi_level == 1)
2201                                         ratr_bitmap &= 0x000f0000;
2202                                 else if (rssi_level == 2)
2203                                         ratr_bitmap &= 0x000ff000;
2204                                 else
2205                                         ratr_bitmap &= 0x000ff005;
2206                         }
2207                 } else {
2208                         if (curtxbw_40mhz) {
2209                                 if (rssi_level == 1)
2210                                         ratr_bitmap &= 0x0f8f0000;
2211                                 else if (rssi_level == 2)
2212                                         ratr_bitmap &= 0x0f8ff000;
2213                                 else
2214                                         ratr_bitmap &= 0x0f8ff015;
2215                         } else {
2216                                 if (rssi_level == 1)
2217                                         ratr_bitmap &= 0x0f8f0000;
2218                                 else if (rssi_level == 2)
2219                                         ratr_bitmap &= 0x0f8ff000;
2220                                 else
2221                                         ratr_bitmap &= 0x0f8ff005;
2222                         }
2223                 }
2224                 /*}*/
2225
2226                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2227                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2228
2229                         if (macid == 0)
2230                                 b_shortgi = true;
2231                         else if (macid == 1)
2232                                 b_shortgi = false;
2233                 }
2234                 break;
2235         default:
2236                 ratr_index = RATR_INX_WIRELESS_NGB;
2237
2238                 if (rtlphy->rf_type == RF_1T2R)
2239                         ratr_bitmap &= 0x000ff0ff;
2240                 else
2241                         ratr_bitmap &= 0x0f0ff0ff;
2242                 break;
2243         }
2244         sta_entry->ratr_index = ratr_index;
2245
2246         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2247                  "ratr_bitmap :%x\n", ratr_bitmap);
2248         *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2249                              (ratr_index << 28);
2250         rate_mask[4] = macid | (b_shortgi ? 0x20 : 0x00) | 0x80;
2251         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2252                  "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
2253                  ratr_index, ratr_bitmap,
2254                  rate_mask[0], rate_mask[1],
2255                  rate_mask[2], rate_mask[3],
2256                  rate_mask[4]);
2257         rtl88e_fill_h2c_cmd(hw, H2C_88E_RA_MASK, 5, rate_mask);
2258         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
2259 }
2260
2261 void rtl88ee_update_hal_rate_tbl(struct ieee80211_hw *hw,
2262                 struct ieee80211_sta *sta, u8 rssi_level)
2263 {
2264         struct rtl_priv *rtlpriv = rtl_priv(hw);
2265
2266         if (rtlpriv->dm.useramask)
2267                 rtl88ee_update_hal_rate_mask(hw, sta, rssi_level);
2268         else
2269                 rtl88ee_update_hal_rate_table(hw, sta);
2270 }
2271
2272 void rtl88ee_update_channel_access_setting(struct ieee80211_hw *hw)
2273 {
2274         struct rtl_priv *rtlpriv = rtl_priv(hw);
2275         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2276         u16 sifs_timer;
2277
2278         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time);
2279         if (!mac->ht_enable)
2280                 sifs_timer = 0x0a0a;
2281         else
2282                 sifs_timer = 0x0e0e;
2283         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2284 }
2285
2286 bool rtl88ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2287 {
2288         struct rtl_priv *rtlpriv = rtl_priv(hw);
2289         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2290         enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2291         u32 u4tmp;
2292         bool b_actuallyset = false;
2293
2294         if (rtlpriv->rtlhal.being_init_adapter)
2295                 return false;
2296
2297         if (ppsc->swrf_processing)
2298                 return false;
2299
2300         spin_lock(&rtlpriv->locks.rf_ps_lock);
2301         if (ppsc->rfchange_inprogress) {
2302                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2303                 return false;
2304         } else {
2305                 ppsc->rfchange_inprogress = true;
2306                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2307         }
2308
2309         cur_rfstate = ppsc->rfpwr_state;
2310
2311         u4tmp = rtl_read_dword(rtlpriv, REG_GPIO_OUTPUT);
2312         e_rfpowerstate_toset = (u4tmp & BIT(31)) ? ERFON : ERFOFF;
2313
2314         if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2315                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2316                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
2317
2318                 e_rfpowerstate_toset = ERFON;
2319                 ppsc->hwradiooff = false;
2320                 b_actuallyset = true;
2321         } else if ((!ppsc->hwradiooff) &&
2322                    (e_rfpowerstate_toset == ERFOFF)) {
2323                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2324                          "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2325
2326                 e_rfpowerstate_toset = ERFOFF;
2327                 ppsc->hwradiooff = true;
2328                 b_actuallyset = true;
2329         }
2330
2331         if (b_actuallyset) {
2332                 spin_lock(&rtlpriv->locks.rf_ps_lock);
2333                 ppsc->rfchange_inprogress = false;
2334                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2335         } else {
2336                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2337                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2338
2339                 spin_lock(&rtlpriv->locks.rf_ps_lock);
2340                 ppsc->rfchange_inprogress = false;
2341                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2342         }
2343
2344         *valid = 1;
2345         return !ppsc->hwradiooff;
2346
2347 }
2348
2349 void rtl88ee_set_key(struct ieee80211_hw *hw, u32 key_index,
2350                      u8 *p_macaddr, bool is_group, u8 enc_algo,
2351                      bool is_wepkey, bool clear_all)
2352 {
2353         struct rtl_priv *rtlpriv = rtl_priv(hw);
2354         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2355         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2356         u8 *macaddr = p_macaddr;
2357         u32 entry_id = 0;
2358         bool is_pairwise = false;
2359         static u8 cam_const_addr[4][6] = {
2360                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2361                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2362                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2363                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2364         };
2365         static u8 cam_const_broad[] = {
2366                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2367         };
2368
2369         if (clear_all) {
2370                 u8 idx = 0;
2371                 u8 cam_offset = 0;
2372                 u8 clear_number = 5;
2373
2374                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2375
2376                 for (idx = 0; idx < clear_number; idx++) {
2377                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2378                         rtl_cam_empty_entry(hw, cam_offset + idx);
2379
2380                         if (idx < 5) {
2381                                 memset(rtlpriv->sec.key_buf[idx], 0,
2382                                        MAX_KEY_LEN);
2383                                 rtlpriv->sec.key_len[idx] = 0;
2384                         }
2385                 }
2386
2387         } else {
2388                 switch (enc_algo) {
2389                 case WEP40_ENCRYPTION:
2390                         enc_algo = CAM_WEP40;
2391                         break;
2392                 case WEP104_ENCRYPTION:
2393                         enc_algo = CAM_WEP104;
2394                         break;
2395                 case TKIP_ENCRYPTION:
2396                         enc_algo = CAM_TKIP;
2397                         break;
2398                 case AESCCMP_ENCRYPTION:
2399                         enc_algo = CAM_AES;
2400                         break;
2401                 default:
2402                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2403                                  "switch case not process\n");
2404                         enc_algo = CAM_TKIP;
2405                         break;
2406                 }
2407
2408                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2409                         macaddr = cam_const_addr[key_index];
2410                         entry_id = key_index;
2411                 } else {
2412                         if (is_group) {
2413                                 macaddr = cam_const_broad;
2414                                 entry_id = key_index;
2415                         } else {
2416                                 if (mac->opmode == NL80211_IFTYPE_AP ||
2417                                     mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2418                                         entry_id =
2419                                           rtl_cam_get_free_entry(hw, p_macaddr);
2420                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2421                                                 RT_TRACE(rtlpriv, COMP_SEC,
2422                                                          DBG_EMERG,
2423                                                          "Can not find free hw security cam entry\n");
2424                                                 return;
2425                                         }
2426                                 } else {
2427                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2428                                 }
2429                                 key_index = PAIRWISE_KEYIDX;
2430                                 is_pairwise = true;
2431                         }
2432                 }
2433
2434                 if (rtlpriv->sec.key_len[key_index] == 0) {
2435                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2436                                  "delete one entry, entry_id is %d\n",
2437                                  entry_id);
2438                         if (mac->opmode == NL80211_IFTYPE_AP ||
2439                                 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2440                                 rtl_cam_del_entry(hw, p_macaddr);
2441                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2442                 } else {
2443                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2444                                  "add one entry\n");
2445                         if (is_pairwise) {
2446                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2447                                          "set Pairwise key\n");
2448
2449                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2450                                                       entry_id, enc_algo,
2451                                                       CAM_CONFIG_NO_USEDK,
2452                                                       rtlpriv->sec.key_buf[key_index]);
2453                         } else {
2454                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2455                                          "set group key\n");
2456
2457                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2458                                         rtl_cam_add_one_entry(hw,
2459                                                         rtlefuse->dev_addr,
2460                                                         PAIRWISE_KEYIDX,
2461                                                         CAM_PAIRWISE_KEY_POSITION,
2462                                                         enc_algo,
2463                                                         CAM_CONFIG_NO_USEDK,
2464                                                         rtlpriv->sec.key_buf
2465                                                         [entry_id]);
2466                                 }
2467
2468                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2469                                                       entry_id, enc_algo,
2470                                                       CAM_CONFIG_NO_USEDK,
2471                                                       rtlpriv->sec.key_buf[entry_id]);
2472                         }
2473
2474                 }
2475         }
2476 }
2477
2478 static void rtl8188ee_bt_var_init(struct ieee80211_hw *hw)
2479 {
2480         struct rtl_priv *rtlpriv = rtl_priv(hw);
2481
2482         rtlpriv->btcoexist.bt_coexistence =
2483                 rtlpriv->btcoexist.eeprom_bt_coexist;
2484         rtlpriv->btcoexist.bt_ant_num = rtlpriv->btcoexist.eeprom_bt_ant_num;
2485         rtlpriv->btcoexist.bt_coexist_type = rtlpriv->btcoexist.eeprom_bt_type;
2486
2487         if (rtlpriv->btcoexist.reg_bt_iso == 2)
2488                 rtlpriv->btcoexist.bt_ant_isolation =
2489                                 rtlpriv->btcoexist.eeprom_bt_ant_isol;
2490         else
2491                 rtlpriv->btcoexist.bt_ant_isolation =
2492                                 rtlpriv->btcoexist.reg_bt_iso;
2493
2494         rtlpriv->btcoexist.bt_radio_shared_type =
2495                 rtlpriv->btcoexist.eeprom_bt_radio_shared;
2496
2497         if (rtlpriv->btcoexist.bt_coexistence) {
2498                 if (rtlpriv->btcoexist.reg_bt_sco == 1)
2499                         rtlpriv->btcoexist.bt_service = BT_OTHER_ACTION;
2500                 else if (rtlpriv->btcoexist.reg_bt_sco == 2)
2501                         rtlpriv->btcoexist.bt_service = BT_SCO;
2502                 else if (rtlpriv->btcoexist.reg_bt_sco == 4)
2503                         rtlpriv->btcoexist.bt_service = BT_BUSY;
2504                 else if (rtlpriv->btcoexist.reg_bt_sco == 5)
2505                         rtlpriv->btcoexist.bt_service = BT_OTHERBUSY;
2506                 else
2507                         rtlpriv->btcoexist.bt_service = BT_IDLE;
2508
2509                 rtlpriv->btcoexist.bt_edca_ul = 0;
2510                 rtlpriv->btcoexist.bt_edca_dl = 0;
2511                 rtlpriv->btcoexist.bt_rssi_state = 0xff;
2512         }
2513 }
2514
2515 void rtl8188ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2516                                               bool auto_load_fail, u8 *hwinfo)
2517 {
2518         struct rtl_priv *rtlpriv = rtl_priv(hw);
2519         u8 value;
2520
2521         if (!auto_load_fail) {
2522                 rtlpriv->btcoexist.eeprom_bt_coexist =
2523                         ((hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & 0xe0) >> 5);
2524                 if (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] == 0xFF)
2525                         rtlpriv->btcoexist.eeprom_bt_coexist  = 0;
2526                 value = hwinfo[EEPROM_RF_BT_SETTING_88E];
2527                 rtlpriv->btcoexist.eeprom_bt_type = ((value & 0xe) >> 1);
2528                 rtlpriv->btcoexist.eeprom_bt_ant_num = (value & 0x1);
2529                 rtlpriv->btcoexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4);
2530                 rtlpriv->btcoexist.eeprom_bt_radio_shared =
2531                                  ((value & 0x20) >> 5);
2532         } else {
2533                 rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2534                 rtlpriv->btcoexist.eeprom_bt_type = BT_2WIRE;
2535                 rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2;
2536                 rtlpriv->btcoexist.eeprom_bt_ant_isol = 0;
2537                 rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2538         }
2539
2540         rtl8188ee_bt_var_init(hw);
2541 }
2542
2543 void rtl8188ee_bt_reg_init(struct ieee80211_hw *hw)
2544 {
2545         struct rtl_priv *rtlpriv = rtl_priv(hw);
2546
2547         /* 0:Low, 1:High, 2:From Efuse. */
2548         rtlpriv->btcoexist.reg_bt_iso = 2;
2549         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2550         rtlpriv->btcoexist.reg_bt_sco = 3;
2551         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2552         rtlpriv->btcoexist.reg_bt_sco = 0;
2553 }
2554
2555 void rtl8188ee_bt_hw_init(struct ieee80211_hw *hw)
2556 {
2557         struct rtl_priv *rtlpriv = rtl_priv(hw);
2558         struct rtl_phy *rtlphy = &rtlpriv->phy;
2559         u8 u1_tmp;
2560
2561         if (rtlpriv->btcoexist.bt_coexistence &&
2562             ((rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) ||
2563               rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC8)) {
2564                 if (rtlpriv->btcoexist.bt_ant_isolation)
2565                         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2566
2567                 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) &
2568                          BIT_OFFSET_LEN_MASK_32(0, 1);
2569                 u1_tmp = u1_tmp |
2570                          ((rtlpriv->btcoexist.bt_ant_isolation == 1) ?
2571                          0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2572                          ((rtlpriv->btcoexist.bt_service == BT_SCO) ?
2573                          0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2574                 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2575
2576                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2577                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2578                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2579
2580                 /* Config to 1T1R. */
2581                 if (rtlphy->rf_type == RF_1T1R) {
2582                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2583                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2584                         rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2585
2586                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2587                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2588                         rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2589                 }
2590         }
2591 }
2592
2593 void rtl88ee_suspend(struct ieee80211_hw *hw)
2594 {
2595 }
2596
2597 void rtl88ee_resume(struct ieee80211_hw *hw)
2598 {
2599 }