drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2013  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../pci.h"
  28 #include "../ps.h"
  29 #include "reg.h"
  30 #include "def.h"
  31 #include "phy.h"
  32 #include "rf.h"
  33 #include "dm.h"
  34 #include "table.h"
  35
  36 static u32 _rtl88e_phy_rf_serial_read(struct ieee80211_hw *hw,
  37                                       enum radio_path rfpath, u32 offset);
  38 static void _rtl88e_phy_rf_serial_write(struct ieee80211_hw *hw,
  39                                         enum radio_path rfpath, u32 offset,
  40                                         u32 data);
  41 static u32 _rtl88e_phy_calculate_bit_shift(u32 bitmask);
  42 static bool _rtl88e_phy_bb8188e_config_parafile(struct ieee80211_hw *hw);
  43 static bool _rtl88e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
  44 static bool phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
  45                                           u8 configtype);
  46 static bool phy_config_bb_with_pghdr(struct ieee80211_hw *hw,
  47                                      u8 configtype);
  48 static void _rtl88e_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
  49 static bool _rtl88e_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
  50                                              u32 cmdtableidx, u32 cmdtablesz,
  51                                              enum swchnlcmd_id cmdid, u32 para1,
  52                                              u32 para2, u32 msdelay);
  53 static bool _rtl88e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
  54                                              u8 channel, u8 *stage, u8 *step,
  55                                              u32 *delay);
  56
  57 static long _rtl88e_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
  58                                          enum wireless_mode wirelessmode,
  59                                          u8 txpwridx);
  60 static void rtl88ee_phy_set_rf_on(struct ieee80211_hw *hw);
  61 static void rtl88e_phy_set_io(struct ieee80211_hw *hw);
  62
  63 u32 rtl88e_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
  64 {
  65         struct rtl_priv *rtlpriv = rtl_priv(hw);
  66         u32 returnvalue, originalvalue, bitshift;
  67
  68         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  69                  "regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask);
  70         originalvalue = rtl_read_dword(rtlpriv, regaddr);
  71         bitshift = _rtl88e_phy_calculate_bit_shift(bitmask);
  72         returnvalue = (originalvalue & bitmask) >> bitshift;
  73
  74         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  75                  "BBR MASK=0x%x Addr[0x%x]=0x%x\n", bitmask,
  76                  regaddr, originalvalue);
  77
  78         return returnvalue;
  79
  80 }
  81
  82 void rtl88e_phy_set_bb_reg(struct ieee80211_hw *hw,
  83                            u32 regaddr, u32 bitmask, u32 data)
  84 {
  85         struct rtl_priv *rtlpriv = rtl_priv(hw);
  86         u32 originalvalue, bitshift;
  87
  88         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  89                  "regaddr(%#x), bitmask(%#x), data(%#x)\n",
  90                  regaddr, bitmask, data);
  91
  92         if (bitmask != MASKDWORD) {
  93                 originalvalue = rtl_read_dword(rtlpriv, regaddr);
  94                 bitshift = _rtl88e_phy_calculate_bit_shift(bitmask);
  95                 data = ((originalvalue & (~bitmask)) | (data << bitshift));
  96         }
  97
  98         rtl_write_dword(rtlpriv, regaddr, data);
  99
 100         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 101                  "regaddr(%#x), bitmask(%#x), data(%#x)\n",
 102                  regaddr, bitmask, data);
 103 }
 104
 105 u32 rtl88e_phy_query_rf_reg(struct ieee80211_hw *hw,
 106                             enum radio_path rfpath, u32 regaddr, u32 bitmask)
 107 {
 108         struct rtl_priv *rtlpriv = rtl_priv(hw);
 109         u32 original_value, readback_value, bitshift;
 110         unsigned long flags;
 111
 112         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 113                  "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
 114                  regaddr, rfpath, bitmask);
 115
 116         spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
 117
 118
 119         original_value = _rtl88e_phy_rf_serial_read(hw, rfpath, regaddr);
 120         bitshift = _rtl88e_phy_calculate_bit_shift(bitmask);
 121         readback_value = (original_value & bitmask) >> bitshift;
 122
 123         spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
 124
 125         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 126                  "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
 127                   regaddr, rfpath, bitmask, original_value);
 128         return readback_value;
 129 }
 130
 131 void rtl88e_phy_set_rf_reg(struct ieee80211_hw *hw,
 132                            enum radio_path rfpath,
 133                            u32 regaddr, u32 bitmask, u32 data)
 134 {
 135         struct rtl_priv *rtlpriv = rtl_priv(hw);
 136         u32 original_value, bitshift;
 137         unsigned long flags;
 138
 139         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 140                  "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 141                   regaddr, bitmask, data, rfpath);
 142
 143         spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
 144
 145         if (bitmask != RFREG_OFFSET_MASK) {
 146                         original_value = _rtl88e_phy_rf_serial_read(hw,
 147                                                                     rfpath,
 148                                                                     regaddr);
 149                         bitshift = _rtl88e_phy_calculate_bit_shift(bitmask);
 150                         data =
 151                             ((original_value & (~bitmask)) |
 152                              (data << bitshift));
 153                 }
 154
 155         _rtl88e_phy_rf_serial_write(hw, rfpath, regaddr, data);
 156
 157
 158         spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
 159
 160         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 161                  "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 162                  regaddr, bitmask, data, rfpath);
 163 }
 164
 165 static u32 _rtl88e_phy_rf_serial_read(struct ieee80211_hw *hw,
 166                                       enum radio_path rfpath, u32 offset)
 167 {
 168         struct rtl_priv *rtlpriv = rtl_priv(hw);
 169         struct rtl_phy *rtlphy = &rtlpriv->phy;
 170         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
 171         u32 newoffset;
 172         u32 tmplong, tmplong2;
 173         u8 rfpi_enable = 0;
 174         u32 retvalue;
 175
 176         offset &= 0xff;
 177         newoffset = offset;
 178         if (RT_CANNOT_IO(hw)) {
 179                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "return all one\n");
 180                 return 0xFFFFFFFF;
 181         }
 182         tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
 183         if (rfpath == RF90_PATH_A)
 184                 tmplong2 = tmplong;
 185         else
 186                 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
 187         tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
 188             (newoffset << 23) | BLSSIREADEDGE;
 189         rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
 190                       tmplong & (~BLSSIREADEDGE));
 191         mdelay(1);
 192         rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
 193         mdelay(2);
 194         if (rfpath == RF90_PATH_A)
 195                 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
 196                                                 BIT(8));
 197         else if (rfpath == RF90_PATH_B)
 198                 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
 199                                                 BIT(8));
 200         if (rfpi_enable)
 201                 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
 202                                          BLSSIREADBACKDATA);
 203         else
 204                 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
 205                                          BLSSIREADBACKDATA);
 206         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 207                  "RFR-%d Addr[0x%x]=0x%x\n",
 208                  rfpath, pphyreg->rf_rb, retvalue);
 209         return retvalue;
 210 }
 211
 212 static void _rtl88e_phy_rf_serial_write(struct ieee80211_hw *hw,
 213                                         enum radio_path rfpath, u32 offset,
 214                                         u32 data)
 215 {
 216         u32 data_and_addr;
 217         u32 newoffset;
 218         struct rtl_priv *rtlpriv = rtl_priv(hw);
 219         struct rtl_phy *rtlphy = &rtlpriv->phy;
 220         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
 221
 222         if (RT_CANNOT_IO(hw)) {
 223                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "stop\n");
 224                 return;
 225         }
 226         offset &= 0xff;
 227         newoffset = offset;
 228         data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
 229         rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
 230         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 231                  "RFW-%d Addr[0x%x]=0x%x\n",
 232                  rfpath, pphyreg->rf3wire_offset, data_and_addr);
 233 }
 234
 235 static u32 _rtl88e_phy_calculate_bit_shift(u32 bitmask)
 236 {
 237         u32 i;
 238
 239         for (i = 0; i <= 31; i++) {
 240                 if (((bitmask >> i) & 0x1) == 1)
 241                         break;
 242         }
 243         return i;
 244 }
 245
 246 bool rtl88e_phy_mac_config(struct ieee80211_hw *hw)
 247 {
 248         struct rtl_priv *rtlpriv = rtl_priv(hw);
 249         bool rtstatus = _rtl88e_phy_config_mac_with_headerfile(hw);
 250
 251         rtl_write_byte(rtlpriv, 0x04CA, 0x0B);
 252         return rtstatus;
 253 }
 254
 255 bool rtl88e_phy_bb_config(struct ieee80211_hw *hw)
 256 {
 257         bool rtstatus = true;
 258         struct rtl_priv *rtlpriv = rtl_priv(hw);
 259         u16 regval;
 260         u8 b_reg_hwparafile = 1;
 261         u32 tmp;
 262         _rtl88e_phy_init_bb_rf_register_definition(hw);
 263         regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 264         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
 265                        regval | BIT(13) | BIT(0) | BIT(1));
 266
 267         rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
 268         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
 269                        FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
 270                        FEN_BB_GLB_RSTN | FEN_BBRSTB);
 271         tmp = rtl_read_dword(rtlpriv, 0x4c);
 272         rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23));
 273         if (b_reg_hwparafile == 1)
 274                 rtstatus = _rtl88e_phy_bb8188e_config_parafile(hw);
 275         return rtstatus;
 276 }
 277
 278 bool rtl88e_phy_rf_config(struct ieee80211_hw *hw)
 279 {
 280         return rtl88e_phy_rf6052_config(hw);
 281 }
 282
 283 static bool _rtl88e_check_condition(struct ieee80211_hw *hw,
 284                                     const u32  condition)
 285 {
 286         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 287         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 288         u32 _board = rtlefuse->board_type; /*need efuse define*/
 289         u32 _interface = rtlhal->interface;
 290         u32 _platform = 0x08;/*SupportPlatform */
 291         u32 cond = condition;
 292
 293         if (condition == 0xCDCDCDCD)
 294                 return true;
 295
 296         cond = condition & 0xFF;
 297         if ((_board & cond) == 0 && cond != 0x1F)
 298                 return false;
 299
 300         cond = condition & 0xFF00;
 301         cond = cond >> 8;
 302         if ((_interface & cond) == 0 && cond != 0x07)
 303                 return false;
 304
 305         cond = condition & 0xFF0000;
 306         cond = cond >> 16;
 307         if ((_platform & cond) == 0 && cond != 0x0F)
 308                 return false;
 309         return true;
 310 }
 311
 312 static void _rtl8188e_config_rf_reg(struct ieee80211_hw *hw, u32 addr,
 313                                     u32 data, enum radio_path rfpath,
 314                                     u32 regaddr)
 315 {
 316         if (addr == 0xffe) {
 317                 mdelay(50);
 318         } else if (addr == 0xfd) {
 319                 mdelay(5);
 320         } else if (addr == 0xfc) {
 321                 mdelay(1);
 322         } else if (addr == 0xfb) {
 323                 udelay(50);
 324         } else if (addr == 0xfa) {
 325                 udelay(5);
 326         } else if (addr == 0xf9) {
 327                 udelay(1);
 328         } else {
 329                 rtl_set_rfreg(hw, rfpath, regaddr,
 330                               RFREG_OFFSET_MASK,
 331                               data);
 332                 udelay(1);
 333         }
 334 }
 335
 336 static void _rtl8188e_config_rf_radio_a(struct ieee80211_hw *hw,
 337                                         u32 addr, u32 data)
 338 {
 339         u32 content = 0x1000; /*RF Content: radio_a_txt*/
 340         u32 maskforphyset = (u32)(content & 0xE000);
 341
 342         _rtl8188e_config_rf_reg(hw, addr, data, RF90_PATH_A,
 343                 addr | maskforphyset);
 344 }
 345
 346 static void _rtl8188e_config_bb_reg(struct ieee80211_hw *hw,
 347                                     u32 addr, u32 data)
 348 {
 349         if (addr == 0xfe) {
 350                 mdelay(50);
 351         } else if (addr == 0xfd) {
 352                 mdelay(5);
 353         } else if (addr == 0xfc) {
 354                 mdelay(1);
 355         } else if (addr == 0xfb) {
 356                 udelay(50);
 357         } else if (addr == 0xfa) {
 358                 udelay(5);
 359         } else if (addr == 0xf9) {
 360                 udelay(1);
 361         } else {
 362                 rtl_set_bbreg(hw, addr, MASKDWORD, data);
 363                 udelay(1);
 364         }
 365 }
 366
 367 static bool _rtl88e_phy_bb8188e_config_parafile(struct ieee80211_hw *hw)
 368 {
 369         struct rtl_priv *rtlpriv = rtl_priv(hw);
 370         struct rtl_phy *rtlphy = &rtlpriv->phy;
 371         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 372         bool rtstatus;
 373
 374         rtstatus = phy_config_bb_with_headerfile(hw, BASEBAND_CONFIG_PHY_REG);
 375         if (!rtstatus) {
 376                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!");
 377                 return false;
 378         }
 379
 380         if (!rtlefuse->autoload_failflag) {
 381                 rtlphy->pwrgroup_cnt = 0;
 382                 rtstatus =
 383                   phy_config_bb_with_pghdr(hw, BASEBAND_CONFIG_PHY_REG);
 384         }
 385         if (!rtstatus) {
 386                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!");
 387                 return false;
 388         }
 389         rtstatus =
 390           phy_config_bb_with_headerfile(hw, BASEBAND_CONFIG_AGC_TAB);
 391         if (!rtstatus) {
 392                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n");
 393                 return false;
 394         }
 395         rtlphy->cck_high_power =
 396           (bool)(rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, 0x200));
 397
 398         return true;
 399 }
 400
 401 static bool _rtl88e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
 402 {
 403         struct rtl_priv *rtlpriv = rtl_priv(hw);
 404         u32 i;
 405         u32 arraylength;
 406         u32 *ptrarray;
 407
 408         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl8188EMACPHY_Array\n");
 409         arraylength = RTL8188EEMAC_1T_ARRAYLEN;
 410         ptrarray = RTL8188EEMAC_1T_ARRAY;
 411         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 412                  "Img:RTL8188EEMAC_1T_ARRAY LEN %d\n", arraylength);
 413         for (i = 0; i < arraylength; i = i + 2)
 414                 rtl_write_byte(rtlpriv, ptrarray[i], (u8)ptrarray[i + 1]);
 415         return true;
 416 }
 417
 418 #define READ_NEXT_PAIR(v1, v2, i)                       \
 419         do {                                            \
 420                 i += 2; v1 = array_table[i];            \
 421                 v2 = array_table[i+1];                  \
 422         } while (0)
 423
 424 static void handle_branch1(struct ieee80211_hw *hw, u16 arraylen,
 425                            u32 *array_table)
 426 {
 427         u32 v1;
 428         u32 v2;
 429         int i;
 430
 431         for (i = 0; i < arraylen; i = i + 2) {
 432                 v1 = array_table[i];
 433                 v2 = array_table[i+1];
 434                 if (v1 < 0xcdcdcdcd) {
 435                         _rtl8188e_config_bb_reg(hw, v1, v2);
 436                 } else { /*This line is the start line of branch.*/
 437                         /* to protect READ_NEXT_PAIR not overrun */
 438                         if (i >= arraylen - 2)
 439                                 break;
 440
 441                         if (!_rtl88e_check_condition(hw, array_table[i])) {
 442                                 /*Discard the following (offset, data) pairs*/
 443                                 READ_NEXT_PAIR(v1, v2, i);
 444                                 while (v2 != 0xDEAD &&
 445                                        v2 != 0xCDEF &&
 446                                        v2 != 0xCDCD && i < arraylen - 2)
 447                                         READ_NEXT_PAIR(v1, v2, i);
 448                                 i -= 2; /* prevent from for-loop += 2*/
 449                         } else { /* Configure matched pairs and skip
 450                                   * to end of if-else.
 451                                   */
 452                                 READ_NEXT_PAIR(v1, v2, i);
 453                                 while (v2 != 0xDEAD &&
 454                                        v2 != 0xCDEF &&
 455                                        v2 != 0xCDCD && i < arraylen - 2) {
 456                                         _rtl8188e_config_bb_reg(hw, v1, v2);
 457                                         READ_NEXT_PAIR(v1, v2, i);
 458                                 }
 459
 460                                 while (v2 != 0xDEAD && i < arraylen - 2)
 461                                         READ_NEXT_PAIR(v1, v2, i);
 462                         }
 463                 }
 464         }
 465 }
 466
 467 static void handle_branch2(struct ieee80211_hw *hw, u16 arraylen,
 468                            u32 *array_table)
 469 {
 470         struct rtl_priv *rtlpriv = rtl_priv(hw);
 471         u32 v1;
 472         u32 v2;
 473         int i;
 474
 475         for (i = 0; i < arraylen; i = i + 2) {
 476                 v1 = array_table[i];
 477                 v2 = array_table[i+1];
 478                 if (v1 < 0xCDCDCDCD) {
 479                         rtl_set_bbreg(hw, array_table[i], MASKDWORD,
 480                                       array_table[i + 1]);
 481                         udelay(1);
 482                         continue;
 483                 } else { /*This line is the start line of branch.*/
 484                         /* to protect READ_NEXT_PAIR not overrun */
 485                         if (i >= arraylen - 2)
 486                                 break;
 487
 488                         if (!_rtl88e_check_condition(hw, array_table[i])) {
 489                                 /*Discard the following (offset, data) pairs*/
 490                                 READ_NEXT_PAIR(v1, v2, i);
 491                                 while (v2 != 0xDEAD &&
 492                                        v2 != 0xCDEF &&
 493                                        v2 != 0xCDCD && i < arraylen - 2)
 494                                         READ_NEXT_PAIR(v1, v2, i);
 495                                 i -= 2; /* prevent from for-loop += 2*/
 496                         } else { /* Configure matched pairs and skip
 497                                   * to end of if-else.
 498                                   */
 499                                 READ_NEXT_PAIR(v1, v2, i);
 500                                 while (v2 != 0xDEAD &&
 501                                        v2 != 0xCDEF &&
 502                                        v2 != 0xCDCD && i < arraylen - 2) {
 503                                         rtl_set_bbreg(hw, array_table[i],
 504                                                       MASKDWORD,
 505                                                       array_table[i + 1]);
 506                                         udelay(1);
 507                                         READ_NEXT_PAIR(v1, v2, i);
 508                                 }
 509
 510                                 while (v2 != 0xDEAD && i < arraylen - 2)
 511                                         READ_NEXT_PAIR(v1, v2, i);
 512                         }
 513                 }
 514                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 515                          "The agctab_array_table[0] is %x Rtl818EEPHY_REGArray[1] is %x\n",
 516                          array_table[i], array_table[i + 1]);
 517         }
 518 }
 519
 520 static bool phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
 521                                           u8 configtype)
 522 {
 523         u32 *array_table;
 524         u16 arraylen;
 525
 526         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 527                 arraylen = RTL8188EEPHY_REG_1TARRAYLEN;
 528                 array_table = RTL8188EEPHY_REG_1TARRAY;
 529                 handle_branch1(hw, arraylen, array_table);
 530         } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
 531                 arraylen = RTL8188EEAGCTAB_1TARRAYLEN;
 532                 array_table = RTL8188EEAGCTAB_1TARRAY;
 533                 handle_branch2(hw, arraylen, array_table);
 534         }
 535         return true;
 536 }
 537
 538 static void store_pwrindex_rate_offset(struct ieee80211_hw *hw,
 539                                        u32 regaddr, u32 bitmask,
 540                                        u32 data)
 541 {
 542         struct rtl_priv *rtlpriv = rtl_priv(hw);
 543         struct rtl_phy *rtlphy = &rtlpriv->phy;
 544         int count = rtlphy->pwrgroup_cnt;
 545
 546         if (regaddr == RTXAGC_A_RATE18_06) {
 547                 rtlphy->mcs_txpwrlevel_origoffset[count][0] = data;
 548                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 549                          "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
 550                           count,
 551                           rtlphy->mcs_txpwrlevel_origoffset[count][0]);
 552         }
 553         if (regaddr == RTXAGC_A_RATE54_24) {
 554                 rtlphy->mcs_txpwrlevel_origoffset[count][1] = data;
 555                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 556                          "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
 557                           count,
 558                           rtlphy->mcs_txpwrlevel_origoffset[count][1]);
 559         }
 560         if (regaddr == RTXAGC_A_CCK1_MCS32) {
 561                 rtlphy->mcs_txpwrlevel_origoffset[count][6] = data;
 562                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 563                          "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
 564                           count,
 565                           rtlphy->mcs_txpwrlevel_origoffset[count][6]);
 566         }
 567         if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
 568                 rtlphy->mcs_txpwrlevel_origoffset[count][7] = data;
 569                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 570                          "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
 571                           count,
 572                           rtlphy->mcs_txpwrlevel_origoffset[count][7]);
 573         }
 574         if (regaddr == RTXAGC_A_MCS03_MCS00) {
 575                 rtlphy->mcs_txpwrlevel_origoffset[count][2] = data;
 576                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 577                          "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
 578                           count,
 579                           rtlphy->mcs_txpwrlevel_origoffset[count][2]);
 580         }
 581         if (regaddr == RTXAGC_A_MCS07_MCS04) {
 582                 rtlphy->mcs_txpwrlevel_origoffset[count][3] = data;
 583                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 584                          "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
 585                           count,
 586                           rtlphy->mcs_txpwrlevel_origoffset[count][3]);
 587         }
 588         if (regaddr == RTXAGC_A_MCS11_MCS08) {
 589                 rtlphy->mcs_txpwrlevel_origoffset[count][4] = data;
 590                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 591                          "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
 592                           count,
 593                           rtlphy->mcs_txpwrlevel_origoffset[count][4]);
 594         }
 595         if (regaddr == RTXAGC_A_MCS15_MCS12) {
 596                 rtlphy->mcs_txpwrlevel_origoffset[count][5] = data;
 597                 if (get_rf_type(rtlphy) == RF_1T1R) {
 598                         count++;
 599                         rtlphy->pwrgroup_cnt = count;
 600                 }
 601                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 602                          "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
 603                           count,
 604                           rtlphy->mcs_txpwrlevel_origoffset[count][5]);
 605         }
 606         if (regaddr == RTXAGC_B_RATE18_06) {
 607                 rtlphy->mcs_txpwrlevel_origoffset[count][8] = data;
 608                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 609                          "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
 610                           count,
 611                           rtlphy->mcs_txpwrlevel_origoffset[count][8]);
 612         }
 613         if (regaddr == RTXAGC_B_RATE54_24) {
 614                 rtlphy->mcs_txpwrlevel_origoffset[count][9] = data;
 615                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 616                          "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
 617                           count,
 618                           rtlphy->mcs_txpwrlevel_origoffset[count][9]);
 619         }
 620         if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
 621                 rtlphy->mcs_txpwrlevel_origoffset[count][14] = data;
 622                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 623                          "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
 624                           count,
 625                           rtlphy->mcs_txpwrlevel_origoffset[count][14]);
 626         }
 627         if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
 628                 rtlphy->mcs_txpwrlevel_origoffset[count][15] = data;
 629                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 630                          "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
 631                           count,
 632                           rtlphy->mcs_txpwrlevel_origoffset[count][15]);
 633         }
 634         if (regaddr == RTXAGC_B_MCS03_MCS00) {
 635                 rtlphy->mcs_txpwrlevel_origoffset[count][10] = data;
 636                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 637                          "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
 638                           count,
 639                           rtlphy->mcs_txpwrlevel_origoffset[count][10]);
 640         }
 641         if (regaddr == RTXAGC_B_MCS07_MCS04) {
 642                 rtlphy->mcs_txpwrlevel_origoffset[count][11] = data;
 643                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 644                          "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
 645                           count,
 646                           rtlphy->mcs_txpwrlevel_origoffset[count][11]);
 647         }
 648         if (regaddr == RTXAGC_B_MCS11_MCS08) {
 649                 rtlphy->mcs_txpwrlevel_origoffset[count][12] = data;
 650                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 651                          "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
 652                           count,
 653                           rtlphy->mcs_txpwrlevel_origoffset[count][12]);
 654         }
 655         if (regaddr == RTXAGC_B_MCS15_MCS12) {
 656                 rtlphy->mcs_txpwrlevel_origoffset[count][13] = data;
 657                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 658                          "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
 659                           count,
 660                           rtlphy->mcs_txpwrlevel_origoffset[count][13]);
 661                 if (get_rf_type(rtlphy) != RF_1T1R) {
 662                         count++;
 663                         rtlphy->pwrgroup_cnt = count;
 664                 }
 665         }
 666 }
 667
 668 static bool phy_config_bb_with_pghdr(struct ieee80211_hw *hw, u8 configtype)
 669 {
 670         struct rtl_priv *rtlpriv = rtl_priv(hw);
 671         int i;
 672         u32 *phy_reg_page;
 673         u16 phy_reg_page_len;
 674         u32 v1 = 0, v2 = 0, v3 = 0;
 675
 676         phy_reg_page_len = RTL8188EEPHY_REG_ARRAY_PGLEN;
 677         phy_reg_page = RTL8188EEPHY_REG_ARRAY_PG;
 678
 679         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 680                 for (i = 0; i < phy_reg_page_len; i = i + 3) {
 681                         v1 = phy_reg_page[i];
 682                         v2 = phy_reg_page[i+1];
 683                         v3 = phy_reg_page[i+2];
 684
 685                         if (v1 < 0xcdcdcdcd) {
 686                                 if (phy_reg_page[i] == 0xfe)
 687                                         mdelay(50);
 688                                 else if (phy_reg_page[i] == 0xfd)
 689                                         mdelay(5);
 690                                 else if (phy_reg_page[i] == 0xfc)
 691                                         mdelay(1);
 692                                 else if (phy_reg_page[i] == 0xfb)
 693                                         udelay(50);
 694                                 else if (phy_reg_page[i] == 0xfa)
 695                                         udelay(5);
 696                                 else if (phy_reg_page[i] == 0xf9)
 697                                         udelay(1);
 698
 699                                 store_pwrindex_rate_offset(hw, phy_reg_page[i],
 700                                                            phy_reg_page[i + 1],
 701                                                            phy_reg_page[i + 2]);
 702                                 continue;
 703                         } else {
 704                                 if (!_rtl88e_check_condition(hw,
 705                                                              phy_reg_page[i])) {
 706                                         /*don't need the hw_body*/
 707                                     i += 2; /* skip the pair of expression*/
 708                                     /* to protect 'i+1' 'i+2' not overrun */
 709                                     if (i >= phy_reg_page_len - 2)
 710                                         break;
 711
 712                                     v1 = phy_reg_page[i];
 713                                     v2 = phy_reg_page[i+1];
 714                                     v3 = phy_reg_page[i+2];
 715                                     while (v2 != 0xDEAD &&
 716                                            i < phy_reg_page_len - 5) {
 717                                         i += 3;
 718                                         v1 = phy_reg_page[i];
 719                                         v2 = phy_reg_page[i+1];
 720                                         v3 = phy_reg_page[i+2];
 721                                     }
 722                                 }
 723                         }
 724                 }
 725         } else {
 726                 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
 727                          "configtype != BaseBand_Config_PHY_REG\n");
 728         }
 729         return true;
 730 }
 731
 732 #define READ_NEXT_RF_PAIR(v1, v2, i) \
 733 do { \
 734         i += 2; \
 735         v1 = radioa_array_table[i]; \
 736         v2 = radioa_array_table[i+1]; \
 737 } while (0)
 738
 739 static void process_path_a(struct ieee80211_hw *hw,
 740                            u16  radioa_arraylen,
 741                            u32 *radioa_array_table)
 742 {
 743         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 744         u32 v1, v2;
 745         int i;
 746
 747         for (i = 0; i < radioa_arraylen; i = i + 2) {
 748                 v1 = radioa_array_table[i];
 749                 v2 = radioa_array_table[i+1];
 750                 if (v1 < 0xcdcdcdcd) {
 751                         _rtl8188e_config_rf_radio_a(hw, v1, v2);
 752                 } else { /*This line is the start line of branch.*/
 753                         /* to protect READ_NEXT_PAIR not overrun */
 754                         if (i >= radioa_arraylen - 2)
 755                                 break;
 756
 757                         if (!_rtl88e_check_condition(hw, radioa_array_table[i])) {
 758                                 /*Discard the following (offset, data) pairs*/
 759                                 READ_NEXT_RF_PAIR(v1, v2, i);
 760                                 while (v2 != 0xDEAD &&
 761                                        v2 != 0xCDEF &&
 762                                        v2 != 0xCDCD &&
 763                                        i < radioa_arraylen - 2) {
 764                                         READ_NEXT_RF_PAIR(v1, v2, i);
 765                                 }
 766                                 i -= 2; /* prevent from for-loop += 2*/
 767                         } else { /* Configure matched pairs and
 768                                   * skip to end of if-else.
 769                                   */
 770                                 READ_NEXT_RF_PAIR(v1, v2, i);
 771                                 while (v2 != 0xDEAD &&
 772                                        v2 != 0xCDEF &&
 773                                        v2 != 0xCDCD &&
 774                                        i < radioa_arraylen - 2) {
 775                                         _rtl8188e_config_rf_radio_a(hw, v1, v2);
 776                                         READ_NEXT_RF_PAIR(v1, v2, i);
 777                                 }
 778
 779                                 while (v2 != 0xDEAD &&
 780                                        i < radioa_arraylen - 2)
 781                                         READ_NEXT_RF_PAIR(v1, v2, i);
 782                         }
 783                 }
 784         }
 785
 786         if (rtlhal->oem_id == RT_CID_819X_HP)
 787                 _rtl8188e_config_rf_radio_a(hw, 0x52, 0x7E4BD);
 788 }
 789
 790 bool rtl88e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
 791                                           enum radio_path rfpath)
 792 {
 793         struct rtl_priv *rtlpriv = rtl_priv(hw);
 794         bool rtstatus = true;
 795         u32 *radioa_array_table;
 796         u16 radioa_arraylen;
 797
 798         radioa_arraylen = RTL8188EE_RADIOA_1TARRAYLEN;
 799         radioa_array_table = RTL8188EE_RADIOA_1TARRAY;
 800         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 801                  "Radio_A:RTL8188EE_RADIOA_1TARRAY %d\n", radioa_arraylen);
 802         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
 803         rtstatus = true;
 804         switch (rfpath) {
 805         case RF90_PATH_A:
 806                 process_path_a(hw, radioa_arraylen, radioa_array_table);
 807                 break;
 808         case RF90_PATH_B:
 809         case RF90_PATH_C:
 810         case RF90_PATH_D:
 811                 break;
 812         }
 813         return true;
 814 }
 815
 816 void rtl88e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
 817 {
 818         struct rtl_priv *rtlpriv = rtl_priv(hw);
 819         struct rtl_phy *rtlphy = &rtlpriv->phy;
 820
 821         rtlphy->default_initialgain[0] =
 822             (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
 823         rtlphy->default_initialgain[1] =
 824             (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
 825         rtlphy->default_initialgain[2] =
 826             (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
 827         rtlphy->default_initialgain[3] =
 828             (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
 829
 830         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 831                  "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
 832                  rtlphy->default_initialgain[0],
 833                  rtlphy->default_initialgain[1],
 834                  rtlphy->default_initialgain[2],
 835                  rtlphy->default_initialgain[3]);
 836
 837         rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
 838                                               MASKBYTE0);
 839         rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
 840                                               MASKDWORD);
 841
 842         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 843                  "Default framesync (0x%x) = 0x%x\n",
 844                  ROFDM0_RXDETECTOR3, rtlphy->framesync);
 845 }
 846
 847 static void _rtl88e_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
 848 {
 849         struct rtl_priv *rtlpriv = rtl_priv(hw);
 850         struct rtl_phy *rtlphy = &rtlpriv->phy;
 851
 852         rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
 853         rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
 854         rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
 855         rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
 856
 857         rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
 858         rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
 859         rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
 860         rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
 861
 862         rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
 863         rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
 864
 865         rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
 866         rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
 867
 868         rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
 869             RFPGA0_XA_LSSIPARAMETER;
 870         rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
 871             RFPGA0_XB_LSSIPARAMETER;
 872
 873         rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
 874         rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
 875         rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
 876         rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
 877
 878         rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 879         rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 880         rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 881         rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 882
 883         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
 884         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
 885
 886         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
 887         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
 888
 889         rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl =
 890             RFPGA0_XAB_SWITCHCONTROL;
 891         rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl =
 892             RFPGA0_XAB_SWITCHCONTROL;
 893         rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl =
 894             RFPGA0_XCD_SWITCHCONTROL;
 895         rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl =
 896             RFPGA0_XCD_SWITCHCONTROL;
 897
 898         rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
 899         rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
 900         rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
 901         rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
 902
 903         rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
 904         rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
 905         rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
 906         rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
 907
 908         rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
 909         rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
 910         rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE;
 911         rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
 912
 913         rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
 914         rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
 915         rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
 916         rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
 917
 918         rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
 919         rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
 920         rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
 921         rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
 922
 923         rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
 924         rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
 925
 926         rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
 927         rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
 928
 929         rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
 930         rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;
 931 }
 932
 933 void rtl88e_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
 934 {
 935         struct rtl_priv *rtlpriv = rtl_priv(hw);
 936         struct rtl_phy *rtlphy = &rtlpriv->phy;
 937         u8 txpwr_level;
 938         long txpwr_dbm;
 939
 940         txpwr_level = rtlphy->cur_cck_txpwridx;
 941         txpwr_dbm = _rtl88e_phy_txpwr_idx_to_dbm(hw,
 942                                                  WIRELESS_MODE_B, txpwr_level);
 943         txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
 944         if (_rtl88e_phy_txpwr_idx_to_dbm(hw,
 945                                          WIRELESS_MODE_G,
 946                                          txpwr_level) > txpwr_dbm)
 947                 txpwr_dbm =
 948                     _rtl88e_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
 949                                                  txpwr_level);
 950         txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
 951         if (_rtl88e_phy_txpwr_idx_to_dbm(hw,
 952                                          WIRELESS_MODE_N_24G,
 953                                          txpwr_level) > txpwr_dbm)
 954                 txpwr_dbm =
 955                     _rtl88e_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
 956                                                  txpwr_level);
 957         *powerlevel = txpwr_dbm;
 958 }
 959
 960 static void handle_path_a(struct rtl_efuse *rtlefuse, u8 index,
 961                           u8 *cckpowerlevel, u8 *ofdmpowerlevel,
 962                           u8 *bw20powerlevel, u8 *bw40powerlevel)
 963 {
 964         cckpowerlevel[RF90_PATH_A] =
 965             rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
 966                 /*-8~7 */
 967         if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][index] > 0x0f)
 968                 bw20powerlevel[RF90_PATH_A] =
 969                   rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index] -
 970                   (~(rtlefuse->txpwr_ht20diff[RF90_PATH_A][index]) + 1);
 971         else
 972                 bw20powerlevel[RF90_PATH_A] =
 973                   rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index] +
 974                   rtlefuse->txpwr_ht20diff[RF90_PATH_A][index];
 975         if (rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][index] > 0xf)
 976                 ofdmpowerlevel[RF90_PATH_A] =
 977                   rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index] -
 978                   (~(rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][index])+1);
 979         else
 980                 ofdmpowerlevel[RF90_PATH_A] =
 981                 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index] +
 982                   rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][index];
 983         bw40powerlevel[RF90_PATH_A] =
 984           rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
 985 }
 986
 987 static void _rtl88e_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
 988                                       u8 *cckpowerlevel, u8 *ofdmpowerlevel,
 989                                       u8 *bw20powerlevel, u8 *bw40powerlevel)
 990 {
 991         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 992         u8 index = (channel - 1);
 993         u8 rf_path = 0;
 994
 995         for (rf_path = 0; rf_path < 2; rf_path++) {
 996                 if (rf_path == RF90_PATH_A) {
 997                         handle_path_a(rtlefuse, index, cckpowerlevel,
 998                                       ofdmpowerlevel, bw20powerlevel,
 999                                       bw40powerlevel);
1000                 } else if (rf_path == RF90_PATH_B) {
1001                         cckpowerlevel[RF90_PATH_B] =
1002                           rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
1003                         bw20powerlevel[RF90_PATH_B] =
1004                           rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index] +
1005                           rtlefuse->txpwr_ht20diff[RF90_PATH_B][index];
1006                         ofdmpowerlevel[RF90_PATH_B] =
1007                           rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index] +
1008                           rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][index];
1009                         bw40powerlevel[RF90_PATH_B] =
1010                           rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
1011                 }
1012         }
1013
1014 }
1015
1016 static void _rtl88e_ccxpower_index_check(struct ieee80211_hw *hw,
1017                                          u8 channel, u8 *cckpowerlevel,
1018                                          u8 *ofdmpowerlevel, u8 *bw20powerlevel,
1019                                          u8 *bw40powerlevel)
1020 {
1021         struct rtl_priv *rtlpriv = rtl_priv(hw);
1022         struct rtl_phy *rtlphy = &rtlpriv->phy;
1023
1024         rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
1025         rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
1026         rtlphy->cur_bw20_txpwridx = bw20powerlevel[0];
1027         rtlphy->cur_bw40_txpwridx = bw40powerlevel[0];
1028
1029 }
1030
1031 void rtl88e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
1032 {
1033         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1034         u8 cckpowerlevel[MAX_TX_COUNT]  = {0};
1035         u8 ofdmpowerlevel[MAX_TX_COUNT] = {0};
1036         u8 bw20powerlevel[MAX_TX_COUNT] = {0};
1037         u8 bw40powerlevel[MAX_TX_COUNT] = {0};
1038
1039         if (!rtlefuse->txpwr_fromeprom)
1040                 return;
1041         _rtl88e_get_txpower_index(hw, channel,
1042                                   &cckpowerlevel[0], &ofdmpowerlevel[0],
1043                                   &bw20powerlevel[0], &bw40powerlevel[0]);
1044         _rtl88e_ccxpower_index_check(hw, channel,
1045                                      &cckpowerlevel[0], &ofdmpowerlevel[0],
1046                                      &bw20powerlevel[0], &bw40powerlevel[0]);
1047         rtl88e_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
1048         rtl88e_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0],
1049                                            &bw20powerlevel[0],
1050                                            &bw40powerlevel[0], channel);
1051 }
1052
1053 static long _rtl88e_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
1054                                          enum wireless_mode wirelessmode,
1055                                          u8 txpwridx)
1056 {
1057         long offset;
1058         long pwrout_dbm;
1059
1060         switch (wirelessmode) {
1061         case WIRELESS_MODE_B:
1062                 offset = -7;
1063                 break;
1064         case WIRELESS_MODE_G:
1065         case WIRELESS_MODE_N_24G:
1066                 offset = -8;
1067                 break;
1068         default:
1069                 offset = -8;
1070                 break;
1071         }
1072         pwrout_dbm = txpwridx / 2 + offset;
1073         return pwrout_dbm;
1074 }
1075
1076 void rtl88e_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
1077 {
1078         struct rtl_priv *rtlpriv = rtl_priv(hw);
1079         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1080         enum io_type iotype;
1081
1082         if (!is_hal_stop(rtlhal)) {
1083                 switch (operation) {
1084                 case SCAN_OPT_BACKUP_BAND0:
1085                         iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
1086                         rtlpriv->cfg->ops->set_hw_reg(hw,
1087                                                       HW_VAR_IO_CMD,
1088                                                       (u8 *)&iotype);
1089
1090                         break;
1091                 case SCAN_OPT_RESTORE:
1092                         iotype = IO_CMD_RESUME_DM_BY_SCAN;
1093                         rtlpriv->cfg->ops->set_hw_reg(hw,
1094                                                       HW_VAR_IO_CMD,
1095                                                       (u8 *)&iotype);
1096                         break;
1097                 default:
1098                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1099                                  "Unknown Scan Backup operation.\n");
1100                         break;
1101                 }
1102         }
1103 }
1104
1105 void rtl88e_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
1106 {
1107         struct rtl_priv *rtlpriv = rtl_priv(hw);
1108         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1109         struct rtl_phy *rtlphy = &rtlpriv->phy;
1110         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1111         u8 reg_bw_opmode;
1112         u8 reg_prsr_rsc;
1113
1114         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1115                  "Switch to %s bandwidth\n",
1116                   rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
1117                   "20MHz" : "40MHz");
1118
1119         if (is_hal_stop(rtlhal)) {
1120                 rtlphy->set_bwmode_inprogress = false;
1121                 return;
1122         }
1123
1124         reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
1125         reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
1126
1127         switch (rtlphy->current_chan_bw) {
1128         case HT_CHANNEL_WIDTH_20:
1129                 reg_bw_opmode |= BW_OPMODE_20MHZ;
1130                 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1131                 break;
1132         case HT_CHANNEL_WIDTH_20_40:
1133                 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
1134                 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1135                 reg_prsr_rsc =
1136                     (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
1137                 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
1138                 break;
1139         default:
1140                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1141                          "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
1142                 break;
1143         }
1144
1145         switch (rtlphy->current_chan_bw) {
1146         case HT_CHANNEL_WIDTH_20:
1147                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
1148                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
1149         /*      rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);*/
1150                 break;
1151         case HT_CHANNEL_WIDTH_20_40:
1152                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
1153                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
1154
1155                 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
1156                               (mac->cur_40_prime_sc >> 1));
1157                 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
1158                 /*rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);*/
1159
1160                 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
1161                               (mac->cur_40_prime_sc ==
1162                                HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1163                 break;
1164         default:
1165                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1166                          "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
1167                 break;
1168         }
1169         rtl88e_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1170         rtlphy->set_bwmode_inprogress = false;
1171         RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, "\n");
1172 }
1173
1174 void rtl88e_phy_set_bw_mode(struct ieee80211_hw *hw,
1175                             enum nl80211_channel_type ch_type)
1176 {
1177         struct rtl_priv *rtlpriv = rtl_priv(hw);
1178         struct rtl_phy *rtlphy = &rtlpriv->phy;
1179         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1180         u8 tmp_bw = rtlphy->current_chan_bw;
1181
1182         if (rtlphy->set_bwmode_inprogress)
1183                 return;
1184         rtlphy->set_bwmode_inprogress = true;
1185         if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1186                 rtl88e_phy_set_bw_mode_callback(hw);
1187         } else {
1188                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1189                          "false driver sleep or unload\n");
1190                 rtlphy->set_bwmode_inprogress = false;
1191                 rtlphy->current_chan_bw = tmp_bw;
1192         }
1193 }
1194
1195 void rtl88e_phy_sw_chnl_callback(struct ieee80211_hw *hw)
1196 {
1197         struct rtl_priv *rtlpriv = rtl_priv(hw);
1198         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1199         struct rtl_phy *rtlphy = &rtlpriv->phy;
1200         u32 delay;
1201
1202         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1203                  "switch to channel%d\n", rtlphy->current_channel);
1204         if (is_hal_stop(rtlhal))
1205                 return;
1206         do {
1207                 if (!rtlphy->sw_chnl_inprogress)
1208                         break;
1209                 if (!_rtl88e_phy_sw_chnl_step_by_step
1210                     (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
1211                      &rtlphy->sw_chnl_step, &delay)) {
1212                         if (delay > 0)
1213                                 mdelay(delay);
1214                         else
1215                                 continue;
1216                 } else {
1217                         rtlphy->sw_chnl_inprogress = false;
1218                 }
1219                 break;
1220         } while (true);
1221         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
1222 }
1223
1224 u8 rtl88e_phy_sw_chnl(struct ieee80211_hw *hw)
1225 {
1226         struct rtl_priv *rtlpriv = rtl_priv(hw);
1227         struct rtl_phy *rtlphy = &rtlpriv->phy;
1228         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1229
1230         if (rtlphy->sw_chnl_inprogress)
1231                 return 0;
1232         if (rtlphy->set_bwmode_inprogress)
1233                 return 0;
1234         RT_ASSERT((rtlphy->current_channel <= 14),
1235                   "WIRELESS_MODE_G but channel>14");
1236         rtlphy->sw_chnl_inprogress = true;
1237         rtlphy->sw_chnl_stage = 0;
1238         rtlphy->sw_chnl_step = 0;
1239         if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1240                 rtl88e_phy_sw_chnl_callback(hw);
1241                 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1242                          "sw_chnl_inprogress false schdule workitem current channel %d\n",
1243                          rtlphy->current_channel);
1244                 rtlphy->sw_chnl_inprogress = false;
1245         } else {
1246                 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1247                          "sw_chnl_inprogress false driver sleep or unload\n");
1248                 rtlphy->sw_chnl_inprogress = false;
1249         }
1250         return 1;
1251 }
1252
1253 static bool _rtl88e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
1254                                              u8 channel, u8 *stage, u8 *step,
1255                                              u32 *delay)
1256 {
1257         struct rtl_priv *rtlpriv = rtl_priv(hw);
1258         struct rtl_phy *rtlphy = &rtlpriv->phy;
1259         struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
1260         u32 precommoncmdcnt;
1261         struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
1262         u32 postcommoncmdcnt;
1263         struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
1264         u32 rfdependcmdcnt;
1265         struct swchnlcmd *currentcmd = NULL;
1266         u8 rfpath;
1267         u8 num_total_rfpath = rtlphy->num_total_rfpath;
1268
1269         precommoncmdcnt = 0;
1270         _rtl88e_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1271                                          MAX_PRECMD_CNT,
1272                                          CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
1273         _rtl88e_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1274                                          MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
1275
1276         postcommoncmdcnt = 0;
1277
1278         _rtl88e_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
1279                                          MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
1280
1281         rfdependcmdcnt = 0;
1282
1283         RT_ASSERT((channel >= 1 && channel <= 14),
1284                   "illegal channel for Zebra: %d\n", channel);
1285
1286         _rtl88e_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1287                                          MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
1288                                          RF_CHNLBW, channel, 10);
1289
1290         _rtl88e_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1291                                          MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0,
1292                                          0);
1293
1294         do {
1295                 switch (*stage) {
1296                 case 0:
1297                         currentcmd = &precommoncmd[*step];
1298                         break;
1299                 case 1:
1300                         currentcmd = &rfdependcmd[*step];
1301                         break;
1302                 case 2:
1303                         currentcmd = &postcommoncmd[*step];
1304                         break;
1305                 default:
1306                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1307                                  "Invalid 'stage' = %d, Check it!\n", *stage);
1308                         return true;
1309                 }
1310
1311                 if (currentcmd->cmdid == CMDID_END) {
1312                         if ((*stage) == 2)
1313                                 return true;
1314                         (*stage)++;
1315                         (*step) = 0;
1316                         continue;
1317                 }
1318
1319                 switch (currentcmd->cmdid) {
1320                 case CMDID_SET_TXPOWEROWER_LEVEL:
1321                         rtl88e_phy_set_txpower_level(hw, channel);
1322                         break;
1323                 case CMDID_WRITEPORT_ULONG:
1324                         rtl_write_dword(rtlpriv, currentcmd->para1,
1325                                         currentcmd->para2);
1326                         break;
1327                 case CMDID_WRITEPORT_USHORT:
1328                         rtl_write_word(rtlpriv, currentcmd->para1,
1329                                        (u16)currentcmd->para2);
1330                         break;
1331                 case CMDID_WRITEPORT_UCHAR:
1332                         rtl_write_byte(rtlpriv, currentcmd->para1,
1333                                        (u8)currentcmd->para2);
1334                         break;
1335                 case CMDID_RF_WRITEREG:
1336                         for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
1337                                 rtlphy->rfreg_chnlval[rfpath] =
1338                                     ((rtlphy->rfreg_chnlval[rfpath] &
1339                                       0xfffffc00) | currentcmd->para2);
1340
1341                                 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1342                                               currentcmd->para1,
1343                                               RFREG_OFFSET_MASK,
1344                                               rtlphy->rfreg_chnlval[rfpath]);
1345                         }
1346                         break;
1347                 default:
1348                         RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1349                                  "switch case not process\n");
1350                         break;
1351                 }
1352
1353                 break;
1354         } while (true);
1355
1356         (*delay) = currentcmd->msdelay;
1357         (*step)++;
1358         return false;
1359 }
1360
1361 static bool _rtl88e_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
1362                                              u32 cmdtableidx, u32 cmdtablesz,
1363                                              enum swchnlcmd_id cmdid,
1364                                              u32 para1, u32 para2, u32 msdelay)
1365 {
1366         struct swchnlcmd *pcmd;
1367
1368         if (cmdtable == NULL) {
1369                 RT_ASSERT(false, "cmdtable cannot be NULL.\n");
1370                 return false;
1371         }
1372
1373         if (cmdtableidx >= cmdtablesz)
1374                 return false;
1375
1376         pcmd = cmdtable + cmdtableidx;
1377         pcmd->cmdid = cmdid;
1378         pcmd->para1 = para1;
1379         pcmd->para2 = para2;
1380         pcmd->msdelay = msdelay;
1381         return true;
1382 }
1383
1384 static u8 _rtl88e_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
1385 {
1386         u32 reg_eac, reg_e94, reg_e9c, reg_ea4;
1387         u8 result = 0x00;
1388
1389         rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1c);
1390         rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x30008c1c);
1391         rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x8214032a);
1392         rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160000);
1393
1394         rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1395         rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1396         rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1397
1398         mdelay(IQK_DELAY_TIME);
1399
1400         reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1401         reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1402         reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1403         reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1404
1405         if (!(reg_eac & BIT(28)) &&
1406             (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1407             (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1408                 result |= 0x01;
1409         return result;
1410 }
1411
1412 static u8 _rtl88e_phy_path_b_iqk(struct ieee80211_hw *hw)
1413 {
1414         u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
1415         u8 result = 0x00;
1416
1417         rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
1418         rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
1419         mdelay(IQK_DELAY_TIME);
1420         reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1421         reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1422         reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1423         reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1424         reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1425
1426         if (!(reg_eac & BIT(31)) &&
1427             (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
1428             (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
1429                 result |= 0x01;
1430         else
1431                 return result;
1432         if (!(reg_eac & BIT(30)) &&
1433             (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
1434             (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
1435                 result |= 0x02;
1436         return result;
1437 }
1438
1439 static u8 _rtl88e_phy_path_a_rx_iqk(struct ieee80211_hw *hw, bool config_pathb)
1440 {
1441         u32 reg_eac, reg_e94, reg_e9c, reg_ea4, u32temp;
1442         u8 result = 0x00;
1443
1444         /*Get TXIMR Setting*/
1445         /*Modify RX IQK mode table*/
1446         rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1447         rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
1448         rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
1449         rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
1450         rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b);
1451         rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1452
1453         /*IQK Setting*/
1454         rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
1455         rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x81004800);
1456
1457         /*path a IQK setting*/
1458         rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x10008c1c);
1459         rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x30008c1c);
1460         rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160804);
1461         rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160000);
1462
1463         /*LO calibration Setting*/
1464         rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);
1465         /*one shot,path A LOK & iqk*/
1466         rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1467         rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1468
1469         mdelay(IQK_DELAY_TIME);
1470
1471         reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
1472         reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);
1473         reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);
1474
1475
1476         if (!(reg_eac & BIT(28)) &&
1477             (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1478             (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1479                 result |= 0x01;
1480         else
1481                 return result;
1482
1483         u32temp = 0x80007C00 | (reg_e94&0x3FF0000) |
1484                   ((reg_e9c&0x3FF0000) >> 16);
1485         rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp);
1486         /*RX IQK*/
1487         /*Modify RX IQK mode table*/
1488         rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1489         rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
1490         rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
1491         rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
1492         rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa);
1493         rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1494
1495         /*IQK Setting*/
1496         rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1497
1498         /*path a IQK setting*/
1499         rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x30008c1c);
1500         rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x10008c1c);
1501         rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c05);
1502         rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c05);
1503
1504         /*LO calibration Setting*/
1505         rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);
1506         /*one shot,path A LOK & iqk*/
1507         rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1508         rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1509
1510         mdelay(IQK_DELAY_TIME);
1511
1512         reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
1513         reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);
1514         reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);
1515         reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);
1516
1517         if (!(reg_eac & BIT(27)) &&
1518             (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
1519             (((reg_eac & 0x03FF0000) >> 16) != 0x36))
1520                 result |= 0x02;
1521         return result;
1522 }
1523
1524 static void _rtl88e_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
1525                                                bool iqk_ok, long result[][8],
1526                                                u8 final_candidate, bool btxonly)
1527 {
1528         u32 oldval_0, x, tx0_a, reg;
1529         long y, tx0_c;
1530
1531         if (final_candidate == 0xFF) {
1532                 return;
1533         } else if (iqk_ok) {
1534                 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
1535                                           MASKDWORD) >> 22) & 0x3FF;
1536                 x = result[final_candidate][0];
1537                 if ((x & 0x00000200) != 0)
1538                         x = x | 0xFFFFFC00;
1539                 tx0_a = (x * oldval_0) >> 8;
1540                 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
1541                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
1542                               ((x * oldval_0 >> 7) & 0x1));
1543                 y = result[final_candidate][1];
1544                 if ((y & 0x00000200) != 0)
1545                         y = y | 0xFFFFFC00;
1546                 tx0_c = (y * oldval_0) >> 8;
1547                 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
1548                               ((tx0_c & 0x3C0) >> 6));
1549                 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
1550                               (tx0_c & 0x3F));
1551                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
1552                               ((y * oldval_0 >> 7) & 0x1));
1553                 if (btxonly)
1554                         return;
1555                 reg = result[final_candidate][2];
1556                 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
1557                 reg = result[final_candidate][3] & 0x3F;
1558                 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
1559                 reg = (result[final_candidate][3] >> 6) & 0xF;
1560                 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
1561         }
1562 }
1563
1564 static void _rtl88e_phy_save_adda_registers(struct ieee80211_hw *hw,
1565                                             u32 *addareg, u32 *addabackup,
1566                                             u32 registernum)
1567 {
1568         u32 i;
1569
1570         for (i = 0; i < registernum; i++)
1571                 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
1572 }
1573
1574 static void _rtl88e_phy_save_mac_registers(struct ieee80211_hw *hw,
1575                                            u32 *macreg, u32 *macbackup)
1576 {
1577         struct rtl_priv *rtlpriv = rtl_priv(hw);
1578         u32 i;
1579
1580         for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1581                 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1582         macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1583 }
1584
1585 static void _rtl88e_phy_reload_adda_registers(struct ieee80211_hw *hw,
1586                                               u32 *addareg, u32 *addabackup,
1587                                               u32 regiesternum)
1588 {
1589         u32 i;
1590
1591         for (i = 0; i < regiesternum; i++)
1592                 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
1593 }
1594
1595 static void _rtl88e_phy_reload_mac_registers(struct ieee80211_hw *hw,
1596                                              u32 *macreg, u32 *macbackup)
1597 {
1598         struct rtl_priv *rtlpriv = rtl_priv(hw);
1599         u32 i;
1600
1601         for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1602                 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1603         rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
1604 }
1605
1606 static void _rtl88e_phy_path_adda_on(struct ieee80211_hw *hw,
1607                                      u32 *addareg, bool is_patha_on, bool is2t)
1608 {
1609         u32 pathon;
1610         u32 i;
1611
1612         pathon = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
1613         if (false == is2t) {
1614                 pathon = 0x0bdb25a0;
1615                 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
1616         } else {
1617                 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);
1618         }
1619
1620         for (i = 1; i < IQK_ADDA_REG_NUM; i++)
1621                 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon);
1622 }
1623
1624 static void _rtl88e_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1625                                                 u32 *macreg, u32 *macbackup)
1626 {
1627         struct rtl_priv *rtlpriv = rtl_priv(hw);
1628         u32 i = 0;
1629
1630         rtl_write_byte(rtlpriv, macreg[i], 0x3F);
1631
1632         for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1633                 rtl_write_byte(rtlpriv, macreg[i],
1634                                (u8) (macbackup[i] & (~BIT(3))));
1635         rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1636 }
1637
1638 static void _rtl88e_phy_path_a_standby(struct ieee80211_hw *hw)
1639 {
1640         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1641         rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1642         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1643 }
1644
1645 static void _rtl88e_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
1646 {
1647         u32 mode;
1648
1649         mode = pi_mode ? 0x01000100 : 0x01000000;
1650         rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1651         rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1652 }
1653
1654 static bool _rtl88e_phy_simularity_compare(struct ieee80211_hw *hw,
1655                                            long result[][8], u8 c1, u8 c2)
1656 {
1657         u32 i, j, diff, simularity_bitmap, bound;
1658         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1659
1660         u8 final_candidate[2] = { 0xFF, 0xFF };
1661         bool bresult = true, is2t = IS_92C_SERIAL(rtlhal->version);
1662
1663         if (is2t)
1664                 bound = 8;
1665         else
1666                 bound = 4;
1667
1668         simularity_bitmap = 0;
1669
1670         for (i = 0; i < bound; i++) {
1671                 diff = (result[c1][i] > result[c2][i]) ?
1672                     (result[c1][i] - result[c2][i]) :
1673                     (result[c2][i] - result[c1][i]);
1674
1675                 if (diff > MAX_TOLERANCE) {
1676                         if ((i == 2 || i == 6) && !simularity_bitmap) {
1677                                 if (result[c1][i] + result[c1][i + 1] == 0)
1678                                         final_candidate[(i / 4)] = c2;
1679                                 else if (result[c2][i] + result[c2][i + 1] == 0)
1680                                         final_candidate[(i / 4)] = c1;
1681                                 else
1682                                         simularity_bitmap = simularity_bitmap |
1683                                             (1 << i);
1684                         } else
1685                                 simularity_bitmap =
1686                                     simularity_bitmap | (1 << i);
1687                 }
1688         }
1689
1690         if (simularity_bitmap == 0) {
1691                 for (i = 0; i < (bound / 4); i++) {
1692                         if (final_candidate[i] != 0xFF) {
1693                                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1694                                         result[3][j] =
1695                                             result[final_candidate[i]][j];
1696                                 bresult = false;
1697                         }
1698                 }
1699                 return bresult;
1700         } else if (!(simularity_bitmap & 0x0F)) {
1701                 for (i = 0; i < 4; i++)
1702                         result[3][i] = result[c1][i];
1703                 return false;
1704         } else if (!(simularity_bitmap & 0xF0) && is2t) {
1705                 for (i = 4; i < 8; i++)
1706                         result[3][i] = result[c1][i];
1707                 return false;
1708         } else {
1709                 return false;
1710         }
1711
1712 }
1713
1714 static void _rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw,
1715                                      long result[][8], u8 t, bool is2t)
1716 {
1717         struct rtl_priv *rtlpriv = rtl_priv(hw);
1718         struct rtl_phy *rtlphy = &rtlpriv->phy;
1719         u32 i;
1720         u8 patha_ok, pathb_ok;
1721         u32 adda_reg[IQK_ADDA_REG_NUM] = {
1722                 0x85c, 0xe6c, 0xe70, 0xe74,
1723                 0xe78, 0xe7c, 0xe80, 0xe84,
1724                 0xe88, 0xe8c, 0xed0, 0xed4,
1725                 0xed8, 0xedc, 0xee0, 0xeec
1726         };
1727         u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1728                 0x522, 0x550, 0x551, 0x040
1729         };
1730         u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
1731                 ROFDM0_TRXPATHENABLE, ROFDM0_TRMUXPAR,
1732                 RFPGA0_XCD_RFINTERFACESW, 0xb68, 0xb6c,
1733                 0x870, 0x860, 0x864, 0x800
1734         };
1735         const u32 retrycount = 2;
1736
1737         if (t == 0) {
1738                 _rtl88e_phy_save_adda_registers(hw, adda_reg,
1739                                                 rtlphy->adda_backup, 16);
1740                 _rtl88e_phy_save_mac_registers(hw, iqk_mac_reg,
1741                                                rtlphy->iqk_mac_backup);
1742                 _rtl88e_phy_save_adda_registers(hw, iqk_bb_reg,
1743                                                 rtlphy->iqk_bb_backup,
1744                                                 IQK_BB_REG_NUM);
1745         }
1746         _rtl88e_phy_path_adda_on(hw, adda_reg, true, is2t);
1747         if (t == 0) {
1748                 rtlphy->rfpi_enable =
1749                   (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, BIT(8));
1750         }
1751
1752         if (!rtlphy->rfpi_enable)
1753                 _rtl88e_phy_pi_mode_switch(hw, true);
1754         /*BB Setting*/
1755         rtl_set_bbreg(hw, 0x800, BIT(24), 0x00);
1756         rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
1757         rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
1758         rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
1759
1760         rtl_set_bbreg(hw, 0x870, BIT(10), 0x01);
1761         rtl_set_bbreg(hw, 0x870, BIT(26), 0x01);
1762         rtl_set_bbreg(hw, 0x860, BIT(10), 0x00);
1763         rtl_set_bbreg(hw, 0x864, BIT(10), 0x00);
1764
1765         if (is2t) {
1766                 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1767                 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
1768         }
1769         _rtl88e_phy_mac_setting_calibration(hw, iqk_mac_reg,
1770                                             rtlphy->iqk_mac_backup);
1771         rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
1772         if (is2t)
1773                 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
1774
1775         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1776         rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1777         rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x81004800);
1778         for (i = 0; i < retrycount; i++) {
1779                 patha_ok = _rtl88e_phy_path_a_iqk(hw, is2t);
1780                 if (patha_ok == 0x01) {
1781                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1782                                  "Path A Tx IQK Success!!\n");
1783                         result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1784                                         0x3FF0000) >> 16;
1785                         result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1786                                         0x3FF0000) >> 16;
1787                         break;
1788                 }
1789         }
1790
1791         for (i = 0; i < retrycount; i++) {
1792                 patha_ok = _rtl88e_phy_path_a_rx_iqk(hw, is2t);
1793                 if (patha_ok == 0x03) {
1794                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1795                                  "Path A Rx IQK Success!!\n");
1796                         result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1797                                         0x3FF0000) >> 16;
1798                         result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1799                                         0x3FF0000) >> 16;
1800                         break;
1801                 } else {
1802                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1803                                  "Path a RX iqk fail!!!\n");
1804                 }
1805         }
1806
1807         if (0 == patha_ok)
1808                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1809                          "Path A IQK Success!!\n");
1810         if (is2t) {
1811                 _rtl88e_phy_path_a_standby(hw);
1812                 _rtl88e_phy_path_adda_on(hw, adda_reg, false, is2t);
1813                 for (i = 0; i < retrycount; i++) {
1814                         pathb_ok = _rtl88e_phy_path_b_iqk(hw);
1815                         if (pathb_ok == 0x03) {
1816                                 result[t][4] = (rtl_get_bbreg(hw,
1817                                                               0xeb4,
1818                                                               MASKDWORD) &
1819                                                 0x3FF0000) >> 16;
1820                                 result[t][5] =
1821                                     (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1822                                      0x3FF0000) >> 16;
1823                                 result[t][6] =
1824                                     (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
1825                                      0x3FF0000) >> 16;
1826                                 result[t][7] =
1827                                     (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
1828                                      0x3FF0000) >> 16;
1829                                 break;
1830                         } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1831                                 result[t][4] = (rtl_get_bbreg(hw,
1832                                                               0xeb4,
1833                                                               MASKDWORD) &
1834                                                 0x3FF0000) >> 16;
1835                         }
1836                         result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1837                                         0x3FF0000) >> 16;
1838                 }
1839         }
1840
1841         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1842
1843         if (t != 0) {
1844                 if (!rtlphy->rfpi_enable)
1845                         _rtl88e_phy_pi_mode_switch(hw, false);
1846                 _rtl88e_phy_reload_adda_registers(hw, adda_reg,
1847                                                   rtlphy->adda_backup, 16);
1848                 _rtl88e_phy_reload_mac_registers(hw, iqk_mac_reg,
1849                                                  rtlphy->iqk_mac_backup);
1850                 _rtl88e_phy_reload_adda_registers(hw, iqk_bb_reg,
1851                                                   rtlphy->iqk_bb_backup,
1852                                                   IQK_BB_REG_NUM);
1853
1854                 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
1855                 if (is2t)
1856                         rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
1857                 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00);
1858                 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00);
1859         }
1860         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "88ee IQK Finish!!\n");
1861 }
1862
1863 static void _rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
1864 {
1865         u8 tmpreg;
1866         u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
1867         struct rtl_priv *rtlpriv = rtl_priv(hw);
1868
1869         tmpreg = rtl_read_byte(rtlpriv, 0xd03);
1870
1871         if ((tmpreg & 0x70) != 0)
1872                 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
1873         else
1874                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1875
1876         if ((tmpreg & 0x70) != 0) {
1877                 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
1878
1879                 if (is2t)
1880                         rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
1881                                                   MASK12BITS);
1882
1883                 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
1884                               (rf_a_mode & 0x8FFFF) | 0x10000);
1885
1886                 if (is2t)
1887                         rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
1888                                       (rf_b_mode & 0x8FFFF) | 0x10000);
1889         }
1890         lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
1891
1892         rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
1893
1894         mdelay(100);
1895
1896         if ((tmpreg & 0x70) != 0) {
1897                 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
1898                 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
1899
1900                 if (is2t)
1901                         rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
1902                                       rf_b_mode);
1903         } else {
1904                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1905         }
1906 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1907
1908 }
1909
1910 static void _rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw,
1911                                           bool bmain, bool is2t)
1912 {
1913         struct rtl_priv *rtlpriv = rtl_priv(hw);
1914         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1915         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1916         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1917
1918         if (is_hal_stop(rtlhal)) {
1919                 u8 u1btmp;
1920                 u1btmp = rtl_read_byte(rtlpriv, REG_LEDCFG0);
1921                 rtl_write_byte(rtlpriv, REG_LEDCFG0, u1btmp | BIT(7));
1922                 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1923         }
1924         if (is2t) {
1925                 if (bmain)
1926                         rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1927                                       BIT(5) | BIT(6), 0x1);
1928                 else
1929                         rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1930                                       BIT(5) | BIT(6), 0x2);
1931         } else {
1932                 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0);
1933                 rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201);
1934
1935                 /* We use the RF definition of MAIN and AUX,
1936                  * left antenna and right antenna repectively.
1937                  * Default output at AUX.
1938                  */
1939                 if (bmain) {
1940                         rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
1941                                       BIT(14) | BIT(13) | BIT(12), 0);
1942                         rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1943                                       BIT(5) | BIT(4) | BIT(3), 0);
1944                         if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1945                                 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 0);
1946                 } else {
1947                         rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
1948                                       BIT(14) | BIT(13) | BIT(12), 1);
1949                         rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1950                                       BIT(5) | BIT(4) | BIT(3), 1);
1951                         if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1952                                 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 1);
1953                 }
1954         }
1955 }
1956
1957 #undef IQK_ADDA_REG_NUM
1958 #undef IQK_DELAY_TIME
1959
1960 void rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
1961 {
1962         struct rtl_priv *rtlpriv = rtl_priv(hw);
1963         struct rtl_phy *rtlphy = &rtlpriv->phy;
1964         long result[4][8];
1965         u8 i, final_candidate;
1966         bool b_patha_ok, b_pathb_ok;
1967         long reg_e94, reg_e9c, reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4,
1968             reg_ecc, reg_tmp = 0;
1969         bool is12simular, is13simular, is23simular;
1970         u32 iqk_bb_reg[9] = {
1971                 ROFDM0_XARXIQIMBALANCE,
1972                 ROFDM0_XBRXIQIMBALANCE,
1973                 ROFDM0_ECCATHRESHOLD,
1974                 ROFDM0_AGCRSSITABLE,
1975                 ROFDM0_XATXIQIMBALANCE,
1976                 ROFDM0_XBTXIQIMBALANCE,
1977                 ROFDM0_XCTXAFE,
1978                 ROFDM0_XDTXAFE,
1979                 ROFDM0_RXIQEXTANTA
1980         };
1981
1982         if (b_recovery) {
1983                 _rtl88e_phy_reload_adda_registers(hw,
1984                                                   iqk_bb_reg,
1985                                                   rtlphy->iqk_bb_backup, 9);
1986                 return;
1987         }
1988
1989         for (i = 0; i < 8; i++) {
1990                 result[0][i] = 0;
1991                 result[1][i] = 0;
1992                 result[2][i] = 0;
1993                 result[3][i] = 0;
1994         }
1995         final_candidate = 0xff;
1996         b_patha_ok = false;
1997         b_pathb_ok = false;
1998         is12simular = false;
1999         is23simular = false;
2000         is13simular = false;
2001         for (i = 0; i < 3; i++) {
2002                 if (get_rf_type(rtlphy) == RF_2T2R)
2003                         _rtl88e_phy_iq_calibrate(hw, result, i, true);
2004                 else
2005                         _rtl88e_phy_iq_calibrate(hw, result, i, false);
2006                 if (i == 1) {
2007                         is12simular =
2008                           _rtl88e_phy_simularity_compare(hw, result, 0, 1);
2009                         if (is12simular) {
2010                                 final_candidate = 0;
2011                                 break;
2012                         }
2013                 }
2014                 if (i == 2) {
2015                         is13simular =
2016                           _rtl88e_phy_simularity_compare(hw, result, 0, 2);
2017                         if (is13simular) {
2018                                 final_candidate = 0;
2019                                 break;
2020                         }
2021                         is23simular =
2022                            _rtl88e_phy_simularity_compare(hw, result, 1, 2);
2023                         if (is23simular) {
2024                                 final_candidate = 1;
2025                         } else {
2026                                 for (i = 0; i < 8; i++)
2027                                         reg_tmp += result[3][i];
2028
2029                                 if (reg_tmp != 0)
2030                                         final_candidate = 3;
2031                                 else
2032                                         final_candidate = 0xFF;
2033                         }
2034                 }
2035         }
2036         for (i = 0; i < 4; i++) {
2037                 reg_e94 = result[i][0];
2038                 reg_e9c = result[i][1];
2039                 reg_ea4 = result[i][2];
2040                 reg_eac = result[i][3];
2041                 reg_eb4 = result[i][4];
2042                 reg_ebc = result[i][5];
2043                 reg_ec4 = result[i][6];
2044                 reg_ecc = result[i][7];
2045         }
2046         if (final_candidate != 0xff) {
2047                 reg_e94 = result[final_candidate][0];
2048                 reg_e9c = result[final_candidate][1];
2049                 reg_ea4 = result[final_candidate][2];
2050                 reg_eac = result[final_candidate][3];
2051                 reg_eb4 = result[final_candidate][4];
2052                 reg_ebc = result[final_candidate][5];
2053                 reg_ec4 = result[final_candidate][6];
2054                 reg_ecc = result[final_candidate][7];
2055                 rtlphy->reg_eb4 = reg_eb4;
2056                 rtlphy->reg_ebc = reg_ebc;
2057                 rtlphy->reg_e94 = reg_e94;
2058                 rtlphy->reg_e9c = reg_e9c;
2059                 b_patha_ok = true;
2060                 b_pathb_ok = true;
2061         } else {
2062                 rtlphy->reg_e94 = 0x100;
2063                 rtlphy->reg_eb4 = 0x100;
2064                 rtlphy->reg_e9c = 0x0;
2065                 rtlphy->reg_ebc = 0x0;
2066         }
2067         if (reg_e94 != 0) /*&&(reg_ea4 != 0) */
2068                 _rtl88e_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result,
2069                                                    final_candidate,
2070                                                    (reg_ea4 == 0));
2071         if (final_candidate != 0xFF) {
2072                 for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
2073                         rtlphy->iqk_matrix[0].value[0][i] =
2074                                 result[final_candidate][i];
2075                 rtlphy->iqk_matrix[0].iqk_done = true;
2076
2077         }
2078         _rtl88e_phy_save_adda_registers(hw, iqk_bb_reg,
2079                                         rtlphy->iqk_bb_backup, 9);
2080 }
2081
2082 void rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw)
2083 {
2084         struct rtl_priv *rtlpriv = rtl_priv(hw);
2085         struct rtl_phy *rtlphy = &rtlpriv->phy;
2086         struct rtl_hal *rtlhal = &rtlpriv->rtlhal;
2087         u32 timeout = 2000, timecount = 0;
2088
2089         while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
2090                 udelay(50);
2091                 timecount += 50;
2092         }
2093
2094         rtlphy->lck_inprogress = true;
2095         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2096                 "LCK:Start!!! currentband %x delay %d ms\n",
2097                  rtlhal->current_bandtype, timecount);
2098
2099         _rtl88e_phy_lc_calibrate(hw, false);
2100
2101         rtlphy->lck_inprogress = false;
2102 }
2103
2104 void rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
2105 {
2106         _rtl88e_phy_set_rfpath_switch(hw, bmain, false);
2107 }
2108
2109 bool rtl88e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
2110 {
2111         struct rtl_priv *rtlpriv = rtl_priv(hw);
2112         struct rtl_phy *rtlphy = &rtlpriv->phy;
2113         bool postprocessing = false;
2114
2115         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2116                  "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
2117                   iotype, rtlphy->set_io_inprogress);
2118         do {
2119                 switch (iotype) {
2120                 case IO_CMD_RESUME_DM_BY_SCAN:
2121                         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2122                                  "[IO CMD] Resume DM after scan.\n");
2123                         postprocessing = true;
2124                         break;
2125                 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
2126                         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2127                                  "[IO CMD] Pause DM before scan.\n");
2128                         postprocessing = true;
2129                         break;
2130                 default:
2131                         RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2132                                  "switch case not process\n");
2133                         break;
2134                 }
2135         } while (false);
2136         if (postprocessing && !rtlphy->set_io_inprogress) {
2137                 rtlphy->set_io_inprogress = true;
2138                 rtlphy->current_io_type = iotype;
2139         } else {
2140                 return false;
2141         }
2142         rtl88e_phy_set_io(hw);
2143         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
2144         return true;
2145 }
2146
2147 static void rtl88e_phy_set_io(struct ieee80211_hw *hw)
2148 {
2149         struct rtl_priv *rtlpriv = rtl_priv(hw);
2150         struct rtl_phy *rtlphy = &rtlpriv->phy;
2151         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
2152
2153         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2154                  "--->Cmd(%#x), set_io_inprogress(%d)\n",
2155                   rtlphy->current_io_type, rtlphy->set_io_inprogress);
2156         switch (rtlphy->current_io_type) {
2157         case IO_CMD_RESUME_DM_BY_SCAN:
2158                 dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
2159                 /*rtl92c_dm_write_dig(hw);*/
2160                 rtl88e_phy_set_txpower_level(hw, rtlphy->current_channel);
2161                 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x83);
2162                 break;
2163         case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
2164                 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue;
2165                 dm_digtable->cur_igvalue = 0x17;
2166                 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x40);
2167                 break;
2168         default:
2169                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2170                          "switch case not process\n");
2171                 break;
2172         }
2173         rtlphy->set_io_inprogress = false;
2174         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2175                  "(%#x)\n", rtlphy->current_io_type);
2176 }
2177
2178 static void rtl88ee_phy_set_rf_on(struct ieee80211_hw *hw)
2179 {
2180         struct rtl_priv *rtlpriv = rtl_priv(hw);
2181
2182         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
2183         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2184         /*rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);*/
2185         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2186         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2187         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2188 }
2189
2190 static void _rtl88ee_phy_set_rf_sleep(struct ieee80211_hw *hw)
2191 {
2192         struct rtl_priv *rtlpriv = rtl_priv(hw);
2193
2194         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2195         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
2196         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2197         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
2198 }
2199
2200 static bool _rtl88ee_phy_set_rf_power_state(struct ieee80211_hw *hw,
2201                                             enum rf_pwrstate rfpwr_state)
2202 {
2203         struct rtl_priv *rtlpriv = rtl_priv(hw);
2204         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2205         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2206         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2207         bool bresult = true;
2208         u8 i, queue_id;
2209         struct rtl8192_tx_ring *ring = NULL;
2210
2211         switch (rfpwr_state) {
2212         case ERFON:
2213                 if ((ppsc->rfpwr_state == ERFOFF) &&
2214                     RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
2215                         bool rtstatus;
2216                         u32 initializecount = 0;
2217
2218                         do {
2219                                 initializecount++;
2220                                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2221                                          "IPS Set eRf nic enable\n");
2222                                 rtstatus = rtl_ps_enable_nic(hw);
2223                         } while (!rtstatus &&
2224                                  (initializecount < 10));
2225                         RT_CLEAR_PS_LEVEL(ppsc,
2226                                           RT_RF_OFF_LEVL_HALT_NIC);
2227                 } else {
2228                         RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2229                                  "Set ERFON sleeped:%d ms\n",
2230                                   jiffies_to_msecs(jiffies -
2231                                                    ppsc->
2232                                                    last_sleep_jiffies));
2233                         ppsc->last_awake_jiffies = jiffies;
2234                         rtl88ee_phy_set_rf_on(hw);
2235                 }
2236                 if (mac->link_state == MAC80211_LINKED) {
2237                         rtlpriv->cfg->ops->led_control(hw,
2238                                                        LED_CTL_LINK);
2239                 } else {
2240                         rtlpriv->cfg->ops->led_control(hw,
2241                                                        LED_CTL_NO_LINK);
2242                 }
2243                 break;
2244         case ERFOFF:
2245                 for (queue_id = 0, i = 0;
2246                      queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
2247                         ring = &pcipriv->dev.tx_ring[queue_id];
2248                         if (queue_id == BEACON_QUEUE ||
2249                             skb_queue_len(&ring->queue) == 0) {
2250                                 queue_id++;
2251                                 continue;
2252                         } else {
2253                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2254                                          "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
2255                                          (i + 1), queue_id,
2256                                          skb_queue_len(&ring->queue));
2257
2258                                 udelay(10);
2259                                 i++;
2260                         }
2261                         if (i >= MAX_DOZE_WAITING_TIMES_9x) {
2262                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2263                                          "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
2264                                           MAX_DOZE_WAITING_TIMES_9x,
2265                                           queue_id,
2266                                           skb_queue_len(&ring->queue));
2267                                 break;
2268                         }
2269                 }
2270
2271                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
2272                         RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2273                                  "IPS Set eRf nic disable\n");
2274                         rtl_ps_disable_nic(hw);
2275                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2276                 } else {
2277                         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
2278                                 rtlpriv->cfg->ops->led_control(hw,
2279                                                                LED_CTL_NO_LINK);
2280                         } else {
2281                                 rtlpriv->cfg->ops->led_control(hw,
2282                                                                LED_CTL_POWER_OFF);
2283                         }
2284                 }
2285                 break;
2286         case ERFSLEEP:{
2287                         if (ppsc->rfpwr_state == ERFOFF)
2288                                 break;
2289                         for (queue_id = 0, i = 0;
2290                              queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
2291                                 ring = &pcipriv->dev.tx_ring[queue_id];
2292                                 if (skb_queue_len(&ring->queue) == 0) {
2293                                         queue_id++;
2294                                         continue;
2295                                 } else {
2296                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2297                                                  "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
2298                                                  (i + 1), queue_id,
2299                                                  skb_queue_len(&ring->queue));
2300
2301                                         udelay(10);
2302                                         i++;
2303                                 }
2304                                 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
2305                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2306                                                  "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
2307                                                  MAX_DOZE_WAITING_TIMES_9x,
2308                                                  queue_id,
2309                                                  skb_queue_len(&ring->queue));
2310                                         break;
2311                                 }
2312                         }
2313                         RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2314                                  "Set ERFSLEEP awaked:%d ms\n",
2315                                   jiffies_to_msecs(jiffies -
2316                                   ppsc->last_awake_jiffies));
2317                         ppsc->last_sleep_jiffies = jiffies;
2318                         _rtl88ee_phy_set_rf_sleep(hw);
2319                         break;
2320                 }
2321         default:
2322                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2323                          "switch case not process\n");
2324                 bresult = false;
2325                 break;
2326         }
2327         if (bresult)
2328                 ppsc->rfpwr_state = rfpwr_state;
2329         return bresult;
2330 }
2331
2332 bool rtl88e_phy_set_rf_power_state(struct ieee80211_hw *hw,
2333                                    enum rf_pwrstate rfpwr_state)
2334 {
2335         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2336
2337         bool bresult = false;
2338
2339         if (rfpwr_state == ppsc->rfpwr_state)
2340                 return bresult;
2341         bresult = _rtl88ee_phy_set_rf_power_state(hw, rfpwr_state);
2342         return bresult;
2343 }