drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #ifndef __RTL8723E_PWRSEQ_H__
  27 #define __RTL8723E_PWRSEQ_H__
  28
  29 #include "../pwrseqcmd.h"
  30 /*
  31  *      Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd
  32  *      There are 6 HW Power States:
  33  *      0: POFF--Power Off
  34  *      1: PDN--Power Down
  35  *      2: CARDEMU--Card Emulation
  36  *      3: ACT--Active Mode
  37  *      4: LPS--Low Power State
  38  *      5: SUS--Suspend
  39  *
  40  *      The transision from different states are defined below
  41  *      TRANS_CARDEMU_TO_ACT
  42  *      TRANS_ACT_TO_CARDEMU
  43  *      TRANS_CARDEMU_TO_SUS
  44  *      TRANS_SUS_TO_CARDEMU
  45  *      TRANS_CARDEMU_TO_PDN
  46  *      TRANS_ACT_TO_LPS
  47  *      TRANS_LPS_TO_ACT
  48  *
  49  *      TRANS_END
  50  */
  51
  52 #define RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS     10
  53 #define RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS     10
  54 #define RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS     10
  55 #define RTL8723A_TRANS_SUS_TO_CARDEMU_STEPS     10
  56 #define RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS     10
  57 #define RTL8723A_TRANS_PDN_TO_CARDEMU_STEPS     10
  58 #define RTL8723A_TRANS_ACT_TO_LPS_STEPS         15
  59 #define RTL8723A_TRANS_LPS_TO_ACT_STEPS         15
  60 #define RTL8723A_TRANS_END_STEPS                1
  61
  62 /* format */
  63 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }*/
  64
  65 #define RTL8723A_TRANS_CARDEMU_TO_ACT   \
  66         /* disable SW LPS 0x04[10]=0*/  \
  67         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  68                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), 0},\
  69         /* wait till 0x04[17] = 1    power ready*/      \
  70         {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  71                 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},\
  72         /* release WLON reset  0x04[16]=1*/     \
  73         {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  74                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
  75         /* disable HWPDN 0x04[15]=0*/ \
  76         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  77                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
  78         /* disable WL suspend*/ \
  79         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  80                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},\
  81         /* polling until return 0*/ \
  82         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  83                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
  84         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  85                 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},
  86
  87 /* format */
  88 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
  89
  90 #define RTL8723A_TRANS_ACT_TO_CARDEMU   \
  91         /*0x1F[7:0] = 0 turn off RF*/ \
  92         {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  93                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},      \
  94         {0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  95                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
  96         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  97                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
  98         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  99                 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0},
 100
 101 /* format */
 102 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/
 103 #define RTL8723A_TRANS_CARDEMU_TO_SUS                   \
 104                 /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/      \
 105         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
 106                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, \
 107                 BIT(4)|BIT(3), (BIT(4)|BIT(3))},\
 108 /*0x04[12:11] = 2b'01 enable WL suspend*/       \
 109         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK| \
 110                 PWR_INTF_SDIO_MSK,\
 111                 PWR_BASEADDR_MAC, \
 112                 PWR_CMD_WRITE, \
 113                 BIT(3)|BIT(4), BIT(3)}, \
 114 /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
 115         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 116                 PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, \
 117                 PWR_CMD_WRITE, BIT(3)|BIT(4), \
 118                 BIT(3)|BIT(4)}, \
 119 /*Set SDIO suspend local register*/     \
 120         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 121                 PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
 122                 PWR_CMD_WRITE, BIT(0), BIT(0)}, \
 123 /*wait power state to suspend*/ \
 124         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 125                 PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
 126                 PWR_CMD_POLLING, BIT(1), 0},
 127
 128 /* format */
 129 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
 130
 131 #define RTL8723A_TRANS_SUS_TO_CARDEMU   \
 132  /*Set SDIO suspend local register*/    \
 133         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
 134                 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},\
 135  /*wait power state to suspend*/ \
 136         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
 137                 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},\
 138  /*0x04[12:11] = 2b'01enable WL suspend*/ \
 139         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 140                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
 141
 142 /* format */
 143 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
 144
 145 #define RTL8723A_TRANS_CARDEMU_TO_CARDDIS \
 146  /*0x04[12:11] = 2b'01 enable WL suspend*/       \
 147         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 148                 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, \
 149                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
 150 /*0x04[10] = 1, enable SW LPS*/ \
 151         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 152                 PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC,\
 153                 PWR_CMD_WRITE, BIT(2), BIT(2)}, \
 154 /*Set SDIO suspend local register*/ \
 155         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 156                 PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
 157                 PWR_CMD_WRITE, BIT(0), BIT(0)}, \
 158  /*wait power state to suspend*/ \
 159         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 160                 PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
 161                 PWR_CMD_POLLING, BIT(1), 0},
 162
 163 /* format */
 164 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
 165
 166 #define RTL8723A_TRANS_CARDDIS_TO_CARDEMU\
 167 /*Set SDIO suspend local register*/     \
 168         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 169                 PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
 170                 PWR_CMD_WRITE, BIT(0), 0}, \
 171  /*wait power state to suspend*/ \
 172         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 173                 PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
 174                 PWR_CMD_POLLING, BIT(1), BIT(1)},\
 175  /*0x04[12:11] = 2b'00enable WL suspend*/ \
 176         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 177                 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
 178                 PWR_CMD_WRITE, BIT(3)|BIT(4), 0},\
 179 /*PCIe DMA start*/ \
 180         {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 181                 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
 182                 PWR_CMD_WRITE, 0xFF, 0},
 183
 184 /* format */
 185 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
 186 #define RTL8723A_TRANS_CARDEMU_TO_PDN   \
 187         {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 188                 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
 189                 PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/\
 190         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 191                 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
 192                 PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/
 193
 194 /* format */
 195 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
 196 #define RTL8723A_TRANS_PDN_TO_CARDEMU   \
 197         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 198                 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
 199                 PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/
 200
 201 /* format */
 202 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
 203
 204 #define RTL8723A_TRANS_ACT_TO_LPS       \
 205         {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 206                 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
 207                 PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/    \
 208         {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 209                 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
 210                 PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
 211         /*Should be zero if no packet is transmitting*/ \
 212         {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 213                 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
 214                 PWR_CMD_POLLING, 0xFF, 0},\
 215         /*Should be zero if no packet is transmitting*/ \
 216         {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 217                 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
 218                 PWR_CMD_POLLING, 0xFF, 0},\
 219         /*Should be zero if no packet is transmitting*/ \
 220         {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 221                 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
 222                 PWR_CMD_POLLING, 0xFF, 0},\
 223         /*Should be zero if no packet is transmitting*/ \
 224         {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 225                 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
 226                 PWR_CMD_POLLING, 0xFF, 0},\
 227         /*CCK and OFDM are disabled,and clock are gated*/ \
 228         {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 229                 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
 230                 PWR_CMD_WRITE, BIT(0), 0},\
 231         {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 232                 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
 233                 PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/\
 234         {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 235                 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
 236                 PWR_CMD_WRITE, BIT(1), 0},/*Whole BB is reset*/ \
 237         {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 238                 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
 239                 PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/    \
 240         {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 241                 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
 242                 PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/    \
 243         /*Respond TxOK to scheduler*/   \
 244         {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 245                 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
 246                 PWR_CMD_WRITE, BIT(5), BIT(5)},\
 247
 248 #define RTL8723A_TRANS_LPS_TO_ACT\
 249 /* format */    \
 250 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */ \
 251         {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 252                 PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
 253                 PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
 254         {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 255                 PWR_INTF_USB_MSK, PWR_BASEADDR_MAC,\
 256                 PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
 257         {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 258                 PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC,\
 259                 PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
 260         {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 261                 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
 262                 PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
 263         /*.     0x08[4] = 0              switch TSF to 40M*/\
 264         {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 265                 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
 266                 PWR_CMD_WRITE, BIT(4), 0},  \
 267         /*Polling 0x109[7]=0  TSF in 40M*/\
 268         {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 269                 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
 270                 PWR_CMD_POLLING, BIT(7), 0}, \
 271         /*.     0x29[7:6] = 2b'00        enable BB clock*/\
 272         {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 273                 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
 274                 PWR_CMD_WRITE, BIT(6)|BIT(7), 0},\
 275          /*.    0x101[1] = 1*/\
 276         {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 277                 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
 278                 PWR_CMD_WRITE, BIT(1), BIT(1)},\
 279          /*.    0x100[7:0] = 0xFF        enable WMAC TRX*/\
 280         {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 281                 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
 282                 PWR_CMD_WRITE, 0xFF, 0xFF},\
 283          /*.    0x02[1:0] = 2b'11        enable BB macro*/\
 284         {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 285                 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
 286                 PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)},\
 287         {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
 288                 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
 289                 PWR_CMD_WRITE, 0xFF, 0}, /*.    0x522 = 0*/
 290
 291 /* format */
 292 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
 293
 294 #define RTL8723A_TRANS_END \
 295         {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 296         0, PWR_CMD_END, 0, 0}
 297
 298 extern struct wlan_pwr_cfg rtl8723A_power_on_flow
 299                 [RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS +
 300                  RTL8723A_TRANS_END_STEPS];
 301 extern struct wlan_pwr_cfg rtl8723A_radio_off_flow
 302                 [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
 303                  RTL8723A_TRANS_END_STEPS];
 304 extern struct wlan_pwr_cfg rtl8723A_card_disable_flow
 305                 [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
 306                  RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS +
 307                  RTL8723A_TRANS_END_STEPS];
 308 extern struct wlan_pwr_cfg rtl8723A_card_enable_flow
 309                 [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
 310                  RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS +
 311                  RTL8723A_TRANS_END_STEPS];
 312 extern struct wlan_pwr_cfg rtl8723A_suspend_flow
 313                 [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
 314                  RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS +
 315                  RTL8723A_TRANS_END_STEPS];
 316 extern struct wlan_pwr_cfg rtl8723A_resume_flow
 317                 [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
 318                  RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS +
 319                  RTL8723A_TRANS_END_STEPS];
 320 extern struct wlan_pwr_cfg rtl8723A_hwpdn_flow
 321                 [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
 322                  RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS +
 323                  RTL8723A_TRANS_END_STEPS];
 324 extern struct wlan_pwr_cfg rtl8723A_enter_lps_flow
 325                 [RTL8723A_TRANS_ACT_TO_LPS_STEPS + RTL8723A_TRANS_END_STEPS];
 326 extern struct wlan_pwr_cfg rtl8723A_leave_lps_flow
 327                 [RTL8723A_TRANS_LPS_TO_ACT_STEPS + RTL8723A_TRANS_END_STEPS];
 328
 329 /* RTL8723 Power Configuration CMDs for PCIe interface */
 330 #define Rtl8723_NIC_PWR_ON_FLOW         rtl8723A_power_on_flow
 331 #define Rtl8723_NIC_RF_OFF_FLOW         rtl8723A_radio_off_flow
 332 #define Rtl8723_NIC_DISABLE_FLOW        rtl8723A_card_disable_flow
 333 #define Rtl8723_NIC_ENABLE_FLOW         rtl8723A_card_enable_flow
 334 #define Rtl8723_NIC_SUSPEND_FLOW        rtl8723A_suspend_flow
 335 #define Rtl8723_NIC_RESUME_FLOW         rtl8723A_resume_flow
 336 #define Rtl8723_NIC_PDN_FLOW            rtl8723A_hwpdn_flow
 337 #define Rtl8723_NIC_LPS_ENTER_FLOW      rtl8723A_enter_lps_flow
 338 #define Rtl8723_NIC_LPS_LEAVE_FLOW      rtl8723A_leave_lps_flow
 339
 340 #endif