drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2014  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #ifndef __RTL8723BE_PWRSEQ_H__
  27 #define __RTL8723BE_PWRSEQ_H__
  28
  29 #include "../pwrseqcmd.h"
  30 /**
  31  *      Check document WM-20130425-JackieLau-RTL8723B_Power_Architecture v05.vsd
  32  *      There are 6 HW Power States:
  33  *      0: POFF--Power Off
  34  *      1: PDN--Power Down
  35  *      2: CARDEMU--Card Emulation
  36  *      3: ACT--Active Mode
  37  *      4: LPS--Low Power State
  38  *      5: SUS--Suspend
  39  *
  40  *      The transision from different states are defined below
  41  *      TRANS_CARDEMU_TO_ACT
  42  *      TRANS_ACT_TO_CARDEMU
  43  *      TRANS_CARDEMU_TO_SUS
  44  *      TRANS_SUS_TO_CARDEMU
  45  *      TRANS_CARDEMU_TO_PDN
  46  *      TRANS_ACT_TO_LPS
  47  *      TRANS_LPS_TO_ACT
  48  *
  49  *      TRANS_END
  50  */
  51 #define RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS     23
  52 #define RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS     15
  53 #define RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS     15
  54 #define RTL8723B_TRANS_SUS_TO_CARDEMU_STEPS     15
  55 #define RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS     15
  56 #define RTL8723B_TRANS_PDN_TO_CARDEMU_STEPS     15
  57 #define RTL8723B_TRANS_ACT_TO_LPS_STEPS         15
  58 #define RTL8723B_TRANS_LPS_TO_ACT_STEPS         15
  59 #define RTL8723B_TRANS_END_STEPS                1
  60
  61 #define RTL8723B_TRANS_CARDEMU_TO_ACT                                   \
  62         /* format */                                                    \
  63         /* comments here */                                             \
  64         /* {offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value}, */\
  65         /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/  \
  66         {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
  67          PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK,                          \
  68          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},              \
  69         /*0x67[0] = 0 to disable BT_GPS_SEL pins*/                      \
  70         {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
  71          PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK,                          \
  72          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},                   \
  73         /*Delay 1ms*/                                                   \
  74         {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
  75          PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK,                          \
  76          PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},          \
  77         /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/   \
  78         {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
  79          PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK,                          \
  80          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), 0},                   \
  81         /* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/          \
  82         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  83          PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)|BIT(2)), 0},   \
  84         /* Disable USB suspend */                                       \
  85         {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
  86          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , BIT(0)},             \
  87         /* wait till 0x04[17] = 1    power ready*/                      \
  88         {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  89          PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},            \
  90         /* Enable USB suspend */                                        \
  91         {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
  92          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , 0},                  \
  93         /* release WLON reset  0x04[16]=1*/                             \
  94         {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  95          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},              \
  96         /* disable HWPDN 0x04[15]=0*/                                   \
  97         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  98          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},                   \
  99         /* disable WL suspend*/                                         \
 100         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 101          PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},          \
 102         /* polling until return 0*/                                     \
 103         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 104          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},              \
 105         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 106          PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},                 \
 107         /* Enable WL control XTAL setting*/                             \
 108         {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 109          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},              \
 110         /*Enable falling edge triggering interrupt*/                    \
 111         {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 112          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},              \
 113         /*Enable GPIO9 interrupt mode*/                                 \
 114         {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 115          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},              \
 116         /*Enable GPIO9 input mode*/                                     \
 117         {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 118          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},                   \
 119         /*Enable HSISR GPIO[C:0] interrupt*/                            \
 120         {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 121          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},              \
 122         /*Enable HSISR GPIO9 interrupt*/                                \
 123         {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 124          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},              \
 125         /*For GPIO9 internal pull high setting by test chip*/           \
 126         {0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 127          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3), BIT(3)},              \
 128         /*For GPIO9 internal pull high setting*/                        \
 129         {0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 130          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},
 131
 132 #define RTL8723B_TRANS_ACT_TO_CARDEMU                                   \
 133         /* format */                                                    \
 134         /* comments here */                                             \
 135         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 136         /*0x1F[7:0] = 0 turn off RF*/                                   \
 137         {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 138          PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},                     \
 139         /*0x4C[24] = 0x4F[0] = 0, */                                    \
 140         /*switch DPDT_SEL_P output from register 0x65[2] */             \
 141         {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 142          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},                   \
 143         /*Enable rising edge triggering interrupt*/                     \
 144         {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 145          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},                   \
 146          /*0x04[9] = 1 turn off MAC by HW state machine*/               \
 147         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 148          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},              \
 149          /*wait till 0x04[9] = 0 polling until return 0 to disable*/    \
 150         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 151          PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0},                 \
 152         /* Enable BT control XTAL setting*/                             \
 153         {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 154          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), 0},                   \
 155         /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/           \
 156         {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 157          PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC,        \
 158          PWR_CMD_WRITE, BIT(5), BIT(5)},                                \
 159         /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/                   \
 160         {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 161          PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC,        \
 162          PWR_CMD_WRITE, BIT(0), 0},
 163
 164 #define RTL8723B_TRANS_CARDEMU_TO_SUS                                   \
 165         /* format */                                                    \
 166         /* comments here */                                             \
 167         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
 168         /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/              \
 169         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
 170          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))}, \
 171         /*0x04[12:11] = 2b'01 enable WL suspend*/                       \
 172         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 173          PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC,        \
 174          PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},                       \
 175         /*0x23[4] = 1b'1 12H LDO enter sleep mode*/                     \
 176         {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 177          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)},              \
 178         /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \
 179         {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 180          PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20},                  \
 181         /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/              \
 182         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
 183          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\
 184         /*Set SDIO suspend local register*/                             \
 185         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 186          PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)},             \
 187         /*wait power state to suspend*/                                 \
 188         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 189          PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
 190
 191 #define RTL8723B_TRANS_SUS_TO_CARDEMU                                   \
 192         /* format */                                                    \
 193         /* comments here */                                             \
 194         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 195         /*clear suspend enable and power down enable*/                  \
 196         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 197          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0},          \
 198         /*Set SDIO suspend local register*/                             \
 199         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 200          PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},                  \
 201         /*wait power state to suspend*/                                 \
 202         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 203          PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},           \
 204         /*0x23[4] = 1b'0 12H LDO enter normal mode*/                    \
 205         {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 206          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},                   \
 207         /*0x04[12:11] = 2b'01enable WL suspend*/                        \
 208         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 209          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
 210
 211 #define RTL8723B_TRANS_CARDEMU_TO_CARDDIS                               \
 212         /* format */                                                    \
 213         /* comments here */                                             \
 214         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 215         /*0x07=0x20 , SOP option to disable BG/MB*/                     \
 216         {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 217          PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20},                  \
 218         /*0x04[12:11] = 2b'01 enable WL suspend*/                       \
 219         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 220          PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK,                          \
 221          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)},       \
 222         /*0x04[10] = 1, enable SW LPS*/                                 \
 223         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
 224          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), BIT(2)},              \
 225         /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/                  \
 226         {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,    \
 227          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 1},                   \
 228         /*0x23[4] = 1b'1 12H LDO enter sleep mode*/                     \
 229         {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 230          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)},              \
 231         /*Set SDIO suspend local register*/                             \
 232         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 233          PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)},             \
 234         /*wait power state to suspend*/                                 \
 235         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 236          PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
 237
 238 #define RTL8723B_TRANS_CARDDIS_TO_CARDEMU                               \
 239         /* format */                                                    \
 240         /* comments here */                                             \
 241         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 242         /*clear suspend enable and power down enable*/                  \
 243         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 244          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0},          \
 245         /*Set SDIO suspend local register*/                             \
 246         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 247          PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},                  \
 248         /*wait power state to suspend*/                                 \
 249         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 250          PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},           \
 251         /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/                 \
 252         {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,    \
 253          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},                   \
 254         /*0x04[12:11] = 2b'01enable WL suspend*/                        \
 255         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 256          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},            \
 257         /*0x23[4] = 1b'0 12H LDO enter normal mode*/                    \
 258         {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 259          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},                   \
 260         /*PCIe DMA start*/                                              \
 261         {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
 262          PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},
 263
 264 #define RTL8723B_TRANS_CARDEMU_TO_PDN                                   \
 265         /* format */                                                    \
 266         /* comments here */                                             \
 267         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 268         /*0x23[4] = 1b'1 12H LDO enter sleep mode*/                     \
 269         {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 270          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)},              \
 271         /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/        \
 272         {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 273          PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC,        \
 274          PWR_CMD_WRITE, 0xFF, 0x20},                                    \
 275         /* 0x04[16] = 0*/                                               \
 276         {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 277          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},                   \
 278         /* 0x04[15] = 1*/                                               \
 279         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 280          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},
 281
 282 #define RTL8723B_TRANS_PDN_TO_CARDEMU                                   \
 283         /* format */                                                    \
 284         /* comments here */                                             \
 285         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 286         /* 0x04[15] = 0*/                                               \
 287         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 288          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},
 289
 290 #define RTL8723B_TRANS_ACT_TO_LPS                                       \
 291         /* format */                                                    \
 292         /* comments here */                                             \
 293         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 294         /*PCIe DMA stop*/                                               \
 295         {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
 296          PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},                  \
 297         /*Tx Pause*/                                                    \
 298         {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 299          PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},                  \
 300         /*Should be zero if no packet is transmitting*/                 \
 301         {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 302          PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},                   \
 303         /*Should be zero if no packet is transmitting*/                 \
 304         {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 305          PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},                   \
 306         /*Should be zero if no packet is transmitting*/                 \
 307         {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 308          PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},                   \
 309         /*Should be zero if no packet is transmitting*/                 \
 310         {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 311          PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},                   \
 312         /*CCK and OFDM are disabled,and clock are gated*/               \
 313         {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 314          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},                   \
 315         /*Delay 1us*/                                                   \
 316         {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 317          PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},          \
 318         /*Whole BB is reset*/                                           \
 319         {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 320          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},                   \
 321         /*Reset MAC TRX*/                                               \
 322         {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 323          PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},                  \
 324         /*check if removed later*/                                      \
 325         {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 326          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},                   \
 327         /*When driver enter Sus/ Disable, enable LOP for BT*/           \
 328         {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 329          PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},                  \
 330         /*Respond TxOK to scheduler*/                                   \
 331         {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 332          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)},
 333
 334 #define RTL8723B_TRANS_LPS_TO_ACT                                       \
 335         /* format */                                                    \
 336         /* comments here */                                             \
 337         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 338         /*SDIO RPWM*/                                                   \
 339         {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 340          PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84},                 \
 341         /*USB RPWM*/                                                    \
 342         {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,    \
 343          PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84},                  \
 344         /*PCIe RPWM*/                                                   \
 345         {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
 346          PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84},                  \
 347         /*Delay*/                                                       \
 348         {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 349          PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS},          \
 350         /*.     0x08[4] = 0              switch TSF to 40M*/            \
 351         {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 352          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},                   \
 353         /*Polling 0x109[7]=0  TSF in 40M*/                              \
 354         {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 355          PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0},                 \
 356         /*.     0x29[7:6] = 2b'00        enable BB clock*/              \
 357         {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 358          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0},            \
 359         /*.     0x101[1] = 1*/                                          \
 360         {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 361          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},              \
 362         /*.     0x100[7:0] = 0xFF        enable WMAC TRX*/              \
 363         {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 364          PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},                  \
 365         /*.     0x02[1:0] = 2b'11        enable BB macro*/              \
 366         {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 367          PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \
 368         /*.     0x522 = 0*/                                             \
 369         {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 370          PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},
 371
 372 #define RTL8723B_TRANS_END                                              \
 373         /* format */                                                    \
 374         /* comments here */                                             \
 375         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 376         {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, \
 377          PWR_CMD_END, 0, 0},
 378
 379 extern struct wlan_pwr_cfg rtl8723B_power_on_flow
 380                                 [RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS +
 381                                  RTL8723B_TRANS_END_STEPS];
 382 extern struct wlan_pwr_cfg rtl8723B_radio_off_flow
 383                                 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
 384                                  RTL8723B_TRANS_END_STEPS];
 385 extern struct wlan_pwr_cfg rtl8723B_card_disable_flow
 386                                 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
 387                                  RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS +
 388                                  RTL8723B_TRANS_END_STEPS];
 389 extern struct wlan_pwr_cfg rtl8723B_card_enable_flow
 390                                 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
 391                                  RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS +
 392                                  RTL8723B_TRANS_END_STEPS];
 393 extern struct wlan_pwr_cfg rtl8723B_suspend_flow
 394                                 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
 395                                  RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS +
 396                                  RTL8723B_TRANS_END_STEPS];
 397 extern struct wlan_pwr_cfg rtl8723B_resume_flow
 398                                 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
 399                                  RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS +
 400                                  RTL8723B_TRANS_END_STEPS];
 401 extern struct wlan_pwr_cfg rtl8723B_hwpdn_flow
 402                                 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
 403                                  RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS +
 404                                  RTL8723B_TRANS_END_STEPS];
 405 extern struct wlan_pwr_cfg rtl8723B_enter_lps_flow
 406                                 [RTL8723B_TRANS_ACT_TO_LPS_STEPS +
 407                                  RTL8723B_TRANS_END_STEPS];
 408 extern struct wlan_pwr_cfg rtl8723B_leave_lps_flow
 409                                 [RTL8723B_TRANS_LPS_TO_ACT_STEPS +
 410                                  RTL8723B_TRANS_END_STEPS];
 411
 412 /* RTL8723 Power Configuration CMDs for PCIe interface */
 413 #define RTL8723_NIC_PWR_ON_FLOW         rtl8723B_power_on_flow
 414 #define RTL8723_NIC_RF_OFF_FLOW         rtl8723B_radio_off_flow
 415 #define RTL8723_NIC_DISABLE_FLOW        rtl8723B_card_disable_flow
 416 #define RTL8723_NIC_ENABLE_FLOW         rtl8723B_card_enable_flow
 417 #define RTL8723_NIC_SUSPEND_FLOW        rtl8723B_suspend_flow
 418 #define RTL8723_NIC_RESUME_FLOW         rtl8723B_resume_flow
 419 #define RTL8723_NIC_PDN_FLOW            rtl8723B_hwpdn_flow
 420 #define RTL8723_NIC_LPS_ENTER_FLOW      rtl8723B_enter_lps_flow
 421 #define RTL8723_NIC_LPS_LEAVE_FLOW      rtl8723B_leave_lps_flow
 422
 423 #endif