drivers/net/wireless/realtek/rtlwifi/rtl8723be/sw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2014  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../core.h"
  28 #include "../pci.h"
  29 #include "reg.h"
  30 #include "def.h"
  31 #include "phy.h"
  32 #include "../rtl8723com/phy_common.h"
  33 #include "dm.h"
  34 #include "../rtl8723com/dm_common.h"
  35 #include "hw.h"
  36 #include "fw.h"
  37 #include "../rtl8723com/fw_common.h"
  38 #include "sw.h"
  39 #include "trx.h"
  40 #include "led.h"
  41 #include "table.h"
  42 #include "../btcoexist/rtl_btc.h"
  43
  44 #include <linux/vmalloc.h>
  45 #include <linux/module.h>
  46
  47 static void rtl8723be_init_aspm_vars(struct ieee80211_hw *hw)
  48 {
  49         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  50
  51         /*close ASPM for AMD defaultly */
  52         rtlpci->const_amdpci_aspm = 0;
  53
  54         /* ASPM PS mode.
  55          * 0 - Disable ASPM,
  56          * 1 - Enable ASPM without Clock Req,
  57          * 2 - Enable ASPM with Clock Req,
  58          * 3 - Alwyas Enable ASPM with Clock Req,
  59          * 4 - Always Enable ASPM without Clock Req.
  60          * set defult to RTL8192CE:3 RTL8192E:2
  61          */
  62         rtlpci->const_pci_aspm = 3;
  63
  64         /*Setting for PCI-E device */
  65         rtlpci->const_devicepci_aspm_setting = 0x03;
  66
  67         /*Setting for PCI-E bridge */
  68         rtlpci->const_hostpci_aspm_setting = 0x02;
  69
  70         /* In Hw/Sw Radio Off situation.
  71          * 0 - Default,
  72          * 1 - From ASPM setting without low Mac Pwr,
  73          * 2 - From ASPM setting with low Mac Pwr,
  74          * 3 - Bus D3
  75          * set default to RTL8192CE:0 RTL8192SE:2
  76          */
  77         rtlpci->const_hwsw_rfoff_d3 = 0;
  78
  79         /* This setting works for those device with
  80          * backdoor ASPM setting such as EPHY setting.
  81          * 0 - Not support ASPM,
  82          * 1 - Support ASPM,
  83          * 2 - According to chipset.
  84          */
  85         rtlpci->const_support_pciaspm = 1;
  86 }
  87
  88 int rtl8723be_init_sw_vars(struct ieee80211_hw *hw)
  89 {
  90         int err = 0;
  91         struct rtl_priv *rtlpriv = rtl_priv(hw);
  92         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  93         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  94
  95         rtl8723be_bt_reg_init(hw);
  96         rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
  97         rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer();
  98
  99         rtlpriv->dm.dm_initialgain_enable = 1;
 100         rtlpriv->dm.dm_flag = 0;
 101         rtlpriv->dm.disable_framebursting = 0;
 102         rtlpriv->dm.thermalvalue = 0;
 103         rtlpci->transmit_config = CFENDFORM | BIT(15) | BIT(24) | BIT(25);
 104
 105         rtlpriv->phy.lck_inprogress = false;
 106
 107         mac->ht_enable = true;
 108
 109         /* compatible 5G band 88ce just 2.4G band & smsp */
 110         rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
 111         rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
 112         rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
 113
 114         rtlpci->receive_config = (RCR_APPFCS            |
 115                                   RCR_APP_MIC           |
 116                                   RCR_APP_ICV           |
 117                                   RCR_APP_PHYST_RXFF    |
 118                                   RCR_HTC_LOC_CTRL      |
 119                                   RCR_AMF               |
 120                                   RCR_ACF               |
 121                                   RCR_ADF               |
 122                                   RCR_AICV              |
 123                                   RCR_AB                |
 124                                   RCR_AM                |
 125                                   RCR_APM               |
 126                                   0);
 127
 128         rtlpci->irq_mask[0] = (u32) (IMR_PSTIMEOUT      |
 129                                      IMR_HSISR_IND_ON_INT       |
 130                                      IMR_C2HCMD         |
 131                                      IMR_HIGHDOK        |
 132                                      IMR_MGNTDOK        |
 133                                      IMR_BKDOK          |
 134                                      IMR_BEDOK          |
 135                                      IMR_VIDOK          |
 136                                      IMR_VODOK          |
 137                                      IMR_RDU            |
 138                                      IMR_ROK            |
 139                                      0);
 140
 141         rtlpci->irq_mask[1] = (u32)(IMR_RXFOVW | 0);
 142
 143         rtlpci->sys_irq_mask = (u32)(HSIMR_PDN_INT_EN   |
 144                                      HSIMR_RON_INT_EN   |
 145                                      0);
 146
 147         /* for debug level */
 148         rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
 149         /* for LPS & IPS */
 150         rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
 151         rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
 152         rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
 153         rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
 154         if (rtlpriv->cfg->mod_params->disable_watchdog)
 155                 pr_info("watchdog disabled\n");
 156         rtlpriv->psc.reg_fwctrl_lps = 3;
 157         rtlpriv->psc.reg_max_lps_awakeintvl = 5;
 158         /* for ASPM, you can close aspm through
 159          * set const_support_pciaspm = 0
 160          */
 161         rtl8723be_init_aspm_vars(hw);
 162
 163         if (rtlpriv->psc.reg_fwctrl_lps == 1)
 164                 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
 165         else if (rtlpriv->psc.reg_fwctrl_lps == 2)
 166                 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
 167         else if (rtlpriv->psc.reg_fwctrl_lps == 3)
 168                 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
 169
 170         /*low power: Disable 32k */
 171         rtlpriv->psc.low_power_enable = false;
 172
 173         rtlpriv->rtlhal.earlymode_enable = false;
 174
 175         /* for firmware buf */
 176         rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
 177         if (!rtlpriv->rtlhal.pfirmware) {
 178                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 179                          "Can't alloc buffer for fw.\n");
 180                 return 1;
 181         }
 182
 183         rtlpriv->max_fw_size = 0x8000;
 184         pr_info("Using firmware %s\n", rtlpriv->cfg->fw_name);
 185         err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
 186                                       rtlpriv->io.dev, GFP_KERNEL, hw,
 187                                       rtl_fw_cb);
 188         if (err) {
 189                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 190                          "Failed to request firmware!\n");
 191                 return 1;
 192         }
 193         return 0;
 194 }
 195
 196 void rtl8723be_deinit_sw_vars(struct ieee80211_hw *hw)
 197 {
 198         struct rtl_priv *rtlpriv = rtl_priv(hw);
 199
 200         if (rtlpriv->rtlhal.pfirmware) {
 201                 vfree(rtlpriv->rtlhal.pfirmware);
 202                 rtlpriv->rtlhal.pfirmware = NULL;
 203         }
 204 }
 205
 206 /* get bt coexist status */
 207 bool rtl8723be_get_btc_status(void)
 208 {
 209         return true;
 210 }
 211
 212 static bool is_fw_header(struct rtlwifi_firmware_header *hdr)
 213 {
 214         return (le16_to_cpu(hdr->signature) & 0xfff0) == 0x5300;
 215 }
 216
 217 static struct rtl_hal_ops rtl8723be_hal_ops = {
 218         .init_sw_vars = rtl8723be_init_sw_vars,
 219         .deinit_sw_vars = rtl8723be_deinit_sw_vars,
 220         .read_eeprom_info = rtl8723be_read_eeprom_info,
 221         .interrupt_recognized = rtl8723be_interrupt_recognized,
 222         .hw_init = rtl8723be_hw_init,
 223         .hw_disable = rtl8723be_card_disable,
 224         .hw_suspend = rtl8723be_suspend,
 225         .hw_resume = rtl8723be_resume,
 226         .enable_interrupt = rtl8723be_enable_interrupt,
 227         .disable_interrupt = rtl8723be_disable_interrupt,
 228         .set_network_type = rtl8723be_set_network_type,
 229         .set_chk_bssid = rtl8723be_set_check_bssid,
 230         .set_qos = rtl8723be_set_qos,
 231         .set_bcn_reg = rtl8723be_set_beacon_related_registers,
 232         .set_bcn_intv = rtl8723be_set_beacon_interval,
 233         .update_interrupt_mask = rtl8723be_update_interrupt_mask,
 234         .get_hw_reg = rtl8723be_get_hw_reg,
 235         .set_hw_reg = rtl8723be_set_hw_reg,
 236         .update_rate_tbl = rtl8723be_update_hal_rate_tbl,
 237         .fill_tx_desc = rtl8723be_tx_fill_desc,
 238         .fill_tx_cmddesc = rtl8723be_tx_fill_cmddesc,
 239         .query_rx_desc = rtl8723be_rx_query_desc,
 240         .set_channel_access = rtl8723be_update_channel_access_setting,
 241         .radio_onoff_checking = rtl8723be_gpio_radio_on_off_checking,
 242         .set_bw_mode = rtl8723be_phy_set_bw_mode,
 243         .switch_channel = rtl8723be_phy_sw_chnl,
 244         .dm_watchdog = rtl8723be_dm_watchdog,
 245         .scan_operation_backup = rtl8723be_phy_scan_operation_backup,
 246         .set_rf_power_state = rtl8723be_phy_set_rf_power_state,
 247         .led_control = rtl8723be_led_control,
 248         .set_desc = rtl8723be_set_desc,
 249         .get_desc = rtl8723be_get_desc,
 250         .is_tx_desc_closed = rtl8723be_is_tx_desc_closed,
 251         .tx_polling = rtl8723be_tx_polling,
 252         .enable_hw_sec = rtl8723be_enable_hw_security_config,
 253         .set_key = rtl8723be_set_key,
 254         .init_sw_leds = rtl8723be_init_sw_leds,
 255         .get_bbreg = rtl8723_phy_query_bb_reg,
 256         .set_bbreg = rtl8723_phy_set_bb_reg,
 257         .get_rfreg = rtl8723be_phy_query_rf_reg,
 258         .set_rfreg = rtl8723be_phy_set_rf_reg,
 259         .fill_h2c_cmd = rtl8723be_fill_h2c_cmd,
 260         .get_btc_status = rtl8723be_get_btc_status,
 261         .rx_command_packet = rtl8723be_rx_command_packet,
 262         .is_fw_header = is_fw_header,
 263 };
 264
 265 static struct rtl_mod_params rtl8723be_mod_params = {
 266         .sw_crypto = false,
 267         .inactiveps = true,
 268         .swctrl_lps = false,
 269         .fwctrl_lps = true,
 270 };
 271
 272 static struct rtl_hal_cfg rtl8723be_hal_cfg = {
 273         .bar_id = 2,
 274         .write_readback = true,
 275         .name = "rtl8723be_pci",
 276         .fw_name = "rtlwifi/rtl8723befw.bin",
 277         .ops = &rtl8723be_hal_ops,
 278         .mod_params = &rtl8723be_mod_params,
 279         .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
 280         .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
 281         .maps[SYS_CLK] = REG_SYS_CLKR,
 282         .maps[MAC_RCR_AM] = AM,
 283         .maps[MAC_RCR_AB] = AB,
 284         .maps[MAC_RCR_ACRC32] = ACRC32,
 285         .maps[MAC_RCR_ACF] = ACF,
 286         .maps[MAC_RCR_AAP] = AAP,
 287         .maps[MAC_HIMR] = REG_HIMR,
 288         .maps[MAC_HIMRE] = REG_HIMRE,
 289         .maps[MAC_HSISR] = REG_HSISR,
 290
 291         .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
 292
 293         .maps[EFUSE_TEST] = REG_EFUSE_TEST,
 294         .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
 295         .maps[EFUSE_CLK] = 0,
 296         .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
 297         .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
 298         .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
 299         .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
 300         .maps[EFUSE_ANA8M] = ANA8M,
 301         .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
 302         .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
 303         .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
 304         .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
 305
 306         .maps[RWCAM] = REG_CAMCMD,
 307         .maps[WCAMI] = REG_CAMWRITE,
 308         .maps[RCAMO] = REG_CAMREAD,
 309         .maps[CAMDBG] = REG_CAMDBG,
 310         .maps[SECR] = REG_SECCFG,
 311         .maps[SEC_CAM_NONE] = CAM_NONE,
 312         .maps[SEC_CAM_WEP40] = CAM_WEP40,
 313         .maps[SEC_CAM_TKIP] = CAM_TKIP,
 314         .maps[SEC_CAM_AES] = CAM_AES,
 315         .maps[SEC_CAM_WEP104] = CAM_WEP104,
 316
 317         .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
 318         .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
 319         .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
 320         .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
 321         .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
 322         .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
 323 /*      .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,     */   /*need check*/
 324         .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
 325         .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
 326         .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
 327         .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
 328         .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
 329         .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
 330         .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
 331 /*      .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,*/
 332 /*      .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,*/
 333
 334         .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
 335         .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
 336         .maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,
 337         .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
 338         .maps[RTL_IMR_RDU] = IMR_RDU,
 339         .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
 340         .maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
 341         .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
 342         .maps[RTL_IMR_TBDER] = IMR_TBDER,
 343         .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
 344         .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
 345         .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
 346         .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
 347         .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
 348         .maps[RTL_IMR_VODOK] = IMR_VODOK,
 349         .maps[RTL_IMR_ROK] = IMR_ROK,
 350         .maps[RTL_IMR_HSISR_IND] = IMR_HSISR_IND_ON_INT,
 351         .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
 352
 353         .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
 354         .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
 355         .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
 356         .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
 357         .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
 358         .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
 359         .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
 360         .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
 361         .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
 362         .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
 363         .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
 364         .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
 365
 366         .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
 367         .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
 368 };
 369
 370 static struct pci_device_id rtl8723be_pci_ids[] = {
 371         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0xB723, rtl8723be_hal_cfg)},
 372         {},
 373 };
 374
 375 MODULE_DEVICE_TABLE(pci, rtl8723be_pci_ids);
 376
 377 MODULE_AUTHOR("PageHe   <page_he@realsil.com.cn>");
 378 MODULE_AUTHOR("Realtek WlanFAE  <wlanfae@realtek.com>");
 379 MODULE_LICENSE("GPL");
 380 MODULE_DESCRIPTION("Realtek 8723BE 802.11n PCI wireless");
 381 MODULE_FIRMWARE("rtlwifi/rtl8723befw.bin");
 382
 383 module_param_named(swenc, rtl8723be_mod_params.sw_crypto, bool, 0444);
 384 module_param_named(debug, rtl8723be_mod_params.debug, int, 0444);
 385 module_param_named(ips, rtl8723be_mod_params.inactiveps, bool, 0444);
 386 module_param_named(swlps, rtl8723be_mod_params.swctrl_lps, bool, 0444);
 387 module_param_named(fwlps, rtl8723be_mod_params.fwctrl_lps, bool, 0444);
 388 module_param_named(msi, rtl8723be_mod_params.msi_support, bool, 0444);
 389 module_param_named(disable_watchdog, rtl8723be_mod_params.disable_watchdog,
 390                    bool, 0444);
 391 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
 392 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
 393 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
 394 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
 395 MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 0)\n");
 396 MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
 397 MODULE_PARM_DESC(disable_watchdog,
 398                  "Set to 1 to disable the watchdog (default 0)\n");
 399
 400 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
 401
 402 static struct pci_driver rtl8723be_driver = {
 403         .name = KBUILD_MODNAME,
 404         .id_table = rtl8723be_pci_ids,
 405         .probe = rtl_pci_probe,
 406         .remove = rtl_pci_disconnect,
 407         .driver.pm = &rtlwifi_pm_ops,
 408 };
 409
 410 module_pci_driver(rtl8723be_driver);