drivers/net/wireless/rtlwifi/rtl8192ee/dm.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2014  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #ifndef __RTL92E_DM_H__
  27 #define __RTL92E_DM_H__
  28
  29 #define OFDMCCA_TH                              500
  30 #define BW_IND_BIAS                             500
  31 #define MF_USC                                  2
  32 #define MF_LSC                                  1
  33 #define MF_USC_LSC                              0
  34 #define MONITOR_TIME                            30
  35
  36 #define MAIN_ANT                                0
  37 #define AUX_ANT                                 1
  38 #define MAIN_ANT_CG_TRX                         1
  39 #define AUX_ANT_CG_TRX                          0
  40 #define MAIN_ANT_CGCS_RX                        0
  41 #define AUX_ANT_CGCS_RX                         1
  42
  43 /*RF REG LIST*/
  44 #define DM_REG_RF_MODE_11N                      0x00
  45 #define DM_REG_RF_0B_11N                        0x0B
  46 #define DM_REG_CHNBW_11N                        0x18
  47 #define DM_REG_T_METER_11N                      0x24
  48 #define DM_REG_RF_25_11N                        0x25
  49 #define DM_REG_RF_26_11N                        0x26
  50 #define DM_REG_RF_27_11N                        0x27
  51 #define DM_REG_RF_2B_11N                        0x2B
  52 #define DM_REG_RF_2C_11N                        0x2C
  53 #define DM_REG_RXRF_A3_11N                      0x3C
  54 #define DM_REG_T_METER_92D_11N                  0x42
  55 #define DM_REG_T_METER_92E_11N                  0x42
  56
  57 /*BB REG LIST*/
  58 /*PAGE 8 */
  59 #define DM_REG_BB_CTRL_11N                      0x800
  60 #define DM_REG_RF_PIN_11N                       0x804
  61 #define DM_REG_PSD_CTRL_11N                     0x808
  62 #define DM_REG_TX_ANT_CTRL_11N                  0x80C
  63 #define DM_REG_BB_PWR_SAV5_11N                  0x818
  64 #define DM_REG_CCK_RPT_FORMAT_11N               0x824
  65 #define DM_REG_RX_DEFUALT_A_11N                 0x858
  66 #define DM_REG_RX_DEFUALT_B_11N                 0x85A
  67 #define DM_REG_BB_PWR_SAV3_11N                  0x85C
  68 #define DM_REG_ANTSEL_CTRL_11N                  0x860
  69 #define DM_REG_RX_ANT_CTRL_11N                  0x864
  70 #define DM_REG_PIN_CTRL_11N                     0x870
  71 #define DM_REG_BB_PWR_SAV1_11N                  0x874
  72 #define DM_REG_ANTSEL_PATH_11N                  0x878
  73 #define DM_REG_BB_3WIRE_11N                     0x88C
  74 #define DM_REG_SC_CNT_11N                       0x8C4
  75 #define DM_REG_PSD_DATA_11N                     0x8B4
  76 /*PAGE 9*/
  77 #define DM_REG_ANT_MAPPING1_11N                 0x914
  78 #define DM_REG_ANT_MAPPING2_11N                 0x918
  79 /*PAGE A*/
  80 #define DM_REG_CCK_ANTDIV_PARA1_11N             0xA00
  81 #define DM_REG_CCK_CCA_11N                      0xA0A
  82 #define DM_REG_CCK_ANTDIV_PARA2_11N             0xA0C
  83 #define DM_REG_CCK_ANTDIV_PARA3_11N             0xA10
  84 #define DM_REG_CCK_ANTDIV_PARA4_11N             0xA14
  85 #define DM_REG_CCK_FILTER_PARA1_11N             0xA22
  86 #define DM_REG_CCK_FILTER_PARA2_11N             0xA23
  87 #define DM_REG_CCK_FILTER_PARA3_11N             0xA24
  88 #define DM_REG_CCK_FILTER_PARA4_11N             0xA25
  89 #define DM_REG_CCK_FILTER_PARA5_11N             0xA26
  90 #define DM_REG_CCK_FILTER_PARA6_11N             0xA27
  91 #define DM_REG_CCK_FILTER_PARA7_11N             0xA28
  92 #define DM_REG_CCK_FILTER_PARA8_11N             0xA29
  93 #define DM_REG_CCK_FA_RST_11N                   0xA2C
  94 #define DM_REG_CCK_FA_MSB_11N                   0xA58
  95 #define DM_REG_CCK_FA_LSB_11N                   0xA5C
  96 #define DM_REG_CCK_CCA_CNT_11N                  0xA60
  97 #define DM_REG_BB_PWR_SAV4_11N                  0xA74
  98 /*PAGE B */
  99 #define DM_REG_LNA_SWITCH_11N                   0xB2C
 100 #define DM_REG_PATH_SWITCH_11N                  0xB30
 101 #define DM_REG_RSSI_CTRL_11N                    0xB38
 102 #define DM_REG_CONFIG_ANTA_11N                  0xB68
 103 #define DM_REG_RSSI_BT_11N                      0xB9C
 104 /*PAGE C */
 105 #define DM_REG_OFDM_FA_HOLDC_11N                0xC00
 106 #define DM_REG_RX_PATH_11N                      0xC04
 107 #define DM_REG_TRMUX_11N                        0xC08
 108 #define DM_REG_OFDM_FA_RSTC_11N                 0xC0C
 109 #define DM_REG_RXIQI_MATRIX_11N                 0xC14
 110 #define DM_REG_TXIQK_MATRIX_LSB1_11N            0xC4C
 111 #define DM_REG_IGI_A_11N                        0xC50
 112 #define DM_REG_ANTDIV_PARA2_11N                 0xC54
 113 #define DM_REG_IGI_B_11N                        0xC58
 114 #define DM_REG_ANTDIV_PARA3_11N                 0xC5C
 115 #define DM_REG_L1SBD_PD_CH_11N                  0XC6C
 116 #define DM_REG_BB_PWR_SAV2_11N                  0xC70
 117 #define DM_REG_RX_OFF_11N                       0xC7C
 118 #define DM_REG_TXIQK_MATRIXA_11N                0xC80
 119 #define DM_REG_TXIQK_MATRIXB_11N                0xC88
 120 #define DM_REG_TXIQK_MATRIXA_LSB2_11N           0xC94
 121 #define DM_REG_TXIQK_MATRIXB_LSB2_11N           0xC9C
 122 #define DM_REG_RXIQK_MATRIX_LSB_11N             0xCA0
 123 #define DM_REG_ANTDIV_PARA1_11N                 0xCA4
 124 #define DM_REG_OFDM_FA_TYPE1_11N                0xCF0
 125 /*PAGE D */
 126 #define DM_REG_OFDM_FA_RSTD_11N                 0xD00
 127 #define DM_REG_OFDM_FA_TYPE2_11N                0xDA0
 128 #define DM_REG_OFDM_FA_TYPE3_11N                0xDA4
 129 #define DM_REG_OFDM_FA_TYPE4_11N                0xDA8
 130 /*PAGE E */
 131 #define DM_REG_TXAGC_A_6_18_11N                 0xE00
 132 #define DM_REG_TXAGC_A_24_54_11N                0xE04
 133 #define DM_REG_TXAGC_A_1_MCS32_11N              0xE08
 134 #define DM_REG_TXAGC_A_MCS0_3_11N               0xE10
 135 #define DM_REG_TXAGC_A_MCS4_7_11N               0xE14
 136 #define DM_REG_TXAGC_A_MCS8_11_11N              0xE18
 137 #define DM_REG_TXAGC_A_MCS12_15_11N             0xE1C
 138 #define DM_REG_FPGA0_IQK_11N                    0xE28
 139 #define DM_REG_TXIQK_TONE_A_11N                 0xE30
 140 #define DM_REG_RXIQK_TONE_A_11N                 0xE34
 141 #define DM_REG_TXIQK_PI_A_11N                   0xE38
 142 #define DM_REG_RXIQK_PI_A_11N                   0xE3C
 143 #define DM_REG_TXIQK_11N                        0xE40
 144 #define DM_REG_RXIQK_11N                        0xE44
 145 #define DM_REG_IQK_AGC_PTS_11N                  0xE48
 146 #define DM_REG_IQK_AGC_RSP_11N                  0xE4C
 147 #define DM_REG_BLUETOOTH_11N                    0xE6C
 148 #define DM_REG_RX_WAIT_CCA_11N                  0xE70
 149 #define DM_REG_TX_CCK_RFON_11N                  0xE74
 150 #define DM_REG_TX_CCK_BBON_11N                  0xE78
 151 #define DM_REG_OFDM_RFON_11N                    0xE7C
 152 #define DM_REG_OFDM_BBON_11N                    0xE80
 153 #define         DM_REG_TX2RX_11N                0xE84
 154 #define DM_REG_TX2TX_11N                        0xE88
 155 #define DM_REG_RX_CCK_11N                       0xE8C
 156 #define DM_REG_RX_OFDM_11N                      0xED0
 157 #define DM_REG_RX_WAIT_RIFS_11N                 0xED4
 158 #define DM_REG_RX2RX_11N                        0xED8
 159 #define DM_REG_STANDBY_11N                      0xEDC
 160 #define DM_REG_SLEEP_11N                        0xEE0
 161 #define DM_REG_PMPD_ANAEN_11N                   0xEEC
 162
 163 /*MAC REG LIST*/
 164 #define DM_REG_BB_RST_11N                       0x02
 165 #define DM_REG_ANTSEL_PIN_11N                   0x4C
 166 #define DM_REG_EARLY_MODE_11N                   0x4D0
 167 #define DM_REG_RSSI_MONITOR_11N                 0x4FE
 168 #define DM_REG_EDCA_VO_11N                      0x500
 169 #define DM_REG_EDCA_VI_11N                      0x504
 170 #define DM_REG_EDCA_BE_11N                      0x508
 171 #define DM_REG_EDCA_BK_11N                      0x50C
 172 #define DM_REG_TXPAUSE_11N                      0x522
 173 #define DM_REG_RESP_TX_11N                      0x6D8
 174 #define DM_REG_ANT_TRAIN_PARA1_11N              0x7b0
 175 #define DM_REG_ANT_TRAIN_PARA2_11N              0x7b4
 176
 177 /*DIG Related*/
 178 #define DM_BIT_IGI_11N                          0x0000007F
 179
 180 #define HAL_DM_DIG_DISABLE                      BIT(0)
 181 #define HAL_DM_HIPWR_DISABLE                    BIT(1)
 182
 183 #define OFDM_TABLE_LENGTH                       43
 184 #define CCK_TABLE_LENGTH                        33
 185
 186 #define OFDM_TABLE_SIZE                         43
 187 #define CCK_TABLE_SIZE                          33
 188
 189 #define BW_AUTO_SWITCH_HIGH_LOW                 25
 190 #define BW_AUTO_SWITCH_LOW_HIGH                 30
 191
 192 #define DM_DIG_FA_UPPER                         0x3e
 193 #define DM_DIG_FA_LOWER                         0x1e
 194 #define DM_DIG_FA_TH0                           0x200
 195 #define DM_DIG_FA_TH1                           0x300
 196 #define DM_DIG_FA_TH2                           0x400
 197
 198 #define RXPATHSELECTION_SS_TH_LOW               30
 199 #define RXPATHSELECTION_DIFF_TH                 18
 200
 201 #define DM_RATR_STA_INIT                        0
 202 #define DM_RATR_STA_HIGH                        1
 203 #define DM_RATR_STA_MIDDLE                      2
 204 #define DM_RATR_STA_LOW                         3
 205
 206 #define CTS2SELF_THVAL                          30
 207 #define REGC38_TH                               20
 208
 209 #define WAIOTTHVAL                              25
 210
 211 #define TXHIGHPWRLEVEL_NORMAL                   0
 212 #define TXHIGHPWRLEVEL_LEVEL1                   1
 213 #define TXHIGHPWRLEVEL_LEVEL2                   2
 214 #define TXHIGHPWRLEVEL_BT1                      3
 215 #define TXHIGHPWRLEVEL_BT2                      4
 216
 217 #define DM_TYPE_BYFW                            0
 218 #define DM_TYPE_BYDRIVER                        1
 219
 220 #define TX_POWER_NEAR_FIELD_THRESH_LVL2         74
 221 #define TX_POWER_NEAR_FIELD_THRESH_LVL1         67
 222 #define TXPWRTRACK_MAX_IDX                      6
 223
 224 /* Dynamic ATC switch */
 225 #define ATC_STATUS_OFF                          0x0     /* enable */
 226 #define ATC_STATUS_ON                           0x1     /* disable */
 227 #define CFO_THRESHOLD_XTAL                      10      /* kHz */
 228 #define CFO_THRESHOLD_ATC                       80      /* kHz */
 229
 230 /* RSSI Dump Message */
 231 #define RA_RSSIDUMP                             0xcb0
 232 #define RB_RSSIDUMP                             0xcb1
 233 #define RS1_RXEVMDUMP                           0xcb2
 234 #define RS2_RXEVMDUMP                           0xcb3
 235 #define RA_RXSNRDUMP                            0xcb4
 236 #define RB_RXSNRDUMP                            0xcb5
 237 #define RA_CFOSHORTDUMP                         0xcb6
 238 #define RB_CFOSHORTDUMP                         0xcb8
 239 #define RA_CFOLONGDUMP                          0xcba
 240 #define RB_CFOLONGDUMP                          0xcbc
 241
 242 void rtl92ee_dm_init(struct ieee80211_hw *hw);
 243 void rtl92ee_dm_watchdog(struct ieee80211_hw *hw);
 244 void rtl92ee_dm_write_cck_cca_thres(struct ieee80211_hw *hw,
 245                                     u8 cur_thres);
 246 void rtl92ee_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi);
 247 void rtl92ee_dm_init_edca_turbo(struct ieee80211_hw *hw);
 248 void rtl92ee_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
 249 void rtl92ee_dm_dynamic_arfb_select(struct ieee80211_hw *hw,
 250                                     u8 rate, bool collision_state);
 251 #endif