drivers/net/wireless/rtlwifi/rtl8821ae/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../efuse.h"
  28 #include "../base.h"
  29 #include "../regd.h"
  30 #include "../cam.h"
  31 #include "../ps.h"
  32 #include "../pci.h"
  33 #include "reg.h"
  34 #include "def.h"
  35 #include "phy.h"
  36 #include "dm.h"
  37 #include "fw.h"
  38 #include "led.h"
  39 #include "hw.h"
  40 #include "../pwrseqcmd.h"
  41 #include "pwrseq.h"
  42 #include "../btcoexist/rtl_btc.h"
  43
  44 #define LLT_CONFIG      5
  45
  46 static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw)
  47 {
  48         struct rtl_priv *rtlpriv = rtl_priv(hw);
  49         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  50         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
  51         unsigned long flags;
  52
  53         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  54         while (skb_queue_len(&ring->queue)) {
  55                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
  56                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
  57
  58                 pci_unmap_single(rtlpci->pdev,
  59                                  rtlpriv->cfg->ops->get_desc(
  60                                  (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
  61                                  skb->len, PCI_DMA_TODEVICE);
  62                 kfree_skb(skb);
  63                 ring->idx = (ring->idx + 1) % ring->entries;
  64         }
  65         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
  66 }
  67
  68 static void _rtl8821ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  69                                         u8 set_bits, u8 clear_bits)
  70 {
  71         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  72         struct rtl_priv *rtlpriv = rtl_priv(hw);
  73
  74         rtlpci->reg_bcn_ctrl_val |= set_bits;
  75         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  76
  77         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
  78 }
  79
  80 void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw)
  81 {
  82         struct rtl_priv *rtlpriv = rtl_priv(hw);
  83         u8 tmp1byte;
  84
  85         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  86         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  87         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  88         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  89         tmp1byte &= ~(BIT(0));
  90         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  91 }
  92
  93 void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw)
  94 {
  95         struct rtl_priv *rtlpriv = rtl_priv(hw);
  96         u8 tmp1byte;
  97
  98         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  99         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
 100         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 101         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
 102         tmp1byte |= BIT(0);
 103         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
 104 }
 105
 106 static void _rtl8821ae_enable_bcn_sub_func(struct ieee80211_hw *hw)
 107 {
 108         _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(1));
 109 }
 110
 111 static void _rtl8821ae_disable_bcn_sub_func(struct ieee80211_hw *hw)
 112 {
 113         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(1), 0);
 114 }
 115
 116 static void _rtl8821ae_set_fw_clock_on(struct ieee80211_hw *hw,
 117                                        u8 rpwm_val, bool b_need_turn_off_ckk)
 118 {
 119         struct rtl_priv *rtlpriv = rtl_priv(hw);
 120         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 121         bool b_support_remote_wake_up;
 122         u32 count = 0, isr_regaddr, content;
 123         bool b_schedule_timer = b_need_turn_off_ckk;
 124
 125         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
 126                                         (u8 *)(&b_support_remote_wake_up));
 127
 128         if (!rtlhal->fw_ready)
 129                 return;
 130         if (!rtlpriv->psc.fw_current_inpsmode)
 131                 return;
 132
 133         while (1) {
 134                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 135                 if (rtlhal->fw_clk_change_in_progress) {
 136                         while (rtlhal->fw_clk_change_in_progress) {
 137                                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 138                                 count++;
 139                                 udelay(100);
 140                                 if (count > 1000)
 141                                         goto change_done;
 142                                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 143                         }
 144                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 145                 } else {
 146                         rtlhal->fw_clk_change_in_progress = false;
 147                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 148                         goto change_done;
 149                 }
 150         }
 151 change_done:
 152         if (IS_IN_LOW_POWER_STATE_8821AE(rtlhal->fw_ps_state)) {
 153                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
 154                                         (u8 *)(&rpwm_val));
 155                 if (FW_PS_IS_ACK(rpwm_val)) {
 156                         isr_regaddr = REG_HISR;
 157                         content = rtl_read_dword(rtlpriv, isr_regaddr);
 158                         while (!(content & IMR_CPWM) && (count < 500)) {
 159                                 udelay(50);
 160                                 count++;
 161                                 content = rtl_read_dword(rtlpriv, isr_regaddr);
 162                         }
 163
 164                         if (content & IMR_CPWM) {
 165                                 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
 166                                 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8821AE;
 167                                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 168                                          "Receive CPWM INT!!! Set rtlhal->FwPSState = %X\n",
 169                                          rtlhal->fw_ps_state);
 170                         }
 171                 }
 172
 173                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 174                 rtlhal->fw_clk_change_in_progress = false;
 175                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 176                 if (b_schedule_timer)
 177                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 178                                   jiffies + MSECS(10));
 179         } else  {
 180                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 181                 rtlhal->fw_clk_change_in_progress = false;
 182                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 183         }
 184 }
 185
 186 static void _rtl8821ae_set_fw_clock_off(struct ieee80211_hw *hw,
 187                                         u8 rpwm_val)
 188 {
 189         struct rtl_priv *rtlpriv = rtl_priv(hw);
 190         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 191         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 192         struct rtl8192_tx_ring *ring;
 193         enum rf_pwrstate rtstate;
 194         bool b_schedule_timer = false;
 195         u8 queue;
 196
 197         if (!rtlhal->fw_ready)
 198                 return;
 199         if (!rtlpriv->psc.fw_current_inpsmode)
 200                 return;
 201         if (!rtlhal->allow_sw_to_change_hwclc)
 202                 return;
 203         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
 204         if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
 205                 return;
 206
 207         for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
 208                 ring = &rtlpci->tx_ring[queue];
 209                 if (skb_queue_len(&ring->queue)) {
 210                         b_schedule_timer = true;
 211                         break;
 212                 }
 213         }
 214
 215         if (b_schedule_timer) {
 216                 mod_timer(&rtlpriv->works.fw_clockoff_timer,
 217                           jiffies + MSECS(10));
 218                 return;
 219         }
 220
 221         if (FW_PS_STATE(rtlhal->fw_ps_state) !=
 222                 FW_PS_STATE_RF_OFF_LOW_PWR_8821AE) {
 223                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 224                 if (!rtlhal->fw_clk_change_in_progress) {
 225                         rtlhal->fw_clk_change_in_progress = true;
 226                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 227                         rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
 228                         rtl_write_word(rtlpriv, REG_HISR, 0x0100);
 229                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 230                                                       (u8 *)(&rpwm_val));
 231                         spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 232                         rtlhal->fw_clk_change_in_progress = false;
 233                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 234                 } else {
 235                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 236                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 237                                   jiffies + MSECS(10));
 238                 }
 239         }
 240 }
 241
 242 static void _rtl8821ae_set_fw_ps_rf_on(struct ieee80211_hw *hw)
 243 {
 244         u8 rpwm_val = 0;
 245
 246         rpwm_val |= (FW_PS_STATE_RF_OFF_8821AE | FW_PS_ACK);
 247         _rtl8821ae_set_fw_clock_on(hw, rpwm_val, true);
 248 }
 249
 250 static void _rtl8821ae_fwlps_leave(struct ieee80211_hw *hw)
 251 {
 252         struct rtl_priv *rtlpriv = rtl_priv(hw);
 253         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 254         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 255         bool fw_current_inps = false;
 256         u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
 257
 258         if (ppsc->low_power_enable) {
 259                 rpwm_val = (FW_PS_STATE_ALL_ON_8821AE|FW_PS_ACK);/* RF on */
 260                 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, false);
 261                 rtlhal->allow_sw_to_change_hwclc = false;
 262                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 263                                 (u8 *)(&fw_pwrmode));
 264                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 265                                 (u8 *)(&fw_current_inps));
 266         } else {
 267                 rpwm_val = FW_PS_STATE_ALL_ON_8821AE;   /* RF on */
 268                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 269                                 (u8 *)(&rpwm_val));
 270                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 271                                 (u8 *)(&fw_pwrmode));
 272                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 273                                 (u8 *)(&fw_current_inps));
 274         }
 275 }
 276
 277 static void _rtl8821ae_fwlps_enter(struct ieee80211_hw *hw)
 278 {
 279         struct rtl_priv *rtlpriv = rtl_priv(hw);
 280         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 281         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 282         bool fw_current_inps = true;
 283         u8 rpwm_val;
 284
 285         if (ppsc->low_power_enable) {
 286                 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_8821AE;   /* RF off */
 287                 rtlpriv->cfg->ops->set_hw_reg(hw,
 288                                 HW_VAR_FW_PSMODE_STATUS,
 289                                 (u8 *)(&fw_current_inps));
 290                 rtlpriv->cfg->ops->set_hw_reg(hw,
 291                                 HW_VAR_H2C_FW_PWRMODE,
 292                                 (u8 *)(&ppsc->fwctrl_psmode));
 293                 rtlhal->allow_sw_to_change_hwclc = true;
 294                 _rtl8821ae_set_fw_clock_off(hw, rpwm_val);
 295         } else {
 296                 rpwm_val = FW_PS_STATE_RF_OFF_8821AE;   /* RF off */
 297                 rtlpriv->cfg->ops->set_hw_reg(hw,
 298                                 HW_VAR_FW_PSMODE_STATUS,
 299                                 (u8 *)(&fw_current_inps));
 300                 rtlpriv->cfg->ops->set_hw_reg(hw,
 301                                 HW_VAR_H2C_FW_PWRMODE,
 302                                 (u8 *)(&ppsc->fwctrl_psmode));
 303                 rtlpriv->cfg->ops->set_hw_reg(hw,
 304                                 HW_VAR_SET_RPWM,
 305                                 (u8 *)(&rpwm_val));
 306         }
 307 }
 308
 309 static void _rtl8821ae_download_rsvd_page(struct ieee80211_hw *hw,
 310                                           bool dl_whole_packets)
 311 {
 312         struct rtl_priv *rtlpriv = rtl_priv(hw);
 313         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
 314         u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
 315         u8 count = 0, dlbcn_count = 0;
 316         bool send_beacon = false;
 317
 318         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 319         rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr | BIT(0)));
 320
 321         _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
 322         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
 323
 324         tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
 325         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 326                        tmp_reg422 & (~BIT(6)));
 327         if (tmp_reg422 & BIT(6))
 328                 send_beacon = true;
 329
 330         do {
 331                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
 332                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
 333                                (bcnvalid_reg | BIT(0)));
 334                 _rtl8821ae_return_beacon_queue_skb(hw);
 335
 336                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 337                         rtl8812ae_set_fw_rsvdpagepkt(hw, false,
 338                                                      dl_whole_packets);
 339                 else
 340                         rtl8821ae_set_fw_rsvdpagepkt(hw, false,
 341                                                      dl_whole_packets);
 342
 343                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
 344                 count = 0;
 345                 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
 346                         count++;
 347                         udelay(10);
 348                         bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
 349                 }
 350                 dlbcn_count++;
 351         } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
 352
 353         if (!(bcnvalid_reg & BIT(0)))
 354                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 355                          "Download RSVD page failed!\n");
 356         if (bcnvalid_reg & BIT(0) && rtlhal->enter_pnp_sleep) {
 357                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, bcnvalid_reg | BIT(0));
 358                 _rtl8821ae_return_beacon_queue_skb(hw);
 359                 if (send_beacon) {
 360                         dlbcn_count = 0;
 361                         do {
 362                                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
 363                                                bcnvalid_reg | BIT(0));
 364
 365                                 _rtl8821ae_return_beacon_queue_skb(hw);
 366
 367                                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 368                                         rtl8812ae_set_fw_rsvdpagepkt(hw, true,
 369                                                                      false);
 370                                 else
 371                                         rtl8821ae_set_fw_rsvdpagepkt(hw, true,
 372                                                                      false);
 373
 374                                 /* check rsvd page download OK. */
 375                                 bcnvalid_reg = rtl_read_byte(rtlpriv,
 376                                                              REG_TDECTRL + 2);
 377                                 count = 0;
 378                                 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
 379                                         count++;
 380                                         udelay(10);
 381                                         bcnvalid_reg =
 382                                           rtl_read_byte(rtlpriv,
 383                                                         REG_TDECTRL + 2);
 384                                 }
 385                                 dlbcn_count++;
 386                         } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
 387
 388                         if (!(bcnvalid_reg & BIT(0)))
 389                                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 390                                          "2 Download RSVD page failed!\n");
 391                 }
 392         }
 393
 394         if (bcnvalid_reg & BIT(0))
 395                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0));
 396
 397         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
 398         _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
 399
 400         if (send_beacon)
 401                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
 402
 403         if (!rtlhal->enter_pnp_sleep) {
 404                 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 405                 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0))));
 406         }
 407 }
 408
 409 void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 410 {
 411         struct rtl_priv *rtlpriv = rtl_priv(hw);
 412         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 413         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 414         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 415
 416         switch (variable) {
 417         case HW_VAR_ETHER_ADDR:
 418                 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_MACID);
 419                 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_MACID + 4);
 420                 break;
 421         case HW_VAR_BSSID:
 422                 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_BSSID);
 423                 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_BSSID+4);
 424                 break;
 425         case HW_VAR_MEDIA_STATUS:
 426                 val[0] = rtl_read_byte(rtlpriv, MSR) & 0x3;
 427                 break;
 428         case HW_VAR_SLOT_TIME:
 429                 *((u8 *)(val)) = mac->slot_time;
 430                 break;
 431         case HW_VAR_BEACON_INTERVAL:
 432                 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_BCN_INTERVAL);
 433                 break;
 434         case HW_VAR_ATIM_WINDOW:
 435                 *((u16 *)(val)) =  rtl_read_word(rtlpriv, REG_ATIMWND);
 436                 break;
 437         case HW_VAR_RCR:
 438                 *((u32 *)(val)) = rtlpci->receive_config;
 439                 break;
 440         case HW_VAR_RF_STATE:
 441                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 442                 break;
 443         case HW_VAR_FWLPS_RF_ON:{
 444                 enum rf_pwrstate rfstate;
 445                 u32 val_rcr;
 446
 447                 rtlpriv->cfg->ops->get_hw_reg(hw,
 448                                               HW_VAR_RF_STATE,
 449                                               (u8 *)(&rfstate));
 450                 if (rfstate == ERFOFF) {
 451                         *((bool *)(val)) = true;
 452                 } else {
 453                         val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 454                         val_rcr &= 0x00070000;
 455                         if (val_rcr)
 456                                 *((bool *)(val)) = false;
 457                         else
 458                                 *((bool *)(val)) = true;
 459                 }
 460                 break; }
 461         case HW_VAR_FW_PSMODE_STATUS:
 462                 *((bool *)(val)) = ppsc->fw_current_inpsmode;
 463                 break;
 464         case HW_VAR_CORRECT_TSF:{
 465                 u64 tsf;
 466                 u32 *ptsf_low = (u32 *)&tsf;
 467                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 468
 469                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 470                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 471
 472                 *((u64 *)(val)) = tsf;
 473
 474                 break; }
 475         case HAL_DEF_WOWLAN:
 476                 if (ppsc->wo_wlan_mode)
 477                         *((bool *)(val)) = true;
 478                 else
 479                         *((bool *)(val)) = false;
 480                 break;
 481         default:
 482                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 483                          "switch case not process %x\n", variable);
 484                 break;
 485         }
 486 }
 487
 488 void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 489 {
 490         struct rtl_priv *rtlpriv = rtl_priv(hw);
 491         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 492         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 493         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 494         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 495         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 496         u8 idx;
 497
 498         switch (variable) {
 499         case HW_VAR_ETHER_ADDR:{
 500                         for (idx = 0; idx < ETH_ALEN; idx++) {
 501                                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
 502                                                val[idx]);
 503                         }
 504                         break;
 505                 }
 506         case HW_VAR_BASIC_RATE:{
 507                         u16 b_rate_cfg = ((u16 *)val)[0];
 508                         b_rate_cfg = b_rate_cfg & 0x15f;
 509                         rtl_write_word(rtlpriv, REG_RRSR, b_rate_cfg);
 510                         break;
 511                 }
 512         case HW_VAR_BSSID:{
 513                         for (idx = 0; idx < ETH_ALEN; idx++) {
 514                                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
 515                                                val[idx]);
 516                         }
 517                         break;
 518                 }
 519         case HW_VAR_SIFS:
 520                 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 521                 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[0]);
 522
 523                 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 524                 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 525
 526                 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
 527                 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM, val[0]);
 528                 break;
 529         case HW_VAR_R2T_SIFS:
 530                 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
 531                 break;
 532         case HW_VAR_SLOT_TIME:{
 533                 u8 e_aci;
 534
 535                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 536                          "HW_VAR_SLOT_TIME %x\n", val[0]);
 537
 538                 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 539
 540                 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 541                         rtlpriv->cfg->ops->set_hw_reg(hw,
 542                                                       HW_VAR_AC_PARAM,
 543                                                       (u8 *)(&e_aci));
 544                 }
 545                 break; }
 546         case HW_VAR_ACK_PREAMBLE:{
 547                 u8 reg_tmp;
 548                 u8 short_preamble = (bool)(*(u8 *)val);
 549
 550                 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
 551                 if (short_preamble) {
 552                         reg_tmp |= BIT(1);
 553                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2,
 554                                        reg_tmp);
 555                 } else {
 556                         reg_tmp &= (~BIT(1));
 557                         rtl_write_byte(rtlpriv,
 558                                 REG_TRXPTCL_CTL + 2,
 559                                 reg_tmp);
 560                 }
 561                 break; }
 562         case HW_VAR_WPA_CONFIG:
 563                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
 564                 break;
 565         case HW_VAR_AMPDU_MIN_SPACE:{
 566                 u8 min_spacing_to_set;
 567                 u8 sec_min_space;
 568
 569                 min_spacing_to_set = *((u8 *)val);
 570                 if (min_spacing_to_set <= 7) {
 571                         sec_min_space = 0;
 572
 573                         if (min_spacing_to_set < sec_min_space)
 574                                 min_spacing_to_set = sec_min_space;
 575
 576                         mac->min_space_cfg = ((mac->min_space_cfg &
 577                                                0xf8) |
 578                                               min_spacing_to_set);
 579
 580                         *val = min_spacing_to_set;
 581
 582                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 583                                  "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 584                                   mac->min_space_cfg);
 585
 586                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 587                                        mac->min_space_cfg);
 588                 }
 589                 break; }
 590         case HW_VAR_SHORTGI_DENSITY:{
 591                 u8 density_to_set;
 592
 593                 density_to_set = *((u8 *)val);
 594                 mac->min_space_cfg |= (density_to_set << 3);
 595
 596                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 597                          "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 598                           mac->min_space_cfg);
 599
 600                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 601                                mac->min_space_cfg);
 602
 603                 break; }
 604         case HW_VAR_AMPDU_FACTOR:{
 605                 u32     ampdu_len =  (*((u8 *)val));
 606
 607                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
 608                         if (ampdu_len < VHT_AGG_SIZE_128K)
 609                                 ampdu_len =
 610                                         (0x2000 << (*((u8 *)val))) - 1;
 611                         else
 612                                 ampdu_len = 0x1ffff;
 613                 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
 614                         if (ampdu_len < HT_AGG_SIZE_64K)
 615                                 ampdu_len =
 616                                         (0x2000 << (*((u8 *)val))) - 1;
 617                         else
 618                                 ampdu_len = 0xffff;
 619                 }
 620                 ampdu_len |= BIT(31);
 621
 622                 rtl_write_dword(rtlpriv,
 623                         REG_AMPDU_MAX_LENGTH_8812, ampdu_len);
 624                 break; }
 625         case HW_VAR_AC_PARAM:{
 626                 u8 e_aci = *((u8 *)val);
 627
 628                 rtl8821ae_dm_init_edca_turbo(hw);
 629                 if (rtlpci->acm_method != EACMWAY2_SW)
 630                         rtlpriv->cfg->ops->set_hw_reg(hw,
 631                                                       HW_VAR_ACM_CTRL,
 632                                                       (u8 *)(&e_aci));
 633                 break; }
 634         case HW_VAR_ACM_CTRL:{
 635                 u8 e_aci = *((u8 *)val);
 636                 union aci_aifsn *p_aci_aifsn =
 637                     (union aci_aifsn *)(&mac->ac[0].aifs);
 638                 u8 acm = p_aci_aifsn->f.acm;
 639                 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 640
 641                 acm_ctrl =
 642                     acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 643
 644                 if (acm) {
 645                         switch (e_aci) {
 646                         case AC0_BE:
 647                                 acm_ctrl |= ACMHW_BEQEN;
 648                                 break;
 649                         case AC2_VI:
 650                                 acm_ctrl |= ACMHW_VIQEN;
 651                                 break;
 652                         case AC3_VO:
 653                                 acm_ctrl |= ACMHW_VOQEN;
 654                                 break;
 655                         default:
 656                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 657                                          "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 658                                          acm);
 659                                 break;
 660                         }
 661                 } else {
 662                         switch (e_aci) {
 663                         case AC0_BE:
 664                                 acm_ctrl &= (~ACMHW_BEQEN);
 665                                 break;
 666                         case AC2_VI:
 667                                 acm_ctrl &= (~ACMHW_VIQEN);
 668                                 break;
 669                         case AC3_VO:
 670                                 acm_ctrl &= (~ACMHW_VOQEN);
 671                                 break;
 672                         default:
 673                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 674                                          "switch case not process\n");
 675                                 break;
 676                         }
 677                 }
 678
 679                 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 680                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 681                          acm_ctrl);
 682                 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 683                 break; }
 684         case HW_VAR_RCR:
 685                 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
 686                 rtlpci->receive_config = ((u32 *)(val))[0];
 687                 break;
 688         case HW_VAR_RETRY_LIMIT:{
 689                 u8 retry_limit = ((u8 *)(val))[0];
 690
 691                 rtl_write_word(rtlpriv, REG_RL,
 692                                retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 693                                retry_limit << RETRY_LIMIT_LONG_SHIFT);
 694                 break; }
 695         case HW_VAR_DUAL_TSF_RST:
 696                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 697                 break;
 698         case HW_VAR_EFUSE_BYTES:
 699                 rtlefuse->efuse_usedbytes = *((u16 *)val);
 700                 break;
 701         case HW_VAR_EFUSE_USAGE:
 702                 rtlefuse->efuse_usedpercentage = *((u8 *)val);
 703                 break;
 704         case HW_VAR_IO_CMD:
 705                 rtl8821ae_phy_set_io_cmd(hw, (*(enum io_type *)val));
 706                 break;
 707         case HW_VAR_SET_RPWM:{
 708                 u8 rpwm_val;
 709
 710                 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 711                 udelay(1);
 712
 713                 if (rpwm_val & BIT(7)) {
 714                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 715                                        (*(u8 *)val));
 716                 } else {
 717                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 718                                        ((*(u8 *)val) | BIT(7)));
 719                 }
 720
 721                 break; }
 722         case HW_VAR_H2C_FW_PWRMODE:
 723                 rtl8821ae_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
 724                 break;
 725         case HW_VAR_FW_PSMODE_STATUS:
 726                 ppsc->fw_current_inpsmode = *((bool *)val);
 727                 break;
 728         case HW_VAR_INIT_RTS_RATE:
 729                 break;
 730         case HW_VAR_RESUME_CLK_ON:
 731                 _rtl8821ae_set_fw_ps_rf_on(hw);
 732                 break;
 733         case HW_VAR_FW_LPS_ACTION:{
 734                 bool b_enter_fwlps = *((bool *)val);
 735
 736                 if (b_enter_fwlps)
 737                         _rtl8821ae_fwlps_enter(hw);
 738                  else
 739                         _rtl8821ae_fwlps_leave(hw);
 740                  break; }
 741         case HW_VAR_H2C_FW_JOINBSSRPT:{
 742                 u8 mstatus = (*(u8 *)val);
 743
 744                 if (mstatus == RT_MEDIA_CONNECT) {
 745                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
 746                                                       NULL);
 747                         _rtl8821ae_download_rsvd_page(hw, false);
 748                 }
 749                 rtl8821ae_set_fw_media_status_rpt_cmd(hw, mstatus);
 750
 751                 break; }
 752         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
 753                 rtl8821ae_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
 754                 break;
 755         case HW_VAR_AID:{
 756                 u16 u2btmp;
 757                 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 758                 u2btmp &= 0xC000;
 759                 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
 760                                mac->assoc_id));
 761                 break; }
 762         case HW_VAR_CORRECT_TSF:{
 763                 u8 btype_ibss = ((u8 *)(val))[0];
 764
 765                 if (btype_ibss)
 766                         _rtl8821ae_stop_tx_beacon(hw);
 767
 768                 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
 769
 770                 rtl_write_dword(rtlpriv, REG_TSFTR,
 771                                 (u32)(mac->tsf & 0xffffffff));
 772                 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 773                                 (u32)((mac->tsf >> 32) & 0xffffffff));
 774
 775                 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
 776
 777                 if (btype_ibss)
 778                         _rtl8821ae_resume_tx_beacon(hw);
 779                 break; }
 780         case HW_VAR_NAV_UPPER: {
 781                 u32     us_nav_upper = ((u32)*val);
 782
 783                 if (us_nav_upper > HAL_92C_NAV_UPPER_UNIT * 0xFF) {
 784                         RT_TRACE(rtlpriv, COMP_INIT , DBG_WARNING,
 785                                  "The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n",
 786                                  us_nav_upper, HAL_92C_NAV_UPPER_UNIT);
 787                         break;
 788                 }
 789                 rtl_write_byte(rtlpriv, REG_NAV_UPPER,
 790                                ((u8)((us_nav_upper +
 791                                 HAL_92C_NAV_UPPER_UNIT - 1) /
 792                                 HAL_92C_NAV_UPPER_UNIT)));
 793                 break; }
 794         case HW_VAR_KEEP_ALIVE: {
 795                 u8 array[2];
 796                 array[0] = 0xff;
 797                 array[1] = *((u8 *)val);
 798                 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_KEEP_ALIVE_CTRL, 2,
 799                                        array);
 800                 break; }
 801         default:
 802                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 803                          "switch case not process %x\n", variable);
 804                 break;
 805         }
 806 }
 807
 808 static bool _rtl8821ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 809 {
 810         struct rtl_priv *rtlpriv = rtl_priv(hw);
 811         bool status = true;
 812         long count = 0;
 813         u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
 814                     _LLT_OP(_LLT_WRITE_ACCESS);
 815
 816         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 817
 818         do {
 819                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 820                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 821                         break;
 822
 823                 if (count > POLLING_LLT_THRESHOLD) {
 824                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 825                                  "Failed to polling write LLT done at address %d!\n",
 826                                  address);
 827                         status = false;
 828                         break;
 829                 }
 830         } while (++count);
 831
 832         return status;
 833 }
 834
 835 static bool _rtl8821ae_llt_table_init(struct ieee80211_hw *hw)
 836 {
 837         struct rtl_priv *rtlpriv = rtl_priv(hw);
 838         unsigned short i;
 839         u8 txpktbuf_bndy;
 840         u32 rqpn;
 841         u8 maxpage;
 842         bool status;
 843
 844         maxpage = 255;
 845         txpktbuf_bndy = 0xF8;
 846         rqpn = 0x80e70808;
 847         if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8812AE) {
 848                 txpktbuf_bndy = 0xFA;
 849                 rqpn = 0x80e90808;
 850         }
 851
 852         rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
 853         rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, MAX_RX_DMA_BUFFER_SIZE - 1);
 854
 855         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 856
 857         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 858         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 859
 860         rtl_write_byte(rtlpriv, REG_PBP, 0x31);
 861         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 862
 863         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 864                 status = _rtl8821ae_llt_write(hw, i, i + 1);
 865                 if (!status)
 866                         return status;
 867         }
 868
 869         status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 870         if (!status)
 871                 return status;
 872
 873         for (i = txpktbuf_bndy; i < maxpage; i++) {
 874                 status = _rtl8821ae_llt_write(hw, i, (i + 1));
 875                 if (!status)
 876                         return status;
 877         }
 878
 879         status = _rtl8821ae_llt_write(hw, maxpage, txpktbuf_bndy);
 880         if (!status)
 881                 return status;
 882
 883         rtl_write_dword(rtlpriv, REG_RQPN, rqpn);
 884
 885         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
 886
 887         return true;
 888 }
 889
 890 static void _rtl8821ae_gen_refresh_led_state(struct ieee80211_hw *hw)
 891 {
 892         struct rtl_priv *rtlpriv = rtl_priv(hw);
 893         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 894         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 895         struct rtl_led *pled0 = &pcipriv->ledctl.sw_led0;
 896         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 897
 898         if (rtlpriv->rtlhal.up_first_time)
 899                 return;
 900
 901         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 902                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 903                         rtl8812ae_sw_led_on(hw, pled0);
 904                 else
 905                         rtl8821ae_sw_led_on(hw, pled0);
 906         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 907                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 908                         rtl8812ae_sw_led_on(hw, pled0);
 909                 else
 910                         rtl8821ae_sw_led_on(hw, pled0);
 911         else
 912                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 913                         rtl8812ae_sw_led_off(hw, pled0);
 914                 else
 915                         rtl8821ae_sw_led_off(hw, pled0);
 916 }
 917
 918 static bool _rtl8821ae_init_mac(struct ieee80211_hw *hw)
 919 {
 920         struct rtl_priv *rtlpriv = rtl_priv(hw);
 921         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 922         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 923
 924         u8 bytetmp = 0;
 925         u16 wordtmp = 0;
 926         bool mac_func_enable = rtlhal->mac_func_enable;
 927
 928         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 929
 930         /*Auto Power Down to CHIP-off State*/
 931         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
 932         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 933
 934         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
 935                 /* HW Power on sequence*/
 936                 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
 937                                               PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
 938                                               RTL8812_NIC_ENABLE_FLOW)) {
 939                                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 940                                          "init 8812 MAC Fail as power on failure\n");
 941                                 return false;
 942                 }
 943         } else {
 944                 /* HW Power on sequence */
 945                 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_A_MSK,
 946                                               PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
 947                                               RTL8821A_NIC_ENABLE_FLOW)){
 948                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 949                                 "init 8821 MAC Fail as power on failure\n");
 950                         return false;
 951                 }
 952         }
 953
 954         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
 955         rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
 956
 957         bytetmp = rtl_read_byte(rtlpriv, REG_CR);
 958         bytetmp = 0xff;
 959         rtl_write_byte(rtlpriv, REG_CR, bytetmp);
 960         mdelay(2);
 961
 962         bytetmp = 0xff;
 963         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
 964         mdelay(2);
 965
 966         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
 967                 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
 968                 if (bytetmp & BIT(0)) {
 969                         bytetmp = rtl_read_byte(rtlpriv, 0x7c);
 970                         bytetmp |= BIT(6);
 971                         rtl_write_byte(rtlpriv, 0x7c, bytetmp);
 972                 }
 973         }
 974
 975         bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
 976         bytetmp &= ~BIT(4);
 977         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp);
 978
 979         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 980
 981         if (!mac_func_enable) {
 982                 if (!_rtl8821ae_llt_table_init(hw))
 983                         return false;
 984         }
 985
 986         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 987         rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
 988
 989         /* Enable FW Beamformer Interrupt */
 990         bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
 991         rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
 992
 993         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 994         wordtmp &= 0xf;
 995         wordtmp |= 0xF5B1;
 996         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 997
 998         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 999         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1000         rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
1001         /*low address*/
1002         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
1003                         rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
1004         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
1005                         rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
1006         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
1007                         rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
1008         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
1009                         rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
1010         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
1011                         rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
1012         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
1013                         rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
1014         rtl_write_dword(rtlpriv, REG_HQ_DESA,
1015                         rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
1016         rtl_write_dword(rtlpriv, REG_RX_DESA,
1017                         rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
1018
1019         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
1020
1021         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
1022
1023         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0);
1024
1025         rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
1026         _rtl8821ae_gen_refresh_led_state(hw);
1027
1028         return true;
1029 }
1030
1031 static void _rtl8821ae_hw_configure(struct ieee80211_hw *hw)
1032 {
1033         struct rtl_priv *rtlpriv = rtl_priv(hw);
1034         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1035         u32 reg_rrsr;
1036
1037         reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1038
1039         rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
1040         /* ARFB table 9 for 11ac 5G 2SS */
1041         rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
1042         /* ARFB table 10 for 11ac 5G 1SS */
1043         rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
1044         /* ARFB table 11 for 11ac 24G 1SS */
1045         rtl_write_dword(rtlpriv, REG_ARFR2, 0x00000015);
1046         rtl_write_dword(rtlpriv, REG_ARFR2 + 4, 0x003ff000);
1047         /* ARFB table 12 for 11ac 24G 1SS */
1048         rtl_write_dword(rtlpriv, REG_ARFR3, 0x00000015);
1049         rtl_write_dword(rtlpriv, REG_ARFR3 + 4, 0xffcff000);
1050         /* 0x420[7] = 0 , enable retry AMPDU in new AMPD not singal MPDU. */
1051         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
1052         rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
1053
1054         /*Set retry limit*/
1055         rtl_write_word(rtlpriv, REG_RL, 0x0707);
1056
1057         /* Set Data / Response auto rate fallack retry count*/
1058         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
1059         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
1060         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
1061         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
1062
1063         rtlpci->reg_bcn_ctrl_val = 0x1d;
1064         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
1065
1066         /* TBTT prohibit hold time. Suggested by designer TimChen. */
1067         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1068
1069         /* AGGR_BK_TIME Reg51A 0x16 */
1070         rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
1071
1072         /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
1073         rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
1074
1075         rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
1076         rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
1077         rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1F1F);
1078 }
1079
1080 static u16 _rtl8821ae_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
1081 {
1082         u16 ret = 0;
1083         u8 tmp = 0, count = 0;
1084
1085         rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
1086         tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1087         count = 0;
1088         while (tmp && count < 20) {
1089                 udelay(10);
1090                 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1091                 count++;
1092         }
1093         if (0 == tmp)
1094                 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
1095
1096         return ret;
1097 }
1098
1099 static void _rtl8821ae_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
1100 {
1101         u8 tmp = 0, count = 0;
1102
1103         rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
1104         rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
1105         tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1106         count = 0;
1107         while (tmp && count < 20) {
1108                 udelay(10);
1109                 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1110                 count++;
1111         }
1112 }
1113
1114 static u8 _rtl8821ae_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
1115 {
1116         u16 read_addr = addr & 0xfffc;
1117         u8 tmp = 0, count = 0, ret = 0;
1118
1119         rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
1120         rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
1121         tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1122         count = 0;
1123         while (tmp && count < 20) {
1124                 udelay(10);
1125                 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1126                 count++;
1127         }
1128         if (0 == tmp) {
1129                 read_addr = REG_DBI_RDATA + addr % 4;
1130                 ret = rtl_read_word(rtlpriv, read_addr);
1131         }
1132         return ret;
1133 }
1134
1135 static void _rtl8821ae_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
1136 {
1137         u8 tmp = 0, count = 0;
1138         u16 wrtie_addr, remainder = addr % 4;
1139
1140         wrtie_addr = REG_DBI_WDATA + remainder;
1141         rtl_write_byte(rtlpriv, wrtie_addr, data);
1142
1143         wrtie_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
1144         rtl_write_word(rtlpriv, REG_DBI_ADDR, wrtie_addr);
1145
1146         rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
1147
1148         tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1149         count = 0;
1150         while (tmp && count < 20) {
1151                 udelay(10);
1152                 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1153                 count++;
1154         }
1155 }
1156
1157 static void _rtl8821ae_enable_aspm_back_door(struct ieee80211_hw *hw)
1158 {
1159         struct rtl_priv *rtlpriv = rtl_priv(hw);
1160         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1161         u8 tmp;
1162
1163         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1164                 if (_rtl8821ae_mdio_read(rtlpriv, 0x04) != 0x8544)
1165                         _rtl8821ae_mdio_write(rtlpriv, 0x04, 0x8544);
1166
1167                 if (_rtl8821ae_mdio_read(rtlpriv, 0x0b) != 0x0070)
1168                         _rtl8821ae_mdio_write(rtlpriv, 0x0b, 0x0070);
1169         }
1170
1171         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x70f);
1172         _rtl8821ae_dbi_write(rtlpriv, 0x70f, tmp | BIT(7));
1173
1174         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x719);
1175         _rtl8821ae_dbi_write(rtlpriv, 0x719, tmp | BIT(3) | BIT(4));
1176
1177         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1178                 tmp  = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1179                 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp|BIT(4));
1180         }
1181 }
1182
1183 void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw)
1184 {
1185         struct rtl_priv *rtlpriv = rtl_priv(hw);
1186         u8 sec_reg_value;
1187         u8 tmp;
1188
1189         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1190                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1191                   rtlpriv->sec.pairwise_enc_algorithm,
1192                   rtlpriv->sec.group_enc_algorithm);
1193
1194         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1195                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1196                          "not open hw encryption\n");
1197                 return;
1198         }
1199
1200         sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1201
1202         if (rtlpriv->sec.use_defaultkey) {
1203                 sec_reg_value |= SCR_TXUSEDK;
1204                 sec_reg_value |= SCR_RXUSEDK;
1205         }
1206
1207         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1208
1209         tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1210         rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));
1211
1212         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1213                  "The SECR-value %x\n", sec_reg_value);
1214
1215         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1216 }
1217
1218 /* Static MacID Mapping (cf. Used in MacIdDoStaticMapping) ---------- */
1219 #define MAC_ID_STATIC_FOR_DEFAULT_PORT                          0
1220 #define MAC_ID_STATIC_FOR_BROADCAST_MULTICAST           1
1221 #define MAC_ID_STATIC_FOR_BT_CLIENT_START                               2
1222 #define MAC_ID_STATIC_FOR_BT_CLIENT_END                         3
1223 /* ----------------------------------------------------------- */
1224
1225 static void rtl8821ae_macid_initialize_mediastatus(struct ieee80211_hw *hw)
1226 {
1227         struct rtl_priv *rtlpriv = rtl_priv(hw);
1228         u8      media_rpt[4] = {RT_MEDIA_CONNECT, 1,
1229                 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1230                 MAC_ID_STATIC_FOR_BT_CLIENT_END};
1231
1232         rtlpriv->cfg->ops->set_hw_reg(hw,
1233                 HW_VAR_H2C_FW_MEDIASTATUSRPT, media_rpt);
1234
1235         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1236                  "Initialize MacId media status: from %d to %d\n",
1237                  MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1238                  MAC_ID_STATIC_FOR_BT_CLIENT_END);
1239 }
1240
1241 static bool _rtl8821ae_check_pcie_dma_hang(struct ieee80211_hw *hw)
1242 {
1243         struct rtl_priv *rtlpriv = rtl_priv(hw);
1244         u8 tmp;
1245
1246         /* write reg 0x350 Bit[26]=1. Enable debug port. */
1247         tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1248         if (!(tmp & BIT(2))) {
1249                 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2)));
1250                 mdelay(100);
1251         }
1252
1253         /* read reg 0x350 Bit[25] if 1 : RX hang */
1254         /* read reg 0x350 Bit[24] if 1 : TX hang */
1255         tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1256         if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1257                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1258                          "CheckPcieDMAHang8821AE(): true! Reset PCIE DMA!\n");
1259                 return true;
1260         } else {
1261                 return false;
1262         }
1263 }
1264
1265 static bool _rtl8821ae_reset_pcie_interface_dma(struct ieee80211_hw *hw,
1266                                          bool mac_power_on,
1267                                          bool in_watchdog)
1268 {
1269         struct rtl_priv *rtlpriv = rtl_priv(hw);
1270         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1271         u8 tmp;
1272         bool release_mac_rx_pause;
1273         u8 backup_pcie_dma_pause;
1274
1275         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1276
1277         /* 1. Disable register write lock. 0x1c[1] = 0 */
1278         tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1279         tmp &= ~(BIT(1));
1280         rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1281         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1282                 /* write 0xCC bit[2] = 1'b1 */
1283                 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1284                 tmp |= BIT(2);
1285                 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1286         }
1287
1288         /* 2. Check and pause TRX DMA */
1289         /* write 0x284 bit[18] = 1'b1 */
1290         /* write 0x301 = 0xFF */
1291         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1292         if (tmp & BIT(2)) {
1293                 /* Already pause before the function for another purpose. */
1294                 release_mac_rx_pause = false;
1295         } else {
1296                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1297                 release_mac_rx_pause = true;
1298         }
1299         backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
1300         if (backup_pcie_dma_pause != 0xFF)
1301                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
1302
1303         if (mac_power_on) {
1304                 /* 3. reset TRX function */
1305                 /* write 0x100 = 0x00 */
1306                 rtl_write_byte(rtlpriv, REG_CR, 0);
1307         }
1308
1309         /* 4. Reset PCIe DMA. 0x3[0] = 0 */
1310         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1311         tmp &= ~(BIT(0));
1312         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1313
1314         /* 5. Enable PCIe DMA. 0x3[0] = 1 */
1315         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1316         tmp |= BIT(0);
1317         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1318
1319         if (mac_power_on) {
1320                 /* 6. enable TRX function */
1321                 /* write 0x100 = 0xFF */
1322                 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1323
1324                 /* We should init LLT & RQPN and
1325                  * prepare Tx/Rx descrptor address later
1326                  * because MAC function is reset.*/
1327         }
1328
1329         /* 7. Restore PCIe autoload down bit */
1330         /* 8812AE does not has the defination. */
1331         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1332                 /* write 0xF8 bit[17] = 1'b1 */
1333                 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
1334                 tmp |= BIT(1);
1335                 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
1336         }
1337
1338         /* In MAC power on state, BB and RF maybe in ON state,
1339          * if we release TRx DMA here.
1340          * it will cause packets to be started to Tx/Rx,
1341          * so we release Tx/Rx DMA later.*/
1342         if (!mac_power_on/* || in_watchdog*/) {
1343                 /* 8. release TRX DMA */
1344                 /* write 0x284 bit[18] = 1'b0 */
1345                 /* write 0x301 = 0x00 */
1346                 if (release_mac_rx_pause) {
1347                         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1348                         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
1349                                        tmp & (~BIT(2)));
1350                 }
1351                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
1352                                backup_pcie_dma_pause);
1353         }
1354
1355         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1356                 /* 9. lock system register */
1357                 /* write 0xCC bit[2] = 1'b0 */
1358                 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1359                 tmp &= ~(BIT(2));
1360                 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1361         }
1362         return true;
1363 }
1364
1365 static void _rtl8821ae_get_wakeup_reason(struct ieee80211_hw *hw)
1366 {
1367         struct rtl_priv *rtlpriv = rtl_priv(hw);
1368         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1369         struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1370         u8 fw_reason = 0;
1371         struct timeval ts;
1372
1373         fw_reason = rtl_read_byte(rtlpriv, REG_MCUTST_WOWLAN);
1374
1375         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "WOL Read 0x1c7 = %02X\n",
1376                  fw_reason);
1377
1378         ppsc->wakeup_reason = 0;
1379
1380         rtlhal->last_suspend_sec = ts.tv_sec;
1381
1382         switch (fw_reason) {
1383         case FW_WOW_V2_PTK_UPDATE_EVENT:
1384                 ppsc->wakeup_reason = WOL_REASON_PTK_UPDATE;
1385                 do_gettimeofday(&ts);
1386                 ppsc->last_wakeup_time = ts.tv_sec*1000 + ts.tv_usec/1000;
1387                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1388                          "It's a WOL PTK Key update event!\n");
1389                 break;
1390         case FW_WOW_V2_GTK_UPDATE_EVENT:
1391                 ppsc->wakeup_reason = WOL_REASON_GTK_UPDATE;
1392                 do_gettimeofday(&ts);
1393                 ppsc->last_wakeup_time = ts.tv_sec*1000 + ts.tv_usec/1000;
1394                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1395                          "It's a WOL GTK Key update event!\n");
1396                 break;
1397         case FW_WOW_V2_DISASSOC_EVENT:
1398                 ppsc->wakeup_reason = WOL_REASON_DISASSOC;
1399                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1400                          "It's a disassociation event!\n");
1401                 break;
1402         case FW_WOW_V2_DEAUTH_EVENT:
1403                 ppsc->wakeup_reason = WOL_REASON_DEAUTH;
1404                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1405                          "It's a deauth event!\n");
1406                 break;
1407         case FW_WOW_V2_FW_DISCONNECT_EVENT:
1408                 ppsc->wakeup_reason = WOL_REASON_AP_LOST;
1409                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1410                          "It's a Fw disconnect decision (AP lost) event!\n");
1411         break;
1412         case FW_WOW_V2_MAGIC_PKT_EVENT:
1413                 ppsc->wakeup_reason = WOL_REASON_MAGIC_PKT;
1414                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1415                          "It's a magic packet event!\n");
1416                 break;
1417         case FW_WOW_V2_UNICAST_PKT_EVENT:
1418                 ppsc->wakeup_reason = WOL_REASON_UNICAST_PKT;
1419                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1420                          "It's an unicast packet event!\n");
1421                 break;
1422         case FW_WOW_V2_PATTERN_PKT_EVENT:
1423                 ppsc->wakeup_reason = WOL_REASON_PATTERN_PKT;
1424                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1425                          "It's a pattern match event!\n");
1426                 break;
1427         case FW_WOW_V2_RTD3_SSID_MATCH_EVENT:
1428                 ppsc->wakeup_reason = WOL_REASON_RTD3_SSID_MATCH;
1429                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1430                          "It's an RTD3 Ssid match event!\n");
1431                 break;
1432         case FW_WOW_V2_REALWOW_V2_WAKEUPPKT:
1433                 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_WAKEUPPKT;
1434                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1435                          "It's an RealWoW wake packet event!\n");
1436                 break;
1437         case FW_WOW_V2_REALWOW_V2_ACKLOST:
1438                 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_ACKLOST;
1439                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1440                          "It's an RealWoW ack lost event!\n");
1441                 break;
1442         default:
1443                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1444                          "WOL Read 0x1c7 = %02X, Unknown reason!\n",
1445                           fw_reason);
1446                 break;
1447         }
1448 }
1449
1450 static void _rtl8821ae_init_trx_desc_hw_address(struct ieee80211_hw *hw)
1451 {
1452         struct rtl_priv *rtlpriv = rtl_priv(hw);
1453         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1454
1455         /*low address*/
1456         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
1457                         rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
1458         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
1459                         rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
1460         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
1461                         rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
1462         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
1463                         rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
1464         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
1465                         rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
1466         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
1467                         rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
1468         rtl_write_dword(rtlpriv, REG_HQ_DESA,
1469                         rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
1470         rtl_write_dword(rtlpriv, REG_RX_DESA,
1471                         rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
1472 }
1473
1474 static bool _rtl8821ae_init_llt_table(struct ieee80211_hw *hw, u32 boundary)
1475 {
1476         bool status = true;
1477         u32 i;
1478         u32 txpktbuf_bndy = boundary;
1479         u32 last_entry_of_txpktbuf = LAST_ENTRY_OF_TX_PKT_BUFFER;
1480
1481         for (i = 0 ; i < (txpktbuf_bndy - 1) ; i++) {
1482                 status = _rtl8821ae_llt_write(hw, i , i + 1);
1483                 if (!status)
1484                         return status;
1485         }
1486
1487         status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
1488         if (!status)
1489                 return status;
1490
1491         for (i = txpktbuf_bndy ; i < last_entry_of_txpktbuf ; i++) {
1492                 status = _rtl8821ae_llt_write(hw, i, (i + 1));
1493                 if (!status)
1494                         return status;
1495         }
1496
1497         status = _rtl8821ae_llt_write(hw, last_entry_of_txpktbuf,
1498                                       txpktbuf_bndy);
1499         if (!status)
1500                 return status;
1501
1502         return status;
1503 }
1504
1505 static bool _rtl8821ae_dynamic_rqpn(struct ieee80211_hw *hw, u32 boundary,
1506                              u16 npq_rqpn_value, u32 rqpn_val)
1507 {
1508         struct rtl_priv *rtlpriv = rtl_priv(hw);
1509         u8 tmp;
1510         bool ret = true;
1511         u16 count = 0, tmp16;
1512         bool support_remote_wakeup;
1513
1514         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1515                                       (u8 *)(&support_remote_wakeup));
1516
1517         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1518                  "boundary=%#X, NPQ_RQPNValue=%#X, RQPNValue=%#X\n",
1519                   boundary, npq_rqpn_value, rqpn_val);
1520
1521         /* stop PCIe DMA
1522          * 1. 0x301[7:0] = 0xFE */
1523         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1524
1525         /* wait TXFF empty
1526          * 2. polling till 0x41A[15:0]=0x07FF */
1527         tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1528         while ((tmp16 & 0x07FF) != 0x07FF) {
1529                 udelay(100);
1530                 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1531                 count++;
1532                 if ((count % 200) == 0) {
1533                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1534                                  "Tx queue is not empty for 20ms!\n");
1535                 }
1536                 if (count >= 1000) {
1537                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1538                                  "Wait for Tx FIFO empty timeout!\n");
1539                         break;
1540                 }
1541         }
1542
1543         /* TX pause
1544          * 3. reg 0x522=0xFF */
1545         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1546
1547         /* Wait TX State Machine OK
1548          * 4. polling till reg 0x5FB~0x5F8 = 0x00000000 for 50ms */
1549         count = 0;
1550         while (rtl_read_byte(rtlpriv, REG_SCH_TXCMD) != 0) {
1551                 udelay(100);
1552                 count++;
1553                 if (count >= 500) {
1554                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1555                                  "Wait for TX State Machine ready timeout !!\n");
1556                         break;
1557                 }
1558         }
1559
1560         /* stop RX DMA path
1561          * 5.   0x284[18] = 1
1562          * 6.   wait till 0x284[17] == 1
1563          * wait RX DMA idle */
1564         count = 0;
1565         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1566         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1567         do {
1568                 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1569                 udelay(10);
1570                 count++;
1571         } while (!(tmp & BIT(1)) && count < 100);
1572
1573         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1574                  "Wait until Rx DMA Idle. count=%d REG[0x286]=0x%x\n",
1575                   count, tmp);
1576
1577         /* reset BB
1578          * 7.   0x02 [0] = 0 */
1579         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1580         tmp &= ~(BIT(0));
1581         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmp);
1582
1583         /* Reset TRX MAC
1584          * 8.    0x100 = 0x00
1585          * Delay (1ms) */
1586         rtl_write_byte(rtlpriv, REG_CR, 0x00);
1587         udelay(1000);
1588
1589         /* Disable MAC Security Engine
1590          * 9.   0x100 bit[9]=0 */
1591         tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1592         tmp &= ~(BIT(1));
1593         rtl_write_byte(rtlpriv, REG_CR + 1, tmp);
1594
1595         /* To avoid DD-Tim Circuit hang
1596          * 10.  0x553 bit[5]=1 */
1597         tmp = rtl_read_byte(rtlpriv, REG_DUAL_TSF_RST);
1598         rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (tmp | BIT(5)));
1599
1600         /* Enable MAC Security Engine
1601          * 11.  0x100 bit[9]=1 */
1602         tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1603         rtl_write_byte(rtlpriv, REG_CR + 1, (tmp | BIT(1)));
1604
1605         /* Enable TRX MAC
1606          * 12.   0x100 = 0xFF
1607          *      Delay (1ms) */
1608         rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1609         udelay(1000);
1610
1611         /* Enable BB
1612          * 13.  0x02 [0] = 1 */
1613         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1614         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, (tmp | BIT(0)));
1615
1616         /* beacon setting
1617          * 14,15. set beacon head page (reg 0x209 and 0x424) */
1618         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, (u8)boundary);
1619         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, (u8)boundary);
1620         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, (u8)boundary);
1621
1622         /* 16.  WMAC_LBK_BF_HD 0x45D[7:0]
1623          * WMAC_LBK_BF_HD */
1624         rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD,
1625                        (u8)boundary);
1626
1627         rtl_write_word(rtlpriv, REG_TRXFF_BNDY, boundary);
1628
1629         /* init LLT
1630          * 17. init LLT */
1631         if (!_rtl8821ae_init_llt_table(hw, boundary)) {
1632                 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
1633                          "Failed to init LLT table!\n");
1634                 return false;
1635         }
1636
1637         /* reallocate RQPN
1638          * 18. reallocate RQPN and init LLT */
1639         rtl_write_word(rtlpriv, REG_RQPN_NPQ, npq_rqpn_value);
1640         rtl_write_dword(rtlpriv, REG_RQPN, rqpn_val);
1641
1642         /* release Tx pause
1643          * 19. 0x522=0x00 */
1644         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1645
1646         /* enable PCIE DMA
1647          * 20. 0x301[7:0] = 0x00
1648          * 21. 0x284[18] = 0 */
1649         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1650         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1651         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp&~BIT(2)));
1652
1653         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "End.\n");
1654         return ret;
1655 }
1656
1657 static void _rtl8821ae_simple_initialize_adapter(struct ieee80211_hw *hw)
1658 {
1659         struct rtl_priv *rtlpriv = rtl_priv(hw);
1660         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1661         struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1662
1663 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
1664         /* Re-download normal Fw. */
1665         rtl8821ae_set_fw_related_for_wowlan(hw, false);
1666 #endif
1667
1668         /* Re-Initialize LLT table. */
1669         if (rtlhal->re_init_llt_table) {
1670                 u32 rqpn = 0x80e70808;
1671                 u8 rqpn_npq = 0, boundary = 0xF8;
1672                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1673                         rqpn = 0x80e90808;
1674                         boundary = 0xFA;
1675                 }
1676                 if (_rtl8821ae_dynamic_rqpn(hw, boundary, rqpn_npq, rqpn))
1677                         rtlhal->re_init_llt_table = false;
1678         }
1679
1680         ppsc->rfpwr_state = ERFON;
1681 }
1682
1683 static void _rtl8821ae_enable_l1off(struct ieee80211_hw *hw)
1684 {
1685         u8 tmp  = 0;
1686         struct rtl_priv *rtlpriv = rtl_priv(hw);
1687
1688         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1689
1690         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x160);
1691         if (!(tmp & (BIT(2) | BIT(3)))) {
1692                 RT_TRACE(rtlpriv, COMP_POWER | COMP_INIT, DBG_LOUD,
1693                          "0x160(%#x)return!!\n", tmp);
1694                 return;
1695         }
1696
1697         tmp = _rtl8821ae_mdio_read(rtlpriv, 0x1b);
1698         _rtl8821ae_mdio_write(rtlpriv, 0x1b, (tmp | BIT(4)));
1699
1700         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1701         _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp | BIT(5));
1702
1703         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1704 }
1705
1706 static void _rtl8821ae_enable_ltr(struct ieee80211_hw *hw)
1707 {
1708         u8 tmp  = 0;
1709         struct rtl_priv *rtlpriv = rtl_priv(hw);
1710
1711         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1712
1713         /* Check 0x98[10] */
1714         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x99);
1715         if (!(tmp & BIT(2))) {
1716                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1717                          "<---0x99(%#x) return!!\n", tmp);
1718                 return;
1719         }
1720
1721         /* LTR idle latency, 0x90 for 144us */
1722         rtl_write_dword(rtlpriv, 0x798, 0x88908890);
1723
1724         /* LTR active latency, 0x3c for 60us */
1725         rtl_write_dword(rtlpriv, 0x79c, 0x883c883c);
1726
1727         tmp = rtl_read_byte(rtlpriv, 0x7a4);
1728         rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(4)));
1729
1730         tmp = rtl_read_byte(rtlpriv, 0x7a4);
1731         rtl_write_byte(rtlpriv, 0x7a4, (tmp & (~BIT(0))));
1732         rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(0)));
1733
1734         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1735 }
1736
1737 static bool _rtl8821ae_wowlan_initialize_adapter(struct ieee80211_hw *hw)
1738 {
1739         struct rtl_priv *rtlpriv = rtl_priv(hw);
1740         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1741         bool init_finished = true;
1742         u8 tmp = 0;
1743
1744         /* Get Fw wake up reason. */
1745         _rtl8821ae_get_wakeup_reason(hw);
1746
1747         /* Patch Pcie Rx DMA hang after S3/S4 several times.
1748          * The root cause has not be found. */
1749         if (_rtl8821ae_check_pcie_dma_hang(hw))
1750                 _rtl8821ae_reset_pcie_interface_dma(hw, true, false);
1751
1752         /* Prepare Tx/Rx Desc Hw address. */
1753         _rtl8821ae_init_trx_desc_hw_address(hw);
1754
1755         /* Release Pcie Interface Rx DMA to allow wake packet DMA. */
1756         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1757         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Enable PCIE Rx DMA.\n");
1758
1759         /* Check wake up event.
1760          * We should check wake packet bit before disable wowlan by H2C or
1761          * Fw will clear the bit. */
1762         tmp = rtl_read_byte(rtlpriv, REG_FTISR + 3);
1763         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1764                  "Read REG_FTISR 0x13f = %#X\n", tmp);
1765
1766         /* Set the WoWLAN related function control disable. */
1767         rtl8821ae_set_fw_wowlan_mode(hw, false);
1768         rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 0);
1769
1770         if (rtlhal->hw_rof_enable) {
1771                 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
1772                 if (tmp & BIT(1)) {
1773                         /* Clear GPIO9 ISR */
1774                         rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
1775                         init_finished = false;
1776                 } else {
1777                         init_finished = true;
1778                 }
1779         }
1780
1781         if (init_finished) {
1782                 _rtl8821ae_simple_initialize_adapter(hw);
1783
1784                 /* Release Pcie Interface Tx DMA. */
1785                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1786                 /* Release Pcie RX DMA */
1787                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 0x02);
1788
1789                 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1790                 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp & (~BIT(0))));
1791
1792                 _rtl8821ae_enable_l1off(hw);
1793                 _rtl8821ae_enable_ltr(hw);
1794         }
1795
1796         return init_finished;
1797 }
1798
1799 static void _rtl8812ae_bb8812_config_1t(struct ieee80211_hw *hw)
1800 {
1801         /* BB OFDM RX Path_A */
1802         rtl_set_bbreg(hw, 0x808, 0xff, 0x11);
1803         /* BB OFDM TX Path_A */
1804         rtl_set_bbreg(hw, 0x80c, MASKLWORD, 0x1111);
1805         /* BB CCK R/Rx Path_A */
1806         rtl_set_bbreg(hw, 0xa04, 0x0c000000, 0x0);
1807         /* MCS support */
1808         rtl_set_bbreg(hw, 0x8bc, 0xc0000060, 0x4);
1809         /* RF Path_B HSSI OFF */
1810         rtl_set_bbreg(hw, 0xe00, 0xf, 0x4);
1811         /* RF Path_B Power Down */
1812         rtl_set_bbreg(hw, 0xe90, MASKDWORD, 0);
1813         /* ADDA Path_B OFF */
1814         rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0);
1815         rtl_set_bbreg(hw, 0xe64, MASKDWORD, 0);
1816 }
1817
1818 static void _rtl8821ae_poweroff_adapter(struct ieee80211_hw *hw)
1819 {
1820         struct rtl_priv *rtlpriv = rtl_priv(hw);
1821         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1822         u8 u1b_tmp;
1823
1824         rtlhal->mac_func_enable = false;
1825
1826         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1827                 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1828                 /* 1. Run LPS WL RFOFF flow */
1829                 /* RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1830                 "=====>CardDisableRTL8812E,RTL8821A_NIC_LPS_ENTER_FLOW\n");
1831                 */
1832                 rtl_hal_pwrseqcmdparsing(rtlpriv,
1833                         PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1834                         PWR_INTF_PCI_MSK, RTL8821A_NIC_LPS_ENTER_FLOW);
1835         }
1836         /* 2. 0x1F[7:0] = 0 */
1837         /* turn off RF */
1838         /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */
1839         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1840                 rtlhal->fw_ready) {
1841                 rtl8821ae_firmware_selfreset(hw);
1842         }
1843
1844         /* Reset MCU. Suggested by Filen. */
1845         u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1846         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
1847
1848         /* g.   MCUFWDL 0x80[1:0]=0      */
1849         /* reset MCU ready status */
1850         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1851
1852         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1853                 /* HW card disable configuration. */
1854                 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1855                         PWR_INTF_PCI_MSK, RTL8821A_NIC_DISABLE_FLOW);
1856         } else {
1857                 /* HW card disable configuration. */
1858                 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1859                         PWR_INTF_PCI_MSK, RTL8812_NIC_DISABLE_FLOW);
1860         }
1861
1862         /* Reset MCU IO Wrapper */
1863         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1864         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1865         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1866         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1867
1868         /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1869         /* lock ISO/CLK/Power control register */
1870         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1871 }
1872
1873 int rtl8821ae_hw_init(struct ieee80211_hw *hw)
1874 {
1875         struct rtl_priv *rtlpriv = rtl_priv(hw);
1876         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1877         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1878         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1879         bool rtstatus = true;
1880         int err;
1881         u8 tmp_u1b;
1882         bool support_remote_wakeup;
1883         u32 nav_upper = WIFI_NAV_UPPER_US;
1884
1885         rtlhal->being_init_adapter = true;
1886         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1887                                       (u8 *)(&support_remote_wakeup));
1888         rtlpriv->intf_ops->disable_aspm(hw);
1889
1890         /*YP wowlan not considered*/
1891
1892         tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
1893         if (tmp_u1b != 0 && tmp_u1b != 0xEA) {
1894                 rtlhal->mac_func_enable = true;
1895                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1896                          "MAC has already power on.\n");
1897         } else {
1898                 rtlhal->mac_func_enable = false;
1899                 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1900         }
1901
1902         if (support_remote_wakeup &&
1903                 rtlhal->wake_from_pnp_sleep &&
1904                 rtlhal->mac_func_enable) {
1905                 if (_rtl8821ae_wowlan_initialize_adapter(hw)) {
1906                         rtlhal->being_init_adapter = false;
1907                         return 0;
1908                 }
1909         }
1910
1911         if (_rtl8821ae_check_pcie_dma_hang(hw)) {
1912                 _rtl8821ae_reset_pcie_interface_dma(hw,
1913                                                     rtlhal->mac_func_enable,
1914                                                     false);
1915                 rtlhal->mac_func_enable = false;
1916         }
1917
1918         /* Reset MAC/BB/RF status if it is not powered off
1919          * before calling initialize Hw flow to prevent
1920          * from interface and MAC status mismatch.
1921          * 2013.06.21, by tynli. Suggested by SD1 JackieLau. */
1922         if (rtlhal->mac_func_enable) {
1923                 _rtl8821ae_poweroff_adapter(hw);
1924                 rtlhal->mac_func_enable = false;
1925         }
1926
1927         rtstatus = _rtl8821ae_init_mac(hw);
1928         if (rtstatus != true) {
1929                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1930                 err = 1;
1931                 return err;
1932         }
1933
1934         tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1935         tmp_u1b &= 0x7F;
1936         rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b);
1937
1938         err = rtl8821ae_download_fw(hw, false);
1939         if (err) {
1940                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1941                          "Failed to download FW. Init HW without FW now\n");
1942                 err = 1;
1943                 rtlhal->fw_ready = false;
1944                 return err;
1945         } else {
1946                 rtlhal->fw_ready = true;
1947         }
1948         ppsc->fw_current_inpsmode = false;
1949         rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1950         rtlhal->fw_clk_change_in_progress = false;
1951         rtlhal->allow_sw_to_change_hwclc = false;
1952         rtlhal->last_hmeboxnum = 0;
1953
1954         /*SIC_Init(Adapter);
1955         if(rtlhal->AMPDUBurstMode)
1956                 rtl_write_byte(rtlpriv,REG_AMPDU_BURST_MODE_8812,  0x7F);*/
1957
1958         rtl8821ae_phy_mac_config(hw);
1959         /* because last function modify RCR, so we update
1960          * rcr var here, or TP will unstable for receive_config
1961          * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1962          * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1963         rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
1964         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1965         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);*/
1966         rtl8821ae_phy_bb_config(hw);
1967
1968         rtl8821ae_phy_rf_config(hw);
1969
1970         if (rtlpriv->phy.rf_type == RF_1T1R &&
1971                 rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1972                 _rtl8812ae_bb8812_config_1t(hw);
1973
1974         _rtl8821ae_hw_configure(hw);
1975
1976         rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G);
1977
1978         /*set wireless mode*/
1979
1980         rtlhal->mac_func_enable = true;
1981
1982         rtl_cam_reset_all_entry(hw);
1983
1984         rtl8821ae_enable_hw_security_config(hw);
1985
1986         ppsc->rfpwr_state = ERFON;
1987
1988         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1989         _rtl8821ae_enable_aspm_back_door(hw);
1990         rtlpriv->intf_ops->enable_aspm(hw);
1991
1992         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE &&
1993             (rtlhal->rfe_type == 1 || rtlhal->rfe_type == 5))
1994                 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x0302);
1995
1996         rtl8821ae_bt_hw_init(hw);
1997         rtlpriv->rtlhal.being_init_adapter = false;
1998
1999         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_NAV_UPPER, (u8 *)&nav_upper);
2000
2001         /* rtl8821ae_dm_check_txpower_tracking(hw); */
2002         /* rtl8821ae_phy_lc_calibrate(hw); */
2003         if (support_remote_wakeup)
2004                 rtl_write_byte(rtlpriv, REG_WOW_CTRL, 0);
2005
2006         /* Release Rx DMA*/
2007         tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2008         if (tmp_u1b & BIT(2)) {
2009                 /* Release Rx DMA if needed*/
2010                 tmp_u1b &= ~BIT(2);
2011                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
2012         }
2013
2014         /* Release Tx/Rx PCIE DMA if*/
2015         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
2016
2017         rtl8821ae_dm_init(hw);
2018         rtl8821ae_macid_initialize_mediastatus(hw);
2019
2020         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_hw_init() <====\n");
2021         return err;
2022 }
2023
2024 static enum version_8821ae _rtl8821ae_read_chip_version(struct ieee80211_hw *hw)
2025 {
2026         struct rtl_priv *rtlpriv = rtl_priv(hw);
2027         struct rtl_phy *rtlphy = &rtlpriv->phy;
2028         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2029         enum version_8821ae version = VERSION_UNKNOWN;
2030         u32 value32;
2031
2032         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
2033         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2034                  "ReadChipVersion8812A 0xF0 = 0x%x\n", value32);
2035
2036         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
2037                 rtlphy->rf_type = RF_2T2R;
2038         else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
2039                 rtlphy->rf_type = RF_1T1R;
2040
2041         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2042                  "RF_Type is %x!!\n", rtlphy->rf_type);
2043
2044         if (value32 & TRP_VAUX_EN) {
2045                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2046                         if (rtlphy->rf_type == RF_2T2R)
2047                                 version = VERSION_TEST_CHIP_2T2R_8812;
2048                         else
2049                                 version = VERSION_TEST_CHIP_1T1R_8812;
2050                 } else
2051                         version = VERSION_TEST_CHIP_8821;
2052         } else {
2053                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2054                         u32 rtl_id = ((value32 & CHIP_VER_RTL_MASK) >> 12) + 1;
2055
2056                         if (rtlphy->rf_type == RF_2T2R)
2057                                 version =
2058                                         (enum version_8821ae)(CHIP_8812
2059                                         | NORMAL_CHIP |
2060                                         RF_TYPE_2T2R);
2061                         else
2062                                 version = (enum version_8821ae)(CHIP_8812
2063                                         | NORMAL_CHIP);
2064
2065                         version = (enum version_8821ae)(version | (rtl_id << 12));
2066                 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2067                         u32 rtl_id = value32 & CHIP_VER_RTL_MASK;
2068
2069                         version = (enum version_8821ae)(CHIP_8821
2070                                 | NORMAL_CHIP | rtl_id);
2071                 }
2072         }
2073
2074         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2075                 /*WL_HWROF_EN.*/
2076                 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2077                 rtlhal->hw_rof_enable = ((value32 & WL_HWROF_EN) ? 1 : 0);
2078         }
2079
2080         switch (version) {
2081         case VERSION_TEST_CHIP_1T1R_8812:
2082                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2083                          "Chip Version ID: VERSION_TEST_CHIP_1T1R_8812\n");
2084                 break;
2085         case VERSION_TEST_CHIP_2T2R_8812:
2086                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2087                          "Chip Version ID: VERSION_TEST_CHIP_2T2R_8812\n");
2088                 break;
2089         case VERSION_NORMAL_TSMC_CHIP_1T1R_8812:
2090                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2091                          "Chip Version ID:VERSION_NORMAL_TSMC_CHIP_1T1R_8812\n");
2092                 break;
2093         case VERSION_NORMAL_TSMC_CHIP_2T2R_8812:
2094                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2095                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812\n");
2096                 break;
2097         case VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT:
2098                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2099                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812 C CUT\n");
2100                 break;
2101         case VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT:
2102                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2103                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812 C CUT\n");
2104                 break;
2105         case VERSION_TEST_CHIP_8821:
2106                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2107                          "Chip Version ID: VERSION_TEST_CHIP_8821\n");
2108                 break;
2109         case VERSION_NORMAL_TSMC_CHIP_8821:
2110                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2111                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 A CUT\n");
2112                 break;
2113         case VERSION_NORMAL_TSMC_CHIP_8821_B_CUT:
2114                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2115                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 B CUT\n");
2116                 break;
2117         default:
2118                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2119                          "Chip Version ID: Unknow (0x%X)\n", version);
2120                 break;
2121         }
2122
2123         return version;
2124 }
2125
2126 static int _rtl8821ae_set_media_status(struct ieee80211_hw *hw,
2127                                      enum nl80211_iftype type)
2128 {
2129         struct rtl_priv *rtlpriv = rtl_priv(hw);
2130         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
2131         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
2132         bt_msr &= 0xfc;
2133
2134         rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
2135         RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD,
2136                 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
2137
2138         if (type == NL80211_IFTYPE_UNSPECIFIED ||
2139             type == NL80211_IFTYPE_STATION) {
2140                 _rtl8821ae_stop_tx_beacon(hw);
2141                 _rtl8821ae_enable_bcn_sub_func(hw);
2142         } else if (type == NL80211_IFTYPE_ADHOC ||
2143                 type == NL80211_IFTYPE_AP) {
2144                 _rtl8821ae_resume_tx_beacon(hw);
2145                 _rtl8821ae_disable_bcn_sub_func(hw);
2146         } else {
2147                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2148                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
2149                          type);
2150         }
2151
2152         switch (type) {
2153         case NL80211_IFTYPE_UNSPECIFIED:
2154                 bt_msr |= MSR_NOLINK;
2155                 ledaction = LED_CTL_LINK;
2156                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2157                          "Set Network type to NO LINK!\n");
2158                 break;
2159         case NL80211_IFTYPE_ADHOC:
2160                 bt_msr |= MSR_ADHOC;
2161                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2162                          "Set Network type to Ad Hoc!\n");
2163                 break;
2164         case NL80211_IFTYPE_STATION:
2165                 bt_msr |= MSR_INFRA;
2166                 ledaction = LED_CTL_LINK;
2167                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2168                          "Set Network type to STA!\n");
2169                 break;
2170         case NL80211_IFTYPE_AP:
2171                 bt_msr |= MSR_AP;
2172                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2173                          "Set Network type to AP!\n");
2174                 break;
2175         default:
2176                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2177                          "Network type %d not support!\n", type);
2178                 return 1;
2179         }
2180
2181         rtl_write_byte(rtlpriv, MSR, bt_msr);
2182         rtlpriv->cfg->ops->led_control(hw, ledaction);
2183         if ((bt_msr & MSR_MASK) == MSR_AP)
2184                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
2185         else
2186                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
2187
2188         return 0;
2189 }
2190
2191 void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
2192 {
2193         struct rtl_priv *rtlpriv = rtl_priv(hw);
2194         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2195         u32 reg_rcr = rtlpci->receive_config;
2196
2197         if (rtlpriv->psc.rfpwr_state != ERFON)
2198                 return;
2199
2200         if (check_bssid) {
2201                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
2202                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
2203                                               (u8 *)(&reg_rcr));
2204                 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
2205         } else if (!check_bssid) {
2206                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
2207                 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
2208                 rtlpriv->cfg->ops->set_hw_reg(hw,
2209                         HW_VAR_RCR, (u8 *)(&reg_rcr));
2210         }
2211 }
2212
2213 int rtl8821ae_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
2214 {
2215         struct rtl_priv *rtlpriv = rtl_priv(hw);
2216
2217         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_set_network_type!\n");
2218
2219         if (_rtl8821ae_set_media_status(hw, type))
2220                 return -EOPNOTSUPP;
2221
2222         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
2223                 if (type != NL80211_IFTYPE_AP)
2224                         rtl8821ae_set_check_bssid(hw, true);
2225         } else {
2226                 rtl8821ae_set_check_bssid(hw, false);
2227         }
2228
2229         return 0;
2230 }
2231
2232 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
2233 void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci)
2234 {
2235         struct rtl_priv *rtlpriv = rtl_priv(hw);
2236         rtl8821ae_dm_init_edca_turbo(hw);
2237         switch (aci) {
2238         case AC1_BK:
2239                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
2240                 break;
2241         case AC0_BE:
2242                 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
2243                 break;
2244         case AC2_VI:
2245                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
2246                 break;
2247         case AC3_VO:
2248                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
2249                 break;
2250         default:
2251                 RT_ASSERT(false, "invalid aci: %d !\n", aci);
2252                 break;
2253         }
2254 }
2255
2256 static void rtl8821ae_clear_interrupt(struct ieee80211_hw *hw)
2257 {
2258         struct rtl_priv *rtlpriv = rtl_priv(hw);
2259         u32 tmp = rtl_read_dword(rtlpriv, REG_HISR);
2260
2261         rtl_write_dword(rtlpriv, REG_HISR, tmp);
2262
2263         tmp = rtl_read_dword(rtlpriv, REG_HISRE);
2264         rtl_write_dword(rtlpriv, REG_HISRE, tmp);
2265
2266         tmp = rtl_read_dword(rtlpriv, REG_HSISR);
2267         rtl_write_dword(rtlpriv, REG_HSISR, tmp);
2268 }
2269
2270 void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw)
2271 {
2272         struct rtl_priv *rtlpriv = rtl_priv(hw);
2273         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2274
2275         if (!rtlpci->int_clear)
2276                 rtl8821ae_clear_interrupt(hw);/*clear it here first*/
2277
2278         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
2279         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
2280         rtlpci->irq_enabled = true;
2281         /* there are some C2H CMDs have been sent before
2282         system interrupt is enabled, e.g., C2H, CPWM.
2283         *So we need to clear all C2H events that FW has
2284         notified, otherwise FW won't schedule any commands anymore.
2285         */
2286         /* rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0); */
2287         /*enable system interrupt*/
2288         rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
2289 }
2290
2291 void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw)
2292 {
2293         struct rtl_priv *rtlpriv = rtl_priv(hw);
2294         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2295
2296         rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
2297         rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
2298         rtlpci->irq_enabled = false;
2299         /*synchronize_irq(rtlpci->pdev->irq);*/
2300 }
2301
2302 static void _rtl8821ae_clear_pci_pme_status(struct ieee80211_hw *hw)
2303 {
2304         struct rtl_priv *rtlpriv = rtl_priv(hw);
2305         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2306         u16 cap_hdr;
2307         u8 cap_pointer;
2308         u8 cap_id = 0xff;
2309         u8 pmcs_reg;
2310         u8 cnt = 0;
2311
2312         /* Get the Capability pointer first,
2313          * the Capability Pointer is located at
2314          * offset 0x34 from the Function Header */
2315
2316         pci_read_config_byte(rtlpci->pdev, 0x34, &cap_pointer);
2317         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2318                  "PCI configration 0x34 = 0x%2x\n", cap_pointer);
2319
2320         do {
2321                 pci_read_config_word(rtlpci->pdev, cap_pointer, &cap_hdr);
2322                 cap_id = cap_hdr & 0xFF;
2323
2324                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2325                          "in pci configration, cap_pointer%x = %x\n",
2326                           cap_pointer, cap_id);
2327
2328                 if (cap_id == 0x01) {
2329                         break;
2330                 } else {
2331                         /* point to next Capability */
2332                         cap_pointer = (cap_hdr >> 8) & 0xFF;
2333                         /* 0: end of pci capability, 0xff: invalid value */
2334                         if (cap_pointer == 0x00 || cap_pointer == 0xff) {
2335                                 cap_id = 0xff;
2336                                 break;
2337                         }
2338                 }
2339         } while (cnt++ < 200);
2340
2341         if (cap_id == 0x01) {
2342                 /* Get the PM CSR (Control/Status Register),
2343                  * The PME_Status is located at PM Capatibility offset 5, bit 7
2344                  */
2345                 pci_read_config_byte(rtlpci->pdev, cap_pointer + 5, &pmcs_reg);
2346
2347                 if (pmcs_reg & BIT(7)) {
2348                         /* PME event occured, clear the PM_Status by write 1 */
2349                         pmcs_reg = pmcs_reg | BIT(7);
2350
2351                         pci_write_config_byte(rtlpci->pdev, cap_pointer + 5,
2352                                               pmcs_reg);
2353                         /* Read it back to check */
2354                         pci_read_config_byte(rtlpci->pdev, cap_pointer + 5,
2355                                              &pmcs_reg);
2356                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2357                                  "Clear PME status 0x%2x to 0x%2x\n",
2358                                   cap_pointer + 5, pmcs_reg);
2359                 } else {
2360                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2361                                  "PME status(0x%2x) = 0x%2x\n",
2362                                   cap_pointer + 5, pmcs_reg);
2363                 }
2364         } else {
2365                 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
2366                          "Cannot find PME Capability\n");
2367         }
2368 }
2369
2370 void rtl8821ae_card_disable(struct ieee80211_hw *hw)
2371 {
2372         struct rtl_priv *rtlpriv = rtl_priv(hw);
2373         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2374         struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
2375         struct rtl_mac *mac = rtl_mac(rtlpriv);
2376         enum nl80211_iftype opmode;
2377         bool support_remote_wakeup;
2378         u8 tmp;
2379         u32 count = 0;
2380
2381         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
2382                                       (u8 *)(&support_remote_wakeup));
2383
2384         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2385
2386         if (!(support_remote_wakeup && mac->opmode == NL80211_IFTYPE_STATION)
2387             || !rtlhal->enter_pnp_sleep) {
2388                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Normal Power off\n");
2389                 mac->link_state = MAC80211_NOLINK;
2390                 opmode = NL80211_IFTYPE_UNSPECIFIED;
2391                 _rtl8821ae_set_media_status(hw, opmode);
2392                 _rtl8821ae_poweroff_adapter(hw);
2393         } else {
2394                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Wowlan Supported.\n");
2395                 /* 3 <1> Prepare for configuring wowlan related infomations */
2396                 /* Clear Fw WoWLAN event. */
2397                 rtl_write_byte(rtlpriv, REG_MCUTST_WOWLAN, 0x0);
2398
2399 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
2400                 rtl8821ae_set_fw_related_for_wowlan(hw, true);
2401 #endif
2402                 /* Dynamically adjust Tx packet boundary
2403                  * for download reserved page packet.
2404                  * reserve 30 pages for rsvd page */
2405                 if (_rtl8821ae_dynamic_rqpn(hw, 0xE0, 0x3, 0x80c20d0d))
2406                         rtlhal->re_init_llt_table = true;
2407
2408                 /* 3 <2> Set Fw releted H2C cmd. */
2409
2410                 /* Set WoWLAN related security information. */
2411                 rtl8821ae_set_fw_global_info_cmd(hw);
2412
2413                 _rtl8821ae_download_rsvd_page(hw, true);
2414
2415                 /* Just enable AOAC related functions when we connect to AP. */
2416                 printk("mac->link_state = %d\n", mac->link_state);
2417                 if (mac->link_state >= MAC80211_LINKED &&
2418                     mac->opmode == NL80211_IFTYPE_STATION) {
2419                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
2420                         rtl8821ae_set_fw_media_status_rpt_cmd(hw,
2421                                                               RT_MEDIA_CONNECT);
2422
2423                         rtl8821ae_set_fw_wowlan_mode(hw, true);
2424                         /* Enable Fw Keep alive mechanism. */
2425                         rtl8821ae_set_fw_keep_alive_cmd(hw, true);
2426
2427                         /* Enable disconnect decision control. */
2428                         rtl8821ae_set_fw_disconnect_decision_ctrl_cmd(hw, true);
2429                 }
2430
2431                 /* 3 <3> Hw Configutations */
2432
2433                 /* Wait untill Rx DMA Finished before host sleep.
2434                  * FW Pause Rx DMA may happens when received packet doing dma.
2435                  */
2436                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, BIT(2));
2437
2438                 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2439                 count = 0;
2440                 while (!(tmp & BIT(1)) && (count++ < 100)) {
2441                         udelay(10);
2442                         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2443                 }
2444                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2445                          "Wait Rx DMA Finished before host sleep. count=%d\n",
2446                           count);
2447
2448                 /* reset trx ring */
2449                 rtlpriv->intf_ops->reset_trx_ring(hw);
2450
2451                 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x0);
2452
2453                 _rtl8821ae_clear_pci_pme_status(hw);
2454                 tmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
2455                 rtl_write_byte(rtlpriv, REG_SYS_CLKR, tmp | BIT(3));
2456                 /* prevent 8051 to be reset by PERST */
2457                 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x20);
2458                 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x60);
2459         }
2460
2461         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
2462             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
2463                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
2464         /* For wowlan+LPS+32k. */
2465         if (support_remote_wakeup && rtlhal->enter_pnp_sleep) {
2466                 /* Set the WoWLAN related function control enable.
2467                  * It should be the last H2C cmd in the WoWLAN flow. */
2468                 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 1);
2469
2470                 /* Stop Pcie Interface Tx DMA. */
2471                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
2472                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Stop PCIE Tx DMA.\n");
2473
2474                 /* Wait for TxDMA idle. */
2475                 count = 0;
2476                 do {
2477                         tmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG);
2478                         udelay(10);
2479                         count++;
2480                 } while ((tmp != 0) && (count < 100));
2481                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2482                          "Wait Tx DMA Finished before host sleep. count=%d\n",
2483                           count);
2484
2485                 if (rtlhal->hw_rof_enable) {
2486                         printk("hw_rof_enable\n");
2487                         tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
2488                         rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
2489                 }
2490         }
2491         /* after power off we should do iqk again */
2492         rtlpriv->phy.iqk_initialized = false;
2493 }
2494
2495 void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw,
2496                                   u32 *p_inta, u32 *p_intb)
2497 {
2498         struct rtl_priv *rtlpriv = rtl_priv(hw);
2499         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2500
2501         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
2502         rtl_write_dword(rtlpriv, ISR, *p_inta);
2503
2504         *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
2505         rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
2506 }
2507
2508 void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw)
2509 {
2510         struct rtl_priv *rtlpriv = rtl_priv(hw);
2511         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2512         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2513         u16 bcn_interval, atim_window;
2514
2515         bcn_interval = mac->beacon_interval;
2516         atim_window = 2;        /*FIX MERGE */
2517         rtl8821ae_disable_interrupt(hw);
2518         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
2519         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2520         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
2521         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
2522         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
2523         rtl_write_byte(rtlpriv, 0x606, 0x30);
2524         rtlpci->reg_bcn_ctrl_val |= BIT(3);
2525         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
2526         rtl8821ae_enable_interrupt(hw);
2527 }
2528
2529 void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw)
2530 {
2531         struct rtl_priv *rtlpriv = rtl_priv(hw);
2532         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2533         u16 bcn_interval = mac->beacon_interval;
2534
2535         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
2536                  "beacon_interval:%d\n", bcn_interval);
2537         rtl8821ae_disable_interrupt(hw);
2538         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2539         rtl8821ae_enable_interrupt(hw);
2540 }
2541
2542 void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw,
2543                                    u32 add_msr, u32 rm_msr)
2544 {
2545         struct rtl_priv *rtlpriv = rtl_priv(hw);
2546         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2547
2548         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
2549                  "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
2550
2551         if (add_msr)
2552                 rtlpci->irq_mask[0] |= add_msr;
2553         if (rm_msr)
2554                 rtlpci->irq_mask[0] &= (~rm_msr);
2555         rtl8821ae_disable_interrupt(hw);
2556         rtl8821ae_enable_interrupt(hw);
2557 }
2558
2559 static u8 _rtl8821ae_get_chnl_group(u8 chnl)
2560 {
2561         u8 group = 0;
2562
2563         if (chnl <= 14) {
2564                 if (1 <= chnl && chnl <= 2)
2565                         group = 0;
2566         else if (3 <= chnl && chnl <= 5)
2567                         group = 1;
2568         else if (6 <= chnl && chnl <= 8)
2569                         group = 2;
2570         else if (9 <= chnl && chnl <= 11)
2571                         group = 3;
2572         else /*if (12 <= chnl && chnl <= 14)*/
2573                         group = 4;
2574         } else {
2575                 if (36 <= chnl && chnl <= 42)
2576                         group = 0;
2577         else if (44 <= chnl && chnl <= 48)
2578                         group = 1;
2579         else if (50 <= chnl && chnl <= 58)
2580                         group = 2;
2581         else if (60 <= chnl && chnl <= 64)
2582                         group = 3;
2583         else if (100 <= chnl && chnl <= 106)
2584                         group = 4;
2585         else if (108 <= chnl && chnl <= 114)
2586                         group = 5;
2587         else if (116 <= chnl && chnl <= 122)
2588                         group = 6;
2589         else if (124 <= chnl && chnl <= 130)
2590                         group = 7;
2591         else if (132 <= chnl && chnl <= 138)
2592                         group = 8;
2593         else if (140 <= chnl && chnl <= 144)
2594                         group = 9;
2595         else if (149 <= chnl && chnl <= 155)
2596                         group = 10;
2597         else if (157 <= chnl && chnl <= 161)
2598                         group = 11;
2599         else if (165 <= chnl && chnl <= 171)
2600                         group = 12;
2601         else if (173 <= chnl && chnl <= 177)
2602                         group = 13;
2603                 else
2604                         /*RT_TRACE(rtlpriv, COMP_EFUSE,DBG_LOUD,
2605                                 "5G, Channel %d in Group not found\n",chnl);*/
2606                         RT_ASSERT(!COMP_EFUSE,
2607                                 "5G, Channel %d in Group not found\n", chnl);
2608         }
2609         return group;
2610 }
2611
2612 static void _rtl8821ae_read_power_value_fromprom(struct ieee80211_hw *hw,
2613         struct txpower_info_2g *pwrinfo24g,
2614         struct txpower_info_5g *pwrinfo5g,
2615         bool autoload_fail,
2616         u8 *hwinfo)
2617 {
2618         struct rtl_priv *rtlpriv = rtl_priv(hw);
2619         u32 rfPath, eeAddr = EEPROM_TX_PWR_INX, group, TxCount = 0;
2620
2621         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2622                  "hal_ReadPowerValueFromPROM8821ae(): hwinfo[0x%x]=0x%x\n",
2623                  (eeAddr+1), hwinfo[eeAddr+1]);
2624         if (0xFF == hwinfo[eeAddr+1])  /*YJ,add,120316*/
2625                 autoload_fail = true;
2626
2627         if (autoload_fail) {
2628                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2629                          "auto load fail : Use Default value!\n");
2630                 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2631                         /*2.4G default value*/
2632                         for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2633                                 pwrinfo24g->index_cck_base[rfPath][group] =     0x2D;
2634                                 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
2635                         }
2636                         for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2637                                 if (TxCount == 0) {
2638                                         pwrinfo24g->bw20_diff[rfPath][0] = 0x02;
2639                                         pwrinfo24g->ofdm_diff[rfPath][0] = 0x04;
2640                                 } else {
2641                                         pwrinfo24g->bw20_diff[rfPath][TxCount] = 0xFE;
2642                                         pwrinfo24g->bw40_diff[rfPath][TxCount] = 0xFE;
2643                                         pwrinfo24g->cck_diff[rfPath][TxCount] = 0xFE;
2644                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] = 0xFE;
2645                                 }
2646                         }
2647                         /*5G default value*/
2648                         for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++)
2649                                 pwrinfo5g->index_bw40_base[rfPath][group] = 0x2A;
2650
2651                         for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2652                                 if (TxCount == 0) {
2653                                         pwrinfo5g->ofdm_diff[rfPath][0] = 0x04;
2654                                         pwrinfo5g->bw20_diff[rfPath][0] = 0x00;
2655                                         pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
2656                                         pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
2657                                 } else {
2658                                         pwrinfo5g->ofdm_diff[rfPath][0] = 0xFE;
2659                                         pwrinfo5g->bw20_diff[rfPath][0] = 0xFE;
2660                                         pwrinfo5g->bw40_diff[rfPath][0] = 0xFE;
2661                                         pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
2662                                         pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
2663                                 }
2664                         }
2665                 }
2666                 return;
2667         }
2668
2669         rtl_priv(hw)->efuse.txpwr_fromeprom = true;
2670
2671         for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2672                 /*2.4G default value*/
2673                 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2674                         pwrinfo24g->index_cck_base[rfPath][group] = hwinfo[eeAddr++];
2675                         if (pwrinfo24g->index_cck_base[rfPath][group] == 0xFF)
2676                                 pwrinfo24g->index_cck_base[rfPath][group] = 0x2D;
2677                 }
2678                 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) {
2679                         pwrinfo24g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2680                         if (pwrinfo24g->index_bw40_base[rfPath][group] == 0xFF)
2681                                 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
2682                 }
2683                 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2684                         if (TxCount == 0) {
2685                                 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0;
2686                                 /*bit sign number to 8 bit sign number*/
2687                                 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2688                                 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2689                                         pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2690                                 /*bit sign number to 8 bit sign number*/
2691                                 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2692                                 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2693                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2694
2695                                 pwrinfo24g->cck_diff[rfPath][TxCount] = 0;
2696                                 eeAddr++;
2697                         } else {
2698                                 pwrinfo24g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr]&0xf0) >> 4;
2699                                 if (pwrinfo24g->bw40_diff[rfPath][TxCount] & BIT(3))
2700                                         pwrinfo24g->bw40_diff[rfPath][TxCount] |= 0xF0;
2701
2702                                 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2703                                 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2704                                         pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2705
2706                                 eeAddr++;
2707
2708                                 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2709                                 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2710                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2711
2712                                 pwrinfo24g->cck_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2713                                 if (pwrinfo24g->cck_diff[rfPath][TxCount] & BIT(3))
2714                                         pwrinfo24g->cck_diff[rfPath][TxCount] |= 0xF0;
2715
2716                                 eeAddr++;
2717                         }
2718                 }
2719
2720                 /*5G default value*/
2721                 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
2722                         pwrinfo5g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2723                         if (pwrinfo5g->index_bw40_base[rfPath][group] == 0xFF)
2724                                 pwrinfo5g->index_bw40_base[rfPath][group] = 0xFE;
2725                 }
2726
2727                 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2728                         if (TxCount == 0) {
2729                                 pwrinfo5g->bw40_diff[rfPath][TxCount] = 0;
2730
2731                                 pwrinfo5g->bw20_diff[rfPath][0] = (hwinfo[eeAddr] & 0xf0) >> 4;
2732                                 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2733                                         pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2734
2735                                 pwrinfo5g->ofdm_diff[rfPath][0] = (hwinfo[eeAddr] & 0x0f);
2736                                 if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2737                                         pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2738
2739                                 eeAddr++;
2740                         } else {
2741                                 pwrinfo5g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2742                                 if (pwrinfo5g->bw40_diff[rfPath][TxCount] & BIT(3))
2743                                         pwrinfo5g->bw40_diff[rfPath][TxCount] |= 0xF0;
2744
2745                                 pwrinfo5g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2746                                 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2747                                         pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2748
2749                                 eeAddr++;
2750                         }
2751                 }
2752
2753                 pwrinfo5g->ofdm_diff[rfPath][1] =       (hwinfo[eeAddr] & 0xf0) >> 4;
2754                 pwrinfo5g->ofdm_diff[rfPath][2] =       (hwinfo[eeAddr] & 0x0f);
2755
2756                 eeAddr++;
2757
2758                 pwrinfo5g->ofdm_diff[rfPath][3] = (hwinfo[eeAddr] & 0x0f);
2759
2760                 eeAddr++;
2761
2762                 for (TxCount = 1; TxCount < MAX_TX_COUNT; TxCount++) {
2763                         if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2764                                 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2765                 }
2766                 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2767                         pwrinfo5g->bw80_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2768                         /* 4bit sign number to 8 bit sign number */
2769                         if (pwrinfo5g->bw80_diff[rfPath][TxCount] & BIT(3))
2770                                 pwrinfo5g->bw80_diff[rfPath][TxCount] |= 0xF0;
2771                         /* 4bit sign number to 8 bit sign number */
2772                         pwrinfo5g->bw160_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2773                         if (pwrinfo5g->bw160_diff[rfPath][TxCount] & BIT(3))
2774                                 pwrinfo5g->bw160_diff[rfPath][TxCount] |= 0xF0;
2775
2776                         eeAddr++;
2777                 }
2778         }
2779 }
2780 #if 0
2781 static void _rtl8812ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2782                                                  bool autoload_fail,
2783                                                  u8 *hwinfo)
2784 {
2785         struct rtl_priv *rtlpriv = rtl_priv(hw);
2786         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2787         struct txpower_info_2g pwrinfo24g;
2788         struct txpower_info_5g pwrinfo5g;
2789         u8 channel5g[CHANNEL_MAX_NUMBER_5G] = {
2790                 36, 38, 40, 42, 44, 46, 48, 50, 52, 54,
2791                 56, 58, 60, 62, 64, 100, 102, 104, 106,
2792                 108, 110, 112, 114, 116, 118, 120, 122,
2793                 124, 126, 128, 130, 132, 134, 136, 138,
2794                 140, 142, 144, 149, 151, 153, 155, 157,
2795                 159, 161, 163, 165, 167, 168, 169, 171, 173, 175, 177};
2796         u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {42, 58, 106, 122, 138, 155, 171};
2797         u8 rf_path, index;
2798         u8 i;
2799
2800         _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2801                                         &pwrinfo5g, autoload_fail, hwinfo);
2802
2803         for (rf_path = 0; rf_path < 2; rf_path++) {
2804                 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2805                         index = _rtl8821ae_get_chnl_group(i + 1);
2806
2807                         if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2808                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2809                                         pwrinfo24g.index_cck_base[rf_path][5];
2810                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2811                                         pwrinfo24g.index_bw40_base[rf_path][index];
2812                         } else {
2813                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2814                                         pwrinfo24g.index_cck_base[rf_path][index];
2815                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2816                                         pwrinfo24g.index_bw40_base[rf_path][index];
2817                         }
2818                 }
2819
2820                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2821                         index = _rtl8821ae_get_chnl_group(channel5g[i]);
2822                         rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2823                                         pwrinfo5g.index_bw40_base[rf_path][index];
2824                 }
2825                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2826                         u8 upper, lower;
2827                         index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2828                         upper = pwrinfo5g.index_bw40_base[rf_path][index];
2829                         lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2830
2831                         rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2832                 }
2833                 for (i = 0; i < MAX_TX_COUNT; i++) {
2834                         rtlefuse->txpwr_cckdiff[rf_path][i] =
2835                                 pwrinfo24g.cck_diff[rf_path][i];
2836                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2837                                 pwrinfo24g.ofdm_diff[rf_path][i];
2838                         rtlefuse->txpwr_ht20diff[rf_path][i] =
2839                                 pwrinfo24g.bw20_diff[rf_path][i];
2840                         rtlefuse->txpwr_ht40diff[rf_path][i] =
2841                                 pwrinfo24g.bw40_diff[rf_path][i];
2842
2843                         rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2844                                 pwrinfo5g.ofdm_diff[rf_path][i];
2845                         rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2846                                 pwrinfo5g.bw20_diff[rf_path][i];
2847                         rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2848                                 pwrinfo5g.bw40_diff[rf_path][i];
2849                         rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2850                                 pwrinfo5g.bw80_diff[rf_path][i];
2851                 }
2852         }
2853
2854         if (!autoload_fail) {
2855                 rtlefuse->eeprom_regulatory =
2856                         hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;/*bit0~2*/
2857                 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2858                         rtlefuse->eeprom_regulatory = 0;
2859         } else {
2860                 rtlefuse->eeprom_regulatory = 0;
2861         }
2862
2863         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2864         "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2865 }
2866 #endif
2867 static void _rtl8821ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2868                                                  bool autoload_fail,
2869                                                  u8 *hwinfo)
2870 {
2871         struct rtl_priv *rtlpriv = rtl_priv(hw);
2872         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2873         struct txpower_info_2g pwrinfo24g;
2874         struct txpower_info_5g pwrinfo5g;
2875         u8 channel5g[CHANNEL_MAX_NUMBER_5G] = {
2876                 36, 38, 40, 42, 44, 46, 48, 50, 52, 54,
2877                 56, 58, 60, 62, 64, 100, 102, 104, 106,
2878                 108, 110, 112, 114, 116, 118, 120, 122,
2879                 124, 126, 128, 130, 132, 134, 136, 138,
2880                 140, 142, 144, 149, 151, 153, 155, 157,
2881                 159, 161, 163, 165, 167, 168, 169, 171,
2882                 173, 175, 177};
2883         u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {
2884                 42, 58, 106, 122, 138, 155, 171};
2885         u8 rf_path, index;
2886         u8 i;
2887
2888         _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2889                 &pwrinfo5g, autoload_fail, hwinfo);
2890
2891         for (rf_path = 0; rf_path < 2; rf_path++) {
2892                 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2893                         index = _rtl8821ae_get_chnl_group(i + 1);
2894
2895                         if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2896                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2897                                         pwrinfo24g.index_cck_base[rf_path][5];
2898                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2899                                         pwrinfo24g.index_bw40_base[rf_path][index];
2900                         } else {
2901                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2902                                         pwrinfo24g.index_cck_base[rf_path][index];
2903                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2904                                         pwrinfo24g.index_bw40_base[rf_path][index];
2905                         }
2906                 }
2907
2908                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2909                         index = _rtl8821ae_get_chnl_group(channel5g[i]);
2910                         rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2911                                 pwrinfo5g.index_bw40_base[rf_path][index];
2912                 }
2913                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2914                         u8 upper, lower;
2915                         index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2916                         upper = pwrinfo5g.index_bw40_base[rf_path][index];
2917                         lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2918
2919                         rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2920                 }
2921                 for (i = 0; i < MAX_TX_COUNT; i++) {
2922                         rtlefuse->txpwr_cckdiff[rf_path][i] =
2923                                 pwrinfo24g.cck_diff[rf_path][i];
2924                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2925                                 pwrinfo24g.ofdm_diff[rf_path][i];
2926                         rtlefuse->txpwr_ht20diff[rf_path][i] =
2927                                 pwrinfo24g.bw20_diff[rf_path][i];
2928                         rtlefuse->txpwr_ht40diff[rf_path][i] =
2929                                 pwrinfo24g.bw40_diff[rf_path][i];
2930
2931                         rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2932                                 pwrinfo5g.ofdm_diff[rf_path][i];
2933                         rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2934                                 pwrinfo5g.bw20_diff[rf_path][i];
2935                         rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2936                                 pwrinfo5g.bw40_diff[rf_path][i];
2937                         rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2938                                 pwrinfo5g.bw80_diff[rf_path][i];
2939                 }
2940         }
2941         /*bit0~2*/
2942         if (!autoload_fail) {
2943                 rtlefuse->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;
2944                 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2945                         rtlefuse->eeprom_regulatory = 0;
2946         } else {
2947                 rtlefuse->eeprom_regulatory = 0;
2948         }
2949
2950         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2951         "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2952 }
2953
2954 static void _rtl8812ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
2955                                     bool autoload_fail)
2956 {
2957         struct rtl_priv *rtlpriv = rtl_priv(hw);
2958         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2959
2960         if (!autoload_fail) {
2961                 rtlhal->pa_type_2g = hwinfo[0xBC];
2962                 rtlhal->lna_type_2g = hwinfo[0xBD];
2963                 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
2964                         rtlhal->pa_type_2g = 0;
2965                         rtlhal->lna_type_2g = 0;
2966                 }
2967                 rtlhal->external_pa_2g = ((rtlhal->pa_type_2g & BIT(5)) &&
2968                                           (rtlhal->pa_type_2g & BIT(4))) ?
2969                                          1 : 0;
2970                 rtlhal->external_lna_2g = ((rtlhal->lna_type_2g & BIT(7)) &&
2971                                            (rtlhal->lna_type_2g & BIT(3))) ?
2972                                           1 : 0;
2973
2974                 rtlhal->pa_type_5g = hwinfo[0xBC];
2975                 rtlhal->lna_type_5g = hwinfo[0xBF];
2976                 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
2977                         rtlhal->pa_type_5g = 0;
2978                         rtlhal->lna_type_5g = 0;
2979                 }
2980                 rtlhal->external_pa_5g = ((rtlhal->pa_type_5g & BIT(1)) &&
2981                                           (rtlhal->pa_type_5g & BIT(0))) ?
2982                                          1 : 0;
2983                 rtlhal->external_lna_5g = ((rtlhal->lna_type_5g & BIT(7)) &&
2984                                            (rtlhal->lna_type_5g & BIT(3))) ?
2985                                           1 : 0;
2986         } else {
2987                 rtlhal->external_pa_2g  = 0;
2988                 rtlhal->external_lna_2g = 0;
2989                 rtlhal->external_pa_5g  = 0;
2990                 rtlhal->external_lna_5g = 0;
2991         }
2992 }
2993
2994 static void _rtl8821ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
2995                                     bool autoload_fail)
2996 {
2997         struct rtl_priv *rtlpriv = rtl_priv(hw);
2998         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2999
3000         if (!autoload_fail) {
3001                 rtlhal->pa_type_2g = hwinfo[0xBC];
3002                 rtlhal->lna_type_2g = hwinfo[0xBD];
3003                 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
3004                         rtlhal->pa_type_2g = 0;
3005                         rtlhal->lna_type_2g = 0;
3006                 }
3007                 rtlhal->external_pa_2g = (rtlhal->pa_type_2g & BIT(5)) ? 1 : 0;
3008                 rtlhal->external_lna_2g = (rtlhal->lna_type_2g & BIT(7)) ? 1 : 0;
3009
3010                 rtlhal->pa_type_5g = hwinfo[0xBC];
3011                 rtlhal->lna_type_5g = hwinfo[0xBF];
3012                 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
3013                         rtlhal->pa_type_5g = 0;
3014                         rtlhal->lna_type_5g = 0;
3015                 }
3016                 rtlhal->external_pa_5g = (rtlhal->pa_type_5g & BIT(1)) ? 1 : 0;
3017                 rtlhal->external_lna_5g = (rtlhal->lna_type_5g & BIT(7)) ? 1 : 0;
3018         } else {
3019                 rtlhal->external_pa_2g  = 0;
3020                 rtlhal->external_lna_2g = 0;
3021                 rtlhal->external_pa_5g  = 0;
3022                 rtlhal->external_lna_5g = 0;
3023         }
3024 }
3025
3026 static void _rtl8821ae_read_rfe_type(struct ieee80211_hw *hw, u8 *hwinfo,
3027                               bool autoload_fail)
3028 {
3029         struct rtl_priv *rtlpriv = rtl_priv(hw);
3030         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
3031
3032         if (!autoload_fail) {
3033                 if (hwinfo[EEPROM_RFE_OPTION] & BIT(7)) {
3034                         if (rtlhal->external_lna_5g) {
3035                                 if (rtlhal->external_pa_5g) {
3036                                         if (rtlhal->external_lna_2g &&
3037                                             rtlhal->external_pa_2g)
3038                                                 rtlhal->rfe_type = 3;
3039                                         else
3040                                                 rtlhal->rfe_type = 0;
3041                                 } else {
3042                                         rtlhal->rfe_type = 2;
3043                                 }
3044                         } else {
3045                                 rtlhal->rfe_type = 4;
3046                         }
3047                 } else {
3048                         rtlhal->rfe_type = hwinfo[EEPROM_RFE_OPTION] & 0x3F;
3049
3050                         if (rtlhal->rfe_type == 4 &&
3051                             (rtlhal->external_pa_5g ||
3052                              rtlhal->external_pa_2g ||
3053                              rtlhal->external_lna_5g ||
3054                              rtlhal->external_lna_2g)) {
3055                                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
3056                                         rtlhal->rfe_type = 2;
3057                         }
3058                 }
3059         } else {
3060                 rtlhal->rfe_type = 0x04;
3061         }
3062
3063         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3064                  "RFE Type: 0x%2x\n", rtlhal->rfe_type);
3065 }
3066
3067 static void _rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3068                                               bool auto_load_fail, u8 *hwinfo)
3069 {
3070         struct rtl_priv *rtlpriv = rtl_priv(hw);
3071         u8 value;
3072
3073         if (!auto_load_fail) {
3074                 value = *(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION];
3075                 if (((value & 0xe0) >> 5) == 0x1)
3076                         rtlpriv->btcoexist.btc_info.btcoexist = 1;
3077                 else
3078                         rtlpriv->btcoexist.btc_info.btcoexist = 0;
3079                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3080
3081                 value = hwinfo[EEPROM_RF_BT_SETTING];
3082                 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3083         } else {
3084                 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3085                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3086                 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3087         }
3088         /*move BT_InitHalVars() to init_sw_vars*/
3089 }
3090
3091 static void _rtl8821ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3092                                               bool auto_load_fail, u8 *hwinfo)
3093 {
3094         struct rtl_priv *rtlpriv = rtl_priv(hw);
3095         u8 value;
3096         u32 tmpu_32;
3097
3098         if (!auto_load_fail) {
3099                 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
3100                 if (tmpu_32 & BIT(18))
3101                         rtlpriv->btcoexist.btc_info.btcoexist = 1;
3102                 else
3103                         rtlpriv->btcoexist.btc_info.btcoexist = 0;
3104                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3105
3106                 value = hwinfo[EEPROM_RF_BT_SETTING];
3107                 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3108         } else {
3109                 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3110                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3111                 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3112         }
3113         /*move BT_InitHalVars() to init_sw_vars*/
3114 }
3115
3116 static void _rtl8821ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_test)
3117 {
3118         struct rtl_priv *rtlpriv = rtl_priv(hw);
3119         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3120         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3121         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3122         u16 i, usvalue;
3123         u8 hwinfo[HWSET_MAX_SIZE];
3124         u16 eeprom_id;
3125
3126         if (b_pseudo_test) {
3127                 ;/* need add */
3128         }
3129
3130         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
3131                 rtl_efuse_shadow_map_update(hw);
3132                 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
3133                        HWSET_MAX_SIZE);
3134         } else if (rtlefuse->epromtype == EEPROM_93C46) {
3135                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3136                          "RTL819X Not boot from eeprom, check it !!");
3137         }
3138
3139         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP\n",
3140                       hwinfo, HWSET_MAX_SIZE);
3141
3142         eeprom_id = *((u16 *)&hwinfo[0]);
3143         if (eeprom_id != RTL_EEPROM_ID) {
3144                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3145                          "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
3146                 rtlefuse->autoload_failflag = true;
3147         } else {
3148                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
3149                 rtlefuse->autoload_failflag = false;
3150         }
3151
3152         if (rtlefuse->autoload_failflag) {
3153                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3154                          "RTL8812AE autoload_failflag, check it !!");
3155                 return;
3156         }
3157
3158         rtlefuse->eeprom_version = *(u8 *)&hwinfo[EEPROM_VERSION];
3159         if (rtlefuse->eeprom_version == 0xff)
3160                         rtlefuse->eeprom_version = 0;
3161
3162         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3163                  "EEPROM version: 0x%2x\n", rtlefuse->eeprom_version);
3164
3165         rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
3166         rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
3167         rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
3168         rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
3169         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3170                  "EEPROMId = 0x%4x\n", eeprom_id);
3171         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3172                  "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
3173         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3174                  "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
3175         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3176                  "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
3177         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3178                  "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
3179
3180         /*customer ID*/
3181         rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
3182         if (rtlefuse->eeprom_oemid == 0xFF)
3183                 rtlefuse->eeprom_oemid = 0;
3184
3185         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3186                  "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
3187
3188         for (i = 0; i < 6; i += 2) {
3189                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
3190                 *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue;
3191         }
3192
3193         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
3194                  "dev_addr: %pM\n", rtlefuse->dev_addr);
3195
3196         _rtl8821ae_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
3197                                                hwinfo);
3198
3199         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
3200                 _rtl8812ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag);
3201                 _rtl8812ae_read_bt_coexist_info_from_hwpg(hw,
3202                                 rtlefuse->autoload_failflag, hwinfo);
3203         } else {
3204                 _rtl8821ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag);
3205                 _rtl8821ae_read_bt_coexist_info_from_hwpg(hw,
3206                                 rtlefuse->autoload_failflag, hwinfo);
3207         }
3208
3209         _rtl8821ae_read_rfe_type(hw, hwinfo, rtlefuse->autoload_failflag);
3210         /*board type*/
3211         rtlefuse->board_type = ODM_BOARD_DEFAULT;
3212         if (rtlhal->external_lna_2g != 0)
3213                 rtlefuse->board_type |= ODM_BOARD_EXT_LNA;
3214         if (rtlhal->external_lna_5g != 0)
3215                 rtlefuse->board_type |= ODM_BOARD_EXT_LNA_5G;
3216         if (rtlhal->external_pa_2g != 0)
3217                 rtlefuse->board_type |= ODM_BOARD_EXT_PA;
3218         if (rtlhal->external_pa_5g != 0)
3219                 rtlefuse->board_type |= ODM_BOARD_EXT_PA_5G;
3220
3221         if (rtlpriv->btcoexist.btc_info.btcoexist == 1)
3222                 rtlefuse->board_type |= ODM_BOARD_BT;
3223
3224         rtlhal->board_type = rtlefuse->board_type;
3225         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3226                  "board_type = 0x%x\n", rtlefuse->board_type);
3227
3228         rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
3229         if (rtlefuse->eeprom_channelplan == 0xff)
3230                 rtlefuse->eeprom_channelplan = 0x7F;
3231
3232         /* set channel plan from efuse */
3233         rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
3234
3235         /*parse xtal*/
3236         rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8821AE];
3237         if (rtlefuse->crystalcap == 0xFF)
3238                 rtlefuse->crystalcap = 0x20;
3239
3240         rtlefuse->eeprom_thermalmeter = *(u8 *)&hwinfo[EEPROM_THERMAL_METER];
3241         if ((rtlefuse->eeprom_thermalmeter == 0xff) ||
3242             rtlefuse->autoload_failflag) {
3243                 rtlefuse->apk_thermalmeterignore = true;
3244                 rtlefuse->eeprom_thermalmeter = 0xff;
3245         }
3246
3247         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
3248         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3249                  "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
3250
3251         if (!rtlefuse->autoload_failflag) {
3252                 rtlefuse->antenna_div_cfg =
3253                   (hwinfo[EEPROM_RF_BOARD_OPTION] & 0x18) >> 3;
3254                 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xff)
3255                         rtlefuse->antenna_div_cfg = 0;
3256
3257                 if (rtlpriv->btcoexist.btc_info.btcoexist == 1 &&
3258                     rtlpriv->btcoexist.btc_info.ant_num == ANT_X1)
3259                         rtlefuse->antenna_div_cfg = 0;
3260
3261                 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
3262                 if (rtlefuse->antenna_div_type == 0xff)
3263                         rtlefuse->antenna_div_type = FIXED_HW_ANTDIV;
3264         } else {
3265                 rtlefuse->antenna_div_cfg = 0;
3266                 rtlefuse->antenna_div_type = 0;
3267         }
3268
3269         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3270                 "SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n",
3271                 rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type);
3272
3273         pcipriv->ledctl.led_opendrain = true;
3274
3275         if (rtlhal->oem_id == RT_CID_DEFAULT) {
3276                 switch (rtlefuse->eeprom_oemid) {
3277                 case RT_CID_DEFAULT:
3278                         break;
3279                 case EEPROM_CID_TOSHIBA:
3280                         rtlhal->oem_id = RT_CID_TOSHIBA;
3281                         break;
3282                 case EEPROM_CID_CCX:
3283                         rtlhal->oem_id = RT_CID_CCX;
3284                         break;
3285                 case EEPROM_CID_QMI:
3286                         rtlhal->oem_id = RT_CID_819X_QMI;
3287                         break;
3288                 case EEPROM_CID_WHQL:
3289                         break;
3290                 default:
3291                         break;
3292                 }
3293         }
3294 }
3295
3296 /*static void _rtl8821ae_hal_customized_behavior(struct ieee80211_hw *hw)
3297 {
3298         struct rtl_priv *rtlpriv = rtl_priv(hw);
3299         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3300         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3301
3302         pcipriv->ledctl.led_opendrain = true;
3303         switch (rtlhal->oem_id) {
3304         case RT_CID_819X_HP:
3305                 pcipriv->ledctl.led_opendrain = true;
3306                 break;
3307         case RT_CID_819X_LENOVO:
3308         case RT_CID_DEFAULT:
3309         case RT_CID_TOSHIBA:
3310         case RT_CID_CCX:
3311         case RT_CID_819X_ACER:
3312         case RT_CID_WHQL:
3313         default:
3314                 break;
3315         }
3316         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
3317                  "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
3318 }*/
3319
3320 void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw)
3321 {
3322         struct rtl_priv *rtlpriv = rtl_priv(hw);
3323         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3324         struct rtl_phy *rtlphy = &rtlpriv->phy;
3325         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3326         u8 tmp_u1b;
3327
3328         rtlhal->version = _rtl8821ae_read_chip_version(hw);
3329         if (get_rf_type(rtlphy) == RF_1T1R)
3330                 rtlpriv->dm.rfpath_rxenable[0] = true;
3331         else
3332                 rtlpriv->dm.rfpath_rxenable[0] =
3333                     rtlpriv->dm.rfpath_rxenable[1] = true;
3334         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
3335                                                 rtlhal->version);
3336
3337         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
3338         if (tmp_u1b & BIT(4)) {
3339                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
3340                 rtlefuse->epromtype = EEPROM_93C46;
3341         } else {
3342                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
3343                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
3344         }
3345
3346         if (tmp_u1b & BIT(5)) {
3347                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
3348                 rtlefuse->autoload_failflag = false;
3349                 _rtl8821ae_read_adapter_info(hw, false);
3350         } else {
3351                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
3352         }
3353         /*hal_ReadRFType_8812A()*/
3354         /* _rtl8821ae_hal_customized_behavior(hw); */
3355 }
3356
3357 static void rtl8821ae_update_hal_rate_table(struct ieee80211_hw *hw,
3358                 struct ieee80211_sta *sta)
3359 {
3360         struct rtl_priv *rtlpriv = rtl_priv(hw);
3361         struct rtl_phy *rtlphy = &rtlpriv->phy;
3362         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3363         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3364         u32 ratr_value;
3365         u8 ratr_index = 0;
3366         u8 b_nmode = mac->ht_enable;
3367         u8 mimo_ps = IEEE80211_SMPS_OFF;
3368         u16 shortgi_rate;
3369         u32 tmp_ratr_value;
3370         u8 curtxbw_40mhz = mac->bw_40;
3371         u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3372                                 1 : 0;
3373         u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3374                                 1 : 0;
3375         enum wireless_mode wirelessmode = mac->mode;
3376
3377         if (rtlhal->current_bandtype == BAND_ON_5G)
3378                 ratr_value = sta->supp_rates[1] << 4;
3379         else
3380                 ratr_value = sta->supp_rates[0];
3381         if (mac->opmode == NL80211_IFTYPE_ADHOC)
3382                 ratr_value = 0xfff;
3383         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
3384                         sta->ht_cap.mcs.rx_mask[0] << 12);
3385         switch (wirelessmode) {
3386         case WIRELESS_MODE_B:
3387                 if (ratr_value & 0x0000000c)
3388                         ratr_value &= 0x0000000d;
3389                 else
3390                         ratr_value &= 0x0000000f;
3391                 break;
3392         case WIRELESS_MODE_G:
3393                 ratr_value &= 0x00000FF5;
3394                 break;
3395         case WIRELESS_MODE_N_24G:
3396         case WIRELESS_MODE_N_5G:
3397                 b_nmode = 1;
3398                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
3399                         ratr_value &= 0x0007F005;
3400                 } else {
3401                         u32 ratr_mask;
3402
3403                         if (get_rf_type(rtlphy) == RF_1T2R ||
3404                             get_rf_type(rtlphy) == RF_1T1R)
3405                                 ratr_mask = 0x000ff005;
3406                         else
3407                                 ratr_mask = 0x0f0ff005;
3408
3409                         ratr_value &= ratr_mask;
3410                 }
3411                 break;
3412         default:
3413                 if (rtlphy->rf_type == RF_1T2R)
3414                         ratr_value &= 0x000ff0ff;
3415                 else
3416                         ratr_value &= 0x0f0ff0ff;
3417
3418                 break;
3419         }
3420
3421         if ((rtlpriv->btcoexist.bt_coexistence) &&
3422              (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
3423              (rtlpriv->btcoexist.bt_cur_state) &&
3424              (rtlpriv->btcoexist.bt_ant_isolation) &&
3425              ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
3426              (rtlpriv->btcoexist.bt_service == BT_BUSY)))
3427                 ratr_value &= 0x0fffcfc0;
3428         else
3429                 ratr_value &= 0x0FFFFFFF;
3430
3431         if (b_nmode && ((curtxbw_40mhz &&
3432                          b_curshortgi_40mhz) || (!curtxbw_40mhz &&
3433                                                  b_curshortgi_20mhz))) {
3434                 ratr_value |= 0x10000000;
3435                 tmp_ratr_value = (ratr_value >> 12);
3436
3437                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
3438                         if ((1 << shortgi_rate) & tmp_ratr_value)
3439                                 break;
3440                 }
3441
3442                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
3443                     (shortgi_rate << 4) | (shortgi_rate);
3444         }
3445
3446         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
3447
3448         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
3449                  "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
3450 }
3451
3452 static u8 _rtl8821ae_mrate_idx_to_arfr_id(
3453         struct ieee80211_hw *hw, u8 rate_index,
3454         enum wireless_mode wirelessmode)
3455 {
3456         struct rtl_priv *rtlpriv = rtl_priv(hw);
3457         struct rtl_phy *rtlphy = &rtlpriv->phy;
3458         u8 ret = 0;
3459         switch (rate_index) {
3460         case RATR_INX_WIRELESS_NGB:
3461                 if (rtlphy->rf_type == RF_1T1R)
3462                         ret = 1;
3463                 else
3464                         ret = 0;
3465                 ; break;
3466         case RATR_INX_WIRELESS_N:
3467         case RATR_INX_WIRELESS_NG:
3468                 if (rtlphy->rf_type == RF_1T1R)
3469                         ret = 5;
3470                 else
3471                         ret = 4;
3472                 ; break;
3473         case RATR_INX_WIRELESS_NB:
3474                 if (rtlphy->rf_type == RF_1T1R)
3475                         ret = 3;
3476                 else
3477                         ret = 2;
3478                 ; break;
3479         case RATR_INX_WIRELESS_GB:
3480                 ret = 6;
3481                 break;
3482         case RATR_INX_WIRELESS_G:
3483                 ret = 7;
3484                 break;
3485         case RATR_INX_WIRELESS_B:
3486                 ret = 8;
3487                 break;
3488         case RATR_INX_WIRELESS_MC:
3489                 if ((wirelessmode == WIRELESS_MODE_B)
3490                         || (wirelessmode == WIRELESS_MODE_G)
3491                         || (wirelessmode == WIRELESS_MODE_N_24G)
3492                         || (wirelessmode == WIRELESS_MODE_AC_24G))
3493                         ret = 6;
3494                 else
3495                         ret = 7;
3496         case RATR_INX_WIRELESS_AC_5N:
3497                 if (rtlphy->rf_type == RF_1T1R)
3498                         ret = 10;
3499                 else
3500                         ret = 9;
3501                 break;
3502         case RATR_INX_WIRELESS_AC_24N:
3503                 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) {
3504                         if (rtlphy->rf_type == RF_1T1R)
3505                                 ret = 10;
3506                         else
3507                                 ret = 9;
3508                 } else {
3509                         if (rtlphy->rf_type == RF_1T1R)
3510                                 ret = 11;
3511                         else
3512                                 ret = 12;
3513                 }
3514                 break;
3515         default:
3516                 ret = 0; break;
3517         }
3518         return ret;
3519 }
3520
3521 static u32 _rtl8821ae_rate_to_bitmap_2ssvht(__le16 vht_rate)
3522 {
3523         u8 i, j, tmp_rate;
3524         u32 rate_bitmap = 0;
3525
3526         for (i = j = 0; i < 4; i += 2, j += 10) {
3527                 tmp_rate = (le16_to_cpu(vht_rate) >> i) & 3;
3528
3529                 switch (tmp_rate) {
3530                 case 2:
3531                         rate_bitmap = rate_bitmap | (0x03ff << j);
3532                         break;
3533                 case 1:
3534                         rate_bitmap = rate_bitmap | (0x01ff << j);
3535                         break;
3536                 case 0:
3537                         rate_bitmap = rate_bitmap | (0x00ff << j);
3538                         break;
3539                 default:
3540                         break;
3541                 }
3542         }
3543
3544         return rate_bitmap;
3545 }
3546
3547 static u32 _rtl8821ae_set_ra_vht_ratr_bitmap(struct ieee80211_hw *hw,
3548                                              enum wireless_mode wirelessmode,
3549                                              u32 ratr_bitmap)
3550 {
3551         struct rtl_priv *rtlpriv = rtl_priv(hw);
3552         struct rtl_phy *rtlphy = &rtlpriv->phy;
3553         u32 ret_bitmap = ratr_bitmap;
3554
3555         if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40
3556                 || rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
3557                 ret_bitmap = ratr_bitmap;
3558         else if (wirelessmode == WIRELESS_MODE_AC_5G
3559                 || wirelessmode == WIRELESS_MODE_AC_24G) {
3560                 if (rtlphy->rf_type == RF_1T1R)
3561                         ret_bitmap = ratr_bitmap & (~BIT21);
3562                 else
3563                         ret_bitmap = ratr_bitmap & (~(BIT31|BIT21));
3564         }
3565
3566         return ret_bitmap;
3567 }
3568
3569 static u8 _rtl8821ae_get_vht_eni(enum wireless_mode wirelessmode,
3570                         u32 ratr_bitmap)
3571 {
3572         u8 ret = 0;
3573         if (wirelessmode < WIRELESS_MODE_N_24G)
3574                 ret =  0;
3575         else if (wirelessmode == WIRELESS_MODE_AC_24G) {
3576                 if (ratr_bitmap & 0xfff00000)   /* Mix , 2SS */
3577                         ret = 3;
3578                 else                                    /* Mix, 1SS */
3579                         ret = 2;
3580         } else if (wirelessmode == WIRELESS_MODE_AC_5G) {
3581                         ret = 1;
3582         } /* VHT */
3583
3584         return ret << 4;
3585 }
3586
3587 static u8 _rtl8821ae_get_ra_ldpc(struct ieee80211_hw *hw,
3588                              u8 mac_id, struct rtl_sta_info *sta_entry,
3589                              enum wireless_mode wirelessmode)
3590 {
3591         u8 b_ldpc = 0;
3592         /*not support ldpc, do not open*/
3593         return b_ldpc << 2;
3594 }
3595
3596 static u8 _rtl8821ae_get_ra_rftype(struct ieee80211_hw *hw,
3597                           enum wireless_mode wirelessmode,
3598                           u32 ratr_bitmap)
3599 {
3600         struct rtl_priv *rtlpriv = rtl_priv(hw);
3601         struct rtl_phy *rtlphy = &rtlpriv->phy;
3602         u8 rf_type = RF_1T1R;
3603
3604         if (rtlphy->rf_type == RF_1T1R)
3605                 rf_type = RF_1T1R;
3606         else if (wirelessmode == WIRELESS_MODE_AC_5G
3607                 || wirelessmode == WIRELESS_MODE_AC_24G
3608                 || wirelessmode == WIRELESS_MODE_AC_ONLY) {
3609                 if (ratr_bitmap & 0xffc00000)
3610                         rf_type = RF_2T2R;
3611         } else if (wirelessmode == WIRELESS_MODE_N_5G
3612                 || wirelessmode == WIRELESS_MODE_N_24G) {
3613                 if (ratr_bitmap & 0xfff00000)
3614                         rf_type = RF_2T2R;
3615         }
3616
3617         return rf_type;
3618 }
3619
3620 static bool _rtl8821ae_get_ra_shortgi(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
3621                               u8 mac_id)
3622 {
3623         bool b_short_gi = false;
3624         u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3625                                 1 : 0;
3626         u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3627                                 1 : 0;
3628         u8 b_curshortgi_80mhz = 0;
3629         b_curshortgi_80mhz = (sta->vht_cap.cap &
3630                               IEEE80211_VHT_CAP_SHORT_GI_80) ? 1 : 0;
3631
3632         if (mac_id == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST)
3633                         b_short_gi = false;
3634
3635         if (b_curshortgi_40mhz || b_curshortgi_80mhz
3636                 || b_curshortgi_20mhz)
3637                 b_short_gi = true;
3638
3639         return b_short_gi;
3640 }
3641
3642 static void rtl8821ae_update_hal_rate_mask(struct ieee80211_hw *hw,
3643                 struct ieee80211_sta *sta, u8 rssi_level)
3644 {
3645         struct rtl_priv *rtlpriv = rtl_priv(hw);
3646         struct rtl_phy *rtlphy = &rtlpriv->phy;
3647         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3648         struct rtl_sta_info *sta_entry = NULL;
3649         u32 ratr_bitmap;
3650         u8 ratr_index;
3651         enum wireless_mode wirelessmode = 0;
3652         u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
3653                                 ? 1 : 0;
3654         bool b_shortgi = false;
3655         u8 rate_mask[7];
3656         u8 macid = 0;
3657         u8 mimo_ps = IEEE80211_SMPS_OFF;
3658         u8 rf_type;
3659
3660         sta_entry = (struct rtl_sta_info *)sta->drv_priv;
3661         wirelessmode = sta_entry->wireless_mode;
3662
3663         RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD,
3664                  "wireless mode = 0x%x\n", wirelessmode);
3665         if (mac->opmode == NL80211_IFTYPE_STATION ||
3666                 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
3667                 curtxbw_40mhz = mac->bw_40;
3668         } else if (mac->opmode == NL80211_IFTYPE_AP ||
3669                 mac->opmode == NL80211_IFTYPE_ADHOC)
3670                 macid = sta->aid + 1;
3671         if (wirelessmode == WIRELESS_MODE_N_5G ||
3672             wirelessmode == WIRELESS_MODE_AC_5G ||
3673             wirelessmode == WIRELESS_MODE_A)
3674                 ratr_bitmap = sta->supp_rates[NL80211_BAND_5GHZ] << 4;
3675         else
3676                 ratr_bitmap = sta->supp_rates[NL80211_BAND_2GHZ];
3677
3678         if (mac->opmode == NL80211_IFTYPE_ADHOC)
3679                 ratr_bitmap = 0xfff;
3680
3681         if (wirelessmode == WIRELESS_MODE_N_24G
3682                 || wirelessmode == WIRELESS_MODE_N_5G)
3683                 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
3684                                 sta->ht_cap.mcs.rx_mask[0] << 12);
3685         else if (wirelessmode == WIRELESS_MODE_AC_24G
3686                 || wirelessmode == WIRELESS_MODE_AC_5G
3687                 || wirelessmode == WIRELESS_MODE_AC_ONLY)
3688                 ratr_bitmap |= _rtl8821ae_rate_to_bitmap_2ssvht(
3689                                 sta->vht_cap.vht_mcs.rx_mcs_map) << 12;
3690
3691         b_shortgi = _rtl8821ae_get_ra_shortgi(hw, sta, macid);
3692         rf_type = _rtl8821ae_get_ra_rftype(hw, wirelessmode, ratr_bitmap);
3693
3694 /*mac id owner*/
3695         switch (wirelessmode) {
3696         case WIRELESS_MODE_B:
3697                 ratr_index = RATR_INX_WIRELESS_B;
3698                 if (ratr_bitmap & 0x0000000c)
3699                         ratr_bitmap &= 0x0000000d;
3700                 else
3701                         ratr_bitmap &= 0x0000000f;
3702                 break;
3703         case WIRELESS_MODE_G:
3704                 ratr_index = RATR_INX_WIRELESS_GB;
3705
3706                 if (rssi_level == 1)
3707                         ratr_bitmap &= 0x00000f00;
3708                 else if (rssi_level == 2)
3709                         ratr_bitmap &= 0x00000ff0;
3710                 else
3711                         ratr_bitmap &= 0x00000ff5;
3712                 break;
3713         case WIRELESS_MODE_A:
3714                 ratr_index = RATR_INX_WIRELESS_G;
3715                 ratr_bitmap &= 0x00000ff0;
3716                 break;
3717         case WIRELESS_MODE_N_24G:
3718         case WIRELESS_MODE_N_5G:
3719                 if (wirelessmode == WIRELESS_MODE_N_24G)
3720                         ratr_index = RATR_INX_WIRELESS_NGB;
3721                 else
3722                         ratr_index = RATR_INX_WIRELESS_NG;
3723
3724                 if (mimo_ps == IEEE80211_SMPS_STATIC
3725                         || mimo_ps == IEEE80211_SMPS_DYNAMIC) {
3726                         if (rssi_level == 1)
3727                                 ratr_bitmap &= 0x000f0000;
3728                         else if (rssi_level == 2)
3729                                 ratr_bitmap &= 0x000ff000;
3730                         else
3731                                 ratr_bitmap &= 0x000ff005;
3732                 } else {
3733                         if (rf_type == RF_1T1R) {
3734                                 if (curtxbw_40mhz) {
3735                                         if (rssi_level == 1)
3736                                                 ratr_bitmap &= 0x000f0000;
3737                                         else if (rssi_level == 2)
3738                                                 ratr_bitmap &= 0x000ff000;
3739                                         else
3740                                                 ratr_bitmap &= 0x000ff015;
3741                                 } else {
3742                                         if (rssi_level == 1)
3743                                                 ratr_bitmap &= 0x000f0000;
3744                                         else if (rssi_level == 2)
3745                                                 ratr_bitmap &= 0x000ff000;
3746                                         else
3747                                                 ratr_bitmap &= 0x000ff005;
3748                                 }
3749                         } else {
3750                                 if (curtxbw_40mhz) {
3751                                         if (rssi_level == 1)
3752                                                 ratr_bitmap &= 0x0fff0000;
3753                                         else if (rssi_level == 2)
3754                                                 ratr_bitmap &= 0x0ffff000;
3755                                         else
3756                                                 ratr_bitmap &= 0x0ffff015;
3757                                 } else {
3758                                         if (rssi_level == 1)
3759                                                 ratr_bitmap &= 0x0fff0000;
3760                                         else if (rssi_level == 2)
3761                                                 ratr_bitmap &= 0x0ffff000;
3762                                         else
3763                                                 ratr_bitmap &= 0x0ffff005;
3764                                 }
3765                         }
3766                 }
3767                 break;
3768
3769         case WIRELESS_MODE_AC_24G:
3770                 ratr_index = RATR_INX_WIRELESS_AC_24N;
3771                 if (rssi_level == 1)
3772                         ratr_bitmap &= 0xfc3f0000;
3773                 else if (rssi_level == 2)
3774                         ratr_bitmap &= 0xfffff000;
3775                 else
3776                         ratr_bitmap &= 0xffffffff;
3777                 break;
3778
3779         case WIRELESS_MODE_AC_5G:
3780                 ratr_index = RATR_INX_WIRELESS_AC_5N;
3781
3782                 if (rf_type == RF_1T1R) {
3783                         if (rssi_level == 1)    /*add by Gary for ac-series*/
3784                                 ratr_bitmap &= 0x003f8000;
3785                         else if (rssi_level == 2)
3786                                 ratr_bitmap &= 0x003ff000;
3787                         else
3788                                 ratr_bitmap &= 0x003ff010;
3789                 } else {
3790                         if (rssi_level == 1)
3791                                 ratr_bitmap &= 0xfe3f8000;
3792                         else if (rssi_level == 2)
3793                                 ratr_bitmap &= 0xfffff000;
3794                         else
3795                                 ratr_bitmap &= 0xfffff010;
3796                 }
3797                 break;
3798
3799         default:
3800                 ratr_index = RATR_INX_WIRELESS_NGB;
3801
3802                 if (rf_type == RF_1T2R)
3803                         ratr_bitmap &= 0x000ff0ff;
3804                 else
3805                         ratr_bitmap &= 0x0f8ff0ff;
3806                 break;
3807         }
3808
3809         ratr_index = _rtl8821ae_mrate_idx_to_arfr_id(hw, ratr_index, wirelessmode);
3810         sta_entry->ratr_index = ratr_index;
3811         ratr_bitmap = _rtl8821ae_set_ra_vht_ratr_bitmap(hw, wirelessmode,
3812                                                         ratr_bitmap);
3813
3814         RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD,
3815                  "ratr_bitmap :%x\n", ratr_bitmap);
3816
3817         /* *(u32 *)& rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
3818                                        (ratr_index << 28)); */
3819
3820         rate_mask[0] = macid;
3821         rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00);
3822         rate_mask[2] = rtlphy->current_chan_bw
3823                            | _rtl8821ae_get_vht_eni(wirelessmode, ratr_bitmap)
3824                            | _rtl8821ae_get_ra_ldpc(hw, macid, sta_entry, wirelessmode);
3825
3826         rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
3827         rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
3828         rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
3829         rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
3830
3831         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
3832                  "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
3833                  ratr_index, ratr_bitmap,
3834                  rate_mask[0], rate_mask[1],
3835                  rate_mask[2], rate_mask[3],
3836                  rate_mask[4], rate_mask[5],
3837                  rate_mask[6]);
3838         rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_RA_MASK, 7, rate_mask);
3839         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
3840 }
3841
3842 void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
3843                 struct ieee80211_sta *sta, u8 rssi_level)
3844 {
3845         struct rtl_priv *rtlpriv = rtl_priv(hw);
3846         if (rtlpriv->dm.useramask)
3847                 rtl8821ae_update_hal_rate_mask(hw, sta, rssi_level);
3848         else
3849                 /*RT_TRACE(rtlpriv, COMP_RATR,DBG_LOUD,
3850                            "rtl8821ae_update_hal_rate_tbl() Error! 8821ae FW RA Only");*/
3851                 rtl8821ae_update_hal_rate_table(hw, sta);
3852 }
3853
3854 void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw)
3855 {
3856         struct rtl_priv *rtlpriv = rtl_priv(hw);
3857         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3858         u8 wireless_mode = mac->mode;
3859         u8 sifs_timer, r2t_sifs;
3860
3861         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
3862                                       (u8 *)&mac->slot_time);
3863         if (wireless_mode == WIRELESS_MODE_G)
3864                 sifs_timer = 0x0a;
3865         else
3866                 sifs_timer = 0x0e;
3867         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
3868
3869         r2t_sifs = 0xa;
3870
3871         if (wireless_mode == WIRELESS_MODE_AC_5G &&
3872             (mac->vht_ldpc_cap & LDPC_VHT_ENABLE_RX) &&
3873             (mac->vht_stbc_cap & STBC_VHT_ENABLE_RX)) {
3874                 if (mac->vendor == PEER_ATH)
3875                         r2t_sifs = 0x8;
3876                 else
3877                         r2t_sifs = 0xa;
3878         } else if (wireless_mode == WIRELESS_MODE_AC_5G) {
3879                 r2t_sifs = 0xa;
3880         }
3881
3882         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_R2T_SIFS, (u8 *)&r2t_sifs);
3883 }
3884
3885 bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
3886 {
3887         struct rtl_priv *rtlpriv = rtl_priv(hw);
3888         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3889         struct rtl_phy *rtlphy = &rtlpriv->phy;
3890         enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
3891         u8 u1tmp = 0;
3892         bool b_actuallyset = false;
3893
3894         if (rtlpriv->rtlhal.being_init_adapter)
3895                 return false;
3896
3897         if (ppsc->swrf_processing)
3898                 return false;
3899
3900         spin_lock(&rtlpriv->locks.rf_ps_lock);
3901         if (ppsc->rfchange_inprogress) {
3902                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3903                 return false;
3904         } else {
3905                 ppsc->rfchange_inprogress = true;
3906                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3907         }
3908
3909         cur_rfstate = ppsc->rfpwr_state;
3910
3911         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
3912                         rtl_read_byte(rtlpriv,
3913                                         REG_GPIO_IO_SEL_2) & ~(BIT(1)));
3914
3915         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
3916
3917         if (rtlphy->polarity_ctl)
3918                 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
3919         else
3920                 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
3921
3922         if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
3923                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3924                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
3925
3926                 e_rfpowerstate_toset = ERFON;
3927                 ppsc->hwradiooff = false;
3928                 b_actuallyset = true;
3929         } else if ((!ppsc->hwradiooff)
3930                    && (e_rfpowerstate_toset == ERFOFF)) {
3931                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3932                          "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
3933
3934                 e_rfpowerstate_toset = ERFOFF;
3935                 ppsc->hwradiooff = true;
3936                 b_actuallyset = true;
3937         }
3938
3939         if (b_actuallyset) {
3940                 spin_lock(&rtlpriv->locks.rf_ps_lock);
3941                 ppsc->rfchange_inprogress = false;
3942                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3943         } else {
3944                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
3945                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3946
3947                 spin_lock(&rtlpriv->locks.rf_ps_lock);
3948                 ppsc->rfchange_inprogress = false;
3949                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3950         }
3951
3952         *valid = 1;
3953         return !ppsc->hwradiooff;
3954 }
3955
3956 void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index,
3957                      u8 *p_macaddr, bool is_group, u8 enc_algo,
3958                      bool is_wepkey, bool clear_all)
3959 {
3960         struct rtl_priv *rtlpriv = rtl_priv(hw);
3961         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3962         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3963         u8 *macaddr = p_macaddr;
3964         u32 entry_id = 0;
3965         bool is_pairwise = false;
3966
3967         static u8 cam_const_addr[4][6] = {
3968                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
3969                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
3970                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
3971                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
3972         };
3973         static u8 cam_const_broad[] = {
3974                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
3975         };
3976
3977         if (clear_all) {
3978                 u8 idx = 0;
3979                 u8 cam_offset = 0;
3980                 u8 clear_number = 5;
3981
3982                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
3983
3984                 for (idx = 0; idx < clear_number; idx++) {
3985                         rtl_cam_mark_invalid(hw, cam_offset + idx);
3986                         rtl_cam_empty_entry(hw, cam_offset + idx);
3987
3988                         if (idx < 5) {
3989                                 memset(rtlpriv->sec.key_buf[idx], 0,
3990                                        MAX_KEY_LEN);
3991                                 rtlpriv->sec.key_len[idx] = 0;
3992                         }
3993                 }
3994         } else {
3995                 switch (enc_algo) {
3996                 case WEP40_ENCRYPTION:
3997                         enc_algo = CAM_WEP40;
3998                         break;
3999                 case WEP104_ENCRYPTION:
4000                         enc_algo = CAM_WEP104;
4001                         break;
4002                 case TKIP_ENCRYPTION:
4003                         enc_algo = CAM_TKIP;
4004                         break;
4005                 case AESCCMP_ENCRYPTION:
4006                         enc_algo = CAM_AES;
4007                         break;
4008                 default:
4009                         RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
4010                                  "switch case not process\n");
4011                         enc_algo = CAM_TKIP;
4012                         break;
4013                 }
4014
4015                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
4016                         macaddr = cam_const_addr[key_index];
4017                         entry_id = key_index;
4018                 } else {
4019                         if (is_group) {
4020                                 macaddr = cam_const_broad;
4021                                 entry_id = key_index;
4022                         } else {
4023                                 if (mac->opmode == NL80211_IFTYPE_AP) {
4024                                         entry_id = rtl_cam_get_free_entry(hw, p_macaddr);
4025                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
4026                                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_EMERG,
4027                                                          "Can not find free hwsecurity cam entry\n");
4028                                                 return;
4029                                         }
4030                                 } else {
4031                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
4032                                 }
4033
4034                                 key_index = PAIRWISE_KEYIDX;
4035                                 is_pairwise = true;
4036                         }
4037                 }
4038
4039                 if (rtlpriv->sec.key_len[key_index] == 0) {
4040                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
4041                                  "delete one entry, entry_id is %d\n",
4042                                  entry_id);
4043                         if (mac->opmode == NL80211_IFTYPE_AP)
4044                                 rtl_cam_del_entry(hw, p_macaddr);
4045                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
4046                 } else {
4047                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
4048                                  "add one entry\n");
4049                         if (is_pairwise) {
4050                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
4051                                          "set Pairwise key\n");
4052
4053                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
4054                                                       entry_id, enc_algo,
4055                                                       CAM_CONFIG_NO_USEDK,
4056                                                       rtlpriv->sec.key_buf[key_index]);
4057                         } else {
4058                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
4059                                          "set group key\n");
4060
4061                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
4062                                         rtl_cam_add_one_entry(hw,
4063                                                         rtlefuse->dev_addr,
4064                                                         PAIRWISE_KEYIDX,
4065                                                         CAM_PAIRWISE_KEY_POSITION,
4066                                                         enc_algo,
4067                                                         CAM_CONFIG_NO_USEDK,
4068                                                         rtlpriv->sec.key_buf
4069                                                         [entry_id]);
4070                                 }
4071
4072                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
4073                                                 entry_id, enc_algo,
4074                                                 CAM_CONFIG_NO_USEDK,
4075                                                 rtlpriv->sec.key_buf[entry_id]);
4076                         }
4077                 }
4078         }
4079 }
4080
4081 void rtl8821ae_bt_reg_init(struct ieee80211_hw *hw)
4082 {
4083         struct rtl_priv *rtlpriv = rtl_priv(hw);
4084
4085         /* 0:Low, 1:High, 2:From Efuse. */
4086         rtlpriv->btcoexist.reg_bt_iso = 2;
4087         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
4088         rtlpriv->btcoexist.reg_bt_sco = 3;
4089         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
4090         rtlpriv->btcoexist.reg_bt_sco = 0;
4091 }
4092
4093 void rtl8821ae_bt_hw_init(struct ieee80211_hw *hw)
4094 {
4095         struct rtl_priv *rtlpriv = rtl_priv(hw);
4096
4097         if (rtlpriv->cfg->ops->get_btc_status())
4098                 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
4099 }
4100
4101 void rtl8821ae_suspend(struct ieee80211_hw *hw)
4102 {
4103 }
4104
4105 void rtl8821ae_resume(struct ieee80211_hw *hw)
4106 {
4107 }
4108
4109 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
4110 void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw,
4111         bool allow_all_da, bool write_into_reg)
4112 {
4113         struct rtl_priv *rtlpriv = rtl_priv(hw);
4114         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
4115
4116         if (allow_all_da) /* Set BIT0 */
4117                 rtlpci->receive_config |= RCR_AAP;
4118         else /* Clear BIT0 */
4119                 rtlpci->receive_config &= ~RCR_AAP;
4120
4121         if (write_into_reg)
4122                 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
4123
4124         RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
4125                 "receive_config=0x%08X, write_into_reg=%d\n",
4126                 rtlpci->receive_config, write_into_reg);
4127 }
4128
4129 /* WKFMCAMAddAllEntry8812 */
4130 void rtl8821ae_add_wowlan_pattern(struct ieee80211_hw *hw,
4131                                   struct rtl_wow_pattern *rtl_pattern,
4132                                   u8 index)
4133 {
4134         struct rtl_priv *rtlpriv = rtl_priv(hw);
4135         u32 cam = 0;
4136         u8 addr = 0;
4137         u16 rxbuf_addr;
4138         u8 tmp, count = 0;
4139         u16 cam_start;
4140         u16 offset;
4141
4142         /* Count the WFCAM entry start offset. */
4143
4144         /* RX page size = 128 byte */
4145         offset = MAX_RX_DMA_BUFFER_SIZE_8812 / 128;
4146         /* We should start from the boundry */
4147         cam_start = offset * 128;
4148
4149         /* Enable Rx packet buffer access. */
4150         rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
4151         for (addr = 0; addr < WKFMCAM_ADDR_NUM; addr++) {
4152                 /* Set Rx packet buffer offset.
4153                  * RxBufer pointer increases 1,
4154                  * we can access 8 bytes in Rx packet buffer.
4155                  * CAM start offset (unit: 1 byte) =  index*WKFMCAM_SIZE
4156                  * RxBufer addr = (CAM start offset +
4157                  *                 per entry offset of a WKFM CAM)/8
4158                  *      * index: The index of the wake up frame mask
4159                  *      * WKFMCAM_SIZE: the total size of one WKFM CAM
4160                  *      * per entry offset of a WKFM CAM: Addr*4 bytes
4161                  */
4162                 rxbuf_addr = (cam_start + index * WKFMCAM_SIZE + addr * 4) >> 3;
4163                 /* Set R/W start offset */
4164                 rtl_write_word(rtlpriv, REG_PKTBUF_DBG_CTRL, rxbuf_addr);
4165
4166                 if (addr == 0) {
4167                         cam = BIT(31) | rtl_pattern->crc;
4168
4169                         if (rtl_pattern->type == UNICAST_PATTERN)
4170                                 cam |= BIT(24);
4171                         else if (rtl_pattern->type == MULTICAST_PATTERN)
4172                                 cam |= BIT(25);
4173                         else if (rtl_pattern->type == BROADCAST_PATTERN)
4174                                 cam |= BIT(26);
4175
4176                         rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4177                         RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4178                                  "WRITE entry[%d] 0x%x: %x\n", addr,
4179                                   REG_PKTBUF_DBG_DATA_L, cam);
4180
4181                         /* Write to Rx packet buffer. */
4182                         rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4183                 } else if (addr == 2 || addr == 4) {/* WKFM[127:0] */
4184                         cam = rtl_pattern->mask[addr - 2];
4185
4186                         rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4187                         RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4188                                  "WRITE entry[%d] 0x%x: %x\n", addr,
4189                                   REG_PKTBUF_DBG_DATA_L, cam);
4190
4191                         rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4192                 } else if (addr == 3 || addr == 5) {/* WKFM[127:0] */
4193                         cam = rtl_pattern->mask[addr - 2];
4194
4195                         rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_H, cam);
4196                         RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4197                                  "WRITE entry[%d] 0x%x: %x\n", addr,
4198                                   REG_PKTBUF_DBG_DATA_H, cam);
4199
4200                         rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0xf001);
4201                 }
4202
4203                 count = 0;
4204                 do {
4205                         tmp = rtl_read_byte(rtlpriv, REG_RXPKTBUF_CTRL);
4206                         udelay(2);
4207                         count++;
4208                 } while (tmp && count < 100);
4209
4210                 RT_ASSERT((count < 100),
4211                           "Write wake up frame mask FAIL %d value!\n", tmp);
4212         }
4213         /* Disable Rx packet buffer access. */
4214         rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL,
4215                        DISABLE_TRXPKT_BUF_ACCESS);
4216 }