drivers/pinctrl/sh-pfc/pfc-r8a7779.c

   1 /*
   2  * r8a7779 processor support - PFC hardware block
   3  *
   4  * Copyright (C) 2011, 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Magnus Damm
   6  * Copyright (C) 2013  Cogent Embedded, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21
  22 #include <linux/kernel.h>
  23
  24 #include "sh_pfc.h"
  25
  26 #define PORT_GP_9(bank, fn, sfx)                                        \
  27         PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx),       \
  28         PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx),       \
  29         PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx),       \
  30         PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx),       \
  31         PORT_GP_1(bank, 8, fn, sfx)
  32
  33 #define CPU_ALL_PORT(fn, sfx)                                           \
  34         PORT_GP_32(0, fn, sfx),                                         \
  35         PORT_GP_32(1, fn, sfx),                                         \
  36         PORT_GP_32(2, fn, sfx),                                         \
  37         PORT_GP_32(3, fn, sfx),                                         \
  38         PORT_GP_32(4, fn, sfx),                                         \
  39         PORT_GP_32(5, fn, sfx),                                         \
  40         PORT_GP_9(6, fn, sfx)
  41
  42 enum {
  43         PINMUX_RESERVED = 0,
  44
  45         PINMUX_DATA_BEGIN,
  46         GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */
  47         PINMUX_DATA_END,
  48
  49         PINMUX_FUNCTION_BEGIN,
  50         GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */
  51
  52         /* GPSR0 */
  53         FN_AVS1, FN_AVS2, FN_IP0_7_6, FN_A17,
  54         FN_A18, FN_A19, FN_IP0_9_8, FN_IP0_11_10,
  55         FN_IP0_13_12, FN_IP0_15_14, FN_IP0_18_16, FN_IP0_22_19,
  56         FN_IP0_24_23, FN_IP0_25, FN_IP0_27_26, FN_IP1_1_0,
  57         FN_IP1_3_2, FN_IP1_6_4, FN_IP1_10_7, FN_IP1_14_11,
  58         FN_IP1_18_15, FN_IP0_5_3, FN_IP0_30_28, FN_IP2_18_16,
  59         FN_IP2_21_19, FN_IP2_30_28, FN_IP3_2_0, FN_IP3_11_9,
  60         FN_IP3_14_12, FN_IP3_22_21, FN_IP3_26_24, FN_IP3_31_29,
  61
  62         /* GPSR1 */
  63         FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, FN_IP4_10_8,
  64         FN_IP4_11, FN_IP4_12, FN_IP4_13, FN_IP4_14,
  65         FN_IP4_15, FN_IP4_16, FN_IP4_19_17, FN_IP4_22_20,
  66         FN_IP4_23, FN_IP4_24, FN_IP4_25, FN_IP4_26,
  67         FN_IP4_27, FN_IP4_28, FN_IP4_31_29, FN_IP5_2_0,
  68         FN_IP5_3, FN_IP5_4, FN_IP5_5, FN_IP5_6,
  69         FN_IP5_7, FN_IP5_8, FN_IP5_10_9, FN_IP5_12_11,
  70         FN_IP5_14_13, FN_IP5_16_15, FN_IP5_20_17, FN_IP5_23_21,
  71
  72         /* GPSR2 */
  73         FN_IP5_27_24, FN_IP8_20, FN_IP8_22_21, FN_IP8_24_23,
  74         FN_IP8_27_25, FN_IP8_30_28, FN_IP9_1_0, FN_IP9_3_2,
  75         FN_IP9_4, FN_IP9_5, FN_IP9_6, FN_IP9_7,
  76         FN_IP9_9_8, FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14,
  77         FN_IP9_18_16, FN_IP9_21_19, FN_IP9_23_22, FN_IP9_25_24,
  78         FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3,
  79         FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
  80         FN_IP10_20_18, FN_IP10_23_21, FN_IP10_25_24, FN_IP10_28_26,
  81
  82         /* GPSR3 */
  83         FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
  84         FN_IP11_11_9, FN_IP11_14_12, FN_IP11_17_15, FN_IP11_20_18,
  85         FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
  86         FN_IP12_5_3, FN_IP12_8_6, FN_IP12_11_9, FN_IP12_14_12,
  87         FN_IP12_17_15, FN_IP7_16_15, FN_IP7_18_17, FN_IP7_28_27,
  88         FN_IP7_30_29, FN_IP7_20_19, FN_IP7_22_21, FN_IP7_24_23,
  89         FN_IP7_26_25, FN_IP1_20_19, FN_IP1_22_21, FN_IP1_24_23,
  90         FN_IP5_28, FN_IP5_30_29, FN_IP6_1_0, FN_IP6_3_2,
  91
  92         /* GPSR4 */
  93         FN_IP6_5_4, FN_IP6_7_6, FN_IP6_8, FN_IP6_11_9,
  94         FN_IP6_14_12, FN_IP6_17_15, FN_IP6_19_18, FN_IP6_22_20,
  95         FN_IP6_24_23, FN_IP6_26_25, FN_IP6_30_29, FN_IP7_1_0,
  96         FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10,
  97         FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
  98         FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4,
  99         FN_IP8_11_8, FN_IP8_15_12, FN_USB_PENC0, FN_USB_PENC1,
 100         FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19,
 101
 102         /* GPSR5 */
 103         FN_A1, FN_A2, FN_A3, FN_A4,
 104         FN_A5, FN_A6, FN_A7, FN_A8,
 105         FN_A9, FN_A10, FN_A11, FN_A12,
 106         FN_A13, FN_A14, FN_A15, FN_A16,
 107         FN_RD, FN_WE0, FN_WE1, FN_EX_WAIT0,
 108         FN_IP3_23, FN_IP3_27, FN_IP3_28, FN_IP2_22,
 109         FN_IP2_23, FN_IP2_24, FN_IP2_25, FN_IP2_26,
 110         FN_IP2_27, FN_IP3_3, FN_IP3_4, FN_IP3_5,
 111
 112         /* GPSR6 */
 113         FN_IP3_6, FN_IP3_7, FN_IP3_8, FN_IP3_15,
 114         FN_IP3_16, FN_IP3_17, FN_IP3_18, FN_IP3_19,
 115         FN_IP3_20,
 116
 117         /* IPSR0 */
 118         FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
 119         FN_HRTS1, FN_RX4_C,
 120         FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B,
 121         FN_CS0, FN_HSPI_CS2_B,
 122         FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B,
 123         FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
 124         FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
 125         FN_CTS0_B,
 126         FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
 127         FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B,
 128         FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
 129         FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
 130         FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B,
 131         FN_A20, FN_TX5_D, FN_HSPI_TX2_B,
 132         FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
 133         FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
 134         FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
 135         FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
 136         FN_SCIF_CLK, FN_TCLK0_C,
 137
 138         /* IPSR1 */
 139         FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6,
 140         FN_FD6, FN_EX_CS1, FN_MMC0_D7, FN_FD7,
 141         FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
 142         FN_ATACS00, FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD,
 143         FN_FRE, FN_ATACS10, FN_VI1_R4, FN_RX5_B,
 144         FN_HSCK1, FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9,
 145         FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
 146         FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
 147         FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, FN_EX_CS5,
 148         FN_SD1_DAT1, FN_MMC0_D1, FN_FD1, FN_ATAWR0,
 149         FN_VI1_R6, FN_HRX1, FN_RX2_E, FN_RX0_B,
 150         FN_SSI_WS9, FN_MLB_CLK, FN_PWM2, FN_SCK4,
 151         FN_MLB_SIG, FN_PWM3, FN_TX4, FN_MLB_DAT,
 152         FN_PWM4, FN_RX4, FN_HTX0, FN_TX1,
 153         FN_SDATA, FN_CTS0_C, FN_SUB_TCK, FN_CC5_STATE2,
 154         FN_CC5_STATE10, FN_CC5_STATE18, FN_CC5_STATE26, FN_CC5_STATE34,
 155
 156         /* IPSR2 */
 157         FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
 158         FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
 159         FN_CC5_STATE27, FN_CC5_STATE35, FN_HSCK0, FN_SCK1,
 160         FN_MTS, FN_PWM5, FN_SCK0_C, FN_SSI_SDATA9_B,
 161         FN_SUB_TDO, FN_CC5_STATE0, FN_CC5_STATE8, FN_CC5_STATE16,
 162         FN_CC5_STATE24, FN_CC5_STATE32, FN_HCTS0, FN_CTS1,
 163         FN_STM, FN_PWM0_D, FN_RX0_C, FN_SCIF_CLK_C,
 164         FN_SUB_TRST, FN_TCLK1_B, FN_CC5_OSCOUT, FN_HRTS0,
 165         FN_RTS1_TANS, FN_MDATA, FN_TX0_C, FN_SUB_TMS,
 166         FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17, FN_CC5_STATE25,
 167         FN_CC5_STATE33, FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0,
 168         FN_GPS_CLK_B, FN_AUDATA0, FN_TX5_C, FN_DU0_DR1,
 169         FN_LCDOUT1, FN_DACK0, FN_DRACK0, FN_GPS_SIGN_B,
 170         FN_AUDATA1, FN_RX5_C, FN_DU0_DR2, FN_LCDOUT2,
 171         FN_DU0_DR3, FN_LCDOUT3, FN_DU0_DR4, FN_LCDOUT4,
 172         FN_DU0_DR5, FN_LCDOUT5, FN_DU0_DR6, FN_LCDOUT6,
 173         FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8,
 174         FN_DREQ1, FN_SCL2, FN_AUDATA2,
 175
 176         /* IPSR3 */
 177         FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
 178         FN_AUDATA3, FN_DU0_DG2, FN_LCDOUT10, FN_DU0_DG3,
 179         FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12, FN_DU0_DG5,
 180         FN_LCDOUT13, FN_DU0_DG6, FN_LCDOUT14, FN_DU0_DG7,
 181         FN_LCDOUT15, FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1,
 182         FN_SCL1, FN_TCLK1, FN_AUDATA4, FN_DU0_DB1,
 183         FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1, FN_GPS_MAG_B,
 184         FN_AUDATA5, FN_SCK5_C, FN_DU0_DB2, FN_LCDOUT18,
 185         FN_DU0_DB3, FN_LCDOUT19, FN_DU0_DB4, FN_LCDOUT20,
 186         FN_DU0_DB5, FN_LCDOUT21, FN_DU0_DB6, FN_LCDOUT22,
 187         FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
 188         FN_TX3_D_IRDA_TX_D, FN_SCL3_B, FN_DU0_DOTCLKOUT0, FN_QCLK,
 189         FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
 190         FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, FN_DU0_EXHSYNC_DU0_HSYNC,
 191         FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
 192         FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX,
 193         FN_TX2_C, FN_SCL2_C, FN_REMOCON,
 194
 195         /* IPSR4 */
 196         FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C,
 197         FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
 198         FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, FN_DU1_DR0,
 199         FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK, FN_TX3_E_IRDA_TX_E,
 200         FN_AUDCK, FN_PWMFSW0_B, FN_DU1_DR1, FN_VI2_DATA1_VI2_B1,
 201         FN_PWM0, FN_SD3_CMD, FN_RX3_E_IRDA_RX_E, FN_AUDSYNC,
 202         FN_CTS0_D, FN_DU1_DR2, FN_VI2_G0, FN_DU1_DR3,
 203         FN_VI2_G1, FN_DU1_DR4, FN_VI2_G2, FN_DU1_DR5,
 204         FN_VI2_G3, FN_DU1_DR6, FN_VI2_G4, FN_DU1_DR7,
 205         FN_VI2_G5, FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B,
 206         FN_SD3_DAT2, FN_SCK3_E, FN_AUDATA6, FN_TX0_D,
 207         FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
 208         FN_SCK5, FN_AUDATA7, FN_RX0_D, FN_DU1_DG2,
 209         FN_VI2_G6, FN_DU1_DG3, FN_VI2_G7, FN_DU1_DG4,
 210         FN_VI2_R0, FN_DU1_DG5, FN_VI2_R1, FN_DU1_DG6,
 211         FN_VI2_R2, FN_DU1_DG7, FN_VI2_R3, FN_DU1_DB0,
 212         FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0, FN_TX5,
 213         FN_SCK0_D,
 214
 215         /* IPSR5 */
 216         FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
 217         FN_RX5, FN_RTS0_D_TANS_D, FN_DU1_DB2, FN_VI2_R4,
 218         FN_DU1_DB3, FN_VI2_R5, FN_DU1_DB4, FN_VI2_R6,
 219         FN_DU1_DB5, FN_VI2_R7, FN_DU1_DB6, FN_SCL2_D,
 220         FN_DU1_DB7, FN_SDA2_D, FN_DU1_DOTCLKIN, FN_VI2_CLKENB,
 221         FN_HSPI_CS1, FN_SCL1_D, FN_DU1_DOTCLKOUT, FN_VI2_FIELD,
 222         FN_SDA1_D, FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC,
 223         FN_VI3_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC,
 224         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
 225         FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
 226         FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D,
 227         FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
 228         FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
 229         FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B,
 230         FN_SD3_WP, FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD,
 231         FN_AUDIO_CLKOUT, FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D,
 232         FN_AUDIO_CLKA, FN_CAN_TXCLK, FN_AUDIO_CLKB, FN_USB_OVC2,
 233         FN_CAN_DEBUGOUT0, FN_MOUT0,
 234
 235         /* IPSR6 */
 236         FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, FN_SSI_WS0129,
 237         FN_CAN_DEBUGOUT2, FN_MOUT2, FN_SSI_SDATA0, FN_CAN_DEBUGOUT3,
 238         FN_MOUT5, FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6,
 239         FN_SSI_SDATA2, FN_CAN_DEBUGOUT5, FN_SSI_SCK34, FN_CAN_DEBUGOUT6,
 240         FN_CAN0_TX_B, FN_IERX, FN_SSI_SCK9_C, FN_SSI_WS34,
 241         FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX, FN_SSI_WS9_C,
 242         FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
 243         FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, FN_SSI_SDATA4,
 244         FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, FN_SSI_SCK5, FN_ADICLK,
 245         FN_CAN_DEBUGOUT10, FN_SCK3, FN_TCLK0_D, FN_SSI_WS5,
 246         FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX, FN_SSI_SDATA5,
 247         FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX, FN_SSI_SCK6,
 248         FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
 249
 250         /* IPSR7 */
 251         FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B,
 252         FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
 253         FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
 254         FN_HSPI_CLK1_C, FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B,
 255         FN_SSI_WS9_B, FN_HSPI_CS1_C, FN_SSI_SDATA7, FN_CAN_DEBUGOUT15,
 256         FN_IRQ2_B, FN_TCLK1_C, FN_HSPI_TX1_C, FN_SSI_SDATA8,
 257         FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C, FN_SD0_CLK,
 258         FN_ATACS01, FN_SCK1_B, FN_SD0_CMD, FN_ATACS11,
 259         FN_TX1_B, FN_CC5_TDO, FN_SD0_DAT0, FN_ATADIR1,
 260         FN_RX1_B, FN_CC5_TRST, FN_SD0_DAT1, FN_ATAG1,
 261         FN_SCK2_B, FN_CC5_TMS, FN_SD0_DAT2, FN_ATARD1,
 262         FN_TX2_B, FN_CC5_TCK, FN_SD0_DAT3, FN_ATAWR1,
 263         FN_RX2_B, FN_CC5_TDI, FN_SD0_CD, FN_DREQ2,
 264         FN_RTS1_B_TANS_B, FN_SD0_WP, FN_DACK2, FN_CTS1_B,
 265
 266         /* IPSR8 */
 267         FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
 268         FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
 269         FN_CC5_STATE36, FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1,
 270         FN_AD_DI, FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21,
 271         FN_CC5_STATE29, FN_CC5_STATE37, FN_HSPI_TX0, FN_TX0,
 272         FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO, FN_CC5_STATE6, FN_CC5_STATE14,
 273         FN_CC5_STATE22, FN_CC5_STATE30, FN_CC5_STATE38, FN_HSPI_RX0,
 274         FN_RX0, FN_CAN_STEP0, FN_AD_NCS, FN_CC5_STATE7,
 275         FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31, FN_CC5_STATE39,
 276         FN_FMCLK, FN_RDS_CLK, FN_PCMOE, FN_BPFCLK,
 277         FN_PCMWE, FN_FMIN, FN_RDS_DATA, FN_VI0_CLK,
 278         FN_MMC1_CLK, FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B,
 279         FN_MT1_SYNC, FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B,
 280         FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
 281         FN_MMC1_CMD, FN_HSCK1_B, FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B,
 282         FN_RTS1_C_TANS_C, FN_RX4_D, FN_PWMFSW0_C,
 283
 284         /* IPSR9 */
 285         FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, FN_VI0_DATA1_VI0_B1,
 286         FN_HCTS1_B, FN_MT1_PWM, FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
 287         FN_VI0_DATA3_VI0_B3, FN_MMC1_D1, FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
 288         FN_VI0_DATA5_VI0_B5, FN_MMC1_D3, FN_VI0_DATA6_VI0_B6, FN_MMC1_D4,
 289         FN_ARM_TRACEDATA_0, FN_VI0_DATA7_VI0_B7, FN_MMC1_D5,
 290         FN_ARM_TRACEDATA_1, FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0,
 291         FN_ARM_TRACEDATA_2, FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1,
 292         FN_ARM_TRACEDATA_3, FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6,
 293         FN_ARM_TRACEDATA_4, FN_TS_SPSYNC0, FN_VI0_G3, FN_ETH_CRS_DV,
 294         FN_MMC1_D7, FN_ARM_TRACEDATA_5, FN_TS_SDAT0, FN_VI0_G4,
 295         FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6, FN_VI0_G5,
 296         FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7, FN_VI0_G6,
 297         FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8, FN_VI0_G7,
 298         FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
 299
 300         /* IPSR10 */
 301         FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
 302         FN_ARM_TRACEDATA_10, FN_DREQ0_C, FN_VI0_R1, FN_SSI_SDATA8_C,
 303         FN_DACK1_B, FN_ARM_TRACEDATA_11, FN_DACK0_C, FN_DRACK0_C,
 304         FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
 305         FN_ARM_TRACEDATA_12, FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B,
 306         FN_IRQ3, FN_ARM_TRACEDATA_13, FN_VI0_R4, FN_ETH_REFCLK,
 307         FN_SD2_CD_B, FN_HSPI_CLK1_B, FN_ARM_TRACEDATA_14, FN_MT1_CLK,
 308         FN_TS_SCK0, FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
 309         FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, FN_VI0_R6,
 310         FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B, FN_TRACECLK,
 311         FN_MT1_BEN, FN_PWMFSW0_D, FN_VI0_R7, FN_ETH_MDIO,
 312         FN_DACK2_C, FN_HSPI_RX1_B, FN_SCIF_CLK_D, FN_TRACECTL,
 313         FN_MT1_PEN, FN_VI1_CLK, FN_SIM_D, FN_SDA3,
 314         FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
 315         FN_PWMFSW0_E, FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4,
 316         FN_SIM_CLK, FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3,
 317
 318         /* IPSR11 */
 319         FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
 320         FN_ADICLK_B, FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK,
 321         FN_SPV_TMS, FN_ADICS_B_SAMP_B, FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2,
 322         FN_MT0_D, FN_SPVTDI, FN_ADIDATA_B, FN_VI1_DATA3_VI1_B3,
 323         FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO, FN_ADICHS0_B,
 324         FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
 325         FN_HSPI_CLK1_D, FN_ADICHS1_B, FN_VI1_DATA5_VI1_B5, FN_SD2_CMD,
 326         FN_MT0_SYNC, FN_SPA_TCK, FN_HSPI_CS1_D, FN_ADICHS2_B,
 327         FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
 328         FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM,
 329         FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0,
 330         FN_TS_SCK1, FN_DREQ2_B, FN_TX2,
 331         FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1,
 332         FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B,
 333
 334         /* IPSR12 */
 335         FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
 336         FN_SCK2, FN_HSCK0_B, FN_VI1_G3, FN_VI3_DATA3,
 337         FN_SSI_SCK2, FN_TS_SDAT1, FN_SCL1_C, FN_HTX0_B,
 338         FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C,
 339         FN_SIM_RST_B, FN_HRX0_B, FN_VI1_G5, FN_VI3_DATA5,
 340         FN_GPS_CLK, FN_FSE, FN_TX4_B, FN_SIM_D_B,
 341         FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB,
 342         FN_RX4_B, FN_SIM_CLK_B, FN_VI1_G7, FN_VI3_DATA7,
 343         FN_GPS_MAG, FN_FCE, FN_SCK4_B,
 344
 345         FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
 346         FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
 347         FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
 348         FN_SEL_SCIF3_3, FN_SEL_SCIF3_4,
 349         FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
 350         FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
 351         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2,
 352         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
 353         FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2,
 354         FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
 355         FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
 356         FN_SEL_VI0_0, FN_SEL_VI0_1,
 357         FN_SEL_SD2_0, FN_SEL_SD2_1,
 358         FN_SEL_INT3_0, FN_SEL_INT3_1,
 359         FN_SEL_INT2_0, FN_SEL_INT2_1,
 360         FN_SEL_INT1_0, FN_SEL_INT1_1,
 361         FN_SEL_INT0_0, FN_SEL_INT0_1,
 362         FN_SEL_IE_0, FN_SEL_IE_1,
 363         FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2,
 364         FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
 365         FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2,
 366
 367         FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2,
 368         FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3,
 369         FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
 370         FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
 371         FN_SEL_CAN0_0, FN_SEL_CAN0_1,
 372         FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
 373         FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
 374         FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2,
 375         FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4,
 376         FN_SEL_ADI_0, FN_SEL_ADI_1,
 377         FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
 378         FN_SEL_SIM_0, FN_SEL_SIM_1,
 379         FN_SEL_HSPI2_0, FN_SEL_HSPI2_1,
 380         FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3,
 381         FN_SEL_I2C3_0, FN_SEL_I2C3_1,
 382         FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
 383         FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
 384         PINMUX_FUNCTION_END,
 385
 386         PINMUX_MARK_BEGIN,
 387         AVS1_MARK, AVS2_MARK, A17_MARK, A18_MARK,
 388         A19_MARK,
 389
 390         RD_WR_MARK, FWE_MARK, ATAG0_MARK, VI1_R7_MARK,
 391         HRTS1_MARK, RX4_C_MARK,
 392         CS1_A26_MARK, HSPI_TX2_MARK, SDSELF_B_MARK,
 393         CS0_MARK, HSPI_CS2_B_MARK,
 394         CLKOUT_MARK, TX3C_IRDA_TX_C_MARK, PWM0_B_MARK,
 395         A25_MARK, SD1_WP_MARK, MMC0_D5_MARK, FD5_MARK,
 396         HSPI_RX2_MARK, VI1_R3_MARK, TX5_B_MARK, SSI_SDATA7_B_MARK, CTS0_B_MARK,
 397         A24_MARK, SD1_CD_MARK, MMC0_D4_MARK, FD4_MARK,
 398         HSPI_CS2_MARK, VI1_R2_MARK, SSI_WS78_B_MARK,
 399         A23_MARK, FCLE_MARK, HSPI_CLK2_MARK, VI1_R1_MARK,
 400         A22_MARK, RX5_D_MARK, HSPI_RX2_B_MARK, VI1_R0_MARK,
 401         A21_MARK, SCK5_D_MARK, HSPI_CLK2_B_MARK,
 402         A20_MARK, TX5_D_MARK, HSPI_TX2_B_MARK,
 403         A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
 404         BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
 405         ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
 406         USB_PENC0_MARK, USB_PENC1_MARK, USB_PENC2_MARK,
 407         SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
 408         SCIF_CLK_MARK, TCLK0_C_MARK,
 409
 410         EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
 411         FD6_MARK, EX_CS1_MARK, MMC0_D7_MARK, FD7_MARK,
 412         EX_CS2_MARK, SD1_CLK_MARK, MMC0_CLK_MARK, FALE_MARK,
 413         ATACS00_MARK, EX_CS3_MARK, SD1_CMD_MARK, MMC0_CMD_MARK,
 414         FRE_MARK, ATACS10_MARK, VI1_R4_MARK, RX5_B_MARK,
 415         HSCK1_MARK, SSI_SDATA8_B_MARK, RTS0_B_TANS_B_MARK, SSI_SDATA9_MARK,
 416         EX_CS4_MARK, SD1_DAT0_MARK, MMC0_D0_MARK, FD0_MARK,
 417         ATARD0_MARK, VI1_R5_MARK, SCK5_B_MARK, HTX1_MARK,
 418         TX2_E_MARK, TX0_B_MARK, SSI_SCK9_MARK, EX_CS5_MARK,
 419         SD1_DAT1_MARK, MMC0_D1_MARK, FD1_MARK, ATAWR0_MARK,
 420         VI1_R6_MARK, HRX1_MARK, RX2_E_MARK, RX0_B_MARK,
 421         SSI_WS9_MARK, MLB_CLK_MARK, PWM2_MARK, SCK4_MARK,
 422         MLB_SIG_MARK, PWM3_MARK, TX4_MARK, MLB_DAT_MARK,
 423         PWM4_MARK, RX4_MARK, HTX0_MARK, TX1_MARK,
 424         SDATA_MARK, CTS0_C_MARK, SUB_TCK_MARK, CC5_STATE2_MARK,
 425         CC5_STATE10_MARK, CC5_STATE18_MARK, CC5_STATE26_MARK, CC5_STATE34_MARK,
 426
 427         HRX0_MARK, RX1_MARK, SCKZ_MARK, RTS0_C_TANS_C_MARK,
 428         SUB_TDI_MARK, CC5_STATE3_MARK, CC5_STATE11_MARK, CC5_STATE19_MARK,
 429         CC5_STATE27_MARK, CC5_STATE35_MARK, HSCK0_MARK, SCK1_MARK,
 430         MTS_MARK, PWM5_MARK, SCK0_C_MARK, SSI_SDATA9_B_MARK,
 431         SUB_TDO_MARK, CC5_STATE0_MARK, CC5_STATE8_MARK, CC5_STATE16_MARK,
 432         CC5_STATE24_MARK, CC5_STATE32_MARK, HCTS0_MARK, CTS1_MARK,
 433         STM_MARK, PWM0_D_MARK, RX0_C_MARK, SCIF_CLK_C_MARK,
 434         SUB_TRST_MARK, TCLK1_B_MARK, CC5_OSCOUT_MARK, HRTS0_MARK,
 435         RTS1_TANS_MARK, MDATA_MARK, TX0_C_MARK, SUB_TMS_MARK,
 436         CC5_STATE1_MARK, CC5_STATE9_MARK, CC5_STATE17_MARK, CC5_STATE25_MARK,
 437         CC5_STATE33_MARK, DU0_DR0_MARK, LCDOUT0_MARK, DREQ0_MARK,
 438         GPS_CLK_B_MARK, AUDATA0_MARK, TX5_C_MARK, DU0_DR1_MARK,
 439         LCDOUT1_MARK, DACK0_MARK, DRACK0_MARK, GPS_SIGN_B_MARK,
 440         AUDATA1_MARK, RX5_C_MARK, DU0_DR2_MARK, LCDOUT2_MARK,
 441         DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK,
 442         DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK,
 443         DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK,
 444         DREQ1_MARK, SCL2_MARK, AUDATA2_MARK,
 445
 446         DU0_DG1_MARK, LCDOUT9_MARK, DACK1_MARK, SDA2_MARK,
 447         AUDATA3_MARK, DU0_DG2_MARK, LCDOUT10_MARK, DU0_DG3_MARK,
 448         LCDOUT11_MARK, DU0_DG4_MARK, LCDOUT12_MARK, DU0_DG5_MARK,
 449         LCDOUT13_MARK, DU0_DG6_MARK, LCDOUT14_MARK, DU0_DG7_MARK,
 450         LCDOUT15_MARK, DU0_DB0_MARK, LCDOUT16_MARK, EX_WAIT1_MARK,
 451         SCL1_MARK, TCLK1_MARK, AUDATA4_MARK, DU0_DB1_MARK,
 452         LCDOUT17_MARK, EX_WAIT2_MARK, SDA1_MARK, GPS_MAG_B_MARK,
 453         AUDATA5_MARK, SCK5_C_MARK, DU0_DB2_MARK, LCDOUT18_MARK,
 454         DU0_DB3_MARK, LCDOUT19_MARK, DU0_DB4_MARK, LCDOUT20_MARK,
 455         DU0_DB5_MARK, LCDOUT21_MARK, DU0_DB6_MARK, LCDOUT22_MARK,
 456         DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
 457         TX3_D_IRDA_TX_D_MARK, SCL3_B_MARK, DU0_DOTCLKOUT0_MARK, QCLK_MARK,
 458         DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, RX3_D_IRDA_RX_D_MARK, SDA3_B_MARK,
 459         SDA2_C_MARK, DACK0_B_MARK, DRACK0_B_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
 460         QSTH_QHS_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
 461         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CAN1_TX_MARK,
 462         TX2_C_MARK, SCL2_C_MARK, REMOCON_MARK,
 463
 464         DU0_DISP_MARK, QPOLA_MARK, CAN_CLK_C_MARK, SCK2_C_MARK,
 465         DU0_CDE_MARK, QPOLB_MARK, CAN1_RX_MARK, RX2_C_MARK,
 466         DREQ0_B_MARK, SSI_SCK78_B_MARK, SCK0_B_MARK, DU1_DR0_MARK,
 467         VI2_DATA0_VI2_B0_MARK, PWM6_MARK, SD3_CLK_MARK, TX3_E_IRDA_TX_E_MARK,
 468         AUDCK_MARK, PWMFSW0_B_MARK, DU1_DR1_MARK, VI2_DATA1_VI2_B1_MARK,
 469         PWM0_MARK, SD3_CMD_MARK, RX3_E_IRDA_RX_E_MARK, AUDSYNC_MARK,
 470         CTS0_D_MARK, DU1_DR2_MARK, VI2_G0_MARK, DU1_DR3_MARK,
 471         VI2_G1_MARK, DU1_DR4_MARK, VI2_G2_MARK, DU1_DR5_MARK,
 472         VI2_G3_MARK, DU1_DR6_MARK, VI2_G4_MARK, DU1_DR7_MARK,
 473         VI2_G5_MARK, DU1_DG0_MARK, VI2_DATA2_VI2_B2_MARK, SCL1_B_MARK,
 474         SD3_DAT2_MARK, SCK3_E_MARK, AUDATA6_MARK, TX0_D_MARK,
 475         DU1_DG1_MARK, VI2_DATA3_VI2_B3_MARK, SDA1_B_MARK, SD3_DAT3_MARK,
 476         SCK5_MARK, AUDATA7_MARK, RX0_D_MARK, DU1_DG2_MARK,
 477         VI2_G6_MARK, DU1_DG3_MARK, VI2_G7_MARK, DU1_DG4_MARK,
 478         VI2_R0_MARK, DU1_DG5_MARK, VI2_R1_MARK, DU1_DG6_MARK,
 479         VI2_R2_MARK, DU1_DG7_MARK, VI2_R3_MARK, DU1_DB0_MARK,
 480         VI2_DATA4_VI2_B4_MARK, SCL2_B_MARK, SD3_DAT0_MARK, TX5_MARK,
 481         SCK0_D_MARK,
 482
 483         DU1_DB1_MARK, VI2_DATA5_VI2_B5_MARK, SDA2_B_MARK, SD3_DAT1_MARK,
 484         RX5_MARK, RTS0_D_TANS_D_MARK, DU1_DB2_MARK, VI2_R4_MARK,
 485         DU1_DB3_MARK, VI2_R5_MARK, DU1_DB4_MARK, VI2_R6_MARK,
 486         DU1_DB5_MARK, VI2_R7_MARK, DU1_DB6_MARK, SCL2_D_MARK,
 487         DU1_DB7_MARK, SDA2_D_MARK, DU1_DOTCLKIN_MARK, VI2_CLKENB_MARK,
 488         HSPI_CS1_MARK, SCL1_D_MARK, DU1_DOTCLKOUT_MARK, VI2_FIELD_MARK,
 489         SDA1_D_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, VI2_HSYNC_MARK,
 490         VI3_HSYNC_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, VI2_VSYNC_MARK,
 491         VI3_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, VI2_CLK_MARK,
 492         TX3_B_IRDA_TX_B_MARK, SD3_CD_MARK, HSPI_TX1_MARK, VI1_CLKENB_MARK,
 493         VI3_CLKENB_MARK, AUDIO_CLKC_MARK, TX2_D_MARK, SPEEDIN_MARK,
 494         GPS_SIGN_D_MARK, DU1_DISP_MARK, VI2_DATA6_VI2_B6_MARK, TCLK0_MARK,
 495         QSTVA_B_QVS_B_MARK, HSPI_CLK1_MARK, SCK2_D_MARK, AUDIO_CLKOUT_B_MARK,
 496         GPS_MAG_D_MARK, DU1_CDE_MARK, VI2_DATA7_VI2_B7_MARK,
 497         RX3_B_IRDA_RX_B_MARK, SD3_WP_MARK, HSPI_RX1_MARK, VI1_FIELD_MARK,
 498         VI3_FIELD_MARK, AUDIO_CLKOUT_MARK, RX2_D_MARK, GPS_CLK_C_MARK,
 499         GPS_CLK_D_MARK, AUDIO_CLKA_MARK, CAN_TXCLK_MARK, AUDIO_CLKB_MARK,
 500         USB_OVC2_MARK, CAN_DEBUGOUT0_MARK, MOUT0_MARK,
 501
 502         SSI_SCK0129_MARK, CAN_DEBUGOUT1_MARK, MOUT1_MARK, SSI_WS0129_MARK,
 503         CAN_DEBUGOUT2_MARK, MOUT2_MARK, SSI_SDATA0_MARK, CAN_DEBUGOUT3_MARK,
 504         MOUT5_MARK, SSI_SDATA1_MARK, CAN_DEBUGOUT4_MARK, MOUT6_MARK,
 505         SSI_SDATA2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK34_MARK,
 506         CAN_DEBUGOUT6_MARK, CAN0_TX_B_MARK, IERX_MARK, SSI_SCK9_C_MARK,
 507         SSI_WS34_MARK, CAN_DEBUGOUT7_MARK, CAN0_RX_B_MARK, IETX_MARK,
 508         SSI_WS9_C_MARK, SSI_SDATA3_MARK, PWM0_C_MARK, CAN_DEBUGOUT8_MARK,
 509         CAN_CLK_B_MARK, IECLK_MARK, SCIF_CLK_B_MARK, TCLK0_B_MARK,
 510         SSI_SDATA4_MARK, CAN_DEBUGOUT9_MARK, SSI_SDATA9_C_MARK, SSI_SCK5_MARK,
 511         ADICLK_MARK, CAN_DEBUGOUT10_MARK, SCK3_MARK, TCLK0_D_MARK,
 512         SSI_WS5_MARK, ADICS_SAMP_MARK, CAN_DEBUGOUT11_MARK, TX3_IRDA_TX_MARK,
 513         SSI_SDATA5_MARK, ADIDATA_MARK, CAN_DEBUGOUT12_MARK, RX3_IRDA_RX_MARK,
 514         SSI_SCK6_MARK, ADICHS0_MARK, CAN0_TX_MARK, IERX_B_MARK,
 515
 516         SSI_WS6_MARK, ADICHS1_MARK, CAN0_RX_MARK, IETX_B_MARK,
 517         SSI_SDATA6_MARK, ADICHS2_MARK, CAN_CLK_MARK, IECLK_B_MARK,
 518         SSI_SCK78_MARK, CAN_DEBUGOUT13_MARK, IRQ0_B_MARK, SSI_SCK9_B_MARK,
 519         HSPI_CLK1_C_MARK, SSI_WS78_MARK, CAN_DEBUGOUT14_MARK, IRQ1_B_MARK,
 520         SSI_WS9_B_MARK, HSPI_CS1_C_MARK, SSI_SDATA7_MARK, CAN_DEBUGOUT15_MARK,
 521         IRQ2_B_MARK, TCLK1_C_MARK, HSPI_TX1_C_MARK, SSI_SDATA8_MARK,
 522         VSP_MARK, IRQ3_B_MARK, HSPI_RX1_C_MARK, SD0_CLK_MARK,
 523         ATACS01_MARK, SCK1_B_MARK, SD0_CMD_MARK, ATACS11_MARK,
 524         TX1_B_MARK, CC5_TDO_MARK, SD0_DAT0_MARK, ATADIR1_MARK,
 525         RX1_B_MARK, CC5_TRST_MARK, SD0_DAT1_MARK, ATAG1_MARK,
 526         SCK2_B_MARK, CC5_TMS_MARK, SD0_DAT2_MARK, ATARD1_MARK,
 527         TX2_B_MARK, CC5_TCK_MARK, SD0_DAT3_MARK, ATAWR1_MARK,
 528         RX2_B_MARK, CC5_TDI_MARK, SD0_CD_MARK, DREQ2_MARK,
 529         RTS1_B_TANS_B_MARK, SD0_WP_MARK, DACK2_MARK, CTS1_B_MARK,
 530
 531         HSPI_CLK0_MARK, CTS0_MARK, USB_OVC0_MARK, AD_CLK_MARK,
 532         CC5_STATE4_MARK, CC5_STATE12_MARK, CC5_STATE20_MARK, CC5_STATE28_MARK,
 533         CC5_STATE36_MARK, HSPI_CS0_MARK, RTS0_TANS_MARK, USB_OVC1_MARK,
 534         AD_DI_MARK, CC5_STATE5_MARK, CC5_STATE13_MARK, CC5_STATE21_MARK,
 535         CC5_STATE29_MARK, CC5_STATE37_MARK, HSPI_TX0_MARK, TX0_MARK,
 536         CAN_DEBUG_HW_TRIGGER_MARK, AD_DO_MARK, CC5_STATE6_MARK,
 537         CC5_STATE14_MARK, CC5_STATE22_MARK, CC5_STATE30_MARK,
 538         CC5_STATE38_MARK, HSPI_RX0_MARK, RX0_MARK, CAN_STEP0_MARK,
 539         AD_NCS_MARK, CC5_STATE7_MARK, CC5_STATE15_MARK, CC5_STATE23_MARK,
 540         CC5_STATE31_MARK, CC5_STATE39_MARK, FMCLK_MARK, RDS_CLK_MARK,
 541         PCMOE_MARK, BPFCLK_MARK, PCMWE_MARK, FMIN_MARK, RDS_DATA_MARK,
 542         VI0_CLK_MARK, MMC1_CLK_MARK, VI0_CLKENB_MARK, TX1_C_MARK, HTX1_B_MARK,
 543         MT1_SYNC_MARK, VI0_FIELD_MARK, RX1_C_MARK, HRX1_B_MARK,
 544         VI0_HSYNC_MARK, VI0_DATA0_B_VI0_B0_B_MARK, CTS1_C_MARK, TX4_D_MARK,
 545         MMC1_CMD_MARK, HSCK1_B_MARK, VI0_VSYNC_MARK, VI0_DATA1_B_VI0_B1_B_MARK,
 546         RTS1_C_TANS_C_MARK, RX4_D_MARK, PWMFSW0_C_MARK,
 547
 548         VI0_DATA0_VI0_B0_MARK, HRTS1_B_MARK, MT1_VCXO_MARK,
 549         VI0_DATA1_VI0_B1_MARK, HCTS1_B_MARK, MT1_PWM_MARK,
 550         VI0_DATA2_VI0_B2_MARK, MMC1_D0_MARK, VI0_DATA3_VI0_B3_MARK,
 551         MMC1_D1_MARK, VI0_DATA4_VI0_B4_MARK, MMC1_D2_MARK,
 552         VI0_DATA5_VI0_B5_MARK, MMC1_D3_MARK, VI0_DATA6_VI0_B6_MARK,
 553         MMC1_D4_MARK, ARM_TRACEDATA_0_MARK, VI0_DATA7_VI0_B7_MARK,
 554         MMC1_D5_MARK, ARM_TRACEDATA_1_MARK, VI0_G0_MARK, SSI_SCK78_C_MARK,
 555         IRQ0_MARK, ARM_TRACEDATA_2_MARK, VI0_G1_MARK, SSI_WS78_C_MARK,
 556         IRQ1_MARK, ARM_TRACEDATA_3_MARK, VI0_G2_MARK, ETH_TXD1_MARK,
 557         MMC1_D6_MARK, ARM_TRACEDATA_4_MARK, TS_SPSYNC0_MARK, VI0_G3_MARK,
 558         ETH_CRS_DV_MARK, MMC1_D7_MARK, ARM_TRACEDATA_5_MARK, TS_SDAT0_MARK,
 559         VI0_G4_MARK, ETH_TX_EN_MARK, SD2_DAT0_B_MARK, ARM_TRACEDATA_6_MARK,
 560         VI0_G5_MARK, ETH_RX_ER_MARK, SD2_DAT1_B_MARK, ARM_TRACEDATA_7_MARK,
 561         VI0_G6_MARK, ETH_RXD0_MARK, SD2_DAT2_B_MARK, ARM_TRACEDATA_8_MARK,
 562         VI0_G7_MARK, ETH_RXD1_MARK, SD2_DAT3_B_MARK, ARM_TRACEDATA_9_MARK,
 563
 564         VI0_R0_MARK, SSI_SDATA7_C_MARK, SCK1_C_MARK, DREQ1_B_MARK,
 565         ARM_TRACEDATA_10_MARK, DREQ0_C_MARK, VI0_R1_MARK, SSI_SDATA8_C_MARK,
 566         DACK1_B_MARK, ARM_TRACEDATA_11_MARK, DACK0_C_MARK, DRACK0_C_MARK,
 567         VI0_R2_MARK, ETH_LINK_MARK, SD2_CLK_B_MARK, IRQ2_MARK,
 568         ARM_TRACEDATA_12_MARK, VI0_R3_MARK, ETH_MAGIC_MARK, SD2_CMD_B_MARK,
 569         IRQ3_MARK, ARM_TRACEDATA_13_MARK, VI0_R4_MARK, ETH_REFCLK_MARK,
 570         SD2_CD_B_MARK, HSPI_CLK1_B_MARK, ARM_TRACEDATA_14_MARK, MT1_CLK_MARK,
 571         TS_SCK0_MARK, VI0_R5_MARK, ETH_TXD0_MARK, SD2_WP_B_MARK,
 572         HSPI_CS1_B_MARK, ARM_TRACEDATA_15_MARK, MT1_D_MARK, TS_SDEN0_MARK,
 573         VI0_R6_MARK, ETH_MDC_MARK, DREQ2_C_MARK, HSPI_TX1_B_MARK,
 574         TRACECLK_MARK, MT1_BEN_MARK, PWMFSW0_D_MARK, VI0_R7_MARK,
 575         ETH_MDIO_MARK, DACK2_C_MARK, HSPI_RX1_B_MARK, SCIF_CLK_D_MARK,
 576         TRACECTL_MARK, MT1_PEN_MARK, VI1_CLK_MARK, SIM_D_MARK, SDA3_MARK,
 577         VI1_HSYNC_MARK, VI3_CLK_MARK, SSI_SCK4_MARK, GPS_SIGN_C_MARK,
 578         PWMFSW0_E_MARK, VI1_VSYNC_MARK, AUDIO_CLKOUT_C_MARK, SSI_WS4_MARK,
 579         SIM_CLK_MARK, GPS_MAG_C_MARK, SPV_TRST_MARK, SCL3_MARK,
 580
 581         VI1_DATA0_VI1_B0_MARK, SD2_DAT0_MARK, SIM_RST_MARK, SPV_TCK_MARK,
 582         ADICLK_B_MARK, VI1_DATA1_VI1_B1_MARK, SD2_DAT1_MARK, MT0_CLK_MARK,
 583         SPV_TMS_MARK, ADICS_B_SAMP_B_MARK, VI1_DATA2_VI1_B2_MARK,
 584         SD2_DAT2_MARK, MT0_D_MARK, SPVTDI_MARK, ADIDATA_B_MARK,
 585         VI1_DATA3_VI1_B3_MARK, SD2_DAT3_MARK, MT0_BEN_MARK, SPV_TDO_MARK,
 586         ADICHS0_B_MARK, VI1_DATA4_VI1_B4_MARK, SD2_CLK_MARK, MT0_PEN_MARK,
 587         SPA_TRST_MARK, HSPI_CLK1_D_MARK, ADICHS1_B_MARK,
 588         VI1_DATA5_VI1_B5_MARK, SD2_CMD_MARK, MT0_SYNC_MARK, SPA_TCK_MARK,
 589         HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK,
 590         MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK,
 591         SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK,
 592         VI1_G0_MARK, VI3_DATA0_MARK, TS_SCK1_MARK,
 593         DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK,
 594         VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK,
 595         DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK,
 596
 597         VI1_G2_MARK, VI3_DATA2_MARK, SSI_WS1_MARK, TS_SPSYNC1_MARK,
 598         SCK2_MARK, HSCK0_B_MARK, VI1_G3_MARK, VI3_DATA3_MARK,
 599         SSI_SCK2_MARK, TS_SDAT1_MARK, SCL1_C_MARK, HTX0_B_MARK,
 600         VI1_G4_MARK, VI3_DATA4_MARK, SSI_WS2_MARK, SDA1_C_MARK,
 601         SIM_RST_B_MARK, HRX0_B_MARK, VI1_G5_MARK, VI3_DATA5_MARK,
 602         GPS_CLK_MARK, FSE_MARK, TX4_B_MARK, SIM_D_B_MARK,
 603         VI1_G6_MARK, VI3_DATA6_MARK, GPS_SIGN_MARK, FRB_MARK,
 604         RX4_B_MARK, SIM_CLK_B_MARK, VI1_G7_MARK, VI3_DATA7_MARK,
 605         GPS_MAG_MARK, FCE_MARK, SCK4_B_MARK,
 606         PINMUX_MARK_END,
 607 };
 608
 609 static const u16 pinmux_data[] = {
 610         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 611
 612         PINMUX_DATA(AVS1_MARK, FN_AVS1),
 613         PINMUX_DATA(AVS1_MARK, FN_AVS1),
 614         PINMUX_DATA(A17_MARK, FN_A17),
 615         PINMUX_DATA(A18_MARK, FN_A18),
 616         PINMUX_DATA(A19_MARK, FN_A19),
 617
 618         PINMUX_DATA(USB_PENC0_MARK, FN_USB_PENC0),
 619         PINMUX_DATA(USB_PENC1_MARK, FN_USB_PENC1),
 620
 621         PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
 622         PINMUX_IPSR_MSEL(IP0_2_0, SCK0, SEL_SCIF0_0),
 623         PINMUX_IPSR_DATA(IP0_2_0, PWM1),
 624         PINMUX_IPSR_MSEL(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
 625         PINMUX_IPSR_MSEL(IP0_2_0, SCIF_CLK, SEL_SCIF_0),
 626         PINMUX_IPSR_MSEL(IP0_2_0, TCLK0_C, SEL_TMU0_2),
 627         PINMUX_IPSR_DATA(IP0_5_3, BS),
 628         PINMUX_IPSR_DATA(IP0_5_3, SD1_DAT2),
 629         PINMUX_IPSR_DATA(IP0_5_3, MMC0_D2),
 630         PINMUX_IPSR_DATA(IP0_5_3, FD2),
 631         PINMUX_IPSR_DATA(IP0_5_3, ATADIR0),
 632         PINMUX_IPSR_DATA(IP0_5_3, SDSELF),
 633         PINMUX_IPSR_MSEL(IP0_5_3, HCTS1, SEL_HSCIF1_0),
 634         PINMUX_IPSR_DATA(IP0_5_3, TX4_C),
 635         PINMUX_IPSR_DATA(IP0_7_6, A0),
 636         PINMUX_IPSR_DATA(IP0_7_6, SD1_DAT3),
 637         PINMUX_IPSR_DATA(IP0_7_6, MMC0_D3),
 638         PINMUX_IPSR_DATA(IP0_7_6, FD3),
 639         PINMUX_IPSR_DATA(IP0_9_8, A20),
 640         PINMUX_IPSR_DATA(IP0_9_8, TX5_D),
 641         PINMUX_IPSR_DATA(IP0_9_8, HSPI_TX2_B),
 642         PINMUX_IPSR_DATA(IP0_11_10, A21),
 643         PINMUX_IPSR_MSEL(IP0_11_10, SCK5_D, SEL_SCIF5_3),
 644         PINMUX_IPSR_MSEL(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1),
 645         PINMUX_IPSR_DATA(IP0_13_12, A22),
 646         PINMUX_IPSR_MSEL(IP0_13_12, RX5_D, SEL_SCIF5_3),
 647         PINMUX_IPSR_MSEL(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1),
 648         PINMUX_IPSR_DATA(IP0_13_12, VI1_R0),
 649         PINMUX_IPSR_DATA(IP0_15_14, A23),
 650         PINMUX_IPSR_DATA(IP0_15_14, FCLE),
 651         PINMUX_IPSR_MSEL(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0),
 652         PINMUX_IPSR_DATA(IP0_15_14, VI1_R1),
 653         PINMUX_IPSR_DATA(IP0_18_16, A24),
 654         PINMUX_IPSR_DATA(IP0_18_16, SD1_CD),
 655         PINMUX_IPSR_DATA(IP0_18_16, MMC0_D4),
 656         PINMUX_IPSR_DATA(IP0_18_16, FD4),
 657         PINMUX_IPSR_MSEL(IP0_18_16, HSPI_CS2, SEL_HSPI2_0),
 658         PINMUX_IPSR_DATA(IP0_18_16, VI1_R2),
 659         PINMUX_IPSR_MSEL(IP0_18_16, SSI_WS78_B, SEL_SSI7_1),
 660         PINMUX_IPSR_DATA(IP0_22_19, A25),
 661         PINMUX_IPSR_DATA(IP0_22_19, SD1_WP),
 662         PINMUX_IPSR_DATA(IP0_22_19, MMC0_D5),
 663         PINMUX_IPSR_DATA(IP0_22_19, FD5),
 664         PINMUX_IPSR_MSEL(IP0_22_19, HSPI_RX2, SEL_HSPI2_0),
 665         PINMUX_IPSR_DATA(IP0_22_19, VI1_R3),
 666         PINMUX_IPSR_DATA(IP0_22_19, TX5_B),
 667         PINMUX_IPSR_MSEL(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1),
 668         PINMUX_IPSR_MSEL(IP0_22_19, CTS0_B, SEL_SCIF0_1),
 669         PINMUX_IPSR_DATA(IP0_24_23, CLKOUT),
 670         PINMUX_IPSR_DATA(IP0_24_23, TX3C_IRDA_TX_C),
 671         PINMUX_IPSR_DATA(IP0_24_23, PWM0_B),
 672         PINMUX_IPSR_DATA(IP0_25, CS0),
 673         PINMUX_IPSR_MSEL(IP0_25, HSPI_CS2_B, SEL_HSPI2_1),
 674         PINMUX_IPSR_DATA(IP0_27_26, CS1_A26),
 675         PINMUX_IPSR_DATA(IP0_27_26, HSPI_TX2),
 676         PINMUX_IPSR_DATA(IP0_27_26, SDSELF_B),
 677         PINMUX_IPSR_DATA(IP0_30_28, RD_WR),
 678         PINMUX_IPSR_DATA(IP0_30_28, FWE),
 679         PINMUX_IPSR_DATA(IP0_30_28, ATAG0),
 680         PINMUX_IPSR_DATA(IP0_30_28, VI1_R7),
 681         PINMUX_IPSR_MSEL(IP0_30_28, HRTS1, SEL_HSCIF1_0),
 682         PINMUX_IPSR_MSEL(IP0_30_28, RX4_C, SEL_SCIF4_2),
 683
 684         PINMUX_IPSR_DATA(IP1_1_0, EX_CS0),
 685         PINMUX_IPSR_MSEL(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2),
 686         PINMUX_IPSR_DATA(IP1_1_0, MMC0_D6),
 687         PINMUX_IPSR_DATA(IP1_1_0, FD6),
 688         PINMUX_IPSR_DATA(IP1_3_2, EX_CS1),
 689         PINMUX_IPSR_DATA(IP1_3_2, MMC0_D7),
 690         PINMUX_IPSR_DATA(IP1_3_2, FD7),
 691         PINMUX_IPSR_DATA(IP1_6_4, EX_CS2),
 692         PINMUX_IPSR_DATA(IP1_6_4, SD1_CLK),
 693         PINMUX_IPSR_DATA(IP1_6_4, MMC0_CLK),
 694         PINMUX_IPSR_DATA(IP1_6_4, FALE),
 695         PINMUX_IPSR_DATA(IP1_6_4, ATACS00),
 696         PINMUX_IPSR_DATA(IP1_10_7, EX_CS3),
 697         PINMUX_IPSR_DATA(IP1_10_7, SD1_CMD),
 698         PINMUX_IPSR_DATA(IP1_10_7, MMC0_CMD),
 699         PINMUX_IPSR_DATA(IP1_10_7, FRE),
 700         PINMUX_IPSR_DATA(IP1_10_7, ATACS10),
 701         PINMUX_IPSR_DATA(IP1_10_7, VI1_R4),
 702         PINMUX_IPSR_MSEL(IP1_10_7, RX5_B, SEL_SCIF5_1),
 703         PINMUX_IPSR_MSEL(IP1_10_7, HSCK1, SEL_HSCIF1_0),
 704         PINMUX_IPSR_MSEL(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1),
 705         PINMUX_IPSR_MSEL(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1),
 706         PINMUX_IPSR_MSEL(IP1_10_7, SSI_SDATA9, SEL_SSI9_0),
 707         PINMUX_IPSR_DATA(IP1_14_11, EX_CS4),
 708         PINMUX_IPSR_DATA(IP1_14_11, SD1_DAT0),
 709         PINMUX_IPSR_DATA(IP1_14_11, MMC0_D0),
 710         PINMUX_IPSR_DATA(IP1_14_11, FD0),
 711         PINMUX_IPSR_DATA(IP1_14_11, ATARD0),
 712         PINMUX_IPSR_DATA(IP1_14_11, VI1_R5),
 713         PINMUX_IPSR_MSEL(IP1_14_11, SCK5_B, SEL_SCIF5_1),
 714         PINMUX_IPSR_DATA(IP1_14_11, HTX1),
 715         PINMUX_IPSR_DATA(IP1_14_11, TX2_E),
 716         PINMUX_IPSR_DATA(IP1_14_11, TX0_B),
 717         PINMUX_IPSR_MSEL(IP1_14_11, SSI_SCK9, SEL_SSI9_0),
 718         PINMUX_IPSR_DATA(IP1_18_15, EX_CS5),
 719         PINMUX_IPSR_DATA(IP1_18_15, SD1_DAT1),
 720         PINMUX_IPSR_DATA(IP1_18_15, MMC0_D1),
 721         PINMUX_IPSR_DATA(IP1_18_15, FD1),
 722         PINMUX_IPSR_DATA(IP1_18_15, ATAWR0),
 723         PINMUX_IPSR_DATA(IP1_18_15, VI1_R6),
 724         PINMUX_IPSR_MSEL(IP1_18_15, HRX1, SEL_HSCIF1_0),
 725         PINMUX_IPSR_MSEL(IP1_18_15, RX2_E, SEL_SCIF2_4),
 726         PINMUX_IPSR_MSEL(IP1_18_15, RX0_B, SEL_SCIF0_1),
 727         PINMUX_IPSR_MSEL(IP1_18_15, SSI_WS9, SEL_SSI9_0),
 728         PINMUX_IPSR_DATA(IP1_20_19, MLB_CLK),
 729         PINMUX_IPSR_DATA(IP1_20_19, PWM2),
 730         PINMUX_IPSR_MSEL(IP1_20_19, SCK4, SEL_SCIF4_0),
 731         PINMUX_IPSR_DATA(IP1_22_21, MLB_SIG),
 732         PINMUX_IPSR_DATA(IP1_22_21, PWM3),
 733         PINMUX_IPSR_DATA(IP1_22_21, TX4),
 734         PINMUX_IPSR_DATA(IP1_24_23, MLB_DAT),
 735         PINMUX_IPSR_DATA(IP1_24_23, PWM4),
 736         PINMUX_IPSR_MSEL(IP1_24_23, RX4, SEL_SCIF4_0),
 737         PINMUX_IPSR_DATA(IP1_28_25, HTX0),
 738         PINMUX_IPSR_DATA(IP1_28_25, TX1),
 739         PINMUX_IPSR_DATA(IP1_28_25, SDATA),
 740         PINMUX_IPSR_MSEL(IP1_28_25, CTS0_C, SEL_SCIF0_2),
 741         PINMUX_IPSR_DATA(IP1_28_25, SUB_TCK),
 742         PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE2),
 743         PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE10),
 744         PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE18),
 745         PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE26),
 746         PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE34),
 747
 748         PINMUX_IPSR_MSEL(IP2_3_0, HRX0, SEL_HSCIF0_0),
 749         PINMUX_IPSR_MSEL(IP2_3_0, RX1, SEL_SCIF1_0),
 750         PINMUX_IPSR_DATA(IP2_3_0, SCKZ),
 751         PINMUX_IPSR_MSEL(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2),
 752         PINMUX_IPSR_DATA(IP2_3_0, SUB_TDI),
 753         PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE3),
 754         PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE11),
 755         PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE19),
 756         PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE27),
 757         PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE35),
 758         PINMUX_IPSR_MSEL(IP2_7_4, HSCK0, SEL_HSCIF0_0),
 759         PINMUX_IPSR_MSEL(IP2_7_4, SCK1, SEL_SCIF1_0),
 760         PINMUX_IPSR_DATA(IP2_7_4, MTS),
 761         PINMUX_IPSR_DATA(IP2_7_4, PWM5),
 762         PINMUX_IPSR_MSEL(IP2_7_4, SCK0_C, SEL_SCIF0_2),
 763         PINMUX_IPSR_MSEL(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1),
 764         PINMUX_IPSR_DATA(IP2_7_4, SUB_TDO),
 765         PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE0),
 766         PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE8),
 767         PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE16),
 768         PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE24),
 769         PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE32),
 770         PINMUX_IPSR_MSEL(IP2_11_8, HCTS0, SEL_HSCIF0_0),
 771         PINMUX_IPSR_MSEL(IP2_11_8, CTS1, SEL_SCIF1_0),
 772         PINMUX_IPSR_DATA(IP2_11_8, STM),
 773         PINMUX_IPSR_DATA(IP2_11_8, PWM0_D),
 774         PINMUX_IPSR_MSEL(IP2_11_8, RX0_C, SEL_SCIF0_2),
 775         PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2),
 776         PINMUX_IPSR_DATA(IP2_11_8, SUB_TRST),
 777         PINMUX_IPSR_MSEL(IP2_11_8, TCLK1_B, SEL_TMU1_1),
 778         PINMUX_IPSR_DATA(IP2_11_8, CC5_OSCOUT),
 779         PINMUX_IPSR_MSEL(IP2_15_12, HRTS0, SEL_HSCIF0_0),
 780         PINMUX_IPSR_MSEL(IP2_15_12, RTS1_TANS, SEL_SCIF1_0),
 781         PINMUX_IPSR_DATA(IP2_15_12, MDATA),
 782         PINMUX_IPSR_DATA(IP2_15_12, TX0_C),
 783         PINMUX_IPSR_DATA(IP2_15_12, SUB_TMS),
 784         PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE1),
 785         PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE9),
 786         PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE17),
 787         PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE25),
 788         PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE33),
 789         PINMUX_IPSR_DATA(IP2_18_16, DU0_DR0),
 790         PINMUX_IPSR_DATA(IP2_18_16, LCDOUT0),
 791         PINMUX_IPSR_MSEL(IP2_18_16, DREQ0, SEL_EXBUS0_0),
 792         PINMUX_IPSR_MSEL(IP2_18_16, GPS_CLK_B, SEL_GPS_1),
 793         PINMUX_IPSR_DATA(IP2_18_16, AUDATA0),
 794         PINMUX_IPSR_DATA(IP2_18_16, TX5_C),
 795         PINMUX_IPSR_DATA(IP2_21_19, DU0_DR1),
 796         PINMUX_IPSR_DATA(IP2_21_19, LCDOUT1),
 797         PINMUX_IPSR_DATA(IP2_21_19, DACK0),
 798         PINMUX_IPSR_DATA(IP2_21_19, DRACK0),
 799         PINMUX_IPSR_MSEL(IP2_21_19, GPS_SIGN_B, SEL_GPS_1),
 800         PINMUX_IPSR_DATA(IP2_21_19, AUDATA1),
 801         PINMUX_IPSR_MSEL(IP2_21_19, RX5_C, SEL_SCIF5_2),
 802         PINMUX_IPSR_DATA(IP2_22, DU0_DR2),
 803         PINMUX_IPSR_DATA(IP2_22, LCDOUT2),
 804         PINMUX_IPSR_DATA(IP2_23, DU0_DR3),
 805         PINMUX_IPSR_DATA(IP2_23, LCDOUT3),
 806         PINMUX_IPSR_DATA(IP2_24, DU0_DR4),
 807         PINMUX_IPSR_DATA(IP2_24, LCDOUT4),
 808         PINMUX_IPSR_DATA(IP2_25, DU0_DR5),
 809         PINMUX_IPSR_DATA(IP2_25, LCDOUT5),
 810         PINMUX_IPSR_DATA(IP2_26, DU0_DR6),
 811         PINMUX_IPSR_DATA(IP2_26, LCDOUT6),
 812         PINMUX_IPSR_DATA(IP2_27, DU0_DR7),
 813         PINMUX_IPSR_DATA(IP2_27, LCDOUT7),
 814         PINMUX_IPSR_DATA(IP2_30_28, DU0_DG0),
 815         PINMUX_IPSR_DATA(IP2_30_28, LCDOUT8),
 816         PINMUX_IPSR_MSEL(IP2_30_28, DREQ1, SEL_EXBUS1_0),
 817         PINMUX_IPSR_MSEL(IP2_30_28, SCL2, SEL_I2C2_0),
 818         PINMUX_IPSR_DATA(IP2_30_28, AUDATA2),
 819
 820         PINMUX_IPSR_DATA(IP3_2_0, DU0_DG1),
 821         PINMUX_IPSR_DATA(IP3_2_0, LCDOUT9),
 822         PINMUX_IPSR_DATA(IP3_2_0, DACK1),
 823         PINMUX_IPSR_MSEL(IP3_2_0, SDA2, SEL_I2C2_0),
 824         PINMUX_IPSR_DATA(IP3_2_0, AUDATA3),
 825         PINMUX_IPSR_DATA(IP3_3, DU0_DG2),
 826         PINMUX_IPSR_DATA(IP3_3, LCDOUT10),
 827         PINMUX_IPSR_DATA(IP3_4, DU0_DG3),
 828         PINMUX_IPSR_DATA(IP3_4, LCDOUT11),
 829         PINMUX_IPSR_DATA(IP3_5, DU0_DG4),
 830         PINMUX_IPSR_DATA(IP3_5, LCDOUT12),
 831         PINMUX_IPSR_DATA(IP3_6, DU0_DG5),
 832         PINMUX_IPSR_DATA(IP3_6, LCDOUT13),
 833         PINMUX_IPSR_DATA(IP3_7, DU0_DG6),
 834         PINMUX_IPSR_DATA(IP3_7, LCDOUT14),
 835         PINMUX_IPSR_DATA(IP3_8, DU0_DG7),
 836         PINMUX_IPSR_DATA(IP3_8, LCDOUT15),
 837         PINMUX_IPSR_DATA(IP3_11_9, DU0_DB0),
 838         PINMUX_IPSR_DATA(IP3_11_9, LCDOUT16),
 839         PINMUX_IPSR_DATA(IP3_11_9, EX_WAIT1),
 840         PINMUX_IPSR_MSEL(IP3_11_9, SCL1, SEL_I2C1_0),
 841         PINMUX_IPSR_MSEL(IP3_11_9, TCLK1, SEL_TMU1_0),
 842         PINMUX_IPSR_DATA(IP3_11_9, AUDATA4),
 843         PINMUX_IPSR_DATA(IP3_14_12, DU0_DB1),
 844         PINMUX_IPSR_DATA(IP3_14_12, LCDOUT17),
 845         PINMUX_IPSR_DATA(IP3_14_12, EX_WAIT2),
 846         PINMUX_IPSR_MSEL(IP3_14_12, SDA1, SEL_I2C1_0),
 847         PINMUX_IPSR_MSEL(IP3_14_12, GPS_MAG_B, SEL_GPS_1),
 848         PINMUX_IPSR_DATA(IP3_14_12, AUDATA5),
 849         PINMUX_IPSR_MSEL(IP3_14_12, SCK5_C, SEL_SCIF5_2),
 850         PINMUX_IPSR_DATA(IP3_15, DU0_DB2),
 851         PINMUX_IPSR_DATA(IP3_15, LCDOUT18),
 852         PINMUX_IPSR_DATA(IP3_16, DU0_DB3),
 853         PINMUX_IPSR_DATA(IP3_16, LCDOUT19),
 854         PINMUX_IPSR_DATA(IP3_17, DU0_DB4),
 855         PINMUX_IPSR_DATA(IP3_17, LCDOUT20),
 856         PINMUX_IPSR_DATA(IP3_18, DU0_DB5),
 857         PINMUX_IPSR_DATA(IP3_18, LCDOUT21),
 858         PINMUX_IPSR_DATA(IP3_19, DU0_DB6),
 859         PINMUX_IPSR_DATA(IP3_19, LCDOUT22),
 860         PINMUX_IPSR_DATA(IP3_20, DU0_DB7),
 861         PINMUX_IPSR_DATA(IP3_20, LCDOUT23),
 862         PINMUX_IPSR_DATA(IP3_22_21, DU0_DOTCLKIN),
 863         PINMUX_IPSR_DATA(IP3_22_21, QSTVA_QVS),
 864         PINMUX_IPSR_DATA(IP3_22_21, TX3_D_IRDA_TX_D),
 865         PINMUX_IPSR_MSEL(IP3_22_21, SCL3_B, SEL_I2C3_1),
 866         PINMUX_IPSR_DATA(IP3_23, DU0_DOTCLKOUT0),
 867         PINMUX_IPSR_DATA(IP3_23, QCLK),
 868         PINMUX_IPSR_DATA(IP3_26_24, DU0_DOTCLKOUT1),
 869         PINMUX_IPSR_DATA(IP3_26_24, QSTVB_QVE),
 870         PINMUX_IPSR_MSEL(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3),
 871         PINMUX_IPSR_MSEL(IP3_26_24, SDA3_B, SEL_I2C3_1),
 872         PINMUX_IPSR_MSEL(IP3_26_24, SDA2_C, SEL_I2C2_2),
 873         PINMUX_IPSR_DATA(IP3_26_24, DACK0_B),
 874         PINMUX_IPSR_DATA(IP3_26_24, DRACK0_B),
 875         PINMUX_IPSR_DATA(IP3_27, DU0_EXHSYNC_DU0_HSYNC),
 876         PINMUX_IPSR_DATA(IP3_27, QSTH_QHS),
 877         PINMUX_IPSR_DATA(IP3_28, DU0_EXVSYNC_DU0_VSYNC),
 878         PINMUX_IPSR_DATA(IP3_28, QSTB_QHE),
 879         PINMUX_IPSR_DATA(IP3_31_29, DU0_EXODDF_DU0_ODDF_DISP_CDE),
 880         PINMUX_IPSR_DATA(IP3_31_29, QCPV_QDE),
 881         PINMUX_IPSR_DATA(IP3_31_29, CAN1_TX),
 882         PINMUX_IPSR_DATA(IP3_31_29, TX2_C),
 883         PINMUX_IPSR_MSEL(IP3_31_29, SCL2_C, SEL_I2C2_2),
 884         PINMUX_IPSR_DATA(IP3_31_29, REMOCON),
 885
 886         PINMUX_IPSR_DATA(IP4_1_0, DU0_DISP),
 887         PINMUX_IPSR_DATA(IP4_1_0, QPOLA),
 888         PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2),
 889         PINMUX_IPSR_MSEL(IP4_1_0, SCK2_C, SEL_SCIF2_2),
 890         PINMUX_IPSR_DATA(IP4_4_2, DU0_CDE),
 891         PINMUX_IPSR_DATA(IP4_4_2, QPOLB),
 892         PINMUX_IPSR_DATA(IP4_4_2, CAN1_RX),
 893         PINMUX_IPSR_MSEL(IP4_4_2, RX2_C, SEL_SCIF2_2),
 894         PINMUX_IPSR_MSEL(IP4_4_2, DREQ0_B, SEL_EXBUS0_1),
 895         PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1),
 896         PINMUX_IPSR_MSEL(IP4_4_2, SCK0_B, SEL_SCIF0_1),
 897         PINMUX_IPSR_DATA(IP4_7_5, DU1_DR0),
 898         PINMUX_IPSR_DATA(IP4_7_5, VI2_DATA0_VI2_B0),
 899         PINMUX_IPSR_DATA(IP4_7_5, PWM6),
 900         PINMUX_IPSR_DATA(IP4_7_5, SD3_CLK),
 901         PINMUX_IPSR_DATA(IP4_7_5, TX3_E_IRDA_TX_E),
 902         PINMUX_IPSR_DATA(IP4_7_5, AUDCK),
 903         PINMUX_IPSR_MSEL(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1),
 904         PINMUX_IPSR_DATA(IP4_10_8, DU1_DR1),
 905         PINMUX_IPSR_DATA(IP4_10_8, VI2_DATA1_VI2_B1),
 906         PINMUX_IPSR_DATA(IP4_10_8, PWM0),
 907         PINMUX_IPSR_DATA(IP4_10_8, SD3_CMD),
 908         PINMUX_IPSR_MSEL(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4),
 909         PINMUX_IPSR_DATA(IP4_10_8, AUDSYNC),
 910         PINMUX_IPSR_MSEL(IP4_10_8, CTS0_D, SEL_SCIF0_3),
 911         PINMUX_IPSR_DATA(IP4_11, DU1_DR2),
 912         PINMUX_IPSR_DATA(IP4_11, VI2_G0),
 913         PINMUX_IPSR_DATA(IP4_12, DU1_DR3),
 914         PINMUX_IPSR_DATA(IP4_12, VI2_G1),
 915         PINMUX_IPSR_DATA(IP4_13, DU1_DR4),
 916         PINMUX_IPSR_DATA(IP4_13, VI2_G2),
 917         PINMUX_IPSR_DATA(IP4_14, DU1_DR5),
 918         PINMUX_IPSR_DATA(IP4_14, VI2_G3),
 919         PINMUX_IPSR_DATA(IP4_15, DU1_DR6),
 920         PINMUX_IPSR_DATA(IP4_15, VI2_G4),
 921         PINMUX_IPSR_DATA(IP4_16, DU1_DR7),
 922         PINMUX_IPSR_DATA(IP4_16, VI2_G5),
 923         PINMUX_IPSR_DATA(IP4_19_17, DU1_DG0),
 924         PINMUX_IPSR_DATA(IP4_19_17, VI2_DATA2_VI2_B2),
 925         PINMUX_IPSR_MSEL(IP4_19_17, SCL1_B, SEL_I2C1_1),
 926         PINMUX_IPSR_DATA(IP4_19_17, SD3_DAT2),
 927         PINMUX_IPSR_MSEL(IP4_19_17, SCK3_E, SEL_SCIF3_4),
 928         PINMUX_IPSR_DATA(IP4_19_17, AUDATA6),
 929         PINMUX_IPSR_DATA(IP4_19_17, TX0_D),
 930         PINMUX_IPSR_DATA(IP4_22_20, DU1_DG1),
 931         PINMUX_IPSR_DATA(IP4_22_20, VI2_DATA3_VI2_B3),
 932         PINMUX_IPSR_MSEL(IP4_22_20, SDA1_B, SEL_I2C1_1),
 933         PINMUX_IPSR_DATA(IP4_22_20, SD3_DAT3),
 934         PINMUX_IPSR_MSEL(IP4_22_20, SCK5, SEL_SCIF5_0),
 935         PINMUX_IPSR_DATA(IP4_22_20, AUDATA7),
 936         PINMUX_IPSR_MSEL(IP4_22_20, RX0_D, SEL_SCIF0_3),
 937         PINMUX_IPSR_DATA(IP4_23, DU1_DG2),
 938         PINMUX_IPSR_DATA(IP4_23, VI2_G6),
 939         PINMUX_IPSR_DATA(IP4_24, DU1_DG3),
 940         PINMUX_IPSR_DATA(IP4_24, VI2_G7),
 941         PINMUX_IPSR_DATA(IP4_25, DU1_DG4),
 942         PINMUX_IPSR_DATA(IP4_25, VI2_R0),
 943         PINMUX_IPSR_DATA(IP4_26, DU1_DG5),
 944         PINMUX_IPSR_DATA(IP4_26, VI2_R1),
 945         PINMUX_IPSR_DATA(IP4_27, DU1_DG6),
 946         PINMUX_IPSR_DATA(IP4_27, VI2_R2),
 947         PINMUX_IPSR_DATA(IP4_28, DU1_DG7),
 948         PINMUX_IPSR_DATA(IP4_28, VI2_R3),
 949         PINMUX_IPSR_DATA(IP4_31_29, DU1_DB0),
 950         PINMUX_IPSR_DATA(IP4_31_29, VI2_DATA4_VI2_B4),
 951         PINMUX_IPSR_MSEL(IP4_31_29, SCL2_B, SEL_I2C2_1),
 952         PINMUX_IPSR_DATA(IP4_31_29, SD3_DAT0),
 953         PINMUX_IPSR_DATA(IP4_31_29, TX5),
 954         PINMUX_IPSR_MSEL(IP4_31_29, SCK0_D, SEL_SCIF0_3),
 955
 956         PINMUX_IPSR_DATA(IP5_2_0, DU1_DB1),
 957         PINMUX_IPSR_DATA(IP5_2_0, VI2_DATA5_VI2_B5),
 958         PINMUX_IPSR_MSEL(IP5_2_0, SDA2_B, SEL_I2C2_1),
 959         PINMUX_IPSR_DATA(IP5_2_0, SD3_DAT1),
 960         PINMUX_IPSR_MSEL(IP5_2_0, RX5, SEL_SCIF5_0),
 961         PINMUX_IPSR_MSEL(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3),
 962         PINMUX_IPSR_DATA(IP5_3, DU1_DB2),
 963         PINMUX_IPSR_DATA(IP5_3, VI2_R4),
 964         PINMUX_IPSR_DATA(IP5_4, DU1_DB3),
 965         PINMUX_IPSR_DATA(IP5_4, VI2_R5),
 966         PINMUX_IPSR_DATA(IP5_5, DU1_DB4),
 967         PINMUX_IPSR_DATA(IP5_5, VI2_R6),
 968         PINMUX_IPSR_DATA(IP5_6, DU1_DB5),
 969         PINMUX_IPSR_DATA(IP5_6, VI2_R7),
 970         PINMUX_IPSR_DATA(IP5_7, DU1_DB6),
 971         PINMUX_IPSR_MSEL(IP5_7, SCL2_D, SEL_I2C2_3),
 972         PINMUX_IPSR_DATA(IP5_8, DU1_DB7),
 973         PINMUX_IPSR_MSEL(IP5_8, SDA2_D, SEL_I2C2_3),
 974         PINMUX_IPSR_DATA(IP5_10_9, DU1_DOTCLKIN),
 975         PINMUX_IPSR_DATA(IP5_10_9, VI2_CLKENB),
 976         PINMUX_IPSR_MSEL(IP5_10_9, HSPI_CS1, SEL_HSPI1_0),
 977         PINMUX_IPSR_MSEL(IP5_10_9, SCL1_D, SEL_I2C1_3),
 978         PINMUX_IPSR_DATA(IP5_12_11, DU1_DOTCLKOUT),
 979         PINMUX_IPSR_DATA(IP5_12_11, VI2_FIELD),
 980         PINMUX_IPSR_MSEL(IP5_12_11, SDA1_D, SEL_I2C1_3),
 981         PINMUX_IPSR_DATA(IP5_14_13, DU1_EXHSYNC_DU1_HSYNC),
 982         PINMUX_IPSR_DATA(IP5_14_13, VI2_HSYNC),
 983         PINMUX_IPSR_DATA(IP5_14_13, VI3_HSYNC),
 984         PINMUX_IPSR_DATA(IP5_16_15, DU1_EXVSYNC_DU1_VSYNC),
 985         PINMUX_IPSR_DATA(IP5_16_15, VI2_VSYNC),
 986         PINMUX_IPSR_DATA(IP5_16_15, VI3_VSYNC),
 987         PINMUX_IPSR_DATA(IP5_20_17, DU1_EXODDF_DU1_ODDF_DISP_CDE),
 988         PINMUX_IPSR_DATA(IP5_20_17, VI2_CLK),
 989         PINMUX_IPSR_DATA(IP5_20_17, TX3_B_IRDA_TX_B),
 990         PINMUX_IPSR_DATA(IP5_20_17, SD3_CD),
 991         PINMUX_IPSR_DATA(IP5_20_17, HSPI_TX1),
 992         PINMUX_IPSR_DATA(IP5_20_17, VI1_CLKENB),
 993         PINMUX_IPSR_DATA(IP5_20_17, VI3_CLKENB),
 994         PINMUX_IPSR_DATA(IP5_20_17, AUDIO_CLKC),
 995         PINMUX_IPSR_DATA(IP5_20_17, TX2_D),
 996         PINMUX_IPSR_DATA(IP5_20_17, SPEEDIN),
 997         PINMUX_IPSR_MSEL(IP5_20_17, GPS_SIGN_D, SEL_GPS_3),
 998         PINMUX_IPSR_DATA(IP5_23_21, DU1_DISP),
 999         PINMUX_IPSR_DATA(IP5_23_21, VI2_DATA6_VI2_B6),
1000         PINMUX_IPSR_MSEL(IP5_23_21, TCLK0, SEL_TMU0_0),
1001         PINMUX_IPSR_DATA(IP5_23_21, QSTVA_B_QVS_B),
1002         PINMUX_IPSR_MSEL(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0),
1003         PINMUX_IPSR_MSEL(IP5_23_21, SCK2_D, SEL_SCIF2_3),
1004         PINMUX_IPSR_DATA(IP5_23_21, AUDIO_CLKOUT_B),
1005         PINMUX_IPSR_MSEL(IP5_23_21, GPS_MAG_D, SEL_GPS_3),
1006         PINMUX_IPSR_DATA(IP5_27_24, DU1_CDE),
1007         PINMUX_IPSR_DATA(IP5_27_24, VI2_DATA7_VI2_B7),
1008         PINMUX_IPSR_MSEL(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1),
1009         PINMUX_IPSR_DATA(IP5_27_24, SD3_WP),
1010         PINMUX_IPSR_MSEL(IP5_27_24, HSPI_RX1, SEL_HSPI1_0),
1011         PINMUX_IPSR_DATA(IP5_27_24, VI1_FIELD),
1012         PINMUX_IPSR_DATA(IP5_27_24, VI3_FIELD),
1013         PINMUX_IPSR_DATA(IP5_27_24, AUDIO_CLKOUT),
1014         PINMUX_IPSR_MSEL(IP5_27_24, RX2_D, SEL_SCIF2_3),
1015         PINMUX_IPSR_MSEL(IP5_27_24, GPS_CLK_C, SEL_GPS_2),
1016         PINMUX_IPSR_MSEL(IP5_27_24, GPS_CLK_D, SEL_GPS_3),
1017         PINMUX_IPSR_DATA(IP5_28, AUDIO_CLKA),
1018         PINMUX_IPSR_DATA(IP5_28, CAN_TXCLK),
1019         PINMUX_IPSR_DATA(IP5_30_29, AUDIO_CLKB),
1020         PINMUX_IPSR_DATA(IP5_30_29, USB_OVC2),
1021         PINMUX_IPSR_DATA(IP5_30_29, CAN_DEBUGOUT0),
1022         PINMUX_IPSR_DATA(IP5_30_29, MOUT0),
1023
1024         PINMUX_IPSR_DATA(IP6_1_0, SSI_SCK0129),
1025         PINMUX_IPSR_DATA(IP6_1_0, CAN_DEBUGOUT1),
1026         PINMUX_IPSR_DATA(IP6_1_0, MOUT1),
1027         PINMUX_IPSR_DATA(IP6_3_2, SSI_WS0129),
1028         PINMUX_IPSR_DATA(IP6_3_2, CAN_DEBUGOUT2),
1029         PINMUX_IPSR_DATA(IP6_3_2, MOUT2),
1030         PINMUX_IPSR_DATA(IP6_5_4, SSI_SDATA0),
1031         PINMUX_IPSR_DATA(IP6_5_4, CAN_DEBUGOUT3),
1032         PINMUX_IPSR_DATA(IP6_5_4, MOUT5),
1033         PINMUX_IPSR_DATA(IP6_7_6, SSI_SDATA1),
1034         PINMUX_IPSR_DATA(IP6_7_6, CAN_DEBUGOUT4),
1035         PINMUX_IPSR_DATA(IP6_7_6, MOUT6),
1036         PINMUX_IPSR_DATA(IP6_8, SSI_SDATA2),
1037         PINMUX_IPSR_DATA(IP6_8, CAN_DEBUGOUT5),
1038         PINMUX_IPSR_DATA(IP6_11_9, SSI_SCK34),
1039         PINMUX_IPSR_DATA(IP6_11_9, CAN_DEBUGOUT6),
1040         PINMUX_IPSR_DATA(IP6_11_9, CAN0_TX_B),
1041         PINMUX_IPSR_MSEL(IP6_11_9, IERX, SEL_IE_0),
1042         PINMUX_IPSR_MSEL(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2),
1043         PINMUX_IPSR_DATA(IP6_14_12, SSI_WS34),
1044         PINMUX_IPSR_DATA(IP6_14_12, CAN_DEBUGOUT7),
1045         PINMUX_IPSR_MSEL(IP6_14_12, CAN0_RX_B, SEL_CAN0_1),
1046         PINMUX_IPSR_DATA(IP6_14_12, IETX),
1047         PINMUX_IPSR_MSEL(IP6_14_12, SSI_WS9_C, SEL_SSI9_2),
1048         PINMUX_IPSR_DATA(IP6_17_15, SSI_SDATA3),
1049         PINMUX_IPSR_DATA(IP6_17_15, PWM0_C),
1050         PINMUX_IPSR_DATA(IP6_17_15, CAN_DEBUGOUT8),
1051         PINMUX_IPSR_MSEL(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1),
1052         PINMUX_IPSR_MSEL(IP6_17_15, IECLK, SEL_IE_0),
1053         PINMUX_IPSR_MSEL(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1),
1054         PINMUX_IPSR_MSEL(IP6_17_15, TCLK0_B, SEL_TMU0_1),
1055         PINMUX_IPSR_DATA(IP6_19_18, SSI_SDATA4),
1056         PINMUX_IPSR_DATA(IP6_19_18, CAN_DEBUGOUT9),
1057         PINMUX_IPSR_MSEL(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2),
1058         PINMUX_IPSR_DATA(IP6_22_20, SSI_SCK5),
1059         PINMUX_IPSR_DATA(IP6_22_20, ADICLK),
1060         PINMUX_IPSR_DATA(IP6_22_20, CAN_DEBUGOUT10),
1061         PINMUX_IPSR_MSEL(IP6_22_20, SCK3, SEL_SCIF3_0),
1062         PINMUX_IPSR_MSEL(IP6_22_20, TCLK0_D, SEL_TMU0_3),
1063         PINMUX_IPSR_DATA(IP6_24_23, SSI_WS5),
1064         PINMUX_IPSR_MSEL(IP6_24_23, ADICS_SAMP, SEL_ADI_0),
1065         PINMUX_IPSR_DATA(IP6_24_23, CAN_DEBUGOUT11),
1066         PINMUX_IPSR_DATA(IP6_24_23, TX3_IRDA_TX),
1067         PINMUX_IPSR_DATA(IP6_26_25, SSI_SDATA5),
1068         PINMUX_IPSR_MSEL(IP6_26_25, ADIDATA, SEL_ADI_0),
1069         PINMUX_IPSR_DATA(IP6_26_25, CAN_DEBUGOUT12),
1070         PINMUX_IPSR_MSEL(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0),
1071         PINMUX_IPSR_DATA(IP6_30_29, SSI_SCK6),
1072         PINMUX_IPSR_DATA(IP6_30_29, ADICHS0),
1073         PINMUX_IPSR_DATA(IP6_30_29, CAN0_TX),
1074         PINMUX_IPSR_MSEL(IP6_30_29, IERX_B, SEL_IE_1),
1075
1076         PINMUX_IPSR_DATA(IP7_1_0, SSI_WS6),
1077         PINMUX_IPSR_DATA(IP7_1_0, ADICHS1),
1078         PINMUX_IPSR_MSEL(IP7_1_0, CAN0_RX, SEL_CAN0_0),
1079         PINMUX_IPSR_DATA(IP7_1_0, IETX_B),
1080         PINMUX_IPSR_DATA(IP7_3_2, SSI_SDATA6),
1081         PINMUX_IPSR_DATA(IP7_3_2, ADICHS2),
1082         PINMUX_IPSR_MSEL(IP7_3_2, CAN_CLK, SEL_CANCLK_0),
1083         PINMUX_IPSR_MSEL(IP7_3_2, IECLK_B, SEL_IE_1),
1084         PINMUX_IPSR_MSEL(IP7_6_4, SSI_SCK78, SEL_SSI7_0),
1085         PINMUX_IPSR_DATA(IP7_6_4, CAN_DEBUGOUT13),
1086         PINMUX_IPSR_MSEL(IP7_6_4, IRQ0_B, SEL_INT0_1),
1087         PINMUX_IPSR_MSEL(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1),
1088         PINMUX_IPSR_MSEL(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2),
1089         PINMUX_IPSR_MSEL(IP7_9_7, SSI_WS78, SEL_SSI7_0),
1090         PINMUX_IPSR_DATA(IP7_9_7, CAN_DEBUGOUT14),
1091         PINMUX_IPSR_MSEL(IP7_9_7, IRQ1_B, SEL_INT1_1),
1092         PINMUX_IPSR_MSEL(IP7_9_7, SSI_WS9_B, SEL_SSI9_1),
1093         PINMUX_IPSR_MSEL(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2),
1094         PINMUX_IPSR_MSEL(IP7_12_10, SSI_SDATA7, SEL_SSI7_0),
1095         PINMUX_IPSR_DATA(IP7_12_10, CAN_DEBUGOUT15),
1096         PINMUX_IPSR_MSEL(IP7_12_10, IRQ2_B, SEL_INT2_1),
1097         PINMUX_IPSR_MSEL(IP7_12_10, TCLK1_C, SEL_TMU1_2),
1098         PINMUX_IPSR_DATA(IP7_12_10, HSPI_TX1_C),
1099         PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA8, SEL_SSI8_0),
1100         PINMUX_IPSR_DATA(IP7_14_13, VSP),
1101         PINMUX_IPSR_MSEL(IP7_14_13, IRQ3_B, SEL_INT3_1),
1102         PINMUX_IPSR_MSEL(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2),
1103         PINMUX_IPSR_DATA(IP7_16_15, SD0_CLK),
1104         PINMUX_IPSR_DATA(IP7_16_15, ATACS01),
1105         PINMUX_IPSR_MSEL(IP7_16_15, SCK1_B, SEL_SCIF1_1),
1106         PINMUX_IPSR_DATA(IP7_18_17, SD0_CMD),
1107         PINMUX_IPSR_DATA(IP7_18_17, ATACS11),
1108         PINMUX_IPSR_DATA(IP7_18_17, TX1_B),
1109         PINMUX_IPSR_DATA(IP7_18_17, CC5_TDO),
1110         PINMUX_IPSR_DATA(IP7_20_19, SD0_DAT0),
1111         PINMUX_IPSR_DATA(IP7_20_19, ATADIR1),
1112         PINMUX_IPSR_MSEL(IP7_20_19, RX1_B, SEL_SCIF1_1),
1113         PINMUX_IPSR_DATA(IP7_20_19, CC5_TRST),
1114         PINMUX_IPSR_DATA(IP7_22_21, SD0_DAT1),
1115         PINMUX_IPSR_DATA(IP7_22_21, ATAG1),
1116         PINMUX_IPSR_MSEL(IP7_22_21, SCK2_B, SEL_SCIF2_1),
1117         PINMUX_IPSR_DATA(IP7_22_21, CC5_TMS),
1118         PINMUX_IPSR_DATA(IP7_24_23, SD0_DAT2),
1119         PINMUX_IPSR_DATA(IP7_24_23, ATARD1),
1120         PINMUX_IPSR_DATA(IP7_24_23, TX2_B),
1121         PINMUX_IPSR_DATA(IP7_24_23, CC5_TCK),
1122         PINMUX_IPSR_DATA(IP7_26_25, SD0_DAT3),
1123         PINMUX_IPSR_DATA(IP7_26_25, ATAWR1),
1124         PINMUX_IPSR_MSEL(IP7_26_25, RX2_B, SEL_SCIF2_1),
1125         PINMUX_IPSR_DATA(IP7_26_25, CC5_TDI),
1126         PINMUX_IPSR_DATA(IP7_28_27, SD0_CD),
1127         PINMUX_IPSR_MSEL(IP7_28_27, DREQ2, SEL_EXBUS2_0),
1128         PINMUX_IPSR_MSEL(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1),
1129         PINMUX_IPSR_DATA(IP7_30_29, SD0_WP),
1130         PINMUX_IPSR_DATA(IP7_30_29, DACK2),
1131         PINMUX_IPSR_MSEL(IP7_30_29, CTS1_B, SEL_SCIF1_1),
1132
1133         PINMUX_IPSR_DATA(IP8_3_0, HSPI_CLK0),
1134         PINMUX_IPSR_MSEL(IP8_3_0, CTS0, SEL_SCIF0_0),
1135         PINMUX_IPSR_DATA(IP8_3_0, USB_OVC0),
1136         PINMUX_IPSR_DATA(IP8_3_0, AD_CLK),
1137         PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE4),
1138         PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE12),
1139         PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE20),
1140         PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE28),
1141         PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE36),
1142         PINMUX_IPSR_DATA(IP8_7_4, HSPI_CS0),
1143         PINMUX_IPSR_MSEL(IP8_7_4, RTS0_TANS, SEL_SCIF0_0),
1144         PINMUX_IPSR_DATA(IP8_7_4, USB_OVC1),
1145         PINMUX_IPSR_DATA(IP8_7_4, AD_DI),
1146         PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE5),
1147         PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE13),
1148         PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE21),
1149         PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE29),
1150         PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE37),
1151         PINMUX_IPSR_DATA(IP8_11_8, HSPI_TX0),
1152         PINMUX_IPSR_DATA(IP8_11_8, TX0),
1153         PINMUX_IPSR_DATA(IP8_11_8, CAN_DEBUG_HW_TRIGGER),
1154         PINMUX_IPSR_DATA(IP8_11_8, AD_DO),
1155         PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE6),
1156         PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE14),
1157         PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE22),
1158         PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE30),
1159         PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE38),
1160         PINMUX_IPSR_DATA(IP8_15_12, HSPI_RX0),
1161         PINMUX_IPSR_MSEL(IP8_15_12, RX0, SEL_SCIF0_0),
1162         PINMUX_IPSR_DATA(IP8_15_12, CAN_STEP0),
1163         PINMUX_IPSR_DATA(IP8_15_12, AD_NCS),
1164         PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE7),
1165         PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE15),
1166         PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE23),
1167         PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE31),
1168         PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE39),
1169         PINMUX_IPSR_DATA(IP8_17_16, FMCLK),
1170         PINMUX_IPSR_DATA(IP8_17_16, RDS_CLK),
1171         PINMUX_IPSR_DATA(IP8_17_16, PCMOE),
1172         PINMUX_IPSR_DATA(IP8_18, BPFCLK),
1173         PINMUX_IPSR_DATA(IP8_18, PCMWE),
1174         PINMUX_IPSR_DATA(IP8_19, FMIN),
1175         PINMUX_IPSR_DATA(IP8_19, RDS_DATA),
1176         PINMUX_IPSR_DATA(IP8_20, VI0_CLK),
1177         PINMUX_IPSR_DATA(IP8_20, MMC1_CLK),
1178         PINMUX_IPSR_DATA(IP8_22_21, VI0_CLKENB),
1179         PINMUX_IPSR_DATA(IP8_22_21, TX1_C),
1180         PINMUX_IPSR_DATA(IP8_22_21, HTX1_B),
1181         PINMUX_IPSR_DATA(IP8_22_21, MT1_SYNC),
1182         PINMUX_IPSR_DATA(IP8_24_23, VI0_FIELD),
1183         PINMUX_IPSR_MSEL(IP8_24_23, RX1_C, SEL_SCIF1_2),
1184         PINMUX_IPSR_MSEL(IP8_24_23, HRX1_B, SEL_HSCIF1_1),
1185         PINMUX_IPSR_DATA(IP8_27_25, VI0_HSYNC),
1186         PINMUX_IPSR_MSEL(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1),
1187         PINMUX_IPSR_MSEL(IP8_27_25, CTS1_C, SEL_SCIF1_2),
1188         PINMUX_IPSR_DATA(IP8_27_25, TX4_D),
1189         PINMUX_IPSR_DATA(IP8_27_25, MMC1_CMD),
1190         PINMUX_IPSR_MSEL(IP8_27_25, HSCK1_B, SEL_HSCIF1_1),
1191         PINMUX_IPSR_DATA(IP8_30_28, VI0_VSYNC),
1192         PINMUX_IPSR_MSEL(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1),
1193         PINMUX_IPSR_MSEL(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2),
1194         PINMUX_IPSR_MSEL(IP8_30_28, RX4_D, SEL_SCIF4_3),
1195         PINMUX_IPSR_MSEL(IP8_30_28, PWMFSW0_C, SEL_PWMFSW_2),
1196
1197         PINMUX_IPSR_MSEL(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0),
1198         PINMUX_IPSR_MSEL(IP9_1_0, HRTS1_B, SEL_HSCIF1_1),
1199         PINMUX_IPSR_DATA(IP9_1_0, MT1_VCXO),
1200         PINMUX_IPSR_MSEL(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0),
1201         PINMUX_IPSR_MSEL(IP9_3_2, HCTS1_B, SEL_HSCIF1_1),
1202         PINMUX_IPSR_DATA(IP9_3_2, MT1_PWM),
1203         PINMUX_IPSR_DATA(IP9_4, VI0_DATA2_VI0_B2),
1204         PINMUX_IPSR_DATA(IP9_4, MMC1_D0),
1205         PINMUX_IPSR_DATA(IP9_5, VI0_DATA3_VI0_B3),
1206         PINMUX_IPSR_DATA(IP9_5, MMC1_D1),
1207         PINMUX_IPSR_DATA(IP9_6, VI0_DATA4_VI0_B4),
1208         PINMUX_IPSR_DATA(IP9_6, MMC1_D2),
1209         PINMUX_IPSR_DATA(IP9_7, VI0_DATA5_VI0_B5),
1210         PINMUX_IPSR_DATA(IP9_7, MMC1_D3),
1211         PINMUX_IPSR_DATA(IP9_9_8, VI0_DATA6_VI0_B6),
1212         PINMUX_IPSR_DATA(IP9_9_8, MMC1_D4),
1213         PINMUX_IPSR_DATA(IP9_9_8, ARM_TRACEDATA_0),
1214         PINMUX_IPSR_DATA(IP9_11_10, VI0_DATA7_VI0_B7),
1215         PINMUX_IPSR_DATA(IP9_11_10, MMC1_D5),
1216         PINMUX_IPSR_DATA(IP9_11_10, ARM_TRACEDATA_1),
1217         PINMUX_IPSR_DATA(IP9_13_12, VI0_G0),
1218         PINMUX_IPSR_MSEL(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2),
1219         PINMUX_IPSR_MSEL(IP9_13_12, IRQ0, SEL_INT0_0),
1220         PINMUX_IPSR_DATA(IP9_13_12, ARM_TRACEDATA_2),
1221         PINMUX_IPSR_DATA(IP9_15_14, VI0_G1),
1222         PINMUX_IPSR_MSEL(IP9_15_14, SSI_WS78_C, SEL_SSI7_2),
1223         PINMUX_IPSR_MSEL(IP9_15_14, IRQ1, SEL_INT1_0),
1224         PINMUX_IPSR_DATA(IP9_15_14, ARM_TRACEDATA_3),
1225         PINMUX_IPSR_DATA(IP9_18_16, VI0_G2),
1226         PINMUX_IPSR_DATA(IP9_18_16, ETH_TXD1),
1227         PINMUX_IPSR_DATA(IP9_18_16, MMC1_D6),
1228         PINMUX_IPSR_DATA(IP9_18_16, ARM_TRACEDATA_4),
1229         PINMUX_IPSR_DATA(IP9_18_16, TS_SPSYNC0),
1230         PINMUX_IPSR_DATA(IP9_21_19, VI0_G3),
1231         PINMUX_IPSR_DATA(IP9_21_19, ETH_CRS_DV),
1232         PINMUX_IPSR_DATA(IP9_21_19, MMC1_D7),
1233         PINMUX_IPSR_DATA(IP9_21_19, ARM_TRACEDATA_5),
1234         PINMUX_IPSR_DATA(IP9_21_19, TS_SDAT0),
1235         PINMUX_IPSR_DATA(IP9_23_22, VI0_G4),
1236         PINMUX_IPSR_DATA(IP9_23_22, ETH_TX_EN),
1237         PINMUX_IPSR_MSEL(IP9_23_22, SD2_DAT0_B, SEL_SD2_1),
1238         PINMUX_IPSR_DATA(IP9_23_22, ARM_TRACEDATA_6),
1239         PINMUX_IPSR_DATA(IP9_25_24, VI0_G5),
1240         PINMUX_IPSR_DATA(IP9_25_24, ETH_RX_ER),
1241         PINMUX_IPSR_MSEL(IP9_25_24, SD2_DAT1_B, SEL_SD2_1),
1242         PINMUX_IPSR_DATA(IP9_25_24, ARM_TRACEDATA_7),
1243         PINMUX_IPSR_DATA(IP9_27_26, VI0_G6),
1244         PINMUX_IPSR_DATA(IP9_27_26, ETH_RXD0),
1245         PINMUX_IPSR_MSEL(IP9_27_26, SD2_DAT2_B, SEL_SD2_1),
1246         PINMUX_IPSR_DATA(IP9_27_26, ARM_TRACEDATA_8),
1247         PINMUX_IPSR_DATA(IP9_29_28, VI0_G7),
1248         PINMUX_IPSR_DATA(IP9_29_28, ETH_RXD1),
1249         PINMUX_IPSR_MSEL(IP9_29_28, SD2_DAT3_B, SEL_SD2_1),
1250         PINMUX_IPSR_DATA(IP9_29_28, ARM_TRACEDATA_9),
1251
1252         PINMUX_IPSR_DATA(IP10_2_0, VI0_R0),
1253         PINMUX_IPSR_MSEL(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2),
1254         PINMUX_IPSR_MSEL(IP10_2_0, SCK1_C, SEL_SCIF1_2),
1255         PINMUX_IPSR_MSEL(IP10_2_0, DREQ1_B, SEL_EXBUS1_0),
1256         PINMUX_IPSR_DATA(IP10_2_0, ARM_TRACEDATA_10),
1257         PINMUX_IPSR_MSEL(IP10_2_0, DREQ0_C, SEL_EXBUS0_2),
1258         PINMUX_IPSR_DATA(IP10_5_3, VI0_R1),
1259         PINMUX_IPSR_MSEL(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2),
1260         PINMUX_IPSR_DATA(IP10_5_3, DACK1_B),
1261         PINMUX_IPSR_DATA(IP10_5_3, ARM_TRACEDATA_11),
1262         PINMUX_IPSR_DATA(IP10_5_3, DACK0_C),
1263         PINMUX_IPSR_DATA(IP10_5_3, DRACK0_C),
1264         PINMUX_IPSR_DATA(IP10_8_6, VI0_R2),
1265         PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK),
1266         PINMUX_IPSR_DATA(IP10_8_6, SD2_CLK_B),
1267         PINMUX_IPSR_MSEL(IP10_8_6, IRQ2, SEL_INT2_0),
1268         PINMUX_IPSR_DATA(IP10_8_6, ARM_TRACEDATA_12),
1269         PINMUX_IPSR_DATA(IP10_11_9, VI0_R3),
1270         PINMUX_IPSR_DATA(IP10_11_9, ETH_MAGIC),
1271         PINMUX_IPSR_MSEL(IP10_11_9, SD2_CMD_B, SEL_SD2_1),
1272         PINMUX_IPSR_MSEL(IP10_11_9, IRQ3, SEL_INT3_0),
1273         PINMUX_IPSR_DATA(IP10_11_9, ARM_TRACEDATA_13),
1274         PINMUX_IPSR_DATA(IP10_14_12, VI0_R4),
1275         PINMUX_IPSR_DATA(IP10_14_12, ETH_REFCLK),
1276         PINMUX_IPSR_MSEL(IP10_14_12, SD2_CD_B, SEL_SD2_1),
1277         PINMUX_IPSR_MSEL(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1),
1278         PINMUX_IPSR_DATA(IP10_14_12, ARM_TRACEDATA_14),
1279         PINMUX_IPSR_DATA(IP10_14_12, MT1_CLK),
1280         PINMUX_IPSR_DATA(IP10_14_12, TS_SCK0),
1281         PINMUX_IPSR_DATA(IP10_17_15, VI0_R5),
1282         PINMUX_IPSR_DATA(IP10_17_15, ETH_TXD0),
1283         PINMUX_IPSR_MSEL(IP10_17_15, SD2_WP_B, SEL_SD2_1),
1284         PINMUX_IPSR_MSEL(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1),
1285         PINMUX_IPSR_DATA(IP10_17_15, ARM_TRACEDATA_15),
1286         PINMUX_IPSR_DATA(IP10_17_15, MT1_D),
1287         PINMUX_IPSR_DATA(IP10_17_15, TS_SDEN0),
1288         PINMUX_IPSR_DATA(IP10_20_18, VI0_R6),
1289         PINMUX_IPSR_DATA(IP10_20_18, ETH_MDC),
1290         PINMUX_IPSR_MSEL(IP10_20_18, DREQ2_C, SEL_EXBUS2_2),
1291         PINMUX_IPSR_DATA(IP10_20_18, HSPI_TX1_B),
1292         PINMUX_IPSR_DATA(IP10_20_18, TRACECLK),
1293         PINMUX_IPSR_DATA(IP10_20_18, MT1_BEN),
1294         PINMUX_IPSR_MSEL(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3),
1295         PINMUX_IPSR_DATA(IP10_23_21, VI0_R7),
1296         PINMUX_IPSR_DATA(IP10_23_21, ETH_MDIO),
1297         PINMUX_IPSR_DATA(IP10_23_21, DACK2_C),
1298         PINMUX_IPSR_MSEL(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1),
1299         PINMUX_IPSR_MSEL(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3),
1300         PINMUX_IPSR_DATA(IP10_23_21, TRACECTL),
1301         PINMUX_IPSR_DATA(IP10_23_21, MT1_PEN),
1302         PINMUX_IPSR_DATA(IP10_25_24, VI1_CLK),
1303         PINMUX_IPSR_MSEL(IP10_25_24, SIM_D, SEL_SIM_0),
1304         PINMUX_IPSR_MSEL(IP10_25_24, SDA3, SEL_I2C3_0),
1305         PINMUX_IPSR_DATA(IP10_28_26, VI1_HSYNC),
1306         PINMUX_IPSR_DATA(IP10_28_26, VI3_CLK),
1307         PINMUX_IPSR_DATA(IP10_28_26, SSI_SCK4),
1308         PINMUX_IPSR_MSEL(IP10_28_26, GPS_SIGN_C, SEL_GPS_2),
1309         PINMUX_IPSR_MSEL(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4),
1310         PINMUX_IPSR_DATA(IP10_31_29, VI1_VSYNC),
1311         PINMUX_IPSR_DATA(IP10_31_29, AUDIO_CLKOUT_C),
1312         PINMUX_IPSR_DATA(IP10_31_29, SSI_WS4),
1313         PINMUX_IPSR_DATA(IP10_31_29, SIM_CLK),
1314         PINMUX_IPSR_MSEL(IP10_31_29, GPS_MAG_C, SEL_GPS_2),
1315         PINMUX_IPSR_DATA(IP10_31_29, SPV_TRST),
1316         PINMUX_IPSR_MSEL(IP10_31_29, SCL3, SEL_I2C3_0),
1317
1318         PINMUX_IPSR_DATA(IP11_2_0, VI1_DATA0_VI1_B0),
1319         PINMUX_IPSR_MSEL(IP11_2_0, SD2_DAT0, SEL_SD2_0),
1320         PINMUX_IPSR_DATA(IP11_2_0, SIM_RST),
1321         PINMUX_IPSR_DATA(IP11_2_0, SPV_TCK),
1322         PINMUX_IPSR_DATA(IP11_2_0, ADICLK_B),
1323         PINMUX_IPSR_DATA(IP11_5_3, VI1_DATA1_VI1_B1),
1324         PINMUX_IPSR_MSEL(IP11_5_3, SD2_DAT1, SEL_SD2_0),
1325         PINMUX_IPSR_DATA(IP11_5_3, MT0_CLK),
1326         PINMUX_IPSR_DATA(IP11_5_3, SPV_TMS),
1327         PINMUX_IPSR_MSEL(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1),
1328         PINMUX_IPSR_DATA(IP11_8_6, VI1_DATA2_VI1_B2),
1329         PINMUX_IPSR_MSEL(IP11_8_6, SD2_DAT2, SEL_SD2_0),
1330         PINMUX_IPSR_DATA(IP11_8_6, MT0_D),
1331         PINMUX_IPSR_DATA(IP11_8_6, SPVTDI),
1332         PINMUX_IPSR_MSEL(IP11_8_6, ADIDATA_B, SEL_ADI_1),
1333         PINMUX_IPSR_DATA(IP11_11_9, VI1_DATA3_VI1_B3),
1334         PINMUX_IPSR_MSEL(IP11_11_9, SD2_DAT3, SEL_SD2_0),
1335         PINMUX_IPSR_DATA(IP11_11_9, MT0_BEN),
1336         PINMUX_IPSR_DATA(IP11_11_9, SPV_TDO),
1337         PINMUX_IPSR_DATA(IP11_11_9, ADICHS0_B),
1338         PINMUX_IPSR_DATA(IP11_14_12, VI1_DATA4_VI1_B4),
1339         PINMUX_IPSR_DATA(IP11_14_12, SD2_CLK),
1340         PINMUX_IPSR_DATA(IP11_14_12, MT0_PEN),
1341         PINMUX_IPSR_DATA(IP11_14_12, SPA_TRST),
1342         PINMUX_IPSR_MSEL(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3),
1343         PINMUX_IPSR_DATA(IP11_14_12, ADICHS1_B),
1344         PINMUX_IPSR_DATA(IP11_17_15, VI1_DATA5_VI1_B5),
1345         PINMUX_IPSR_MSEL(IP11_17_15, SD2_CMD, SEL_SD2_0),
1346         PINMUX_IPSR_DATA(IP11_17_15, MT0_SYNC),
1347         PINMUX_IPSR_DATA(IP11_17_15, SPA_TCK),
1348         PINMUX_IPSR_MSEL(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3),
1349         PINMUX_IPSR_DATA(IP11_17_15, ADICHS2_B),
1350         PINMUX_IPSR_DATA(IP11_20_18, VI1_DATA6_VI1_B6),
1351         PINMUX_IPSR_MSEL(IP11_20_18, SD2_CD, SEL_SD2_0),
1352         PINMUX_IPSR_DATA(IP11_20_18, MT0_VCXO),
1353         PINMUX_IPSR_DATA(IP11_20_18, SPA_TMS),
1354         PINMUX_IPSR_DATA(IP11_20_18, HSPI_TX1_D),
1355         PINMUX_IPSR_DATA(IP11_23_21, VI1_DATA7_VI1_B7),
1356         PINMUX_IPSR_MSEL(IP11_23_21, SD2_WP, SEL_SD2_0),
1357         PINMUX_IPSR_DATA(IP11_23_21, MT0_PWM),
1358         PINMUX_IPSR_DATA(IP11_23_21, SPA_TDI),
1359         PINMUX_IPSR_MSEL(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3),
1360         PINMUX_IPSR_DATA(IP11_26_24, VI1_G0),
1361         PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0),
1362         PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1),
1363         PINMUX_IPSR_MSEL(IP11_26_24, DREQ2_B, SEL_EXBUS2_1),
1364         PINMUX_IPSR_DATA(IP11_26_24, TX2),
1365         PINMUX_IPSR_DATA(IP11_26_24, SPA_TDO),
1366         PINMUX_IPSR_MSEL(IP11_26_24, HCTS0_B, SEL_HSCIF0_1),
1367         PINMUX_IPSR_DATA(IP11_29_27, VI1_G1),
1368         PINMUX_IPSR_DATA(IP11_29_27, VI3_DATA1),
1369         PINMUX_IPSR_DATA(IP11_29_27, SSI_SCK1),
1370         PINMUX_IPSR_DATA(IP11_29_27, TS_SDEN1),
1371         PINMUX_IPSR_DATA(IP11_29_27, DACK2_B),
1372         PINMUX_IPSR_MSEL(IP11_29_27, RX2, SEL_SCIF2_0),
1373         PINMUX_IPSR_MSEL(IP11_29_27, HRTS0_B, SEL_HSCIF0_1),
1374
1375         PINMUX_IPSR_DATA(IP12_2_0, VI1_G2),
1376         PINMUX_IPSR_DATA(IP12_2_0, VI3_DATA2),
1377         PINMUX_IPSR_DATA(IP12_2_0, SSI_WS1),
1378         PINMUX_IPSR_DATA(IP12_2_0, TS_SPSYNC1),
1379         PINMUX_IPSR_MSEL(IP12_2_0, SCK2, SEL_SCIF2_0),
1380         PINMUX_IPSR_MSEL(IP12_2_0, HSCK0_B, SEL_HSCIF0_1),
1381         PINMUX_IPSR_DATA(IP12_5_3, VI1_G3),
1382         PINMUX_IPSR_DATA(IP12_5_3, VI3_DATA3),
1383         PINMUX_IPSR_DATA(IP12_5_3, SSI_SCK2),
1384         PINMUX_IPSR_DATA(IP12_5_3, TS_SDAT1),
1385         PINMUX_IPSR_MSEL(IP12_5_3, SCL1_C, SEL_I2C1_2),
1386         PINMUX_IPSR_DATA(IP12_5_3, HTX0_B),
1387         PINMUX_IPSR_DATA(IP12_8_6, VI1_G4),
1388         PINMUX_IPSR_DATA(IP12_8_6, VI3_DATA4),
1389         PINMUX_IPSR_DATA(IP12_8_6, SSI_WS2),
1390         PINMUX_IPSR_MSEL(IP12_8_6, SDA1_C, SEL_I2C1_2),
1391         PINMUX_IPSR_DATA(IP12_8_6, SIM_RST_B),
1392         PINMUX_IPSR_MSEL(IP12_8_6, HRX0_B, SEL_HSCIF0_1),
1393         PINMUX_IPSR_DATA(IP12_11_9, VI1_G5),
1394         PINMUX_IPSR_DATA(IP12_11_9, VI3_DATA5),
1395         PINMUX_IPSR_MSEL(IP12_11_9, GPS_CLK, SEL_GPS_0),
1396         PINMUX_IPSR_DATA(IP12_11_9, FSE),
1397         PINMUX_IPSR_DATA(IP12_11_9, TX4_B),
1398         PINMUX_IPSR_MSEL(IP12_11_9, SIM_D_B, SEL_SIM_1),
1399         PINMUX_IPSR_DATA(IP12_14_12, VI1_G6),
1400         PINMUX_IPSR_DATA(IP12_14_12, VI3_DATA6),
1401         PINMUX_IPSR_MSEL(IP12_14_12, GPS_SIGN, SEL_GPS_0),
1402         PINMUX_IPSR_DATA(IP12_14_12, FRB),
1403         PINMUX_IPSR_MSEL(IP12_14_12, RX4_B, SEL_SCIF4_1),
1404         PINMUX_IPSR_DATA(IP12_14_12, SIM_CLK_B),
1405         PINMUX_IPSR_DATA(IP12_17_15, VI1_G7),
1406         PINMUX_IPSR_DATA(IP12_17_15, VI3_DATA7),
1407         PINMUX_IPSR_MSEL(IP12_17_15, GPS_MAG, SEL_GPS_0),
1408         PINMUX_IPSR_DATA(IP12_17_15, FCE),
1409         PINMUX_IPSR_MSEL(IP12_17_15, SCK4_B, SEL_SCIF4_1),
1410 };
1411
1412 static const struct sh_pfc_pin pinmux_pins[] = {
1413         PINMUX_GPIO_GP_ALL(),
1414 };
1415
1416 /* - DU0 -------------------------------------------------------------------- */
1417 static const unsigned int du0_rgb666_pins[] = {
1418         /* R[7:2], G[7:2], B[7:2] */
1419         RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26),
1420         RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
1421         RCAR_GP_PIN(6, 2),  RCAR_GP_PIN(6, 1),  RCAR_GP_PIN(6, 0),
1422         RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29),
1423         RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 7),  RCAR_GP_PIN(6, 6),
1424         RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 4),  RCAR_GP_PIN(6, 3),
1425 };
1426 static const unsigned int du0_rgb666_mux[] = {
1427         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1428         DU0_DR3_MARK, DU0_DR2_MARK,
1429         DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1430         DU0_DG3_MARK, DU0_DG2_MARK,
1431         DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1432         DU0_DB3_MARK, DU0_DB2_MARK,
1433 };
1434 static const unsigned int du0_rgb888_pins[] = {
1435         /* R[7:0], G[7:0], B[7:0] */
1436         RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26),
1437         RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
1438         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23), RCAR_GP_PIN(6, 2),
1439         RCAR_GP_PIN(6, 1),  RCAR_GP_PIN(6, 0),  RCAR_GP_PIN(5, 31),
1440         RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29), RCAR_GP_PIN(0, 26),
1441         RCAR_GP_PIN(0, 25), RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 7),
1442         RCAR_GP_PIN(6, 6),  RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 4),
1443         RCAR_GP_PIN(6, 3),  RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 27),
1444 };
1445 static const unsigned int du0_rgb888_mux[] = {
1446         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1447         DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
1448         DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1449         DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
1450         DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1451         DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
1452 };
1453 static const unsigned int du0_clk_in_pins[] = {
1454         /* CLKIN */
1455         RCAR_GP_PIN(0, 29),
1456 };
1457 static const unsigned int du0_clk_in_mux[] = {
1458         DU0_DOTCLKIN_MARK,
1459 };
1460 static const unsigned int du0_clk_out_0_pins[] = {
1461         /* CLKOUT */
1462         RCAR_GP_PIN(5, 20),
1463 };
1464 static const unsigned int du0_clk_out_0_mux[] = {
1465         DU0_DOTCLKOUT0_MARK,
1466 };
1467 static const unsigned int du0_clk_out_1_pins[] = {
1468         /* CLKOUT */
1469         RCAR_GP_PIN(0, 30),
1470 };
1471 static const unsigned int du0_clk_out_1_mux[] = {
1472         DU0_DOTCLKOUT1_MARK,
1473 };
1474 static const unsigned int du0_sync_0_pins[] = {
1475         /* VSYNC, HSYNC, DISP */
1476         RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(0, 31),
1477 };
1478 static const unsigned int du0_sync_0_mux[] = {
1479         DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
1480         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
1481 };
1482 static const unsigned int du0_sync_1_pins[] = {
1483         /* VSYNC, HSYNC, DISP */
1484         RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(1, 0),
1485 };
1486 static const unsigned int du0_sync_1_mux[] = {
1487         DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
1488         DU0_DISP_MARK
1489 };
1490 static const unsigned int du0_oddf_pins[] = {
1491         /* ODDF */
1492         RCAR_GP_PIN(0, 31),
1493 };
1494 static const unsigned int du0_oddf_mux[] = {
1495         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
1496 };
1497 static const unsigned int du0_cde_pins[] = {
1498         /* CDE */
1499         RCAR_GP_PIN(1, 1),
1500 };
1501 static const unsigned int du0_cde_mux[] = {
1502         DU0_CDE_MARK
1503 };
1504 /* - DU1 -------------------------------------------------------------------- */
1505 static const unsigned int du1_rgb666_pins[] = {
1506         /* R[7:2], G[7:2], B[7:2] */
1507         RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 8),  RCAR_GP_PIN(1, 7),
1508         RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),  RCAR_GP_PIN(1, 4),
1509         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
1510         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
1511         RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1512         RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 20),
1513 };
1514 static const unsigned int du1_rgb666_mux[] = {
1515         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1516         DU1_DR3_MARK, DU1_DR2_MARK,
1517         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1518         DU1_DG3_MARK, DU1_DG2_MARK,
1519         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1520         DU1_DB3_MARK, DU1_DB2_MARK,
1521 };
1522 static const unsigned int du1_rgb888_pins[] = {
1523         /* R[7:0], G[7:0], B[7:0] */
1524         RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 8),  RCAR_GP_PIN(1, 7),
1525         RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),  RCAR_GP_PIN(1, 4),
1526         RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 17),
1527         RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
1528         RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11),
1529         RCAR_GP_PIN(1, 0),  RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24),
1530         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1531         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1532 };
1533 static const unsigned int du1_rgb888_mux[] = {
1534         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1535         DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1536         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1537         DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1538         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1539         DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1540 };
1541 static const unsigned int du1_clk_in_pins[] = {
1542         /* CLKIN */
1543         RCAR_GP_PIN(1, 26),
1544 };
1545 static const unsigned int du1_clk_in_mux[] = {
1546         DU1_DOTCLKIN_MARK,
1547 };
1548 static const unsigned int du1_clk_out_pins[] = {
1549         /* CLKOUT */
1550         RCAR_GP_PIN(1, 27),
1551 };
1552 static const unsigned int du1_clk_out_mux[] = {
1553         DU1_DOTCLKOUT_MARK,
1554 };
1555 static const unsigned int du1_sync_0_pins[] = {
1556         /* VSYNC, HSYNC, DISP */
1557         RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 30),
1558 };
1559 static const unsigned int du1_sync_0_mux[] = {
1560         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
1561         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
1562 };
1563 static const unsigned int du1_sync_1_pins[] = {
1564         /* VSYNC, HSYNC, DISP */
1565         RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 31),
1566 };
1567 static const unsigned int du1_sync_1_mux[] = {
1568         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
1569         DU1_DISP_MARK
1570 };
1571 static const unsigned int du1_oddf_pins[] = {
1572         /* ODDF */
1573         RCAR_GP_PIN(1, 30),
1574 };
1575 static const unsigned int du1_oddf_mux[] = {
1576         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
1577 };
1578 static const unsigned int du1_cde_pins[] = {
1579         /* CDE */
1580         RCAR_GP_PIN(2, 0),
1581 };
1582 static const unsigned int du1_cde_mux[] = {
1583         DU1_CDE_MARK
1584 };
1585 /* - Ether ------------------------------------------------------------------ */
1586 static const unsigned int ether_rmii_pins[] = {
1587         /*
1588          * ETH_TXD0, ETH_TXD1, ETH_TX_EN,  ETH_REFCLK,
1589          * ETH_RXD0, ETH_RXD1, ETH_CRS_DV, ETH_RX_ER,
1590          * ETH_MDIO, ETH_MDC
1591          */
1592         RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 18),
1593         RCAR_GP_PIN(2, 26),
1594         RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 17),
1595         RCAR_GP_PIN(2, 19),
1596         RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 28),
1597 };
1598 static const unsigned int ether_rmii_mux[] = {
1599         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK,  ETH_REFCLK_MARK,
1600         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK,
1601         ETH_MDIO_MARK, ETH_MDC_MARK,
1602 };
1603 static const unsigned int ether_link_pins[] = {
1604         /* ETH_LINK */
1605         RCAR_GP_PIN(2, 24),
1606 };
1607 static const unsigned int ether_link_mux[] = {
1608         ETH_LINK_MARK,
1609 };
1610 static const unsigned int ether_magic_pins[] = {
1611         /* ETH_MAGIC */
1612         RCAR_GP_PIN(2, 25),
1613 };
1614 static const unsigned int ether_magic_mux[] = {
1615         ETH_MAGIC_MARK,
1616 };
1617 /* - HSPI0 ------------------------------------------------------------------ */
1618 static const unsigned int hspi0_pins[] = {
1619         /* CLK, CS, RX, TX */
1620         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 25),
1621         RCAR_GP_PIN(4, 24),
1622 };
1623 static const unsigned int hspi0_mux[] = {
1624         HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK,
1625 };
1626 /* - HSPI1 ------------------------------------------------------------------ */
1627 static const unsigned int hspi1_pins[] = {
1628         /* CLK, CS, RX, TX */
1629         RCAR_GP_PIN(1, 31), RCAR_GP_PIN(1, 26), RCAR_GP_PIN(2, 0),
1630         RCAR_GP_PIN(1, 30),
1631 };
1632 static const unsigned int hspi1_mux[] = {
1633         HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK,
1634 };
1635 static const unsigned int hspi1_b_pins[] = {
1636         /* CLK, CS, RX, TX */
1637         RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 29),
1638         RCAR_GP_PIN(2, 28),
1639 };
1640 static const unsigned int hspi1_b_mux[] = {
1641         HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK,
1642 };
1643 static const unsigned int hspi1_c_pins[] = {
1644         /* CLK, CS, RX, TX */
1645         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 16),
1646         RCAR_GP_PIN(4, 15),
1647 };
1648 static const unsigned int hspi1_c_mux[] = {
1649         HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK,
1650 };
1651 static const unsigned int hspi1_d_pins[] = {
1652         /* CLK, CS, RX, TX */
1653         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 8),
1654         RCAR_GP_PIN(3, 7),
1655 };
1656 static const unsigned int hspi1_d_mux[] = {
1657         HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK,
1658 };
1659 /* - HSPI2 ------------------------------------------------------------------ */
1660 static const unsigned int hspi2_pins[] = {
1661         /* CLK, CS, RX, TX */
1662         RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
1663         RCAR_GP_PIN(0, 14),
1664 };
1665 static const unsigned int hspi2_mux[] = {
1666         HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK,
1667 };
1668 static const unsigned int hspi2_b_pins[] = {
1669         /* CLK, CS, RX, TX */
1670         RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 8),
1671         RCAR_GP_PIN(0, 6),
1672 };
1673 static const unsigned int hspi2_b_mux[] = {
1674         HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK,
1675 };
1676 /* - I2C1 ------------------------------------------------------------------ */
1677 static const unsigned int i2c1_pins[] = {
1678         /* SCL, SDA, */
1679         RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
1680 };
1681 static const unsigned int i2c1_mux[] = {
1682         SCL1_MARK, SDA1_MARK,
1683 };
1684 static const unsigned int i2c1_b_pins[] = {
1685         /* SCL, SDA, */
1686         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
1687 };
1688 static const unsigned int i2c1_b_mux[] = {
1689         SCL1_B_MARK, SDA1_B_MARK,
1690 };
1691 static const unsigned int i2c1_c_pins[] = {
1692         /* SCL, SDA, */
1693         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1694 };
1695 static const unsigned int i2c1_c_mux[] = {
1696         SCL1_C_MARK, SDA1_C_MARK,
1697 };
1698 static const unsigned int i2c1_d_pins[] = {
1699         /* SCL, SDA, */
1700         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
1701 };
1702 static const unsigned int i2c1_d_mux[] = {
1703         SCL1_D_MARK, SDA1_D_MARK,
1704 };
1705 /* - I2C2 ------------------------------------------------------------------ */
1706 static const unsigned int i2c2_pins[] = {
1707         /* SCL, SDA, */
1708         RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 26),
1709 };
1710 static const unsigned int i2c2_mux[] = {
1711         SCL2_MARK, SDA2_MARK,
1712 };
1713 static const unsigned int i2c2_b_pins[] = {
1714         /* SCL, SDA, */
1715         RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
1716 };
1717 static const unsigned int i2c2_b_mux[] = {
1718         SCL2_B_MARK, SDA2_B_MARK,
1719 };
1720 static const unsigned int i2c2_c_pins[] = {
1721         /* SCL, SDA */
1722         RCAR_GP_PIN(0, 31), RCAR_GP_PIN(0, 30),
1723 };
1724 static const unsigned int i2c2_c_mux[] = {
1725         SCL2_C_MARK, SDA2_C_MARK,
1726 };
1727 static const unsigned int i2c2_d_pins[] = {
1728         /* SCL, SDA */
1729         RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
1730 };
1731 static const unsigned int i2c2_d_mux[] = {
1732         SCL2_D_MARK, SDA2_D_MARK,
1733 };
1734 /* - I2C3 ------------------------------------------------------------------ */
1735 static const unsigned int i2c3_pins[] = {
1736         /* SCL, SDA, */
1737         RCAR_GP_PIN(3, 0), RCAR_GP_PIN(2, 30),
1738 };
1739 static const unsigned int i2c3_mux[] = {
1740         SCL3_MARK, SDA3_MARK,
1741 };
1742 static const unsigned int i2c3_b_pins[] = {
1743         /* SCL, SDA, */
1744         RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 30),
1745 };
1746 static const unsigned int i2c3_b_mux[] = {
1747         SCL3_B_MARK, SDA3_B_MARK,
1748 };
1749 /* - INTC ------------------------------------------------------------------- */
1750 static const unsigned int intc_irq0_pins[] = {
1751         /* IRQ */
1752         RCAR_GP_PIN(2, 14),
1753 };
1754 static const unsigned int intc_irq0_mux[] = {
1755         IRQ0_MARK,
1756 };
1757 static const unsigned int intc_irq0_b_pins[] = {
1758         /* IRQ */
1759         RCAR_GP_PIN(4, 13),
1760 };
1761 static const unsigned int intc_irq0_b_mux[] = {
1762         IRQ0_B_MARK,
1763 };
1764 static const unsigned int intc_irq1_pins[] = {
1765         /* IRQ */
1766         RCAR_GP_PIN(2, 15),
1767 };
1768 static const unsigned int intc_irq1_mux[] = {
1769         IRQ1_MARK,
1770 };
1771 static const unsigned int intc_irq1_b_pins[] = {
1772         /* IRQ */
1773         RCAR_GP_PIN(4, 14),
1774 };
1775 static const unsigned int intc_irq1_b_mux[] = {
1776         IRQ1_B_MARK,
1777 };
1778 static const unsigned int intc_irq2_pins[] = {
1779         /* IRQ */
1780         RCAR_GP_PIN(2, 24),
1781 };
1782 static const unsigned int intc_irq2_mux[] = {
1783         IRQ2_MARK,
1784 };
1785 static const unsigned int intc_irq2_b_pins[] = {
1786         /* IRQ */
1787         RCAR_GP_PIN(4, 15),
1788 };
1789 static const unsigned int intc_irq2_b_mux[] = {
1790         IRQ2_B_MARK,
1791 };
1792 static const unsigned int intc_irq3_pins[] = {
1793         /* IRQ */
1794         RCAR_GP_PIN(2, 25),
1795 };
1796 static const unsigned int intc_irq3_mux[] = {
1797         IRQ3_MARK,
1798 };
1799 static const unsigned int intc_irq3_b_pins[] = {
1800         /* IRQ */
1801         RCAR_GP_PIN(4, 16),
1802 };
1803 static const unsigned int intc_irq3_b_mux[] = {
1804         IRQ3_B_MARK,
1805 };
1806 /* - LSBC ------------------------------------------------------------------- */
1807 static const unsigned int lbsc_cs0_pins[] = {
1808         /* CS */
1809         RCAR_GP_PIN(0, 13),
1810 };
1811 static const unsigned int lbsc_cs0_mux[] = {
1812         CS0_MARK,
1813 };
1814 static const unsigned int lbsc_cs1_pins[] = {
1815         /* CS */
1816         RCAR_GP_PIN(0, 14),
1817 };
1818 static const unsigned int lbsc_cs1_mux[] = {
1819         CS1_A26_MARK,
1820 };
1821 static const unsigned int lbsc_ex_cs0_pins[] = {
1822         /* CS */
1823         RCAR_GP_PIN(0, 15),
1824 };
1825 static const unsigned int lbsc_ex_cs0_mux[] = {
1826         EX_CS0_MARK,
1827 };
1828 static const unsigned int lbsc_ex_cs1_pins[] = {
1829         /* CS */
1830         RCAR_GP_PIN(0, 16),
1831 };
1832 static const unsigned int lbsc_ex_cs1_mux[] = {
1833         EX_CS1_MARK,
1834 };
1835 static const unsigned int lbsc_ex_cs2_pins[] = {
1836         /* CS */
1837         RCAR_GP_PIN(0, 17),
1838 };
1839 static const unsigned int lbsc_ex_cs2_mux[] = {
1840         EX_CS2_MARK,
1841 };
1842 static const unsigned int lbsc_ex_cs3_pins[] = {
1843         /* CS */
1844         RCAR_GP_PIN(0, 18),
1845 };
1846 static const unsigned int lbsc_ex_cs3_mux[] = {
1847         EX_CS3_MARK,
1848 };
1849 static const unsigned int lbsc_ex_cs4_pins[] = {
1850         /* CS */
1851         RCAR_GP_PIN(0, 19),
1852 };
1853 static const unsigned int lbsc_ex_cs4_mux[] = {
1854         EX_CS4_MARK,
1855 };
1856 static const unsigned int lbsc_ex_cs5_pins[] = {
1857         /* CS */
1858         RCAR_GP_PIN(0, 20),
1859 };
1860 static const unsigned int lbsc_ex_cs5_mux[] = {
1861         EX_CS5_MARK,
1862 };
1863 /* - MMCIF ------------------------------------------------------------------ */
1864 static const unsigned int mmc0_data1_pins[] = {
1865         /* D[0] */
1866         RCAR_GP_PIN(0, 19),
1867 };
1868 static const unsigned int mmc0_data1_mux[] = {
1869         MMC0_D0_MARK,
1870 };
1871 static const unsigned int mmc0_data4_pins[] = {
1872         /* D[0:3] */
1873         RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
1874         RCAR_GP_PIN(0, 2),
1875 };
1876 static const unsigned int mmc0_data4_mux[] = {
1877         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
1878 };
1879 static const unsigned int mmc0_data8_pins[] = {
1880         /* D[0:7] */
1881         RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
1882         RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
1883         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
1884 };
1885 static const unsigned int mmc0_data8_mux[] = {
1886         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
1887         MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
1888 };
1889 static const unsigned int mmc0_ctrl_pins[] = {
1890         /* CMD, CLK */
1891         RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17),
1892 };
1893 static const unsigned int mmc0_ctrl_mux[] = {
1894         MMC0_CMD_MARK, MMC0_CLK_MARK,
1895 };
1896 static const unsigned int mmc1_data1_pins[] = {
1897         /* D[0] */
1898         RCAR_GP_PIN(2, 8),
1899 };
1900 static const unsigned int mmc1_data1_mux[] = {
1901         MMC1_D0_MARK,
1902 };
1903 static const unsigned int mmc1_data4_pins[] = {
1904         /* D[0:3] */
1905         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
1906         RCAR_GP_PIN(2, 11),
1907 };
1908 static const unsigned int mmc1_data4_mux[] = {
1909         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
1910 };
1911 static const unsigned int mmc1_data8_pins[] = {
1912         /* D[0:7] */
1913         RCAR_GP_PIN(2, 8),  RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 10),
1914         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1915         RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
1916 };
1917 static const unsigned int mmc1_data8_mux[] = {
1918         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
1919         MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
1920 };
1921 static const unsigned int mmc1_ctrl_pins[] = {
1922         /* CMD, CLK */
1923         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 1),
1924 };
1925 static const unsigned int mmc1_ctrl_mux[] = {
1926         MMC1_CMD_MARK, MMC1_CLK_MARK,
1927 };
1928 /* - SCIF0 ------------------------------------------------------------------ */
1929 static const unsigned int scif0_data_pins[] = {
1930         /* RXD, TXD */
1931         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
1932 };
1933 static const unsigned int scif0_data_mux[] = {
1934         RX0_MARK, TX0_MARK,
1935 };
1936 static const unsigned int scif0_clk_pins[] = {
1937         /* SCK */
1938         RCAR_GP_PIN(4, 28),
1939 };
1940 static const unsigned int scif0_clk_mux[] = {
1941         SCK0_MARK,
1942 };
1943 static const unsigned int scif0_ctrl_pins[] = {
1944         /* RTS, CTS */
1945         RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22),
1946 };
1947 static const unsigned int scif0_ctrl_mux[] = {
1948         RTS0_TANS_MARK, CTS0_MARK,
1949 };
1950 static const unsigned int scif0_data_b_pins[] = {
1951         /* RXD, TXD */
1952         RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
1953 };
1954 static const unsigned int scif0_data_b_mux[] = {
1955         RX0_B_MARK, TX0_B_MARK,
1956 };
1957 static const unsigned int scif0_clk_b_pins[] = {
1958         /* SCK */
1959         RCAR_GP_PIN(1, 1),
1960 };
1961 static const unsigned int scif0_clk_b_mux[] = {
1962         SCK0_B_MARK,
1963 };
1964 static const unsigned int scif0_ctrl_b_pins[] = {
1965         /* RTS, CTS */
1966         RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11),
1967 };
1968 static const unsigned int scif0_ctrl_b_mux[] = {
1969         RTS0_B_TANS_B_MARK, CTS0_B_MARK,
1970 };
1971 static const unsigned int scif0_data_c_pins[] = {
1972         /* RXD, TXD */
1973         RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
1974 };
1975 static const unsigned int scif0_data_c_mux[] = {
1976         RX0_C_MARK, TX0_C_MARK,
1977 };
1978 static const unsigned int scif0_clk_c_pins[] = {
1979         /* SCK */
1980         RCAR_GP_PIN(4, 17),
1981 };
1982 static const unsigned int scif0_clk_c_mux[] = {
1983         SCK0_C_MARK,
1984 };
1985 static const unsigned int scif0_ctrl_c_pins[] = {
1986         /* RTS, CTS */
1987         RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1988 };
1989 static const unsigned int scif0_ctrl_c_mux[] = {
1990         RTS0_C_TANS_C_MARK, CTS0_C_MARK,
1991 };
1992 static const unsigned int scif0_data_d_pins[] = {
1993         /* RXD, TXD */
1994         RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
1995 };
1996 static const unsigned int scif0_data_d_mux[] = {
1997         RX0_D_MARK, TX0_D_MARK,
1998 };
1999 static const unsigned int scif0_clk_d_pins[] = {
2000         /* SCK */
2001         RCAR_GP_PIN(1, 18),
2002 };
2003 static const unsigned int scif0_clk_d_mux[] = {
2004         SCK0_D_MARK,
2005 };
2006 static const unsigned int scif0_ctrl_d_pins[] = {
2007         /* RTS, CTS */
2008         RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 3),
2009 };
2010 static const unsigned int scif0_ctrl_d_mux[] = {
2011         RTS0_D_TANS_D_MARK, CTS0_D_MARK,
2012 };
2013 /* - SCIF1 ------------------------------------------------------------------ */
2014 static const unsigned int scif1_data_pins[] = {
2015         /* RXD, TXD */
2016         RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
2017 };
2018 static const unsigned int scif1_data_mux[] = {
2019         RX1_MARK, TX1_MARK,
2020 };
2021 static const unsigned int scif1_clk_pins[] = {
2022         /* SCK */
2023         RCAR_GP_PIN(4, 17),
2024 };
2025 static const unsigned int scif1_clk_mux[] = {
2026         SCK1_MARK,
2027 };
2028 static const unsigned int scif1_ctrl_pins[] = {
2029         /* RTS, CTS */
2030         RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
2031 };
2032 static const unsigned int scif1_ctrl_mux[] = {
2033         RTS1_TANS_MARK, CTS1_MARK,
2034 };
2035 static const unsigned int scif1_data_b_pins[] = {
2036         /* RXD, TXD */
2037         RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 18),
2038 };
2039 static const unsigned int scif1_data_b_mux[] = {
2040         RX1_B_MARK, TX1_B_MARK,
2041 };
2042 static const unsigned int scif1_clk_b_pins[] = {
2043         /* SCK */
2044         RCAR_GP_PIN(3, 17),
2045 };
2046 static const unsigned int scif1_clk_b_mux[] = {
2047         SCK1_B_MARK,
2048 };
2049 static const unsigned int scif1_ctrl_b_pins[] = {
2050         /* RTS, CTS */
2051         RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
2052 };
2053 static const unsigned int scif1_ctrl_b_mux[] = {
2054         RTS1_B_TANS_B_MARK, CTS1_B_MARK,
2055 };
2056 static const unsigned int scif1_data_c_pins[] = {
2057         /* RXD, TXD */
2058         RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
2059 };
2060 static const unsigned int scif1_data_c_mux[] = {
2061         RX1_C_MARK, TX1_C_MARK,
2062 };
2063 static const unsigned int scif1_clk_c_pins[] = {
2064         /* SCK */
2065         RCAR_GP_PIN(2, 22),
2066 };
2067 static const unsigned int scif1_clk_c_mux[] = {
2068         SCK1_C_MARK,
2069 };
2070 static const unsigned int scif1_ctrl_c_pins[] = {
2071         /* RTS, CTS */
2072         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2073 };
2074 static const unsigned int scif1_ctrl_c_mux[] = {
2075         RTS1_C_TANS_C_MARK, CTS1_C_MARK,
2076 };
2077 /* - SCIF2 ------------------------------------------------------------------ */
2078 static const unsigned int scif2_data_pins[] = {
2079         /* RXD, TXD */
2080         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 9),
2081 };
2082 static const unsigned int scif2_data_mux[] = {
2083         RX2_MARK, TX2_MARK,
2084 };
2085 static const unsigned int scif2_clk_pins[] = {
2086         /* SCK */
2087         RCAR_GP_PIN(3, 11),
2088 };
2089 static const unsigned int scif2_clk_mux[] = {
2090         SCK2_MARK,
2091 };
2092 static const unsigned int scif2_data_b_pins[] = {
2093         /* RXD, TXD */
2094         RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 23),
2095 };
2096 static const unsigned int scif2_data_b_mux[] = {
2097         RX2_B_MARK, TX2_B_MARK,
2098 };
2099 static const unsigned int scif2_clk_b_pins[] = {
2100         /* SCK */
2101         RCAR_GP_PIN(3, 22),
2102 };
2103 static const unsigned int scif2_clk_b_mux[] = {
2104         SCK2_B_MARK,
2105 };
2106 static const unsigned int scif2_data_c_pins[] = {
2107         /* RXD, TXD */
2108         RCAR_GP_PIN(1, 1), RCAR_GP_PIN(0, 31),
2109 };
2110 static const unsigned int scif2_data_c_mux[] = {
2111         RX2_C_MARK, TX2_C_MARK,
2112 };
2113 static const unsigned int scif2_clk_c_pins[] = {
2114         /* SCK */
2115         RCAR_GP_PIN(1, 0),
2116 };
2117 static const unsigned int scif2_clk_c_mux[] = {
2118         SCK2_C_MARK,
2119 };
2120 static const unsigned int scif2_data_d_pins[] = {
2121         /* RXD, TXD */
2122         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30),
2123 };
2124 static const unsigned int scif2_data_d_mux[] = {
2125         RX2_D_MARK, TX2_D_MARK,
2126 };
2127 static const unsigned int scif2_clk_d_pins[] = {
2128         /* SCK */
2129         RCAR_GP_PIN(1, 31),
2130 };
2131 static const unsigned int scif2_clk_d_mux[] = {
2132         SCK2_D_MARK,
2133 };
2134 static const unsigned int scif2_data_e_pins[] = {
2135         /* RXD, TXD */
2136         RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
2137 };
2138 static const unsigned int scif2_data_e_mux[] = {
2139         RX2_E_MARK, TX2_E_MARK,
2140 };
2141 /* - SCIF3 ------------------------------------------------------------------ */
2142 static const unsigned int scif3_data_pins[] = {
2143         /* RXD, TXD */
2144         RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8),
2145 };
2146 static const unsigned int scif3_data_mux[] = {
2147         RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK,
2148 };
2149 static const unsigned int scif3_clk_pins[] = {
2150         /* SCK */
2151         RCAR_GP_PIN(4, 7),
2152 };
2153 static const unsigned int scif3_clk_mux[] = {
2154         SCK3_MARK,
2155 };
2156
2157 static const unsigned int scif3_data_b_pins[] = {
2158         /* RXD, TXD */
2159         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30),
2160 };
2161 static const unsigned int scif3_data_b_mux[] = {
2162         RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK,
2163 };
2164 static const unsigned int scif3_data_c_pins[] = {
2165         /* RXD, TXD */
2166         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 12),
2167 };
2168 static const unsigned int scif3_data_c_mux[] = {
2169         RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK,
2170 };
2171 static const unsigned int scif3_data_d_pins[] = {
2172         /* RXD, TXD */
2173         RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 29),
2174 };
2175 static const unsigned int scif3_data_d_mux[] = {
2176         RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK,
2177 };
2178 static const unsigned int scif3_data_e_pins[] = {
2179         /* RXD, TXD */
2180         RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2181 };
2182 static const unsigned int scif3_data_e_mux[] = {
2183         RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK,
2184 };
2185 static const unsigned int scif3_clk_e_pins[] = {
2186         /* SCK */
2187         RCAR_GP_PIN(1, 10),
2188 };
2189 static const unsigned int scif3_clk_e_mux[] = {
2190         SCK3_E_MARK,
2191 };
2192 /* - SCIF4 ------------------------------------------------------------------ */
2193 static const unsigned int scif4_data_pins[] = {
2194         /* RXD, TXD */
2195         RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 26),
2196 };
2197 static const unsigned int scif4_data_mux[] = {
2198         RX4_MARK, TX4_MARK,
2199 };
2200 static const unsigned int scif4_clk_pins[] = {
2201         /* SCK */
2202         RCAR_GP_PIN(3, 25),
2203 };
2204 static const unsigned int scif4_clk_mux[] = {
2205         SCK4_MARK,
2206 };
2207 static const unsigned int scif4_data_b_pins[] = {
2208         /* RXD, TXD */
2209         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
2210 };
2211 static const unsigned int scif4_data_b_mux[] = {
2212         RX4_B_MARK, TX4_B_MARK,
2213 };
2214 static const unsigned int scif4_clk_b_pins[] = {
2215         /* SCK */
2216         RCAR_GP_PIN(3, 16),
2217 };
2218 static const unsigned int scif4_clk_b_mux[] = {
2219         SCK4_B_MARK,
2220 };
2221 static const unsigned int scif4_data_c_pins[] = {
2222         /* RXD, TXD */
2223         RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
2224 };
2225 static const unsigned int scif4_data_c_mux[] = {
2226         RX4_C_MARK, TX4_C_MARK,
2227 };
2228 static const unsigned int scif4_data_d_pins[] = {
2229         /* RXD, TXD */
2230         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2231 };
2232 static const unsigned int scif4_data_d_mux[] = {
2233         RX4_D_MARK, TX4_D_MARK,
2234 };
2235 /* - SCIF5 ------------------------------------------------------------------ */
2236 static const unsigned int scif5_data_pins[] = {
2237         /* RXD, TXD */
2238         RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2239 };
2240 static const unsigned int scif5_data_mux[] = {
2241         RX5_MARK, TX5_MARK,
2242 };
2243 static const unsigned int scif5_clk_pins[] = {
2244         /* SCK */
2245         RCAR_GP_PIN(1, 11),
2246 };
2247 static const unsigned int scif5_clk_mux[] = {
2248         SCK5_MARK,
2249 };
2250 static const unsigned int scif5_data_b_pins[] = {
2251         /* RXD, TXD */
2252         RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11),
2253 };
2254 static const unsigned int scif5_data_b_mux[] = {
2255         RX5_B_MARK, TX5_B_MARK,
2256 };
2257 static const unsigned int scif5_clk_b_pins[] = {
2258         /* SCK */
2259         RCAR_GP_PIN(0, 19),
2260 };
2261 static const unsigned int scif5_clk_b_mux[] = {
2262         SCK5_B_MARK,
2263 };
2264 static const unsigned int scif5_data_c_pins[] = {
2265         /* RXD, TXD */
2266         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23),
2267 };
2268 static const unsigned int scif5_data_c_mux[] = {
2269         RX5_C_MARK, TX5_C_MARK,
2270 };
2271 static const unsigned int scif5_clk_c_pins[] = {
2272         /* SCK */
2273         RCAR_GP_PIN(0, 28),
2274 };
2275 static const unsigned int scif5_clk_c_mux[] = {
2276         SCK5_C_MARK,
2277 };
2278 static const unsigned int scif5_data_d_pins[] = {
2279         /* RXD, TXD */
2280         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6),
2281 };
2282 static const unsigned int scif5_data_d_mux[] = {
2283         RX5_D_MARK, TX5_D_MARK,
2284 };
2285 static const unsigned int scif5_clk_d_pins[] = {
2286         /* SCK */
2287         RCAR_GP_PIN(0, 7),
2288 };
2289 static const unsigned int scif5_clk_d_mux[] = {
2290         SCK5_D_MARK,
2291 };
2292 /* - SDHI0 ------------------------------------------------------------------ */
2293 static const unsigned int sdhi0_data1_pins[] = {
2294         /* D0 */
2295         RCAR_GP_PIN(3, 21),
2296 };
2297 static const unsigned int sdhi0_data1_mux[] = {
2298         SD0_DAT0_MARK,
2299 };
2300 static const unsigned int sdhi0_data4_pins[] = {
2301         /* D[0:3] */
2302         RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2303         RCAR_GP_PIN(3, 24),
2304 };
2305 static const unsigned int sdhi0_data4_mux[] = {
2306         SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
2307 };
2308 static const unsigned int sdhi0_ctrl_pins[] = {
2309         /* CMD, CLK */
2310         RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 17),
2311 };
2312 static const unsigned int sdhi0_ctrl_mux[] = {
2313         SD0_CMD_MARK, SD0_CLK_MARK,
2314 };
2315 static const unsigned int sdhi0_cd_pins[] = {
2316         /* CD */
2317         RCAR_GP_PIN(3, 19),
2318 };
2319 static const unsigned int sdhi0_cd_mux[] = {
2320         SD0_CD_MARK,
2321 };
2322 static const unsigned int sdhi0_wp_pins[] = {
2323         /* WP */
2324         RCAR_GP_PIN(3, 20),
2325 };
2326 static const unsigned int sdhi0_wp_mux[] = {
2327         SD0_WP_MARK,
2328 };
2329 /* - SDHI1 ------------------------------------------------------------------ */
2330 static const unsigned int sdhi1_data1_pins[] = {
2331         /* D0 */
2332         RCAR_GP_PIN(0, 19),
2333 };
2334 static const unsigned int sdhi1_data1_mux[] = {
2335         SD1_DAT0_MARK,
2336 };
2337 static const unsigned int sdhi1_data4_pins[] = {
2338         /* D[0:3] */
2339         RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
2340         RCAR_GP_PIN(0, 2),
2341 };
2342 static const unsigned int sdhi1_data4_mux[] = {
2343         SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
2344 };
2345 static const unsigned int sdhi1_ctrl_pins[] = {
2346         /* CMD, CLK */
2347         RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17),
2348 };
2349 static const unsigned int sdhi1_ctrl_mux[] = {
2350         SD1_CMD_MARK, SD1_CLK_MARK,
2351 };
2352 static const unsigned int sdhi1_cd_pins[] = {
2353         /* CD */
2354         RCAR_GP_PIN(0, 10),
2355 };
2356 static const unsigned int sdhi1_cd_mux[] = {
2357         SD1_CD_MARK,
2358 };
2359 static const unsigned int sdhi1_wp_pins[] = {
2360         /* WP */
2361         RCAR_GP_PIN(0, 11),
2362 };
2363 static const unsigned int sdhi1_wp_mux[] = {
2364         SD1_WP_MARK,
2365 };
2366 /* - SDHI2 ------------------------------------------------------------------ */
2367 static const unsigned int sdhi2_data1_pins[] = {
2368         /* D0 */
2369         RCAR_GP_PIN(3, 1),
2370 };
2371 static const unsigned int sdhi2_data1_mux[] = {
2372         SD2_DAT0_MARK,
2373 };
2374 static const unsigned int sdhi2_data4_pins[] = {
2375         /* D[0:3] */
2376         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2377         RCAR_GP_PIN(3, 4),
2378 };
2379 static const unsigned int sdhi2_data4_mux[] = {
2380         SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
2381 };
2382 static const unsigned int sdhi2_ctrl_pins[] = {
2383         /* CMD, CLK */
2384         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
2385 };
2386 static const unsigned int sdhi2_ctrl_mux[] = {
2387         SD2_CMD_MARK, SD2_CLK_MARK,
2388 };
2389 static const unsigned int sdhi2_cd_pins[] = {
2390         /* CD */
2391         RCAR_GP_PIN(3, 7),
2392 };
2393 static const unsigned int sdhi2_cd_mux[] = {
2394         SD2_CD_MARK,
2395 };
2396 static const unsigned int sdhi2_wp_pins[] = {
2397         /* WP */
2398         RCAR_GP_PIN(3, 8),
2399 };
2400 static const unsigned int sdhi2_wp_mux[] = {
2401         SD2_WP_MARK,
2402 };
2403 /* - SDHI3 ------------------------------------------------------------------ */
2404 static const unsigned int sdhi3_data1_pins[] = {
2405         /* D0 */
2406         RCAR_GP_PIN(1, 18),
2407 };
2408 static const unsigned int sdhi3_data1_mux[] = {
2409         SD3_DAT0_MARK,
2410 };
2411 static const unsigned int sdhi3_data4_pins[] = {
2412         /* D[0:3] */
2413         RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20),
2414         RCAR_GP_PIN(1, 21),
2415 };
2416 static const unsigned int sdhi3_data4_mux[] = {
2417         SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
2418 };
2419 static const unsigned int sdhi3_ctrl_pins[] = {
2420         /* CMD, CLK */
2421         RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2422 };
2423 static const unsigned int sdhi3_ctrl_mux[] = {
2424         SD3_CMD_MARK, SD3_CLK_MARK,
2425 };
2426 static const unsigned int sdhi3_cd_pins[] = {
2427         /* CD */
2428         RCAR_GP_PIN(1, 30),
2429 };
2430 static const unsigned int sdhi3_cd_mux[] = {
2431         SD3_CD_MARK,
2432 };
2433 static const unsigned int sdhi3_wp_pins[] = {
2434         /* WP */
2435         RCAR_GP_PIN(2, 0),
2436 };
2437 static const unsigned int sdhi3_wp_mux[] = {
2438         SD3_WP_MARK,
2439 };
2440 /* - USB0 ------------------------------------------------------------------- */
2441 static const unsigned int usb0_pins[] = {
2442         /* PENC */
2443         RCAR_GP_PIN(4, 26),
2444 };
2445 static const unsigned int usb0_mux[] = {
2446         USB_PENC0_MARK,
2447 };
2448 static const unsigned int usb0_ovc_pins[] = {
2449         /* USB_OVC */
2450         RCAR_GP_PIN(4, 22),
2451 };
2452 static const unsigned int usb0_ovc_mux[] = {
2453         USB_OVC0_MARK,
2454 };
2455 /* - USB1 ------------------------------------------------------------------- */
2456 static const unsigned int usb1_pins[] = {
2457         /* PENC */
2458         RCAR_GP_PIN(4, 27),
2459 };
2460 static const unsigned int usb1_mux[] = {
2461         USB_PENC1_MARK,
2462 };
2463 static const unsigned int usb1_ovc_pins[] = {
2464         /* USB_OVC */
2465         RCAR_GP_PIN(4, 24),
2466 };
2467 static const unsigned int usb1_ovc_mux[] = {
2468         USB_OVC1_MARK,
2469 };
2470 /* - USB2 ------------------------------------------------------------------- */
2471 static const unsigned int usb2_pins[] = {
2472         /* PENC */
2473         RCAR_GP_PIN(4, 28),
2474 };
2475 static const unsigned int usb2_mux[] = {
2476         USB_PENC2_MARK,
2477 };
2478 static const unsigned int usb2_ovc_pins[] = {
2479         /* USB_OVC */
2480         RCAR_GP_PIN(3, 29),
2481 };
2482 static const unsigned int usb2_ovc_mux[] = {
2483         USB_OVC2_MARK,
2484 };
2485 /* - VIN0 ------------------------------------------------------------------- */
2486 static const unsigned int vin0_data8_pins[] = {
2487         /* D[0:7] */
2488         RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 8),
2489         RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
2490         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
2491 };
2492 static const unsigned int vin0_data8_mux[] = {
2493         VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, VI0_DATA2_VI0_B2_MARK,
2494         VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
2495         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
2496 };
2497 static const unsigned int vin0_clk_pins[] = {
2498         /* CLK */
2499         RCAR_GP_PIN(2, 1),
2500 };
2501 static const unsigned int vin0_clk_mux[] = {
2502         VI0_CLK_MARK,
2503 };
2504 static const unsigned int vin0_sync_pins[] = {
2505         /* HSYNC, VSYNC */
2506         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2507 };
2508 static const unsigned int vin0_sync_mux[] = {
2509         VI0_HSYNC_MARK, VI0_VSYNC_MARK,
2510 };
2511 /* - VIN1 ------------------------------------------------------------------- */
2512 static const unsigned int vin1_data8_pins[] = {
2513         /* D[0:7] */
2514         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2515         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
2516         RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
2517 };
2518 static const unsigned int vin1_data8_mux[] = {
2519         VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, VI1_DATA2_VI1_B2_MARK,
2520         VI1_DATA3_VI1_B3_MARK, VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
2521         VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
2522 };
2523 static const unsigned int vin1_clk_pins[] = {
2524         /* CLK */
2525         RCAR_GP_PIN(2, 30),
2526 };
2527 static const unsigned int vin1_clk_mux[] = {
2528         VI1_CLK_MARK,
2529 };
2530 static const unsigned int vin1_sync_pins[] = {
2531         /* HSYNC, VSYNC */
2532         RCAR_GP_PIN(2, 31), RCAR_GP_PIN(3, 0),
2533 };
2534 static const unsigned int vin1_sync_mux[] = {
2535         VI1_HSYNC_MARK, VI1_VSYNC_MARK,
2536 };
2537 /* - VIN2 ------------------------------------------------------------------- */
2538 static const unsigned int vin2_data8_pins[] = {
2539         /* D[0:7] */
2540         RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 10),
2541         RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
2542         RCAR_GP_PIN(1, 31), RCAR_GP_PIN(2, 0),
2543 };
2544 static const unsigned int vin2_data8_mux[] = {
2545         VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, VI2_DATA2_VI2_B2_MARK,
2546         VI2_DATA3_VI2_B3_MARK, VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
2547         VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
2548 };
2549 static const unsigned int vin2_clk_pins[] = {
2550         /* CLK */
2551         RCAR_GP_PIN(1, 30),
2552 };
2553 static const unsigned int vin2_clk_mux[] = {
2554         VI2_CLK_MARK,
2555 };
2556 static const unsigned int vin2_sync_pins[] = {
2557         /* HSYNC, VSYNC */
2558         RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29),
2559 };
2560 static const unsigned int vin2_sync_mux[] = {
2561         VI2_HSYNC_MARK, VI2_VSYNC_MARK,
2562 };
2563 /* - VIN3 ------------------------------------------------------------------- */
2564 static const unsigned int vin3_data8_pins[] = {
2565         /* D[0:7] */
2566         RCAR_GP_PIN(3, 9),  RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2567         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
2568         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
2569 };
2570 static const unsigned int vin3_data8_mux[] = {
2571         VI3_DATA0_MARK, VI3_DATA1_MARK, VI3_DATA2_MARK,
2572         VI3_DATA3_MARK, VI3_DATA4_MARK, VI3_DATA5_MARK,
2573         VI3_DATA6_MARK, VI3_DATA7_MARK,
2574 };
2575 static const unsigned int vin3_clk_pins[] = {
2576         /* CLK */
2577         RCAR_GP_PIN(2, 31),
2578 };
2579 static const unsigned int vin3_clk_mux[] = {
2580         VI3_CLK_MARK,
2581 };
2582 static const unsigned int vin3_sync_pins[] = {
2583         /* HSYNC, VSYNC */
2584         RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29),
2585 };
2586 static const unsigned int vin3_sync_mux[] = {
2587         VI3_HSYNC_MARK, VI3_VSYNC_MARK,
2588 };
2589
2590 static const struct sh_pfc_pin_group pinmux_groups[] = {
2591         SH_PFC_PIN_GROUP(du0_rgb666),
2592         SH_PFC_PIN_GROUP(du0_rgb888),
2593         SH_PFC_PIN_GROUP(du0_clk_in),
2594         SH_PFC_PIN_GROUP(du0_clk_out_0),
2595         SH_PFC_PIN_GROUP(du0_clk_out_1),
2596         SH_PFC_PIN_GROUP(du0_sync_0),
2597         SH_PFC_PIN_GROUP(du0_sync_1),
2598         SH_PFC_PIN_GROUP(du0_oddf),
2599         SH_PFC_PIN_GROUP(du0_cde),
2600         SH_PFC_PIN_GROUP(du1_rgb666),
2601         SH_PFC_PIN_GROUP(du1_rgb888),
2602         SH_PFC_PIN_GROUP(du1_clk_in),
2603         SH_PFC_PIN_GROUP(du1_clk_out),
2604         SH_PFC_PIN_GROUP(du1_sync_0),
2605         SH_PFC_PIN_GROUP(du1_sync_1),
2606         SH_PFC_PIN_GROUP(du1_oddf),
2607         SH_PFC_PIN_GROUP(du1_cde),
2608         SH_PFC_PIN_GROUP(ether_rmii),
2609         SH_PFC_PIN_GROUP(ether_link),
2610         SH_PFC_PIN_GROUP(ether_magic),
2611         SH_PFC_PIN_GROUP(hspi0),
2612         SH_PFC_PIN_GROUP(hspi1),
2613         SH_PFC_PIN_GROUP(hspi1_b),
2614         SH_PFC_PIN_GROUP(hspi1_c),
2615         SH_PFC_PIN_GROUP(hspi1_d),
2616         SH_PFC_PIN_GROUP(hspi2),
2617         SH_PFC_PIN_GROUP(hspi2_b),
2618         SH_PFC_PIN_GROUP(i2c1),
2619         SH_PFC_PIN_GROUP(i2c1_b),
2620         SH_PFC_PIN_GROUP(i2c1_c),
2621         SH_PFC_PIN_GROUP(i2c1_d),
2622         SH_PFC_PIN_GROUP(i2c2),
2623         SH_PFC_PIN_GROUP(i2c2_b),
2624         SH_PFC_PIN_GROUP(i2c2_c),
2625         SH_PFC_PIN_GROUP(i2c2_d),
2626         SH_PFC_PIN_GROUP(i2c3),
2627         SH_PFC_PIN_GROUP(i2c3_b),
2628         SH_PFC_PIN_GROUP(intc_irq0),
2629         SH_PFC_PIN_GROUP(intc_irq0_b),
2630         SH_PFC_PIN_GROUP(intc_irq1),
2631         SH_PFC_PIN_GROUP(intc_irq1_b),
2632         SH_PFC_PIN_GROUP(intc_irq2),
2633         SH_PFC_PIN_GROUP(intc_irq2_b),
2634         SH_PFC_PIN_GROUP(intc_irq3),
2635         SH_PFC_PIN_GROUP(intc_irq3_b),
2636         SH_PFC_PIN_GROUP(lbsc_cs0),
2637         SH_PFC_PIN_GROUP(lbsc_cs1),
2638         SH_PFC_PIN_GROUP(lbsc_ex_cs0),
2639         SH_PFC_PIN_GROUP(lbsc_ex_cs1),
2640         SH_PFC_PIN_GROUP(lbsc_ex_cs2),
2641         SH_PFC_PIN_GROUP(lbsc_ex_cs3),
2642         SH_PFC_PIN_GROUP(lbsc_ex_cs4),
2643         SH_PFC_PIN_GROUP(lbsc_ex_cs5),
2644         SH_PFC_PIN_GROUP(mmc0_data1),
2645         SH_PFC_PIN_GROUP(mmc0_data4),
2646         SH_PFC_PIN_GROUP(mmc0_data8),
2647         SH_PFC_PIN_GROUP(mmc0_ctrl),
2648         SH_PFC_PIN_GROUP(mmc1_data1),
2649         SH_PFC_PIN_GROUP(mmc1_data4),
2650         SH_PFC_PIN_GROUP(mmc1_data8),
2651         SH_PFC_PIN_GROUP(mmc1_ctrl),
2652         SH_PFC_PIN_GROUP(scif0_data),
2653         SH_PFC_PIN_GROUP(scif0_clk),
2654         SH_PFC_PIN_GROUP(scif0_ctrl),
2655         SH_PFC_PIN_GROUP(scif0_data_b),
2656         SH_PFC_PIN_GROUP(scif0_clk_b),
2657         SH_PFC_PIN_GROUP(scif0_ctrl_b),
2658         SH_PFC_PIN_GROUP(scif0_data_c),
2659         SH_PFC_PIN_GROUP(scif0_clk_c),
2660         SH_PFC_PIN_GROUP(scif0_ctrl_c),
2661         SH_PFC_PIN_GROUP(scif0_data_d),
2662         SH_PFC_PIN_GROUP(scif0_clk_d),
2663         SH_PFC_PIN_GROUP(scif0_ctrl_d),
2664         SH_PFC_PIN_GROUP(scif1_data),
2665         SH_PFC_PIN_GROUP(scif1_clk),
2666         SH_PFC_PIN_GROUP(scif1_ctrl),
2667         SH_PFC_PIN_GROUP(scif1_data_b),
2668         SH_PFC_PIN_GROUP(scif1_clk_b),
2669         SH_PFC_PIN_GROUP(scif1_ctrl_b),
2670         SH_PFC_PIN_GROUP(scif1_data_c),
2671         SH_PFC_PIN_GROUP(scif1_clk_c),
2672         SH_PFC_PIN_GROUP(scif1_ctrl_c),
2673         SH_PFC_PIN_GROUP(scif2_data),
2674         SH_PFC_PIN_GROUP(scif2_clk),
2675         SH_PFC_PIN_GROUP(scif2_data_b),
2676         SH_PFC_PIN_GROUP(scif2_clk_b),
2677         SH_PFC_PIN_GROUP(scif2_data_c),
2678         SH_PFC_PIN_GROUP(scif2_clk_c),
2679         SH_PFC_PIN_GROUP(scif2_data_d),
2680         SH_PFC_PIN_GROUP(scif2_clk_d),
2681         SH_PFC_PIN_GROUP(scif2_data_e),
2682         SH_PFC_PIN_GROUP(scif3_data),
2683         SH_PFC_PIN_GROUP(scif3_clk),
2684         SH_PFC_PIN_GROUP(scif3_data_b),
2685         SH_PFC_PIN_GROUP(scif3_data_c),
2686         SH_PFC_PIN_GROUP(scif3_data_d),
2687         SH_PFC_PIN_GROUP(scif3_data_e),
2688         SH_PFC_PIN_GROUP(scif3_clk_e),
2689         SH_PFC_PIN_GROUP(scif4_data),
2690         SH_PFC_PIN_GROUP(scif4_clk),
2691         SH_PFC_PIN_GROUP(scif4_data_b),
2692         SH_PFC_PIN_GROUP(scif4_clk_b),
2693         SH_PFC_PIN_GROUP(scif4_data_c),
2694         SH_PFC_PIN_GROUP(scif4_data_d),
2695         SH_PFC_PIN_GROUP(scif5_data),
2696         SH_PFC_PIN_GROUP(scif5_clk),
2697         SH_PFC_PIN_GROUP(scif5_data_b),
2698         SH_PFC_PIN_GROUP(scif5_clk_b),
2699         SH_PFC_PIN_GROUP(scif5_data_c),
2700         SH_PFC_PIN_GROUP(scif5_clk_c),
2701         SH_PFC_PIN_GROUP(scif5_data_d),
2702         SH_PFC_PIN_GROUP(scif5_clk_d),
2703         SH_PFC_PIN_GROUP(sdhi0_data1),
2704         SH_PFC_PIN_GROUP(sdhi0_data4),
2705         SH_PFC_PIN_GROUP(sdhi0_ctrl),
2706         SH_PFC_PIN_GROUP(sdhi0_cd),
2707         SH_PFC_PIN_GROUP(sdhi0_wp),
2708         SH_PFC_PIN_GROUP(sdhi1_data1),
2709         SH_PFC_PIN_GROUP(sdhi1_data4),
2710         SH_PFC_PIN_GROUP(sdhi1_ctrl),
2711         SH_PFC_PIN_GROUP(sdhi1_cd),
2712         SH_PFC_PIN_GROUP(sdhi1_wp),
2713         SH_PFC_PIN_GROUP(sdhi2_data1),
2714         SH_PFC_PIN_GROUP(sdhi2_data4),
2715         SH_PFC_PIN_GROUP(sdhi2_ctrl),
2716         SH_PFC_PIN_GROUP(sdhi2_cd),
2717         SH_PFC_PIN_GROUP(sdhi2_wp),
2718         SH_PFC_PIN_GROUP(sdhi3_data1),
2719         SH_PFC_PIN_GROUP(sdhi3_data4),
2720         SH_PFC_PIN_GROUP(sdhi3_ctrl),
2721         SH_PFC_PIN_GROUP(sdhi3_cd),
2722         SH_PFC_PIN_GROUP(sdhi3_wp),
2723         SH_PFC_PIN_GROUP(usb0),
2724         SH_PFC_PIN_GROUP(usb0_ovc),
2725         SH_PFC_PIN_GROUP(usb1),
2726         SH_PFC_PIN_GROUP(usb1_ovc),
2727         SH_PFC_PIN_GROUP(usb2),
2728         SH_PFC_PIN_GROUP(usb2_ovc),
2729         SH_PFC_PIN_GROUP(vin0_data8),
2730         SH_PFC_PIN_GROUP(vin0_clk),
2731         SH_PFC_PIN_GROUP(vin0_sync),
2732         SH_PFC_PIN_GROUP(vin1_data8),
2733         SH_PFC_PIN_GROUP(vin1_clk),
2734         SH_PFC_PIN_GROUP(vin1_sync),
2735         SH_PFC_PIN_GROUP(vin2_data8),
2736         SH_PFC_PIN_GROUP(vin2_clk),
2737         SH_PFC_PIN_GROUP(vin2_sync),
2738         SH_PFC_PIN_GROUP(vin3_data8),
2739         SH_PFC_PIN_GROUP(vin3_clk),
2740         SH_PFC_PIN_GROUP(vin3_sync),
2741 };
2742
2743 static const char * const du0_groups[] = {
2744         "du0_rgb666",
2745         "du0_rgb888",
2746         "du0_clk_in",
2747         "du0_clk_out_0",
2748         "du0_clk_out_1",
2749         "du0_sync_0",
2750         "du0_sync_1",
2751         "du0_oddf",
2752         "du0_cde",
2753 };
2754
2755 static const char * const du1_groups[] = {
2756         "du1_rgb666",
2757         "du1_rgb888",
2758         "du1_clk_in",
2759         "du1_clk_out",
2760         "du1_sync_0",
2761         "du1_sync_1",
2762         "du1_oddf",
2763         "du1_cde",
2764 };
2765
2766 static const char * const ether_groups[] = {
2767         "ether_rmii",
2768         "ether_link",
2769         "ether_magic",
2770 };
2771
2772 static const char * const hspi0_groups[] = {
2773         "hspi0",
2774 };
2775
2776 static const char * const hspi1_groups[] = {
2777         "hspi1",
2778         "hspi1_b",
2779         "hspi1_c",
2780         "hspi1_d",
2781 };
2782
2783 static const char * const hspi2_groups[] = {
2784         "hspi2",
2785         "hspi2_b",
2786 };
2787
2788 static const char * const i2c1_groups[] = {
2789         "i2c1",
2790         "i2c1_b",
2791         "i2c1_c",
2792         "i2c1_d",
2793 };
2794
2795 static const char * const i2c2_groups[] = {
2796         "i2c2",
2797         "i2c2_b",
2798         "i2c2_c",
2799         "i2c2_d",
2800 };
2801
2802 static const char * const i2c3_groups[] = {
2803         "i2c3",
2804         "i2c3_b",
2805 };
2806
2807 static const char * const intc_groups[] = {
2808         "intc_irq0",
2809         "intc_irq0_b",
2810         "intc_irq1",
2811         "intc_irq1_b",
2812         "intc_irq2",
2813         "intc_irq2_b",
2814         "intc_irq3",
2815         "intc_irq3_b",
2816 };
2817
2818 static const char * const lbsc_groups[] = {
2819         "lbsc_cs0",
2820         "lbsc_cs1",
2821         "lbsc_ex_cs0",
2822         "lbsc_ex_cs1",
2823         "lbsc_ex_cs2",
2824         "lbsc_ex_cs3",
2825         "lbsc_ex_cs4",
2826         "lbsc_ex_cs5",
2827 };
2828
2829 static const char * const mmc0_groups[] = {
2830         "mmc0_data1",
2831         "mmc0_data4",
2832         "mmc0_data8",
2833         "mmc0_ctrl",
2834 };
2835
2836 static const char * const mmc1_groups[] = {
2837         "mmc1_data1",
2838         "mmc1_data4",
2839         "mmc1_data8",
2840         "mmc1_ctrl",
2841 };
2842
2843 static const char * const scif0_groups[] = {
2844         "scif0_data",
2845         "scif0_clk",
2846         "scif0_ctrl",
2847         "scif0_data_b",
2848         "scif0_clk_b",
2849         "scif0_ctrl_b",
2850         "scif0_data_c",
2851         "scif0_clk_c",
2852         "scif0_ctrl_c",
2853         "scif0_data_d",
2854         "scif0_clk_d",
2855         "scif0_ctrl_d",
2856 };
2857
2858 static const char * const scif1_groups[] = {
2859         "scif1_data",
2860         "scif1_clk",
2861         "scif1_ctrl",
2862         "scif1_data_b",
2863         "scif1_clk_b",
2864         "scif1_ctrl_b",
2865         "scif1_data_c",
2866         "scif1_clk_c",
2867         "scif1_ctrl_c",
2868 };
2869
2870 static const char * const scif2_groups[] = {
2871         "scif2_data",
2872         "scif2_clk",
2873         "scif2_data_b",
2874         "scif2_clk_b",
2875         "scif2_data_c",
2876         "scif2_clk_c",
2877         "scif2_data_d",
2878         "scif2_clk_d",
2879         "scif2_data_e",
2880 };
2881
2882 static const char * const scif3_groups[] = {
2883         "scif3_data",
2884         "scif3_clk",
2885         "scif3_data_b",
2886         "scif3_data_c",
2887         "scif3_data_d",
2888         "scif3_data_e",
2889         "scif3_clk_e",
2890 };
2891
2892 static const char * const scif4_groups[] = {
2893         "scif4_data",
2894         "scif4_clk",
2895         "scif4_data_b",
2896         "scif4_clk_b",
2897         "scif4_data_c",
2898         "scif4_data_d",
2899 };
2900
2901 static const char * const scif5_groups[] = {
2902         "scif5_data",
2903         "scif5_clk",
2904         "scif5_data_b",
2905         "scif5_clk_b",
2906         "scif5_data_c",
2907         "scif5_clk_c",
2908         "scif5_data_d",
2909         "scif5_clk_d",
2910 };
2911
2912 static const char * const sdhi0_groups[] = {
2913         "sdhi0_data1",
2914         "sdhi0_data4",
2915         "sdhi0_ctrl",
2916         "sdhi0_cd",
2917         "sdhi0_wp",
2918 };
2919
2920 static const char * const sdhi1_groups[] = {
2921         "sdhi1_data1",
2922         "sdhi1_data4",
2923         "sdhi1_ctrl",
2924         "sdhi1_cd",
2925         "sdhi1_wp",
2926 };
2927
2928 static const char * const sdhi2_groups[] = {
2929         "sdhi2_data1",
2930         "sdhi2_data4",
2931         "sdhi2_ctrl",
2932         "sdhi2_cd",
2933         "sdhi2_wp",
2934 };
2935
2936 static const char * const sdhi3_groups[] = {
2937         "sdhi3_data1",
2938         "sdhi3_data4",
2939         "sdhi3_ctrl",
2940         "sdhi3_cd",
2941         "sdhi3_wp",
2942 };
2943
2944 static const char * const usb0_groups[] = {
2945         "usb0",
2946         "usb0_ovc",
2947 };
2948
2949 static const char * const usb1_groups[] = {
2950         "usb1",
2951         "usb1_ovc",
2952 };
2953
2954 static const char * const usb2_groups[] = {
2955         "usb2",
2956         "usb2_ovc",
2957 };
2958
2959 static const char * const vin0_groups[] = {
2960         "vin0_data8",
2961         "vin0_clk",
2962         "vin0_sync",
2963 };
2964
2965 static const char * const vin1_groups[] = {
2966         "vin1_data8",
2967         "vin1_clk",
2968         "vin1_sync",
2969 };
2970
2971 static const char * const vin2_groups[] = {
2972         "vin2_data8",
2973         "vin2_clk",
2974         "vin2_sync",
2975 };
2976
2977 static const char * const vin3_groups[] = {
2978         "vin3_data8",
2979         "vin3_clk",
2980         "vin3_sync",
2981 };
2982
2983 static const struct sh_pfc_function pinmux_functions[] = {
2984         SH_PFC_FUNCTION(du0),
2985         SH_PFC_FUNCTION(du1),
2986         SH_PFC_FUNCTION(ether),
2987         SH_PFC_FUNCTION(hspi0),
2988         SH_PFC_FUNCTION(hspi1),
2989         SH_PFC_FUNCTION(hspi2),
2990         SH_PFC_FUNCTION(i2c1),
2991         SH_PFC_FUNCTION(i2c2),
2992         SH_PFC_FUNCTION(i2c3),
2993         SH_PFC_FUNCTION(intc),
2994         SH_PFC_FUNCTION(lbsc),
2995         SH_PFC_FUNCTION(mmc0),
2996         SH_PFC_FUNCTION(mmc1),
2997         SH_PFC_FUNCTION(sdhi0),
2998         SH_PFC_FUNCTION(sdhi1),
2999         SH_PFC_FUNCTION(sdhi2),
3000         SH_PFC_FUNCTION(sdhi3),
3001         SH_PFC_FUNCTION(scif0),
3002         SH_PFC_FUNCTION(scif1),
3003         SH_PFC_FUNCTION(scif2),
3004         SH_PFC_FUNCTION(scif3),
3005         SH_PFC_FUNCTION(scif4),
3006         SH_PFC_FUNCTION(scif5),
3007         SH_PFC_FUNCTION(usb0),
3008         SH_PFC_FUNCTION(usb1),
3009         SH_PFC_FUNCTION(usb2),
3010         SH_PFC_FUNCTION(vin0),
3011         SH_PFC_FUNCTION(vin1),
3012         SH_PFC_FUNCTION(vin2),
3013         SH_PFC_FUNCTION(vin3),
3014 };
3015
3016 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3017         { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
3018                 GP_0_31_FN, FN_IP3_31_29,
3019                 GP_0_30_FN, FN_IP3_26_24,
3020                 GP_0_29_FN, FN_IP3_22_21,
3021                 GP_0_28_FN, FN_IP3_14_12,
3022                 GP_0_27_FN, FN_IP3_11_9,
3023                 GP_0_26_FN, FN_IP3_2_0,
3024                 GP_0_25_FN, FN_IP2_30_28,
3025                 GP_0_24_FN, FN_IP2_21_19,
3026                 GP_0_23_FN, FN_IP2_18_16,
3027                 GP_0_22_FN, FN_IP0_30_28,
3028                 GP_0_21_FN, FN_IP0_5_3,
3029                 GP_0_20_FN, FN_IP1_18_15,
3030                 GP_0_19_FN, FN_IP1_14_11,
3031                 GP_0_18_FN, FN_IP1_10_7,
3032                 GP_0_17_FN, FN_IP1_6_4,
3033                 GP_0_16_FN, FN_IP1_3_2,
3034                 GP_0_15_FN, FN_IP1_1_0,
3035                 GP_0_14_FN, FN_IP0_27_26,
3036                 GP_0_13_FN, FN_IP0_25,
3037                 GP_0_12_FN, FN_IP0_24_23,
3038                 GP_0_11_FN, FN_IP0_22_19,
3039                 GP_0_10_FN, FN_IP0_18_16,
3040                 GP_0_9_FN, FN_IP0_15_14,
3041                 GP_0_8_FN, FN_IP0_13_12,
3042                 GP_0_7_FN, FN_IP0_11_10,
3043                 GP_0_6_FN, FN_IP0_9_8,
3044                 GP_0_5_FN, FN_A19,
3045                 GP_0_4_FN, FN_A18,
3046                 GP_0_3_FN, FN_A17,
3047                 GP_0_2_FN, FN_IP0_7_6,
3048                 GP_0_1_FN, FN_AVS2,
3049                 GP_0_0_FN, FN_AVS1 }
3050         },
3051         { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {
3052                 GP_1_31_FN, FN_IP5_23_21,
3053                 GP_1_30_FN, FN_IP5_20_17,
3054                 GP_1_29_FN, FN_IP5_16_15,
3055                 GP_1_28_FN, FN_IP5_14_13,
3056                 GP_1_27_FN, FN_IP5_12_11,
3057                 GP_1_26_FN, FN_IP5_10_9,
3058                 GP_1_25_FN, FN_IP5_8,
3059                 GP_1_24_FN, FN_IP5_7,
3060                 GP_1_23_FN, FN_IP5_6,
3061                 GP_1_22_FN, FN_IP5_5,
3062                 GP_1_21_FN, FN_IP5_4,
3063                 GP_1_20_FN, FN_IP5_3,
3064                 GP_1_19_FN, FN_IP5_2_0,
3065                 GP_1_18_FN, FN_IP4_31_29,
3066                 GP_1_17_FN, FN_IP4_28,
3067                 GP_1_16_FN, FN_IP4_27,
3068                 GP_1_15_FN, FN_IP4_26,
3069                 GP_1_14_FN, FN_IP4_25,
3070                 GP_1_13_FN, FN_IP4_24,
3071                 GP_1_12_FN, FN_IP4_23,
3072                 GP_1_11_FN, FN_IP4_22_20,
3073                 GP_1_10_FN, FN_IP4_19_17,
3074                 GP_1_9_FN, FN_IP4_16,
3075                 GP_1_8_FN, FN_IP4_15,
3076                 GP_1_7_FN, FN_IP4_14,
3077                 GP_1_6_FN, FN_IP4_13,
3078                 GP_1_5_FN, FN_IP4_12,
3079                 GP_1_4_FN, FN_IP4_11,
3080                 GP_1_3_FN, FN_IP4_10_8,
3081                 GP_1_2_FN, FN_IP4_7_5,
3082                 GP_1_1_FN, FN_IP4_4_2,
3083                 GP_1_0_FN, FN_IP4_1_0 }
3084         },
3085         { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {
3086                 GP_2_31_FN, FN_IP10_28_26,
3087                 GP_2_30_FN, FN_IP10_25_24,
3088                 GP_2_29_FN, FN_IP10_23_21,
3089                 GP_2_28_FN, FN_IP10_20_18,
3090                 GP_2_27_FN, FN_IP10_17_15,
3091                 GP_2_26_FN, FN_IP10_14_12,
3092                 GP_2_25_FN, FN_IP10_11_9,
3093                 GP_2_24_FN, FN_IP10_8_6,
3094                 GP_2_23_FN, FN_IP10_5_3,
3095                 GP_2_22_FN, FN_IP10_2_0,
3096                 GP_2_21_FN, FN_IP9_29_28,
3097                 GP_2_20_FN, FN_IP9_27_26,
3098                 GP_2_19_FN, FN_IP9_25_24,
3099                 GP_2_18_FN, FN_IP9_23_22,
3100                 GP_2_17_FN, FN_IP9_21_19,
3101                 GP_2_16_FN, FN_IP9_18_16,
3102                 GP_2_15_FN, FN_IP9_15_14,
3103                 GP_2_14_FN, FN_IP9_13_12,
3104                 GP_2_13_FN, FN_IP9_11_10,
3105                 GP_2_12_FN, FN_IP9_9_8,
3106                 GP_2_11_FN, FN_IP9_7,
3107                 GP_2_10_FN, FN_IP9_6,
3108                 GP_2_9_FN, FN_IP9_5,
3109                 GP_2_8_FN, FN_IP9_4,
3110                 GP_2_7_FN, FN_IP9_3_2,
3111                 GP_2_6_FN, FN_IP9_1_0,
3112                 GP_2_5_FN, FN_IP8_30_28,
3113                 GP_2_4_FN, FN_IP8_27_25,
3114                 GP_2_3_FN, FN_IP8_24_23,
3115                 GP_2_2_FN, FN_IP8_22_21,
3116                 GP_2_1_FN, FN_IP8_20,
3117                 GP_2_0_FN, FN_IP5_27_24 }
3118         },
3119         { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {
3120                 GP_3_31_FN, FN_IP6_3_2,
3121                 GP_3_30_FN, FN_IP6_1_0,
3122                 GP_3_29_FN, FN_IP5_30_29,
3123                 GP_3_28_FN, FN_IP5_28,
3124                 GP_3_27_FN, FN_IP1_24_23,
3125                 GP_3_26_FN, FN_IP1_22_21,
3126                 GP_3_25_FN, FN_IP1_20_19,
3127                 GP_3_24_FN, FN_IP7_26_25,
3128                 GP_3_23_FN, FN_IP7_24_23,
3129                 GP_3_22_FN, FN_IP7_22_21,
3130                 GP_3_21_FN, FN_IP7_20_19,
3131                 GP_3_20_FN, FN_IP7_30_29,
3132                 GP_3_19_FN, FN_IP7_28_27,
3133                 GP_3_18_FN, FN_IP7_18_17,
3134                 GP_3_17_FN, FN_IP7_16_15,
3135                 GP_3_16_FN, FN_IP12_17_15,
3136                 GP_3_15_FN, FN_IP12_14_12,
3137                 GP_3_14_FN, FN_IP12_11_9,
3138                 GP_3_13_FN, FN_IP12_8_6,
3139                 GP_3_12_FN, FN_IP12_5_3,
3140                 GP_3_11_FN, FN_IP12_2_0,
3141                 GP_3_10_FN, FN_IP11_29_27,
3142                 GP_3_9_FN, FN_IP11_26_24,
3143                 GP_3_8_FN, FN_IP11_23_21,
3144                 GP_3_7_FN, FN_IP11_20_18,
3145                 GP_3_6_FN, FN_IP11_17_15,
3146                 GP_3_5_FN, FN_IP11_14_12,
3147                 GP_3_4_FN, FN_IP11_11_9,
3148                 GP_3_3_FN, FN_IP11_8_6,
3149                 GP_3_2_FN, FN_IP11_5_3,
3150                 GP_3_1_FN, FN_IP11_2_0,
3151                 GP_3_0_FN, FN_IP10_31_29 }
3152         },
3153         { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {
3154                 GP_4_31_FN, FN_IP8_19,
3155                 GP_4_30_FN, FN_IP8_18,
3156                 GP_4_29_FN, FN_IP8_17_16,
3157                 GP_4_28_FN, FN_IP0_2_0,
3158                 GP_4_27_FN, FN_USB_PENC1,
3159                 GP_4_26_FN, FN_USB_PENC0,
3160                 GP_4_25_FN, FN_IP8_15_12,
3161                 GP_4_24_FN, FN_IP8_11_8,
3162                 GP_4_23_FN, FN_IP8_7_4,
3163                 GP_4_22_FN, FN_IP8_3_0,
3164                 GP_4_21_FN, FN_IP2_3_0,
3165                 GP_4_20_FN, FN_IP1_28_25,
3166                 GP_4_19_FN, FN_IP2_15_12,
3167                 GP_4_18_FN, FN_IP2_11_8,
3168                 GP_4_17_FN, FN_IP2_7_4,
3169                 GP_4_16_FN, FN_IP7_14_13,
3170                 GP_4_15_FN, FN_IP7_12_10,
3171                 GP_4_14_FN, FN_IP7_9_7,
3172                 GP_4_13_FN, FN_IP7_6_4,
3173                 GP_4_12_FN, FN_IP7_3_2,
3174                 GP_4_11_FN, FN_IP7_1_0,
3175                 GP_4_10_FN, FN_IP6_30_29,
3176                 GP_4_9_FN, FN_IP6_26_25,
3177                 GP_4_8_FN, FN_IP6_24_23,
3178                 GP_4_7_FN, FN_IP6_22_20,
3179                 GP_4_6_FN, FN_IP6_19_18,
3180                 GP_4_5_FN, FN_IP6_17_15,
3181                 GP_4_4_FN, FN_IP6_14_12,
3182                 GP_4_3_FN, FN_IP6_11_9,
3183                 GP_4_2_FN, FN_IP6_8,
3184                 GP_4_1_FN, FN_IP6_7_6,
3185                 GP_4_0_FN, FN_IP6_5_4 }
3186         },
3187         { PINMUX_CFG_REG("GPSR5", 0xfffc0018, 32, 1) {
3188                 GP_5_31_FN, FN_IP3_5,
3189                 GP_5_30_FN, FN_IP3_4,
3190                 GP_5_29_FN, FN_IP3_3,
3191                 GP_5_28_FN, FN_IP2_27,
3192                 GP_5_27_FN, FN_IP2_26,
3193                 GP_5_26_FN, FN_IP2_25,
3194                 GP_5_25_FN, FN_IP2_24,
3195                 GP_5_24_FN, FN_IP2_23,
3196                 GP_5_23_FN, FN_IP2_22,
3197                 GP_5_22_FN, FN_IP3_28,
3198                 GP_5_21_FN, FN_IP3_27,
3199                 GP_5_20_FN, FN_IP3_23,
3200                 GP_5_19_FN, FN_EX_WAIT0,
3201                 GP_5_18_FN, FN_WE1,
3202                 GP_5_17_FN, FN_WE0,
3203                 GP_5_16_FN, FN_RD,
3204                 GP_5_15_FN, FN_A16,
3205                 GP_5_14_FN, FN_A15,
3206                 GP_5_13_FN, FN_A14,
3207                 GP_5_12_FN, FN_A13,
3208                 GP_5_11_FN, FN_A12,
3209                 GP_5_10_FN, FN_A11,
3210                 GP_5_9_FN, FN_A10,
3211                 GP_5_8_FN, FN_A9,
3212                 GP_5_7_FN, FN_A8,
3213                 GP_5_6_FN, FN_A7,
3214                 GP_5_5_FN, FN_A6,
3215                 GP_5_4_FN, FN_A5,
3216                 GP_5_3_FN, FN_A4,
3217                 GP_5_2_FN, FN_A3,
3218                 GP_5_1_FN, FN_A2,
3219                 GP_5_0_FN, FN_A1 }
3220         },
3221         { PINMUX_CFG_REG("GPSR6", 0xfffc001c, 32, 1) {
3222                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3223                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3224                 0, 0, 0, 0, 0, 0, 0, 0,
3225                 0, 0,
3226                 0, 0,
3227                 0, 0,
3228                 GP_6_8_FN, FN_IP3_20,
3229                 GP_6_7_FN, FN_IP3_19,
3230                 GP_6_6_FN, FN_IP3_18,
3231                 GP_6_5_FN, FN_IP3_17,
3232                 GP_6_4_FN, FN_IP3_16,
3233                 GP_6_3_FN, FN_IP3_15,
3234                 GP_6_2_FN, FN_IP3_8,
3235                 GP_6_1_FN, FN_IP3_7,
3236                 GP_6_0_FN, FN_IP3_6 }
3237         },
3238
3239         { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
3240                              1, 3, 2, 1, 2, 4, 3, 2, 2, 2, 2, 2, 3, 3) {
3241                 /* IP0_31 [1] */
3242                 0, 0,
3243                 /* IP0_30_28 [3] */
3244                 FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
3245                 FN_HRTS1, FN_RX4_C, 0, 0,
3246                 /* IP0_27_26 [2] */
3247                 FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B, 0,
3248                 /* IP0_25 [1] */
3249                 FN_CS0, FN_HSPI_CS2_B,
3250                 /* IP0_24_23 [2] */
3251                 FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B, 0,
3252                 /* IP0_22_19 [4] */
3253                 FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
3254                 FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
3255                 FN_CTS0_B, 0, 0, 0,
3256                 0, 0, 0, 0,
3257                 /* IP0_18_16 [3] */
3258                 FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
3259                 FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B, 0,
3260                 /* IP0_15_14 [2] */
3261                 FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
3262                 /* IP0_13_12 [2] */
3263                 FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
3264                 /* IP0_11_10 [2] */
3265                 FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B, 0,
3266                 /* IP0_9_8 [2] */
3267                 FN_A20, FN_TX5_D, FN_HSPI_TX2_B, 0,
3268                 /* IP0_7_6 [2] */
3269                 FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
3270                 /* IP0_5_3 [3] */
3271                 FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
3272                 FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
3273                 /* IP0_2_0 [3] */
3274                 FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
3275                 FN_SCIF_CLK, FN_TCLK0_C, 0, 0 }
3276         },
3277         { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
3278                              3, 4, 2, 2, 2, 4, 4, 4, 3, 2, 2) {
3279                 /* IP1_31_29 [3] */
3280                 0, 0, 0, 0, 0, 0, 0, 0,
3281                 /* IP1_28_25 [4] */
3282                 FN_HTX0, FN_TX1, FN_SDATA, FN_CTS0_C,
3283                 FN_SUB_TCK, FN_CC5_STATE2, FN_CC5_STATE10, FN_CC5_STATE18,
3284                 FN_CC5_STATE26, FN_CC5_STATE34, 0, 0,
3285                 0, 0, 0, 0,
3286                 /* IP1_24_23 [2] */
3287                 FN_MLB_DAT, FN_PWM4, FN_RX4, 0,
3288                 /* IP1_22_21 [2] */
3289                 FN_MLB_SIG, FN_PWM3, FN_TX4, 0,
3290                 /* IP1_20_19 [2] */
3291                 FN_MLB_CLK, FN_PWM2, FN_SCK4, 0,
3292                 /* IP1_18_15 [4] */
3293                 FN_EX_CS5, FN_SD1_DAT1, FN_MMC0_D1, FN_FD1,
3294                 FN_ATAWR0, FN_VI1_R6, FN_HRX1, FN_RX2_E,
3295                 FN_RX0_B, FN_SSI_WS9, 0, 0,
3296                 0, 0, 0, 0,
3297                 /* IP1_14_11 [4] */
3298                 FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
3299                 FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
3300                 FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, 0,
3301                 0, 0, 0, 0,
3302                 /* IP1_10_7 [4] */
3303                 FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD, FN_FRE,
3304                 FN_ATACS10, FN_VI1_R4, FN_RX5_B, FN_HSCK1,
3305                 FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9, 0,
3306                 0, 0, 0, 0,
3307                 /* IP1_6_4 [3] */
3308                 FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
3309                 FN_ATACS00, 0, 0, 0,
3310                 /* IP1_3_2 [2] */
3311                 FN_EX_CS1, FN_MMC0_D7, FN_FD7, 0,
3312                 /* IP1_1_0 [2] */
3313                 FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, FN_FD6 }
3314         },
3315         { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
3316                              1, 3, 1, 1, 1, 1, 1, 1, 3, 3, 4, 4, 4, 4) {
3317                 /* IP2_31 [1] */
3318                 0, 0,
3319                 /* IP2_30_28 [3] */
3320                 FN_DU0_DG0, FN_LCDOUT8, FN_DREQ1, FN_SCL2,
3321                 FN_AUDATA2, 0, 0, 0,
3322                 /* IP2_27 [1] */
3323                 FN_DU0_DR7, FN_LCDOUT7,
3324                 /* IP2_26 [1] */
3325                 FN_DU0_DR6, FN_LCDOUT6,
3326                 /* IP2_25 [1] */
3327                 FN_DU0_DR5, FN_LCDOUT5,
3328                 /* IP2_24 [1] */
3329                 FN_DU0_DR4, FN_LCDOUT4,
3330                 /* IP2_23 [1] */
3331                 FN_DU0_DR3, FN_LCDOUT3,
3332                 /* IP2_22 [1] */
3333                 FN_DU0_DR2, FN_LCDOUT2,
3334                 /* IP2_21_19 [3] */
3335                 FN_DU0_DR1, FN_LCDOUT1, FN_DACK0, FN_DRACK0,
3336                 FN_GPS_SIGN_B, FN_AUDATA1, FN_RX5_C, 0,
3337                 /* IP2_18_16 [3] */
3338                 FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0, FN_GPS_CLK_B,
3339                 FN_AUDATA0, FN_TX5_C, 0, 0,
3340                 /* IP2_15_12 [4] */
3341                 FN_HRTS0, FN_RTS1_TANS, FN_MDATA, FN_TX0_C,
3342                 FN_SUB_TMS, FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17,
3343                 FN_CC5_STATE25, FN_CC5_STATE33, 0, 0,
3344                 0, 0, 0, 0,
3345                 /* IP2_11_8 [4] */
3346                 FN_HCTS0, FN_CTS1, FN_STM, FN_PWM0_D,
3347                 FN_RX0_C, FN_SCIF_CLK_C, FN_SUB_TRST, FN_TCLK1_B,
3348                 FN_CC5_OSCOUT, 0, 0, 0,
3349                 0, 0, 0, 0,
3350                 /* IP2_7_4 [4] */
3351                 FN_HSCK0, FN_SCK1, FN_MTS, FN_PWM5,
3352                 FN_SCK0_C, FN_SSI_SDATA9_B, FN_SUB_TDO, FN_CC5_STATE0,
3353                 FN_CC5_STATE8, FN_CC5_STATE16, FN_CC5_STATE24, FN_CC5_STATE32,
3354                 0, 0, 0, 0,
3355                 /* IP2_3_0 [4] */
3356                 FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
3357                 FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
3358                 FN_CC5_STATE27, FN_CC5_STATE35, 0, 0,
3359                 0, 0, 0, 0 }
3360         },
3361         { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
3362                              3, 1, 1, 3, 1, 2, 1, 1, 1, 1, 1,
3363                              1, 3, 3, 1, 1, 1, 1, 1, 1, 3) {
3364             /* IP3_31_29 [3] */
3365             FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX, FN_TX2_C,
3366             FN_SCL2_C, FN_REMOCON, 0, 0,
3367             /* IP3_28 [1] */
3368             FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
3369             /* IP3_27 [1] */
3370             FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
3371             /* IP3_26_24 [3] */
3372             FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
3373             FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, 0,
3374             /* IP3_23 [1] */
3375             FN_DU0_DOTCLKOUT0, FN_QCLK,
3376             /* IP3_22_21 [2] */
3377             FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_TX3_D_IRDA_TX_D, FN_SCL3_B,
3378             /* IP3_20 [1] */
3379             FN_DU0_DB7, FN_LCDOUT23,
3380             /* IP3_19 [1] */
3381             FN_DU0_DB6, FN_LCDOUT22,
3382             /* IP3_18 [1] */
3383             FN_DU0_DB5, FN_LCDOUT21,
3384             /* IP3_17 [1] */
3385             FN_DU0_DB4, FN_LCDOUT20,
3386             /* IP3_16 [1] */
3387             FN_DU0_DB3, FN_LCDOUT19,
3388             /* IP3_15 [1] */
3389             FN_DU0_DB2, FN_LCDOUT18,
3390             /* IP3_14_12 [3] */
3391             FN_DU0_DB1, FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1,
3392             FN_GPS_MAG_B, FN_AUDATA5, FN_SCK5_C, 0,
3393             /* IP3_11_9 [3] */
3394             FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1, FN_SCL1,
3395             FN_TCLK1, FN_AUDATA4, 0, 0,
3396             /* IP3_8 [1] */
3397             FN_DU0_DG7, FN_LCDOUT15,
3398             /* IP3_7 [1] */
3399             FN_DU0_DG6, FN_LCDOUT14,
3400             /* IP3_6 [1] */
3401             FN_DU0_DG5, FN_LCDOUT13,
3402             /* IP3_5 [1] */
3403             FN_DU0_DG4, FN_LCDOUT12,
3404             /* IP3_4 [1] */
3405             FN_DU0_DG3, FN_LCDOUT11,
3406             /* IP3_3 [1] */
3407             FN_DU0_DG2, FN_LCDOUT10,
3408             /* IP3_2_0 [3] */
3409             FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
3410             FN_AUDATA3, 0, 0, 0 }
3411         },
3412         { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
3413                              3, 1, 1, 1, 1, 1, 1, 3, 3,
3414                              1, 1, 1, 1, 1, 1, 3, 3, 3, 2) {
3415             /* IP4_31_29 [3] */
3416             FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0,
3417             FN_TX5, FN_SCK0_D, 0, 0,
3418             /* IP4_28 [1] */
3419             FN_DU1_DG7, FN_VI2_R3,
3420             /* IP4_27 [1] */
3421             FN_DU1_DG6, FN_VI2_R2,
3422             /* IP4_26 [1] */
3423             FN_DU1_DG5, FN_VI2_R1,
3424             /* IP4_25 [1] */
3425             FN_DU1_DG4, FN_VI2_R0,
3426             /* IP4_24 [1] */
3427             FN_DU1_DG3, FN_VI2_G7,
3428             /* IP4_23 [1] */
3429             FN_DU1_DG2, FN_VI2_G6,
3430             /* IP4_22_20 [3] */
3431             FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
3432             FN_SCK5, FN_AUDATA7, FN_RX0_D, 0,
3433             /* IP4_19_17 [3] */
3434             FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B, FN_SD3_DAT2,
3435             FN_SCK3_E, FN_AUDATA6, FN_TX0_D, 0,
3436             /* IP4_16 [1] */
3437             FN_DU1_DR7, FN_VI2_G5,
3438             /* IP4_15 [1] */
3439             FN_DU1_DR6, FN_VI2_G4,
3440             /* IP4_14 [1] */
3441             FN_DU1_DR5, FN_VI2_G3,
3442             /* IP4_13 [1] */
3443             FN_DU1_DR4, FN_VI2_G2,
3444             /* IP4_12 [1] */
3445             FN_DU1_DR3, FN_VI2_G1,
3446             /* IP4_11 [1] */
3447             FN_DU1_DR2, FN_VI2_G0,
3448             /* IP4_10_8 [3] */
3449             FN_DU1_DR1, FN_VI2_DATA1_VI2_B1, FN_PWM0, FN_SD3_CMD,
3450             FN_RX3_E_IRDA_RX_E, FN_AUDSYNC, FN_CTS0_D, 0,
3451             /* IP4_7_5 [3] */
3452             FN_DU1_DR0, FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK,
3453             FN_TX3_E_IRDA_TX_E, FN_AUDCK, FN_PWMFSW0_B, 0,
3454             /* IP4_4_2 [3] */
3455             FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
3456             FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, 0,
3457             /* IP4_1_0 [2] */
3458             FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C }
3459         },
3460         { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
3461                              1, 2, 1, 4, 3, 4, 2, 2,
3462                              2, 2, 1, 1, 1, 1, 1, 1, 3) {
3463             /* IP5_31 [1] */
3464             0, 0,
3465             /* IP5_30_29 [2] */
3466             FN_AUDIO_CLKB, FN_USB_OVC2, FN_CAN_DEBUGOUT0, FN_MOUT0,
3467             /* IP5_28 [1] */
3468             FN_AUDIO_CLKA, FN_CAN_TXCLK,
3469             /* IP5_27_24 [4] */
3470             FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B, FN_SD3_WP,
3471             FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD, FN_AUDIO_CLKOUT,
3472             FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D, 0,
3473             0, 0, 0, 0,
3474             /* IP5_23_21 [3] */
3475             FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
3476             FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
3477             /* IP5_20_17 [4] */
3478             FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
3479             FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
3480             FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D, 0,
3481             0, 0, 0, 0,
3482             /* IP5_16_15 [2] */
3483             FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC, 0,
3484             /* IP5_14_13 [2] */
3485             FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC, FN_VI3_HSYNC, 0,
3486             /* IP5_12_11 [2] */
3487             FN_DU1_DOTCLKOUT, FN_VI2_FIELD, FN_SDA1_D, 0,
3488             /* IP5_10_9 [2] */
3489             FN_DU1_DOTCLKIN, FN_VI2_CLKENB, FN_HSPI_CS1, FN_SCL1_D,
3490             /* IP5_8 [1] */
3491             FN_DU1_DB7, FN_SDA2_D,
3492             /* IP5_7 [1] */
3493             FN_DU1_DB6, FN_SCL2_D,
3494             /* IP5_6 [1] */
3495             FN_DU1_DB5, FN_VI2_R7,
3496             /* IP5_5 [1] */
3497             FN_DU1_DB4, FN_VI2_R6,
3498             /* IP5_4 [1] */
3499             FN_DU1_DB3, FN_VI2_R5,
3500             /* IP5_3 [1] */
3501             FN_DU1_DB2, FN_VI2_R4,
3502             /* IP5_2_0 [3] */
3503             FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
3504             FN_RX5, FN_RTS0_D_TANS_D, 0, 0 }
3505         },
3506         { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
3507                              1, 2, 2, 2, 2, 3, 2, 3, 3, 3, 1, 2, 2, 2, 2) {
3508             /* IP6_31 [1] */
3509             0, 0,
3510             /* IP6_30_29 [2] */
3511             FN_SSI_SCK6, FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
3512             /* IP_28_27 [2] */
3513             0, 0, 0, 0,
3514             /* IP6_26_25 [2] */
3515             FN_SSI_SDATA5, FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX,
3516             /* IP6_24_23 [2] */
3517             FN_SSI_WS5, FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX,
3518             /* IP6_22_20 [3] */
3519             FN_SSI_SCK5, FN_ADICLK, FN_CAN_DEBUGOUT10, FN_SCK3,
3520             FN_TCLK0_D, 0, 0, 0,
3521             /* IP6_19_18 [2] */
3522             FN_SSI_SDATA4, FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, 0,
3523             /* IP6_17_15 [3] */
3524             FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
3525             FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, 0,
3526             /* IP6_14_12 [3] */
3527             FN_SSI_WS34, FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX,
3528             FN_SSI_WS9_C, 0, 0, 0,
3529             /* IP6_11_9 [3] */
3530             FN_SSI_SCK34, FN_CAN_DEBUGOUT6, FN_CAN0_TX_B, FN_IERX,
3531             FN_SSI_SCK9_C, 0, 0, 0,
3532             /* IP6_8 [1] */
3533             FN_SSI_SDATA2, FN_CAN_DEBUGOUT5,
3534             /* IP6_7_6 [2] */
3535             FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6, 0,
3536             /* IP6_5_4 [2] */
3537             FN_SSI_SDATA0, FN_CAN_DEBUGOUT3, FN_MOUT5, 0,
3538             /* IP6_3_2 [2] */
3539             FN_SSI_WS0129, FN_CAN_DEBUGOUT2, FN_MOUT2, 0,
3540             /* IP6_1_0 [2] */
3541             FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, 0 }
3542         },
3543         { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
3544                              1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 2, 2) {
3545             /* IP7_31 [1] */
3546             0, 0,
3547             /* IP7_30_29 [2] */
3548             FN_SD0_WP, FN_DACK2, FN_CTS1_B, 0,
3549             /* IP7_28_27 [2] */
3550             FN_SD0_CD, FN_DREQ2, FN_RTS1_B_TANS_B, 0,
3551             /* IP7_26_25 [2] */
3552             FN_SD0_DAT3, FN_ATAWR1, FN_RX2_B, FN_CC5_TDI,
3553             /* IP7_24_23 [2] */
3554             FN_SD0_DAT2, FN_ATARD1, FN_TX2_B, FN_CC5_TCK,
3555             /* IP7_22_21 [2] */
3556             FN_SD0_DAT1, FN_ATAG1, FN_SCK2_B, FN_CC5_TMS,
3557             /* IP7_20_19 [2] */
3558             FN_SD0_DAT0, FN_ATADIR1, FN_RX1_B, FN_CC5_TRST,
3559             /* IP7_18_17 [2] */
3560             FN_SD0_CMD, FN_ATACS11, FN_TX1_B, FN_CC5_TDO,
3561             /* IP7_16_15 [2] */
3562             FN_SD0_CLK, FN_ATACS01, FN_SCK1_B, 0,
3563             /* IP7_14_13 [2] */
3564             FN_SSI_SDATA8, FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C,
3565             /* IP7_12_10 [3] */
3566             FN_SSI_SDATA7, FN_CAN_DEBUGOUT15, FN_IRQ2_B, FN_TCLK1_C,
3567             FN_HSPI_TX1_C, 0, 0, 0,
3568             /* IP7_9_7 [3] */
3569             FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B, FN_SSI_WS9_B,
3570             FN_HSPI_CS1_C, 0, 0, 0,
3571             /* IP7_6_4 [3] */
3572             FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
3573             FN_HSPI_CLK1_C, 0, 0, 0,
3574             /* IP7_3_2 [2] */
3575             FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
3576             /* IP7_1_0 [2] */
3577             FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B }
3578         },
3579         { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
3580                              1, 3, 3, 2, 2, 1, 1, 1, 2, 4, 4, 4, 4) {
3581             /* IP8_31 [1] */
3582             0, 0,
3583             /* IP8_30_28 [3] */
3584             FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B, FN_RTS1_C_TANS_C, FN_RX4_D,
3585             FN_PWMFSW0_C, 0, 0, 0,
3586             /* IP8_27_25 [3] */
3587             FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
3588             FN_MMC1_CMD, FN_HSCK1_B, 0, 0,
3589             /* IP8_24_23 [2] */
3590             FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B, 0,
3591             /* IP8_22_21 [2] */
3592             FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B, FN_MT1_SYNC,
3593             /* IP8_20 [1] */
3594             FN_VI0_CLK, FN_MMC1_CLK,
3595             /* IP8_19 [1] */
3596             FN_FMIN, FN_RDS_DATA,
3597             /* IP8_18 [1] */
3598             FN_BPFCLK, FN_PCMWE,
3599             /* IP8_17_16 [2] */
3600             FN_FMCLK, FN_RDS_CLK, FN_PCMOE, 0,
3601             /* IP8_15_12 [4] */
3602             FN_HSPI_RX0, FN_RX0, FN_CAN_STEP0, FN_AD_NCS,
3603             FN_CC5_STATE7, FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31,
3604             FN_CC5_STATE39, 0, 0, 0,
3605             0, 0, 0, 0,
3606             /* IP8_11_8 [4] */
3607             FN_HSPI_TX0, FN_TX0, FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO,
3608             FN_CC5_STATE6, FN_CC5_STATE14, FN_CC5_STATE22, FN_CC5_STATE30,
3609             FN_CC5_STATE38, 0, 0, 0,
3610             0, 0, 0, 0,
3611             /* IP8_7_4 [4] */
3612             FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1, FN_AD_DI,
3613             FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21, FN_CC5_STATE29,
3614             FN_CC5_STATE37, 0, 0, 0,
3615             0, 0, 0, 0,
3616             /* IP8_3_0 [4] */
3617             FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
3618             FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
3619             FN_CC5_STATE36, 0, 0, 0,
3620             0, 0, 0, 0 }
3621         },
3622         { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
3623                              2, 2, 2, 2, 2, 3, 3, 2, 2,
3624                              2, 2, 1, 1, 1, 1, 2, 2) {
3625             /* IP9_31_30 [2] */
3626             0, 0, 0, 0,
3627             /* IP9_29_28 [2] */
3628             FN_VI0_G7, FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
3629             /* IP9_27_26 [2] */
3630             FN_VI0_G6, FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8,
3631             /* IP9_25_24 [2] */
3632             FN_VI0_G5, FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7,
3633             /* IP9_23_22 [2] */
3634             FN_VI0_G4, FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6,
3635             /* IP9_21_19 [3] */
3636             FN_VI0_G3, FN_ETH_CRS_DV, FN_MMC1_D7, FN_ARM_TRACEDATA_5,
3637             FN_TS_SDAT0, 0, 0, 0,
3638             /* IP9_18_16 [3] */
3639             FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6, FN_ARM_TRACEDATA_4,
3640             FN_TS_SPSYNC0, 0, 0, 0,
3641             /* IP9_15_14 [2] */
3642             FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1, FN_ARM_TRACEDATA_3,
3643             /* IP9_13_12 [2] */
3644             FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0, FN_ARM_TRACEDATA_2,
3645             /* IP9_11_10 [2] */
3646             FN_VI0_DATA7_VI0_B7, FN_MMC1_D5, FN_ARM_TRACEDATA_1, 0,
3647             /* IP9_9_8 [2] */
3648             FN_VI0_DATA6_VI0_B6, FN_MMC1_D4, FN_ARM_TRACEDATA_0, 0,
3649             /* IP9_7 [1] */
3650             FN_VI0_DATA5_VI0_B5, FN_MMC1_D3,
3651             /* IP9_6 [1] */
3652             FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
3653             /* IP9_5 [1] */
3654             FN_VI0_DATA3_VI0_B3, FN_MMC1_D1,
3655             /* IP9_4 [1] */
3656             FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
3657             /* IP9_3_2 [2] */
3658             FN_VI0_DATA1_VI0_B1, FN_HCTS1_B, FN_MT1_PWM, 0,
3659             /* IP9_1_0 [2] */
3660             FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, 0 }
3661         },
3662         { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
3663                              3, 3, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
3664             /* IP10_31_29 [3] */
3665             FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4, FN_SIM_CLK,
3666             FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3, 0,
3667             /* IP10_28_26 [3] */
3668             FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
3669             FN_PWMFSW0_E, 0, 0, 0,
3670             /* IP10_25_24 [2] */
3671             FN_VI1_CLK, FN_SIM_D, FN_SDA3, 0,
3672             /* IP10_23_21 [3] */
3673             FN_VI0_R7, FN_ETH_MDIO, FN_DACK2_C, FN_HSPI_RX1_B,
3674             FN_SCIF_CLK_D, FN_TRACECTL, FN_MT1_PEN, 0,
3675             /* IP10_20_18 [3] */
3676             FN_VI0_R6, FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B,
3677             FN_TRACECLK, FN_MT1_BEN, FN_PWMFSW0_D, 0,
3678             /* IP10_17_15 [3] */
3679             FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
3680             FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, 0,
3681             /* IP10_14_12 [3] */
3682             FN_VI0_R4, FN_ETH_REFCLK, FN_SD2_CD_B, FN_HSPI_CLK1_B,
3683             FN_ARM_TRACEDATA_14, FN_MT1_CLK, FN_TS_SCK0, 0,
3684             /* IP10_11_9 [3] */
3685             FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B, FN_IRQ3,
3686             FN_ARM_TRACEDATA_13, 0, 0, 0,
3687             /* IP10_8_6 [3] */
3688             FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
3689             FN_ARM_TRACEDATA_12, 0, 0, 0,
3690             /* IP10_5_3 [3] */
3691             FN_VI0_R1, FN_SSI_SDATA8_C, FN_DACK1_B, FN_ARM_TRACEDATA_11,
3692             FN_DACK0_C, FN_DRACK0_C, 0, 0,
3693             /* IP10_2_0 [3] */
3694             FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
3695             FN_ARM_TRACEDATA_10, FN_DREQ0_C, 0, 0 }
3696         },
3697         { PINMUX_CFG_REG_VAR("IPSR11", 0xfffc004c, 32,
3698                              2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
3699             /* IP11_31_30 [2] */
3700             0, 0, 0, 0,
3701             /* IP11_29_27 [3] */
3702             FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1,
3703             FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0,
3704             /* IP11_26_24 [3] */
3705             FN_VI1_G0, FN_VI3_DATA0, 0, FN_TS_SCK1,
3706             FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B,
3707             /* IP11_23_21 [3] */
3708             FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI,
3709             FN_HSPI_RX1_D, 0, 0, 0,
3710             /* IP11_20_18 [3] */
3711             FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
3712             FN_HSPI_TX1_D, 0, 0, 0,
3713             /* IP11_17_15 [3] */
3714             FN_VI1_DATA5_VI1_B5, FN_SD2_CMD, FN_MT0_SYNC, FN_SPA_TCK,
3715             FN_HSPI_CS1_D, FN_ADICHS2_B, 0, 0,
3716             /* IP11_14_12 [3] */
3717             FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
3718             FN_HSPI_CLK1_D, FN_ADICHS1_B, 0, 0,
3719             /* IP11_11_9 [3] */
3720             FN_VI1_DATA3_VI1_B3, FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO,
3721             FN_ADICHS0_B, 0, 0, 0,
3722             /* IP11_8_6 [3] */
3723             FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2, FN_MT0_D, FN_SPVTDI,
3724             FN_ADIDATA_B, 0, 0, 0,
3725             /* IP11_5_3 [3] */
3726             FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK, FN_SPV_TMS,
3727             FN_ADICS_B_SAMP_B, 0, 0, 0,
3728             /* IP11_2_0 [3] */
3729             FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
3730             FN_ADICLK_B, 0, 0, 0 }
3731         },
3732         { PINMUX_CFG_REG_VAR("IPSR12", 0xfffc0050, 32,
3733                              4, 4, 4, 2, 3, 3, 3, 3, 3, 3) {
3734             /* IP12_31_28 [4] */
3735             0, 0, 0, 0, 0, 0, 0, 0,
3736             0, 0, 0, 0, 0, 0, 0, 0,
3737             /* IP12_27_24 [4] */
3738             0, 0, 0, 0, 0, 0, 0, 0,
3739             0, 0, 0, 0, 0, 0, 0, 0,
3740             /* IP12_23_20 [4] */
3741             0, 0, 0, 0, 0, 0, 0, 0,
3742             0, 0, 0, 0, 0, 0, 0, 0,
3743             /* IP12_19_18 [2] */
3744             0, 0, 0, 0,
3745             /* IP12_17_15 [3] */
3746             FN_VI1_G7, FN_VI3_DATA7, FN_GPS_MAG, FN_FCE,
3747             FN_SCK4_B, 0, 0, 0,
3748             /* IP12_14_12 [3] */
3749             FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB,
3750             FN_RX4_B, FN_SIM_CLK_B, 0, 0,
3751             /* IP12_11_9 [3] */
3752             FN_VI1_G5, FN_VI3_DATA5, FN_GPS_CLK, FN_FSE,
3753             FN_TX4_B, FN_SIM_D_B, 0, 0,
3754             /* IP12_8_6 [3] */
3755             FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C,
3756             FN_SIM_RST_B, FN_HRX0_B, 0, 0,
3757             /* IP12_5_3 [3] */
3758             FN_VI1_G3, FN_VI3_DATA3, FN_SSI_SCK2, FN_TS_SDAT1,
3759             FN_SCL1_C, FN_HTX0_B, 0, 0,
3760             /* IP12_2_0 [3] */
3761             FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
3762             FN_SCK2, FN_HSCK0_B, 0, 0 }
3763         },
3764         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xfffc0090, 32,
3765                              2, 2, 3, 3, 2, 2, 2, 2, 2,
3766                              1, 1, 1, 1, 1, 1, 1, 2, 1, 2) {
3767             /* SEL_SCIF5 [2] */
3768             FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
3769             /* SEL_SCIF4 [2] */
3770             FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
3771             /* SEL_SCIF3 [3] */
3772             FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
3773             FN_SEL_SCIF3_4, 0, 0, 0,
3774             /* SEL_SCIF2 [3] */
3775             FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
3776             FN_SEL_SCIF2_4, 0, 0, 0,
3777             /* SEL_SCIF1 [2] */
3778             FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
3779             /* SEL_SCIF0 [2] */
3780             FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
3781             /* SEL_SSI9 [2] */
3782             FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2, 0,
3783             /* SEL_SSI8 [2] */
3784             FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0,
3785             /* SEL_SSI7 [2] */
3786             FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
3787             /* SEL_VI0 [1] */
3788             FN_SEL_VI0_0, FN_SEL_VI0_1,
3789             /* SEL_SD2 [1] */
3790             FN_SEL_SD2_0, FN_SEL_SD2_1,
3791             /* SEL_INT3 [1] */
3792             FN_SEL_INT3_0, FN_SEL_INT3_1,
3793             /* SEL_INT2 [1] */
3794             FN_SEL_INT2_0, FN_SEL_INT2_1,
3795             /* SEL_INT1 [1] */
3796             FN_SEL_INT1_0, FN_SEL_INT1_1,
3797             /* SEL_INT0 [1] */
3798             FN_SEL_INT0_0, FN_SEL_INT0_1,
3799             /* SEL_IE [1] */
3800             FN_SEL_IE_0, FN_SEL_IE_1,
3801             /* SEL_EXBUS2 [2] */
3802             FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2, 0,
3803             /* SEL_EXBUS1 [1] */
3804             FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
3805             /* SEL_EXBUS0 [2] */
3806             FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, 0 }
3807         },
3808         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xfffc0094, 32,
3809                              2, 2, 2, 2, 1, 1, 1, 3, 1,
3810                              2, 2, 2, 2, 1, 1, 2, 1, 2, 2) {
3811             /* SEL_TMU1 [2] */
3812             FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2, 0,
3813             /* SEL_TMU0 [2] */
3814             FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3,
3815             /* SEL_SCIF [2] */
3816             FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
3817             /* SEL_CANCLK [2] */
3818             FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, 0,
3819             /* SEL_CAN0 [1] */
3820             FN_SEL_CAN0_0, FN_SEL_CAN0_1,
3821             /* SEL_HSCIF1 [1] */
3822             FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
3823             /* SEL_HSCIF0 [1] */
3824             FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
3825             /* SEL_PWMFSW [3] */
3826             FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2,
3827             FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4, 0, 0, 0,
3828             /* SEL_ADI [1] */
3829             FN_SEL_ADI_0, FN_SEL_ADI_1,
3830             /* [2] */
3831             0, 0, 0, 0,
3832             /* [2] */
3833             0, 0, 0, 0,
3834             /* [2] */
3835             0, 0, 0, 0,
3836             /* SEL_GPS [2] */
3837             FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
3838             /* SEL_SIM [1] */
3839             FN_SEL_SIM_0, FN_SEL_SIM_1,
3840             /* SEL_HSPI2 [1] */
3841             FN_SEL_HSPI2_0, FN_SEL_HSPI2_1,
3842             /* SEL_HSPI1 [2] */
3843             FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3,
3844             /* SEL_I2C3 [1] */
3845             FN_SEL_I2C3_0, FN_SEL_I2C3_1,
3846             /* SEL_I2C2 [2] */
3847             FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
3848             /* SEL_I2C1 [2] */
3849             FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 }
3850         },
3851         { },
3852 };
3853
3854 const struct sh_pfc_soc_info r8a7779_pinmux_info = {
3855         .name = "r8a7779_pfc",
3856
3857         .unlock_reg = 0xfffc0000, /* PMMR */
3858
3859         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3860
3861         .pins = pinmux_pins,
3862         .nr_pins = ARRAY_SIZE(pinmux_pins),
3863         .groups = pinmux_groups,
3864         .nr_groups = ARRAY_SIZE(pinmux_groups),
3865         .functions = pinmux_functions,
3866         .nr_functions = ARRAY_SIZE(pinmux_functions),
3867
3868         .cfg_regs = pinmux_config_regs,
3869
3870         .pinmux_data = pinmux_data,
3871         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
3872 };