2 * r8a7794 processor support - PFC hardware block.
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2015 Renesas Solutions Corp.
6 * Copyright (C) 2015 Cogent Embedded, Inc., <source@cogentembedded.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2
10 * as published by the Free Software Foundation.
13 #include <linux/kernel.h>
18 #define PORT_GP_26(bank, fn, sfx) \
19 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
20 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
21 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
22 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
23 PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
24 PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
25 PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
26 PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
27 PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
28 PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
29 PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
30 PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
31 PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx)
33 #define PORT_GP_28(bank, fn, sfx) \
34 PORT_GP_26(bank, fn, sfx), \
35 PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx)
37 #define CPU_ALL_PORT(fn, sfx) \
38 PORT_GP_32(0, fn, sfx), \
39 PORT_GP_26(1, fn, sfx), \
40 PORT_GP_32(2, fn, sfx), \
41 PORT_GP_32(3, fn, sfx), \
42 PORT_GP_32(4, fn, sfx), \
43 PORT_GP_28(5, fn, sfx), \
44 PORT_GP_26(6, fn, sfx)
53 PINMUX_FUNCTION_BEGIN,
57 FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28,
58 FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6,
59 FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18,
60 FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27,
61 FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4,
62 FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14,
66 FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30,
67 FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10,
68 FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18,
69 FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31,
70 FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0,
73 FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12,
74 FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23,
75 FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2,
76 FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14,
77 FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24,
78 FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2,
79 FN_IP6_5_4, FN_IP6_7_6,
82 FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13,
83 FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20,
84 FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3,
85 FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
86 FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3,
87 FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17,
91 FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3,
92 FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17,
93 FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0,
94 FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
95 FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27,
96 FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8,
97 FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16,
100 FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
101 FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13,
102 FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24,
103 FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9,
104 FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21,
105 FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC,
108 FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2,
109 FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD,
110 FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0,
111 FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
112 FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
115 FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK,
116 FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1,
117 FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3,
118 FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD,
119 FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B,
120 FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B,
121 FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4,
122 FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D,
125 FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, FN_D7, FN_IRQ3, FN_TCLK1,
126 FN_PWM6_B, FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, FN_D9, FN_HSCIF2_HTX,
127 FN_I2C1_SDA_B, FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6,
128 FN_PWM5_C, FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
129 FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, FN_D13,
130 FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B, FN_D14, FN_SCIFA1_RXD,
131 FN_IIC0_SCL_B, FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B, FN_A0,
132 FN_SCIFB1_SCK, FN_PWM3_B, FN_A1, FN_SCIFB1_TXD, FN_A3, FN_SCIFB0_SCK,
133 FN_A4, FN_SCIFB0_TXD, FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
134 FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
137 FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, FN_A8, FN_MSIOF1_RXD,
138 FN_SCIFA0_RXD_B, FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, FN_A10,
139 FN_MSIOF1_SCK, FN_IIC1_SCL_B, FN_A11, FN_MSIOF1_SYNC, FN_IIC1_SDA_B,
140 FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, FN_A13, FN_MSIOF1_SS2,
141 FN_SCIFA5_TXD_B, FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
142 FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, FN_A16,
143 FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_VSP, FN_CAN_CLK_C,
144 FN_TPUTO2_B, FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
145 FN_AVB_AVTP_CAPTURE_B, FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E,
146 FN_CAN1_TX_B, FN_AVB_AVTP_MATCH_B, FN_A19, FN_MSIOF2_SS2, FN_PWM4,
147 FN_TPUTO2, FN_MOUT0, FN_A20, FN_SPCLK, FN_MOUT1,
150 FN_A21, FN_MOSI_IO0, FN_MOUT2, FN_A22, FN_MISO_IO1, FN_MOUT5,
151 FN_ATADIR1_N, FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N, FN_A24, FN_IO3,
152 FN_EX_WAIT2, FN_A25, FN_SSL, FN_ATARD1_N, FN_CS0_N, FN_VI1_DATA8,
153 FN_CS1_N_A26, FN_VI1_DATA9, FN_EX_CS0_N, FN_VI1_DATA10, FN_EX_CS1_N,
154 FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, FN_EX_CS2_N, FN_PWM0,
155 FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD,
156 FN_SDATA_B, FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
157 FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B, FN_EX_CS4_N,
158 FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_RIF0_D0, FN_FMCLK,
159 FN_SCIFB2_CTS_N, FN_SCKZ_B, FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E,
160 FN_TS_SPSYNC_B, FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B,
161 FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, FN_MTS_N_B,
162 FN_RD_N, FN_ATACS11_N, FN_RD_WR_N, FN_ATAG1_N,
165 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, FN_DU0_DR0,
166 FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, FN_CC50_STATE0,
167 FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, FN_CC50_STATE1,
168 FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, FN_DU0_DR3, FN_LCDOUT19,
169 FN_CC50_STATE3, FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, FN_DU0_DR5,
170 FN_LCDOUT21, FN_CC50_STATE5, FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6,
171 FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, FN_DU0_DG0, FN_LCDOUT8,
172 FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, FN_CC50_STATE8, FN_DU0_DG1, FN_LCDOUT9,
173 FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, FN_CC50_STATE9, FN_DU0_DG2, FN_LCDOUT10,
174 FN_CC50_STATE10, FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, FN_DU0_DG4,
175 FN_LCDOUT12, FN_CC50_STATE12,
178 FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, FN_DU0_DG6, FN_LCDOUT14,
179 FN_CC50_STATE14, FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, FN_DU0_DB0,
180 FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C,
181 FN_CC50_STATE16, FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
182 FN_CAN0_TX_C, FN_CC50_STATE17, FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18,
183 FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, FN_DU0_DB4, FN_LCDOUT4,
184 FN_CC50_STATE20, FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, FN_DU0_DB6,
185 FN_LCDOUT6, FN_CC50_STATE22, FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23,
186 FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, FN_DU0_DOTCLKOUT0,
187 FN_QCLK, FN_CC50_STATE25, FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE,
188 FN_CC50_STATE26, FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27,
191 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28,
192 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
193 FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, FN_DU0_CDE, FN_QPOLB,
194 FN_CC50_STATE31, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0,
195 FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, FN_VI0_DATA2_VI0_B2,
196 FN_AVB_RXD1, FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, FN_VI0_DATA4_VI0_B4,
197 FN_AVB_RXD3, FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6,
198 FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, FN_VI0_CLKENB,
199 FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, FN_VI0_FIELD,
200 FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N,
201 FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N,
202 FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN,
203 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, FN_AVB_TX_CLK,
204 FN_ADIDATA, FN_AD_DI,
207 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, FN_AVB_TXD0,
208 FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B,
209 FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3,
210 FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N,
211 FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
212 FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
213 FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C,
214 FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C,
215 FN_IIC1_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0,
216 FN_SCIF2_TXD_C, FN_IIC1_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B,
217 FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
218 FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
219 FN_SSI_WS6_B, FN_DREQ0_N, FN_SCIFB1_RXD,
222 FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC,
223 FN_SSI_SDATA6_B, FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C,
224 FN_AUDIO_CLKA_B, FN_AVB_MDIO, FN_SSI_SCK78_B, FN_HSCIF0_HTX,
225 FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, FN_SSI_WS78_B,
226 FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
227 FN_AVB_MAGIC, FN_SSI_SDATA7_B, FN_HSCIF0_HRTS_N, FN_VI0_R7,
228 FN_SCIF0_TXD_D, FN_I2C0_SDA_E, FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
229 FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
230 FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
231 FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0,
232 FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, FN_I2C1_SCL, FN_SCIF4_RXD,
233 FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B,
234 FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_RIF1_CLK_B,
235 FN_TS_SCK_D, FN_BPFCLK_C, FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C,
236 FN_DU1_DR2, FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
239 FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_RIF1_D1_B,
240 FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, FN_MSIOF0_SCK, FN_IRQ0,
241 FN_TS_SDATA, FN_DU1_DR4, FN_RIF1_SYNC, FN_TPUTO1_C, FN_MSIOF0_SYNC,
242 FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_RIF1_CLK, FN_BPFCLK_B, FN_MSIOF0_SS1,
243 FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_RIF1_D0, FN_FMCLK_B,
244 FN_RDS_CLK_B, FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
245 FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, FN_HSCIF1_HRX, FN_I2C4_SCL,
246 FN_PWM6, FN_DU1_DG0, FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
247 FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B,
248 FN_SPEEDIN_B, FN_VSP_B, FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK,
249 FN_DU1_DG3, FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32,
250 FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B,
251 FN_CAN_STEP0, FN_CC50_STATE33, FN_SCIF1_SCK, FN_PWM3, FN_TCLK2,
252 FN_DU1_DG5, FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34,
255 FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, FN_CAN_DEBUGOUT0,
256 FN_CC50_STATE35, FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
257 FN_CAN_DEBUGOUT1, FN_CC50_STATE36, FN_SCIF2_RXD, FN_IIC1_SCL,
258 FN_DU1_DB0, FN_SSI_SDATA2_B, FN_USB0_EXTLP, FN_CAN_DEBUGOUT2,
259 FN_CC50_STATE37, FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
260 FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, FN_SCIF2_SCK, FN_IRQ1,
261 FN_DU1_DB2, FN_SSI_WS9_B, FN_USB0_IDIN, FN_CAN_DEBUGOUT4,
262 FN_CC50_STATE39, FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
263 FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT,
264 FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C,
265 FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C, FN_SCIF3_TXD,
266 FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C, FN_SSI_WS4_B,
267 FN_CAN_DEBUGOUT7, FN_RDS_DATA_C, FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6,
268 FN_AUDIO_CLKC_C, FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, FN_I2C2_SDA,
269 FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, FN_CAN_DEBUGOUT9,
270 FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10,
273 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
274 FN_CAN_DEBUGOUT11, FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C,
275 FN_DU1_DOTCLKOUT1, FN_CAN_DEBUGOUT12, FN_SSI_SCK6, FN_SCIFA1_SCK_B,
276 FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13, FN_SSI_WS6,
277 FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
278 FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
279 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78,
280 FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, FN_SSI_WS78,
281 FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7,
282 FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N,
283 FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
284 FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D,
285 FN_ADICS_SAMP_B, FN_AD_DO_B, FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B,
286 FN_ADICLK_B, FN_AD_CLK_B,
289 FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
290 FN_AD_NCS_N_B, FN_DREQ1_N_B, FN_SSI_WS34, FN_MSIOF1_SS1_B,
291 FN_SCIFA1_RXD_C, FN_ADICHS1_B, FN_CAN1_RX_C, FN_DACK1_B, FN_SSI_SDATA3,
292 FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, FN_CAN1_TX_C,
293 FN_DREQ2_N, FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX, FN_SSI_WS4,
294 FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX, FN_SSI_SDATA4, FN_MLB_DAT,
295 FN_IERX_B, FN_IRD_SCK, FN_SSI_SDATA8, FN_SCIF1_SCK_B,
296 FN_PWM1_B, FN_IRQ9, FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, FN_SSI_SCK1,
297 FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
298 FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, FN_SSI_WS1, FN_SCIF1_TXD_B,
299 FN_IIC1_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH,
300 FN_ETH_RX_ER_B, FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_SDATA, FN_VI1_DATA1,
301 FN_ATAG0_N, FN_ETH_RXD0_B, FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2,
302 FN_MDATA, FN_ATAWR0_N, FN_ETH_RXD1_B,
305 FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, FN_SCKZ,
306 FN_ATACS00_N, FN_ETH_LINK_B, FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B,
307 FN_SCIFA0_TXD_D, FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B,
308 FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_MTS_N,
309 FN_EX_WAIT1, FN_ETH_TXD1_B, FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E,
310 FN_VI1_DATA6, FN_ATARD0_N, FN_ETH_TX_EN_B, FN_SSI_SDATA9,
311 FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, FN_ATADIR0_N,
312 FN_ETH_MAGIC_B, FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D,
313 FN_VI1_CLKENB, FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B,
314 FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
315 FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B, FN_AUDIO_CLKC,
316 FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, FN_TS_SDEN_C,
317 FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D, FN_AUDIO_CLKOUT, FN_I2C4_SDA_B,
318 FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, FN_TS_SPSYNC_C, FN_RIF0_D1_B,
319 FN_FMIN_E, FN_RDS_DATA_D,
322 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
323 FN_SEL_ADI_0, FN_SEL_ADI_1, FN_SEL_CAN_0, FN_SEL_CAN_1,
324 FN_SEL_CAN_2, FN_SEL_CAN_3, FN_SEL_DARC_0, FN_SEL_DARC_1,
325 FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_DR0_0,
326 FN_SEL_DR0_1, FN_SEL_DR1_0, FN_SEL_DR1_1, FN_SEL_DR2_0, FN_SEL_DR2_1,
327 FN_SEL_DR3_0, FN_SEL_DR3_1, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_FSN_0,
328 FN_SEL_FSN_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2,
329 FN_SEL_I2C00_3, FN_SEL_I2C00_4, FN_SEL_I2C01_0, FN_SEL_I2C01_1,
330 FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, FN_SEL_I2C02_0,
331 FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4,
332 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
333 FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2,
334 FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_IIC00_0, FN_SEL_IIC00_1,
335 FN_SEL_IIC00_2, FN_SEL_IIC00_3, FN_SEL_AVB_0, FN_SEL_AVB_1,
338 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC01_0,
339 FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, FN_SEL_LBS_0,
340 FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0,
341 FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0,
342 FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0,
343 FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0,
344 FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
345 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1,
346 FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1,
347 FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_SPDM_0, FN_SEL_SPDM_1,
348 FN_SEL_TMU_0, FN_SEL_TMU_1, FN_SEL_TSIF0_0, FN_SEL_TSIF0_1,
349 FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1,
350 FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1,
351 FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
352 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_RDS_0, FN_SEL_RDS_1,
353 FN_SEL_RDS_2, FN_SEL_RDS_3,
356 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
357 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0,
358 FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
359 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
360 FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2,
361 FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0,
362 FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0,
363 FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0,
364 FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0,
369 A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK,
371 USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
373 SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK,
374 SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK,
376 SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
377 SD1_DATA2_MARK, SD1_DATA3_MARK,
380 SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK,
381 MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK,
382 SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK,
383 SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK,
384 MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK,
385 CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK,
386 CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK,
387 SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK,
388 SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK,
389 SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK,
392 D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK, D7_MARK, IRQ3_MARK,
393 TCLK1_MARK, PWM6_B_MARK, D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK,
394 D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK, D10_MARK,
395 HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
396 D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK,
397 D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK,
398 D13_MARK, SCIFA1_SCK_MARK, TANS1_MARK, PWM2_C_MARK, TCLK2_B_MARK,
399 D14_MARK, SCIFA1_RXD_MARK, IIC0_SCL_B_MARK, D15_MARK, SCIFA1_TXD_MARK,
400 IIC0_SDA_B_MARK, A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK, A1_MARK,
401 SCIFB1_TXD_MARK, A3_MARK, SCIFB0_SCK_MARK, A4_MARK, SCIFB0_TXD_MARK,
402 A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK, A6_MARK,
403 SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK,
406 A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK, A8_MARK, MSIOF1_RXD_MARK,
407 SCIFA0_RXD_B_MARK, A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK,
408 A10_MARK, MSIOF1_SCK_MARK, IIC1_SCL_B_MARK, A11_MARK, MSIOF1_SYNC_MARK,
409 IIC1_SDA_B_MARK, A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK,
410 A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK, A14_MARK, MSIOF2_RXD_MARK,
411 HSCIF0_HRX_B_MARK, DREQ1_N_MARK, A15_MARK, MSIOF2_TXD_MARK,
412 HSCIF0_HTX_B_MARK, DACK1_MARK, A16_MARK, MSIOF2_SCK_MARK,
413 HSCIF0_HSCK_B_MARK, SPEEDIN_MARK, VSP_MARK, CAN_CLK_C_MARK,
414 TPUTO2_B_MARK, A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK,
415 CAN1_RX_B_MARK, AVB_AVTP_CAPTURE_B_MARK, A18_MARK, MSIOF2_SS1_MARK,
416 SCIF4_TXD_E_MARK, CAN1_TX_B_MARK, AVB_AVTP_MATCH_B_MARK, A19_MARK,
417 MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK, MOUT0_MARK, A20_MARK,
418 SPCLK_MARK, MOUT1_MARK,
421 A21_MARK, MOSI_IO0_MARK, MOUT2_MARK, A22_MARK, MISO_IO1_MARK,
422 MOUT5_MARK, ATADIR1_N_MARK, A23_MARK, IO2_MARK, MOUT6_MARK,
423 ATAWR1_N_MARK, A24_MARK, IO3_MARK, EX_WAIT2_MARK, A25_MARK, SSL_MARK,
424 ATARD1_N_MARK, CS0_N_MARK, VI1_DATA8_MARK, CS1_N_A26_MARK,
425 VI1_DATA9_MARK, EX_CS0_N_MARK, VI1_DATA10_MARK, EX_CS1_N_MARK,
426 TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK, EX_CS2_N_MARK,
427 PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK, RIF0_SYNC_MARK,
428 TPUTO3_MARK, SCIFB2_TXD_MARK, SDATA_B_MARK, EX_CS3_N_MARK,
429 SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK, RIF0_CLK_MARK,
430 BPFCLK_MARK, SCIFB2_SCK_MARK, MDATA_B_MARK, EX_CS4_N_MARK,
431 SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK, RIF0_D0_MARK,
432 FMCLK_MARK, SCIFB2_CTS_N_MARK, SCKZ_B_MARK, EX_CS5_N_MARK,
433 SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK, RIF0_D1_MARK,
434 FMIN_MARK, SCIFB2_RTS_N_MARK, STM_N_B_MARK, BS_N_MARK, DRACK0_MARK,
435 PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK, MTS_N_B_MARK, RD_N_MARK,
436 ATACS11_N_MARK, RD_WR_N_MARK, ATAG1_N_MARK,
439 EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK, PWMFSW0_MARK,
440 DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK,
441 CC50_STATE0_MARK, DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK,
442 I2C2_SDA_D_MARK, CC50_STATE1_MARK, DU0_DR2_MARK, LCDOUT18_MARK,
443 CC50_STATE2_MARK, DU0_DR3_MARK, LCDOUT19_MARK, CC50_STATE3_MARK,
444 DU0_DR4_MARK, LCDOUT20_MARK, CC50_STATE4_MARK, DU0_DR5_MARK,
445 LCDOUT21_MARK, CC50_STATE5_MARK, DU0_DR6_MARK, LCDOUT22_MARK,
446 CC50_STATE6_MARK, DU0_DR7_MARK, LCDOUT23_MARK, CC50_STATE7_MARK,
447 DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK,
448 CC50_STATE8_MARK, DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK,
449 I2C3_SDA_D_MARK, CC50_STATE9_MARK, DU0_DG2_MARK, LCDOUT10_MARK,
450 CC50_STATE10_MARK, DU0_DG3_MARK, LCDOUT11_MARK, CC50_STATE11_MARK,
451 DU0_DG4_MARK, LCDOUT12_MARK, CC50_STATE12_MARK,
454 DU0_DG5_MARK, LCDOUT13_MARK, CC50_STATE13_MARK, DU0_DG6_MARK,
455 LCDOUT14_MARK, CC50_STATE14_MARK, DU0_DG7_MARK, LCDOUT15_MARK,
456 CC50_STATE15_MARK, DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK,
457 I2C4_SCL_D_MARK, CAN0_RX_C_MARK, CC50_STATE16_MARK, DU0_DB1_MARK,
458 LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK, CAN0_TX_C_MARK,
459 CC50_STATE17_MARK, DU0_DB2_MARK, LCDOUT2_MARK, CC50_STATE18_MARK,
460 DU0_DB3_MARK, LCDOUT3_MARK, CC50_STATE19_MARK, DU0_DB4_MARK,
461 LCDOUT4_MARK, CC50_STATE20_MARK, DU0_DB5_MARK, LCDOUT5_MARK,
462 CC50_STATE21_MARK, DU0_DB6_MARK, LCDOUT6_MARK, CC50_STATE22_MARK,
463 DU0_DB7_MARK, LCDOUT7_MARK, CC50_STATE23_MARK, DU0_DOTCLKIN_MARK,
464 QSTVA_QVS_MARK, CC50_STATE24_MARK, DU0_DOTCLKOUT0_MARK,
465 QCLK_MARK, CC50_STATE25_MARK, DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK,
466 CC50_STATE26_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
470 DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, CC50_STATE28_MARK,
471 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CC50_STATE29_MARK,
472 DU0_DISP_MARK, QPOLA_MARK, CC50_STATE30_MARK, DU0_CDE_MARK, QPOLB_MARK,
473 CC50_STATE31_MARK, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK,
474 AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
475 VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, VI0_DATA3_VI0_B3_MARK,
476 AVB_RXD2_MARK, VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
477 VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK,
478 AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, VI0_CLKENB_MARK,
479 I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, AVB_RXD7_MARK,
480 VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
481 AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK,
482 IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK,
483 I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK,
484 VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK, AVB_TX_CLK_MARK,
485 ADIDATA_MARK, AD_DI_MARK,
488 ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, IIC0_SDA_D_MARK,
489 AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK,
490 MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK,
491 AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK,
492 CAN0_TX_B_MARK, AVB_TXD2_MARK, ADICHS0_MARK, AD_NCS_N_MARK,
493 ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
494 AVB_TXD3_MARK, ADICHS1_MARK, ETH_LINK_MARK, VI0_G5_MARK,
495 MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK,
496 ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
497 SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK,
498 IIC1_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK,
499 VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC1_SDA_D_MARK, AVB_TXD7_MARK,
500 SSI_SDATA5_B_MARK, ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK,
501 AVB_TX_ER_MARK, SSI_SCK6_B_MARK, ETH_TXD0_MARK, VI0_R2_MARK,
502 SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
503 DREQ0_N_MARK, SCIFB1_RXD_MARK,
506 ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK,
507 AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK,
508 I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK,
509 HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK,
510 AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK,
511 SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK,
512 HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK,
513 AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK,
514 HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK,
515 I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK,
516 AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
517 SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
518 CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK,
519 DU1_DR0_MARK, RIF1_SYNC_B_MARK, TS_SDATA_D_MARK, TPUTO1_B_MARK,
520 I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, RIF1_CLK_B_MARK,
521 TS_SCK_D_MARK, BPFCLK_C_MARK, MSIOF0_RXD_MARK, SCIF5_RXD_MARK,
522 I2C2_SCL_C_MARK, DU1_DR2_MARK, RIF1_D0_B_MARK, TS_SDEN_D_MARK,
523 FMCLK_C_MARK, RDS_CLK_MARK,
526 MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK,
527 RIF1_D1_B_MARK, TS_SPSYNC_D_MARK, FMIN_C_MARK, RDS_DATA_MARK,
528 MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, RIF1_SYNC_MARK,
529 TPUTO1_C_MARK, MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK,
530 RIF1_CLK_MARK, BPFCLK_B_MARK, MSIOF0_SS1_MARK, SCIFA0_RXD_MARK,
531 TS_SDEN_MARK, DU1_DR6_MARK, RIF1_D0_MARK, FMCLK_B_MARK, RDS_CLK_B_MARK,
532 MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK,
533 RIF1_D1_MARK, FMIN_B_MARK, RDS_DATA_B_MARK, HSCIF1_HRX_MARK,
534 I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK, HSCIF1_HTX_MARK,
535 I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK, HSCIF1_HSCK_MARK,
536 PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK, SPEEDIN_B_MARK,
537 VSP_B_MARK, HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK,
538 DU1_DG3_MARK, SSI_SCK1_B_MARK, CAN_DEBUG_HW_TRIGGER_MARK,
539 CC50_STATE32_MARK, HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK,
540 DU1_DG4_MARK, SSI_WS1_B_MARK, CAN_STEP0_MARK, CC50_STATE33_MARK,
541 SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK,
542 CAN_TXCLK_MARK, CC50_STATE34_MARK,
545 SCIF1_RXD_MARK, IIC0_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK,
546 CAN_DEBUGOUT0_MARK, CC50_STATE35_MARK, SCIF1_TXD_MARK, IIC0_SDA_MARK,
547 DU1_DG7_MARK, SSI_WS2_B_MARK, CAN_DEBUGOUT1_MARK, CC50_STATE36_MARK,
548 SCIF2_RXD_MARK, IIC1_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
549 USB0_EXTLP_MARK, CAN_DEBUGOUT2_MARK, CC50_STATE37_MARK, SCIF2_TXD_MARK,
550 IIC1_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK, USB0_OVC1_MARK,
551 CAN_DEBUGOUT3_MARK, CC50_STATE38_MARK, SCIF2_SCK_MARK, IRQ1_MARK,
552 DU1_DB2_MARK, SSI_WS9_B_MARK, USB0_IDIN_MARK, CAN_DEBUGOUT4_MARK,
553 CC50_STATE39_MARK, SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK,
554 DU1_DB3_MARK, SSI_SDATA9_B_MARK, TANS2_MARK, CAN_DEBUGOUT5_MARK,
555 CC50_OSCOUT_MARK, SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK,
556 DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK, CAN_DEBUGOUT6_MARK,
557 RDS_CLK_C_MARK, SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK,
558 DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK, CAN_DEBUGOUT7_MARK,
559 RDS_DATA_C_MARK, I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK,
560 AUDIO_CLKC_C_MARK, SSI_SDATA4_B_MARK, CAN_DEBUGOUT8_MARK, I2C2_SDA_MARK,
561 SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK, CAN_DEBUGOUT9_MARK,
562 SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK, CAN_DEBUGOUT10_MARK,
565 SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
566 CAN_DEBUGOUT11_MARK, SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK,
567 DU1_DOTCLKOUT1_MARK, CAN_DEBUGOUT12_MARK, SSI_SCK6_MARK,
568 SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, CAN_DEBUGOUT13_MARK,
569 SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
570 DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK,
571 SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
572 CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK,
573 DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK,
574 DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK,
575 AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK,
576 MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK,
577 PCMWE_N_MARK, SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK,
578 ADICS_SAMP_B_MARK, AD_DO_B_MARK, SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK,
579 PWM0_B_MARK, ADICLK_B_MARK, AD_CLK_B_MARK,
582 SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK,
583 AD_NCS_N_B_MARK, DREQ1_N_B_MARK, SSI_WS34_MARK, MSIOF1_SS1_B_MARK,
584 SCIFA1_RXD_C_MARK, ADICHS1_B_MARK, CAN1_RX_C_MARK, DACK1_B_MARK,
585 SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK,
586 CAN1_TX_C_MARK, DREQ2_N_MARK, SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK,
587 IRD_TX_MARK, SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK, IRD_RX_MARK,
588 SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK, IRD_SCK_MARK,
589 SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK,
590 DACK2_MARK, ETH_MDIO_B_MARK, SSI_SCK1_MARK, SCIF1_RXD_B_MARK,
591 IIC1_SCL_C_MARK, VI1_CLK_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_MARK,
592 ETH_CRS_DV_B_MARK, SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC1_SDA_C_MARK,
593 VI1_DATA0_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_MARK, ETH_RX_ER_B_MARK,
594 SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, SDATA_MARK,
595 ATAG0_N_MARK, ETH_RXD0_B_MARK, SSI_SCK2_MARK, HSCIF1_HTX_B_MARK,
596 VI1_DATA2_MARK, MDATA_MARK, ATAWR0_N_MARK, ETH_RXD1_B_MARK,
599 SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK,
600 SCKZ_MARK, ATACS00_N_MARK, ETH_LINK_B_MARK, SSI_SDATA2_MARK,
601 HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK, VI1_DATA4_MARK, STM_N_MARK,
602 ATACS10_N_MARK, ETH_REFCLK_B_MARK, SSI_SCK9_MARK, SCIF2_SCK_B_MARK,
603 PWM2_B_MARK, VI1_DATA5_MARK, MTS_N_MARK, EX_WAIT1_MARK,
604 ETH_TXD1_B_MARK, SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK,
605 VI1_DATA6_MARK, ATARD0_N_MARK, ETH_TX_EN_B_MARK, SSI_SDATA9_MARK,
606 SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK, ATADIR0_N_MARK,
607 ETH_MAGIC_B_MARK, AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK,
608 VI1_CLKENB_MARK, TS_SDATA_C_MARK, RIF0_SYNC_B_MARK, ETH_TXD0_B_MARK,
609 AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK,
610 TS_SCK_C_MARK, RIF0_CLK_B_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK,
611 AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK,
612 TS_SDEN_C_MARK, RIF0_D0_B_MARK, FMCLK_E_MARK, RDS_CLK_D_MARK,
613 AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK,
614 TS_SPSYNC_C_MARK, RIF0_D1_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK,
618 static const u16 pinmux_data[] = {
619 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
621 PINMUX_DATA(A2_MARK, FN_A2),
622 PINMUX_DATA(WE0_N_MARK, FN_WE0_N),
623 PINMUX_DATA(WE1_N_MARK, FN_WE1_N),
624 PINMUX_DATA(DACK0_MARK, FN_DACK0),
625 PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
626 PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC),
627 PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
628 PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC),
629 PINMUX_DATA(SD0_CLK_MARK, FN_SD0_CLK),
630 PINMUX_DATA(SD0_CMD_MARK, FN_SD0_CMD),
631 PINMUX_DATA(SD0_DATA0_MARK, FN_SD0_DATA0),
632 PINMUX_DATA(SD0_DATA1_MARK, FN_SD0_DATA1),
633 PINMUX_DATA(SD0_DATA2_MARK, FN_SD0_DATA2),
634 PINMUX_DATA(SD0_DATA3_MARK, FN_SD0_DATA3),
635 PINMUX_DATA(SD0_CD_MARK, FN_SD0_CD),
636 PINMUX_DATA(SD0_WP_MARK, FN_SD0_WP),
637 PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK),
638 PINMUX_DATA(SD1_CMD_MARK, FN_SD1_CMD),
639 PINMUX_DATA(SD1_DATA0_MARK, FN_SD1_DATA0),
640 PINMUX_DATA(SD1_DATA1_MARK, FN_SD1_DATA1),
641 PINMUX_DATA(SD1_DATA2_MARK, FN_SD1_DATA2),
642 PINMUX_DATA(SD1_DATA3_MARK, FN_SD1_DATA3),
645 PINMUX_IPSR_DATA(IP0_0, SD1_CD),
646 PINMUX_IPSR_MSEL(IP0_0, CAN0_RX, SEL_CAN0_0),
647 PINMUX_IPSR_DATA(IP0_9_8, SD1_WP),
648 PINMUX_IPSR_DATA(IP0_9_8, IRQ7),
649 PINMUX_IPSR_MSEL(IP0_9_8, CAN0_TX, SEL_CAN0_0),
650 PINMUX_IPSR_DATA(IP0_10, MMC_CLK),
651 PINMUX_IPSR_DATA(IP0_10, SD2_CLK),
652 PINMUX_IPSR_DATA(IP0_11, MMC_CMD),
653 PINMUX_IPSR_DATA(IP0_11, SD2_CMD),
654 PINMUX_IPSR_DATA(IP0_12, MMC_D0),
655 PINMUX_IPSR_DATA(IP0_12, SD2_DATA0),
656 PINMUX_IPSR_DATA(IP0_13, MMC_D1),
657 PINMUX_IPSR_DATA(IP0_13, SD2_DATA1),
658 PINMUX_IPSR_DATA(IP0_14, MMC_D2),
659 PINMUX_IPSR_DATA(IP0_14, SD2_DATA2),
660 PINMUX_IPSR_DATA(IP0_15, MMC_D3),
661 PINMUX_IPSR_DATA(IP0_15, SD2_DATA3),
662 PINMUX_IPSR_DATA(IP0_16, MMC_D4),
663 PINMUX_IPSR_DATA(IP0_16, SD2_CD),
664 PINMUX_IPSR_DATA(IP0_17, MMC_D5),
665 PINMUX_IPSR_DATA(IP0_17, SD2_WP),
666 PINMUX_IPSR_DATA(IP0_19_18, MMC_D6),
667 PINMUX_IPSR_MSEL(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
668 PINMUX_IPSR_MSEL(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
669 PINMUX_IPSR_MSEL(IP0_19_18, CAN1_RX, SEL_CAN1_0),
670 PINMUX_IPSR_DATA(IP0_21_20, MMC_D7),
671 PINMUX_IPSR_MSEL(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
672 PINMUX_IPSR_MSEL(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
673 PINMUX_IPSR_MSEL(IP0_21_20, CAN1_TX, SEL_CAN1_0),
674 PINMUX_IPSR_DATA(IP0_23_22, D0),
675 PINMUX_IPSR_MSEL(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
676 PINMUX_IPSR_DATA(IP0_23_22, IRQ4),
677 PINMUX_IPSR_DATA(IP0_24, D1),
678 PINMUX_IPSR_MSEL(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
679 PINMUX_IPSR_DATA(IP0_25, D2),
680 PINMUX_IPSR_MSEL(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1),
681 PINMUX_IPSR_DATA(IP0_27_26, D3),
682 PINMUX_IPSR_MSEL(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1),
683 PINMUX_IPSR_MSEL(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1),
684 PINMUX_IPSR_DATA(IP0_29_28, D4),
685 PINMUX_IPSR_MSEL(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1),
686 PINMUX_IPSR_MSEL(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1),
687 PINMUX_IPSR_DATA(IP0_31_30, D5),
688 PINMUX_IPSR_MSEL(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1),
689 PINMUX_IPSR_MSEL(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3),
692 PINMUX_IPSR_DATA(IP1_1_0, D6),
693 PINMUX_IPSR_MSEL(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1),
694 PINMUX_IPSR_MSEL(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3),
695 PINMUX_IPSR_DATA(IP1_3_2, D7),
696 PINMUX_IPSR_DATA(IP1_3_2, IRQ3),
697 PINMUX_IPSR_MSEL(IP1_3_2, TCLK1, SEL_TMU_0),
698 PINMUX_IPSR_DATA(IP1_3_2, PWM6_B),
699 PINMUX_IPSR_DATA(IP1_5_4, D8),
700 PINMUX_IPSR_DATA(IP1_5_4, HSCIF2_HRX),
701 PINMUX_IPSR_MSEL(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1),
702 PINMUX_IPSR_DATA(IP1_7_6, D9),
703 PINMUX_IPSR_DATA(IP1_7_6, HSCIF2_HTX),
704 PINMUX_IPSR_MSEL(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1),
705 PINMUX_IPSR_DATA(IP1_10_8, D10),
706 PINMUX_IPSR_DATA(IP1_10_8, HSCIF2_HSCK),
707 PINMUX_IPSR_MSEL(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2),
708 PINMUX_IPSR_DATA(IP1_10_8, IRQ6),
709 PINMUX_IPSR_DATA(IP1_10_8, PWM5_C),
710 PINMUX_IPSR_DATA(IP1_12_11, D11),
711 PINMUX_IPSR_DATA(IP1_12_11, HSCIF2_HCTS_N),
712 PINMUX_IPSR_MSEL(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2),
713 PINMUX_IPSR_MSEL(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3),
714 PINMUX_IPSR_DATA(IP1_14_13, D12),
715 PINMUX_IPSR_DATA(IP1_14_13, HSCIF2_HRTS_N),
716 PINMUX_IPSR_MSEL(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2),
717 PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3),
718 PINMUX_IPSR_DATA(IP1_17_15, D13),
719 PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0),
720 PINMUX_IPSR_DATA(IP1_17_15, TANS1),
721 PINMUX_IPSR_DATA(IP1_17_15, PWM2_C),
722 PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1),
723 PINMUX_IPSR_DATA(IP1_19_18, D14),
724 PINMUX_IPSR_MSEL(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0),
725 PINMUX_IPSR_MSEL(IP1_19_18, IIC0_SCL_B, SEL_IIC00_1),
726 PINMUX_IPSR_DATA(IP1_21_20, D15),
727 PINMUX_IPSR_MSEL(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0),
728 PINMUX_IPSR_MSEL(IP1_21_20, IIC0_SDA_B, SEL_IIC00_1),
729 PINMUX_IPSR_DATA(IP1_23_22, A0),
730 PINMUX_IPSR_DATA(IP1_23_22, SCIFB1_SCK),
731 PINMUX_IPSR_DATA(IP1_23_22, PWM3_B),
732 PINMUX_IPSR_DATA(IP1_24, A1),
733 PINMUX_IPSR_DATA(IP1_24, SCIFB1_TXD),
734 PINMUX_IPSR_DATA(IP1_26, A3),
735 PINMUX_IPSR_DATA(IP1_26, SCIFB0_SCK),
736 PINMUX_IPSR_DATA(IP1_27, A4),
737 PINMUX_IPSR_DATA(IP1_27, SCIFB0_TXD),
738 PINMUX_IPSR_DATA(IP1_29_28, A5),
739 PINMUX_IPSR_DATA(IP1_29_28, SCIFB0_RXD),
740 PINMUX_IPSR_DATA(IP1_29_28, PWM4_B),
741 PINMUX_IPSR_DATA(IP1_29_28, TPUTO3_C),
742 PINMUX_IPSR_DATA(IP1_31_30, A6),
743 PINMUX_IPSR_DATA(IP1_31_30, SCIFB0_CTS_N),
744 PINMUX_IPSR_MSEL(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1),
745 PINMUX_IPSR_DATA(IP1_31_30, TPUTO2_C),
748 PINMUX_IPSR_DATA(IP2_1_0, A7),
749 PINMUX_IPSR_DATA(IP2_1_0, SCIFB0_RTS_N),
750 PINMUX_IPSR_MSEL(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1),
751 PINMUX_IPSR_DATA(IP2_3_2, A8),
752 PINMUX_IPSR_MSEL(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0),
753 PINMUX_IPSR_MSEL(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1),
754 PINMUX_IPSR_DATA(IP2_5_4, A9),
755 PINMUX_IPSR_MSEL(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0),
756 PINMUX_IPSR_MSEL(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1),
757 PINMUX_IPSR_DATA(IP2_7_6, A10),
758 PINMUX_IPSR_MSEL(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0),
759 PINMUX_IPSR_MSEL(IP2_7_6, IIC1_SCL_B, SEL_IIC01_1),
760 PINMUX_IPSR_DATA(IP2_9_8, A11),
761 PINMUX_IPSR_MSEL(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0),
762 PINMUX_IPSR_MSEL(IP2_9_8, IIC1_SDA_B, SEL_IIC01_1),
763 PINMUX_IPSR_DATA(IP2_11_10, A12),
764 PINMUX_IPSR_MSEL(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0),
765 PINMUX_IPSR_MSEL(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1),
766 PINMUX_IPSR_DATA(IP2_13_12, A13),
767 PINMUX_IPSR_MSEL(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0),
768 PINMUX_IPSR_MSEL(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1),
769 PINMUX_IPSR_DATA(IP2_15_14, A14),
770 PINMUX_IPSR_MSEL(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0),
771 PINMUX_IPSR_MSEL(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1),
772 PINMUX_IPSR_MSEL(IP2_15_14, DREQ1_N, SEL_LBS_0),
773 PINMUX_IPSR_DATA(IP2_17_16, A15),
774 PINMUX_IPSR_MSEL(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0),
775 PINMUX_IPSR_MSEL(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1),
776 PINMUX_IPSR_MSEL(IP2_17_16, DACK1, SEL_LBS_0),
777 PINMUX_IPSR_DATA(IP2_20_18, A16),
778 PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0),
779 PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1),
780 PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0),
781 PINMUX_IPSR_MSEL(IP2_20_18, VSP, SEL_SPDM_0),
782 PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2),
783 PINMUX_IPSR_DATA(IP2_20_18, TPUTO2_B),
784 PINMUX_IPSR_DATA(IP2_23_21, A17),
785 PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0),
786 PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4),
787 PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1),
788 PINMUX_IPSR_MSEL(IP2_23_21, AVB_AVTP_CAPTURE_B, SEL_AVB_1),
789 PINMUX_IPSR_DATA(IP2_26_24, A18),
790 PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0),
791 PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4),
792 PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1),
793 PINMUX_IPSR_MSEL(IP2_26_24, AVB_AVTP_MATCH_B, SEL_AVB_1),
794 PINMUX_IPSR_DATA(IP2_29_27, A19),
795 PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0),
796 PINMUX_IPSR_DATA(IP2_29_27, PWM4),
797 PINMUX_IPSR_DATA(IP2_29_27, TPUTO2),
798 PINMUX_IPSR_DATA(IP2_29_27, MOUT0),
799 PINMUX_IPSR_DATA(IP2_31_30, A20),
800 PINMUX_IPSR_DATA(IP2_31_30, SPCLK),
801 PINMUX_IPSR_DATA(IP2_29_27, MOUT1),
804 PINMUX_IPSR_DATA(IP3_1_0, A21),
805 PINMUX_IPSR_DATA(IP3_1_0, MOSI_IO0),
806 PINMUX_IPSR_DATA(IP3_1_0, MOUT2),
807 PINMUX_IPSR_DATA(IP3_3_2, A22),
808 PINMUX_IPSR_DATA(IP3_3_2, MISO_IO1),
809 PINMUX_IPSR_DATA(IP3_3_2, MOUT5),
810 PINMUX_IPSR_DATA(IP3_3_2, ATADIR1_N),
811 PINMUX_IPSR_DATA(IP3_5_4, A23),
812 PINMUX_IPSR_DATA(IP3_5_4, IO2),
813 PINMUX_IPSR_DATA(IP3_5_4, MOUT6),
814 PINMUX_IPSR_DATA(IP3_5_4, ATAWR1_N),
815 PINMUX_IPSR_DATA(IP3_7_6, A24),
816 PINMUX_IPSR_DATA(IP3_7_6, IO3),
817 PINMUX_IPSR_DATA(IP3_7_6, EX_WAIT2),
818 PINMUX_IPSR_DATA(IP3_9_8, A25),
819 PINMUX_IPSR_DATA(IP3_9_8, SSL),
820 PINMUX_IPSR_DATA(IP3_9_8, ATARD1_N),
821 PINMUX_IPSR_DATA(IP3_10, CS0_N),
822 PINMUX_IPSR_DATA(IP3_10, VI1_DATA8),
823 PINMUX_IPSR_DATA(IP3_11, CS1_N_A26),
824 PINMUX_IPSR_DATA(IP3_11, VI1_DATA9),
825 PINMUX_IPSR_DATA(IP3_12, EX_CS0_N),
826 PINMUX_IPSR_DATA(IP3_12, VI1_DATA10),
827 PINMUX_IPSR_DATA(IP3_14_13, EX_CS1_N),
828 PINMUX_IPSR_DATA(IP3_14_13, TPUTO3_B),
829 PINMUX_IPSR_DATA(IP3_14_13, SCIFB2_RXD),
830 PINMUX_IPSR_DATA(IP3_14_13, VI1_DATA11),
831 PINMUX_IPSR_DATA(IP3_17_15, EX_CS2_N),
832 PINMUX_IPSR_DATA(IP3_17_15, PWM0),
833 PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2),
834 PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1),
835 PINMUX_IPSR_MSEL(IP3_17_15, RIF0_SYNC, SEL_DR0_0),
836 PINMUX_IPSR_DATA(IP3_17_15, TPUTO3),
837 PINMUX_IPSR_DATA(IP3_17_15, SCIFB2_TXD),
838 PINMUX_IPSR_MSEL(IP3_17_15, SDATA_B, SEL_FSN_1),
839 PINMUX_IPSR_DATA(IP3_20_18, EX_CS3_N),
840 PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0),
841 PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2),
842 PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1),
843 PINMUX_IPSR_MSEL(IP3_20_18, RIF0_CLK, SEL_DR0_0),
844 PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0),
845 PINMUX_IPSR_DATA(IP3_20_18, SCIFB2_SCK),
846 PINMUX_IPSR_MSEL(IP3_20_18, MDATA_B, SEL_FSN_1),
847 PINMUX_IPSR_DATA(IP3_23_21, EX_CS4_N),
848 PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0),
849 PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4),
850 PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1),
851 PINMUX_IPSR_MSEL(IP3_23_21, RIF0_D0, SEL_DR0_0),
852 PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0),
853 PINMUX_IPSR_DATA(IP3_23_21, SCIFB2_CTS_N),
854 PINMUX_IPSR_MSEL(IP3_23_21, SCKZ_B, SEL_FSN_1),
855 PINMUX_IPSR_DATA(IP3_26_24, EX_CS5_N),
856 PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0),
857 PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4),
858 PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1),
859 PINMUX_IPSR_MSEL(IP3_26_24, RIF0_D1, SEL_DR1_0),
860 PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0),
861 PINMUX_IPSR_DATA(IP3_26_24, SCIFB2_RTS_N),
862 PINMUX_IPSR_MSEL(IP3_26_24, STM_N_B, SEL_FSN_1),
863 PINMUX_IPSR_DATA(IP3_29_27, BS_N),
864 PINMUX_IPSR_DATA(IP3_29_27, DRACK0),
865 PINMUX_IPSR_DATA(IP3_29_27, PWM1_C),
866 PINMUX_IPSR_DATA(IP3_29_27, TPUTO0_C),
867 PINMUX_IPSR_DATA(IP3_29_27, ATACS01_N),
868 PINMUX_IPSR_MSEL(IP3_29_27, MTS_N_B, SEL_FSN_1),
869 PINMUX_IPSR_DATA(IP3_30, RD_N),
870 PINMUX_IPSR_DATA(IP3_30, ATACS11_N),
871 PINMUX_IPSR_DATA(IP3_31, RD_WR_N),
872 PINMUX_IPSR_DATA(IP3_31, ATAG1_N),
875 PINMUX_IPSR_DATA(IP4_1_0, EX_WAIT0),
876 PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1),
877 PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0),
878 PINMUX_IPSR_DATA(IP4_1_0, PWMFSW0),
879 PINMUX_IPSR_DATA(IP4_4_2, DU0_DR0),
880 PINMUX_IPSR_DATA(IP4_4_2, LCDOUT16),
881 PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2),
882 PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3),
883 PINMUX_IPSR_DATA(IP4_4_2, CC50_STATE0),
884 PINMUX_IPSR_DATA(IP4_7_5, DU0_DR1),
885 PINMUX_IPSR_DATA(IP4_7_5, LCDOUT17),
886 PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2),
887 PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3),
888 PINMUX_IPSR_DATA(IP4_9_8, CC50_STATE1),
889 PINMUX_IPSR_DATA(IP4_9_8, DU0_DR2),
890 PINMUX_IPSR_DATA(IP4_9_8, LCDOUT18),
891 PINMUX_IPSR_DATA(IP4_9_8, CC50_STATE2),
892 PINMUX_IPSR_DATA(IP4_11_10, DU0_DR3),
893 PINMUX_IPSR_DATA(IP4_11_10, LCDOUT19),
894 PINMUX_IPSR_DATA(IP4_11_10, CC50_STATE3),
895 PINMUX_IPSR_DATA(IP4_13_12, DU0_DR4),
896 PINMUX_IPSR_DATA(IP4_13_12, LCDOUT20),
897 PINMUX_IPSR_DATA(IP4_13_12, CC50_STATE4),
898 PINMUX_IPSR_DATA(IP4_15_14, DU0_DR5),
899 PINMUX_IPSR_DATA(IP4_15_14, LCDOUT21),
900 PINMUX_IPSR_DATA(IP4_15_14, CC50_STATE5),
901 PINMUX_IPSR_DATA(IP4_17_16, DU0_DR6),
902 PINMUX_IPSR_DATA(IP4_17_16, LCDOUT22),
903 PINMUX_IPSR_DATA(IP4_17_16, CC50_STATE6),
904 PINMUX_IPSR_DATA(IP4_19_18, DU0_DR7),
905 PINMUX_IPSR_DATA(IP4_19_18, LCDOUT23),
906 PINMUX_IPSR_DATA(IP4_19_18, CC50_STATE7),
907 PINMUX_IPSR_DATA(IP4_22_20, DU0_DG0),
908 PINMUX_IPSR_DATA(IP4_22_20, LCDOUT8),
909 PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2),
910 PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3),
911 PINMUX_IPSR_DATA(IP4_22_20, CC50_STATE8),
912 PINMUX_IPSR_DATA(IP4_25_23, DU0_DG1),
913 PINMUX_IPSR_DATA(IP4_25_23, LCDOUT9),
914 PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2),
915 PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3),
916 PINMUX_IPSR_DATA(IP4_25_23, CC50_STATE9),
917 PINMUX_IPSR_DATA(IP4_27_26, DU0_DG2),
918 PINMUX_IPSR_DATA(IP4_27_26, LCDOUT10),
919 PINMUX_IPSR_DATA(IP4_27_26, CC50_STATE10),
920 PINMUX_IPSR_DATA(IP4_29_28, DU0_DG3),
921 PINMUX_IPSR_DATA(IP4_29_28, LCDOUT11),
922 PINMUX_IPSR_DATA(IP4_29_28, CC50_STATE11),
923 PINMUX_IPSR_DATA(IP4_31_30, DU0_DG4),
924 PINMUX_IPSR_DATA(IP4_31_30, LCDOUT12),
925 PINMUX_IPSR_DATA(IP4_31_30, CC50_STATE12),
928 PINMUX_IPSR_DATA(IP5_1_0, DU0_DG5),
929 PINMUX_IPSR_DATA(IP5_1_0, LCDOUT13),
930 PINMUX_IPSR_DATA(IP5_1_0, CC50_STATE13),
931 PINMUX_IPSR_DATA(IP5_3_2, DU0_DG6),
932 PINMUX_IPSR_DATA(IP5_3_2, LCDOUT14),
933 PINMUX_IPSR_DATA(IP5_3_2, CC50_STATE14),
934 PINMUX_IPSR_DATA(IP5_5_4, DU0_DG7),
935 PINMUX_IPSR_DATA(IP5_5_4, LCDOUT15),
936 PINMUX_IPSR_DATA(IP5_5_4, CC50_STATE15),
937 PINMUX_IPSR_DATA(IP5_8_6, DU0_DB0),
938 PINMUX_IPSR_DATA(IP5_8_6, LCDOUT0),
939 PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2),
940 PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3),
941 PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2),
942 PINMUX_IPSR_DATA(IP5_8_6, CC50_STATE16),
943 PINMUX_IPSR_DATA(IP5_11_9, DU0_DB1),
944 PINMUX_IPSR_DATA(IP5_11_9, LCDOUT1),
945 PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
946 PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3),
947 PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2),
948 PINMUX_IPSR_DATA(IP5_11_9, CC50_STATE17),
949 PINMUX_IPSR_DATA(IP5_13_12, DU0_DB2),
950 PINMUX_IPSR_DATA(IP5_13_12, LCDOUT2),
951 PINMUX_IPSR_DATA(IP5_13_12, CC50_STATE18),
952 PINMUX_IPSR_DATA(IP5_15_14, DU0_DB3),
953 PINMUX_IPSR_DATA(IP5_15_14, LCDOUT3),
954 PINMUX_IPSR_DATA(IP5_15_14, CC50_STATE19),
955 PINMUX_IPSR_DATA(IP5_17_16, DU0_DB4),
956 PINMUX_IPSR_DATA(IP5_17_16, LCDOUT4),
957 PINMUX_IPSR_DATA(IP5_17_16, CC50_STATE20),
958 PINMUX_IPSR_DATA(IP5_19_18, DU0_DB5),
959 PINMUX_IPSR_DATA(IP5_19_18, LCDOUT5),
960 PINMUX_IPSR_DATA(IP5_19_18, CC50_STATE21),
961 PINMUX_IPSR_DATA(IP5_21_20, DU0_DB6),
962 PINMUX_IPSR_DATA(IP5_21_20, LCDOUT6),
963 PINMUX_IPSR_DATA(IP5_21_20, CC50_STATE22),
964 PINMUX_IPSR_DATA(IP5_23_22, DU0_DB7),
965 PINMUX_IPSR_DATA(IP5_23_22, LCDOUT7),
966 PINMUX_IPSR_DATA(IP5_23_22, CC50_STATE23),
967 PINMUX_IPSR_DATA(IP5_25_24, DU0_DOTCLKIN),
968 PINMUX_IPSR_DATA(IP5_25_24, QSTVA_QVS),
969 PINMUX_IPSR_DATA(IP5_25_24, CC50_STATE24),
970 PINMUX_IPSR_DATA(IP5_27_26, DU0_DOTCLKOUT0),
971 PINMUX_IPSR_DATA(IP5_27_26, QCLK),
972 PINMUX_IPSR_DATA(IP5_27_26, CC50_STATE25),
973 PINMUX_IPSR_DATA(IP5_29_28, DU0_DOTCLKOUT1),
974 PINMUX_IPSR_DATA(IP5_29_28, QSTVB_QVE),
975 PINMUX_IPSR_DATA(IP5_29_28, CC50_STATE26),
976 PINMUX_IPSR_DATA(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC),
977 PINMUX_IPSR_DATA(IP5_31_30, QSTH_QHS),
978 PINMUX_IPSR_DATA(IP5_31_30, CC50_STATE27),
981 PINMUX_IPSR_DATA(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
982 PINMUX_IPSR_DATA(IP6_1_0, QSTB_QHE),
983 PINMUX_IPSR_DATA(IP6_1_0, CC50_STATE28),
984 PINMUX_IPSR_DATA(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
985 PINMUX_IPSR_DATA(IP6_3_2, QCPV_QDE),
986 PINMUX_IPSR_DATA(IP6_3_2, CC50_STATE29),
987 PINMUX_IPSR_DATA(IP6_5_4, DU0_DISP),
988 PINMUX_IPSR_DATA(IP6_5_4, QPOLA),
989 PINMUX_IPSR_DATA(IP6_5_4, CC50_STATE30),
990 PINMUX_IPSR_DATA(IP6_7_6, DU0_CDE),
991 PINMUX_IPSR_DATA(IP6_7_6, QPOLB),
992 PINMUX_IPSR_DATA(IP6_7_6, CC50_STATE31),
993 PINMUX_IPSR_DATA(IP6_8, VI0_CLK),
994 PINMUX_IPSR_DATA(IP6_8, AVB_RX_CLK),
995 PINMUX_IPSR_DATA(IP6_9, VI0_DATA0_VI0_B0),
996 PINMUX_IPSR_DATA(IP6_9, AVB_RX_DV),
997 PINMUX_IPSR_DATA(IP6_10, VI0_DATA1_VI0_B1),
998 PINMUX_IPSR_DATA(IP6_10, AVB_RXD0),
999 PINMUX_IPSR_DATA(IP6_11, VI0_DATA2_VI0_B2),
1000 PINMUX_IPSR_DATA(IP6_11, AVB_RXD1),
1001 PINMUX_IPSR_DATA(IP6_12, VI0_DATA3_VI0_B3),
1002 PINMUX_IPSR_DATA(IP6_12, AVB_RXD2),
1003 PINMUX_IPSR_DATA(IP6_13, VI0_DATA4_VI0_B4),
1004 PINMUX_IPSR_DATA(IP6_13, AVB_RXD3),
1005 PINMUX_IPSR_DATA(IP6_14, VI0_DATA5_VI0_B5),
1006 PINMUX_IPSR_DATA(IP6_14, AVB_RXD4),
1007 PINMUX_IPSR_DATA(IP6_15, VI0_DATA6_VI0_B6),
1008 PINMUX_IPSR_DATA(IP6_15, AVB_RXD5),
1009 PINMUX_IPSR_DATA(IP6_16, VI0_DATA7_VI0_B7),
1010 PINMUX_IPSR_DATA(IP6_16, AVB_RXD6),
1011 PINMUX_IPSR_DATA(IP6_19_17, VI0_CLKENB),
1012 PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
1013 PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
1014 PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2),
1015 PINMUX_IPSR_DATA(IP6_19_17, AVB_RXD7),
1016 PINMUX_IPSR_DATA(IP6_22_20, VI0_FIELD),
1017 PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
1018 PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
1019 PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2),
1020 PINMUX_IPSR_DATA(IP6_22_20, AVB_RX_ER),
1021 PINMUX_IPSR_DATA(IP6_25_23, VI0_HSYNC_N),
1022 PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
1023 PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
1024 PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2),
1025 PINMUX_IPSR_DATA(IP6_25_23, AVB_COL),
1026 PINMUX_IPSR_DATA(IP6_28_26, VI0_VSYNC_N),
1027 PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
1028 PINMUX_IPSR_MSEL(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
1029 PINMUX_IPSR_MSEL(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
1030 PINMUX_IPSR_DATA(IP6_28_26, AVB_TX_EN),
1031 PINMUX_IPSR_MSEL(IP6_31_29, ETH_MDIO, SEL_ETH_0),
1032 PINMUX_IPSR_DATA(IP6_31_29, VI0_G0),
1033 PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
1034 PINMUX_IPSR_MSEL(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3),
1035 PINMUX_IPSR_DATA(IP6_31_29, AVB_TX_CLK),
1036 PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0),
1037 PINMUX_IPSR_MSEL(IP6_31_29, AD_DI, SEL_ADI_0),
1040 PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
1041 PINMUX_IPSR_DATA(IP7_2_0, VI0_G1),
1042 PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
1043 PINMUX_IPSR_MSEL(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3),
1044 PINMUX_IPSR_DATA(IP7_2_0, AVB_TXD0),
1045 PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
1046 PINMUX_IPSR_MSEL(IP7_2_0, AD_DO, SEL_ADI_0),
1047 PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
1048 PINMUX_IPSR_DATA(IP7_5_3, VI0_G2),
1049 PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
1050 PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
1051 PINMUX_IPSR_DATA(IP7_5_3, AVB_TXD1),
1052 PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0),
1053 PINMUX_IPSR_MSEL(IP7_5_3, AD_CLK, SEL_ADI_0),
1054 PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0),
1055 PINMUX_IPSR_DATA(IP7_8_6, VI0_G3),
1056 PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
1057 PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
1058 PINMUX_IPSR_DATA(IP7_8_6, AVB_TXD2),
1059 PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0),
1060 PINMUX_IPSR_MSEL(IP7_8_6, AD_NCS_N, SEL_ADI_0),
1061 PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0),
1062 PINMUX_IPSR_DATA(IP7_11_9, VI0_G4),
1063 PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
1064 PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
1065 PINMUX_IPSR_DATA(IP7_11_9, AVB_TXD3),
1066 PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0),
1067 PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0),
1068 PINMUX_IPSR_DATA(IP7_14_12, VI0_G5),
1069 PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
1070 PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
1071 PINMUX_IPSR_DATA(IP7_14_12, AVB_TXD4),
1072 PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0),
1073 PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
1074 PINMUX_IPSR_DATA(IP7_17_15, VI0_G6),
1075 PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
1076 PINMUX_IPSR_DATA(IP7_17_15, AVB_TXD5),
1077 PINMUX_IPSR_MSEL(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
1078 PINMUX_IPSR_MSEL(IP7_20_18, ETH_TXD1, SEL_ETH_0),
1079 PINMUX_IPSR_DATA(IP7_20_18, VI0_G7),
1080 PINMUX_IPSR_MSEL(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
1081 PINMUX_IPSR_MSEL(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3),
1082 PINMUX_IPSR_DATA(IP7_20_18, AVB_TXD6),
1083 PINMUX_IPSR_MSEL(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
1084 PINMUX_IPSR_MSEL(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
1085 PINMUX_IPSR_DATA(IP7_23_21, VI0_R0),
1086 PINMUX_IPSR_MSEL(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
1087 PINMUX_IPSR_MSEL(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3),
1088 PINMUX_IPSR_DATA(IP7_23_21, AVB_TXD7),
1089 PINMUX_IPSR_MSEL(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
1090 PINMUX_IPSR_MSEL(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
1091 PINMUX_IPSR_DATA(IP7_26_24, VI0_R1),
1092 PINMUX_IPSR_MSEL(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
1093 PINMUX_IPSR_DATA(IP7_26_24, AVB_TX_ER),
1094 PINMUX_IPSR_MSEL(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
1095 PINMUX_IPSR_MSEL(IP7_29_27, ETH_TXD0, SEL_ETH_0),
1096 PINMUX_IPSR_DATA(IP7_29_27, VI0_R2),
1097 PINMUX_IPSR_MSEL(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
1098 PINMUX_IPSR_MSEL(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
1099 PINMUX_IPSR_DATA(IP7_29_27, AVB_GTX_CLK),
1100 PINMUX_IPSR_MSEL(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
1101 PINMUX_IPSR_DATA(IP7_31, DREQ0_N),
1102 PINMUX_IPSR_DATA(IP7_31, SCIFB1_RXD),
1105 PINMUX_IPSR_MSEL(IP8_2_0, ETH_MDC, SEL_ETH_0),
1106 PINMUX_IPSR_DATA(IP8_2_0, VI0_R3),
1107 PINMUX_IPSR_MSEL(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
1108 PINMUX_IPSR_MSEL(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
1109 PINMUX_IPSR_DATA(IP8_2_0, AVB_MDC),
1110 PINMUX_IPSR_MSEL(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
1111 PINMUX_IPSR_MSEL(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
1112 PINMUX_IPSR_DATA(IP8_5_3, VI0_R4),
1113 PINMUX_IPSR_MSEL(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
1114 PINMUX_IPSR_MSEL(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
1115 PINMUX_IPSR_DATA(IP8_5_3, AVB_MDIO),
1116 PINMUX_IPSR_MSEL(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
1117 PINMUX_IPSR_MSEL(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
1118 PINMUX_IPSR_DATA(IP8_8_6, VI0_R5),
1119 PINMUX_IPSR_MSEL(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
1120 PINMUX_IPSR_MSEL(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1121 PINMUX_IPSR_DATA(IP8_5_3, AVB_LINK),
1122 PINMUX_IPSR_MSEL(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
1123 PINMUX_IPSR_DATA(IP8_11_9, HSCIF0_HCTS_N),
1124 PINMUX_IPSR_DATA(IP8_11_9, VI0_R6),
1125 PINMUX_IPSR_MSEL(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
1126 PINMUX_IPSR_MSEL(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
1127 PINMUX_IPSR_DATA(IP8_11_9, AVB_MAGIC),
1128 PINMUX_IPSR_MSEL(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
1129 PINMUX_IPSR_DATA(IP8_14_12, HSCIF0_HRTS_N),
1130 PINMUX_IPSR_DATA(IP8_14_12, VI0_R7),
1131 PINMUX_IPSR_MSEL(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
1132 PINMUX_IPSR_MSEL(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
1133 PINMUX_IPSR_DATA(IP8_14_12, AVB_PHY_INT),
1134 PINMUX_IPSR_MSEL(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
1135 PINMUX_IPSR_MSEL(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
1136 PINMUX_IPSR_MSEL(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
1137 PINMUX_IPSR_DATA(IP8_16_15, AVB_CRS),
1138 PINMUX_IPSR_MSEL(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
1139 PINMUX_IPSR_MSEL(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
1140 PINMUX_IPSR_MSEL(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
1141 PINMUX_IPSR_DATA(IP8_19_17, PWM5),
1142 PINMUX_IPSR_MSEL(IP8_19_17, TCLK1_B, SEL_TMU_1),
1143 PINMUX_IPSR_DATA(IP8_19_17, AVB_GTXREFCLK),
1144 PINMUX_IPSR_MSEL(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
1145 PINMUX_IPSR_DATA(IP8_19_17, TPUTO0_B),
1146 PINMUX_IPSR_MSEL(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
1147 PINMUX_IPSR_MSEL(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
1148 PINMUX_IPSR_DATA(IP8_22_20, TPUTO0),
1149 PINMUX_IPSR_MSEL(IP8_22_20, CAN_CLK, SEL_CAN_0),
1150 PINMUX_IPSR_DATA(IP8_22_20, DVC_MUTE),
1151 PINMUX_IPSR_MSEL(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
1152 PINMUX_IPSR_MSEL(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
1153 PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
1154 PINMUX_IPSR_DATA(IP8_25_23, PWM5_B),
1155 PINMUX_IPSR_DATA(IP8_25_23, DU1_DR0),
1156 PINMUX_IPSR_MSEL(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1),
1157 PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
1158 PINMUX_IPSR_DATA(IP8_25_23, TPUTO1_B),
1159 PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
1160 PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
1161 PINMUX_IPSR_DATA(IP8_28_26, IRQ5),
1162 PINMUX_IPSR_DATA(IP8_28_26, DU1_DR1),
1163 PINMUX_IPSR_MSEL(IP8_28_26, RIF1_CLK_B, SEL_DR2_1),
1164 PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
1165 PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2),
1166 PINMUX_IPSR_DATA(IP8_31_29, MSIOF0_RXD),
1167 PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
1168 PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
1169 PINMUX_IPSR_DATA(IP8_31_29, DU1_DR2),
1170 PINMUX_IPSR_MSEL(IP8_31_29, RIF1_D0_B, SEL_DR2_1),
1171 PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
1172 PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2),
1173 PINMUX_IPSR_MSEL(IP8_31_29, RDS_CLK, SEL_RDS_0),
1176 PINMUX_IPSR_DATA(IP9_2_0, MSIOF0_TXD),
1177 PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0),
1178 PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2),
1179 PINMUX_IPSR_DATA(IP9_2_0, DU1_DR3),
1180 PINMUX_IPSR_MSEL(IP9_2_0, RIF1_D1_B, SEL_DR3_1),
1181 PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3),
1182 PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2),
1183 PINMUX_IPSR_MSEL(IP9_2_0, RDS_DATA, SEL_RDS_0),
1184 PINMUX_IPSR_DATA(IP9_5_3, MSIOF0_SCK),
1185 PINMUX_IPSR_DATA(IP9_5_3, IRQ0),
1186 PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0),
1187 PINMUX_IPSR_DATA(IP9_5_3, DU1_DR4),
1188 PINMUX_IPSR_MSEL(IP9_5_3, RIF1_SYNC, SEL_DR2_0),
1189 PINMUX_IPSR_DATA(IP9_5_3, TPUTO1_C),
1190 PINMUX_IPSR_DATA(IP9_8_6, MSIOF0_SYNC),
1191 PINMUX_IPSR_DATA(IP9_8_6, PWM1),
1192 PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0),
1193 PINMUX_IPSR_DATA(IP9_8_6, DU1_DR5),
1194 PINMUX_IPSR_MSEL(IP9_8_6, RIF1_CLK, SEL_DR2_0),
1195 PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1),
1196 PINMUX_IPSR_DATA(IP9_11_9, MSIOF0_SS1),
1197 PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0),
1198 PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0),
1199 PINMUX_IPSR_DATA(IP9_11_9, DU1_DR6),
1200 PINMUX_IPSR_MSEL(IP9_11_9, RIF1_D0, SEL_DR2_0),
1201 PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1),
1202 PINMUX_IPSR_MSEL(IP9_11_9, RDS_CLK_B, SEL_RDS_1),
1203 PINMUX_IPSR_DATA(IP9_14_12, MSIOF0_SS2),
1204 PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0),
1205 PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0),
1206 PINMUX_IPSR_DATA(IP9_14_12, DU1_DR7),
1207 PINMUX_IPSR_MSEL(IP9_14_12, RIF1_D1, SEL_DR3_0),
1208 PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1),
1209 PINMUX_IPSR_MSEL(IP9_14_12, RDS_DATA_B, SEL_RDS_1),
1210 PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0),
1211 PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0),
1212 PINMUX_IPSR_DATA(IP9_16_15, PWM6),
1213 PINMUX_IPSR_DATA(IP9_16_15, DU1_DG0),
1214 PINMUX_IPSR_MSEL(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0),
1215 PINMUX_IPSR_MSEL(IP9_18_17, I2C4_SDA, SEL_I2C04_0),
1216 PINMUX_IPSR_DATA(IP9_18_17, TPUTO1),
1217 PINMUX_IPSR_DATA(IP9_18_17, DU1_DG1),
1218 PINMUX_IPSR_DATA(IP9_21_19, HSCIF1_HSCK),
1219 PINMUX_IPSR_DATA(IP9_21_19, PWM2),
1220 PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0),
1221 PINMUX_IPSR_DATA(IP9_21_19, DU1_DG2),
1222 PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1),
1223 PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1),
1224 PINMUX_IPSR_MSEL(IP9_21_19, VSP_B, SEL_SPDM_1),
1225 PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0),
1226 PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0),
1227 PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0),
1228 PINMUX_IPSR_DATA(IP9_24_22, DU1_DG3),
1229 PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1),
1230 PINMUX_IPSR_DATA(IP9_24_22, CAN_DEBUG_HW_TRIGGER),
1231 PINMUX_IPSR_DATA(IP9_24_22, CC50_STATE32),
1232 PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0),
1233 PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0),
1234 PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0),
1235 PINMUX_IPSR_DATA(IP9_27_25, DU1_DG4),
1236 PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1),
1237 PINMUX_IPSR_DATA(IP9_27_25, CAN_STEP0),
1238 PINMUX_IPSR_DATA(IP9_27_25, CC50_STATE33),
1239 PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0),
1240 PINMUX_IPSR_DATA(IP9_30_28, PWM3),
1241 PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0),
1242 PINMUX_IPSR_DATA(IP9_30_28, DU1_DG5),
1243 PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1),
1244 PINMUX_IPSR_DATA(IP9_30_28, CAN_TXCLK),
1245 PINMUX_IPSR_DATA(IP9_30_28, CC50_STATE34),
1248 PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0),
1249 PINMUX_IPSR_MSEL(IP10_2_0, IIC0_SCL, SEL_IIC00_0),
1250 PINMUX_IPSR_DATA(IP10_2_0, DU1_DG6),
1251 PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1),
1252 PINMUX_IPSR_DATA(IP10_2_0, CAN_DEBUGOUT0),
1253 PINMUX_IPSR_DATA(IP10_2_0, CC50_STATE35),
1254 PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0),
1255 PINMUX_IPSR_MSEL(IP10_5_3, IIC0_SDA, SEL_IIC00_0),
1256 PINMUX_IPSR_DATA(IP10_5_3, DU1_DG7),
1257 PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1),
1258 PINMUX_IPSR_DATA(IP10_5_3, CAN_DEBUGOUT1),
1259 PINMUX_IPSR_DATA(IP10_5_3, CC50_STATE36),
1260 PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0),
1261 PINMUX_IPSR_MSEL(IP10_8_6, IIC1_SCL, SEL_IIC01_0),
1262 PINMUX_IPSR_DATA(IP10_8_6, DU1_DB0),
1263 PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1),
1264 PINMUX_IPSR_DATA(IP10_8_6, USB0_EXTLP),
1265 PINMUX_IPSR_DATA(IP10_8_6, CAN_DEBUGOUT2),
1266 PINMUX_IPSR_DATA(IP10_8_6, CC50_STATE37),
1267 PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0),
1268 PINMUX_IPSR_MSEL(IP10_11_9, IIC1_SDA, SEL_IIC01_0),
1269 PINMUX_IPSR_DATA(IP10_11_9, DU1_DB1),
1270 PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1),
1271 PINMUX_IPSR_DATA(IP10_11_9, USB0_OVC1),
1272 PINMUX_IPSR_DATA(IP10_11_9, CAN_DEBUGOUT3),
1273 PINMUX_IPSR_DATA(IP10_11_9, CC50_STATE38),
1274 PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0),
1275 PINMUX_IPSR_DATA(IP10_14_12, IRQ1),
1276 PINMUX_IPSR_DATA(IP10_14_12, DU1_DB2),
1277 PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1),
1278 PINMUX_IPSR_DATA(IP10_14_12, USB0_IDIN),
1279 PINMUX_IPSR_DATA(IP10_14_12, CAN_DEBUGOUT4),
1280 PINMUX_IPSR_DATA(IP10_14_12, CC50_STATE39),
1281 PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0),
1282 PINMUX_IPSR_DATA(IP10_17_15, IRQ2),
1283 PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3),
1284 PINMUX_IPSR_DATA(IP10_17_15, DU1_DB3),
1285 PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1),
1286 PINMUX_IPSR_DATA(IP10_17_15, TANS2),
1287 PINMUX_IPSR_DATA(IP10_17_15, CAN_DEBUGOUT5),
1288 PINMUX_IPSR_DATA(IP10_17_15, CC50_OSCOUT),
1289 PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0),
1290 PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4),
1291 PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3),
1292 PINMUX_IPSR_DATA(IP10_20_18, DU1_DB4),
1293 PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2),
1294 PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1),
1295 PINMUX_IPSR_DATA(IP10_20_18, CAN_DEBUGOUT6),
1296 PINMUX_IPSR_MSEL(IP10_20_18, RDS_CLK_C, SEL_RDS_2),
1297 PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0),
1298 PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4),
1299 PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3),
1300 PINMUX_IPSR_DATA(IP10_23_21, DU1_DB5),
1301 PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2),
1302 PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1),
1303 PINMUX_IPSR_DATA(IP10_23_21, CAN_DEBUGOUT7),
1304 PINMUX_IPSR_MSEL(IP10_23_21, RDS_DATA_C, SEL_RDS_2),
1305 PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0),
1306 PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0),
1307 PINMUX_IPSR_DATA(IP10_26_24, DU1_DB6),
1308 PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2),
1309 PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1),
1310 PINMUX_IPSR_DATA(IP10_26_24, CAN_DEBUGOUT8),
1311 PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0),
1312 PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0),
1313 PINMUX_IPSR_DATA(IP10_29_27, DU1_DB7),
1314 PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2),
1315 PINMUX_IPSR_DATA(IP10_29_27, CAN_DEBUGOUT9),
1316 PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0),
1317 PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0),
1318 PINMUX_IPSR_DATA(IP10_31_30, DU1_DOTCLKIN),
1319 PINMUX_IPSR_DATA(IP10_31_30, CAN_DEBUGOUT10),
1322 PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0),
1323 PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1324 PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
1325 PINMUX_IPSR_DATA(IP11_2_0, DU1_DOTCLKOUT0),
1326 PINMUX_IPSR_DATA(IP11_2_0, CAN_DEBUGOUT11),
1327 PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
1328 PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
1329 PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
1330 PINMUX_IPSR_DATA(IP11_5_3, DU1_DOTCLKOUT1),
1331 PINMUX_IPSR_DATA(IP11_5_3, CAN_DEBUGOUT12),
1332 PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
1333 PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
1334 PINMUX_IPSR_DATA(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
1335 PINMUX_IPSR_DATA(IP11_7_6, CAN_DEBUGOUT13),
1336 PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0),
1337 PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
1338 PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
1339 PINMUX_IPSR_DATA(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
1340 PINMUX_IPSR_DATA(IP11_10_8, CAN_DEBUGOUT14),
1341 PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
1342 PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
1343 PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
1344 PINMUX_IPSR_DATA(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1345 PINMUX_IPSR_DATA(IP11_13_11, CAN_DEBUGOUT15),
1346 PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
1347 PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
1348 PINMUX_IPSR_MSEL(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2),
1349 PINMUX_IPSR_DATA(IP11_15_14, DU1_DISP),
1350 PINMUX_IPSR_MSEL(IP11_17_16, SSI_WS78, SEL_SSI7_0),
1351 PINMUX_IPSR_MSEL(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
1352 PINMUX_IPSR_MSEL(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2),
1353 PINMUX_IPSR_DATA(IP11_17_16, DU1_CDE),
1354 PINMUX_IPSR_MSEL(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
1355 PINMUX_IPSR_MSEL(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
1356 PINMUX_IPSR_DATA(IP11_20_18, IRQ8),
1357 PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
1358 PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
1359 PINMUX_IPSR_DATA(IP11_20_18, PCMOE_N),
1360 PINMUX_IPSR_DATA(IP11_23_21, SSI_SCK0129),
1361 PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
1362 PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
1363 PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1),
1364 PINMUX_IPSR_MSEL(IP11_23_21, AD_DI_B, SEL_ADI_1),
1365 PINMUX_IPSR_DATA(IP11_23_21, PCMWE_N),
1366 PINMUX_IPSR_DATA(IP11_26_24, SSI_WS0129),
1367 PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
1368 PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
1369 PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
1370 PINMUX_IPSR_MSEL(IP11_26_24, AD_DO_B, SEL_ADI_1),
1371 PINMUX_IPSR_DATA(IP11_29_27, SSI_SDATA0),
1372 PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
1373 PINMUX_IPSR_DATA(IP11_29_27, PWM0_B),
1374 PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1),
1375 PINMUX_IPSR_MSEL(IP11_29_27, AD_CLK_B, SEL_ADI_1),
1378 PINMUX_IPSR_DATA(IP12_2_0, SSI_SCK34),
1379 PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1),
1380 PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2),
1381 PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1),
1382 PINMUX_IPSR_MSEL(IP12_2_0, AD_NCS_N_B, SEL_ADI_1),
1383 PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1),
1384 PINMUX_IPSR_DATA(IP12_5_3, SSI_WS34),
1385 PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1),
1386 PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2),
1387 PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1),
1388 PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2),
1389 PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1),
1390 PINMUX_IPSR_DATA(IP12_8_6, SSI_SDATA3),
1391 PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1),
1392 PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2),
1393 PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1),
1394 PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2),
1395 PINMUX_IPSR_DATA(IP12_8_6, DREQ2_N),
1396 PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0),
1397 PINMUX_IPSR_DATA(IP12_10_9, MLB_CLK),
1398 PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1),
1399 PINMUX_IPSR_DATA(IP12_10_9, IRD_TX),
1400 PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0),
1401 PINMUX_IPSR_DATA(IP12_12_11, MLB_SIG),
1402 PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1),
1403 PINMUX_IPSR_DATA(IP12_12_11, IRD_RX),
1404 PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0),
1405 PINMUX_IPSR_DATA(IP12_14_13, MLB_DAT),
1406 PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1),
1407 PINMUX_IPSR_DATA(IP12_14_13, IRD_SCK),
1408 PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0),
1409 PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1),
1410 PINMUX_IPSR_DATA(IP12_17_15, PWM1_B),
1411 PINMUX_IPSR_DATA(IP12_17_15, IRQ9),
1412 PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0),
1413 PINMUX_IPSR_DATA(IP12_17_15, DACK2),
1414 PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1),
1415 PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0),
1416 PINMUX_IPSR_MSEL(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1),
1417 PINMUX_IPSR_MSEL(IP12_20_18, IIC1_SCL_C, SEL_IIC01_2),
1418 PINMUX_IPSR_DATA(IP12_20_18, VI1_CLK),
1419 PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3),
1420 PINMUX_IPSR_MSEL(IP12_20_18, AVB_AVTP_CAPTURE, SEL_AVB_0),
1421 PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1),
1422 PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0),
1423 PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1),
1424 PINMUX_IPSR_MSEL(IP12_23_21, IIC1_SDA_C, SEL_IIC01_2),
1425 PINMUX_IPSR_DATA(IP12_23_21, VI1_DATA0),
1426 PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3),
1427 PINMUX_IPSR_MSEL(IP12_23_21, AVB_AVTP_MATCH, SEL_AVB_0),
1428 PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1),
1429 PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0),
1430 PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),
1431 PINMUX_IPSR_DATA(IP12_26_24, VI1_DATA1),
1432 PINMUX_IPSR_MSEL(IP12_26_24, SDATA, SEL_FSN_0),
1433 PINMUX_IPSR_DATA(IP12_26_24, ATAG0_N),
1434 PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),
1435 PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0),
1436 PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),
1437 PINMUX_IPSR_DATA(IP12_29_27, VI1_DATA2),
1438 PINMUX_IPSR_MSEL(IP12_29_27, MDATA, SEL_FSN_0),
1439 PINMUX_IPSR_DATA(IP12_29_27, ATAWR0_N),
1440 PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),
1443 PINMUX_IPSR_MSEL(IP13_2_0, SSI_WS2, SEL_SSI2_0),
1444 PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1),
1445 PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3),
1446 PINMUX_IPSR_DATA(IP13_2_0, VI1_DATA3),
1447 PINMUX_IPSR_MSEL(IP13_2_0, SCKZ, SEL_FSN_0),
1448 PINMUX_IPSR_DATA(IP13_2_0, ATACS00_N),
1449 PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1),
1450 PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0),
1451 PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1),
1452 PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3),
1453 PINMUX_IPSR_DATA(IP13_5_3, VI1_DATA4),
1454 PINMUX_IPSR_MSEL(IP13_5_3, STM_N, SEL_FSN_0),
1455 PINMUX_IPSR_DATA(IP13_5_3, ATACS10_N),
1456 PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1),
1457 PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0),
1458 PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1),
1459 PINMUX_IPSR_DATA(IP13_8_6, PWM2_B),
1460 PINMUX_IPSR_DATA(IP13_8_6, VI1_DATA5),
1461 PINMUX_IPSR_MSEL(IP13_8_6, MTS_N, SEL_FSN_0),
1462 PINMUX_IPSR_DATA(IP13_8_6, EX_WAIT1),
1463 PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1),
1464 PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0),
1465 PINMUX_IPSR_MSEL(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1),
1466 PINMUX_IPSR_MSEL(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4),
1467 PINMUX_IPSR_DATA(IP13_11_9, VI1_DATA6),
1468 PINMUX_IPSR_DATA(IP13_11_9, ATARD0_N),
1469 PINMUX_IPSR_MSEL(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1),
1470 PINMUX_IPSR_MSEL(IP13_14_12, SSI_SDATA9, SEL_SSI9_0),
1471 PINMUX_IPSR_MSEL(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1),
1472 PINMUX_IPSR_MSEL(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4),
1473 PINMUX_IPSR_DATA(IP13_14_12, VI1_DATA7),
1474 PINMUX_IPSR_DATA(IP13_14_12, ATADIR0_N),
1475 PINMUX_IPSR_MSEL(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1),
1476 PINMUX_IPSR_MSEL(IP13_17_15, AUDIO_CLKA, SEL_ADG_0),
1477 PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1),
1478 PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3),
1479 PINMUX_IPSR_DATA(IP13_17_15, VI1_CLKENB),
1480 PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2),
1481 PINMUX_IPSR_MSEL(IP13_17_15, RIF0_SYNC_B, SEL_DR0_1),
1482 PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1),
1483 PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0),
1484 PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1),
1485 PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3),
1486 PINMUX_IPSR_DATA(IP13_20_18, VI1_FIELD),
1487 PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2),
1488 PINMUX_IPSR_MSEL(IP13_20_18, RIF0_CLK_B, SEL_DR0_1),
1489 PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4),
1490 PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1),
1491 PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0),
1492 PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1),
1493 PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3),
1494 PINMUX_IPSR_DATA(IP13_23_21, VI1_HSYNC_N),
1495 PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2),
1496 PINMUX_IPSR_MSEL(IP13_23_21, RIF0_D0_B, SEL_DR0_1),
1497 PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4),
1498 PINMUX_IPSR_MSEL(IP13_23_21, RDS_CLK_D, SEL_RDS_3),
1499 PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0),
1500 PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1),
1501 PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3),
1502 PINMUX_IPSR_DATA(IP13_26_24, VI1_VSYNC_N),
1503 PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2),
1504 PINMUX_IPSR_MSEL(IP13_26_24, RIF0_D1_B, SEL_DR1_1),
1505 PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4),
1506 PINMUX_IPSR_MSEL(IP13_26_24, RDS_DATA_D, SEL_RDS_3),
1509 static const struct sh_pfc_pin pinmux_pins[] = {
1510 PINMUX_GPIO_GP_ALL(),
1513 /* - ETH -------------------------------------------------------------------- */
1514 static const unsigned int eth_link_pins[] = {
1518 static const unsigned int eth_link_mux[] = {
1521 static const unsigned int eth_magic_pins[] = {
1525 static const unsigned int eth_magic_mux[] = {
1528 static const unsigned int eth_mdio_pins[] = {
1530 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 13),
1532 static const unsigned int eth_mdio_mux[] = {
1533 ETH_MDC_MARK, ETH_MDIO_MARK,
1535 static const unsigned int eth_rmii_pins[] = {
1536 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1537 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 15),
1538 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 20),
1539 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 19),
1541 static const unsigned int eth_rmii_mux[] = {
1542 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1543 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
1545 static const unsigned int eth_link_b_pins[] = {
1549 static const unsigned int eth_link_b_mux[] = {
1552 static const unsigned int eth_magic_b_pins[] = {
1556 static const unsigned int eth_magic_b_mux[] = {
1559 static const unsigned int eth_mdio_b_pins[] = {
1561 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 10),
1563 static const unsigned int eth_mdio_b_mux[] = {
1564 ETH_MDC_B_MARK, ETH_MDIO_B_MARK,
1566 static const unsigned int eth_rmii_b_pins[] = {
1567 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1568 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 12),
1569 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 17),
1570 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 16),
1572 static const unsigned int eth_rmii_b_mux[] = {
1573 ETH_RXD0_B_MARK, ETH_RXD1_B_MARK, ETH_RX_ER_B_MARK, ETH_CRS_DV_B_MARK,
1574 ETH_TXD0_B_MARK, ETH_TXD1_B_MARK, ETH_TX_EN_B_MARK, ETH_REFCLK_B_MARK,
1576 /* - HSCIF0 ----------------------------------------------------------------- */
1577 static const unsigned int hscif0_data_pins[] = {
1579 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1581 static const unsigned int hscif0_data_mux[] = {
1582 HSCIF0_HRX_MARK, HSCIF0_HTX_MARK,
1584 static const unsigned int hscif0_clk_pins[] = {
1588 static const unsigned int hscif0_clk_mux[] = {
1591 static const unsigned int hscif0_ctrl_pins[] = {
1593 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
1595 static const unsigned int hscif0_ctrl_mux[] = {
1596 HSCIF0_HRTS_N_MARK, HSCIF0_HCTS_N_MARK,
1598 static const unsigned int hscif0_data_b_pins[] = {
1600 RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31),
1602 static const unsigned int hscif0_data_b_mux[] = {
1603 HSCIF0_HRX_B_MARK, HSCIF0_HTX_B_MARK,
1605 static const unsigned int hscif0_clk_b_pins[] = {
1609 static const unsigned int hscif0_clk_b_mux[] = {
1612 /* - HSCIF1 ----------------------------------------------------------------- */
1613 static const unsigned int hscif1_data_pins[] = {
1615 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1617 static const unsigned int hscif1_data_mux[] = {
1618 HSCIF1_HRX_MARK, HSCIF1_HTX_MARK,
1620 static const unsigned int hscif1_clk_pins[] = {
1624 static const unsigned int hscif1_clk_mux[] = {
1627 static const unsigned int hscif1_ctrl_pins[] = {
1629 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
1631 static const unsigned int hscif1_ctrl_mux[] = {
1632 HSCIF1_HRTS_N_MARK, HSCIF1_HCTS_N_MARK,
1634 static const unsigned int hscif1_data_b_pins[] = {
1636 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1638 static const unsigned int hscif1_data_b_mux[] = {
1639 HSCIF1_HRX_B_MARK, HSCIF1_HTX_B_MARK,
1641 static const unsigned int hscif1_ctrl_b_pins[] = {
1643 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
1645 static const unsigned int hscif1_ctrl_b_mux[] = {
1646 HSCIF1_HRTS_N_B_MARK, HSCIF1_HCTS_N_B_MARK,
1648 /* - HSCIF2 ----------------------------------------------------------------- */
1649 static const unsigned int hscif2_data_pins[] = {
1651 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
1653 static const unsigned int hscif2_data_mux[] = {
1654 HSCIF2_HRX_MARK, HSCIF2_HTX_MARK,
1656 static const unsigned int hscif2_clk_pins[] = {
1660 static const unsigned int hscif2_clk_mux[] = {
1663 static const unsigned int hscif2_ctrl_pins[] = {
1665 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
1667 static const unsigned int hscif2_ctrl_mux[] = {
1668 HSCIF2_HRTS_N_MARK, HSCIF2_HCTS_N_MARK,
1670 /* - I2C0 ------------------------------------------------------------------- */
1671 static const unsigned int i2c0_pins[] = {
1673 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
1675 static const unsigned int i2c0_mux[] = {
1676 I2C0_SCL_MARK, I2C0_SDA_MARK,
1678 static const unsigned int i2c0_b_pins[] = {
1680 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
1682 static const unsigned int i2c0_b_mux[] = {
1683 I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
1685 static const unsigned int i2c0_c_pins[] = {
1687 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1689 static const unsigned int i2c0_c_mux[] = {
1690 I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
1692 static const unsigned int i2c0_d_pins[] = {
1694 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
1696 static const unsigned int i2c0_d_mux[] = {
1697 I2C0_SCL_D_MARK, I2C0_SDA_D_MARK,
1699 static const unsigned int i2c0_e_pins[] = {
1701 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
1703 static const unsigned int i2c0_e_mux[] = {
1704 I2C0_SCL_E_MARK, I2C0_SDA_E_MARK,
1706 /* - I2C1 ------------------------------------------------------------------- */
1707 static const unsigned int i2c1_pins[] = {
1709 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
1711 static const unsigned int i2c1_mux[] = {
1712 I2C1_SCL_MARK, I2C1_SDA_MARK,
1714 static const unsigned int i2c1_b_pins[] = {
1716 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
1718 static const unsigned int i2c1_b_mux[] = {
1719 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
1721 static const unsigned int i2c1_c_pins[] = {
1723 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1725 static const unsigned int i2c1_c_mux[] = {
1726 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
1728 static const unsigned int i2c1_d_pins[] = {
1730 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
1732 static const unsigned int i2c1_d_mux[] = {
1733 I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
1735 static const unsigned int i2c1_e_pins[] = {
1737 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
1739 static const unsigned int i2c1_e_mux[] = {
1740 I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
1742 /* - I2C2 ------------------------------------------------------------------- */
1743 static const unsigned int i2c2_pins[] = {
1745 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
1747 static const unsigned int i2c2_mux[] = {
1748 I2C2_SCL_MARK, I2C2_SDA_MARK,
1750 static const unsigned int i2c2_b_pins[] = {
1752 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
1754 static const unsigned int i2c2_b_mux[] = {
1755 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
1757 static const unsigned int i2c2_c_pins[] = {
1759 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1761 static const unsigned int i2c2_c_mux[] = {
1762 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
1764 static const unsigned int i2c2_d_pins[] = {
1766 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1768 static const unsigned int i2c2_d_mux[] = {
1769 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
1771 static const unsigned int i2c2_e_pins[] = {
1773 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
1775 static const unsigned int i2c2_e_mux[] = {
1776 I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
1778 /* - I2C3 ------------------------------------------------------------------- */
1779 static const unsigned int i2c3_pins[] = {
1781 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1783 static const unsigned int i2c3_mux[] = {
1784 I2C3_SCL_MARK, I2C3_SDA_MARK,
1786 static const unsigned int i2c3_b_pins[] = {
1788 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
1790 static const unsigned int i2c3_b_mux[] = {
1791 I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
1793 static const unsigned int i2c3_c_pins[] = {
1795 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
1797 static const unsigned int i2c3_c_mux[] = {
1798 I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
1800 static const unsigned int i2c3_d_pins[] = {
1802 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1804 static const unsigned int i2c3_d_mux[] = {
1805 I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
1807 static const unsigned int i2c3_e_pins[] = {
1809 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
1811 static const unsigned int i2c3_e_mux[] = {
1812 I2C3_SCL_E_MARK, I2C3_SDA_E_MARK,
1814 /* - I2C4 ------------------------------------------------------------------- */
1815 static const unsigned int i2c4_pins[] = {
1817 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1819 static const unsigned int i2c4_mux[] = {
1820 I2C4_SCL_MARK, I2C4_SDA_MARK,
1822 static const unsigned int i2c4_b_pins[] = {
1824 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
1826 static const unsigned int i2c4_b_mux[] = {
1827 I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
1829 static const unsigned int i2c4_c_pins[] = {
1831 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
1833 static const unsigned int i2c4_c_mux[] = {
1834 I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
1836 static const unsigned int i2c4_d_pins[] = {
1838 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
1840 static const unsigned int i2c4_d_mux[] = {
1841 I2C4_SCL_D_MARK, I2C4_SDA_D_MARK,
1843 static const unsigned int i2c4_e_pins[] = {
1845 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
1847 static const unsigned int i2c4_e_mux[] = {
1848 I2C4_SCL_E_MARK, I2C4_SDA_E_MARK,
1850 /* - INTC ------------------------------------------------------------------- */
1851 static const unsigned int intc_irq0_pins[] = {
1855 static const unsigned int intc_irq0_mux[] = {
1858 static const unsigned int intc_irq1_pins[] = {
1862 static const unsigned int intc_irq1_mux[] = {
1865 static const unsigned int intc_irq2_pins[] = {
1869 static const unsigned int intc_irq2_mux[] = {
1872 static const unsigned int intc_irq3_pins[] = {
1876 static const unsigned int intc_irq3_mux[] = {
1879 static const unsigned int intc_irq4_pins[] = {
1883 static const unsigned int intc_irq4_mux[] = {
1886 static const unsigned int intc_irq5_pins[] = {
1890 static const unsigned int intc_irq5_mux[] = {
1893 static const unsigned int intc_irq6_pins[] = {
1897 static const unsigned int intc_irq6_mux[] = {
1900 static const unsigned int intc_irq7_pins[] = {
1904 static const unsigned int intc_irq7_mux[] = {
1907 static const unsigned int intc_irq8_pins[] = {
1911 static const unsigned int intc_irq8_mux[] = {
1914 static const unsigned int intc_irq9_pins[] = {
1918 static const unsigned int intc_irq9_mux[] = {
1921 /* - MMCIF ------------------------------------------------------------------ */
1922 static const unsigned int mmc_data1_pins[] = {
1926 static const unsigned int mmc_data1_mux[] = {
1929 static const unsigned int mmc_data4_pins[] = {
1931 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
1932 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
1934 static const unsigned int mmc_data4_mux[] = {
1935 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
1937 static const unsigned int mmc_data8_pins[] = {
1939 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
1940 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
1941 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
1942 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
1944 static const unsigned int mmc_data8_mux[] = {
1945 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
1946 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
1948 static const unsigned int mmc_ctrl_pins[] = {
1950 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
1952 static const unsigned int mmc_ctrl_mux[] = {
1953 MMC_CLK_MARK, MMC_CMD_MARK,
1955 /* - MSIOF0 ----------------------------------------------------------------- */
1956 static const unsigned int msiof0_clk_pins[] = {
1960 static const unsigned int msiof0_clk_mux[] = {
1963 static const unsigned int msiof0_sync_pins[] = {
1967 static const unsigned int msiof0_sync_mux[] = {
1970 static const unsigned int msiof0_ss1_pins[] = {
1974 static const unsigned int msiof0_ss1_mux[] = {
1977 static const unsigned int msiof0_ss2_pins[] = {
1981 static const unsigned int msiof0_ss2_mux[] = {
1984 static const unsigned int msiof0_rx_pins[] = {
1988 static const unsigned int msiof0_rx_mux[] = {
1991 static const unsigned int msiof0_tx_pins[] = {
1995 static const unsigned int msiof0_tx_mux[] = {
1998 /* - MSIOF1 ----------------------------------------------------------------- */
1999 static const unsigned int msiof1_clk_pins[] = {
2003 static const unsigned int msiof1_clk_mux[] = {
2006 static const unsigned int msiof1_sync_pins[] = {
2010 static const unsigned int msiof1_sync_mux[] = {
2013 static const unsigned int msiof1_ss1_pins[] = {
2017 static const unsigned int msiof1_ss1_mux[] = {
2020 static const unsigned int msiof1_ss2_pins[] = {
2024 static const unsigned int msiof1_ss2_mux[] = {
2027 static const unsigned int msiof1_rx_pins[] = {
2031 static const unsigned int msiof1_rx_mux[] = {
2034 static const unsigned int msiof1_tx_pins[] = {
2038 static const unsigned int msiof1_tx_mux[] = {
2041 static const unsigned int msiof1_clk_b_pins[] = {
2045 static const unsigned int msiof1_clk_b_mux[] = {
2048 static const unsigned int msiof1_sync_b_pins[] = {
2052 static const unsigned int msiof1_sync_b_mux[] = {
2055 static const unsigned int msiof1_ss1_b_pins[] = {
2059 static const unsigned int msiof1_ss1_b_mux[] = {
2062 static const unsigned int msiof1_ss2_b_pins[] = {
2066 static const unsigned int msiof1_ss2_b_mux[] = {
2069 static const unsigned int msiof1_rx_b_pins[] = {
2073 static const unsigned int msiof1_rx_b_mux[] = {
2076 static const unsigned int msiof1_tx_b_pins[] = {
2080 static const unsigned int msiof1_tx_b_mux[] = {
2083 /* - MSIOF2 ----------------------------------------------------------------- */
2084 static const unsigned int msiof2_clk_pins[] = {
2088 static const unsigned int msiof2_clk_mux[] = {
2091 static const unsigned int msiof2_sync_pins[] = {
2095 static const unsigned int msiof2_sync_mux[] = {
2098 static const unsigned int msiof2_ss1_pins[] = {
2102 static const unsigned int msiof2_ss1_mux[] = {
2105 static const unsigned int msiof2_ss2_pins[] = {
2109 static const unsigned int msiof2_ss2_mux[] = {
2112 static const unsigned int msiof2_rx_pins[] = {
2116 static const unsigned int msiof2_rx_mux[] = {
2119 static const unsigned int msiof2_tx_pins[] = {
2123 static const unsigned int msiof2_tx_mux[] = {
2126 static const unsigned int msiof2_clk_b_pins[] = {
2130 static const unsigned int msiof2_clk_b_mux[] = {
2133 static const unsigned int msiof2_sync_b_pins[] = {
2137 static const unsigned int msiof2_sync_b_mux[] = {
2140 static const unsigned int msiof2_ss1_b_pins[] = {
2144 static const unsigned int msiof2_ss1_b_mux[] = {
2147 static const unsigned int msiof2_ss2_b_pins[] = {
2151 static const unsigned int msiof2_ss2_b_mux[] = {
2154 static const unsigned int msiof2_rx_b_pins[] = {
2158 static const unsigned int msiof2_rx_b_mux[] = {
2161 static const unsigned int msiof2_tx_b_pins[] = {
2165 static const unsigned int msiof2_tx_b_mux[] = {
2168 /* - QSPI ------------------------------------------------------------------- */
2169 static const unsigned int qspi_ctrl_pins[] = {
2171 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2173 static const unsigned int qspi_ctrl_mux[] = {
2174 SPCLK_MARK, SSL_MARK,
2176 static const unsigned int qspi_data2_pins[] = {
2177 /* MOSI_IO0, MISO_IO1 */
2178 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2180 static const unsigned int qspi_data2_mux[] = {
2181 MOSI_IO0_MARK, MISO_IO1_MARK,
2183 static const unsigned int qspi_data4_pins[] = {
2184 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2185 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2188 static const unsigned int qspi_data4_mux[] = {
2189 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2191 /* - SCIF0 ------------------------------------------------------------------ */
2192 static const unsigned int scif0_data_pins[] = {
2194 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2196 static const unsigned int scif0_data_mux[] = {
2197 SCIF0_RXD_MARK, SCIF0_TXD_MARK,
2199 static const unsigned int scif0_data_b_pins[] = {
2201 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
2203 static const unsigned int scif0_data_b_mux[] = {
2204 SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK,
2206 static const unsigned int scif0_data_c_pins[] = {
2208 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2210 static const unsigned int scif0_data_c_mux[] = {
2211 SCIF0_RXD_C_MARK, SCIF0_TXD_C_MARK,
2213 static const unsigned int scif0_data_d_pins[] = {
2215 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
2217 static const unsigned int scif0_data_d_mux[] = {
2218 SCIF0_RXD_D_MARK, SCIF0_TXD_D_MARK,
2220 /* - SCIF1 ------------------------------------------------------------------ */
2221 static const unsigned int scif1_data_pins[] = {
2223 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
2225 static const unsigned int scif1_data_mux[] = {
2226 SCIF1_RXD_MARK, SCIF1_TXD_MARK,
2228 static const unsigned int scif1_clk_pins[] = {
2232 static const unsigned int scif1_clk_mux[] = {
2235 static const unsigned int scif1_data_b_pins[] = {
2237 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
2239 static const unsigned int scif1_data_b_mux[] = {
2240 SCIF1_RXD_B_MARK, SCIF1_TXD_B_MARK,
2242 static const unsigned int scif1_clk_b_pins[] = {
2246 static const unsigned int scif1_clk_b_mux[] = {
2249 static const unsigned int scif1_data_c_pins[] = {
2251 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
2253 static const unsigned int scif1_data_c_mux[] = {
2254 SCIF1_RXD_C_MARK, SCIF1_TXD_C_MARK,
2256 static const unsigned int scif1_clk_c_pins[] = {
2260 static const unsigned int scif1_clk_c_mux[] = {
2263 /* - SCIF2 ------------------------------------------------------------------ */
2264 static const unsigned int scif2_data_pins[] = {
2266 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2268 static const unsigned int scif2_data_mux[] = {
2269 SCIF2_RXD_MARK, SCIF2_TXD_MARK,
2271 static const unsigned int scif2_clk_pins[] = {
2275 static const unsigned int scif2_clk_mux[] = {
2278 static const unsigned int scif2_data_b_pins[] = {
2280 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
2282 static const unsigned int scif2_data_b_mux[] = {
2283 SCIF2_RXD_B_MARK, SCIF2_TXD_B_MARK,
2285 static const unsigned int scif2_clk_b_pins[] = {
2289 static const unsigned int scif2_clk_b_mux[] = {
2292 static const unsigned int scif2_data_c_pins[] = {
2294 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2296 static const unsigned int scif2_data_c_mux[] = {
2297 SCIF2_RXD_C_MARK, SCIF2_TXD_C_MARK,
2299 static const unsigned int scif2_clk_c_pins[] = {
2303 static const unsigned int scif2_clk_c_mux[] = {
2306 /* - SCIF3 ------------------------------------------------------------------ */
2307 static const unsigned int scif3_data_pins[] = {
2309 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
2311 static const unsigned int scif3_data_mux[] = {
2312 SCIF3_RXD_MARK, SCIF3_TXD_MARK,
2314 static const unsigned int scif3_clk_pins[] = {
2318 static const unsigned int scif3_clk_mux[] = {
2321 static const unsigned int scif3_data_b_pins[] = {
2323 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
2325 static const unsigned int scif3_data_b_mux[] = {
2326 SCIF3_RXD_B_MARK, SCIF3_TXD_B_MARK,
2328 static const unsigned int scif3_clk_b_pins[] = {
2332 static const unsigned int scif3_clk_b_mux[] = {
2335 /* - SCIF4 ------------------------------------------------------------------ */
2336 static const unsigned int scif4_data_pins[] = {
2338 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2340 static const unsigned int scif4_data_mux[] = {
2341 SCIF4_RXD_MARK, SCIF4_TXD_MARK,
2343 static const unsigned int scif4_data_b_pins[] = {
2345 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2347 static const unsigned int scif4_data_b_mux[] = {
2348 SCIF4_RXD_B_MARK, SCIF4_TXD_B_MARK,
2350 static const unsigned int scif4_data_c_pins[] = {
2352 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
2354 static const unsigned int scif4_data_c_mux[] = {
2355 SCIF4_RXD_C_MARK, SCIF4_TXD_C_MARK,
2357 static const unsigned int scif4_data_d_pins[] = {
2359 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
2361 static const unsigned int scif4_data_d_mux[] = {
2362 SCIF4_RXD_D_MARK, SCIF4_TXD_D_MARK,
2364 static const unsigned int scif4_data_e_pins[] = {
2366 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
2368 static const unsigned int scif4_data_e_mux[] = {
2369 SCIF4_RXD_E_MARK, SCIF4_TXD_E_MARK,
2371 /* - SCIF5 ------------------------------------------------------------------ */
2372 static const unsigned int scif5_data_pins[] = {
2374 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2376 static const unsigned int scif5_data_mux[] = {
2377 SCIF5_RXD_MARK, SCIF5_TXD_MARK,
2379 static const unsigned int scif5_data_b_pins[] = {
2381 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
2383 static const unsigned int scif5_data_b_mux[] = {
2384 SCIF5_RXD_B_MARK, SCIF5_TXD_B_MARK,
2386 static const unsigned int scif5_data_c_pins[] = {
2388 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 11),
2390 static const unsigned int scif5_data_c_mux[] = {
2391 SCIF5_RXD_C_MARK, SCIF5_TXD_C_MARK,
2393 static const unsigned int scif5_data_d_pins[] = {
2395 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2397 static const unsigned int scif5_data_d_mux[] = {
2398 SCIF5_RXD_D_MARK, SCIF5_TXD_D_MARK,
2400 /* - SCIFA0 ----------------------------------------------------------------- */
2401 static const unsigned int scifa0_data_pins[] = {
2403 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
2405 static const unsigned int scifa0_data_mux[] = {
2406 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2408 static const unsigned int scifa0_data_b_pins[] = {
2410 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2412 static const unsigned int scifa0_data_b_mux[] = {
2413 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2415 static const unsigned int scifa0_data_c_pins[] = {
2417 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
2419 static const unsigned int scifa0_data_c_mux[] = {
2420 SCIFA0_RXD_C_MARK, SCIFA0_TXD_C_MARK
2422 static const unsigned int scifa0_data_d_pins[] = {
2424 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2426 static const unsigned int scifa0_data_d_mux[] = {
2427 SCIFA0_RXD_D_MARK, SCIFA0_TXD_D_MARK
2429 /* - SCIFA1 ----------------------------------------------------------------- */
2430 static const unsigned int scifa1_data_pins[] = {
2432 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2434 static const unsigned int scifa1_data_mux[] = {
2435 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2437 static const unsigned int scifa1_clk_pins[] = {
2441 static const unsigned int scifa1_clk_mux[] = {
2444 static const unsigned int scifa1_data_b_pins[] = {
2446 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2448 static const unsigned int scifa1_data_b_mux[] = {
2449 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2451 static const unsigned int scifa1_clk_b_pins[] = {
2455 static const unsigned int scifa1_clk_b_mux[] = {
2458 static const unsigned int scifa1_data_c_pins[] = {
2460 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2462 static const unsigned int scifa1_data_c_mux[] = {
2463 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2465 static const unsigned int scifa1_clk_c_pins[] = {
2469 static const unsigned int scifa1_clk_c_mux[] = {
2472 /* - SCIFA2 ----------------------------------------------------------------- */
2473 static const unsigned int scifa2_data_pins[] = {
2475 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2477 static const unsigned int scifa2_data_mux[] = {
2478 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2480 static const unsigned int scifa2_clk_pins[] = {
2484 static const unsigned int scifa2_clk_mux[] = {
2487 static const unsigned int scifa2_data_b_pins[] = {
2489 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 0),
2491 static const unsigned int scifa2_data_b_mux[] = {
2492 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
2494 static const unsigned int scifa2_clk_b_pins[] = {
2498 static const unsigned int scifa2_clk_b_mux[] = {
2501 /* - SCIFA3 ----------------------------------------------------------------- */
2502 static const unsigned int scifa3_data_pins[] = {
2504 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2506 static const unsigned int scifa3_data_mux[] = {
2507 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2509 static const unsigned int scifa3_clk_pins[] = {
2513 static const unsigned int scifa3_clk_mux[] = {
2516 static const unsigned int scifa3_data_b_pins[] = {
2518 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
2520 static const unsigned int scifa3_data_b_mux[] = {
2521 SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
2523 static const unsigned int scifa3_clk_b_pins[] = {
2527 static const unsigned int scifa3_clk_b_mux[] = {
2530 /* - SCIFA4 ----------------------------------------------------------------- */
2531 static const unsigned int scifa4_data_pins[] = {
2533 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 12),
2535 static const unsigned int scifa4_data_mux[] = {
2536 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2538 static const unsigned int scifa4_data_b_pins[] = {
2540 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 23),
2542 static const unsigned int scifa4_data_b_mux[] = {
2543 SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
2545 static const unsigned int scifa4_data_c_pins[] = {
2547 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
2549 static const unsigned int scifa4_data_c_mux[] = {
2550 SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
2552 static const unsigned int scifa4_data_d_pins[] = {
2554 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
2556 static const unsigned int scifa4_data_d_mux[] = {
2557 SCIFA4_RXD_D_MARK, SCIFA4_TXD_D_MARK,
2559 /* - SCIFA5 ----------------------------------------------------------------- */
2560 static const unsigned int scifa5_data_pins[] = {
2562 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
2564 static const unsigned int scifa5_data_mux[] = {
2565 SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
2567 static const unsigned int scifa5_data_b_pins[] = {
2569 RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 29),
2571 static const unsigned int scifa5_data_b_mux[] = {
2572 SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
2574 static const unsigned int scifa5_data_c_pins[] = {
2576 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
2578 static const unsigned int scifa5_data_c_mux[] = {
2579 SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
2581 static const unsigned int scifa5_data_d_pins[] = {
2583 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
2585 static const unsigned int scifa5_data_d_mux[] = {
2586 SCIFA5_RXD_D_MARK, SCIFA5_TXD_D_MARK,
2588 /* - SCIFB0 ----------------------------------------------------------------- */
2589 static const unsigned int scifb0_data_pins[] = {
2591 RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 20),
2593 static const unsigned int scifb0_data_mux[] = {
2594 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
2596 static const unsigned int scifb0_clk_pins[] = {
2600 static const unsigned int scifb0_clk_mux[] = {
2603 static const unsigned int scifb0_ctrl_pins[] = {
2605 RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22),
2607 static const unsigned int scifb0_ctrl_mux[] = {
2608 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
2610 /* - SCIFB1 ----------------------------------------------------------------- */
2611 static const unsigned int scifb1_data_pins[] = {
2613 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(0, 17),
2615 static const unsigned int scifb1_data_mux[] = {
2616 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
2618 static const unsigned int scifb1_clk_pins[] = {
2622 static const unsigned int scifb1_clk_mux[] = {
2625 /* - SCIFB2 ----------------------------------------------------------------- */
2626 static const unsigned int scifb2_data_pins[] = {
2628 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
2630 static const unsigned int scifb2_data_mux[] = {
2631 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
2633 static const unsigned int scifb2_clk_pins[] = {
2637 static const unsigned int scifb2_clk_mux[] = {
2640 static const unsigned int scifb2_ctrl_pins[] = {
2642 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2644 static const unsigned int scifb2_ctrl_mux[] = {
2645 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
2647 /* - SDHI0 ------------------------------------------------------------------ */
2648 static const unsigned int sdhi0_data1_pins[] = {
2652 static const unsigned int sdhi0_data1_mux[] = {
2655 static const unsigned int sdhi0_data4_pins[] = {
2657 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
2658 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
2660 static const unsigned int sdhi0_data4_mux[] = {
2661 SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
2663 static const unsigned int sdhi0_ctrl_pins[] = {
2665 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
2667 static const unsigned int sdhi0_ctrl_mux[] = {
2668 SD0_CLK_MARK, SD0_CMD_MARK,
2670 static const unsigned int sdhi0_cd_pins[] = {
2674 static const unsigned int sdhi0_cd_mux[] = {
2677 static const unsigned int sdhi0_wp_pins[] = {
2681 static const unsigned int sdhi0_wp_mux[] = {
2684 /* - SDHI1 ------------------------------------------------------------------ */
2685 static const unsigned int sdhi1_data1_pins[] = {
2689 static const unsigned int sdhi1_data1_mux[] = {
2692 static const unsigned int sdhi1_data4_pins[] = {
2694 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
2695 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
2697 static const unsigned int sdhi1_data4_mux[] = {
2698 SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
2700 static const unsigned int sdhi1_ctrl_pins[] = {
2702 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2704 static const unsigned int sdhi1_ctrl_mux[] = {
2705 SD1_CLK_MARK, SD1_CMD_MARK,
2707 static const unsigned int sdhi1_cd_pins[] = {
2711 static const unsigned int sdhi1_cd_mux[] = {
2714 static const unsigned int sdhi1_wp_pins[] = {
2718 static const unsigned int sdhi1_wp_mux[] = {
2721 /* - SDHI2 ------------------------------------------------------------------ */
2722 static const unsigned int sdhi2_data1_pins[] = {
2726 static const unsigned int sdhi2_data1_mux[] = {
2729 static const unsigned int sdhi2_data4_pins[] = {
2731 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2732 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2734 static const unsigned int sdhi2_data4_mux[] = {
2735 SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
2737 static const unsigned int sdhi2_ctrl_pins[] = {
2739 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2741 static const unsigned int sdhi2_ctrl_mux[] = {
2742 SD2_CLK_MARK, SD2_CMD_MARK,
2744 static const unsigned int sdhi2_cd_pins[] = {
2748 static const unsigned int sdhi2_cd_mux[] = {
2751 static const unsigned int sdhi2_wp_pins[] = {
2755 static const unsigned int sdhi2_wp_mux[] = {
2758 /* - USB0 ------------------------------------------------------------------- */
2759 static const unsigned int usb0_pins[] = {
2760 RCAR_GP_PIN(5, 24), /* PWEN */
2761 RCAR_GP_PIN(5, 25), /* OVC */
2763 static const unsigned int usb0_mux[] = {
2767 /* - USB1 ------------------------------------------------------------------- */
2768 static const unsigned int usb1_pins[] = {
2769 RCAR_GP_PIN(5, 26), /* PWEN */
2770 RCAR_GP_PIN(5, 27), /* OVC */
2772 static const unsigned int usb1_mux[] = {
2776 /* - VIN0 ------------------------------------------------------------------- */
2777 static const union vin_data vin0_data_pins = {
2780 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
2781 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
2782 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
2783 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
2785 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
2786 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
2787 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
2788 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
2790 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22),
2791 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
2792 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
2793 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
2796 static const union vin_data vin0_data_mux = {
2799 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
2800 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
2801 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
2802 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
2804 VI0_G0_MARK, VI0_G1_MARK,
2805 VI0_G2_MARK, VI0_G3_MARK,
2806 VI0_G4_MARK, VI0_G5_MARK,
2807 VI0_G6_MARK, VI0_G7_MARK,
2809 VI0_R0_MARK, VI0_R1_MARK,
2810 VI0_R2_MARK, VI0_R3_MARK,
2811 VI0_R4_MARK, VI0_R5_MARK,
2812 VI0_R6_MARK, VI0_R7_MARK,
2815 static const unsigned int vin0_data18_pins[] = {
2817 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
2818 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
2819 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
2821 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
2822 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
2823 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
2825 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
2826 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
2827 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
2829 static const unsigned int vin0_data18_mux[] = {
2831 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
2832 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
2833 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
2835 VI0_G2_MARK, VI0_G3_MARK,
2836 VI0_G4_MARK, VI0_G5_MARK,
2837 VI0_G6_MARK, VI0_G7_MARK,
2839 VI0_R2_MARK, VI0_R3_MARK,
2840 VI0_R4_MARK, VI0_R5_MARK,
2841 VI0_R6_MARK, VI0_R7_MARK,
2843 static const unsigned int vin0_sync_pins[] = {
2844 RCAR_GP_PIN(3, 11), /* HSYNC */
2845 RCAR_GP_PIN(3, 12), /* VSYNC */
2847 static const unsigned int vin0_sync_mux[] = {
2851 static const unsigned int vin0_field_pins[] = {
2854 static const unsigned int vin0_field_mux[] = {
2857 static const unsigned int vin0_clkenb_pins[] = {
2860 static const unsigned int vin0_clkenb_mux[] = {
2863 static const unsigned int vin0_clk_pins[] = {
2866 static const unsigned int vin0_clk_mux[] = {
2869 /* - VIN1 ------------------------------------------------------------------- */
2870 static const union vin_data vin1_data_pins = {
2872 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
2873 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
2874 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17),
2875 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
2876 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
2877 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2880 static const union vin_data vin1_data_mux = {
2882 VI1_DATA0_MARK, VI1_DATA1_MARK,
2883 VI1_DATA2_MARK, VI1_DATA3_MARK,
2884 VI1_DATA4_MARK, VI1_DATA5_MARK,
2885 VI1_DATA6_MARK, VI1_DATA7_MARK,
2886 VI1_DATA8_MARK, VI1_DATA9_MARK,
2887 VI1_DATA10_MARK, VI1_DATA11_MARK,
2890 static const unsigned int vin1_sync_pins[] = {
2891 RCAR_GP_PIN(5, 22), /* HSYNC */
2892 RCAR_GP_PIN(5, 23), /* VSYNC */
2894 static const unsigned int vin1_sync_mux[] = {
2898 static const unsigned int vin1_field_pins[] = {
2901 static const unsigned int vin1_field_mux[] = {
2904 static const unsigned int vin1_clkenb_pins[] = {
2907 static const unsigned int vin1_clkenb_mux[] = {
2910 static const unsigned int vin1_clk_pins[] = {
2913 static const unsigned int vin1_clk_mux[] = {
2917 static const struct sh_pfc_pin_group pinmux_groups[] = {
2918 SH_PFC_PIN_GROUP(eth_link),
2919 SH_PFC_PIN_GROUP(eth_magic),
2920 SH_PFC_PIN_GROUP(eth_mdio),
2921 SH_PFC_PIN_GROUP(eth_rmii),
2922 SH_PFC_PIN_GROUP(eth_link_b),
2923 SH_PFC_PIN_GROUP(eth_magic_b),
2924 SH_PFC_PIN_GROUP(eth_mdio_b),
2925 SH_PFC_PIN_GROUP(eth_rmii_b),
2926 SH_PFC_PIN_GROUP(hscif0_data),
2927 SH_PFC_PIN_GROUP(hscif0_clk),
2928 SH_PFC_PIN_GROUP(hscif0_ctrl),
2929 SH_PFC_PIN_GROUP(hscif0_data_b),
2930 SH_PFC_PIN_GROUP(hscif0_clk_b),
2931 SH_PFC_PIN_GROUP(hscif1_data),
2932 SH_PFC_PIN_GROUP(hscif1_clk),
2933 SH_PFC_PIN_GROUP(hscif1_ctrl),
2934 SH_PFC_PIN_GROUP(hscif1_data_b),
2935 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
2936 SH_PFC_PIN_GROUP(hscif2_data),
2937 SH_PFC_PIN_GROUP(hscif2_clk),
2938 SH_PFC_PIN_GROUP(hscif2_ctrl),
2939 SH_PFC_PIN_GROUP(i2c0),
2940 SH_PFC_PIN_GROUP(i2c0_b),
2941 SH_PFC_PIN_GROUP(i2c0_c),
2942 SH_PFC_PIN_GROUP(i2c0_d),
2943 SH_PFC_PIN_GROUP(i2c0_e),
2944 SH_PFC_PIN_GROUP(i2c1),
2945 SH_PFC_PIN_GROUP(i2c1_b),
2946 SH_PFC_PIN_GROUP(i2c1_c),
2947 SH_PFC_PIN_GROUP(i2c1_d),
2948 SH_PFC_PIN_GROUP(i2c1_e),
2949 SH_PFC_PIN_GROUP(i2c2),
2950 SH_PFC_PIN_GROUP(i2c2_b),
2951 SH_PFC_PIN_GROUP(i2c2_c),
2952 SH_PFC_PIN_GROUP(i2c2_d),
2953 SH_PFC_PIN_GROUP(i2c2_e),
2954 SH_PFC_PIN_GROUP(i2c3),
2955 SH_PFC_PIN_GROUP(i2c3_b),
2956 SH_PFC_PIN_GROUP(i2c3_c),
2957 SH_PFC_PIN_GROUP(i2c3_d),
2958 SH_PFC_PIN_GROUP(i2c3_e),
2959 SH_PFC_PIN_GROUP(i2c4),
2960 SH_PFC_PIN_GROUP(i2c4_b),
2961 SH_PFC_PIN_GROUP(i2c4_c),
2962 SH_PFC_PIN_GROUP(i2c4_d),
2963 SH_PFC_PIN_GROUP(i2c4_e),
2964 SH_PFC_PIN_GROUP(intc_irq0),
2965 SH_PFC_PIN_GROUP(intc_irq1),
2966 SH_PFC_PIN_GROUP(intc_irq2),
2967 SH_PFC_PIN_GROUP(intc_irq3),
2968 SH_PFC_PIN_GROUP(intc_irq4),
2969 SH_PFC_PIN_GROUP(intc_irq5),
2970 SH_PFC_PIN_GROUP(intc_irq6),
2971 SH_PFC_PIN_GROUP(intc_irq7),
2972 SH_PFC_PIN_GROUP(intc_irq8),
2973 SH_PFC_PIN_GROUP(intc_irq9),
2974 SH_PFC_PIN_GROUP(mmc_data1),
2975 SH_PFC_PIN_GROUP(mmc_data4),
2976 SH_PFC_PIN_GROUP(mmc_data8),
2977 SH_PFC_PIN_GROUP(mmc_ctrl),
2978 SH_PFC_PIN_GROUP(msiof0_clk),
2979 SH_PFC_PIN_GROUP(msiof0_sync),
2980 SH_PFC_PIN_GROUP(msiof0_ss1),
2981 SH_PFC_PIN_GROUP(msiof0_ss2),
2982 SH_PFC_PIN_GROUP(msiof0_rx),
2983 SH_PFC_PIN_GROUP(msiof0_tx),
2984 SH_PFC_PIN_GROUP(msiof1_clk),
2985 SH_PFC_PIN_GROUP(msiof1_sync),
2986 SH_PFC_PIN_GROUP(msiof1_ss1),
2987 SH_PFC_PIN_GROUP(msiof1_ss2),
2988 SH_PFC_PIN_GROUP(msiof1_rx),
2989 SH_PFC_PIN_GROUP(msiof1_tx),
2990 SH_PFC_PIN_GROUP(msiof1_clk_b),
2991 SH_PFC_PIN_GROUP(msiof1_sync_b),
2992 SH_PFC_PIN_GROUP(msiof1_ss1_b),
2993 SH_PFC_PIN_GROUP(msiof1_ss2_b),
2994 SH_PFC_PIN_GROUP(msiof1_rx_b),
2995 SH_PFC_PIN_GROUP(msiof1_tx_b),
2996 SH_PFC_PIN_GROUP(msiof2_clk),
2997 SH_PFC_PIN_GROUP(msiof2_sync),
2998 SH_PFC_PIN_GROUP(msiof2_ss1),
2999 SH_PFC_PIN_GROUP(msiof2_ss2),
3000 SH_PFC_PIN_GROUP(msiof2_rx),
3001 SH_PFC_PIN_GROUP(msiof2_tx),
3002 SH_PFC_PIN_GROUP(msiof2_clk_b),
3003 SH_PFC_PIN_GROUP(msiof2_sync_b),
3004 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3005 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3006 SH_PFC_PIN_GROUP(msiof2_rx_b),
3007 SH_PFC_PIN_GROUP(msiof2_tx_b),
3008 SH_PFC_PIN_GROUP(qspi_ctrl),
3009 SH_PFC_PIN_GROUP(qspi_data2),
3010 SH_PFC_PIN_GROUP(qspi_data4),
3011 SH_PFC_PIN_GROUP(scif0_data),
3012 SH_PFC_PIN_GROUP(scif0_data_b),
3013 SH_PFC_PIN_GROUP(scif0_data_c),
3014 SH_PFC_PIN_GROUP(scif0_data_d),
3015 SH_PFC_PIN_GROUP(scif1_data),
3016 SH_PFC_PIN_GROUP(scif1_clk),
3017 SH_PFC_PIN_GROUP(scif1_data_b),
3018 SH_PFC_PIN_GROUP(scif1_clk_b),
3019 SH_PFC_PIN_GROUP(scif1_data_c),
3020 SH_PFC_PIN_GROUP(scif1_clk_c),
3021 SH_PFC_PIN_GROUP(scif2_data),
3022 SH_PFC_PIN_GROUP(scif2_clk),
3023 SH_PFC_PIN_GROUP(scif2_data_b),
3024 SH_PFC_PIN_GROUP(scif2_clk_b),
3025 SH_PFC_PIN_GROUP(scif2_data_c),
3026 SH_PFC_PIN_GROUP(scif2_clk_c),
3027 SH_PFC_PIN_GROUP(scif3_data),
3028 SH_PFC_PIN_GROUP(scif3_clk),
3029 SH_PFC_PIN_GROUP(scif3_data_b),
3030 SH_PFC_PIN_GROUP(scif3_clk_b),
3031 SH_PFC_PIN_GROUP(scif4_data),
3032 SH_PFC_PIN_GROUP(scif4_data_b),
3033 SH_PFC_PIN_GROUP(scif4_data_c),
3034 SH_PFC_PIN_GROUP(scif4_data_d),
3035 SH_PFC_PIN_GROUP(scif4_data_e),
3036 SH_PFC_PIN_GROUP(scif5_data),
3037 SH_PFC_PIN_GROUP(scif5_data_b),
3038 SH_PFC_PIN_GROUP(scif5_data_c),
3039 SH_PFC_PIN_GROUP(scif5_data_d),
3040 SH_PFC_PIN_GROUP(scifa0_data),
3041 SH_PFC_PIN_GROUP(scifa0_data_b),
3042 SH_PFC_PIN_GROUP(scifa0_data_c),
3043 SH_PFC_PIN_GROUP(scifa0_data_d),
3044 SH_PFC_PIN_GROUP(scifa1_data),
3045 SH_PFC_PIN_GROUP(scifa1_clk),
3046 SH_PFC_PIN_GROUP(scifa1_data_b),
3047 SH_PFC_PIN_GROUP(scifa1_clk_b),
3048 SH_PFC_PIN_GROUP(scifa1_data_c),
3049 SH_PFC_PIN_GROUP(scifa1_clk_c),
3050 SH_PFC_PIN_GROUP(scifa2_data),
3051 SH_PFC_PIN_GROUP(scifa2_clk),
3052 SH_PFC_PIN_GROUP(scifa2_data_b),
3053 SH_PFC_PIN_GROUP(scifa2_clk_b),
3054 SH_PFC_PIN_GROUP(scifa3_data),
3055 SH_PFC_PIN_GROUP(scifa3_clk),
3056 SH_PFC_PIN_GROUP(scifa3_data_b),
3057 SH_PFC_PIN_GROUP(scifa3_clk_b),
3058 SH_PFC_PIN_GROUP(scifa4_data),
3059 SH_PFC_PIN_GROUP(scifa4_data_b),
3060 SH_PFC_PIN_GROUP(scifa4_data_c),
3061 SH_PFC_PIN_GROUP(scifa4_data_d),
3062 SH_PFC_PIN_GROUP(scifa5_data),
3063 SH_PFC_PIN_GROUP(scifa5_data_b),
3064 SH_PFC_PIN_GROUP(scifa5_data_c),
3065 SH_PFC_PIN_GROUP(scifa5_data_d),
3066 SH_PFC_PIN_GROUP(scifb0_data),
3067 SH_PFC_PIN_GROUP(scifb0_clk),
3068 SH_PFC_PIN_GROUP(scifb0_ctrl),
3069 SH_PFC_PIN_GROUP(scifb1_data),
3070 SH_PFC_PIN_GROUP(scifb1_clk),
3071 SH_PFC_PIN_GROUP(scifb2_data),
3072 SH_PFC_PIN_GROUP(scifb2_clk),
3073 SH_PFC_PIN_GROUP(scifb2_ctrl),
3074 SH_PFC_PIN_GROUP(sdhi0_data1),
3075 SH_PFC_PIN_GROUP(sdhi0_data4),
3076 SH_PFC_PIN_GROUP(sdhi0_ctrl),
3077 SH_PFC_PIN_GROUP(sdhi0_cd),
3078 SH_PFC_PIN_GROUP(sdhi0_wp),
3079 SH_PFC_PIN_GROUP(sdhi1_data1),
3080 SH_PFC_PIN_GROUP(sdhi1_data4),
3081 SH_PFC_PIN_GROUP(sdhi1_ctrl),
3082 SH_PFC_PIN_GROUP(sdhi1_cd),
3083 SH_PFC_PIN_GROUP(sdhi1_wp),
3084 SH_PFC_PIN_GROUP(sdhi2_data1),
3085 SH_PFC_PIN_GROUP(sdhi2_data4),
3086 SH_PFC_PIN_GROUP(sdhi2_ctrl),
3087 SH_PFC_PIN_GROUP(sdhi2_cd),
3088 SH_PFC_PIN_GROUP(sdhi2_wp),
3089 SH_PFC_PIN_GROUP(usb0),
3090 SH_PFC_PIN_GROUP(usb1),
3091 VIN_DATA_PIN_GROUP(vin0_data, 24),
3092 VIN_DATA_PIN_GROUP(vin0_data, 20),
3093 SH_PFC_PIN_GROUP(vin0_data18),
3094 VIN_DATA_PIN_GROUP(vin0_data, 16),
3095 VIN_DATA_PIN_GROUP(vin0_data, 12),
3096 VIN_DATA_PIN_GROUP(vin0_data, 10),
3097 VIN_DATA_PIN_GROUP(vin0_data, 8),
3098 SH_PFC_PIN_GROUP(vin0_sync),
3099 SH_PFC_PIN_GROUP(vin0_field),
3100 SH_PFC_PIN_GROUP(vin0_clkenb),
3101 SH_PFC_PIN_GROUP(vin0_clk),
3102 VIN_DATA_PIN_GROUP(vin1_data, 12),
3103 VIN_DATA_PIN_GROUP(vin1_data, 10),
3104 VIN_DATA_PIN_GROUP(vin1_data, 8),
3105 SH_PFC_PIN_GROUP(vin1_sync),
3106 SH_PFC_PIN_GROUP(vin1_field),
3107 SH_PFC_PIN_GROUP(vin1_clkenb),
3108 SH_PFC_PIN_GROUP(vin1_clk),
3111 static const char * const eth_groups[] = {
3122 static const char * const hscif0_groups[] = {
3130 static const char * const hscif1_groups[] = {
3138 static const char * const hscif2_groups[] = {
3144 static const char * const i2c0_groups[] = {
3152 static const char * const i2c1_groups[] = {
3160 static const char * const i2c2_groups[] = {
3168 static const char * const i2c3_groups[] = {
3176 static const char * const i2c4_groups[] = {
3184 static const char * const intc_groups[] = {
3197 static const char * const mmc_groups[] = {
3204 static const char * const msiof0_groups[] = {
3213 static const char * const msiof1_groups[] = {
3228 static const char * const msiof2_groups[] = {
3243 static const char * const qspi_groups[] = {
3249 static const char * const scif0_groups[] = {
3256 static const char * const scif1_groups[] = {
3265 static const char * const scif2_groups[] = {
3274 static const char * const scif3_groups[] = {
3281 static const char * const scif4_groups[] = {
3289 static const char * const scif5_groups[] = {
3296 static const char * const scifa0_groups[] = {
3303 static const char * const scifa1_groups[] = {
3312 static const char * const scifa2_groups[] = {
3319 static const char * const scifa3_groups[] = {
3326 static const char * const scifa4_groups[] = {
3333 static const char * const scifa5_groups[] = {
3340 static const char * const scifb0_groups[] = {
3346 static const char * const scifb1_groups[] = {
3351 static const char * const scifb2_groups[] = {
3357 static const char * const sdhi0_groups[] = {
3365 static const char * const sdhi1_groups[] = {
3373 static const char * const sdhi2_groups[] = {
3381 static const char * const usb0_groups[] = {
3385 static const char * const usb1_groups[] = {
3389 static const char * const vin0_groups[] = {
3403 static const char * const vin1_groups[] = {
3413 static const struct sh_pfc_function pinmux_functions[] = {
3414 SH_PFC_FUNCTION(eth),
3415 SH_PFC_FUNCTION(hscif0),
3416 SH_PFC_FUNCTION(hscif1),
3417 SH_PFC_FUNCTION(hscif2),
3418 SH_PFC_FUNCTION(i2c0),
3419 SH_PFC_FUNCTION(i2c1),
3420 SH_PFC_FUNCTION(i2c2),
3421 SH_PFC_FUNCTION(i2c3),
3422 SH_PFC_FUNCTION(i2c4),
3423 SH_PFC_FUNCTION(intc),
3424 SH_PFC_FUNCTION(mmc),
3425 SH_PFC_FUNCTION(msiof0),
3426 SH_PFC_FUNCTION(msiof1),
3427 SH_PFC_FUNCTION(msiof2),
3428 SH_PFC_FUNCTION(qspi),
3429 SH_PFC_FUNCTION(scif0),
3430 SH_PFC_FUNCTION(scif1),
3431 SH_PFC_FUNCTION(scif2),
3432 SH_PFC_FUNCTION(scif3),
3433 SH_PFC_FUNCTION(scif4),
3434 SH_PFC_FUNCTION(scif5),
3435 SH_PFC_FUNCTION(scifa0),
3436 SH_PFC_FUNCTION(scifa1),
3437 SH_PFC_FUNCTION(scifa2),
3438 SH_PFC_FUNCTION(scifa3),
3439 SH_PFC_FUNCTION(scifa4),
3440 SH_PFC_FUNCTION(scifa5),
3441 SH_PFC_FUNCTION(scifb0),
3442 SH_PFC_FUNCTION(scifb1),
3443 SH_PFC_FUNCTION(scifb2),
3444 SH_PFC_FUNCTION(sdhi0),
3445 SH_PFC_FUNCTION(sdhi1),
3446 SH_PFC_FUNCTION(sdhi2),
3447 SH_PFC_FUNCTION(usb0),
3448 SH_PFC_FUNCTION(usb1),
3449 SH_PFC_FUNCTION(vin0),
3450 SH_PFC_FUNCTION(vin1),
3453 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3454 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
3455 GP_0_31_FN, FN_IP2_17_16,
3456 GP_0_30_FN, FN_IP2_15_14,
3457 GP_0_29_FN, FN_IP2_13_12,
3458 GP_0_28_FN, FN_IP2_11_10,
3459 GP_0_27_FN, FN_IP2_9_8,
3460 GP_0_26_FN, FN_IP2_7_6,
3461 GP_0_25_FN, FN_IP2_5_4,
3462 GP_0_24_FN, FN_IP2_3_2,
3463 GP_0_23_FN, FN_IP2_1_0,
3464 GP_0_22_FN, FN_IP1_31_30,
3465 GP_0_21_FN, FN_IP1_29_28,
3466 GP_0_20_FN, FN_IP1_27,
3467 GP_0_19_FN, FN_IP1_26,
3469 GP_0_17_FN, FN_IP1_24,
3470 GP_0_16_FN, FN_IP1_23_22,
3471 GP_0_15_FN, FN_IP1_21_20,
3472 GP_0_14_FN, FN_IP1_19_18,
3473 GP_0_13_FN, FN_IP1_17_15,
3474 GP_0_12_FN, FN_IP1_14_13,
3475 GP_0_11_FN, FN_IP1_12_11,
3476 GP_0_10_FN, FN_IP1_10_8,
3477 GP_0_9_FN, FN_IP1_7_6,
3478 GP_0_8_FN, FN_IP1_5_4,
3479 GP_0_7_FN, FN_IP1_3_2,
3480 GP_0_6_FN, FN_IP1_1_0,
3481 GP_0_5_FN, FN_IP0_31_30,
3482 GP_0_4_FN, FN_IP0_29_28,
3483 GP_0_3_FN, FN_IP0_27_26,
3484 GP_0_2_FN, FN_IP0_25,
3485 GP_0_1_FN, FN_IP0_24,
3486 GP_0_0_FN, FN_IP0_23_22, }
3488 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
3495 GP_1_25_FN, FN_DACK0,
3496 GP_1_24_FN, FN_IP7_31,
3497 GP_1_23_FN, FN_IP4_1_0,
3498 GP_1_22_FN, FN_WE1_N,
3499 GP_1_21_FN, FN_WE0_N,
3500 GP_1_20_FN, FN_IP3_31,
3501 GP_1_19_FN, FN_IP3_30,
3502 GP_1_18_FN, FN_IP3_29_27,
3503 GP_1_17_FN, FN_IP3_26_24,
3504 GP_1_16_FN, FN_IP3_23_21,
3505 GP_1_15_FN, FN_IP3_20_18,
3506 GP_1_14_FN, FN_IP3_17_15,
3507 GP_1_13_FN, FN_IP3_14_13,
3508 GP_1_12_FN, FN_IP3_12,
3509 GP_1_11_FN, FN_IP3_11,
3510 GP_1_10_FN, FN_IP3_10,
3511 GP_1_9_FN, FN_IP3_9_8,
3512 GP_1_8_FN, FN_IP3_7_6,
3513 GP_1_7_FN, FN_IP3_5_4,
3514 GP_1_6_FN, FN_IP3_3_2,
3515 GP_1_5_FN, FN_IP3_1_0,
3516 GP_1_4_FN, FN_IP2_31_30,
3517 GP_1_3_FN, FN_IP2_29_27,
3518 GP_1_2_FN, FN_IP2_26_24,
3519 GP_1_1_FN, FN_IP2_23_21,
3520 GP_1_0_FN, FN_IP2_20_18, }
3522 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
3523 GP_2_31_FN, FN_IP6_7_6,
3524 GP_2_30_FN, FN_IP6_5_4,
3525 GP_2_29_FN, FN_IP6_3_2,
3526 GP_2_28_FN, FN_IP6_1_0,
3527 GP_2_27_FN, FN_IP5_31_30,
3528 GP_2_26_FN, FN_IP5_29_28,
3529 GP_2_25_FN, FN_IP5_27_26,
3530 GP_2_24_FN, FN_IP5_25_24,
3531 GP_2_23_FN, FN_IP5_23_22,
3532 GP_2_22_FN, FN_IP5_21_20,
3533 GP_2_21_FN, FN_IP5_19_18,
3534 GP_2_20_FN, FN_IP5_17_16,
3535 GP_2_19_FN, FN_IP5_15_14,
3536 GP_2_18_FN, FN_IP5_13_12,
3537 GP_2_17_FN, FN_IP5_11_9,
3538 GP_2_16_FN, FN_IP5_8_6,
3539 GP_2_15_FN, FN_IP5_5_4,
3540 GP_2_14_FN, FN_IP5_3_2,
3541 GP_2_13_FN, FN_IP5_1_0,
3542 GP_2_12_FN, FN_IP4_31_30,
3543 GP_2_11_FN, FN_IP4_29_28,
3544 GP_2_10_FN, FN_IP4_27_26,
3545 GP_2_9_FN, FN_IP4_25_23,
3546 GP_2_8_FN, FN_IP4_22_20,
3547 GP_2_7_FN, FN_IP4_19_18,
3548 GP_2_6_FN, FN_IP4_17_16,
3549 GP_2_5_FN, FN_IP4_15_14,
3550 GP_2_4_FN, FN_IP4_13_12,
3551 GP_2_3_FN, FN_IP4_11_10,
3552 GP_2_2_FN, FN_IP4_9_8,
3553 GP_2_1_FN, FN_IP4_7_5,
3554 GP_2_0_FN, FN_IP4_4_2 }
3556 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
3557 GP_3_31_FN, FN_IP8_22_20,
3558 GP_3_30_FN, FN_IP8_19_17,
3559 GP_3_29_FN, FN_IP8_16_15,
3560 GP_3_28_FN, FN_IP8_14_12,
3561 GP_3_27_FN, FN_IP8_11_9,
3562 GP_3_26_FN, FN_IP8_8_6,
3563 GP_3_25_FN, FN_IP8_5_3,
3564 GP_3_24_FN, FN_IP8_2_0,
3565 GP_3_23_FN, FN_IP7_29_27,
3566 GP_3_22_FN, FN_IP7_26_24,
3567 GP_3_21_FN, FN_IP7_23_21,
3568 GP_3_20_FN, FN_IP7_20_18,
3569 GP_3_19_FN, FN_IP7_17_15,
3570 GP_3_18_FN, FN_IP7_14_12,
3571 GP_3_17_FN, FN_IP7_11_9,
3572 GP_3_16_FN, FN_IP7_8_6,
3573 GP_3_15_FN, FN_IP7_5_3,
3574 GP_3_14_FN, FN_IP7_2_0,
3575 GP_3_13_FN, FN_IP6_31_29,
3576 GP_3_12_FN, FN_IP6_28_26,
3577 GP_3_11_FN, FN_IP6_25_23,
3578 GP_3_10_FN, FN_IP6_22_20,
3579 GP_3_9_FN, FN_IP6_19_17,
3580 GP_3_8_FN, FN_IP6_16,
3581 GP_3_7_FN, FN_IP6_15,
3582 GP_3_6_FN, FN_IP6_14,
3583 GP_3_5_FN, FN_IP6_13,
3584 GP_3_4_FN, FN_IP6_12,
3585 GP_3_3_FN, FN_IP6_11,
3586 GP_3_2_FN, FN_IP6_10,
3587 GP_3_1_FN, FN_IP6_9,
3588 GP_3_0_FN, FN_IP6_8 }
3590 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
3591 GP_4_31_FN, FN_IP11_17_16,
3592 GP_4_30_FN, FN_IP11_15_14,
3593 GP_4_29_FN, FN_IP11_13_11,
3594 GP_4_28_FN, FN_IP11_10_8,
3595 GP_4_27_FN, FN_IP11_7_6,
3596 GP_4_26_FN, FN_IP11_5_3,
3597 GP_4_25_FN, FN_IP11_2_0,
3598 GP_4_24_FN, FN_IP10_31_30,
3599 GP_4_23_FN, FN_IP10_29_27,
3600 GP_4_22_FN, FN_IP10_26_24,
3601 GP_4_21_FN, FN_IP10_23_21,
3602 GP_4_20_FN, FN_IP10_20_18,
3603 GP_4_19_FN, FN_IP10_17_15,
3604 GP_4_18_FN, FN_IP10_14_12,
3605 GP_4_17_FN, FN_IP10_11_9,
3606 GP_4_16_FN, FN_IP10_8_6,
3607 GP_4_15_FN, FN_IP10_5_3,
3608 GP_4_14_FN, FN_IP10_2_0,
3609 GP_4_13_FN, FN_IP9_30_28,
3610 GP_4_12_FN, FN_IP9_27_25,
3611 GP_4_11_FN, FN_IP9_24_22,
3612 GP_4_10_FN, FN_IP9_21_19,
3613 GP_4_9_FN, FN_IP9_18_17,
3614 GP_4_8_FN, FN_IP9_16_15,
3615 GP_4_7_FN, FN_IP9_14_12,
3616 GP_4_6_FN, FN_IP9_11_9,
3617 GP_4_5_FN, FN_IP9_8_6,
3618 GP_4_4_FN, FN_IP9_5_3,
3619 GP_4_3_FN, FN_IP9_2_0,
3620 GP_4_2_FN, FN_IP8_31_29,
3621 GP_4_1_FN, FN_IP8_28_26,
3622 GP_4_0_FN, FN_IP8_25_23 }
3624 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
3629 GP_5_27_FN, FN_USB1_OVC,
3630 GP_5_26_FN, FN_USB1_PWEN,
3631 GP_5_25_FN, FN_USB0_OVC,
3632 GP_5_24_FN, FN_USB0_PWEN,
3633 GP_5_23_FN, FN_IP13_26_24,
3634 GP_5_22_FN, FN_IP13_23_21,
3635 GP_5_21_FN, FN_IP13_20_18,
3636 GP_5_20_FN, FN_IP13_17_15,
3637 GP_5_19_FN, FN_IP13_14_12,
3638 GP_5_18_FN, FN_IP13_11_9,
3639 GP_5_17_FN, FN_IP13_8_6,
3640 GP_5_16_FN, FN_IP13_5_3,
3641 GP_5_15_FN, FN_IP13_2_0,
3642 GP_5_14_FN, FN_IP12_29_27,
3643 GP_5_13_FN, FN_IP12_26_24,
3644 GP_5_12_FN, FN_IP12_23_21,
3645 GP_5_11_FN, FN_IP12_20_18,
3646 GP_5_10_FN, FN_IP12_17_15,
3647 GP_5_9_FN, FN_IP12_14_13,
3648 GP_5_8_FN, FN_IP12_12_11,
3649 GP_5_7_FN, FN_IP12_10_9,
3650 GP_5_6_FN, FN_IP12_8_6,
3651 GP_5_5_FN, FN_IP12_5_3,
3652 GP_5_4_FN, FN_IP12_2_0,
3653 GP_5_3_FN, FN_IP11_29_27,
3654 GP_5_2_FN, FN_IP11_26_24,
3655 GP_5_1_FN, FN_IP11_23_21,
3656 GP_5_0_FN, FN_IP11_20_18 }
3658 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
3665 GP_6_25_FN, FN_IP0_21_20,
3666 GP_6_24_FN, FN_IP0_19_18,
3667 GP_6_23_FN, FN_IP0_17,
3668 GP_6_22_FN, FN_IP0_16,
3669 GP_6_21_FN, FN_IP0_15,
3670 GP_6_20_FN, FN_IP0_14,
3671 GP_6_19_FN, FN_IP0_13,
3672 GP_6_18_FN, FN_IP0_12,
3673 GP_6_17_FN, FN_IP0_11,
3674 GP_6_16_FN, FN_IP0_10,
3675 GP_6_15_FN, FN_IP0_9_8,
3676 GP_6_14_FN, FN_IP0_0,
3677 GP_6_13_FN, FN_SD1_DATA3,
3678 GP_6_12_FN, FN_SD1_DATA2,
3679 GP_6_11_FN, FN_SD1_DATA1,
3680 GP_6_10_FN, FN_SD1_DATA0,
3681 GP_6_9_FN, FN_SD1_CMD,
3682 GP_6_8_FN, FN_SD1_CLK,
3683 GP_6_7_FN, FN_SD0_WP,
3684 GP_6_6_FN, FN_SD0_CD,
3685 GP_6_5_FN, FN_SD0_DATA3,
3686 GP_6_4_FN, FN_SD0_DATA2,
3687 GP_6_3_FN, FN_SD0_DATA1,
3688 GP_6_2_FN, FN_SD0_DATA0,
3689 GP_6_1_FN, FN_SD0_CMD,
3690 GP_6_0_FN, FN_SD0_CLK }
3692 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
3693 2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
3694 2, 1, 1, 1, 1, 1, 1, 1, 1) {
3696 FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
3698 FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0,
3700 FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0,
3702 FN_D2, FN_SCIFA3_TXD_B,
3704 FN_D1, FN_SCIFA3_RXD_B,
3706 FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0,
3708 FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX,
3710 FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX,
3712 FN_MMC_D5, FN_SD2_WP,
3714 FN_MMC_D4, FN_SD2_CD,
3716 FN_MMC_D3, FN_SD2_DATA3,
3718 FN_MMC_D2, FN_SD2_DATA2,
3720 FN_MMC_D1, FN_SD2_DATA1,
3722 FN_MMC_D0, FN_SD2_DATA0,
3724 FN_MMC_CMD, FN_SD2_CMD,
3726 FN_MMC_CLK, FN_SD2_CLK,
3728 FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
3744 FN_SD1_CD, FN_CAN0_RX, }
3746 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
3747 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, 3, 2, 2,
3750 FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
3752 FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
3754 FN_A4, FN_SCIFB0_TXD,
3756 FN_A3, FN_SCIFB0_SCK,
3760 FN_A1, FN_SCIFB1_TXD,
3762 FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 0,
3764 FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B, 0,
3766 FN_D14, FN_SCIFA1_RXD, FN_IIC0_SCL_B, 0,
3768 FN_D13, FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B,
3771 FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
3773 FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
3775 FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
3778 FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, 0,
3780 FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, 0,
3782 FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
3784 FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, }
3786 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
3787 2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2) {
3789 FN_A20, FN_SPCLK, FN_MOUT1, 0,
3791 FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
3794 FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
3795 FN_AVB_AVTP_MATCH_B, 0, 0, 0,
3797 FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
3798 FN_AVB_AVTP_CAPTURE_B, 0, 0, 0,
3800 FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN,
3801 FN_VSP, FN_CAN_CLK_C, FN_TPUTO2_B, 0,
3803 FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
3805 FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
3807 FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, 0,
3809 FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 0,
3811 FN_A11, FN_MSIOF1_SYNC, FN_IIC1_SDA_B, 0,
3813 FN_A10, FN_MSIOF1_SCK, FN_IIC1_SCL_B, 0,
3815 FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 0,
3817 FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0,
3819 FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, }
3821 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
3822 1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2, 2, 2, 2, 2) {
3824 FN_RD_WR_N, FN_ATAG1_N,
3826 FN_RD_N, FN_ATACS11_N,
3828 FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
3831 FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B,
3832 FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B,
3834 FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B,
3835 FN_RIF0_D0, FN_FMCLK, FN_SCIFB2_CTS_N, FN_SCKZ_B,
3837 FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
3838 FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B,
3840 FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B,
3841 FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD, FN_SDATA_B,
3843 FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
3845 FN_EX_CS0_N, FN_VI1_DATA10,
3847 FN_CS1_N_A26, FN_VI1_DATA9,
3849 FN_CS0_N, FN_VI1_DATA8,
3851 FN_A25, FN_SSL, FN_ATARD1_N, 0,
3853 FN_A24, FN_IO3, FN_EX_WAIT2, 0,
3855 FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N,
3857 FN_A22, FN_MISO_IO1, FN_MOUT5, FN_ATADIR1_N,
3859 FN_A21, FN_MOSI_IO0, FN_MOUT2, 0, }
3861 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
3862 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2) {
3864 FN_DU0_DG4, FN_LCDOUT12, FN_CC50_STATE12, 0,
3866 FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, 0,
3868 FN_DU0_DG2, FN_LCDOUT10, FN_CC50_STATE10, 0,
3870 FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
3871 FN_CC50_STATE9, 0, 0, 0,
3873 FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
3874 FN_CC50_STATE8, 0, 0, 0,
3876 FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, 0,
3878 FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6, 0,
3880 FN_DU0_DR5, FN_LCDOUT21, FN_CC50_STATE5, 0,
3882 FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, 0,
3884 FN_DU0_DR3, FN_LCDOUT19, FN_CC50_STATE3, 0,
3886 FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, 0,
3888 FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
3889 FN_CC50_STATE1, 0, 0, 0,
3891 FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
3892 FN_CC50_STATE0, 0, 0, 0,
3894 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, }
3896 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
3897 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2) {
3899 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27, 0,
3901 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_CC50_STATE26, 0,
3903 FN_DU0_DOTCLKOUT0, FN_QCLK, FN_CC50_STATE25, 0,
3905 FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, 0,
3907 FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23, 0,
3909 FN_DU0_DB6, FN_LCDOUT6, FN_CC50_STATE22, 0,
3911 FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, 0,
3913 FN_DU0_DB4, FN_LCDOUT4, FN_CC50_STATE20, 0,
3915 FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, 0,
3917 FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18, 0,
3919 FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
3920 FN_CAN0_TX_C, FN_CC50_STATE17, 0, 0,
3922 FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D,
3923 FN_CAN0_RX_C, FN_CC50_STATE16, 0, 0,
3925 FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, 0,
3927 FN_DU0_DG6, FN_LCDOUT14, FN_CC50_STATE14, 0,
3929 FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, 0, }
3931 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
3932 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
3935 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D,
3936 FN_AVB_TX_CLK, FN_ADIDATA, FN_AD_DI, 0,
3938 FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
3939 FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
3941 FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C,
3942 FN_AVB_COL, 0, 0, 0,
3944 FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C,
3945 FN_AVB_RX_ER, 0, 0, 0,
3947 FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C,
3948 FN_AVB_RXD7, 0, 0, 0,
3950 FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
3952 FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
3954 FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
3956 FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
3958 FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
3960 FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
3962 FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
3964 FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
3966 FN_VI0_CLK, FN_AVB_RX_CLK,
3968 FN_DU0_CDE, FN_QPOLB, FN_CC50_STATE31, 0,
3970 FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0,
3972 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
3974 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, }
3976 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
3977 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
3979 FN_DREQ0_N, FN_SCIFB1_RXD,
3983 FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
3984 FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
3986 FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER,
3987 FN_SSI_SCK6_B, 0, 0, 0,
3989 FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC1_SDA_D,
3990 FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0,
3992 FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC1_SCL_D,
3993 FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0,
3995 FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5,
3996 FN_SSI_SCK5_B, 0, 0, 0,
3998 FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
3999 FN_AVB_TXD4, FN_ADICHS2, 0, 0,
4001 FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D,
4002 FN_AVB_TXD3, FN_ADICHS1, 0, 0,
4004 FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B,
4005 FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, 0,
4007 FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
4008 FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, 0,
4010 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D,
4011 FN_AVB_TXD0, FN_ADICS_SAMP, FN_AD_DO, 0, }
4013 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
4014 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) {
4016 FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
4017 FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
4019 FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
4020 FN_RIF1_CLK_B, FN_TS_SCK_D, FN_BPFCLK_C, 0,
4022 FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
4023 FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
4025 FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK,
4026 FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
4028 FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B,
4029 FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0,
4031 FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
4033 FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
4034 FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0,
4036 FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
4037 FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0,
4039 FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B,
4040 FN_AVB_LINK, FN_SSI_WS78_B, 0, 0,
4042 FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B,
4043 FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
4045 FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
4046 FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, }
4048 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
4049 1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3, 3) {
4053 FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5,
4054 FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34, 0,
4056 FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4,
4057 FN_SSI_WS1_B, FN_CAN_STEP0, FN_CC50_STATE33, 0,
4059 FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3,
4060 FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32, 0,
4062 FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2,
4063 FN_REMOCON_B, FN_SPEEDIN_B, FN_VSP_B, 0,
4065 FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
4067 FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
4069 FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
4070 FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, 0,
4072 FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6,
4073 FN_RIF1_D0, FN_FMCLK_B, FN_RDS_CLK_B, 0,
4075 FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5,
4076 FN_RIF1_CLK, FN_BPFCLK_B, 0, 0,
4078 FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4,
4079 FN_RIF1_SYNC, FN_TPUTO1_C, 0, 0,
4081 FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3,
4082 FN_RIF1_D1_B, FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, }
4084 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
4085 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
4086 /* IP10_31_30 [2] */
4087 FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10,
4088 /* IP10_29_27 [3] */
4089 FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
4090 FN_CAN_DEBUGOUT9, 0, 0, 0,
4091 /* IP10_26_24 [3] */
4092 FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
4093 FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, 0, 0,
4094 /* IP10_23_21 [3] */
4095 FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5,
4096 FN_AUDIO_CLKB_C, FN_SSI_WS4_B, FN_CAN_DEBUGOUT7, FN_RDS_DATA_C,
4097 /* IP10_20_18 [3] */
4098 FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4,
4099 FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C,
4100 /* IP10_17_15 [3] */
4101 FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
4102 FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT,
4103 /* IP10_14_12 [3] */
4104 FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
4105 FN_USB0_IDIN, FN_CAN_DEBUGOUT4, FN_CC50_STATE39, 0,
4107 FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
4108 FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, 0,
4110 FN_SCIF2_RXD, FN_IIC1_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
4111 FN_USB0_EXTLP, FN_CAN_DEBUGOUT2, FN_CC50_STATE37, 0,
4113 FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
4114 FN_CAN_DEBUGOUT1, FN_CC50_STATE36, 0, 0,
4116 FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
4117 FN_CAN_DEBUGOUT0, FN_CC50_STATE35, 0, 0, }
4119 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
4120 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) {
4121 /* IP11_31_30 [2] */
4123 /* IP11_29_27 [3] */
4124 FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
4125 FN_AD_CLK_B, 0, 0, 0,
4126 /* IP11_26_24 [3] */
4127 FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
4128 FN_AD_DO_B, 0, 0, 0,
4129 /* IP11_23_21 [3] */
4130 FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
4131 FN_AD_DI_B, FN_PCMWE_N, 0, 0,
4132 /* IP11_20_18 [3] */
4133 FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
4134 FN_CAN_CLK_D, FN_PCMOE_N, 0, 0,
4135 /* IP11_17_16 [2] */
4136 FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE,
4137 /* IP11_15_14 [2] */
4138 FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP,
4139 /* IP11_13_11 [3] */
4140 FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
4141 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, 0, 0, 0,
4143 FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C,
4144 FN_DU1_EXVSYNC_DU1_VSYNC, FN_CAN_DEBUGOUT14, 0, 0, 0,
4146 FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
4149 FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
4150 FN_CAN_DEBUGOUT12, 0, 0, 0,
4152 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
4153 FN_CAN_DEBUGOUT11, 0, 0, 0, }
4155 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
4156 2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3) {
4157 /* IP12_31_30 [2] */
4159 /* IP12_29_27 [3] */
4160 FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_MDATA,
4161 FN_ATAWR0_N, FN_ETH_RXD1_B, 0, 0,
4162 /* IP12_26_24 [3] */
4163 FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_SDATA,
4164 FN_ATAG0_N, FN_ETH_RXD0_B, 0, 0,
4165 /* IP12_23_21 [3] */
4166 FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC1_SDA_C, FN_VI1_DATA0,
4167 FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, FN_ETH_RX_ER_B, 0,
4168 /* IP12_20_18 [3] */
4169 FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK,
4170 FN_CAN0_RX_D, FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, 0,
4171 /* IP12_17_15 [3] */
4172 FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9,
4173 FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0,
4174 /* IP12_14_13 [2] */
4175 FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, FN_IRD_SCK,
4176 /* IP12_12_11 [2] */
4177 FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX,
4179 FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX,
4181 FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
4182 FN_CAN1_TX_C, FN_DREQ2_N, 0, 0,
4184 FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
4185 FN_CAN1_RX_C, FN_DACK1_B, 0, 0,
4187 FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
4188 FN_AD_NCS_N_B, FN_DREQ1_N_B, 0, 0, }
4190 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
4191 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
4202 /* IP13_26_24 [3] */
4203 FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
4204 FN_TS_SPSYNC_C, FN_RIF0_D1_B, FN_FMIN_E, FN_RDS_DATA_D,
4205 /* IP13_23_21 [3] */
4206 FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
4207 FN_TS_SDEN_C, FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D,
4208 /* IP13_20_18 [3] */
4209 FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
4210 FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B,
4211 /* IP13_17_15 [3] */
4212 FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
4213 FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B, 0,
4214 /* IP13_14_12 [3] */
4215 FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
4216 FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0,
4218 FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6,
4219 FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0,
4221 FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5,
4222 FN_MTS_N, FN_EX_WAIT1, FN_ETH_TXD1_B, 0,
4224 FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D,
4225 FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B, 0,
4227 FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
4228 FN_SCKZ, FN_ATACS00_N, FN_ETH_LINK_B, 0, }
4230 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
4231 2, 1, 2, 3, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3,
4234 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
4236 FN_SEL_ADI_0, FN_SEL_ADI_1,
4238 FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
4240 FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
4241 FN_SEL_DARC_4, 0, 0, 0,
4243 FN_SEL_DR0_0, FN_SEL_DR0_1,
4245 FN_SEL_DR1_0, FN_SEL_DR1_1,
4247 FN_SEL_DR2_0, FN_SEL_DR2_1,
4249 FN_SEL_DR3_0, FN_SEL_DR3_1,
4251 FN_SEL_ETH_0, FN_SEL_ETH_1,
4253 FN_SEL_FSN_0, FN_SEL_FSN_1,
4255 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
4256 FN_SEL_I2C00_4, 0, 0, 0,
4258 FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
4259 FN_SEL_I2C01_4, 0, 0, 0,
4261 FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
4262 FN_SEL_I2C02_4, 0, 0, 0,
4264 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
4265 FN_SEL_I2C03_4, 0, 0, 0,
4267 FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
4268 FN_SEL_I2C04_4, 0, 0, 0,
4270 FN_SEL_IIC00_0, FN_SEL_IIC00_1, FN_SEL_IIC00_2, FN_SEL_IIC00_3,
4272 FN_SEL_AVB_0, FN_SEL_AVB_1, }
4274 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
4275 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1,
4278 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
4280 FN_SEL_IIC01_0, FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3,
4282 FN_SEL_LBS_0, FN_SEL_LBS_1,
4284 FN_SEL_MSI1_0, FN_SEL_MSI1_1,
4286 FN_SEL_MSI2_0, FN_SEL_MSI2_1,
4288 FN_SEL_RAD_0, FN_SEL_RAD_1,
4290 FN_SEL_RCN_0, FN_SEL_RCN_1,
4292 FN_SEL_RSP_0, FN_SEL_RSP_1,
4293 /* SEL_SCIFA0 [2] */
4294 FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
4296 /* SEL_SCIFA1 [2] */
4297 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
4298 /* SEL_SCIFA2 [1] */
4299 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
4300 /* SEL_SCIFA3 [1] */
4301 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
4302 /* SEL_SCIFA4 [2] */
4303 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
4305 /* SEL_SCIFA5 [2] */
4306 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
4309 FN_SEL_SPDM_0, FN_SEL_SPDM_1,
4311 FN_SEL_TMU_0, FN_SEL_TMU_1,
4313 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
4315 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
4317 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
4318 /* SEL_HSCIF0 [1] */
4319 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
4320 /* SEL_HSCIF1 [1] */
4321 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
4323 FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, }
4325 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
4326 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
4327 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
4329 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
4331 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
4333 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
4335 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
4337 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
4338 FN_SEL_SCIF4_4, 0, 0, 0,
4340 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
4342 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
4344 FN_SEL_SSI2_0, FN_SEL_SSI2_1,
4346 FN_SEL_SSI4_0, FN_SEL_SSI4_1,
4348 FN_SEL_SSI5_0, FN_SEL_SSI5_1,
4350 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
4352 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
4354 FN_SEL_SSI8_0, FN_SEL_SSI8_1,
4356 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
4385 const struct sh_pfc_soc_info r8a7794_pinmux_info = {
4386 .name = "r8a77940_pfc",
4387 .unlock_reg = 0xe6060000, /* PMMR */
4389 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4391 .pins = pinmux_pins,
4392 .nr_pins = ARRAY_SIZE(pinmux_pins),
4393 .groups = pinmux_groups,
4394 .nr_groups = ARRAY_SIZE(pinmux_groups),
4395 .functions = pinmux_functions,
4396 .nr_functions = ARRAY_SIZE(pinmux_functions),
4398 .cfg_regs = pinmux_config_regs,
4400 .pinmux_data = pinmux_data,
4401 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
projects / karo-tx-linux.git / blob