drivers/usb/dwc3/dwc3-omap.c

   1 /**
   2  * dwc3-omap.c - OMAP Specific Glue layer
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/kernel.h>
  21 #include <linux/slab.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/platform_data/dwc3-omap.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/ioport.h>
  28 #include <linux/io.h>
  29 #include <linux/of.h>
  30 #include <linux/of_platform.h>
  31 #include <linux/extcon.h>
  32 #include <linux/regulator/consumer.h>
  33
  34 #include <linux/usb/otg.h>
  35
  36 /*
  37  * All these registers belong to OMAP's Wrapper around the
  38  * DesignWare USB3 Core.
  39  */
  40
  41 #define USBOTGSS_REVISION                       0x0000
  42 #define USBOTGSS_SYSCONFIG                      0x0010
  43 #define USBOTGSS_IRQ_EOI                        0x0020
  44 #define USBOTGSS_EOI_OFFSET                     0x0008
  45 #define USBOTGSS_IRQSTATUS_RAW_0                0x0024
  46 #define USBOTGSS_IRQSTATUS_0                    0x0028
  47 #define USBOTGSS_IRQENABLE_SET_0                0x002c
  48 #define USBOTGSS_IRQENABLE_CLR_0                0x0030
  49 #define USBOTGSS_IRQ0_OFFSET                    0x0004
  50 #define USBOTGSS_IRQSTATUS_RAW_1                0x0030
  51 #define USBOTGSS_IRQSTATUS_1                    0x0034
  52 #define USBOTGSS_IRQENABLE_SET_1                0x0038
  53 #define USBOTGSS_IRQENABLE_CLR_1                0x003c
  54 #define USBOTGSS_IRQSTATUS_RAW_2                0x0040
  55 #define USBOTGSS_IRQSTATUS_2                    0x0044
  56 #define USBOTGSS_IRQENABLE_SET_2                0x0048
  57 #define USBOTGSS_IRQENABLE_CLR_2                0x004c
  58 #define USBOTGSS_IRQSTATUS_RAW_3                0x0050
  59 #define USBOTGSS_IRQSTATUS_3                    0x0054
  60 #define USBOTGSS_IRQENABLE_SET_3                0x0058
  61 #define USBOTGSS_IRQENABLE_CLR_3                0x005c
  62 #define USBOTGSS_IRQSTATUS_EOI_MISC             0x0030
  63 #define USBOTGSS_IRQSTATUS_RAW_MISC             0x0034
  64 #define USBOTGSS_IRQSTATUS_MISC                 0x0038
  65 #define USBOTGSS_IRQENABLE_SET_MISC             0x003c
  66 #define USBOTGSS_IRQENABLE_CLR_MISC             0x0040
  67 #define USBOTGSS_IRQMISC_OFFSET                 0x03fc
  68 #define USBOTGSS_UTMI_OTG_STATUS                0x0080
  69 #define USBOTGSS_UTMI_OTG_CTRL                  0x0084
  70 #define USBOTGSS_UTMI_OTG_OFFSET                0x0480
  71 #define USBOTGSS_TXFIFO_DEPTH                   0x0508
  72 #define USBOTGSS_RXFIFO_DEPTH                   0x050c
  73 #define USBOTGSS_MMRAM_OFFSET                   0x0100
  74 #define USBOTGSS_FLADJ                          0x0104
  75 #define USBOTGSS_DEBUG_CFG                      0x0108
  76 #define USBOTGSS_DEBUG_DATA                     0x010c
  77 #define USBOTGSS_DEV_EBC_EN                     0x0110
  78 #define USBOTGSS_DEBUG_OFFSET                   0x0600
  79
  80 /* SYSCONFIG REGISTER */
  81 #define USBOTGSS_SYSCONFIG_DMADISABLE           (1 << 16)
  82
  83 /* IRQ_EOI REGISTER */
  84 #define USBOTGSS_IRQ_EOI_LINE_NUMBER            (1 << 0)
  85
  86 /* IRQS0 BITS */
  87 #define USBOTGSS_IRQO_COREIRQ_ST                (1 << 0)
  88
  89 /* IRQMISC BITS */
  90 #define USBOTGSS_IRQMISC_DMADISABLECLR          (1 << 17)
  91 #define USBOTGSS_IRQMISC_OEVT                   (1 << 16)
  92 #define USBOTGSS_IRQMISC_DRVVBUS_RISE           (1 << 13)
  93 #define USBOTGSS_IRQMISC_CHRGVBUS_RISE          (1 << 12)
  94 #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE       (1 << 11)
  95 #define USBOTGSS_IRQMISC_IDPULLUP_RISE          (1 << 8)
  96 #define USBOTGSS_IRQMISC_DRVVBUS_FALL           (1 << 5)
  97 #define USBOTGSS_IRQMISC_CHRGVBUS_FALL          (1 << 4)
  98 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL               (1 << 3)
  99 #define USBOTGSS_IRQMISC_IDPULLUP_FALL          (1 << 0)
 100
 101 /* UTMI_OTG_STATUS REGISTER */
 102 #define USBOTGSS_UTMI_OTG_STATUS_DRVVBUS        (1 << 5)
 103 #define USBOTGSS_UTMI_OTG_STATUS_CHRGVBUS       (1 << 4)
 104 #define USBOTGSS_UTMI_OTG_STATUS_DISCHRGVBUS    (1 << 3)
 105 #define USBOTGSS_UTMI_OTG_STATUS_IDPULLUP       (1 << 0)
 106
 107 /* UTMI_OTG_CTRL REGISTER */
 108 #define USBOTGSS_UTMI_OTG_CTRL_SW_MODE          (1 << 31)
 109 #define USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT     (1 << 9)
 110 #define USBOTGSS_UTMI_OTG_CTRL_TXBITSTUFFENABLE (1 << 8)
 111 #define USBOTGSS_UTMI_OTG_CTRL_IDDIG            (1 << 4)
 112 #define USBOTGSS_UTMI_OTG_CTRL_SESSEND          (1 << 3)
 113 #define USBOTGSS_UTMI_OTG_CTRL_SESSVALID        (1 << 2)
 114 #define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID        (1 << 1)
 115
 116 struct dwc3_omap {
 117         struct device           *dev;
 118
 119         int                     irq;
 120         void __iomem            *base;
 121
 122         u32                     utmi_otg_ctrl;
 123         u32                     utmi_otg_offset;
 124         u32                     irqmisc_offset;
 125         u32                     irq_eoi_offset;
 126         u32                     debug_offset;
 127         u32                     irq0_offset;
 128
 129         u32                     dma_status:1;
 130
 131         struct extcon_dev       *edev;
 132         struct notifier_block   vbus_nb;
 133         struct notifier_block   id_nb;
 134
 135         struct regulator        *vbus_reg;
 136 };
 137
 138 enum omap_dwc3_vbus_id_status {
 139         OMAP_DWC3_ID_FLOAT,
 140         OMAP_DWC3_ID_GROUND,
 141         OMAP_DWC3_VBUS_OFF,
 142         OMAP_DWC3_VBUS_VALID,
 143 };
 144
 145 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
 146 {
 147         return readl(base + offset);
 148 }
 149
 150 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
 151 {
 152         writel(value, base + offset);
 153 }
 154
 155 static u32 dwc3_omap_read_utmi_ctrl(struct dwc3_omap *omap)
 156 {
 157         return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_CTRL +
 158                                                         omap->utmi_otg_offset);
 159 }
 160
 161 static void dwc3_omap_write_utmi_ctrl(struct dwc3_omap *omap, u32 value)
 162 {
 163         dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL +
 164                                         omap->utmi_otg_offset, value);
 165
 166 }
 167
 168 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
 169 {
 170         return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 -
 171                                                 omap->irq0_offset);
 172 }
 173
 174 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
 175 {
 176         dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
 177                                                 omap->irq0_offset, value);
 178
 179 }
 180
 181 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
 182 {
 183         return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC +
 184                                                 omap->irqmisc_offset);
 185 }
 186
 187 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
 188 {
 189         dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
 190                                         omap->irqmisc_offset, value);
 191
 192 }
 193
 194 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
 195 {
 196         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
 197                                                 omap->irqmisc_offset, value);
 198
 199 }
 200
 201 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
 202 {
 203         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
 204                                                 omap->irq0_offset, value);
 205 }
 206
 207 static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value)
 208 {
 209         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC +
 210                                                 omap->irqmisc_offset, value);
 211 }
 212
 213 static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value)
 214 {
 215         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 -
 216                                                 omap->irq0_offset, value);
 217 }
 218
 219 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
 220         enum omap_dwc3_vbus_id_status status)
 221 {
 222         int     ret;
 223         u32     val;
 224
 225         switch (status) {
 226         case OMAP_DWC3_ID_GROUND:
 227                 if (omap->vbus_reg) {
 228                         ret = regulator_enable(omap->vbus_reg);
 229                         if (ret) {
 230                                 dev_err(omap->dev, "regulator enable failed\n");
 231                                 return;
 232                         }
 233                 }
 234
 235                 val = dwc3_omap_read_utmi_ctrl(omap);
 236                 val &= ~(USBOTGSS_UTMI_OTG_CTRL_IDDIG
 237                                 | USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
 238                                 | USBOTGSS_UTMI_OTG_CTRL_SESSEND);
 239                 val |= USBOTGSS_UTMI_OTG_CTRL_SESSVALID
 240                                 | USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT;
 241                 dwc3_omap_write_utmi_ctrl(omap, val);
 242                 break;
 243
 244         case OMAP_DWC3_VBUS_VALID:
 245                 val = dwc3_omap_read_utmi_ctrl(omap);
 246                 val &= ~USBOTGSS_UTMI_OTG_CTRL_SESSEND;
 247                 val |= USBOTGSS_UTMI_OTG_CTRL_IDDIG
 248                                 | USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
 249                                 | USBOTGSS_UTMI_OTG_CTRL_SESSVALID
 250                                 | USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT;
 251                 dwc3_omap_write_utmi_ctrl(omap, val);
 252                 break;
 253
 254         case OMAP_DWC3_ID_FLOAT:
 255                 if (omap->vbus_reg)
 256                         regulator_disable(omap->vbus_reg);
 257
 258         case OMAP_DWC3_VBUS_OFF:
 259                 val = dwc3_omap_read_utmi_ctrl(omap);
 260                 val &= ~(USBOTGSS_UTMI_OTG_CTRL_SESSVALID
 261                                 | USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
 262                                 | USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT);
 263                 val |= USBOTGSS_UTMI_OTG_CTRL_SESSEND
 264                                 | USBOTGSS_UTMI_OTG_CTRL_IDDIG;
 265                 dwc3_omap_write_utmi_ctrl(omap, val);
 266                 break;
 267
 268         default:
 269                 dev_WARN(omap->dev, "invalid state\n");
 270         }
 271 }
 272
 273 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
 274 {
 275         struct dwc3_omap        *omap = _omap;
 276         u32                     reg;
 277
 278         reg = dwc3_omap_read_irqmisc_status(omap);
 279
 280         if (reg & USBOTGSS_IRQMISC_DMADISABLECLR)
 281                 omap->dma_status = false;
 282
 283         dwc3_omap_write_irqmisc_status(omap, reg);
 284
 285         reg = dwc3_omap_read_irq0_status(omap);
 286
 287         dwc3_omap_write_irq0_status(omap, reg);
 288
 289         return IRQ_HANDLED;
 290 }
 291
 292 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
 293 {
 294         u32                     reg;
 295
 296         /* enable all IRQs */
 297         reg = USBOTGSS_IRQO_COREIRQ_ST;
 298         dwc3_omap_write_irq0_set(omap, reg);
 299
 300         reg = (USBOTGSS_IRQMISC_OEVT |
 301                         USBOTGSS_IRQMISC_DRVVBUS_RISE |
 302                         USBOTGSS_IRQMISC_CHRGVBUS_RISE |
 303                         USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
 304                         USBOTGSS_IRQMISC_IDPULLUP_RISE |
 305                         USBOTGSS_IRQMISC_DRVVBUS_FALL |
 306                         USBOTGSS_IRQMISC_CHRGVBUS_FALL |
 307                         USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
 308                         USBOTGSS_IRQMISC_IDPULLUP_FALL);
 309
 310         dwc3_omap_write_irqmisc_set(omap, reg);
 311 }
 312
 313 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
 314 {
 315         u32                     reg;
 316
 317         /* disable all IRQs */
 318         reg = USBOTGSS_IRQO_COREIRQ_ST;
 319         dwc3_omap_write_irq0_clr(omap, reg);
 320
 321         reg = (USBOTGSS_IRQMISC_OEVT |
 322                         USBOTGSS_IRQMISC_DRVVBUS_RISE |
 323                         USBOTGSS_IRQMISC_CHRGVBUS_RISE |
 324                         USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
 325                         USBOTGSS_IRQMISC_IDPULLUP_RISE |
 326                         USBOTGSS_IRQMISC_DRVVBUS_FALL |
 327                         USBOTGSS_IRQMISC_CHRGVBUS_FALL |
 328                         USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
 329                         USBOTGSS_IRQMISC_IDPULLUP_FALL);
 330
 331         dwc3_omap_write_irqmisc_clr(omap, reg);
 332 }
 333
 334 static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32);
 335
 336 static int dwc3_omap_id_notifier(struct notifier_block *nb,
 337         unsigned long event, void *ptr)
 338 {
 339         struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb);
 340
 341         if (event)
 342                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
 343         else
 344                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);
 345
 346         return NOTIFY_DONE;
 347 }
 348
 349 static int dwc3_omap_vbus_notifier(struct notifier_block *nb,
 350         unsigned long event, void *ptr)
 351 {
 352         struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb);
 353
 354         if (event)
 355                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
 356         else
 357                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
 358
 359         return NOTIFY_DONE;
 360 }
 361
 362 static void dwc3_omap_map_offset(struct dwc3_omap *omap)
 363 {
 364         struct device_node      *node = omap->dev->of_node;
 365
 366         /*
 367          * Differentiate between OMAP5 and AM437x.
 368          *
 369          * For OMAP5(ES2.0) and AM437x wrapper revision is same, even
 370          * though there are changes in wrapper register offsets.
 371          *
 372          * Using dt compatible to differentiate AM437x.
 373          */
 374         if (of_device_is_compatible(node, "ti,am437x-dwc3")) {
 375                 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
 376                 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
 377                 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
 378                 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
 379                 omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
 380         }
 381 }
 382
 383 static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap)
 384 {
 385         u32                     reg;
 386         struct device_node      *node = omap->dev->of_node;
 387         int                     utmi_mode = 0;
 388
 389         reg = dwc3_omap_read_utmi_ctrl(omap);
 390
 391         of_property_read_u32(node, "utmi-mode", &utmi_mode);
 392
 393         switch (utmi_mode) {
 394         case DWC3_OMAP_UTMI_MODE_SW:
 395                 reg |= USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
 396                 break;
 397         case DWC3_OMAP_UTMI_MODE_HW:
 398                 reg &= ~USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
 399                 break;
 400         default:
 401                 dev_WARN(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);
 402         }
 403
 404         dwc3_omap_write_utmi_ctrl(omap, reg);
 405 }
 406
 407 static int dwc3_omap_extcon_register(struct dwc3_omap *omap)
 408 {
 409         int                     ret;
 410         struct device_node      *node = omap->dev->of_node;
 411         struct extcon_dev       *edev;
 412
 413         if (of_property_read_bool(node, "extcon")) {
 414                 edev = extcon_get_edev_by_phandle(omap->dev, 0);
 415                 if (IS_ERR(edev)) {
 416                         dev_vdbg(omap->dev, "couldn't get extcon device\n");
 417                         return -EPROBE_DEFER;
 418                 }
 419
 420                 omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier;
 421                 ret = extcon_register_notifier(edev, EXTCON_USB,
 422                                                 &omap->vbus_nb);
 423                 if (ret < 0)
 424                         dev_vdbg(omap->dev, "failed to register notifier for USB\n");
 425
 426                 omap->id_nb.notifier_call = dwc3_omap_id_notifier;
 427                 ret = extcon_register_notifier(edev, EXTCON_USB_HOST,
 428                                                 &omap->id_nb);
 429                 if (ret < 0)
 430                         dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n");
 431
 432                 if (extcon_get_cable_state_(edev, EXTCON_USB) == true)
 433                         dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
 434                 if (extcon_get_cable_state_(edev, EXTCON_USB_HOST) == true)
 435                         dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
 436
 437                 omap->edev = edev;
 438         }
 439
 440         return 0;
 441 }
 442
 443 static int dwc3_omap_probe(struct platform_device *pdev)
 444 {
 445         struct device_node      *node = pdev->dev.of_node;
 446
 447         struct dwc3_omap        *omap;
 448         struct resource         *res;
 449         struct device           *dev = &pdev->dev;
 450         struct regulator        *vbus_reg = NULL;
 451
 452         int                     ret;
 453         int                     irq;
 454
 455         u32                     reg;
 456
 457         void __iomem            *base;
 458
 459         if (!node) {
 460                 dev_err(dev, "device node not found\n");
 461                 return -EINVAL;
 462         }
 463
 464         omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
 465         if (!omap)
 466                 return -ENOMEM;
 467
 468         platform_set_drvdata(pdev, omap);
 469
 470         irq = platform_get_irq(pdev, 0);
 471         if (irq < 0) {
 472                 dev_err(dev, "missing IRQ resource\n");
 473                 return -EINVAL;
 474         }
 475
 476         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 477         base = devm_ioremap_resource(dev, res);
 478         if (IS_ERR(base))
 479                 return PTR_ERR(base);
 480
 481         if (of_property_read_bool(node, "vbus-supply")) {
 482                 vbus_reg = devm_regulator_get(dev, "vbus");
 483                 if (IS_ERR(vbus_reg)) {
 484                         dev_err(dev, "vbus init failed\n");
 485                         return PTR_ERR(vbus_reg);
 486                 }
 487         }
 488
 489         omap->dev       = dev;
 490         omap->irq       = irq;
 491         omap->base      = base;
 492         omap->vbus_reg  = vbus_reg;
 493         dev->dma_mask   = &dwc3_omap_dma_mask;
 494
 495         pm_runtime_enable(dev);
 496         ret = pm_runtime_get_sync(dev);
 497         if (ret < 0) {
 498                 dev_err(dev, "get_sync failed with err %d\n", ret);
 499                 goto err0;
 500         }
 501
 502         dwc3_omap_map_offset(omap);
 503         dwc3_omap_set_utmi_mode(omap);
 504
 505         /* check the DMA Status */
 506         reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
 507         omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
 508
 509         ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0,
 510                         "dwc3-omap", omap);
 511         if (ret) {
 512                 dev_err(dev, "failed to request IRQ #%d --> %d\n",
 513                                 omap->irq, ret);
 514                 goto err1;
 515         }
 516
 517         ret = dwc3_omap_extcon_register(omap);
 518         if (ret < 0)
 519                 goto err2;
 520
 521         ret = of_platform_populate(node, NULL, NULL, dev);
 522         if (ret) {
 523                 dev_err(&pdev->dev, "failed to create dwc3 core\n");
 524                 goto err3;
 525         }
 526
 527         dwc3_omap_enable_irqs(omap);
 528
 529         return 0;
 530
 531 err3:
 532         extcon_unregister_notifier(omap->edev, EXTCON_USB, &omap->vbus_nb);
 533         extcon_unregister_notifier(omap->edev, EXTCON_USB_HOST, &omap->id_nb);
 534 err2:
 535         dwc3_omap_disable_irqs(omap);
 536
 537 err1:
 538         pm_runtime_put_sync(dev);
 539
 540 err0:
 541         pm_runtime_disable(dev);
 542
 543         return ret;
 544 }
 545
 546 static int dwc3_omap_remove(struct platform_device *pdev)
 547 {
 548         struct dwc3_omap        *omap = platform_get_drvdata(pdev);
 549
 550         extcon_unregister_notifier(omap->edev, EXTCON_USB, &omap->vbus_nb);
 551         extcon_unregister_notifier(omap->edev, EXTCON_USB_HOST, &omap->id_nb);
 552         dwc3_omap_disable_irqs(omap);
 553         of_platform_depopulate(omap->dev);
 554         pm_runtime_put_sync(&pdev->dev);
 555         pm_runtime_disable(&pdev->dev);
 556
 557         return 0;
 558 }
 559
 560 static const struct of_device_id of_dwc3_match[] = {
 561         {
 562                 .compatible =   "ti,dwc3"
 563         },
 564         {
 565                 .compatible =   "ti,am437x-dwc3"
 566         },
 567         { },
 568 };
 569 MODULE_DEVICE_TABLE(of, of_dwc3_match);
 570
 571 #ifdef CONFIG_PM_SLEEP
 572 static int dwc3_omap_suspend(struct device *dev)
 573 {
 574         struct dwc3_omap        *omap = dev_get_drvdata(dev);
 575
 576         omap->utmi_otg_ctrl = dwc3_omap_read_utmi_ctrl(omap);
 577         dwc3_omap_disable_irqs(omap);
 578
 579         return 0;
 580 }
 581
 582 static int dwc3_omap_resume(struct device *dev)
 583 {
 584         struct dwc3_omap        *omap = dev_get_drvdata(dev);
 585
 586         dwc3_omap_write_utmi_ctrl(omap, omap->utmi_otg_ctrl);
 587         dwc3_omap_enable_irqs(omap);
 588
 589         pm_runtime_disable(dev);
 590         pm_runtime_set_active(dev);
 591         pm_runtime_enable(dev);
 592
 593         return 0;
 594 }
 595
 596 static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {
 597
 598         SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
 599 };
 600
 601 #define DEV_PM_OPS      (&dwc3_omap_dev_pm_ops)
 602 #else
 603 #define DEV_PM_OPS      NULL
 604 #endif /* CONFIG_PM_SLEEP */
 605
 606 static struct platform_driver dwc3_omap_driver = {
 607         .probe          = dwc3_omap_probe,
 608         .remove         = dwc3_omap_remove,
 609         .driver         = {
 610                 .name   = "omap-dwc3",
 611                 .of_match_table = of_dwc3_match,
 612                 .pm     = DEV_PM_OPS,
 613         },
 614 };
 615
 616 module_platform_driver(dwc3_omap_driver);
 617
 618 MODULE_ALIAS("platform:omap-dwc3");
 619 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 620 MODULE_LICENSE("GPL v2");
 621 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");