MIPS: Allow kernel use of LL/SC to be separate from the presence of LL/SC.

[karo-tx-linux.git] / arch / mips / include / asm / atomic.h

diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index eb7f01cfd1acb906e2dd1a4ffd02bbd4893bf9f8..dd75d673447e37147c438991829b70c15c7c721b 100644 (file)
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -49,7 +49,7 @@
  */
 static __inline__ void atomic_add(int i, atomic_t * v)
 {
-       if (cpu_has_llsc && R10000_LLSC_WAR) {
+       if (kernel_uses_llsc && R10000_LLSC_WAR) {
                int temp;
 
                __asm__ __volatile__(
@@ -61,7 +61,7 @@ static __inline__ void atomic_add(int i, atomic_t * v)
                "       .set    mips0                                   \n"
                : "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter));
-       } else if (cpu_has_llsc) {
+       } else if (kernel_uses_llsc) {
                int temp;
 
                __asm__ __volatile__(
@@ -94,7 +94,7 @@ static __inline__ void atomic_add(int i, atomic_t * v)
  */
 static __inline__ void atomic_sub(int i, atomic_t * v)
 {
-       if (cpu_has_llsc && R10000_LLSC_WAR) {
+       if (kernel_uses_llsc && R10000_LLSC_WAR) {
                int temp;
 
                __asm__ __volatile__(
@@ -106,7 +106,7 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
                "       .set    mips0                                   \n"
                : "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter));
-       } else if (cpu_has_llsc) {
+       } else if (kernel_uses_llsc) {
                int temp;
 
                __asm__ __volatile__(
@@ -139,7 +139,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
 
        smp_llsc_mb();
 
-       if (cpu_has_llsc && R10000_LLSC_WAR) {
+       if (kernel_uses_llsc && R10000_LLSC_WAR) {
                int temp;
 
                __asm__ __volatile__(
@@ -153,7 +153,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter)
                : "memory");
-       } else if (cpu_has_llsc) {
+       } else if (kernel_uses_llsc) {
                int temp;
 
                __asm__ __volatile__(
@@ -191,7 +191,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
 
        smp_llsc_mb();
 
-       if (cpu_has_llsc && R10000_LLSC_WAR) {
+       if (kernel_uses_llsc && R10000_LLSC_WAR) {
                int temp;
 
                __asm__ __volatile__(
@@ -205,7 +205,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter)
                : "memory");
-       } else if (cpu_has_llsc) {
+       } else if (kernel_uses_llsc) {
                int temp;
 
                __asm__ __volatile__(
@@ -251,7 +251,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
 
        smp_llsc_mb();
 
-       if (cpu_has_llsc && R10000_LLSC_WAR) {
+       if (kernel_uses_llsc && R10000_LLSC_WAR) {
                int temp;
 
                __asm__ __volatile__(
@@ -269,7 +269,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter)
                : "memory");
-       } else if (cpu_has_llsc) {
+       } else if (kernel_uses_llsc) {
                int temp;
 
                __asm__ __volatile__(
@@ -428,7 +428,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
  */
 static __inline__ void atomic64_add(long i, atomic64_t * v)
 {
-       if (cpu_has_llsc && R10000_LLSC_WAR) {
+       if (kernel_uses_llsc && R10000_LLSC_WAR) {
                long temp;
 
                __asm__ __volatile__(
@@ -440,7 +440,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
                "       .set    mips0                                   \n"
                : "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter));
-       } else if (cpu_has_llsc) {
+       } else if (kernel_uses_llsc) {
                long temp;
 
                __asm__ __volatile__(
@@ -473,7 +473,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
  */
 static __inline__ void atomic64_sub(long i, atomic64_t * v)
 {
-       if (cpu_has_llsc && R10000_LLSC_WAR) {
+       if (kernel_uses_llsc && R10000_LLSC_WAR) {
                long temp;
 
                __asm__ __volatile__(
@@ -485,7 +485,7 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
                "       .set    mips0                                   \n"
                : "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter));
-       } else if (cpu_has_llsc) {
+       } else if (kernel_uses_llsc) {
                long temp;
 
                __asm__ __volatile__(
@@ -518,7 +518,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
 
        smp_llsc_mb();
 
-       if (cpu_has_llsc && R10000_LLSC_WAR) {
+       if (kernel_uses_llsc && R10000_LLSC_WAR) {
                long temp;
 
                __asm__ __volatile__(
@@ -532,7 +532,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter)
                : "memory");
-       } else if (cpu_has_llsc) {
+       } else if (kernel_uses_llsc) {
                long temp;
 
                __asm__ __volatile__(
@@ -570,7 +570,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
 
        smp_llsc_mb();
 
-       if (cpu_has_llsc && R10000_LLSC_WAR) {
+       if (kernel_uses_llsc && R10000_LLSC_WAR) {
                long temp;
 
                __asm__ __volatile__(
@@ -584,7 +584,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter)
                : "memory");
-       } else if (cpu_has_llsc) {
+       } else if (kernel_uses_llsc) {
                long temp;
 
                __asm__ __volatile__(
@@ -630,7 +630,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
 
        smp_llsc_mb();
 
-       if (cpu_has_llsc && R10000_LLSC_WAR) {
+       if (kernel_uses_llsc && R10000_LLSC_WAR) {
                long temp;
 
                __asm__ __volatile__(
@@ -648,7 +648,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter)
                : "memory");
-       } else if (cpu_has_llsc) {
+       } else if (kernel_uses_llsc) {
                long temp;
 
                __asm__ __volatile__(