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clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates
authorEmilio López <emilio@elopez.com.ar>
Wed, 27 Mar 2013 21:20:37 +0000 (18:20 -0300)
committerMike Turquette <mturquette@linaro.org>
Thu, 4 Apr 2013 20:51:35 +0000 (13:51 -0700)
commit13569a709ad12aef4d9c2b352c92e95ab7dd201f
tree82c1411a3a64b0d1988c17eb93443a8864765f48tree | snapshot
parent056b205316cc3dcf8a67cf813a26ff8a72bf3cb9commit | diff
clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates

This patchset adds DT support for all the AXI, AHB, APB0 and APB1
gates present on sunxi SoCs.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Documentation/devicetree/bindings/clock/sunxi.txt diff | blob | history
drivers/clk/sunxi/clk-sunxi.c diff | blob | history
Linux kernel for KaRo TX COM modules