Revert "PCI: designware: Program ATU with untranslated address"

Revert f4c55c5a3f7f ("PCI: designware: Program ATU with untranslated
address").

Note that dra7xx_pcie_host_init() now modifies pp->io_base, but we still
need the original value for dw_pcie_setup() in the path below, so this adds
a new io_base_tmp member.  It will be removed later when dw_pcie_setup() is
removed.

  dra7xx_add_pcie_port
    dw_pcie_host_init
      pp->io_base = range.cpu_addr
      pp->io_base_tmp = range.cpu_addr            # <-- added
      pp->ops->host_init
      dra7xx_pcie_host_init                       # ops->host_init
	pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR     # <-- modified
      pci_common_init_dev(..., &dw_pci)
	pcibios_init_hw
	  hw->setup
	  dw_pcie_setup                           # hw_pci.setup
	    pci_ioremap_io(..., pp->io_base_tmp)  # <-- original addr required

[bhelgaas: changelog]
Tested-by: James Morse <james.morse@arm.com>
Tested-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Tested-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>

diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
index 0b4847a9fbfd5cfefb0952e9de0ebb2e62eb2e72..8c3688046c02ff40446833f1a8f3eecebfd9713f 100644 (file)
--- a/drivers/pci/host/pci-dra7xx.c
+++ b/drivers/pci/host/pci-dra7xx.c
@@ -153,10 +153,10 @@ static void dra7xx_pcie_host_init(struct pcie_port *pp)
 {
        dw_pcie_setup_rc(pp);
 
-       pp->io_mod_base &= DRA7XX_CPU_TO_BUS_ADDR;
-       pp->mem_mod_base &= DRA7XX_CPU_TO_BUS_ADDR;
-       pp->cfg0_mod_base &= DRA7XX_CPU_TO_BUS_ADDR;
-       pp->cfg1_mod_base &= DRA7XX_CPU_TO_BUS_ADDR;
+       pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR;
+       pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR;
+       pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR;
+       pp->cfg1_base &= DRA7XX_CPU_TO_BUS_ADDR;
 
        dra7xx_pcie_establish_link(pp);
        if (IS_ENABLED(CONFIG_PCI_MSI))

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index e444acb172b60f5103f87e9f9029988a066cc334..2a43f7388dddbe6f2ce7862b07d61da8a31ab5ac 100644 (file)
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -417,11 +417,8 @@ int dw_pcie_host_init(struct pcie_port *pp)
        struct of_pci_range range;
        struct of_pci_range_parser parser;
        struct resource *cfg_res;
-       u32 val, ns;
-       const __be32 *addrp;
-       int i, index, ret;
-
-       ns = of_n_size_cells(np);
+       u32 val;
+       int i, ret;
 
        cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
        if (cfg_res) {
@@ -429,12 +426,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
                pp->cfg1_size = resource_size(cfg_res)/2;
                pp->cfg0_base = cfg_res->start;
                pp->cfg1_base = cfg_res->start + pp->cfg0_size;
-
-               /* Find the untranslated configuration space address */
-               index = of_property_match_string(np, "reg-names", "config");
-               addrp = of_get_address(np, index, NULL, NULL);
-               pp->cfg0_mod_base = of_read_number(addrp, ns);
-               pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size;
        } else if (!pp->va_cfg0_base) {
                dev_err(pp->dev, "missing *config* reg space\n");
        }
@@ -461,18 +452,13 @@ int dw_pcie_host_init(struct pcie_port *pp)
                        pp->io_size = resource_size(&pp->io);
                        pp->io_bus_addr = range.pci_addr;
                        pp->io_base = range.cpu_addr;
-
-                       /* Find the untranslated IO space address */
-                       pp->io_mod_base = range.cpu_addr;
+                       pp->io_base_tmp = range.cpu_addr;
                }
                if (restype == IORESOURCE_MEM) {
                        of_pci_range_to_resource(&range, np, &pp->mem);
                        pp->mem.name = "MEM";
                        pp->mem_size = resource_size(&pp->mem);
                        pp->mem_bus_addr = range.pci_addr;
-
-                       /* Find the untranslated MEM space address */
-                       pp->mem_mod_base = range.cpu_addr;
                }
                if (restype == 0) {
                        of_pci_range_to_resource(&range, np, &pp->cfg);
@@ -480,11 +466,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
                        pp->cfg1_size = resource_size(&pp->cfg)/2;
                        pp->cfg0_base = pp->cfg.start;
                        pp->cfg1_base = pp->cfg.start + pp->cfg0_size;
-
-                       /* Find the untranslated configuration space address */
-                       pp->cfg0_mod_base = range.cpu_addr;
-                       pp->cfg1_mod_base = pp->cfg0_mod_base +
-                                           pp->cfg0_size;
                }
        }
 
@@ -555,7 +536,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
 
        if (!pp->ops->rd_other_conf)
                dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
-                                         PCIE_ATU_TYPE_MEM, pp->mem_mod_base,
+                                         PCIE_ATU_TYPE_MEM, pp->mem_base,
                                          pp->mem_bus_addr, pp->mem_size);
 
        dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
@@ -592,12 +573,12 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
 
        if (bus->parent->number == pp->root_bus_nr) {
                type = PCIE_ATU_TYPE_CFG0;
-               cpu_addr = pp->cfg0_mod_base;
+               cpu_addr = pp->cfg0_base;
                cfg_size = pp->cfg0_size;
                va_cfg_base = pp->va_cfg0_base;
        } else {
                type = PCIE_ATU_TYPE_CFG1;
-               cpu_addr = pp->cfg1_mod_base;
+               cpu_addr = pp->cfg1_base;
                cfg_size = pp->cfg1_size;
                va_cfg_base = pp->va_cfg1_base;
        }
@@ -607,7 +588,7 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
                                  busdev, cfg_size);
        ret = dw_pcie_cfg_read(va_cfg_base + where, size, val);
        dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
-                                 PCIE_ATU_TYPE_IO, pp->io_mod_base,
+                                 PCIE_ATU_TYPE_IO, pp->io_base,
                                  pp->io_bus_addr, pp->io_size);
 
        return ret;
@@ -626,12 +607,12 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
 
        if (bus->parent->number == pp->root_bus_nr) {
                type = PCIE_ATU_TYPE_CFG0;
-               cpu_addr = pp->cfg0_mod_base;
+               cpu_addr = pp->cfg0_base;
                cfg_size = pp->cfg0_size;
                va_cfg_base = pp->va_cfg0_base;
        } else {
                type = PCIE_ATU_TYPE_CFG1;
-               cpu_addr = pp->cfg1_mod_base;
+               cpu_addr = pp->cfg1_base;
                cfg_size = pp->cfg1_size;
                va_cfg_base = pp->va_cfg1_base;
        }
@@ -641,7 +622,7 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
                                  busdev, cfg_size);
        ret = dw_pcie_cfg_write(va_cfg_base + where, size, val);
        dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
-                                 PCIE_ATU_TYPE_IO, pp->io_mod_base,
+                                 PCIE_ATU_TYPE_IO, pp->io_base,
                                  pp->io_bus_addr, pp->io_size);
 
        return ret;
@@ -729,7 +710,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
 
        if (global_io_offset < SZ_1M && pp->io_size > 0) {
                sys->io_offset = global_io_offset - pp->io_bus_addr;
-               pci_ioremap_io(global_io_offset, pp->io_base);
+               pci_ioremap_io(global_io_offset, pp->io_base_tmp);
                global_io_offset += SZ_64K;
                pci_add_resource_offset(&sys->resources, &pp->io,
                                        sys->io_offset);

diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index e7b3279c3ff09ab5665fd251c4fdc695b4887eae..f21dc287adf196102429f5be6a99f1ee6e60991e 100644 (file)
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -27,19 +27,16 @@ struct pcie_port {
        u8                      root_bus_nr;
        void __iomem            *dbi_base;
        u64                     cfg0_base;
-       u64                     cfg0_mod_base;
        void __iomem            *va_cfg0_base;
        u32                     cfg0_size;
        u64                     cfg1_base;
-       u64                     cfg1_mod_base;
        void __iomem            *va_cfg1_base;
        u32                     cfg1_size;
        u64                     io_base;
-       u64                     io_mod_base;
+       u64                     io_base_tmp;
        phys_addr_t             io_bus_addr;
        u32                     io_size;
        u64                     mem_base;
-       u64                     mem_mod_base;
        phys_addr_t             mem_bus_addr;
        u32                     mem_size;
        struct resource         cfg;